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ac,radv: implement the cs_regalloc_hang HW bug workaround

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Might fix spurious failures on GFX6 and some GFX7 chips.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11675>
This commit is contained in:
Samuel Pitoiset
2021-07-01 13:32:05 +02:00
committed by Marge Bot
parent c905e74842
commit 29f264f258
4 changed files with 25 additions and 9 deletions
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src/amd/vulkan/radv_cmd_buffer.c
+9
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@@ -6134,6 +6134,12 @@ radv_dispatch(struct radv_cmd_buffer *cmd_buffer, const struct radv_dispatch_inf
{
bool has_prefetch = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
bool pipeline_is_dirty = pipeline && pipeline != cmd_buffer->state.emitted_compute_pipeline;
bool cs_regalloc_hang = cmd_buffer->device->physical_device->rad_info.has_cs_regalloc_hang_bug &&
info->blocks[0] * info->blocks[1] * info->blocks[2] > 256;
if (cs_regalloc_hang)
cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
if (cmd_buffer->state.flush_bits &
(RADV_CMD_FLAG_FLUSH_AND_INV_CB | RADV_CMD_FLAG_FLUSH_AND_INV_DB |
@@ -6190,6 +6196,9 @@ radv_dispatch(struct radv_cmd_buffer *cmd_buffer, const struct radv_dispatch_inf
: VK_PIPELINE_BIND_POINT_COMPUTE);
}
if (cs_regalloc_hang)
cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
}