diff --git a/src/freedreno/common/freedreno_dev_info.h b/src/freedreno/common/freedreno_dev_info.h
index 83417e41e24..7d9631d9b62 100644
--- a/src/freedreno/common/freedreno_dev_info.h
+++ b/src/freedreno/common/freedreno_dev_info.h
@@ -175,6 +175,14 @@ struct fd_dev_info {
       /* See ir3_compiler::has_scalar_alu. */
       bool has_scalar_alu;
 
+      /* Whether writing to UBWC attachment and reading the same image as input
+       * attachment or as a texture reads correct values from the image.
+       * If this is false, we may read stale values from the flag buffer,
+       * thus reading incorrect values from the image.
+       * Happens with VK_EXT_attachment_feedback_loop_layout.
+       */
+      bool has_coherent_ubwc_flag_caches;
+
       struct {
          uint32_t PC_POWER_CNTL;
          uint32_t TPL1_DBG_ECO_CNTL;
diff --git a/src/freedreno/common/freedreno_devices.py b/src/freedreno/common/freedreno_devices.py
index 5c8a81126d9..2f6aa02573a 100644
--- a/src/freedreno/common/freedreno_devices.py
+++ b/src/freedreno/common/freedreno_devices.py
@@ -793,6 +793,7 @@ a7xx_base = A6XXProps(
         line_width_min = 1.0,
         line_width_max = 127.5,
         has_scalar_alu = True,
+        has_coherent_ubwc_flag_caches = True,
     )
 
 a7xx_725 = A7XXProps(
diff --git a/src/freedreno/vulkan/tu_pipeline.cc b/src/freedreno/vulkan/tu_pipeline.cc
index f141e25d3e7..477532d198b 100644
--- a/src/freedreno/vulkan/tu_pipeline.cc
+++ b/src/freedreno/vulkan/tu_pipeline.cc
@@ -3634,10 +3634,13 @@ tu_pipeline_builder_parse_rasterization_order(
        * both input and color attachments from one fragment to the next,
        * in rasterization order, without explicit synchronization.
        */
-      sysmem_prim_mode = FLUSH_PER_OVERLAP_AND_OVERWRITE;
+      if (builder->device->physical_device->info->a6xx.has_coherent_ubwc_flag_caches)
+         sysmem_prim_mode = FLUSH_PER_OVERLAP;
+      else
+         sysmem_prim_mode = FLUSH_PER_OVERLAP_AND_OVERWRITE;
       gmem_prim_mode = FLUSH_PER_OVERLAP;
       pipeline->prim_order.sysmem_single_prim_mode = true;
-   } else {
+   } else if (!builder->device->physical_device->info->a6xx.has_coherent_ubwc_flag_caches) {
       /* If there is a feedback loop, then the shader can read the previous value
        * of a pixel being written out. It can also write some components and then
        * read different components without a barrier in between. This is a