From 278d12f991b986eaf50d5959ea4adfcbe715fe33 Mon Sep 17 00:00:00 2001 From: Jason Ekstrand Date: Fri, 3 Dec 2021 22:20:30 -0600 Subject: [PATCH] intel/fs,vec4: Drop prog_data binding tables Reviewed-by: Caio Oliveira Part-of: --- src/intel/compiler/brw_compiler.h | 17 ------- src/intel/compiler/brw_fs.cpp | 22 +-------- src/intel/compiler/brw_fs_generator.cpp | 12 +---- src/intel/compiler/brw_fs_nir.cpp | 56 ++++------------------- src/intel/compiler/brw_vec4_generator.cpp | 9 +--- src/intel/compiler/brw_vec4_nir.cpp | 24 +++------- 6 files changed, 18 insertions(+), 122 deletions(-) diff --git a/src/intel/compiler/brw_compiler.h b/src/intel/compiler/brw_compiler.h index ae722f5dda0..857e75f5eaa 100644 --- a/src/intel/compiler/brw_compiler.h +++ b/src/intel/compiler/brw_compiler.h @@ -734,23 +734,6 @@ struct brw_shader_reloc_value { }; struct brw_stage_prog_data { - struct { - /** size of our binding table. */ - uint32_t size_bytes; - - /** @{ - * surface indices for the various groups of surfaces - */ - uint32_t pull_constants_start; - uint32_t texture_start; - uint32_t gather_texture_start; - uint32_t ubo_start; - uint32_t ssbo_start; - uint32_t image_start; - uint32_t plane_start[3]; - /** @} */ - } binding_table; - struct brw_ubo_range ubo_ranges[4]; GLuint nr_params; /**< number of float params/constants */ diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp index 8ed6221419b..b5ab29095d3 100644 --- a/src/intel/compiler/brw_fs.cpp +++ b/src/intel/compiler/brw_fs.cpp @@ -2374,7 +2374,7 @@ fs_visitor::get_pull_locs(const fs_reg &src, if (src.offset / 32 < range->length) return false; - *out_surf_index = prog_data->binding_table.ubo_start + range->block; + *out_surf_index = range->block; *out_pull_index = (32 * range->start + src.offset) / 4; prog_data->has_ubo_pull = true; @@ -4897,7 +4897,6 @@ lower_sampler_logical_send_gfx7(const fs_builder &bld, fs_inst *inst, opcode op, brw_reg_type_from_bit_size(payload_type_bit_size, BRW_REGISTER_TYPE_UD); const enum brw_reg_type payload_signed_type = brw_reg_type_from_bit_size(payload_type_bit_size, BRW_REGISTER_TYPE_D); - const brw_stage_prog_data *prog_data = bld.shader->stage_prog_data; unsigned reg_width = bld.dispatch_width() / 8; unsigned header_size = 0, length = 0; fs_reg sources[MAX_SAMPLER_MESSAGE_SIZE]; @@ -5182,25 +5181,10 @@ lower_sampler_logical_send_gfx7(const fs_builder &bld, fs_inst *inst, opcode op, const unsigned msg_type = sampler_msg_type(devinfo, op, inst->shadow_compare); - uint32_t base_binding_table_index; - switch (op) { - case SHADER_OPCODE_TG4: - case SHADER_OPCODE_TG4_OFFSET: - base_binding_table_index = prog_data->binding_table.gather_texture_start; - break; - case SHADER_OPCODE_IMAGE_SIZE_LOGICAL: - base_binding_table_index = prog_data->binding_table.image_start; - break; - default: - base_binding_table_index = prog_data->binding_table.texture_start; - break; - } - inst->sfid = BRW_SFID_SAMPLER; if (surface.file == IMM && (sampler.file == IMM || sampler_handle.file != BAD_FILE)) { - inst->desc = brw_sampler_desc(devinfo, - surface.ud + base_binding_table_index, + inst->desc = brw_sampler_desc(devinfo, surface.ud, sampler.file == IMM ? sampler.ud % 16 : 0, msg_type, simd_mode, @@ -5256,8 +5240,6 @@ lower_sampler_logical_send_gfx7(const fs_builder &bld, fs_inst *inst, opcode op, ubld.OR(desc, desc, surface); } } - if (base_binding_table_index) - ubld.ADD(desc, desc, brw_imm_ud(base_binding_table_index)); ubld.AND(desc, desc, brw_imm_ud(0xfff)); inst->src[0] = component(desc, 0); diff --git a/src/intel/compiler/brw_fs_generator.cpp b/src/intel/compiler/brw_fs_generator.cpp index 74c19683ea9..b97aed29f13 100644 --- a/src/intel/compiler/brw_fs_generator.cpp +++ b/src/intel/compiler/brw_fs_generator.cpp @@ -1288,16 +1288,6 @@ fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, } } - uint32_t base_binding_table_index; - switch (inst->opcode) { - case SHADER_OPCODE_TG4: - base_binding_table_index = prog_data->binding_table.gather_texture_start; - break; - default: - base_binding_table_index = prog_data->binding_table.texture_start; - break; - } - assert(surface_index.file == BRW_IMMEDIATE_VALUE); assert(sampler_index.file == BRW_IMMEDIATE_VALUE); @@ -1305,7 +1295,7 @@ fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, retype(dst, BRW_REGISTER_TYPE_UW), inst->base_mrf, src, - surface_index.ud + base_binding_table_index, + surface_index.ud, sampler_index.ud % 16, msg_type, inst->size_written / REG_SIZE, diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index 671dfa8e2ce..0301800cb71 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++ b/src/intel/compiler/brw_fs_nir.cpp @@ -3315,15 +3315,6 @@ fs_visitor::emit_non_coherent_fb_read(const fs_builder &bld, const fs_reg &dst, const brw_wm_prog_key *wm_key = reinterpret_cast(key); assert(!wm_key->coherent_fb_fetch); - const struct brw_wm_prog_data *wm_prog_data = - brw_wm_prog_data(stage_prog_data); - - /* Calculate the surface index relative to the start of the texture binding - * table block, since that's what the texturing messages expect. - */ - const unsigned surface = target + - wm_prog_data->binding_table.render_target_read_start - - wm_prog_data->base.binding_table.texture_start; /* Calculate the fragment coordinates. */ const fs_reg coords = bld.vgrf(BRW_REGISTER_TYPE_UD, 3); @@ -3342,7 +3333,7 @@ fs_visitor::emit_non_coherent_fb_read(const fs_builder &bld, const fs_reg &dst, const fs_reg sample = nir_system_values[SYSTEM_VALUE_SAMPLE_ID]; const fs_reg mcs = wm_key->multisample_fbo ? - emit_mcs_fetch(coords, 3, brw_imm_ud(surface), fs_reg()) : fs_reg(); + emit_mcs_fetch(coords, 3, brw_imm_ud(target), fs_reg()) : fs_reg(); /* Use either a normal or a CMS texel fetch message depending on whether * the framebuffer is single or multisample. On SKL+ use the wide CMS @@ -3373,7 +3364,7 @@ fs_visitor::emit_non_coherent_fb_read(const fs_builder &bld, const fs_reg &dst, srcs[TEX_LOGICAL_SRC_LOD] = brw_imm_ud(0); srcs[TEX_LOGICAL_SRC_SAMPLE_INDEX] = sample; srcs[TEX_LOGICAL_SRC_MCS] = mcs; - srcs[TEX_LOGICAL_SRC_SURFACE] = brw_imm_ud(surface); + srcs[TEX_LOGICAL_SRC_SURFACE] = brw_imm_ud(target); srcs[TEX_LOGICAL_SRC_SAMPLER] = brw_imm_ud(0); srcs[TEX_LOGICAL_SRC_COORD_COMPONENTS] = brw_imm_ud(3); srcs[TEX_LOGICAL_SRC_GRAD_COMPONENTS] = brw_imm_ud(0); @@ -3887,13 +3878,11 @@ fs_visitor::nir_emit_cs_intrinsic(const fs_builder &bld, case nir_intrinsic_load_num_workgroups: { assert(nir_dest_bit_size(instr->dest) == 32); - const unsigned surface = - cs_prog_data->binding_table.work_groups_start; cs_prog_data->uses_num_work_groups = true; fs_reg srcs[SURFACE_LOGICAL_NUM_SRCS]; - srcs[SURFACE_LOGICAL_SRC_SURFACE] = brw_imm_ud(surface); + srcs[SURFACE_LOGICAL_SRC_SURFACE] = brw_imm_ud(0); srcs[SURFACE_LOGICAL_SRC_IMM_DIMS] = brw_imm_ud(1); srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = brw_imm_ud(3); /* num components */ srcs[SURFACE_LOGICAL_SRC_ADDRESS] = brw_imm_ud(0); @@ -4140,17 +4129,6 @@ fs_visitor::get_nir_image_intrinsic_image(const brw::fs_builder &bld, fs_reg image = retype(get_nir_src_imm(instr->src[0]), BRW_REGISTER_TYPE_UD); fs_reg surf_index = image; - if (stage_prog_data->binding_table.image_start > 0) { - if (image.file == BRW_IMMEDIATE_VALUE) { - surf_index = - brw_imm_ud(image.d + stage_prog_data->binding_table.image_start); - } else { - surf_index = vgrf(glsl_type::uint_type); - bld.ADD(surf_index, image, - brw_imm_d(stage_prog_data->binding_table.image_start)); - } - } - return bld.emit_uniformize(surf_index); } @@ -4165,14 +4143,9 @@ fs_visitor::get_nir_ssbo_intrinsic_index(const brw::fs_builder &bld, const unsigned src = is_store ? 1 : 0; if (nir_src_is_const(instr->src[src])) { - unsigned index = stage_prog_data->binding_table.ssbo_start + - nir_src_as_uint(instr->src[src]); - return brw_imm_ud(index); + return brw_imm_ud(nir_src_as_uint(instr->src[src])); } else { - fs_reg surf_index = vgrf(glsl_type::uint_type); - bld.ADD(surf_index, get_nir_src(instr->src[src]), - brw_imm_ud(stage_prog_data->binding_table.ssbo_start)); - return bld.emit_uniformize(surf_index); + return bld.emit_uniformize(get_nir_src(instr->src[src])); } } @@ -4731,8 +4704,7 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr case nir_intrinsic_load_ubo: { fs_reg surf_index; if (nir_src_is_const(instr->src[0])) { - const unsigned index = stage_prog_data->binding_table.ubo_start + - nir_src_as_uint(instr->src[0]); + const unsigned index = nir_src_as_uint(instr->src[0]); surf_index = brw_imm_ud(index); } else { /* The block index is not a constant. Evaluate the index expression @@ -4740,8 +4712,7 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr * from any live channel. */ surf_index = vgrf(glsl_type::uint_type); - bld.ADD(surf_index, get_nir_src(instr->src[0]), - brw_imm_ud(stage_prog_data->binding_table.ubo_start)); + bld.MOV(surf_index, get_nir_src(instr->src[0])); surf_index = bld.emit_uniformize(surf_index); } @@ -5090,7 +5061,7 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr /* Set LOD = 0 */ ubld.MOV(src_payload, brw_imm_d(0)); - const unsigned index = prog_data->binding_table.ssbo_start + ssbo_index; + const unsigned index = ssbo_index; fs_inst *inst = ubld.emit(SHADER_OPCODE_GET_BUFFER_SIZE, ret_payload, src_payload, brw_imm_ud(index)); inst->header_size = 0; @@ -6189,17 +6160,6 @@ fs_visitor::nir_emit_texture(const fs_builder &bld, nir_tex_instr *instr) srcs[TEX_LOGICAL_SRC_MCS] = retype(src, BRW_REGISTER_TYPE_D); break; - case nir_tex_src_plane: { - const uint32_t plane = nir_src_as_uint(instr->src[i].src); - const uint32_t texture_index = - instr->texture_index + - stage_prog_data->binding_table.plane_start[plane] - - stage_prog_data->binding_table.texture_start; - - srcs[TEX_LOGICAL_SRC_SURFACE] = brw_imm_ud(texture_index); - break; - } - default: unreachable("unknown texture source"); } diff --git a/src/intel/compiler/brw_vec4_generator.cpp b/src/intel/compiler/brw_vec4_generator.cpp index 588372864e8..bf548265099 100644 --- a/src/intel/compiler/brw_vec4_generator.cpp +++ b/src/intel/compiler/brw_vec4_generator.cpp @@ -271,11 +271,6 @@ generate_tex(struct brw_codegen *p, if (inst->opcode == SHADER_OPCODE_TXS) return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32; - uint32_t base_binding_table_index = (inst->opcode == SHADER_OPCODE_TG4 || - inst->opcode == SHADER_OPCODE_TG4_OFFSET) - ? prog_data->base.binding_table.gather_texture_start - : prog_data->base.binding_table.texture_start; - if (surface_index.file == BRW_IMMEDIATE_VALUE && sampler_index.file == BRW_IMMEDIATE_VALUE) { uint32_t surface = surface_index.ud; @@ -285,7 +280,7 @@ generate_tex(struct brw_codegen *p, dst, inst->base_mrf, src, - surface + base_binding_table_index, + surface, sampler % 16, msg_type, 1, /* response length */ @@ -314,8 +309,6 @@ generate_tex(struct brw_codegen *p, brw_OR(p, addr, addr, surface_reg); } } - if (base_binding_table_index) - brw_ADD(p, addr, addr, brw_imm_ud(base_binding_table_index)); brw_AND(p, addr, addr, brw_imm_ud(0xfff)); brw_pop_insn_state(p); diff --git a/src/intel/compiler/brw_vec4_nir.cpp b/src/intel/compiler/brw_vec4_nir.cpp index 4600368194d..7dc56f6e657 100644 --- a/src/intel/compiler/brw_vec4_nir.cpp +++ b/src/intel/compiler/brw_vec4_nir.cpp @@ -380,19 +380,11 @@ vec4_visitor::get_nir_ssbo_intrinsic_index(nir_intrinsic_instr *instr) /* SSBO stores are weird in that their index is in src[1] */ const unsigned src = instr->intrinsic == nir_intrinsic_store_ssbo ? 1 : 0; - src_reg surf_index; if (nir_src_is_const(instr->src[src])) { - unsigned index = prog_data->base.binding_table.ssbo_start + - nir_src_as_uint(instr->src[src]); - surf_index = brw_imm_ud(index); + return brw_imm_ud(nir_src_as_uint(instr->src[src])); } else { - surf_index = src_reg(this, glsl_type::uint_type); - emit(ADD(dst_reg(surf_index), get_nir_src(instr->src[src], 1), - brw_imm_ud(prog_data->base.binding_table.ssbo_start))); - surf_index = emit_uniformize(surf_index); + return emit_uniformize(get_nir_src(instr->src[src])); } - - return surf_index; } void @@ -439,15 +431,13 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr) unsigned ssbo_index = nir_src_is_const(instr->src[0]) ? nir_src_as_uint(instr->src[0]) : 0; - const unsigned index = - prog_data->base.binding_table.ssbo_start + ssbo_index; dst_reg result_dst = get_nir_dest(instr->dest); vec4_instruction *inst = new(mem_ctx) vec4_instruction(SHADER_OPCODE_GET_BUFFER_SIZE, result_dst); inst->base_mrf = 2; inst->mlen = 1; /* always at least one */ - inst->src[1] = brw_imm_ud(index); + inst->src[1] = brw_imm_ud(ssbo_index); /* MRF for the first parameter */ src_reg lod = brw_imm_d(0); @@ -630,8 +620,7 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr) /* The block index is a constant, so just emit the binding table entry * as an immediate. */ - const unsigned index = prog_data->base.binding_table.ubo_start + - nir_src_as_uint(instr->src[0]); + const unsigned index = nir_src_as_uint(instr->src[0]); surf_index = brw_imm_ud(index); } else { /* The block index is not a constant. Evaluate the index expression @@ -639,9 +628,8 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr) * from any live channel. */ surf_index = src_reg(this, glsl_type::uint_type); - emit(ADD(dst_reg(surf_index), get_nir_src(instr->src[0], nir_type_int32, - instr->num_components), - brw_imm_ud(prog_data->base.binding_table.ubo_start))); + emit(MOV(dst_reg(surf_index), get_nir_src(instr->src[0], nir_type_int32, + instr->num_components))); surf_index = emit_uniformize(surf_index); }