AlexIndustrial/mesa
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

intel: Drop Wa_1409226450 (stall before instruction cache invalidation)

Browse Source 
Production Tigerlake and DG1 hardware shouldn't need this workaround.
It was only needed on the very first steppings which never went public.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16575>
This commit is contained in:
Kenneth Graunke
2022-05-17 16:37:35 -07:00
committed by Marge Bot
parent 7938ce4af3
commit 27314718a3
2 changed files with 0 additions and 18 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/intel/vulkan/genX_cmd_buffer.c
-6
View File
@@ -2132,12 +2132,6 @@ genX(emit_apply_pipe_flushes)(struct anv_batch *batch,
bits &= ~ANV_PIPE_NEEDS_END_OF_PIPE_SYNC_BIT;
}
/* Wa_1409226450, Wait for EU to be idle before pipe control which
* invalidates the instruction cache
*/
if (GFX_VER == 12 && (bits & ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT))
bits |= ANV_PIPE_CS_STALL_BIT | ANV_PIPE_STALL_AT_SCOREBOARD_BIT;
/* Project: SKL / Argument: LRI Post Sync Operation [23]
*
* "PIPECONTROL command with “Command Streamer Stall Enable” must be