From 257e1515e3f519e726fd2c658fa9a27a376f06e4 Mon Sep 17 00:00:00 2001 From: Paulo Zanoni Date: Mon, 28 Jul 2025 22:43:17 -0700 Subject: [PATCH] brw: null-tile sends don't need to skip L3 on Xe2 and newer Despite the information in "Overview of Memory Access" (57046), the L3 seems to be smarter on Xe2+. See 4aa3b2d3ad73 ("anv: LNL+ doesn't need the special flush for sparse"). The behavior is the same both with vm_bind and TR-TT. v2: Add some comments (Caio). Reviewed-by: Caio Oliveira Signed-off-by: Paulo Zanoni Part-of: --- src/intel/compiler/brw_lower_logical_sends.cpp | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/src/intel/compiler/brw_lower_logical_sends.cpp b/src/intel/compiler/brw_lower_logical_sends.cpp index 1d85fbf433f..963f0230fa7 100644 --- a/src/intel/compiler/brw_lower_logical_sends.cpp +++ b/src/intel/compiler/brw_lower_logical_sends.cpp @@ -1589,9 +1589,15 @@ lower_lsc_memory_logical_send(const brw_builder &bld, brw_inst *inst) unsigned cache_mode = lsc_opcode_is_atomic(op) ? LSC_CACHE(devinfo, STORE, L1UC_L3WB) : volatile_access ? - (lsc_opcode_is_store(op) ? - LSC_CACHE(devinfo, STORE, L1UC_L3UC) : - LSC_CACHE(devinfo, LOAD, L1UC_L3UC)) : + (devinfo->ver >= 20 ? + /* Xe2 has a better L3 that can deal with null tiles.*/ + (lsc_opcode_is_store(op) ? + LSC_CACHE(devinfo, STORE, L1UC_L3WB) : + LSC_CACHE(devinfo, LOAD, L1UC_L3C)) : + /* On older platforms, all caches have to be bypassed. */ + (lsc_opcode_is_store(op) ? + LSC_CACHE(devinfo, STORE, L1UC_L3UC) : + LSC_CACHE(devinfo, LOAD, L1UC_L3UC))) : lsc_opcode_is_store(op) ? LSC_CACHE(devinfo, STORE, L1STATE_L3MOCS) : LSC_CACHE(devinfo, LOAD, L1STATE_L3MOCS);