From 230743da2e9bfb3536b9e76a5bd17b4121ff5b37 Mon Sep 17 00:00:00 2001 From: Georg Lehmann Date: Mon, 4 Mar 2024 15:04:47 +0100 Subject: [PATCH] nir: remove rotate scope MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit All other subgroup operations do not have a scope in NIR, so for consistency rotate shouldn't have one either. Reviewed-by: Daniel Schürmann Part-of: --- .../compiler/aco_instruction_selection.cpp | 1 - src/compiler/nir/nir_intrinsics.py | 2 +- src/compiler/nir/nir_lower_subgroups.c | 20 +++++++++---------- src/compiler/spirv/vtn_subgroup.c | 3 +-- 4 files changed, 11 insertions(+), 15 deletions(-) diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp index 356d7aadce7..f274818ea2f 100644 --- a/src/amd/compiler/aco_instruction_selection.cpp +++ b/src/amd/compiler/aco_instruction_selection.cpp @@ -8475,7 +8475,6 @@ visit_intrinsic(isel_context* ctx, nir_intrinsic_instr* instr) Temp src = get_ssa_temp(ctx, instr->src[0].ssa); Temp delta = get_ssa_temp(ctx, instr->src[1].ssa); Temp dst = get_ssa_temp(ctx, &instr->def); - assert(nir_intrinsic_execution_scope(instr) == SCOPE_SUBGROUP); assert(instr->def.bit_size > 1 && instr->def.bit_size <= 32); if (!nir_src_is_divergent(instr->src[0])) { diff --git a/src/compiler/nir/nir_intrinsics.py b/src/compiler/nir/nir_intrinsics.py index ab952dad907..38e39d17c5d 100644 --- a/src/compiler/nir/nir_intrinsics.py +++ b/src/compiler/nir/nir_intrinsics.py @@ -516,7 +516,7 @@ intrinsic("quad_vote_all", src_comp=[1], dest_comp=1, flags=[CAN_ELIMINATE]) # Rotate operation from SPIR-V: SpvOpGroupNonUniformRotateKHR. intrinsic("rotate", src_comp=[0, 1], dest_comp=0, bit_sizes=src0, - indices=[EXECUTION_SCOPE, CLUSTER_SIZE], flags=[CAN_ELIMINATE]); + indices=[CLUSTER_SIZE], flags=[CAN_ELIMINATE]); intrinsic("reduce", src_comp=[0], dest_comp=0, bit_sizes=src0, indices=[REDUCTION_OP, CLUSTER_SIZE], flags=[CAN_ELIMINATE]) diff --git a/src/compiler/nir/nir_lower_subgroups.c b/src/compiler/nir/nir_lower_subgroups.c index d35cac3818f..2982f7f2e3a 100644 --- a/src/compiler/nir/nir_lower_subgroups.c +++ b/src/compiler/nir/nir_lower_subgroups.c @@ -1061,17 +1061,15 @@ lower_subgroups_instr(nir_builder *b, nir_instr *instr, void *_options) break; case nir_intrinsic_rotate: - if (nir_intrinsic_execution_scope(intrin) == SCOPE_SUBGROUP) { - if (options->lower_rotate_to_shuffle && - (!options->lower_boolean_shuffle || intrin->src[0].ssa->bit_size != 1)) - return lower_to_shuffle(b, intrin, options); - else if (options->lower_to_scalar && intrin->num_components > 1) - return lower_subgroup_op_to_scalar(b, intrin); - else if (options->lower_boolean_shuffle && intrin->src[0].ssa->bit_size == 1) - return lower_boolean_shuffle(b, intrin, options); - else if (options->lower_shuffle_to_32bit && intrin->src[0].ssa->bit_size == 64) - return lower_subgroup_op_to_32bit(b, intrin); - } + if (options->lower_rotate_to_shuffle && + (!options->lower_boolean_shuffle || intrin->src[0].ssa->bit_size != 1)) + return lower_to_shuffle(b, intrin, options); + else if (options->lower_to_scalar && intrin->num_components > 1) + return lower_subgroup_op_to_scalar(b, intrin); + else if (options->lower_boolean_shuffle && intrin->src[0].ssa->bit_size == 1) + return lower_boolean_shuffle(b, intrin, options); + else if (options->lower_shuffle_to_32bit && intrin->src[0].ssa->bit_size == 64) + return lower_subgroup_op_to_32bit(b, intrin); break; case nir_intrinsic_masked_swizzle_amd: if (options->lower_to_scalar && intrin->num_components > 1) { diff --git a/src/compiler/spirv/vtn_subgroup.c b/src/compiler/spirv/vtn_subgroup.c index c75825adee3..2df49bd55c0 100644 --- a/src/compiler/spirv/vtn_subgroup.c +++ b/src/compiler/spirv/vtn_subgroup.c @@ -327,7 +327,6 @@ vtn_handle_subgroup(struct vtn_builder *b, SpvOp opcode, } case SpvOpGroupNonUniformRotateKHR: { - const mesa_scope scope = vtn_translate_scope(b, vtn_constant_uint(b, w[3])); const uint32_t cluster_size = count > 6 ? vtn_constant_uint(b, w[6]) : 0; vtn_fail_if(cluster_size && !IS_POT(cluster_size), "Behavior is undefined unless ClusterSize is at least 1 and a power of 2."); @@ -336,7 +335,7 @@ vtn_handle_subgroup(struct vtn_builder *b, SpvOp opcode, struct vtn_ssa_value *delta = vtn_ssa_value(b, w[5]); vtn_push_nir_ssa(b, w[2], vtn_build_subgroup_instr(b, nir_intrinsic_rotate, - value, delta->def, scope, cluster_size)->def); + value, delta->def, cluster_size, 0)->def); break; }