diff --git a/src/asahi/compiler/agx_opcodes.c.py b/src/asahi/compiler/agx_opcodes.c.py
index 31d00ddda36..08f7c5a0d9c 100644
--- a/src/asahi/compiler/agx_opcodes.c.py
+++ b/src/asahi/compiler/agx_opcodes.c.py
@@ -24,7 +24,6 @@ const struct agx_opcode_info agx_opcodes_info[AGX_NUM_OPCODES] = {
    [AGX_OPCODE_${opcode.upper()}] = {
       "${opcode}", ${op.srcs}, ${op.dests}, ${" | ".join(imms)},
       ${make_encoding(op.encoding_32)},
-      ${make_encoding(op.encoding_16)},
       AGX_SCHEDULE_CLASS_${op.schedule_class.upper()},
       ${int(op.is_float)},
       ${int(op.can_eliminate)},
diff --git a/src/asahi/compiler/agx_opcodes.h.py b/src/asahi/compiler/agx_opcodes.h.py
index 72c7c54c55c..64da7e9b3e5 100644
--- a/src/asahi/compiler/agx_opcodes.h.py
+++ b/src/asahi/compiler/agx_opcodes.h.py
@@ -72,7 +72,6 @@ struct agx_opcode_info {
    unsigned nr_dests;
    uint64_t immediates;
    struct agx_encoding encoding;
-   struct agx_encoding encoding_16;
    enum agx_schedule_class schedule_class;
    bool is_float : 1;
    bool can_eliminate : 1;
diff --git a/src/asahi/compiler/agx_opcodes.py b/src/asahi/compiler/agx_opcodes.py
index 8e4ef117668..ac2b78ad5f9 100644
--- a/src/asahi/compiler/agx_opcodes.py
+++ b/src/asahi/compiler/agx_opcodes.py
@@ -11,7 +11,7 @@ VARIABLE = ~0
 
 class Opcode(object):
    def __init__(self, name, dests, srcs, imms, is_float, can_eliminate,
-                can_reorder, schedule_class, encoding_16, encoding_32):
+                can_reorder, schedule_class, encoding_32):
       self.name = name
       self.dests = dests if dests != VARIABLE else 0
       self.srcs = srcs if srcs != VARIABLE else 0
@@ -22,7 +22,6 @@ class Opcode(object):
       self.can_eliminate = can_eliminate
       self.can_reorder = can_reorder
       self.schedule_class = schedule_class
-      self.encoding_16 = encoding_16
       self.encoding_32 = encoding_32
 
 class Immediate(object):
@@ -47,13 +46,11 @@ class Encoding(object):
          assert(length_long == length_short + (4 if length_short > 8 else 2))
 
 def op(name, encoding_32, dests = 1, srcs = 0, imms = [], is_float = False,
-        can_eliminate = True, can_reorder = True, encoding_16 = None,
-        schedule_class = "none"):
-   encoding_16 = Encoding(encoding_16) if encoding_16 is not None else None
+        can_eliminate = True, can_reorder = True, schedule_class = "none"):
    encoding_32 = Encoding(encoding_32) if encoding_32 is not None else None
 
    opcodes[name] = Opcode(name, dests, srcs, imms, is_float, can_eliminate,
-                          can_reorder, schedule_class,  encoding_16, encoding_32)
+                          can_reorder, schedule_class,  encoding_32)
 
 def immediate(name, ctype = "uint32_t"):
    imm = Immediate(name, ctype)
diff --git a/src/asahi/compiler/agx_pack.c b/src/asahi/compiler/agx_pack.c
index b5ed490f587..d4ef98bfe2f 100644
--- a/src/asahi/compiler/agx_pack.c
+++ b/src/asahi/compiler/agx_pack.c
@@ -409,10 +409,10 @@ static void
 agx_pack_alu(struct util_dynarray *emission, agx_instr *I)
 {
    struct agx_opcode_info info = agx_opcodes_info[I->op];
-   bool is_16 = agx_all_16(I) && info.encoding_16.exact;
+   struct agx_encoding encoding = info.encoding;
+
    bool is_f16 = (I->op == AGX_OPCODE_HMUL || I->op == AGX_OPCODE_HFMA ||
                   I->op == AGX_OPCODE_HADD);
-   struct agx_encoding encoding = is_16 ? info.encoding_16 : info.encoding;
 
    pack_assert_msg(I, encoding.exact, "invalid encoding");
 
@@ -452,7 +452,7 @@ agx_pack_alu(struct util_dynarray *emission, agx_instr *I)
       unsigned src_extend = (src >> 10);
 
       /* Size bit always zero and so omitted for 16-bit */
-      if (is_16 && !is_cmpsel)
+      if (is_f16 && !is_cmpsel)
          pack_assert(I, (src_short & (1 << 9)) == 0);
 
       if (info.is_float || (I->op == AGX_OPCODE_FCMPSEL && !is_cmpsel)) {