diff --git a/src/freedreno/isa/ir3-cat5.xml b/src/freedreno/isa/ir3-cat5.xml index 38fa5b77c40..a129b75fb03 100644 --- a/src/freedreno/isa/ir3-cat5.xml +++ b/src/freedreno/isa/ir3-cat5.xml @@ -85,15 +85,7 @@ SOFTWARE. {SY}{JP}{NAME}{3D}{A}{O}{P}{S} {TYPE}({WRMASK}){DST_HALF}{DST}{SRC1}{SRC2}{SAMP}{TEX} - - - ({TYPE} == 0) /* f16 */ || - ({TYPE} == 2) /* u16 */ || - ({TYPE} == 4) /* s16 */ || - ({TYPE} == 6) /* u8 */ || - ({TYPE} == 7) /* s8 */ - - + diff --git a/src/freedreno/isa/ir3-cat6.xml b/src/freedreno/isa/ir3-cat6.xml index 825f4426224..7c1b2516f10 100644 --- a/src/freedreno/isa/ir3-cat6.xml +++ b/src/freedreno/isa/ir3-cat6.xml @@ -32,6 +32,8 @@ SOFTWARE. 110 + + src->cat6.type @@ -59,7 +61,7 @@ SOFTWARE. - {SY}{JP}{NAME}.{TYPE} {DST}, g[{SRC1}{OFF}], {SIZE} + {SY}{JP}{NAME}.{TYPE} {TYPE_HALF}{DST}, g[{SRC1}{OFF}], {SIZE} @@ -79,12 +81,12 @@ SOFTWARE. - {SY}{JP}{NAME}.{TYPE} {DST}, g[{SRC1}+({SRC2}{OFF})<<{SRC2_BYTE_SHIFT}], {SIZE} + {SY}{JP}{NAME}.{TYPE} {TYPE_HALF}{DST}, g[{SRC1}+({SRC2}{OFF})<<{SRC2_BYTE_SHIFT}], {SIZE} - {SY}{JP}{NAME}.{TYPE} {DST}, g[{SRC1}+{SRC2}<<{SRC2_BYTE_SHIFT}{OFF}<<2], {SIZE} + {SY}{JP}{NAME}.{TYPE} {TYPE_HALF}{DST}, g[{SRC1}+{SRC2}<<{SRC2_BYTE_SHIFT}{OFF}<<2], {SIZE} {SRC2_ADD_DWORD_SHIFT} > 0 @@ -129,7 +131,7 @@ SOFTWARE. - {SY}{JP}{NAME}.{TYPE} g[{SRC1}{OFF}], {SRC3}, {SIZE} + {SY}{JP}{NAME}.{TYPE} g[{SRC1}{OFF}], {TYPE_HALF}{SRC3}, {SIZE} @@ -156,12 +158,12 @@ SOFTWARE. - {SY}{JP}{NAME}.{TYPE} g[{SRC1}+({SRC2}{OFF})<<{DST_BYTE_SHIFT}], {SRC3}, {SIZE} + {SY}{JP}{NAME}.{TYPE} g[{SRC1}+({SRC2}{OFF})<<{DST_BYTE_SHIFT}], {TYPE_HALF}{SRC3}, {SIZE} - {SY}{JP}{NAME}.{TYPE} g[{SRC1}+{SRC2}<<{DST_BYTE_SHIFT}{OFF}<<2], {SRC3}, {SIZE} + {SY}{JP}{NAME}.{TYPE} g[{SRC1}+{SRC2}<<{DST_BYTE_SHIFT}{OFF}<<2], {TYPE_HALF}{SRC3}, {SIZE} {SRC2_ADD_DWORD_SHIFT} > 0 diff --git a/src/freedreno/isa/ir3-common.xml b/src/freedreno/isa/ir3-common.xml index 2b7868336b2..b6717b557e3 100644 --- a/src/freedreno/isa/ir3-common.xml +++ b/src/freedreno/isa/ir3-common.xml @@ -308,6 +308,14 @@ SOFTWARE. + + ({TYPE} == 0) /* f16 */ || + ({TYPE} == 2) /* u16 */ || + ({TYPE} == 4) /* s16 */ || + ({TYPE} == 6) /* u8 */ || + ({TYPE} == 7) /* s8 */ + +