From 228169c87c62caaa8770482d95b2b79a904075ff Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Fri, 28 May 2021 21:52:31 +0200 Subject: [PATCH] aco: Add note about v_alignbyte in the ISA README. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We tried to use this instruction for a more optimal sequence, but it turned out that it doesn't exactly work as it was supposed to. This note is to help others who want to use it. Signed-off-by: Timur Kristóf Reviewed-by: Tony Wasserka Part-of: --- src/amd/compiler/README-ISA.md | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/src/amd/compiler/README-ISA.md b/src/amd/compiler/README-ISA.md index c692fdf7e16..296ba7a864a 100644 --- a/src/amd/compiler/README-ISA.md +++ b/src/amd/compiler/README-ISA.md @@ -44,6 +44,18 @@ is written in the GCN3 reference guide: D.u = CountOneBits(S0.u) + S1.u. ``` +## `v_alignbyte_b32` + +All versions of the ISA document are vague about it, but after some trial and +error we discovered that only 2 bits of the 3rd operand are used. +Therefore, this instruction can't shift more than 24 bits. + +The correct description of `v_alignbyte_b32` is probably the following: + +``` +D.u = ({S0, S1} >> (8 * S2.u[1:0])) & 0xffffffff +``` + ## SMEM stores The Vega ISA references doesn't say this (or doesn't make it clear), but