From 1f253700bc30bb62a9d52f72a121705aee5fe38c Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Mon, 20 Jan 2025 06:23:31 -0800 Subject: [PATCH] radv: do not overallocate the number of exports for streamout on GFX12 This shouldn't be needed because GE_GS_OREDERD_ID is always reset to 0 when streamout is started. Thus it's technically impossible that the ordered ID is more than 12-bit. Signed-off-by: Samuel Pitoiset Part-of: --- src/amd/vulkan/radv_shader.c | 14 +------------- 1 file changed, 1 insertion(+), 13 deletions(-) diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c index 8d3d28af8f3..ccf987c3c83 100644 --- a/src/amd/vulkan/radv_shader.c +++ b/src/amd/vulkan/radv_shader.c @@ -1535,19 +1535,7 @@ radv_precompute_registers_hw_ngg(struct radv_device *device, const struct ac_sha const unsigned num_prim_params = info->outinfo.prim_param_exports; if (pdev->info.gfx_level >= GFX12) { - unsigned num_params = info->outinfo.param_exports; - - /* Since there is no alloc/dealloc mechanism for the 12-bit ordered IDs, they can wrap - * around if there are more than 2^12 workgroups, causing 2 workgroups to get the same - * ordered ID, which would break the streamout algorithm. - * The recommended solution is to use the alloc/dealloc mechanism of the attribute ring, - * which is enough to limit the range of ordered IDs that can be in flight. - */ - if (info->so.num_outputs) { - num_params = MAX2(num_params, 8); - } else { - num_params = MAX2(num_params, 1); - } + const unsigned num_params = MAX2(info->outinfo.param_exports, 1); info->regs.spi_vs_out_config = S_00B0C4_VS_EXPORT_COUNT(num_params - 1) | S_00B0C4_PRIM_EXPORT_COUNT(num_prim_params) | S_00B0C4_NO_PC_EXPORT(no_pc_export);