diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 465a5791f81..438e6a85fb0 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -2613,15 +2613,16 @@ radv_link_shaders(struct radv_pipeline *pipeline, continue; unsigned col_format = (pipeline_key->ps.col_format >> (4 * idx)) & 0xf; - switch (col_format) { - case V_028714_SPI_SHADER_ZERO: + unsigned cb_target_mask = (pipeline_key->ps.cb_target_mask >> (4 * idx)) & 0xf; + + if (col_format == V_028714_SPI_SHADER_ZERO || + (col_format == V_028714_SPI_SHADER_32_R && !cb_target_mask && + !pipeline_key->ps.mrt0_is_dual_src)) { + /* Remove the color export if it's unused or in presence of holes. */ info->outputs_written &= ~BITFIELD64_BIT(var->data.location); var->data.location = 0; var->data.mode = nir_var_shader_temp; fixup_derefs = true; - break; - default: - break; } } if (fixup_derefs) { @@ -2973,6 +2974,8 @@ radv_generate_graphics_pipeline_key(const struct radv_pipeline *pipeline, } key.ps.col_format = blend->spi_shader_col_format; + key.ps.cb_target_mask = blend->cb_target_mask; + key.ps.mrt0_is_dual_src = blend->mrt0_is_dual_src; if (pipeline->device->physical_device->rad_info.chip_class < GFX8) { key.ps.is_int8 = blend->col_format_is_int8; key.ps.is_int10 = blend->col_format_is_int10; diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h index d34781e729f..3195c35be14 100644 --- a/src/amd/vulkan/radv_shader.h +++ b/src/amd/vulkan/radv_shader.h @@ -84,8 +84,10 @@ struct radv_pipeline_key { uint32_t col_format; uint32_t is_int8; uint32_t is_int10; + uint32_t cb_target_mask; uint8_t log2_ps_iter_samples; uint8_t num_samples; + bool mrt0_is_dual_src; bool lower_discard_to_demote; bool enable_mrt_output_nan_fixup;