diff --git a/src/gallium/drivers/radeonsi/si_vpe.c b/src/gallium/drivers/radeonsi/si_vpe.c index 128881aa685..d77fd7bf286 100755 --- a/src/gallium/drivers/radeonsi/si_vpe.c +++ b/src/gallium/drivers/radeonsi/si_vpe.c @@ -33,7 +33,6 @@ #include #include "si_vpe.h" -#define SI_VPE_PRETAG "" #define SI_VPE_LOG_LEVEL_DEFAULT 0 #define SI_VPE_LOG_LEVEL_INFO 1 #define SI_VPE_LOG_LEVEL_WARNING 2 @@ -57,6 +56,17 @@ #define SIVPE_ERR(fmt, args...) \ fprintf(stderr, "SIVPE ERROR %s:%d %s " fmt, __FILE__, __LINE__, __func__, ##args) +#define SIVPE_PRINT(fmt, args...) \ + printf("SIVPE %s: " fmt, __func__, ##args); + +/* Pre-defined color primaries of BT601, BT709, BT2020 */ +static struct vpe_hdr_metadata Color_Parimaries[] = { + /* RedX RedY GreenX GreenY BlueX BlueY WhiteX WhiteY minlum maxlum maxlig avglig*/ + [VPE_PRIMARIES_BT601] = {31500, 17000, 15500, 29750, 7750, 3500, 15635, 16450, 10, 270, 1, 1}, + [VPE_PRIMARIES_BT709] = {32000, 16500, 15000, 30000, 7500, 3000, 15635, 16450, 10, 270, 1, 1}, + [VPE_PRIMARIES_BT2020] = {34000, 16000, 13249, 34500, 7500, 3000, 15635, 16450, 10, 1100, 1, 1}, +}; + /* Use this enum to help us for accessing the anonymous struct src, dst * in blit_info. */ @@ -65,7 +75,6 @@ enum { USE_DST_SURFACE }; - static void * si_vpe_zalloc(void* mem_ctx, size_t size) { @@ -73,7 +82,6 @@ si_vpe_zalloc(void* mem_ctx, size_t size) return CALLOC(1, size); } - static void si_vpe_free(void* mem_ctx, void *ptr) { @@ -84,7 +92,6 @@ si_vpe_free(void* mem_ctx, void *ptr) } } - static void si_vpe_log(void* log_ctx, const char* fmt, ...) { @@ -96,25 +103,18 @@ si_vpe_log(void* log_ctx, const char* fmt, ...) va_end(args); } - static void si_vpe_populate_debug_options(struct vpe_debug_options* debug) { - /* ref: vpe-utils */ - debug->flags.cm_in_bypass = 0; - debug->identity_3dlut = 0; - debug->sce_3dlut = 0; - debug->disable_reuse_bit = 0; + /* Enable debug options here if needed */ } - static void si_vpe_populate_callback_modules(struct vpe_callback_funcs* funcs) { funcs->log = si_vpe_log; funcs->zalloc = si_vpe_zalloc; funcs->free = si_vpe_free; - return; } static char* @@ -167,6 +167,10 @@ si_vpe_get_tf_str(enum vpe_transfer_function tf) return "PQ_NORMALIZED"; case VPE_TF_HLG: return "HLG"; + case VPE_TF_SRGB: + return "SRGB"; + case VPE_TF_BT709: + return "BT709"; case VPE_TF_COUNT: default: return "ERROR"; @@ -184,14 +188,14 @@ next_buffer(struct vpe_video_processor *vpeproc) static enum vpe_status si_vpe_populate_init_data(struct si_context *sctx, struct vpe_init_data* params, uint8_t log_level) { - if (!sctx || !params) { + if (!sctx || !params) return VPE_STATUS_ERROR; - } params->ver_major = sctx->screen->info.ip[AMD_IP_VPE].ver_major; params->ver_minor = sctx->screen->info.ip[AMD_IP_VPE].ver_minor; params->ver_rev = sctx->screen->info.ip[AMD_IP_VPE].ver_rev; + memset(¶ms->debug, 0, sizeof(struct vpe_debug_options)); si_vpe_populate_debug_options(¶ms->debug); si_vpe_populate_callback_modules(¶ms->funcs); @@ -208,14 +212,12 @@ si_vpe_populate_init_data(struct si_context *sctx, struct vpe_init_data* params, static enum vpe_status si_vpe_allocate_buffer(struct vpe_build_bufs **bufs) { - if (!bufs) { + if (!bufs) return VPE_STATUS_ERROR; - } *bufs = (struct vpe_build_bufs *)MALLOC(sizeof(struct vpe_build_bufs)); - if (!*bufs) { + if (!*bufs) return VPE_STATUS_NO_MEMORY; - } (*bufs)->cmd_buf.cpu_va = 0; (*bufs)->emb_buf.cpu_va = 0; @@ -228,19 +230,19 @@ si_vpe_allocate_buffer(struct vpe_build_bufs **bufs) static void si_vpe_free_buffer(struct vpe_build_bufs *bufs) { - if (!bufs) { + if (!bufs) return; - } + free(bufs); } static enum vpe_surface_pixel_format -si_vpe_format(enum pipe_format format) +si_vpe_pipe_map_to_vpe_format(enum pipe_format format) { enum vpe_surface_pixel_format ret; switch (format) { - /* VPE input format: */ + /* YUV format: */ case PIPE_FORMAT_NV12: ret = VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb; break; @@ -250,7 +252,7 @@ si_vpe_format(enum pipe_format format) case PIPE_FORMAT_P010: ret = VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb; break; - /* VPE output format: */ + /* RGB format: */ case PIPE_FORMAT_A8R8G8B8_UNORM: ret = VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA8888; break; @@ -275,6 +277,9 @@ si_vpe_format(enum pipe_format format) case PIPE_FORMAT_B8G8R8X8_UNORM: ret = VPE_SURFACE_PIXEL_FORMAT_GRPH_XRGB8888; break; + /* ARGB 2-10-10-10 formats are not supported in Mesa VA-frontend + * but they are defined in Mesa already. + */ case PIPE_FORMAT_A2R10G10B10_UNORM: ret = VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA1010102; break; @@ -294,7 +299,76 @@ si_vpe_format(enum pipe_format format) return ret; } -static enum vpe_status +static enum vpe_color_primaries +si_vpe_maps_vpp_to_vpe_primaries(enum pipe_video_vpp_color_primaries colour_primaries) +{ + if (colour_primaries == PIPE_VIDEO_VPP_PRI_BT470BG || colour_primaries == PIPE_VIDEO_VPP_PRI_SMPTE170M) + return VPE_PRIMARIES_BT601; + + else if (colour_primaries == PIPE_VIDEO_VPP_PRI_BT709) + return VPE_PRIMARIES_BT709; + + else if (colour_primaries == PIPE_VIDEO_VPP_PRI_BT2020) + return VPE_PRIMARIES_BT2020; + + SIVPE_PRINT("WARNING: map VA-API primaries(%d) to BT709\n", colour_primaries); + return VPE_PRIMARIES_BT709; +} + +static enum vpe_transfer_function +si_vpe_maps_vpp_to_vpe_transfer_function( + enum pipe_video_vpp_transfer_characteristic transfer_characteristics, + enum pipe_video_vpp_matrix_coefficients matrix_coefficients) +{ + if (transfer_characteristics == PIPE_VIDEO_VPP_TRC_BT709) + return (matrix_coefficients == PIPE_VIDEO_VPP_MCF_RGB)? VPE_TF_SRGB : VPE_TF_BT709; + + else if (transfer_characteristics == PIPE_VIDEO_VPP_TRC_GAMMA22) + return VPE_TF_G22; + + else if (transfer_characteristics == PIPE_VIDEO_VPP_TRC_SMPTEST2084) + return VPE_TF_PQ; + + else if (transfer_characteristics == PIPE_VIDEO_VPP_TRC_LINEAR) + return VPE_TF_G10; + + else if (transfer_characteristics == PIPE_VIDEO_VPP_TRC_ARIB_STD_B67) + return VPE_TF_HLG; + + else if (transfer_characteristics == PIPE_VIDEO_VPP_TRC_BT2020_10) + return VPE_TF_G10; + + else if (transfer_characteristics == PIPE_VIDEO_VPP_TRC_SMPTEST428_1) + return VPE_TF_G24; + + else if (transfer_characteristics == PIPE_VIDEO_VPP_TRC_BT2020_12) + return (matrix_coefficients == PIPE_VIDEO_VPP_MCF_RGB)? VPE_TF_SRGB : VPE_TF_BT709; + + SIVPE_PRINT("WARNING: map VA-API transfer_characteristics(%d) to BT709/SRGB\n", transfer_characteristics); + return (matrix_coefficients == PIPE_VIDEO_VPP_MCF_RGB)? VPE_TF_SRGB : VPE_TF_BT709; +} + +static void +si_vpe_load_default_primaries(struct vpe_hdr_metadata* vpe_hdr, enum vpe_color_primaries primaries) +{ + enum vpe_color_primaries pri_idx = (primaries < VPE_PRIMARIES_COUNT)? + primaries : VPE_PRIMARIES_BT709; + + vpe_hdr->redX = Color_Parimaries[pri_idx].redX; + vpe_hdr->redY = Color_Parimaries[pri_idx].redY; + vpe_hdr->greenX = Color_Parimaries[pri_idx].greenX; + vpe_hdr->greenY = Color_Parimaries[pri_idx].greenY; + vpe_hdr->blueX = Color_Parimaries[pri_idx].blueX; + vpe_hdr->blueY = Color_Parimaries[pri_idx].blueY; + vpe_hdr->whiteX = Color_Parimaries[pri_idx].whiteX; + vpe_hdr->whiteY = Color_Parimaries[pri_idx].whiteY; + vpe_hdr->min_mastering = Color_Parimaries[pri_idx].min_mastering; + vpe_hdr->max_mastering = Color_Parimaries[pri_idx].max_mastering; + vpe_hdr->max_content = Color_Parimaries[pri_idx].max_content; + vpe_hdr->avg_content = Color_Parimaries[pri_idx].avg_content; +} + +static void si_vpe_set_color_space(const struct pipe_vpp_desc *process_properties, struct vpe_color_space *color_space, enum pipe_format format, @@ -303,68 +377,51 @@ si_vpe_set_color_space(const struct pipe_vpp_desc *process_properties, enum pipe_video_vpp_color_standard_type colors_standard; enum pipe_video_vpp_color_range color_range; enum pipe_video_vpp_chroma_siting chroma_siting; + enum pipe_video_vpp_color_primaries colour_primaries; + enum pipe_video_vpp_transfer_characteristic transfer_characteristics; + enum pipe_video_vpp_matrix_coefficients matrix_coefficients; if (which_surface == USE_SRC_SURFACE) { - colors_standard = process_properties->in_colors_standard; - color_range = process_properties->in_color_range; - chroma_siting = process_properties->in_chroma_siting; + colors_standard = process_properties->in_colors_standard; + color_range = process_properties->in_color_range; + chroma_siting = process_properties->in_chroma_siting; + colour_primaries = process_properties->in_color_primaries; + transfer_characteristics = process_properties->in_transfer_characteristics; + matrix_coefficients = process_properties->in_matrix_coefficients; } else { - colors_standard = process_properties->out_colors_standard; - color_range = process_properties->out_color_range; - chroma_siting = process_properties->out_chroma_siting; + colors_standard = process_properties->out_colors_standard; + color_range = process_properties->out_color_range; + chroma_siting = process_properties->out_chroma_siting; + colour_primaries = process_properties->out_color_primaries; + transfer_characteristics = process_properties->out_transfer_characteristics; + matrix_coefficients = process_properties->out_matrix_coefficients; } switch (colors_standard) { + case PIPE_VIDEO_VPP_COLOR_STANDARD_TYPE_EXPLICIT: + /* use original settings from user application */ + break; + case PIPE_VIDEO_VPP_COLOR_STANDARD_TYPE_BT601: - color_space->primaries = VPE_PRIMARIES_BT601; - color_space->tf = VPE_TF_G24; - break; - case PIPE_VIDEO_VPP_COLOR_STANDARD_TYPE_BT709: - color_space->primaries = VPE_PRIMARIES_BT709; - color_space->tf = VPE_TF_G22; + colour_primaries = PIPE_VIDEO_VPP_PRI_SMPTE170M; + transfer_characteristics = PIPE_VIDEO_VPP_TRC_SMPTE170M; + matrix_coefficients = PIPE_VIDEO_VPP_MCF_SMPTE170M; break; + case PIPE_VIDEO_VPP_COLOR_STANDARD_TYPE_BT2020: - color_space->primaries = VPE_PRIMARIES_BT2020; - color_space->tf = VPE_TF_PQ; + colour_primaries = PIPE_VIDEO_VPP_PRI_BT2020; + transfer_characteristics = PIPE_VIDEO_VPP_TRC_BT2020_10; + matrix_coefficients = PIPE_VIDEO_VPP_MCF_BT2020_NCL; break; + default: - color_space->primaries = VPE_PRIMARIES_BT709; - color_space->tf = VPE_TF_G22; + case PIPE_VIDEO_VPP_COLOR_STANDARD_TYPE_BT709: + colour_primaries = PIPE_VIDEO_VPP_PRI_BT709; + transfer_characteristics = PIPE_VIDEO_VPP_TRC_BT709; + matrix_coefficients = PIPE_VIDEO_VPP_MCF_BT709; break; } - switch (color_range) { - case PIPE_VIDEO_VPP_CHROMA_COLOR_RANGE_REDUCED: - color_space->range = VPE_COLOR_RANGE_STUDIO; - break; - case PIPE_VIDEO_VPP_CHROMA_COLOR_RANGE_FULL: - color_space->range = VPE_COLOR_RANGE_FULL; - break; - default: - color_space->range = VPE_COLOR_RANGE_FULL; - break; - } - - /* Default use VPE_CHROMA_COSITING_NONE (CENTER | CENTER) */ - color_space->cositing = VPE_CHROMA_COSITING_NONE; - if (chroma_siting & PIPE_VIDEO_VPP_CHROMA_SITING_VERTICAL_CENTER){ - if (chroma_siting & PIPE_VIDEO_VPP_CHROMA_SITING_HORIZONTAL_LEFT) - color_space->cositing = VPE_CHROMA_COSITING_LEFT; - //else if (chroma_siting & PIPE_VIDEO_VPP_CHROMA_SITING_HORIZONTAL_CENTER) - // color_space->cositing = VPE_CHROMA_COSITING_NONE; - } else if (chroma_siting & PIPE_VIDEO_VPP_CHROMA_SITING_VERTICAL_TOP) { - if (chroma_siting & PIPE_VIDEO_VPP_CHROMA_SITING_HORIZONTAL_LEFT) - color_space->cositing = VPE_CHROMA_COSITING_TOPLEFT; - //else if (chroma_siting & PIPE_VIDEO_VPP_CHROMA_SITING_HORIZONTAL_CENTER) - // color_space->cositing = VPE_CHROMA_COSITING_NONE; - } else if (chroma_siting & PIPE_VIDEO_VPP_CHROMA_SITING_VERTICAL_BOTTOM) { - if (chroma_siting & PIPE_VIDEO_VPP_CHROMA_SITING_HORIZONTAL_LEFT) - color_space->cositing = VPE_CHROMA_COSITING_LEFT; - //else if (chroma_siting & PIPE_VIDEO_VPP_CHROMA_SITING_HORIZONTAL_CENTER) - // color_space->cositing = VPE_CHROMA_COSITING_NONE; - } - - /* VPE 1.0 Input format only supports NV12 and NV21 now */ switch (format) { case PIPE_FORMAT_NV12: case PIPE_FORMAT_NV21: @@ -384,13 +441,43 @@ si_vpe_set_color_space(const struct pipe_vpp_desc *process_properties, case PIPE_FORMAT_A2B10G10R10_UNORM: case PIPE_FORMAT_B10G10R10A2_UNORM: default: + matrix_coefficients = PIPE_VIDEO_VPP_MCF_RGB; color_space->encoding = VPE_PIXEL_ENCODING_RGB; break; } - return VPE_STATUS_OK; + + switch (color_range) { + case PIPE_VIDEO_VPP_CHROMA_COLOR_RANGE_REDUCED: + color_space->range = VPE_COLOR_RANGE_STUDIO; + break; + default: + case PIPE_VIDEO_VPP_CHROMA_COLOR_RANGE_FULL: + color_space->range = VPE_COLOR_RANGE_FULL; + break; + } + + /* Force RGB output range is Full to have better color performance */ + /* TO-DO: Should Mesa have to know the display console is TV or PC Monitor? */ + if (!util_format_is_yuv(format) && (which_surface == USE_DST_SURFACE)) + color_space->range = VPE_COLOR_RANGE_FULL; + + /* Default use VPE_CHROMA_COSITING_NONE (CENTER | CENTER) */ + color_space->cositing = VPE_CHROMA_COSITING_NONE; + if (chroma_siting & PIPE_VIDEO_VPP_CHROMA_SITING_VERTICAL_CENTER){ + if (chroma_siting & PIPE_VIDEO_VPP_CHROMA_SITING_HORIZONTAL_LEFT) + color_space->cositing = VPE_CHROMA_COSITING_LEFT; + } else if (chroma_siting & PIPE_VIDEO_VPP_CHROMA_SITING_VERTICAL_TOP) { + if (chroma_siting & PIPE_VIDEO_VPP_CHROMA_SITING_HORIZONTAL_LEFT) + color_space->cositing = VPE_CHROMA_COSITING_TOPLEFT; + } else if (chroma_siting & PIPE_VIDEO_VPP_CHROMA_SITING_VERTICAL_BOTTOM) { + if (chroma_siting & PIPE_VIDEO_VPP_CHROMA_SITING_HORIZONTAL_LEFT) + color_space->cositing = VPE_CHROMA_COSITING_LEFT; + } + + color_space->primaries = si_vpe_maps_vpp_to_vpe_primaries(colour_primaries); + color_space->tf = si_vpe_maps_vpp_to_vpe_transfer_function(transfer_characteristics, matrix_coefficients); } -/* Combine si_vpe_set_plane_address and si_vpe_set_plane_size*/ static enum vpe_status si_vpe_set_plane_info(struct vpe_video_processor *vpeproc, const struct pipe_vpp_desc *process_properties, @@ -400,134 +487,54 @@ si_vpe_set_plane_info(struct vpe_video_processor *vpeproc, { struct vpe_plane_address *plane_address = &surface_info->address; struct vpe_plane_size *plane_size = &surface_info->plane_size; - struct si_resource *si_res; - uint32_t width, height, pitch, pos_x, pos_y, offset; + struct si_texture *si_tex_0; + struct si_texture *si_tex_1; enum pipe_format format; - if (which_surface == USE_SRC_SURFACE) { - pos_x = process_properties->src_region.x0; - pos_y = process_properties->src_region.y0; - width = process_properties->src_region.x1 - pos_x; - height = process_properties->src_region.y1 - pos_y; + if (which_surface == USE_SRC_SURFACE) format = process_properties->base.input_format; - } else { - pos_x = process_properties->dst_region.x0; - pos_y = process_properties->dst_region.y0; - width = process_properties->dst_region.x1 - pos_x; - height = process_properties->dst_region.y1 - pos_y; + else format = process_properties->base.output_format; - } - /* Formate Color Space */ - surface_info->format = si_vpe_format(format); - si_vpe_set_color_space(process_properties, &surface_info->cs, format, which_surface); - - /* Get surface info, such as buffer alignment and offset */ - if (vpeproc->base.context->screen && vpeproc->base.context->screen->resource_get_info) { - vpeproc->base.context->screen->resource_get_info(vpeproc->base.context->screen, - surfaces[0]->texture, - &pitch, - &offset); - } else { - SIVPE_ERR("Get plane pitch and offset info failed\n"); - return VPE_STATUS_ERROR; - } - - si_res = si_resource(surfaces[0]->texture); + /* Trusted memory not supported now */ plane_address->tmz_surface = false; - /* here is the SURFACE size, not image rect */ - plane_size->surface_size.x = 0; - plane_size->surface_size.y = 0; - plane_size->surface_size.width = surfaces[0]->width; - plane_size->surface_size.height = surfaces[0]->height; - plane_size->surface_pitch = pitch; // Byte alignment - - switch (format) { - case PIPE_FORMAT_NV12: - case PIPE_FORMAT_NV21: + /* Only support 1 plane for RGB formats, and 2 plane format for YUV formats */ + if (util_format_is_yuv(format) && util_format_get_num_planes(format) == 2) { + si_tex_0 = (struct si_texture *)surfaces[0]->texture; + si_tex_1 = (struct si_texture *)surfaces[1]->texture; plane_address->type = VPE_PLN_ADDR_TYPE_VIDEO_PROGRESSIVE; - plane_address->video_progressive.luma_addr.quad_part = si_res->gpu_address + offset; - plane_address->video_progressive.luma_meta_addr.quad_part = 0; - plane_address->video_progressive.luma_dcc_const_color.quad_part = 0; - //plane_size->surface_pitch /= 1; // Byte alignment to Pixel alignment - /* Get 2nd plane buffer info */ - if (surfaces[1] && vpeproc->base.context->screen && vpeproc->base.context->screen->resource_get_info) { - vpeproc->base.context->screen->resource_get_info(vpeproc->base.context->screen, - surfaces[1]->texture, - &pitch, - &offset); - } else { - SIVPE_ERR("Get 2nd plane pitch and offset info failed\n"); - return VPE_STATUS_ERROR; - } - si_res = si_resource(surfaces[1]->texture); - plane_address->video_progressive.chroma_addr.quad_part = si_res->gpu_address + offset; - plane_address->video_progressive.chroma_meta_addr.quad_part = 0; - plane_address->video_progressive.chroma_dcc_const_color.quad_part = 0; - - plane_size->chroma_size.x = pos_x; - plane_size->chroma_size.y = pos_y; - plane_size->chroma_size.width = (width + 1) / 2; // 2 pixel-width alignment - plane_size->chroma_size.height = (height + 1) / 2; // 2 pixel-height alignment - plane_size->chroma_pitch = pitch / 2; // Byte alignment to Pixel alignment (NV12/NV21 2nd plane is 16 bits per pixel) - break; - - case PIPE_FORMAT_P010: - plane_address->type = VPE_PLN_ADDR_TYPE_VIDEO_PROGRESSIVE; - plane_address->video_progressive.luma_addr.quad_part = si_res->gpu_address + offset; - plane_address->video_progressive.luma_meta_addr.quad_part = 0; - plane_address->video_progressive.luma_dcc_const_color.quad_part = 0; - plane_size->surface_pitch /= 2; // Byte alignment to Pixel alignment (P010 plane is 16 bits per pixel) - if (surfaces[1] && vpeproc->base.context->screen && vpeproc->base.context->screen->resource_get_info) - vpeproc->base.context->screen->resource_get_info(vpeproc->base.context->screen, - surfaces[1]->texture, - &pitch, - &offset); - else { - SIVPE_ERR("Get 2nd plane pitch and offset info failed\n"); - return VPE_STATUS_ERROR; - } - si_res = si_resource(surfaces[1]->texture); - plane_address->video_progressive.chroma_addr.quad_part = si_res->gpu_address + offset; - plane_address->video_progressive.chroma_meta_addr.quad_part = 0; - plane_address->video_progressive.chroma_dcc_const_color.quad_part = 0; - - plane_size->chroma_size.x = pos_x; - plane_size->chroma_size.y = pos_y; - plane_size->chroma_size.width = (width + 1) / 2; // 2 pixel-width alignment - plane_size->chroma_size.height = (height + 1) / 2; // 2 pixel-height alignment - plane_size->chroma_pitch = pitch / 4; // Byte alignment to Pixel alignment (NV12/NV21 2nd plane is 32 bits per pixel) - break; - - case PIPE_FORMAT_A8R8G8B8_UNORM: - case PIPE_FORMAT_A8B8G8R8_UNORM: - case PIPE_FORMAT_R8G8B8A8_UNORM: - case PIPE_FORMAT_B8G8R8A8_UNORM: - case PIPE_FORMAT_X8R8G8B8_UNORM: - case PIPE_FORMAT_X8B8G8R8_UNORM: - case PIPE_FORMAT_R8G8B8X8_UNORM: - case PIPE_FORMAT_B8G8R8X8_UNORM: + plane_address->video_progressive.luma_addr.quad_part = si_tex_0->buffer.gpu_address + si_tex_0->surface.u.gfx9.surf_offset; + plane_address->video_progressive.chroma_addr.quad_part = si_tex_1->buffer.gpu_address + si_tex_1->surface.u.gfx9.surf_offset; + } else if (!util_format_is_yuv(format) && util_format_get_num_planes(format) == 1){ + si_tex_0 = (struct si_texture *)surfaces[0]->texture; + si_tex_1 = NULL; plane_address->type = VPE_PLN_ADDR_TYPE_GRAPHICS; - plane_address->grph.addr.quad_part = si_res->gpu_address + offset; - plane_address->grph.meta_addr.quad_part = 0; - plane_address->grph.dcc_const_color.quad_part = 0; - plane_size->surface_pitch /= 4; // Byte alignment to Pixel alignment (RGBA plane is 32 bits per pixel) + plane_address->grph.addr.quad_part = si_tex_0->buffer.gpu_address + si_tex_0->surface.u.gfx9.surf_offset; + } else + return VPE_STATUS_NOT_SUPPORTED; - plane_size->chroma_size.x = 0; - plane_size->chroma_size.y = 0; - plane_size->chroma_size.width = 0; - plane_size->chroma_size.height = 0; - plane_size->chroma_pitch = 0; - break; + /* 1st plane ret setting */ + plane_size->surface_size.x = 0; + plane_size->surface_size.y = 0; + plane_size->surface_size.width = surfaces[0]->width; + plane_size->surface_size.height = surfaces[0]->height; + plane_size->surface_pitch = si_tex_0->surface.u.gfx9.surf_pitch; + plane_size->surface_aligned_height = surfaces[0]->height; - case PIPE_FORMAT_A2R10G10B10_UNORM: - case PIPE_FORMAT_R10G10B10A2_UNORM: - case PIPE_FORMAT_A2B10G10R10_UNORM: - case PIPE_FORMAT_B10G10R10A2_UNORM: - default: - SIVPE_ERR("Un-supported format %d\n", format); + /* YUV 2nd plane ret setting */ + if (util_format_get_num_planes(format) == 2) { + plane_size->chroma_size.x = 0; + plane_size->chroma_size.y = 0; + plane_size->chroma_size.width = surfaces[1]->width; + plane_size->chroma_size.height = surfaces[1]->height; + plane_size->chroma_pitch = si_tex_1->surface.u.gfx9.surf_pitch; + plane_size->chrome_aligned_height = surfaces[1]->height; } + + /* Color space setting */ + surface_info->format = si_vpe_pipe_map_to_vpe_format(format); + si_vpe_set_color_space(process_properties, &surface_info->cs, format, which_surface); return VPE_STATUS_OK; } @@ -541,7 +548,8 @@ si_vpe_set_surface_info(struct vpe_video_processor *vpeproc, assert(surface_info); /* Set up surface pitch, plane address, color space */ - si_vpe_set_plane_info(vpeproc, process_properties, surfaces, which_surface, surface_info); + if (VPE_STATUS_OK != si_vpe_set_plane_info(vpeproc, process_properties, surfaces, which_surface, surface_info)) + return VPE_STATUS_NOT_SUPPORTED; struct si_texture *tex = (struct si_texture *)surfaces[0]->texture; surface_info->swizzle = tex->surface.u.gfx9.swizzle_mode; @@ -562,11 +570,17 @@ si_vpe_set_surface_info(struct vpe_video_processor *vpeproc, return VPE_STATUS_OK; } -static enum vpe_status -si_vpe_set_stream(const struct pipe_vpp_desc *process_properties, - struct vpe_stream *stream) +static void +si_vpe_set_stream_in_param(struct vpe_video_processor *vpeproc, + const struct pipe_vpp_desc *process_properties, + struct vpe_stream *stream) { + struct vpe *vpe_handle = vpeproc->vpe_handle; struct vpe_scaling_info *scaling_info = &stream->scaling_info; + struct vpe_blend_info *blend_info = &stream->blend_info; + struct vpe_color_adjust *color_adj = &stream->color_adj; + + /* Init: scaling_info */ scaling_info->src_rect.x = process_properties->src_region.x0; scaling_info->src_rect.y = process_properties->src_region.y0; scaling_info->src_rect.width = process_properties->src_region.x1 - process_properties->src_region.x0; @@ -575,39 +589,30 @@ si_vpe_set_stream(const struct pipe_vpp_desc *process_properties, scaling_info->dst_rect.y = process_properties->dst_region.y0; scaling_info->dst_rect.width = process_properties->dst_region.x1 - process_properties->dst_region.x0; scaling_info->dst_rect.height = process_properties->dst_region.y1 - process_properties->dst_region.y0; - /* Programmable 1 to 8 taps of vertical polyphase filter, and - * programmable 1, 2, 4, 6, 8 taps of horizontal polyphase filter. - */ - scaling_info->taps.v_taps = 4; - scaling_info->taps.h_taps = 4; + scaling_info->taps.v_taps = 0; + scaling_info->taps.h_taps = 0; scaling_info->taps.v_taps_c = 2; scaling_info->taps.h_taps_c = 2; - /* Blending is not supported for now */ - struct vpe_blend_info *blend_info = &stream->blend_info; + vpe_get_optimal_num_of_taps(vpe_handle, scaling_info); + blend_info->blending = false; blend_info->pre_multiplied_alpha = false; - blend_info->global_alpha = false; - blend_info->global_alpha_value = 0.0; + blend_info->global_alpha = blend_info->blending; + blend_info->global_alpha_value = 1.0; + /* Global Alpha for Background ? */ if (process_properties->blend.mode == PIPE_VIDEO_VPP_BLEND_MODE_GLOBAL_ALPHA) { - blend_info->global_alpha = true; + //blend_info->global_alpha = true; blend_info->global_alpha_value = process_properties->blend.global_alpha; } - /* TODO: do ProcAmp in next stage */ - struct vpe_color_adjust *color_adj = &stream->color_adj; + /* TO-DO: do ProcAmp in next stage */ color_adj->brightness = 0.0; color_adj->contrast = 1.0; color_adj->hue = 0.0; color_adj->saturation = 1.0; - /* TODO: Tone Mapping */ - //struct vpe_tonemap_params *tm_params = &stream->tm_params; - - - stream->horizontal_mirror = false; - stream->vertical_mirror = false; switch (process_properties->orientation & 0xF) { case PIPE_VIDEO_VPP_ROTATION_90: stream->rotation = VPE_ROTATION_ANGLE_90; @@ -622,35 +627,58 @@ si_vpe_set_stream(const struct pipe_vpp_desc *process_properties, stream->rotation = VPE_ROTATION_ANGLE_0; break; } - if (process_properties->orientation & PIPE_VIDEO_VPP_FLIP_HORIZONTAL) { - stream->horizontal_mirror = true; + + stream->horizontal_mirror = (process_properties->orientation & PIPE_VIDEO_VPP_FLIP_HORIZONTAL) ? true : false; + stream->vertical_mirror = (process_properties->orientation & PIPE_VIDEO_VPP_FLIP_VERTICAL) ? true : false; + + stream->enable_luma_key = false; + stream->lower_luma_bound = 0.5; + stream->upper_luma_bound = 0.5; + + stream->flags.reserved = 0; + stream->flags.geometric_scaling = 0; + stream->flags.hdr_metadata = 0; + + /* TO-DO: support HDR10 Metadata */ + si_vpe_load_default_primaries(&stream->hdr_metadata, stream->surface_info.cs.primaries); +} + +static void +si_vpe_set_stream_out_param(struct vpe_video_processor *vpeproc, + const struct pipe_vpp_desc *process_properties, + struct vpe_build_param *build_param) +{ + uint32_t background_color = process_properties->background_color; + + build_param->target_rect.x = process_properties->dst_region.x0; + build_param->target_rect.y = process_properties->dst_region.y0; + build_param->target_rect.width = process_properties->dst_region.x1 - process_properties->dst_region.x0; + build_param->target_rect.height = process_properties->dst_region.y1 - process_properties->dst_region.y0; + + build_param->bg_color.is_ycbcr = false; + build_param->bg_color.rgba.r = 0; + build_param->bg_color.rgba.g = 0; + build_param->bg_color.rgba.b = 0; + build_param->bg_color.rgba.a = 0; + + /* Studio color range not start from 0 */ + if (!(background_color & 0xFFFFFF) && (build_param->dst_surface.cs.range == VPE_COLOR_RANGE_STUDIO)) { + build_param->bg_color.rgba.a = (float)((background_color & 0xFF000000) >> 24) / 255.0; + build_param->bg_color.rgba.r = 0.0628; + build_param->bg_color.rgba.g = 0.0628; + build_param->bg_color.rgba.b = 0.0628; + } else if (process_properties->background_color) { + build_param->bg_color.rgba.a = (float)((background_color & 0xFF000000) >> 24) / 255.0; + build_param->bg_color.rgba.r = (float)((background_color & 0x00FF0000) >> 16) / 255.0; + build_param->bg_color.rgba.g = (float)((background_color & 0x0000FF00) >> 8) / 255.0; + build_param->bg_color.rgba.b = (float)(background_color & 0x000000FF) / 255.0; } - if (process_properties->orientation & PIPE_VIDEO_VPP_FLIP_VERTICAL) - stream->vertical_mirror = true; - stream->enable_luma_key = false; - stream->lower_luma_bound = 0.5; - stream->upper_luma_bound = 0.5; + build_param->alpha_mode = VPE_ALPHA_OPAQUE; + build_param->flags.hdr_metadata = 1; - stream->flags.hdr_metadata = 0; - stream->flags.reserved = 0; - - /* TODO: hdr_metadata support in next stage */ - stream->hdr_metadata.redX = 1; - stream->hdr_metadata.redY = 1; - stream->hdr_metadata.greenX = 1; - stream->hdr_metadata.greenY = 1; - stream->hdr_metadata.blueX = 1; - stream->hdr_metadata.blueY = 1; - stream->hdr_metadata.whiteX = 1; - stream->hdr_metadata.whiteY = 1; - - stream->hdr_metadata.min_mastering = 1; - stream->hdr_metadata.max_mastering = 1; - stream->hdr_metadata.max_content = 1; - stream->hdr_metadata.avg_content = 1; - - return VPE_STATUS_OK; + /* TODO: Should support HDR10 Metadata */ + si_vpe_load_default_primaries(&build_param->hdr_metadata, build_param->dst_surface.cs.primaries); } static void @@ -724,6 +752,180 @@ si_vpe_cs_add_surface_buffer(struct vpe_video_processor *vpeproc, } } +static void +si_vpe_show_process_settings(struct vpe_video_processor *vpeproc, + struct vpe_build_param *build_param) +{ + if (vpeproc->log_level >= SI_VPE_LOG_LEVEL_DEBUG) { + SIVPE_PRINT("src surface format(%d) rect (%d, %d, %d, %d)\n", + build_param->streams[0].surface_info.format, + build_param->streams[0].surface_info.plane_size.surface_size.x, + build_param->streams[0].surface_info.plane_size.surface_size.y, + build_param->streams[0].surface_info.plane_size.surface_size.width, + build_param->streams[0].surface_info.plane_size.surface_size.height); + + SIVPE_PRINT("src surface Cositing(%s), primaries(%s), tf(%s), range(%s)\n", + si_vpe_get_cositing_str(build_param->streams[0].surface_info.cs.cositing), + si_vpe_get_primarie_str(build_param->streams[0].surface_info.cs.primaries), + si_vpe_get_tf_str(build_param->streams[0].surface_info.cs.tf), + (build_param->streams[0].surface_info.cs.range == VPE_COLOR_RANGE_FULL)?"FULL":"STUDIO"); + + SIVPE_PRINT("dst surface format(%d) rect (%d, %d, %d, %d)\n", + build_param->dst_surface.format, + build_param->dst_surface.plane_size.surface_size.x, + build_param->dst_surface.plane_size.surface_size.y, + build_param->dst_surface.plane_size.surface_size.width, + build_param->dst_surface.plane_size.surface_size.height); + + SIVPE_PRINT("dst surface Cositing(%s), primaries(%s), tf(%s), range(%s)\n", + si_vpe_get_cositing_str(build_param->dst_surface.cs.cositing), + si_vpe_get_primarie_str(build_param->dst_surface.cs.primaries), + si_vpe_get_tf_str(build_param->dst_surface.cs.tf), + (build_param->dst_surface.cs.range == VPE_COLOR_RANGE_FULL)?"FULL":"STUDIO"); + + SIVPE_PRINT("Source surface pitch(%d), chroma pitch(%d), dst-surface pitch(%d), chroma pitch(%d)\n", + build_param->streams[0].surface_info.plane_size.surface_pitch, + build_param->streams[0].surface_info.plane_size.chroma_pitch, + build_param->dst_surface.plane_size.surface_pitch, + build_param->dst_surface.plane_size.chroma_pitch); + + SIVPE_PRINT("background color RGBA(%0.3f, %0.3f, %0.3f, %0.3f)\n", + build_param->bg_color.rgba.r, + build_param->bg_color.rgba.g, + build_param->bg_color.rgba.b, + build_param->bg_color.rgba.a); + + SIVPE_PRINT("target_rect(%d, %d, %d, %d)\n", + build_param->target_rect.x, + build_param->target_rect.y, + build_param->target_rect.width, + build_param->target_rect.height); + + SIVPE_PRINT("rotation(%d) horizontal_mirror(%d) vertical_mirror(%d)\n", + build_param->streams[0].rotation, + build_param->streams[0].horizontal_mirror, + build_param->streams[0].vertical_mirror); + + SIVPE_PRINT("scaling_src_rect(%d, %d, %d, %d)\n", + build_param->streams[0].scaling_info.src_rect.x, + build_param->streams[0].scaling_info.src_rect.y, + build_param->streams[0].scaling_info.src_rect.width, + build_param->streams[0].scaling_info.src_rect.height); + + SIVPE_PRINT("scaling_dst_rect(%d, %d, %d, %d)\n", + build_param->streams[0].scaling_info.dst_rect.x, + build_param->streams[0].scaling_info.dst_rect.y, + build_param->streams[0].scaling_info.dst_rect.width, + build_param->streams[0].scaling_info.dst_rect.height); + + SIVPE_PRINT("scaling_taps h_taps(%d) v_taps(%d) h_taps_c(%d) v_taps_c(%d)\n", + build_param->streams[0].scaling_info.taps.h_taps, + build_param->streams[0].scaling_info.taps.v_taps, + build_param->streams[0].scaling_info.taps.h_taps_c, + build_param->streams[0].scaling_info.taps.v_taps_c); + + SIVPE_PRINT("blend global_alpha(%d): %0.3f\n", + build_param->streams[0].blend_info.global_alpha, + build_param->streams[0].blend_info.global_alpha_value); + + SIVPE_PRINT("ToneMapping shaper_tf(%d) lut_out_tf(%d) lut_in_gamut(%d) lut_out_gamut(%d)\n", + build_param->streams[0].tm_params.shaper_tf, + build_param->streams[0].tm_params.lut_out_tf, + build_param->streams[0].tm_params.lut_in_gamut, + build_param->streams[0].tm_params.lut_out_gamut); + } +} + +static int +si_vpe_processor_is_process_supported(struct pipe_video_codec *codec, + struct pipe_video_buffer *input_texture, + const struct pipe_vpp_desc *process_properties) +{ + enum vpe_status result = VPE_STATUS_OK; + struct vpe_video_processor *vpeproc = (struct vpe_video_processor *)codec; + struct vpe *vpe_handle = vpeproc->vpe_handle; + struct vpe_build_param *build_param = vpeproc->vpe_build_param; + struct pipe_surface **src_surfaces; + struct vpe_bufs_req bufs_required; + + assert(codec); + assert(process_properties); + assert(vpeproc->dst_surfaces); + + /* Get input surface */ + src_surfaces = input_texture->get_surfaces(input_texture); + if (!src_surfaces || !src_surfaces[0]) { + SIVPE_ERR("Get source surface failed\n"); + return 1; + } + vpeproc->src_surfaces = src_surfaces; + + /* Mesa only sends one input frame at one time (one stream pipe). + * If there is more than one pipe need to be handled, it have to re-locate memory. + * But now we only focuse on handling one stream pipe. + */ + build_param->num_streams = 1; + memset(build_param->streams, 0, sizeof(struct vpe_stream) * build_param->num_streams); + + /* Init input surface setting */ + result = si_vpe_set_surface_info(vpeproc, + process_properties, + vpeproc->src_surfaces, + USE_SRC_SURFACE, + &build_param->streams[0].surface_info); + if (VPE_STATUS_OK != result) { + SIVPE_ERR("Set Src surface failed with result: %d\n", result); + return 1; + } + + /* Init input stream setting */ + si_vpe_set_stream_in_param( + vpeproc, + process_properties, + &build_param->streams[0]); + + /* Init output surface setting */ + result = si_vpe_set_surface_info(vpeproc, + process_properties, + vpeproc->dst_surfaces, + USE_DST_SURFACE, + &build_param->dst_surface); + if (VPE_STATUS_OK != result) { + SIVPE_ERR("Set Dst surface failed with result: %d\n", result); + return 1; + } + + /* Init output stream setting */ + si_vpe_set_stream_out_param( + vpeproc, + process_properties, + build_param); + + /* Shows details of current processing. */ + si_vpe_show_process_settings(vpeproc, build_param); + + if(vpe_handle->level == VPE_IP_LEVEL_1_1) { + build_param->num_instances = 2; + build_param->collaboration_mode = true; + } else { + build_param->num_instances = 1; + build_param->collaboration_mode = false; + } + + result = vpe_check_support(vpe_handle, build_param, &bufs_required); + if (VPE_STATUS_OK != result) { + SIVPE_ERR("Check support failed with result: %d\n", result); + return 1; + } + + if (VPE_EMBBUF_SIZE < bufs_required.emb_buf_size) { + SIVPE_ERR("Required Buffer size is out of allocated: %" PRIu64 "\n", bufs_required.emb_buf_size); + return 1; + } + + return 0; +} + static int si_vpe_processor_process_frame(struct pipe_video_codec *codec, struct pipe_video_buffer *input_texture, @@ -733,121 +935,23 @@ si_vpe_processor_process_frame(struct pipe_video_codec *codec, struct vpe_video_processor *vpeproc = (struct vpe_video_processor *)codec; struct vpe *vpe_handle = vpeproc->vpe_handle; struct vpe_build_param *build_param = vpeproc->vpe_build_param; - struct pipe_surface **src_surfaces; - struct vpe_bufs_req bufs_required; struct rvid_buffer *emb_buf; uint64_t *vpe_ptr; - assert(codec); - assert(process_properties); - assert(vpeproc->dst_surfaces); - - src_surfaces = input_texture->get_surfaces(input_texture); - if (!src_surfaces || !src_surfaces[0]) { - SIVPE_ERR("Get source surface failed\n"); - return 1; - } - vpeproc->src_surfaces = src_surfaces; - - /* Following setting is from si_vpe_set_build_param()*/ - /* VPE 1.0 only support one input */ - build_param->num_streams = 1; - if (build_param->num_streams > VPE_STREAM_MAX_NUM) { - SIVPE_ERR("Can only suppport %d stream(s) now\n", VPE_STREAM_MAX_NUM); - return 1; - } - - if (!build_param->streams) { - SIVPE_ERR("Streams structure is not allocated\n"); - return 1; - } - - if (si_vpe_set_surface_info(vpeproc, - process_properties, - vpeproc->src_surfaces, - USE_SRC_SURFACE, - &build_param->streams[0].surface_info) != VPE_STATUS_OK) + /* Check if the required options are supported */ + if(si_vpe_processor_is_process_supported(codec, input_texture, process_properties)) return 1; - si_vpe_set_stream(process_properties, &build_param->streams[0]); - - if (si_vpe_set_surface_info(vpeproc, - process_properties, - vpeproc->dst_surfaces, - USE_DST_SURFACE, - &build_param->dst_surface) != VPE_STATUS_OK) - return 1; - - if (process_properties->background_color) { - build_param->target_rect.x = 0; - build_param->target_rect.y = 0; - build_param->target_rect.width = vpeproc->dst_surfaces[0]->width; - build_param->target_rect.height = vpeproc->dst_surfaces[0]->height; - } else { - build_param->target_rect.x = process_properties->dst_region.x0; - build_param->target_rect.y = process_properties->dst_region.y0; - build_param->target_rect.width = process_properties->dst_region.x1 - process_properties->dst_region.x0; - build_param->target_rect.height = process_properties->dst_region.y1 - process_properties->dst_region.y0; - } - - /* TODO: background color is not specified in pipe_vpp_desc structure. - * Need to add this filed in pipe_vpp_desc. - */ - build_param->bg_color.is_ycbcr = false; - - if (!(process_properties->background_color & 0xFFFFFF) && - (build_param->dst_surface.cs.range == VPE_COLOR_RANGE_STUDIO)) { - build_param->bg_color.rgba.a = - (float)((process_properties->background_color & 0xFF000000) >> 24) / 255.0; - build_param->bg_color.rgba.r = 0.0628; - build_param->bg_color.rgba.g = 0.0628; - build_param->bg_color.rgba.b = 0.0628; - } else if (process_properties->background_color) { - build_param->bg_color.rgba.a = - (float)((process_properties->background_color & 0xFF000000) >> 24) / 255.0; - build_param->bg_color.rgba.r = - (float)((process_properties->background_color & 0x00FF0000) >> 16) / 255.0; - build_param->bg_color.rgba.g = - (float)((process_properties->background_color & 0x0000FF00) >> 8) / 255.0; - build_param->bg_color.rgba.b = - (float)(process_properties->background_color & 0x000000FF) / 255.0; - } else { - build_param->bg_color.rgba.r = 0; - build_param->bg_color.rgba.g = 0; - build_param->bg_color.rgba.b = 0; - build_param->bg_color.rgba.a = 0; - } - - build_param->alpha_mode = VPE_ALPHA_OPAQUE; - - build_param->flags.hdr_metadata = 0; - build_param->flags.reserved = 1; - - /* TODO: hdr_metadata support in next stage */ - build_param->hdr_metadata.redX = 1; - build_param->hdr_metadata.redY = 1; - build_param->hdr_metadata.greenX = 1; - build_param->hdr_metadata.greenY = 1; - build_param->hdr_metadata.blueX = 1; - build_param->hdr_metadata.blueY = 1; - build_param->hdr_metadata.whiteX = 1; - build_param->hdr_metadata.whiteY = 1; - - build_param->hdr_metadata.min_mastering = 1; - build_param->hdr_metadata.max_mastering = 1; - build_param->hdr_metadata.max_content = 1; - build_param->hdr_metadata.avg_content = 1; - - - /* Setup CmdBuf and EmbBuf address adn size information */ + /* Init CmdBuf address and size information */ vpe_ptr = (uint64_t *)vpeproc->cs.current.buf; vpeproc->vpe_build_bufs->cmd_buf.cpu_va = (uintptr_t)vpe_ptr; vpeproc->vpe_build_bufs->cmd_buf.gpu_va = 0; vpeproc->vpe_build_bufs->cmd_buf.size = vpeproc->cs.current.max_dw; vpeproc->vpe_build_bufs->cmd_buf.tmz = false; - /* Map EmbBuf for CPU access */ + /* Init EmbBuf address and size information */ emb_buf = &vpeproc->emb_buffers[vpeproc->cur_buf]; + /* Map EmbBuf for CPU access */ vpe_ptr = (uint64_t *)vpeproc->ws->buffer_map(vpeproc->ws, emb_buf->res->buf, &vpeproc->cs, @@ -861,111 +965,13 @@ si_vpe_processor_process_frame(struct pipe_video_codec *codec, vpeproc->vpe_build_bufs->emb_buf.size = VPE_EMBBUF_SIZE; vpeproc->vpe_build_bufs->emb_buf.tmz = false; - - if (vpeproc->log_level >= SI_VPE_LOG_LEVEL_DEBUG) { - SIVPE_DBG(vpeproc->log_level, "src surface format(%d) rect (%d, %d, %d, %d)\n", - build_param->streams[0].surface_info.format, - build_param->streams[0].surface_info.plane_size.surface_size.x, - build_param->streams[0].surface_info.plane_size.surface_size.y, - build_param->streams[0].surface_info.plane_size.surface_size.width, - build_param->streams[0].surface_info.plane_size.surface_size.height); - - SIVPE_DBG(vpeproc->log_level, "src surface Cositing(%s), primaries(%s), tf(%s), range(%s)\n", - si_vpe_get_cositing_str(build_param->streams[0].surface_info.cs.cositing), - si_vpe_get_primarie_str(build_param->streams[0].surface_info.cs.primaries), - si_vpe_get_tf_str(build_param->streams[0].surface_info.cs.tf), - (build_param->streams[0].surface_info.cs.range == VPE_COLOR_RANGE_FULL)?"FULL":"STUDIO"); - - SIVPE_DBG(vpeproc->log_level, "dst surface format(%d) rect (%d, %d, %d, %d)\n", - build_param->dst_surface.format, - build_param->dst_surface.plane_size.surface_size.x, - build_param->dst_surface.plane_size.surface_size.y, - build_param->dst_surface.plane_size.surface_size.width, - build_param->dst_surface.plane_size.surface_size.height); - - SIVPE_DBG(vpeproc->log_level, "dst surface Cositing(%s), primaries(%s), tf(%s), range(%s)\n", - si_vpe_get_cositing_str(build_param->dst_surface.cs.cositing), - si_vpe_get_primarie_str(build_param->dst_surface.cs.primaries), - si_vpe_get_tf_str(build_param->dst_surface.cs.tf), - (build_param->dst_surface.cs.range == VPE_COLOR_RANGE_FULL)?"FULL":"STUDIO"); - - SIVPE_DBG(vpeproc->log_level, "Source surface pitch(%d), chroma pitch(%d), dst-surface pitch(%d), chroma pitch(%d)\n", - build_param->streams[0].surface_info.plane_size.surface_pitch, - build_param->streams[0].surface_info.plane_size.chroma_pitch, - build_param->dst_surface.plane_size.surface_pitch, - build_param->dst_surface.plane_size.chroma_pitch); - - SIVPE_DBG(vpeproc->log_level, "background color RGBA(%0.3f, %0.3f, %0.3f, %0.3f)\n", - build_param->bg_color.rgba.r, - build_param->bg_color.rgba.g, - build_param->bg_color.rgba.b, - build_param->bg_color.rgba.a); - - SIVPE_DBG(vpeproc->log_level, "target_rect(%d, %d, %d, %d)\n", - build_param->target_rect.x, - build_param->target_rect.y, - build_param->target_rect.width, - build_param->target_rect.height); - - SIVPE_DBG(vpeproc->log_level, "rotation(%d) horizontal_mirror(%d) vertical_mirror(%d)\n", - build_param->streams[0].rotation, - build_param->streams[0].horizontal_mirror, - build_param->streams[0].vertical_mirror); - - SIVPE_DBG(vpeproc->log_level, "scaling_src_rect(%d, %d, %d, %d)\n", - build_param->streams[0].scaling_info.src_rect.x, - build_param->streams[0].scaling_info.src_rect.y, - build_param->streams[0].scaling_info.src_rect.width, - build_param->streams[0].scaling_info.src_rect.height); - - SIVPE_DBG(vpeproc->log_level, "scaling_dst_rect(%d, %d, %d, %d)\n", - build_param->streams[0].scaling_info.dst_rect.x, - build_param->streams[0].scaling_info.dst_rect.y, - build_param->streams[0].scaling_info.dst_rect.width, - build_param->streams[0].scaling_info.dst_rect.height); - - SIVPE_DBG(vpeproc->log_level, "scaling_taps h_taps(%d) v_taps(%d) h_taps_c(%d) v_taps_c(%d)\n", - build_param->streams[0].scaling_info.taps.h_taps, - build_param->streams[0].scaling_info.taps.v_taps, - build_param->streams[0].scaling_info.taps.h_taps_c, - build_param->streams[0].scaling_info.taps.v_taps_c); - - SIVPE_DBG(vpeproc->log_level, "blend global_alpha(%d): %0.3f\n", - build_param->streams[0].blend_info.global_alpha, - build_param->streams[0].blend_info.global_alpha_value); - - SIVPE_DBG(vpeproc->log_level, "ToneMapping shaper_tf(%d) lut_out_tf(%d) lut_in_gamut(%d) lut_out_gamut(%d)\n", - build_param->streams[0].tm_params.shaper_tf, - build_param->streams[0].tm_params.lut_out_tf, - build_param->streams[0].tm_params.lut_in_gamut, - build_param->streams[0].tm_params.lut_out_gamut); - - //SIVPE_DBG(vpeproc->log_level, "ToneMapping update_3dlut(%d) enable_3dlut(%d)\n", - // build_param->streams[0].tm_params.update_3dlut, - // build_param->streams[0].tm_params.enable_3dlut); - } - - if(vpe_handle->level == VPE_IP_LEVEL_1_1) { - build_param->num_instances = 2; - build_param->collaboration_mode = true; - } else { - build_param->num_instances = 1; - build_param->collaboration_mode = false; - } - - result = vpe_check_support(vpe_handle, build_param, &bufs_required); - if (VPE_STATUS_OK != result) { - SIVPE_ERR("Check support failed with result: %d\n", result); - goto fail; - } - result = vpe_build_commands(vpe_handle, build_param, vpeproc->vpe_build_bufs); if (VPE_STATUS_OK != result) { SIVPE_ERR("Build commands failed with result: %d\n", result); goto fail; } - /* unmap the emb_buf */ + /* Un-map Emb_buf */ vpeproc->ws->buffer_unmap(vpeproc->ws, emb_buf->res->buf); /* Check buffer size */ @@ -977,24 +983,24 @@ si_vpe_processor_process_frame(struct pipe_video_codec *codec, SIVPE_ERR("Embbuf size wrong\n"); goto fail; } - SIVPE_INFO(vpeproc->log_level, "Used buf size: %" PRIu64 ", %" PRIu64 "\n", + SIVPE_DBG(vpeproc->log_level, "Used buf size: %" PRIu64 ", %" PRIu64 "\n", vpeproc->vpe_build_bufs->cmd_buf.size, vpeproc->vpe_build_bufs->emb_buf.size); - /* Have to tell Command Submission context the command length wrote by libvpe */ + /* Have to tell Command Submission context the command length */ vpeproc->cs.current.cdw += (vpeproc->vpe_build_bufs->cmd_buf.size / 4); /* Add embbuf into bo_handle list */ vpeproc->ws->cs_add_buffer(&vpeproc->cs, emb_buf->res->buf, RADEON_USAGE_READ | RADEON_USAGE_SYNCHRONIZED, RADEON_DOMAIN_GTT); + /* Add surface buffers into bo_handle list */ si_vpe_cs_add_surface_buffer(vpeproc, vpeproc->src_surfaces, RADEON_USAGE_READ); si_vpe_cs_add_surface_buffer(vpeproc, vpeproc->dst_surfaces, RADEON_USAGE_WRITE); - SIVPE_DBG(vpeproc->log_level, "Success\n"); return 0; fail: vpeproc->ws->buffer_unmap(vpeproc->ws, emb_buf->res->buf); - SIVPE_ERR("Failed\n"); + SIVPE_ERR("Process frame failed\n"); return 1; } @@ -1010,23 +1016,18 @@ si_vpe_processor_end_frame(struct pipe_video_codec *codec, vpeproc->ws->cs_flush(&vpeproc->cs, picture->flush_flags, &process_fence); next_buffer(vpeproc); - if (picture->fence && process_fence) { + if (picture->fence && process_fence) *picture->fence = process_fence; - SIVPE_INFO(vpeproc->log_level, "Assign process fence\n"); - } else + else SIVPE_WARN(vpeproc->log_level, "Fence may have problem!\n"); - SIVPE_INFO(vpeproc->log_level, "Success\n"); return 0; } static void si_vpe_processor_flush(struct pipe_video_codec *codec) { - //struct vpe_video_processor *vpeproc = (struct vpe_video_processor *)codec; - //assert(codec); - - //SIVPE_DBG(vpeproc->log_level, "Success\n"); + /* Commands will be flushed when end_frame() is called */ return; } @@ -1037,12 +1038,10 @@ static int si_vpe_processor_fence_wait(struct pipe_video_codec *codec, struct vpe_video_processor *vpeproc = (struct vpe_video_processor *)codec; assert(codec); - SIVPE_INFO(vpeproc->log_level, "Wait processor fence\n"); if (!vpeproc->ws->fence_wait(vpeproc->ws, fence, timeout)) { SIVPE_DBG(vpeproc->log_level, "Wait processor fence fail\n"); return 0; } - SIVPE_INFO(vpeproc->log_level, "Wait processor fence success\n"); return 1; } @@ -1053,7 +1052,6 @@ si_vpe_create_processor(struct pipe_context *context, const struct pipe_video_co struct radeon_winsys *ws = sctx->ws; struct vpe_video_processor *vpeproc; struct vpe_init_data *init_data; - const char *str = getenv("AMDGPU_SIVPE_LOG_LEVEL"); unsigned int i; vpeproc = CALLOC_STRUCT(vpe_video_processor); @@ -1062,11 +1060,10 @@ si_vpe_create_processor(struct pipe_context *context, const struct pipe_video_co return NULL; } - /* get SI_VPE debug log level */ - if (str == NULL) - vpeproc->log_level = SI_VPE_LOG_LEVEL_DEFAULT; - else - vpeproc->log_level = atoi(str); + /* SI_VPE debug log level + * Default level(0) only shows error messages + */ + vpeproc->log_level = (uint8_t)debug_get_num_option("AMDGPU_SIVPE_LOG_LEVEL", SI_VPE_LOG_LEVEL_DEFAULT); vpeproc->base = *templ; vpeproc->base.context = context; @@ -1140,7 +1137,9 @@ si_vpe_create_processor(struct pipe_context *context, const struct pipe_video_co goto fail; } - /* Pre-allocate the streams */ + /* Only one input frame is passed in for processing at a time (one stream pipe). + * Only needs to handle one stream processing. + */ vpeproc->vpe_build_param->streams = (struct vpe_stream *)CALLOC(VPE_STREAM_MAX_NUM, sizeof(struct vpe_stream)); if (!vpeproc->vpe_build_param->streams) { SIVPE_ERR("Allocate streams sturcture failed\n");