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radv/meta: convert DGC pipeline layout to vk_meta

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DGC pipelines aren't using the vk_meta helper because that would
require to compute a separate key and that's useless.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32744>
This commit is contained in:
Samuel Pitoiset
2024-12-19 17:55:02 +01:00
committed by Marge Bot
parent 27adadbe63
commit 1a34e799bd
5 changed files with 45 additions and 72 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/amd/vulkan/meta/radv_meta.c
-7
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@@ -503,12 +503,6 @@ radv_device_init_meta(struct radv_device *device)
if (result != VK_SUCCESS)
return result;
if (device->vk.enabled_features.deviceGeneratedCommands) {
result = radv_device_init_dgc_prepare_state(device, on_demand);
if (result != VK_SUCCESS)
return result;
}
if (device->vk.enabled_extensions.KHR_acceleration_structure) {
if (device->vk.enabled_features.nullDescriptor) {
result = radv_device_init_null_accel_struct(device);
@@ -536,7 +530,6 @@ radv_device_init_meta(struct radv_device *device)
void
radv_device_finish_meta(struct radv_device *device)
{
radv_device_finish_dgc_prepare_state(device);
radv_device_finish_meta_etc_decode_state(device);
radv_device_finish_meta_astc_decode_state(device);
radv_device_finish_accel_struct_build_state(device);
src/amd/vulkan/meta/radv_meta.h
-3
View File
@@ -142,9 +142,6 @@ void radv_device_finish_meta_etc_decode_state(struct radv_device *device);
VkResult radv_device_init_meta_astc_decode_state(struct radv_device *device, bool on_demand);
void radv_device_finish_meta_astc_decode_state(struct radv_device *device);
VkResult radv_device_init_dgc_prepare_state(struct radv_device *device, bool on_demand);
void radv_device_finish_dgc_prepare_state(struct radv_device *device);
void radv_meta_save(struct radv_meta_saved_state *saved_state, struct radv_cmd_buffer *cmd_buffer, uint32_t flags);
void radv_meta_restore(const struct radv_meta_saved_state *state, struct radv_cmd_buffer *cmd_buffer);
src/amd/vulkan/radv_device.h
-5
View File
@@ -281,11 +281,6 @@ struct radv_meta_state {
struct vk_texcompress_astc_state *astc_decode;
struct {
VkDescriptorSetLayout ds_layout;
VkPipelineLayout p_layout;
} dgc_prepare;
struct vk_meta_device device;
};
src/amd/vulkan/radv_dgc.c
+44 -57
View File
@@ -2667,73 +2667,60 @@ build_dgc_prepare_shader(struct radv_device *dev, struct radv_indirect_command_l
return b.shader;
}
static VkResult
create_pipeline_layout(struct radv_device *device)
{
VkResult result = VK_SUCCESS;
if (!device->meta_state.dgc_prepare.ds_layout) {
const VkDescriptorSetLayoutBinding binding = {
.binding = 0,
.descriptorType = VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER,
.descriptorCount = 1,
.stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
};
result = radv_meta_create_descriptor_set_layout(device, 1, &binding, &device->meta_state.dgc_prepare.ds_layout);
if (result != VK_SUCCESS)
return result;
}
if (!device->meta_state.dgc_prepare.p_layout) {
const VkPushConstantRange pc_range = {
.stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
.size = sizeof(struct radv_dgc_params),
};
result = radv_meta_create_pipeline_layout(device, &device->meta_state.dgc_prepare.ds_layout, 1, &pc_range,
&device->meta_state.dgc_prepare.p_layout);
}
return result;
}
void
radv_device_finish_dgc_prepare_state(struct radv_device *device)
{
radv_DestroyPipelineLayout(radv_device_to_handle(device), device->meta_state.dgc_prepare.p_layout,
&device->meta_state.alloc);
device->vk.dispatch_table.DestroyDescriptorSetLayout(
radv_device_to_handle(device), device->meta_state.dgc_prepare.ds_layout, &device->meta_state.alloc);
}
VkResult
radv_device_init_dgc_prepare_state(struct radv_device *device, bool on_demand)
{
if (on_demand)
return VK_SUCCESS;
return create_pipeline_layout(device);
}
static VkResult
radv_create_dgc_pipeline(struct radv_device *device, struct radv_indirect_command_layout *layout)
{
struct radv_meta_state *state = &device->meta_state;
const char *key_data = "radv-dgc-layout";
VkResult result;
mtx_lock(&state->mtx);
result = create_pipeline_layout(device);
mtx_unlock(&state->mtx);
const VkDescriptorSetLayoutBinding binding = {
.binding = 0,
.descriptorType = VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER,
.descriptorCount = 1,
.stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
};
const VkDescriptorSetLayoutCreateInfo desc_info = {
.sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO,
.flags = VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT,
.bindingCount = 1,
.pBindings = &binding,
};
const VkPushConstantRange pc_range = {
.stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
.size = sizeof(struct radv_dgc_params),
};
result = vk_meta_get_pipeline_layout(&device->vk, &device->meta_state.device, &desc_info, &pc_range, key_data,
strlen(key_data), &layout->pipeline_layout);
if (result != VK_SUCCESS)
return result;
nir_shader *cs = build_dgc_prepare_shader(device, layout);
result = radv_meta_create_compute_pipeline(device, cs, device->meta_state.dgc_prepare.p_layout, &layout->pipeline);
ralloc_free(cs);
const VkPipelineShaderStageCreateInfo stage_info = {
.sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
.stage = VK_SHADER_STAGE_COMPUTE_BIT,
.module = vk_shader_module_handle_from_nir(cs),
.pName = "main",
.pSpecializationInfo = NULL,
};
const VkComputePipelineCreateInfo pipeline_info = {
.sType = VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO,
.stage = stage_info,
.flags = 0,
.layout = layout->pipeline_layout,
};
/* DGC pipelines don't go through the vk_meta cache because that would require to compute a
* separate key but they are cached on-disk when possible.
*/
result = radv_CreateComputePipelines(vk_device_to_handle(&device->vk), device->meta_state.device.pipeline_cache, 1,
&pipeline_info, NULL, &layout->pipeline);
ralloc_free(cs);
return result;
}
@@ -3098,11 +3085,11 @@ radv_prepare_dgc(struct radv_cmd_buffer *cmd_buffer, const VkGeneratedCommandsIn
radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer), VK_PIPELINE_BIND_POINT_COMPUTE, layout->pipeline);
vk_common_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), device->meta_state.dgc_prepare.p_layout,
vk_common_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), layout->pipeline_layout,
VK_SHADER_STAGE_COMPUTE_BIT, 0, sizeof(params), &params);
radv_meta_push_descriptor_set(
cmd_buffer, VK_PIPELINE_BIND_POINT_COMPUTE, device->meta_state.dgc_prepare.p_layout, 0, 1,
cmd_buffer, VK_PIPELINE_BIND_POINT_COMPUTE, layout->pipeline_layout, 0, 1,
(VkWriteDescriptorSet[]){{.sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
.dstBinding = 0,
.dstArrayElement = 0,
src/amd/vulkan/radv_dgc.h
+1
View File
@@ -24,6 +24,7 @@ struct radv_indirect_command_layout {
uint32_t push_constant_offsets[MAX_PUSH_CONSTANTS_SIZE / 4];
uint64_t sequence_index_mask;
VkPipelineLayout pipeline_layout;
VkPipeline pipeline;
};