diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp index 2de6e9a6deb..d1b57b15d20 100644 --- a/src/amd/compiler/aco_instruction_selection.cpp +++ b/src/amd/compiler/aco_instruction_selection.cpp @@ -9191,7 +9191,6 @@ visit_intrinsic(isel_context* ctx, nir_intrinsic_instr* instr) break; } case nir_intrinsic_export_vertex_amd: { - ctx->block->kind |= block_kind_export_end; create_vs_exports(ctx); break; } @@ -12099,9 +12098,7 @@ select_program(Program* program, unsigned shader_count, struct nir_shader* const if (ctx.program->info.so.num_outputs && ctx.stage.hw == HWStage::VS) emit_streamout(&ctx, 0); - if (ctx.stage.hw == HWStage::VS) { - create_vs_exports(&ctx); - } else if (nir->info.stage == MESA_SHADER_GEOMETRY && !ngg_gs) { + if (nir->info.stage == MESA_SHADER_GEOMETRY && !ngg_gs) { Builder bld(ctx.program, ctx.block); bld.barrier(aco_opcode::p_barrier, memory_sync_info(storage_vmem_output, semantic_release, scope_device)); diff --git a/src/amd/vulkan/radv_nir_to_llvm.c b/src/amd/vulkan/radv_nir_to_llvm.c index 736d2b9b05e..0404d030a52 100644 --- a/src/amd/vulkan/radv_nir_to_llvm.c +++ b/src/amd/vulkan/radv_nir_to_llvm.c @@ -1161,15 +1161,9 @@ handle_shader_outputs_post(struct ac_shader_abi *abi) switch (ctx->stage) { case MESA_SHADER_VERTEX: - if (ctx->shader_info->vs.as_ls) - break; /* Lowered in NIR */ - else if (ctx->shader_info->vs.as_es) - break; /* Lowered in NIR */ - else if (ctx->shader_info->is_ngg) - break; /* Lowered in NIR */ - else - handle_vs_outputs_post(ctx); - break; + case MESA_SHADER_TESS_CTRL: + case MESA_SHADER_TESS_EVAL: + break; /* Lowered in NIR */ case MESA_SHADER_FRAGMENT: handle_fs_outputs_post(ctx); break; @@ -1179,16 +1173,6 @@ handle_shader_outputs_post(struct ac_shader_abi *abi) else emit_gs_epilogue(ctx); break; - case MESA_SHADER_TESS_CTRL: - break; /* Lowered in NIR */ - case MESA_SHADER_TESS_EVAL: - if (ctx->shader_info->tes.as_es) - break; /* Lowered in NIR */ - else if (ctx->shader_info->is_ngg) - break; /* Lowered in NIR */ - else - handle_vs_outputs_post(ctx); - break; default: break; } @@ -1462,7 +1446,9 @@ ac_translate_nir_to_llvm(struct ac_llvm_compiler *ac_llvm, ctx.abi.emit_vertex_with_counter = visit_emit_vertex_with_counter; ctx.abi.emit_primitive = visit_end_primitive; } else if (shaders[shader_idx]->info.stage == MESA_SHADER_TESS_EVAL) { + ctx.abi.export_vertex = radv_llvm_visit_export_vertex; } else if (shaders[shader_idx]->info.stage == MESA_SHADER_VERTEX) { + ctx.abi.export_vertex = radv_llvm_visit_export_vertex; ctx.abi.load_inputs = radv_load_vs_inputs; } diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index a219cce83d5..90c109ee238 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -2181,50 +2181,6 @@ radv_export_multiview(nir_shader *nir) return progress; } -static bool -radv_should_export_implicit_primitive_id(const struct radv_pipeline_stage *producer, - const struct radv_pipeline_stage *consumer) -{ - /* When the primitive ID is read by FS, we must ensure that it's exported by the previous vertex - * stage because it's implicit for VS or TES (but required by the Vulkan spec for GS or MS). - * - * There is two situations to handle: - * - when the next stage is unknown (with graphics pipeline library), the primitive ID is - * exported unconditionally - * - when the pipeline uses NGG, the primitive ID is exported during NGG lowering - */ - assert(producer->stage == MESA_SHADER_VERTEX || producer->stage == MESA_SHADER_TESS_EVAL); - - if ((producer->nir->info.outputs_written & VARYING_BIT_PRIMITIVE_ID) || producer->info.is_ngg) - return false; - - return !consumer || (consumer->stage == MESA_SHADER_FRAGMENT && - (consumer->nir->info.inputs_read & VARYING_BIT_PRIMITIVE_ID)); -} - -static bool -radv_export_implicit_primitive_id(nir_shader *nir) -{ - nir_function_impl *impl = nir_shader_get_entrypoint(nir); - nir_builder b; - nir_builder_init(&b, impl); - - b.cursor = nir_after_cf_list(&impl->body); - - nir_variable *var = nir_variable_create(nir, nir_var_shader_out, glsl_int_type(), NULL); - var->data.location = VARYING_SLOT_PRIMITIVE_ID; - var->data.interpolation = INTERP_MODE_NONE; - - nir_store_var(&b, var, nir_load_primitive_id(&b), 1); - - /* Update outputs_written to reflect that the pass added a new output. */ - nir->info.outputs_written |= BITFIELD64_BIT(VARYING_SLOT_PRIMITIVE_ID); - - nir_metadata_preserve(impl, nir_metadata_block_index | nir_metadata_dominance); - - return true; -} - static void radv_remove_point_size(const struct radv_pipeline_key *pipeline_key, nir_shader *producer, nir_shader *consumer) @@ -2511,10 +2467,6 @@ radv_pipeline_link_vs(const struct radv_device *device, struct radv_pipeline_sta { assert(vs_stage->nir->info.stage == MESA_SHADER_VERTEX); - if (radv_should_export_implicit_primitive_id(vs_stage, next_stage)) { - NIR_PASS(_, vs_stage->nir, radv_export_implicit_primitive_id); - } - if (radv_should_export_multiview(vs_stage, next_stage, pipeline_key)) { NIR_PASS(_, vs_stage->nir, radv_export_multiview); } @@ -2581,10 +2533,6 @@ radv_pipeline_link_tes(const struct radv_device *device, struct radv_pipeline_st { assert(tes_stage->nir->info.stage == MESA_SHADER_TESS_EVAL); - if (radv_should_export_implicit_primitive_id(tes_stage, next_stage)) { - NIR_PASS(_, tes_stage->nir, radv_export_implicit_primitive_id); - } - if (radv_should_export_multiview(tes_stage, next_stage, pipeline_key)) { NIR_PASS(_, tes_stage->nir, radv_export_multiview); } @@ -3900,6 +3848,10 @@ radv_postprocess_nir(struct radv_pipeline *pipeline, if (lowered_ngg) radv_lower_ngg(device, stage, pipeline_key); + if (stage->stage == last_vgt_api_stage && stage->stage != MESA_SHADER_GEOMETRY && !lowered_ngg) + NIR_PASS_V(stage->nir, ac_nir_lower_legacy_vs, + stage->info.outinfo.export_prim_id ? VARYING_SLOT_PRIMITIVE_ID : -1, true); + NIR_PASS(_, stage->nir, nir_opt_idiv_const, 8); NIR_PASS(_, stage->nir, nir_lower_idiv, diff --git a/src/amd/vulkan/radv_shader_info.c b/src/amd/vulkan/radv_shader_info.c index 3625fe2a2e7..525a1e90722 100644 --- a/src/amd/vulkan/radv_shader_info.c +++ b/src/amd/vulkan/radv_shader_info.c @@ -1278,7 +1278,7 @@ radv_link_shaders_info(struct radv_device *device, if (ps_prim_id_in && (producer->stage == MESA_SHADER_VERTEX || producer->stage == MESA_SHADER_TESS_EVAL)) { - /* Mark the primitive ID as output when it's implicitly exported by VS or TES with NGG. */ + /* Mark the primitive ID as output when it's implicitly exported by VS or TES. */ if (outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] == AC_EXP_PARAM_UNDEFINED) outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = outinfo->param_exports++;