diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 3270a05db69..f0718c90fad 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -1877,12 +1877,14 @@ radv_emit_ps_epilog_state(struct radv_cmd_buffer *cmd_buffer, struct radv_shader
    if (cmd_buffer->state.emitted_ps_epilog == ps_epilog)
       return;
 
-   uint32_t col_format = radv_compact_spi_shader_col_format(ps_epilog->spi_shader_col_format);
+   uint32_t col_format = ps_epilog->spi_shader_col_format;
 
    bool need_null_export_workaround = radv_needs_null_export_workaround(device, ps_shader, 0);
    if (need_null_export_workaround && !col_format)
       col_format = V_028714_SPI_SHADER_32_R;
-   radeon_set_context_reg(cmd_buffer->cs, R_028714_SPI_SHADER_COL_FORMAT, col_format);
+
+   radeon_set_context_reg(cmd_buffer->cs, R_028714_SPI_SHADER_COL_FORMAT,
+                          radv_compact_spi_shader_col_format(col_format));
    radeon_set_context_reg(cmd_buffer->cs, R_02823C_CB_SHADER_MASK,
                           ac_get_cb_shader_mask(ps_epilog->spi_shader_col_format));
 
diff --git a/src/amd/vulkan/radv_pipeline_graphics.c b/src/amd/vulkan/radv_pipeline_graphics.c
index 5cc818535f7..44c05f603fd 100644
--- a/src/amd/vulkan/radv_pipeline_graphics.c
+++ b/src/amd/vulkan/radv_pipeline_graphics.c
@@ -2782,6 +2782,14 @@ radv_emit_blend_state(struct radeon_cmdbuf *ctx_cs, const struct radv_shader *ps
    if (ps && ps->info.has_epilog)
       return;
 
+   const bool enable_mrt_compaction = ps && !ps->info.ps.mrt0_is_dual_src;
+   if (enable_mrt_compaction) {
+      /* Make sure to clear color attachments without exports because MRT holes are removed during
+       * compilation for optimal performance.
+       */
+      spi_shader_col_format = radv_compact_spi_shader_col_format(spi_shader_col_format);
+   }
+
    radeon_set_context_reg(ctx_cs, R_028714_SPI_SHADER_COL_FORMAT, spi_shader_col_format);
 
    radeon_set_context_reg(ctx_cs, R_02823C_CB_SHADER_MASK, cb_shader_mask);
@@ -4108,13 +4116,6 @@ radv_graphics_pipeline_init(struct radv_graphics_pipeline *pipeline, struct radv
    pipeline->col_format_non_compacted = blend.spi_shader_col_format;
 
    struct radv_shader *ps = pipeline->base.shaders[MESA_SHADER_FRAGMENT];
-   bool enable_mrt_compaction = ps && !ps->info.has_epilog && !ps->info.ps.mrt0_is_dual_src;
-   if (enable_mrt_compaction) {
-      /* Make sure to clear color attachments without exports because MRT holes are removed during
-       * compilation for optimal performance.
-       */
-      blend.spi_shader_col_format = radv_compact_spi_shader_col_format(blend.spi_shader_col_format);
-   }
 
    unsigned custom_blend_mode = extra ? extra->custom_blend_mode : 0;
    if (radv_needs_null_export_workaround(device, ps, custom_blend_mode) && !blend.spi_shader_col_format) {