diff --git a/src/nouveau/headers/meson.build b/src/nouveau/headers/meson.build index 8d2433f7642..74b21b7df35 100644 --- a/src/nouveau/headers/meson.build +++ b/src/nouveau/headers/meson.build @@ -29,7 +29,7 @@ nv_classes = [ 'clc797', 'clc7c0', 'clc86f', - 'clc9b5', + 'clcab5', 'clcb97', 'clcbc0', 'clcd97', diff --git a/src/nouveau/headers/nv_push.c b/src/nouveau/headers/nv_push.c index c7247a6b89d..c2af75a6677 100644 --- a/src/nouveau/headers/nv_push.c +++ b/src/nouveau/headers/nv_push.c @@ -25,7 +25,7 @@ #include "nv_push_clc6c0.h" #include "nv_push_clc797.h" #include "nv_push_clc7c0.h" -#include "nv_push_clc9b5.h" +#include "nv_push_clcab5.h" #ifndef NDEBUG void @@ -200,8 +200,8 @@ vk_push_print(FILE *fp, const struct nv_push *push, mthd_name = P_PARSE_NV902D_MTHD(mthd); break; case 4: - if (devinfo->cls_copy >= 0xc9b5) - mthd_name = P_PARSE_NVC9B5_MTHD(mthd); + if (devinfo->cls_copy >= 0xcab5) + mthd_name = P_PARSE_NVCAB5_MTHD(mthd); else if (devinfo->cls_copy >= 0xc1b5) mthd_name = P_PARSE_NVC1B5_MTHD(mthd); else if (devinfo->cls_copy >= 0xa0b5) @@ -248,8 +248,8 @@ vk_push_print(FILE *fp, const struct nv_push *push, P_DUMP_NV902D_MTHD_DATA(fp, mthd, value, "\t\t"); break; case 4: - if (devinfo->cls_copy >= 0xc9b5) - P_DUMP_NVC9B5_MTHD_DATA(fp, mthd, value, "\t\t"); + if (devinfo->cls_copy >= 0xcab5) + P_DUMP_NVCAB5_MTHD_DATA(fp, mthd, value, "\t\t"); else if (devinfo->cls_copy >= 0xc1b5) P_DUMP_NVC1B5_MTHD_DATA(fp, mthd, value, "\t\t"); else if (devinfo->cls_copy >= 0xa0b5) diff --git a/src/nouveau/headers/nvidia/classes/clc8b5.h b/src/nouveau/headers/nvidia/classes/clc8b5.h new file mode 100644 index 00000000000..75968de9abb --- /dev/null +++ b/src/nouveau/headers/nvidia/classes/clc8b5.h @@ -0,0 +1,334 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2004 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#include "nvtypes.h" + +#ifndef _clc8b5_h_ +#define _clc8b5_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define HOPPER_DMA_COPY_A (0x0000C8B5) + +#define NVC8B5_NOP (0x00000100) +#define NVC8B5_NOP_PARAMETER 31:0 +#define NVC8B5_PM_TRIGGER (0x00000140) +#define NVC8B5_PM_TRIGGER_V 31:0 +#define NVC8B5_SET_MONITORED_FENCE_TYPE (0x0000021C) +#define NVC8B5_SET_MONITORED_FENCE_TYPE_TYPE 0:0 +#define NVC8B5_SET_MONITORED_FENCE_TYPE_TYPE_MONITORED_FENCE (0x00000000) +#define NVC8B5_SET_MONITORED_FENCE_TYPE_TYPE_MONITORED_FENCE_EXT (0x00000001) +#define NVC8B5_SET_MONITORED_FENCE_SIGNAL_ADDR_BASE_UPPER (0x00000220) +#define NVC8B5_SET_MONITORED_FENCE_SIGNAL_ADDR_BASE_UPPER_UPPER 24:0 +#define NVC8B5_SET_MONITORED_FENCE_SIGNAL_ADDR_BASE_LOWER (0x00000224) +#define NVC8B5_SET_MONITORED_FENCE_SIGNAL_ADDR_BASE_LOWER_LOWER 31:0 +#define NVC8B5_SET_SEMAPHORE_A (0x00000240) +#define NVC8B5_SET_SEMAPHORE_A_UPPER 24:0 +#define NVC8B5_SET_SEMAPHORE_B (0x00000244) +#define NVC8B5_SET_SEMAPHORE_B_LOWER 31:0 +#define NVC8B5_SET_SEMAPHORE_PAYLOAD (0x00000248) +#define NVC8B5_SET_SEMAPHORE_PAYLOAD_PAYLOAD 31:0 +#define NVC8B5_SET_SEMAPHORE_PAYLOAD_UPPER (0x0000024C) +#define NVC8B5_SET_SEMAPHORE_PAYLOAD_UPPER_PAYLOAD 31:0 +#define NVC8B5_SET_RENDER_ENABLE_A (0x00000254) +#define NVC8B5_SET_RENDER_ENABLE_A_UPPER 24:0 +#define NVC8B5_SET_RENDER_ENABLE_B (0x00000258) +#define NVC8B5_SET_RENDER_ENABLE_B_LOWER 31:0 +#define NVC8B5_SET_RENDER_ENABLE_C (0x0000025C) +#define NVC8B5_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVC8B5_SET_RENDER_ENABLE_C_MODE_FALSE (0x00000000) +#define NVC8B5_SET_RENDER_ENABLE_C_MODE_TRUE (0x00000001) +#define NVC8B5_SET_RENDER_ENABLE_C_MODE_CONDITIONAL (0x00000002) +#define NVC8B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL (0x00000003) +#define NVC8B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL (0x00000004) +#define NVC8B5_SET_SRC_PHYS_MODE (0x00000260) +#define NVC8B5_SET_SRC_PHYS_MODE_TARGET 1:0 +#define NVC8B5_SET_SRC_PHYS_MODE_TARGET_LOCAL_FB (0x00000000) +#define NVC8B5_SET_SRC_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001) +#define NVC8B5_SET_SRC_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002) +#define NVC8B5_SET_SRC_PHYS_MODE_TARGET_PEERMEM (0x00000003) +#define NVC8B5_SET_SRC_PHYS_MODE_BASIC_KIND 5:2 +#define NVC8B5_SET_SRC_PHYS_MODE_PEER_ID 8:6 +#define NVC8B5_SET_SRC_PHYS_MODE_FLA 9:9 +#define NVC8B5_SET_DST_PHYS_MODE (0x00000264) +#define NVC8B5_SET_DST_PHYS_MODE_TARGET 1:0 +#define NVC8B5_SET_DST_PHYS_MODE_TARGET_LOCAL_FB (0x00000000) +#define NVC8B5_SET_DST_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001) +#define NVC8B5_SET_DST_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002) +#define NVC8B5_SET_DST_PHYS_MODE_TARGET_PEERMEM (0x00000003) +#define NVC8B5_SET_DST_PHYS_MODE_BASIC_KIND 5:2 +#define NVC8B5_SET_DST_PHYS_MODE_PEER_ID 8:6 +#define NVC8B5_SET_DST_PHYS_MODE_FLA 9:9 +#define NVC8B5_LAUNCH_DMA (0x00000300) +#define NVC8B5_LAUNCH_DMA_DATA_TRANSFER_TYPE 1:0 +#define NVC8B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NONE (0x00000000) +#define NVC8B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_PIPELINED (0x00000001) +#define NVC8B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NON_PIPELINED (0x00000002) +#define NVC8B5_LAUNCH_DMA_FLUSH_ENABLE 2:2 +#define NVC8B5_LAUNCH_DMA_FLUSH_ENABLE_FALSE (0x00000000) +#define NVC8B5_LAUNCH_DMA_FLUSH_ENABLE_TRUE (0x00000001) +#define NVC8B5_LAUNCH_DMA_FLUSH_TYPE 25:25 +#define NVC8B5_LAUNCH_DMA_FLUSH_TYPE_SYS (0x00000000) +#define NVC8B5_LAUNCH_DMA_FLUSH_TYPE_GL (0x00000001) +#define NVC8B5_LAUNCH_DMA_SEMAPHORE_TYPE 4:3 +#define NVC8B5_LAUNCH_DMA_SEMAPHORE_TYPE_NONE (0x00000000) +#define NVC8B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_SEMAPHORE_NO_TIMESTAMP (0x00000001) +#define NVC8B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_SEMAPHORE_WITH_TIMESTAMP (0x00000002) +#define NVC8B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_ONE_WORD_SEMAPHORE (0x00000001) +#define NVC8B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_FOUR_WORD_SEMAPHORE (0x00000002) +#define NVC8B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_CONDITIONAL_INTR_SEMAPHORE (0x00000003) +#define NVC8B5_LAUNCH_DMA_INTERRUPT_TYPE 6:5 +#define NVC8B5_LAUNCH_DMA_INTERRUPT_TYPE_NONE (0x00000000) +#define NVC8B5_LAUNCH_DMA_INTERRUPT_TYPE_BLOCKING (0x00000001) +#define NVC8B5_LAUNCH_DMA_INTERRUPT_TYPE_NON_BLOCKING (0x00000002) +#define NVC8B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT 7:7 +#define NVC8B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NVC8B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_PITCH (0x00000001) +#define NVC8B5_LAUNCH_DMA_DST_MEMORY_LAYOUT 8:8 +#define NVC8B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NVC8B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH (0x00000001) +#define NVC8B5_LAUNCH_DMA_MULTI_LINE_ENABLE 9:9 +#define NVC8B5_LAUNCH_DMA_MULTI_LINE_ENABLE_FALSE (0x00000000) +#define NVC8B5_LAUNCH_DMA_MULTI_LINE_ENABLE_TRUE (0x00000001) +#define NVC8B5_LAUNCH_DMA_REMAP_ENABLE 10:10 +#define NVC8B5_LAUNCH_DMA_REMAP_ENABLE_FALSE (0x00000000) +#define NVC8B5_LAUNCH_DMA_REMAP_ENABLE_TRUE (0x00000001) +#define NVC8B5_LAUNCH_DMA_FORCE_RMWDISABLE 11:11 +#define NVC8B5_LAUNCH_DMA_FORCE_RMWDISABLE_FALSE (0x00000000) +#define NVC8B5_LAUNCH_DMA_FORCE_RMWDISABLE_TRUE (0x00000001) +#define NVC8B5_LAUNCH_DMA_SRC_TYPE 12:12 +#define NVC8B5_LAUNCH_DMA_SRC_TYPE_VIRTUAL (0x00000000) +#define NVC8B5_LAUNCH_DMA_SRC_TYPE_PHYSICAL (0x00000001) +#define NVC8B5_LAUNCH_DMA_DST_TYPE 13:13 +#define NVC8B5_LAUNCH_DMA_DST_TYPE_VIRTUAL (0x00000000) +#define NVC8B5_LAUNCH_DMA_DST_TYPE_PHYSICAL (0x00000001) +#define NVC8B5_LAUNCH_DMA_SEMAPHORE_REDUCTION 17:14 +#define NVC8B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMIN (0x00000000) +#define NVC8B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMAX (0x00000001) +#define NVC8B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IXOR (0x00000002) +#define NVC8B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IAND (0x00000003) +#define NVC8B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IOR (0x00000004) +#define NVC8B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IADD (0x00000005) +#define NVC8B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INC (0x00000006) +#define NVC8B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_DEC (0x00000007) +#define NVC8B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INVALIDA (0x00000008) +#define NVC8B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INVALIDB (0x00000009) +#define NVC8B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FADD (0x0000000A) +#define NVC8B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FMIN (0x0000000B) +#define NVC8B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FMAX (0x0000000C) +#define NVC8B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INVALIDC (0x0000000D) +#define NVC8B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INVALIDD (0x0000000E) +#define NVC8B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INVALIDE (0x0000000F) +#define NVC8B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN 18:18 +#define NVC8B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_SIGNED (0x00000000) +#define NVC8B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_UNSIGNED (0x00000001) +#define NVC8B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE 19:19 +#define NVC8B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_FALSE (0x00000000) +#define NVC8B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_TRUE (0x00000001) +#define NVC8B5_LAUNCH_DMA_COPY_TYPE 21:20 +#define NVC8B5_LAUNCH_DMA_COPY_TYPE_PROT2PROT (0x00000000) +#define NVC8B5_LAUNCH_DMA_COPY_TYPE_DEFAULT (0x00000000) +#define NVC8B5_LAUNCH_DMA_COPY_TYPE_SECURE (0x00000001) +#define NVC8B5_LAUNCH_DMA_COPY_TYPE_NONPROT2NONPROT (0x00000002) +#define NVC8B5_LAUNCH_DMA_COPY_TYPE_RESERVED (0x00000003) +#define NVC8B5_LAUNCH_DMA_VPRMODE 22:22 +#define NVC8B5_LAUNCH_DMA_VPRMODE_VPR_NONE (0x00000000) +#define NVC8B5_LAUNCH_DMA_VPRMODE_VPR_VID2VID (0x00000001) +#define NVC8B5_LAUNCH_DMA_MEMORY_SCRUB_ENABLE 23:23 +#define NVC8B5_LAUNCH_DMA_MEMORY_SCRUB_ENABLE_FALSE (0x00000000) +#define NVC8B5_LAUNCH_DMA_MEMORY_SCRUB_ENABLE_TRUE (0x00000001) +#define NVC8B5_LAUNCH_DMA_RESERVED_START_OF_COPY 24:24 +#define NVC8B5_LAUNCH_DMA_DISABLE_PLC 26:26 +#define NVC8B5_LAUNCH_DMA_DISABLE_PLC_FALSE (0x00000000) +#define NVC8B5_LAUNCH_DMA_DISABLE_PLC_TRUE (0x00000001) +#define NVC8B5_LAUNCH_DMA_SEMAPHORE_PAYLOAD_SIZE 27:27 +#define NVC8B5_LAUNCH_DMA_SEMAPHORE_PAYLOAD_SIZE_ONE_WORD (0x00000000) +#define NVC8B5_LAUNCH_DMA_SEMAPHORE_PAYLOAD_SIZE_TWO_WORD (0x00000001) +#define NVC8B5_LAUNCH_DMA_RESERVED_ERR_CODE 31:28 +#define NVC8B5_OFFSET_IN_UPPER (0x00000400) +#define NVC8B5_OFFSET_IN_UPPER_UPPER 24:0 +#define NVC8B5_OFFSET_IN_LOWER (0x00000404) +#define NVC8B5_OFFSET_IN_LOWER_VALUE 31:0 +#define NVC8B5_OFFSET_OUT_UPPER (0x00000408) +#define NVC8B5_OFFSET_OUT_UPPER_UPPER 24:0 +#define NVC8B5_OFFSET_OUT_LOWER (0x0000040C) +#define NVC8B5_OFFSET_OUT_LOWER_VALUE 31:0 +#define NVC8B5_PITCH_IN (0x00000410) +#define NVC8B5_PITCH_IN_VALUE 31:0 +#define NVC8B5_PITCH_OUT (0x00000414) +#define NVC8B5_PITCH_OUT_VALUE 31:0 +#define NVC8B5_LINE_LENGTH_IN (0x00000418) +#define NVC8B5_LINE_LENGTH_IN_VALUE 31:0 +#define NVC8B5_LINE_COUNT (0x0000041C) +#define NVC8B5_LINE_COUNT_VALUE 31:0 +#define NVC8B5_SET_SECURE_COPY_MODE (0x00000500) +#define NVC8B5_SET_SECURE_COPY_MODE_MODE 0:0 +#define NVC8B5_SET_SECURE_COPY_MODE_MODE_ENCRYPT (0x00000000) +#define NVC8B5_SET_SECURE_COPY_MODE_MODE_DECRYPT (0x00000001) +#define NVC8B5_SET_DECRYPT_AUTH_TAG_COMPARE_ADDR_UPPER (0x00000514) +#define NVC8B5_SET_DECRYPT_AUTH_TAG_COMPARE_ADDR_UPPER_UPPER 24:0 +#define NVC8B5_SET_DECRYPT_AUTH_TAG_COMPARE_ADDR_LOWER (0x00000518) +#define NVC8B5_SET_DECRYPT_AUTH_TAG_COMPARE_ADDR_LOWER_LOWER 31:0 +#define NVC8B5_SET_ENCRYPT_AUTH_TAG_ADDR_UPPER (0x00000530) +#define NVC8B5_SET_ENCRYPT_AUTH_TAG_ADDR_UPPER_UPPER 24:0 +#define NVC8B5_SET_ENCRYPT_AUTH_TAG_ADDR_LOWER (0x00000534) +#define NVC8B5_SET_ENCRYPT_AUTH_TAG_ADDR_LOWER_LOWER 31:0 +#define NVC8B5_SET_ENCRYPT_IV_ADDR_UPPER (0x00000538) +#define NVC8B5_SET_ENCRYPT_IV_ADDR_UPPER_UPPER 24:0 +#define NVC8B5_SET_ENCRYPT_IV_ADDR_LOWER (0x0000053C) +#define NVC8B5_SET_ENCRYPT_IV_ADDR_LOWER_LOWER 31:0 +#define NVC8B5_SET_MEMORY_SCRUB_PARAMETERS (0x000006FC) +#define NVC8B5_SET_MEMORY_SCRUB_PARAMETERS_DISCARDABLE 0:0 +#define NVC8B5_SET_MEMORY_SCRUB_PARAMETERS_DISCARDABLE_FALSE (0x00000000) +#define NVC8B5_SET_MEMORY_SCRUB_PARAMETERS_DISCARDABLE_TRUE (0x00000001) +#define NVC8B5_SET_REMAP_CONST_A (0x00000700) +#define NVC8B5_SET_REMAP_CONST_A_V 31:0 +#define NVC8B5_SET_REMAP_CONST_B (0x00000704) +#define NVC8B5_SET_REMAP_CONST_B_V 31:0 +#define NVC8B5_SET_REMAP_COMPONENTS (0x00000708) +#define NVC8B5_SET_REMAP_COMPONENTS_DST_X 2:0 +#define NVC8B5_SET_REMAP_COMPONENTS_DST_X_SRC_X (0x00000000) +#define NVC8B5_SET_REMAP_COMPONENTS_DST_X_SRC_Y (0x00000001) +#define NVC8B5_SET_REMAP_COMPONENTS_DST_X_SRC_Z (0x00000002) +#define NVC8B5_SET_REMAP_COMPONENTS_DST_X_SRC_W (0x00000003) +#define NVC8B5_SET_REMAP_COMPONENTS_DST_X_CONST_A (0x00000004) +#define NVC8B5_SET_REMAP_COMPONENTS_DST_X_CONST_B (0x00000005) +#define NVC8B5_SET_REMAP_COMPONENTS_DST_X_NO_WRITE (0x00000006) +#define NVC8B5_SET_REMAP_COMPONENTS_DST_Y 6:4 +#define NVC8B5_SET_REMAP_COMPONENTS_DST_Y_SRC_X (0x00000000) +#define NVC8B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Y (0x00000001) +#define NVC8B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Z (0x00000002) +#define NVC8B5_SET_REMAP_COMPONENTS_DST_Y_SRC_W (0x00000003) +#define NVC8B5_SET_REMAP_COMPONENTS_DST_Y_CONST_A (0x00000004) +#define NVC8B5_SET_REMAP_COMPONENTS_DST_Y_CONST_B (0x00000005) +#define NVC8B5_SET_REMAP_COMPONENTS_DST_Y_NO_WRITE (0x00000006) +#define NVC8B5_SET_REMAP_COMPONENTS_DST_Z 10:8 +#define NVC8B5_SET_REMAP_COMPONENTS_DST_Z_SRC_X (0x00000000) +#define NVC8B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Y (0x00000001) +#define NVC8B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Z (0x00000002) +#define NVC8B5_SET_REMAP_COMPONENTS_DST_Z_SRC_W (0x00000003) +#define NVC8B5_SET_REMAP_COMPONENTS_DST_Z_CONST_A (0x00000004) +#define NVC8B5_SET_REMAP_COMPONENTS_DST_Z_CONST_B (0x00000005) +#define NVC8B5_SET_REMAP_COMPONENTS_DST_Z_NO_WRITE (0x00000006) +#define NVC8B5_SET_REMAP_COMPONENTS_DST_W 14:12 +#define NVC8B5_SET_REMAP_COMPONENTS_DST_W_SRC_X (0x00000000) +#define NVC8B5_SET_REMAP_COMPONENTS_DST_W_SRC_Y (0x00000001) +#define NVC8B5_SET_REMAP_COMPONENTS_DST_W_SRC_Z (0x00000002) +#define NVC8B5_SET_REMAP_COMPONENTS_DST_W_SRC_W (0x00000003) +#define NVC8B5_SET_REMAP_COMPONENTS_DST_W_CONST_A (0x00000004) +#define NVC8B5_SET_REMAP_COMPONENTS_DST_W_CONST_B (0x00000005) +#define NVC8B5_SET_REMAP_COMPONENTS_DST_W_NO_WRITE (0x00000006) +#define NVC8B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE 17:16 +#define NVC8B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_ONE (0x00000000) +#define NVC8B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_TWO (0x00000001) +#define NVC8B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_THREE (0x00000002) +#define NVC8B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_FOUR (0x00000003) +#define NVC8B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS 21:20 +#define NVC8B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_ONE (0x00000000) +#define NVC8B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_TWO (0x00000001) +#define NVC8B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_THREE (0x00000002) +#define NVC8B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_FOUR (0x00000003) +#define NVC8B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS 25:24 +#define NVC8B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_ONE (0x00000000) +#define NVC8B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_TWO (0x00000001) +#define NVC8B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_THREE (0x00000002) +#define NVC8B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_FOUR (0x00000003) +#define NVC8B5_SET_DST_BLOCK_SIZE (0x0000070C) +#define NVC8B5_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVC8B5_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB (0x00000000) +#define NVC8B5_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVC8B5_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB (0x00000000) +#define NVC8B5_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS (0x00000001) +#define NVC8B5_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS (0x00000002) +#define NVC8B5_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVC8B5_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVC8B5_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVC8B5_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVC8B5_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB (0x00000000) +#define NVC8B5_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS (0x00000001) +#define NVC8B5_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS (0x00000002) +#define NVC8B5_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS (0x00000003) +#define NVC8B5_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS (0x00000004) +#define NVC8B5_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005) +#define NVC8B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT 15:12 +#define NVC8B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001) +#define NVC8B5_SET_DST_WIDTH (0x00000710) +#define NVC8B5_SET_DST_WIDTH_V 31:0 +#define NVC8B5_SET_DST_HEIGHT (0x00000714) +#define NVC8B5_SET_DST_HEIGHT_V 31:0 +#define NVC8B5_SET_DST_DEPTH (0x00000718) +#define NVC8B5_SET_DST_DEPTH_V 31:0 +#define NVC8B5_SET_DST_LAYER (0x0000071C) +#define NVC8B5_SET_DST_LAYER_V 31:0 +#define NVC8B5_SET_DST_ORIGIN (0x00000720) +#define NVC8B5_SET_DST_ORIGIN_X 15:0 +#define NVC8B5_SET_DST_ORIGIN_Y 31:16 +#define NVC8B5_SET_SRC_BLOCK_SIZE (0x00000728) +#define NVC8B5_SET_SRC_BLOCK_SIZE_WIDTH 3:0 +#define NVC8B5_SET_SRC_BLOCK_SIZE_WIDTH_ONE_GOB (0x00000000) +#define NVC8B5_SET_SRC_BLOCK_SIZE_HEIGHT 7:4 +#define NVC8B5_SET_SRC_BLOCK_SIZE_HEIGHT_ONE_GOB (0x00000000) +#define NVC8B5_SET_SRC_BLOCK_SIZE_HEIGHT_TWO_GOBS (0x00000001) +#define NVC8B5_SET_SRC_BLOCK_SIZE_HEIGHT_FOUR_GOBS (0x00000002) +#define NVC8B5_SET_SRC_BLOCK_SIZE_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVC8B5_SET_SRC_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVC8B5_SET_SRC_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVC8B5_SET_SRC_BLOCK_SIZE_DEPTH 11:8 +#define NVC8B5_SET_SRC_BLOCK_SIZE_DEPTH_ONE_GOB (0x00000000) +#define NVC8B5_SET_SRC_BLOCK_SIZE_DEPTH_TWO_GOBS (0x00000001) +#define NVC8B5_SET_SRC_BLOCK_SIZE_DEPTH_FOUR_GOBS (0x00000002) +#define NVC8B5_SET_SRC_BLOCK_SIZE_DEPTH_EIGHT_GOBS (0x00000003) +#define NVC8B5_SET_SRC_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS (0x00000004) +#define NVC8B5_SET_SRC_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005) +#define NVC8B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT 15:12 +#define NVC8B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001) +#define NVC8B5_SET_SRC_WIDTH (0x0000072C) +#define NVC8B5_SET_SRC_WIDTH_V 31:0 +#define NVC8B5_SET_SRC_HEIGHT (0x00000730) +#define NVC8B5_SET_SRC_HEIGHT_V 31:0 +#define NVC8B5_SET_SRC_DEPTH (0x00000734) +#define NVC8B5_SET_SRC_DEPTH_V 31:0 +#define NVC8B5_SET_SRC_LAYER (0x00000738) +#define NVC8B5_SET_SRC_LAYER_V 31:0 +#define NVC8B5_SET_SRC_ORIGIN (0x0000073C) +#define NVC8B5_SET_SRC_ORIGIN_X 15:0 +#define NVC8B5_SET_SRC_ORIGIN_Y 31:16 +#define NVC8B5_SRC_ORIGIN_X (0x00000744) +#define NVC8B5_SRC_ORIGIN_X_VALUE 31:0 +#define NVC8B5_SRC_ORIGIN_Y (0x00000748) +#define NVC8B5_SRC_ORIGIN_Y_VALUE 31:0 +#define NVC8B5_DST_ORIGIN_X (0x0000074C) +#define NVC8B5_DST_ORIGIN_X_VALUE 31:0 +#define NVC8B5_DST_ORIGIN_Y (0x00000750) +#define NVC8B5_DST_ORIGIN_Y_VALUE 31:0 +#define NVC8B5_PM_TRIGGER_END (0x00001114) +#define NVC8B5_PM_TRIGGER_END_V 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clc8b5_h + diff --git a/src/nouveau/headers/nvidia/classes/clc9b5.h b/src/nouveau/headers/nvidia/classes/clc9b5.h index 54eacc5f8d0..256b129e49d 100644 --- a/src/nouveau/headers/nvidia/classes/clc9b5.h +++ b/src/nouveau/headers/nvidia/classes/clc9b5.h @@ -1,28 +1,27 @@ -/******************************************************************************* - Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. - - Permission is hereby granted, free of charge, to any person obtaining a - copy of this software and associated documentation files (the "Software"), - to deal in the Software without restriction, including without limitation - the rights to use, copy, modify, merge, publish, distribute, sublicense, - and/or sell copies of the Software, and to permit persons to whom the - Software is furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be included in - all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - DEALINGS IN THE SOFTWARE. - -*******************************************************************************/ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2004 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ -////////////////// NOT OFFICAL NVIDIA - HACKED BY airlied #include "nvtypes.h" #ifndef _clc9b5_h_ @@ -32,20 +31,30 @@ extern "C" { #endif -#define BLACKWELL_DMA_COPY_A (0x0000C9B5) +#define BLACKWELL_DMA_COPY_A (0x0000C9B5) #define NVC9B5_NOP (0x00000100) #define NVC9B5_NOP_PARAMETER 31:0 #define NVC9B5_PM_TRIGGER (0x00000140) #define NVC9B5_PM_TRIGGER_V 31:0 +#define NVC9B5_SET_MONITORED_FENCE_TYPE (0x0000021C) +#define NVC9B5_SET_MONITORED_FENCE_TYPE_TYPE 0:0 +#define NVC9B5_SET_MONITORED_FENCE_TYPE_TYPE_MONITORED_FENCE (0x00000000) +#define NVC9B5_SET_MONITORED_FENCE_TYPE_TYPE_MONITORED_FENCE_EXT (0x00000001) +#define NVC9B5_SET_MONITORED_FENCE_SIGNAL_ADDR_BASE_UPPER (0x00000220) +#define NVC9B5_SET_MONITORED_FENCE_SIGNAL_ADDR_BASE_UPPER_UPPER 24:0 +#define NVC9B5_SET_MONITORED_FENCE_SIGNAL_ADDR_BASE_LOWER (0x00000224) +#define NVC9B5_SET_MONITORED_FENCE_SIGNAL_ADDR_BASE_LOWER_LOWER 31:0 #define NVC9B5_SET_SEMAPHORE_A (0x00000240) -#define NVC9B5_SET_SEMAPHORE_A_UPPER 16:0 +#define NVC9B5_SET_SEMAPHORE_A_UPPER 24:0 #define NVC9B5_SET_SEMAPHORE_B (0x00000244) #define NVC9B5_SET_SEMAPHORE_B_LOWER 31:0 #define NVC9B5_SET_SEMAPHORE_PAYLOAD (0x00000248) #define NVC9B5_SET_SEMAPHORE_PAYLOAD_PAYLOAD 31:0 +#define NVC9B5_SET_SEMAPHORE_PAYLOAD_UPPER (0x0000024C) +#define NVC9B5_SET_SEMAPHORE_PAYLOAD_UPPER_PAYLOAD 31:0 #define NVC9B5_SET_RENDER_ENABLE_A (0x00000254) -#define NVC9B5_SET_RENDER_ENABLE_A_UPPER 7:0 +#define NVC9B5_SET_RENDER_ENABLE_A_UPPER 24:0 #define NVC9B5_SET_RENDER_ENABLE_B (0x00000258) #define NVC9B5_SET_RENDER_ENABLE_B_LOWER 31:0 #define NVC9B5_SET_RENDER_ENABLE_C (0x0000025C) @@ -60,11 +69,19 @@ extern "C" { #define NVC9B5_SET_SRC_PHYS_MODE_TARGET_LOCAL_FB (0x00000000) #define NVC9B5_SET_SRC_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001) #define NVC9B5_SET_SRC_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002) +#define NVC9B5_SET_SRC_PHYS_MODE_TARGET_PEERMEM (0x00000003) +#define NVC9B5_SET_SRC_PHYS_MODE_BASIC_KIND 5:2 +#define NVC9B5_SET_SRC_PHYS_MODE_PEER_ID 8:6 +#define NVC9B5_SET_SRC_PHYS_MODE_FLA 9:9 #define NVC9B5_SET_DST_PHYS_MODE (0x00000264) #define NVC9B5_SET_DST_PHYS_MODE_TARGET 1:0 #define NVC9B5_SET_DST_PHYS_MODE_TARGET_LOCAL_FB (0x00000000) #define NVC9B5_SET_DST_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001) #define NVC9B5_SET_DST_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002) +#define NVC9B5_SET_DST_PHYS_MODE_TARGET_PEERMEM (0x00000003) +#define NVC9B5_SET_DST_PHYS_MODE_BASIC_KIND 5:2 +#define NVC9B5_SET_DST_PHYS_MODE_PEER_ID 8:6 +#define NVC9B5_SET_DST_PHYS_MODE_FLA 9:9 #define NVC9B5_LAUNCH_DMA (0x00000300) #define NVC9B5_LAUNCH_DMA_DATA_TRANSFER_TYPE 1:0 #define NVC9B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NONE (0x00000000) @@ -73,10 +90,16 @@ extern "C" { #define NVC9B5_LAUNCH_DMA_FLUSH_ENABLE 2:2 #define NVC9B5_LAUNCH_DMA_FLUSH_ENABLE_FALSE (0x00000000) #define NVC9B5_LAUNCH_DMA_FLUSH_ENABLE_TRUE (0x00000001) +#define NVC9B5_LAUNCH_DMA_FLUSH_TYPE 25:25 +#define NVC9B5_LAUNCH_DMA_FLUSH_TYPE_SYS (0x00000000) +#define NVC9B5_LAUNCH_DMA_FLUSH_TYPE_GL (0x00000001) #define NVC9B5_LAUNCH_DMA_SEMAPHORE_TYPE 4:3 #define NVC9B5_LAUNCH_DMA_SEMAPHORE_TYPE_NONE (0x00000000) +#define NVC9B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_SEMAPHORE_NO_TIMESTAMP (0x00000001) +#define NVC9B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_SEMAPHORE_WITH_TIMESTAMP (0x00000002) #define NVC9B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_ONE_WORD_SEMAPHORE (0x00000001) #define NVC9B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_FOUR_WORD_SEMAPHORE (0x00000002) +#define NVC9B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_CONDITIONAL_INTR_SEMAPHORE (0x00000003) #define NVC9B5_LAUNCH_DMA_INTERRUPT_TYPE 6:5 #define NVC9B5_LAUNCH_DMA_INTERRUPT_TYPE_NONE (0x00000000) #define NVC9B5_LAUNCH_DMA_INTERRUPT_TYPE_BLOCKING (0x00000001) @@ -93,9 +116,6 @@ extern "C" { #define NVC9B5_LAUNCH_DMA_REMAP_ENABLE 10:10 #define NVC9B5_LAUNCH_DMA_REMAP_ENABLE_FALSE (0x00000000) #define NVC9B5_LAUNCH_DMA_REMAP_ENABLE_TRUE (0x00000001) -#define NVC9B5_LAUNCH_DMA_FORCE_RMWDISABLE 11:11 -#define NVC9B5_LAUNCH_DMA_FORCE_RMWDISABLE_FALSE (0x00000000) -#define NVC9B5_LAUNCH_DMA_FORCE_RMWDISABLE_TRUE (0x00000001) #define NVC9B5_LAUNCH_DMA_SRC_TYPE 12:12 #define NVC9B5_LAUNCH_DMA_SRC_TYPE_VIRTUAL (0x00000000) #define NVC9B5_LAUNCH_DMA_SRC_TYPE_PHYSICAL (0x00000001) @@ -111,30 +131,46 @@ extern "C" { #define NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IADD (0x00000005) #define NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INC (0x00000006) #define NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_DEC (0x00000007) +#define NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INVALIDA (0x00000008) +#define NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INVALIDB (0x00000009) #define NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FADD (0x0000000A) +#define NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FMIN (0x0000000B) +#define NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FMAX (0x0000000C) +#define NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INVALIDC (0x0000000D) +#define NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INVALIDD (0x0000000E) +#define NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INVALIDE (0x0000000F) #define NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN 18:18 #define NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_SIGNED (0x00000000) #define NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_UNSIGNED (0x00000001) #define NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE 19:19 #define NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_FALSE (0x00000000) #define NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_TRUE (0x00000001) -#define NVC9B5_LAUNCH_DMA_SRC_BYPASS_L2 20:20 -#define NVC9B5_LAUNCH_DMA_SRC_BYPASS_L2_USE_PTE_SETTING (0x00000000) -#define NVC9B5_LAUNCH_DMA_SRC_BYPASS_L2_FORCE_VOLATILE (0x00000001) -#define NVC9B5_LAUNCH_DMA_DST_BYPASS_L2 21:21 -#define NVC9B5_LAUNCH_DMA_DST_BYPASS_L2_USE_PTE_SETTING (0x00000000) -#define NVC9B5_LAUNCH_DMA_DST_BYPASS_L2_FORCE_VOLATILE (0x00000001) -#define NVC9B5_LAUNCH_DMA_VPRMODE 23:22 +#define NVC9B5_LAUNCH_DMA_COPY_TYPE 21:20 +#define NVC9B5_LAUNCH_DMA_COPY_TYPE_PROT2PROT (0x00000000) +#define NVC9B5_LAUNCH_DMA_COPY_TYPE_DEFAULT (0x00000000) +#define NVC9B5_LAUNCH_DMA_COPY_TYPE_SECURE (0x00000001) +#define NVC9B5_LAUNCH_DMA_COPY_TYPE_NONPROT2NONPROT (0x00000002) +#define NVC9B5_LAUNCH_DMA_COPY_TYPE_RESERVED (0x00000003) +#define NVC9B5_LAUNCH_DMA_VPRMODE 22:22 #define NVC9B5_LAUNCH_DMA_VPRMODE_VPR_NONE (0x00000000) #define NVC9B5_LAUNCH_DMA_VPRMODE_VPR_VID2VID (0x00000001) +#define NVC9B5_LAUNCH_DMA_MEMORY_SCRUB_ENABLE 23:23 +#define NVC9B5_LAUNCH_DMA_MEMORY_SCRUB_ENABLE_FALSE (0x00000000) +#define NVC9B5_LAUNCH_DMA_MEMORY_SCRUB_ENABLE_TRUE (0x00000001) #define NVC9B5_LAUNCH_DMA_RESERVED_START_OF_COPY 24:24 +#define NVC9B5_LAUNCH_DMA_DISABLE_PLC 26:26 +#define NVC9B5_LAUNCH_DMA_DISABLE_PLC_FALSE (0x00000000) +#define NVC9B5_LAUNCH_DMA_DISABLE_PLC_TRUE (0x00000001) +#define NVC9B5_LAUNCH_DMA_SEMAPHORE_PAYLOAD_SIZE 27:27 +#define NVC9B5_LAUNCH_DMA_SEMAPHORE_PAYLOAD_SIZE_ONE_WORD (0x00000000) +#define NVC9B5_LAUNCH_DMA_SEMAPHORE_PAYLOAD_SIZE_TWO_WORD (0x00000001) #define NVC9B5_LAUNCH_DMA_RESERVED_ERR_CODE 31:28 #define NVC9B5_OFFSET_IN_UPPER (0x00000400) -#define NVC9B5_OFFSET_IN_UPPER_UPPER 16:0 +#define NVC9B5_OFFSET_IN_UPPER_UPPER 24:0 #define NVC9B5_OFFSET_IN_LOWER (0x00000404) #define NVC9B5_OFFSET_IN_LOWER_VALUE 31:0 #define NVC9B5_OFFSET_OUT_UPPER (0x00000408) -#define NVC9B5_OFFSET_OUT_UPPER_UPPER 16:0 +#define NVC9B5_OFFSET_OUT_UPPER_UPPER 24:0 #define NVC9B5_OFFSET_OUT_LOWER (0x0000040C) #define NVC9B5_OFFSET_OUT_LOWER_VALUE 31:0 #define NVC9B5_PITCH_IN (0x00000410) @@ -145,6 +181,26 @@ extern "C" { #define NVC9B5_LINE_LENGTH_IN_VALUE 31:0 #define NVC9B5_LINE_COUNT (0x0000041C) #define NVC9B5_LINE_COUNT_VALUE 31:0 +#define NVC9B5_SET_SECURE_COPY_MODE (0x00000500) +#define NVC9B5_SET_SECURE_COPY_MODE_MODE 0:0 +#define NVC9B5_SET_SECURE_COPY_MODE_MODE_ENCRYPT (0x00000000) +#define NVC9B5_SET_SECURE_COPY_MODE_MODE_DECRYPT (0x00000001) +#define NVC9B5_SET_DECRYPT_AUTH_TAG_COMPARE_ADDR_UPPER (0x00000514) +#define NVC9B5_SET_DECRYPT_AUTH_TAG_COMPARE_ADDR_UPPER_UPPER 24:0 +#define NVC9B5_SET_DECRYPT_AUTH_TAG_COMPARE_ADDR_LOWER (0x00000518) +#define NVC9B5_SET_DECRYPT_AUTH_TAG_COMPARE_ADDR_LOWER_LOWER 31:0 +#define NVC9B5_SET_ENCRYPT_AUTH_TAG_ADDR_UPPER (0x00000530) +#define NVC9B5_SET_ENCRYPT_AUTH_TAG_ADDR_UPPER_UPPER 24:0 +#define NVC9B5_SET_ENCRYPT_AUTH_TAG_ADDR_LOWER (0x00000534) +#define NVC9B5_SET_ENCRYPT_AUTH_TAG_ADDR_LOWER_LOWER 31:0 +#define NVC9B5_SET_ENCRYPT_IV_ADDR_UPPER (0x00000538) +#define NVC9B5_SET_ENCRYPT_IV_ADDR_UPPER_UPPER 24:0 +#define NVC9B5_SET_ENCRYPT_IV_ADDR_LOWER (0x0000053C) +#define NVC9B5_SET_ENCRYPT_IV_ADDR_LOWER_LOWER 31:0 +#define NVC9B5_SET_MEMORY_SCRUB_PARAMETERS (0x000006FC) +#define NVC9B5_SET_MEMORY_SCRUB_PARAMETERS_DISCARDABLE 0:0 +#define NVC9B5_SET_MEMORY_SCRUB_PARAMETERS_DISCARDABLE_FALSE (0x00000000) +#define NVC9B5_SET_MEMORY_SCRUB_PARAMETERS_DISCARDABLE_TRUE (0x00000001) #define NVC9B5_SET_REMAP_CONST_A (0x00000700) #define NVC9B5_SET_REMAP_CONST_A_V 31:0 #define NVC9B5_SET_REMAP_CONST_B (0x00000704) @@ -216,11 +272,6 @@ extern "C" { #define NVC9B5_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005) #define NVC9B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT 15:12 #define NVC9B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001) -#define NVC9B5_SET_DST_BLOCK_SIZE_GOB_KIND 17:16 -#define NVC9B5_SET_DST_BLOCK_SIZE_GOB_KIND_32 0 -#define NVC9B5_SET_DST_BLOCK_SIZE_GOB_KIND_8 1 -#define NVC9B5_SET_DST_BLOCK_SIZE_GOB_KIND_16 2 -#define NVC9B5_SET_DST_BLOCK_SIZE_GOB_KIND_24 3 #define NVC9B5_SET_DST_WIDTH (0x00000710) #define NVC9B5_SET_DST_WIDTH_V 31:0 #define NVC9B5_SET_DST_HEIGHT (0x00000714) @@ -251,11 +302,6 @@ extern "C" { #define NVC9B5_SET_SRC_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005) #define NVC9B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT 15:12 #define NVC9B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001) -#define NVC9B5_SET_SRC_BLOCK_SIZE_GOB_KIND 17:16 -#define NVC9B5_SET_SRC_BLOCK_SIZE_GOB_KIND_32 0 -#define NVC9B5_SET_SRC_BLOCK_SIZE_GOB_KIND_8 1 -#define NVC9B5_SET_SRC_BLOCK_SIZE_GOB_KIND_16 2 -#define NVC9B5_SET_SRC_BLOCK_SIZE_GOB_KIND_24 3 #define NVC9B5_SET_SRC_WIDTH (0x0000072C) #define NVC9B5_SET_SRC_WIDTH_V 31:0 #define NVC9B5_SET_SRC_HEIGHT (0x00000730) diff --git a/src/nouveau/headers/nvidia/classes/clcab5.h b/src/nouveau/headers/nvidia/classes/clcab5.h new file mode 100644 index 00000000000..b1edf5aecaa --- /dev/null +++ b/src/nouveau/headers/nvidia/classes/clcab5.h @@ -0,0 +1,342 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2004 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#include "nvtypes.h" + +#ifndef _clcab5_h_ +#define _clcab5_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define BLACKWELL_DMA_COPY_B (0x0000CAB5) + +#define NVCAB5_NOP (0x00000100) +#define NVCAB5_NOP_PARAMETER 31:0 +#define NVCAB5_PM_TRIGGER (0x00000140) +#define NVCAB5_PM_TRIGGER_V 31:0 +#define NVCAB5_SET_MONITORED_FENCE_TYPE (0x0000021C) +#define NVCAB5_SET_MONITORED_FENCE_TYPE_TYPE 0:0 +#define NVCAB5_SET_MONITORED_FENCE_TYPE_TYPE_MONITORED_FENCE (0x00000000) +#define NVCAB5_SET_MONITORED_FENCE_TYPE_TYPE_MONITORED_FENCE_EXT (0x00000001) +#define NVCAB5_SET_MONITORED_FENCE_SIGNAL_ADDR_BASE_UPPER (0x00000220) +#define NVCAB5_SET_MONITORED_FENCE_SIGNAL_ADDR_BASE_UPPER_UPPER 24:0 +#define NVCAB5_SET_MONITORED_FENCE_SIGNAL_ADDR_BASE_LOWER (0x00000224) +#define NVCAB5_SET_MONITORED_FENCE_SIGNAL_ADDR_BASE_LOWER_LOWER 31:0 +#define NVCAB5_SET_SEMAPHORE_A (0x00000240) +#define NVCAB5_SET_SEMAPHORE_A_UPPER 24:0 +#define NVCAB5_SET_SEMAPHORE_B (0x00000244) +#define NVCAB5_SET_SEMAPHORE_B_LOWER 31:0 +#define NVCAB5_SET_SEMAPHORE_PAYLOAD (0x00000248) +#define NVCAB5_SET_SEMAPHORE_PAYLOAD_PAYLOAD 31:0 +#define NVCAB5_SET_SEMAPHORE_PAYLOAD_UPPER (0x0000024C) +#define NVCAB5_SET_SEMAPHORE_PAYLOAD_UPPER_PAYLOAD 31:0 +#define NVCAB5_SET_RENDER_ENABLE_A (0x00000254) +#define NVCAB5_SET_RENDER_ENABLE_A_UPPER 24:0 +#define NVCAB5_SET_RENDER_ENABLE_B (0x00000258) +#define NVCAB5_SET_RENDER_ENABLE_B_LOWER 31:0 +#define NVCAB5_SET_RENDER_ENABLE_C (0x0000025C) +#define NVCAB5_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVCAB5_SET_RENDER_ENABLE_C_MODE_FALSE (0x00000000) +#define NVCAB5_SET_RENDER_ENABLE_C_MODE_TRUE (0x00000001) +#define NVCAB5_SET_RENDER_ENABLE_C_MODE_CONDITIONAL (0x00000002) +#define NVCAB5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL (0x00000003) +#define NVCAB5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL (0x00000004) +#define NVCAB5_SET_SRC_PHYS_MODE (0x00000260) +#define NVCAB5_SET_SRC_PHYS_MODE_TARGET 1:0 +#define NVCAB5_SET_SRC_PHYS_MODE_TARGET_LOCAL_FB (0x00000000) +#define NVCAB5_SET_SRC_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001) +#define NVCAB5_SET_SRC_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002) +#define NVCAB5_SET_SRC_PHYS_MODE_TARGET_PEERMEM (0x00000003) +#define NVCAB5_SET_SRC_PHYS_MODE_BASIC_KIND 5:2 +#define NVCAB5_SET_SRC_PHYS_MODE_PEER_ID 8:6 +#define NVCAB5_SET_SRC_PHYS_MODE_FLA 9:9 +#define NVCAB5_SET_DST_PHYS_MODE (0x00000264) +#define NVCAB5_SET_DST_PHYS_MODE_TARGET 1:0 +#define NVCAB5_SET_DST_PHYS_MODE_TARGET_LOCAL_FB (0x00000000) +#define NVCAB5_SET_DST_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001) +#define NVCAB5_SET_DST_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002) +#define NVCAB5_SET_DST_PHYS_MODE_TARGET_PEERMEM (0x00000003) +#define NVCAB5_SET_DST_PHYS_MODE_BASIC_KIND 5:2 +#define NVCAB5_SET_DST_PHYS_MODE_PEER_ID 8:6 +#define NVCAB5_SET_DST_PHYS_MODE_FLA 9:9 +#define NVCAB5_LAUNCH_DMA (0x00000300) +#define NVCAB5_LAUNCH_DMA_DATA_TRANSFER_TYPE 1:0 +#define NVCAB5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NONE (0x00000000) +#define NVCAB5_LAUNCH_DMA_DATA_TRANSFER_TYPE_PIPELINED (0x00000001) +#define NVCAB5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NON_PIPELINED (0x00000002) +#define NVCAB5_LAUNCH_DMA_DATA_TRANSFER_TYPE_PREFETCH (0x00000003) +#define NVCAB5_LAUNCH_DMA_FLUSH_ENABLE 2:2 +#define NVCAB5_LAUNCH_DMA_FLUSH_ENABLE_FALSE (0x00000000) +#define NVCAB5_LAUNCH_DMA_FLUSH_ENABLE_TRUE (0x00000001) +#define NVCAB5_LAUNCH_DMA_FLUSH_TYPE 25:25 +#define NVCAB5_LAUNCH_DMA_FLUSH_TYPE_SYS (0x00000000) +#define NVCAB5_LAUNCH_DMA_FLUSH_TYPE_GL (0x00000001) +#define NVCAB5_LAUNCH_DMA_SEMAPHORE_TYPE 4:3 +#define NVCAB5_LAUNCH_DMA_SEMAPHORE_TYPE_NONE (0x00000000) +#define NVCAB5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_SEMAPHORE_NO_TIMESTAMP (0x00000001) +#define NVCAB5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_SEMAPHORE_WITH_TIMESTAMP (0x00000002) +#define NVCAB5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_ONE_WORD_SEMAPHORE (0x00000001) +#define NVCAB5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_FOUR_WORD_SEMAPHORE (0x00000002) +#define NVCAB5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_CONDITIONAL_INTR_SEMAPHORE (0x00000003) +#define NVCAB5_LAUNCH_DMA_INTERRUPT_TYPE 6:5 +#define NVCAB5_LAUNCH_DMA_INTERRUPT_TYPE_NONE (0x00000000) +#define NVCAB5_LAUNCH_DMA_INTERRUPT_TYPE_BLOCKING (0x00000001) +#define NVCAB5_LAUNCH_DMA_INTERRUPT_TYPE_NON_BLOCKING (0x00000002) +#define NVCAB5_LAUNCH_DMA_SRC_MEMORY_LAYOUT 7:7 +#define NVCAB5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NVCAB5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_PITCH (0x00000001) +#define NVCAB5_LAUNCH_DMA_DST_MEMORY_LAYOUT 8:8 +#define NVCAB5_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NVCAB5_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH (0x00000001) +#define NVCAB5_LAUNCH_DMA_MULTI_LINE_ENABLE 9:9 +#define NVCAB5_LAUNCH_DMA_MULTI_LINE_ENABLE_FALSE (0x00000000) +#define NVCAB5_LAUNCH_DMA_MULTI_LINE_ENABLE_TRUE (0x00000001) +#define NVCAB5_LAUNCH_DMA_REMAP_ENABLE 10:10 +#define NVCAB5_LAUNCH_DMA_REMAP_ENABLE_FALSE (0x00000000) +#define NVCAB5_LAUNCH_DMA_REMAP_ENABLE_TRUE (0x00000001) +#define NVCAB5_LAUNCH_DMA_SRC_TYPE 12:12 +#define NVCAB5_LAUNCH_DMA_SRC_TYPE_VIRTUAL (0x00000000) +#define NVCAB5_LAUNCH_DMA_SRC_TYPE_PHYSICAL (0x00000001) +#define NVCAB5_LAUNCH_DMA_DST_TYPE 13:13 +#define NVCAB5_LAUNCH_DMA_DST_TYPE_VIRTUAL (0x00000000) +#define NVCAB5_LAUNCH_DMA_DST_TYPE_PHYSICAL (0x00000001) +#define NVCAB5_LAUNCH_DMA_SEMAPHORE_REDUCTION 17:14 +#define NVCAB5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMIN (0x00000000) +#define NVCAB5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMAX (0x00000001) +#define NVCAB5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IXOR (0x00000002) +#define NVCAB5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IAND (0x00000003) +#define NVCAB5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IOR (0x00000004) +#define NVCAB5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IADD (0x00000005) +#define NVCAB5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INC (0x00000006) +#define NVCAB5_LAUNCH_DMA_SEMAPHORE_REDUCTION_DEC (0x00000007) +#define NVCAB5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INVALIDA (0x00000008) +#define NVCAB5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INVALIDB (0x00000009) +#define NVCAB5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FADD (0x0000000A) +#define NVCAB5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FMIN (0x0000000B) +#define NVCAB5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FMAX (0x0000000C) +#define NVCAB5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INVALIDC (0x0000000D) +#define NVCAB5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INVALIDD (0x0000000E) +#define NVCAB5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INVALIDE (0x0000000F) +#define NVCAB5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN 18:18 +#define NVCAB5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_SIGNED (0x00000000) +#define NVCAB5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_UNSIGNED (0x00000001) +#define NVCAB5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE 19:19 +#define NVCAB5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_FALSE (0x00000000) +#define NVCAB5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_TRUE (0x00000001) +#define NVCAB5_LAUNCH_DMA_COPY_TYPE 21:20 +#define NVCAB5_LAUNCH_DMA_COPY_TYPE_PROT2PROT (0x00000000) +#define NVCAB5_LAUNCH_DMA_COPY_TYPE_DEFAULT (0x00000000) +#define NVCAB5_LAUNCH_DMA_COPY_TYPE_SECURE (0x00000001) +#define NVCAB5_LAUNCH_DMA_COPY_TYPE_NONPROT2NONPROT (0x00000002) +#define NVCAB5_LAUNCH_DMA_COPY_TYPE_RESERVED (0x00000003) +#define NVCAB5_LAUNCH_DMA_VPRMODE 22:22 +#define NVCAB5_LAUNCH_DMA_VPRMODE_VPR_NONE (0x00000000) +#define NVCAB5_LAUNCH_DMA_VPRMODE_VPR_VID2VID (0x00000001) +#define NVCAB5_LAUNCH_DMA_MEMORY_SCRUB_ENABLE 23:23 +#define NVCAB5_LAUNCH_DMA_MEMORY_SCRUB_ENABLE_FALSE (0x00000000) +#define NVCAB5_LAUNCH_DMA_MEMORY_SCRUB_ENABLE_TRUE (0x00000001) +#define NVCAB5_LAUNCH_DMA_RESERVED_START_OF_COPY 24:24 +#define NVCAB5_LAUNCH_DMA_DISABLE_PLC 26:26 +#define NVCAB5_LAUNCH_DMA_DISABLE_PLC_FALSE (0x00000000) +#define NVCAB5_LAUNCH_DMA_DISABLE_PLC_TRUE (0x00000001) +#define NVCAB5_LAUNCH_DMA_SEMAPHORE_PAYLOAD_SIZE 27:27 +#define NVCAB5_LAUNCH_DMA_SEMAPHORE_PAYLOAD_SIZE_ONE_WORD (0x00000000) +#define NVCAB5_LAUNCH_DMA_SEMAPHORE_PAYLOAD_SIZE_TWO_WORD (0x00000001) +#define NVCAB5_LAUNCH_DMA_RESERVED_ERR_CODE 31:28 +#define NVCAB5_OFFSET_IN_UPPER (0x00000400) +#define NVCAB5_OFFSET_IN_UPPER_UPPER 24:0 +#define NVCAB5_OFFSET_IN_LOWER (0x00000404) +#define NVCAB5_OFFSET_IN_LOWER_VALUE 31:0 +#define NVCAB5_OFFSET_OUT_UPPER (0x00000408) +#define NVCAB5_OFFSET_OUT_UPPER_UPPER 24:0 +#define NVCAB5_OFFSET_OUT_LOWER (0x0000040C) +#define NVCAB5_OFFSET_OUT_LOWER_VALUE 31:0 +#define NVCAB5_PITCH_IN (0x00000410) +#define NVCAB5_PITCH_IN_VALUE 31:0 +#define NVCAB5_PITCH_OUT (0x00000414) +#define NVCAB5_PITCH_OUT_VALUE 31:0 +#define NVCAB5_LINE_LENGTH_IN (0x00000418) +#define NVCAB5_LINE_LENGTH_IN_VALUE 31:0 +#define NVCAB5_LINE_COUNT (0x0000041C) +#define NVCAB5_LINE_COUNT_VALUE 31:0 +#define NVCAB5_SET_SECURE_COPY_MODE (0x00000500) +#define NVCAB5_SET_SECURE_COPY_MODE_MODE 0:0 +#define NVCAB5_SET_SECURE_COPY_MODE_MODE_ENCRYPT (0x00000000) +#define NVCAB5_SET_SECURE_COPY_MODE_MODE_DECRYPT (0x00000001) +#define NVCAB5_SET_DECRYPT_AUTH_TAG_COMPARE_ADDR_UPPER (0x00000514) +#define NVCAB5_SET_DECRYPT_AUTH_TAG_COMPARE_ADDR_UPPER_UPPER 24:0 +#define NVCAB5_SET_DECRYPT_AUTH_TAG_COMPARE_ADDR_LOWER (0x00000518) +#define NVCAB5_SET_DECRYPT_AUTH_TAG_COMPARE_ADDR_LOWER_LOWER 31:0 +#define NVCAB5_SET_ENCRYPT_AUTH_TAG_ADDR_UPPER (0x00000530) +#define NVCAB5_SET_ENCRYPT_AUTH_TAG_ADDR_UPPER_UPPER 24:0 +#define NVCAB5_SET_ENCRYPT_AUTH_TAG_ADDR_LOWER (0x00000534) +#define NVCAB5_SET_ENCRYPT_AUTH_TAG_ADDR_LOWER_LOWER 31:0 +#define NVCAB5_SET_ENCRYPT_IV_ADDR_UPPER (0x00000538) +#define NVCAB5_SET_ENCRYPT_IV_ADDR_UPPER_UPPER 24:0 +#define NVCAB5_SET_ENCRYPT_IV_ADDR_LOWER (0x0000053C) +#define NVCAB5_SET_ENCRYPT_IV_ADDR_LOWER_LOWER 31:0 +#define NVCAB5_SET_MEMORY_SCRUB_PARAMETERS (0x000006FC) +#define NVCAB5_SET_MEMORY_SCRUB_PARAMETERS_DISCARDABLE 0:0 +#define NVCAB5_SET_MEMORY_SCRUB_PARAMETERS_DISCARDABLE_FALSE (0x00000000) +#define NVCAB5_SET_MEMORY_SCRUB_PARAMETERS_DISCARDABLE_TRUE (0x00000001) +#define NVCAB5_SET_REMAP_CONST_A (0x00000700) +#define NVCAB5_SET_REMAP_CONST_A_V 31:0 +#define NVCAB5_SET_REMAP_CONST_B (0x00000704) +#define NVCAB5_SET_REMAP_CONST_B_V 31:0 +#define NVCAB5_SET_REMAP_COMPONENTS (0x00000708) +#define NVCAB5_SET_REMAP_COMPONENTS_DST_X 2:0 +#define NVCAB5_SET_REMAP_COMPONENTS_DST_X_SRC_X (0x00000000) +#define NVCAB5_SET_REMAP_COMPONENTS_DST_X_SRC_Y (0x00000001) +#define NVCAB5_SET_REMAP_COMPONENTS_DST_X_SRC_Z (0x00000002) +#define NVCAB5_SET_REMAP_COMPONENTS_DST_X_SRC_W (0x00000003) +#define NVCAB5_SET_REMAP_COMPONENTS_DST_X_CONST_A (0x00000004) +#define NVCAB5_SET_REMAP_COMPONENTS_DST_X_CONST_B (0x00000005) +#define NVCAB5_SET_REMAP_COMPONENTS_DST_X_NO_WRITE (0x00000006) +#define NVCAB5_SET_REMAP_COMPONENTS_DST_Y 6:4 +#define NVCAB5_SET_REMAP_COMPONENTS_DST_Y_SRC_X (0x00000000) +#define NVCAB5_SET_REMAP_COMPONENTS_DST_Y_SRC_Y (0x00000001) +#define NVCAB5_SET_REMAP_COMPONENTS_DST_Y_SRC_Z (0x00000002) +#define NVCAB5_SET_REMAP_COMPONENTS_DST_Y_SRC_W (0x00000003) +#define NVCAB5_SET_REMAP_COMPONENTS_DST_Y_CONST_A (0x00000004) +#define NVCAB5_SET_REMAP_COMPONENTS_DST_Y_CONST_B (0x00000005) +#define NVCAB5_SET_REMAP_COMPONENTS_DST_Y_NO_WRITE (0x00000006) +#define NVCAB5_SET_REMAP_COMPONENTS_DST_Z 10:8 +#define NVCAB5_SET_REMAP_COMPONENTS_DST_Z_SRC_X (0x00000000) +#define NVCAB5_SET_REMAP_COMPONENTS_DST_Z_SRC_Y (0x00000001) +#define NVCAB5_SET_REMAP_COMPONENTS_DST_Z_SRC_Z (0x00000002) +#define NVCAB5_SET_REMAP_COMPONENTS_DST_Z_SRC_W (0x00000003) +#define NVCAB5_SET_REMAP_COMPONENTS_DST_Z_CONST_A (0x00000004) +#define NVCAB5_SET_REMAP_COMPONENTS_DST_Z_CONST_B (0x00000005) +#define NVCAB5_SET_REMAP_COMPONENTS_DST_Z_NO_WRITE (0x00000006) +#define NVCAB5_SET_REMAP_COMPONENTS_DST_W 14:12 +#define NVCAB5_SET_REMAP_COMPONENTS_DST_W_SRC_X (0x00000000) +#define NVCAB5_SET_REMAP_COMPONENTS_DST_W_SRC_Y (0x00000001) +#define NVCAB5_SET_REMAP_COMPONENTS_DST_W_SRC_Z (0x00000002) +#define NVCAB5_SET_REMAP_COMPONENTS_DST_W_SRC_W (0x00000003) +#define NVCAB5_SET_REMAP_COMPONENTS_DST_W_CONST_A (0x00000004) +#define NVCAB5_SET_REMAP_COMPONENTS_DST_W_CONST_B (0x00000005) +#define NVCAB5_SET_REMAP_COMPONENTS_DST_W_NO_WRITE (0x00000006) +#define NVCAB5_SET_REMAP_COMPONENTS_COMPONENT_SIZE 17:16 +#define NVCAB5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_ONE (0x00000000) +#define NVCAB5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_TWO (0x00000001) +#define NVCAB5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_THREE (0x00000002) +#define NVCAB5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_FOUR (0x00000003) +#define NVCAB5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS 21:20 +#define NVCAB5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_ONE (0x00000000) +#define NVCAB5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_TWO (0x00000001) +#define NVCAB5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_THREE (0x00000002) +#define NVCAB5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_FOUR (0x00000003) +#define NVCAB5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS 25:24 +#define NVCAB5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_ONE (0x00000000) +#define NVCAB5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_TWO (0x00000001) +#define NVCAB5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_THREE (0x00000002) +#define NVCAB5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_FOUR (0x00000003) +#define NVCAB5_SET_DST_BLOCK_SIZE (0x0000070C) +#define NVCAB5_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVCAB5_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB (0x00000000) +#define NVCAB5_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVCAB5_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB (0x00000000) +#define NVCAB5_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS (0x00000001) +#define NVCAB5_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS (0x00000002) +#define NVCAB5_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVCAB5_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVCAB5_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVCAB5_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVCAB5_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB (0x00000000) +#define NVCAB5_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS (0x00000001) +#define NVCAB5_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS (0x00000002) +#define NVCAB5_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS (0x00000003) +#define NVCAB5_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS (0x00000004) +#define NVCAB5_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005) +#define NVCAB5_SET_DST_BLOCK_SIZE_GOB_HEIGHT 15:12 +#define NVCAB5_SET_DST_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001) +#define NVCAB5_SET_DST_BLOCK_SIZE_KIND_BPP 17:16 +#define NVCAB5_SET_DST_BLOCK_SIZE_KIND_BPP_BL_32 (0x00000000) +#define NVCAB5_SET_DST_BLOCK_SIZE_KIND_BPP_BL_8 (0x00000001) +#define NVCAB5_SET_DST_BLOCK_SIZE_KIND_BPP_BL_16 (0x00000002) +#define NVCAB5_SET_DST_BLOCK_SIZE_KIND_BPP_BL_24 (0x00000003) +#define NVCAB5_SET_DST_WIDTH (0x00000710) +#define NVCAB5_SET_DST_WIDTH_V 31:0 +#define NVCAB5_SET_DST_HEIGHT (0x00000714) +#define NVCAB5_SET_DST_HEIGHT_V 31:0 +#define NVCAB5_SET_DST_DEPTH (0x00000718) +#define NVCAB5_SET_DST_DEPTH_V 31:0 +#define NVCAB5_SET_DST_LAYER (0x0000071C) +#define NVCAB5_SET_DST_LAYER_V 31:0 +#define NVCAB5_SET_DST_ORIGIN (0x00000720) +#define NVCAB5_SET_DST_ORIGIN_X 15:0 +#define NVCAB5_SET_DST_ORIGIN_Y 31:16 +#define NVCAB5_SET_SRC_BLOCK_SIZE (0x00000728) +#define NVCAB5_SET_SRC_BLOCK_SIZE_WIDTH 3:0 +#define NVCAB5_SET_SRC_BLOCK_SIZE_WIDTH_ONE_GOB (0x00000000) +#define NVCAB5_SET_SRC_BLOCK_SIZE_HEIGHT 7:4 +#define NVCAB5_SET_SRC_BLOCK_SIZE_HEIGHT_ONE_GOB (0x00000000) +#define NVCAB5_SET_SRC_BLOCK_SIZE_HEIGHT_TWO_GOBS (0x00000001) +#define NVCAB5_SET_SRC_BLOCK_SIZE_HEIGHT_FOUR_GOBS (0x00000002) +#define NVCAB5_SET_SRC_BLOCK_SIZE_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVCAB5_SET_SRC_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVCAB5_SET_SRC_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVCAB5_SET_SRC_BLOCK_SIZE_DEPTH 11:8 +#define NVCAB5_SET_SRC_BLOCK_SIZE_DEPTH_ONE_GOB (0x00000000) +#define NVCAB5_SET_SRC_BLOCK_SIZE_DEPTH_TWO_GOBS (0x00000001) +#define NVCAB5_SET_SRC_BLOCK_SIZE_DEPTH_FOUR_GOBS (0x00000002) +#define NVCAB5_SET_SRC_BLOCK_SIZE_DEPTH_EIGHT_GOBS (0x00000003) +#define NVCAB5_SET_SRC_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS (0x00000004) +#define NVCAB5_SET_SRC_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005) +#define NVCAB5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT 15:12 +#define NVCAB5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001) +#define NVCAB5_SET_SRC_BLOCK_SIZE_KIND_BPP 17:16 +#define NVCAB5_SET_SRC_BLOCK_SIZE_KIND_BPP_BL_32 (0x00000000) +#define NVCAB5_SET_SRC_BLOCK_SIZE_KIND_BPP_BL_8 (0x00000001) +#define NVCAB5_SET_SRC_BLOCK_SIZE_KIND_BPP_BL_16 (0x00000002) +#define NVCAB5_SET_SRC_BLOCK_SIZE_KIND_BPP_BL_24 (0x00000003) +#define NVCAB5_SET_SRC_WIDTH (0x0000072C) +#define NVCAB5_SET_SRC_WIDTH_V 31:0 +#define NVCAB5_SET_SRC_HEIGHT (0x00000730) +#define NVCAB5_SET_SRC_HEIGHT_V 31:0 +#define NVCAB5_SET_SRC_DEPTH (0x00000734) +#define NVCAB5_SET_SRC_DEPTH_V 31:0 +#define NVCAB5_SET_SRC_LAYER (0x00000738) +#define NVCAB5_SET_SRC_LAYER_V 31:0 +#define NVCAB5_SET_SRC_ORIGIN (0x0000073C) +#define NVCAB5_SET_SRC_ORIGIN_X 15:0 +#define NVCAB5_SET_SRC_ORIGIN_Y 31:16 +#define NVCAB5_SRC_ORIGIN_X (0x00000744) +#define NVCAB5_SRC_ORIGIN_X_VALUE 31:0 +#define NVCAB5_SRC_ORIGIN_Y (0x00000748) +#define NVCAB5_SRC_ORIGIN_Y_VALUE 31:0 +#define NVCAB5_DST_ORIGIN_X (0x0000074C) +#define NVCAB5_DST_ORIGIN_X_VALUE 31:0 +#define NVCAB5_DST_ORIGIN_Y (0x00000750) +#define NVCAB5_DST_ORIGIN_Y_VALUE 31:0 +#define NVCAB5_PM_TRIGGER_END (0x00001114) +#define NVCAB5_PM_TRIGGER_END_V 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clcab5_h + diff --git a/src/nouveau/vulkan/nvk_cmd_copy.c b/src/nouveau/vulkan/nvk_cmd_copy.c index 3510e36ad39..e8c6b492b72 100644 --- a/src/nouveau/vulkan/nvk_cmd_copy.c +++ b/src/nouveau/vulkan/nvk_cmd_copy.c @@ -19,7 +19,7 @@ #include "nv_push_cl902d.h" #include "nv_push_cl90b5.h" #include "nv_push_clc1b5.h" -#include "nv_push_clc9b5.h" +#include "nv_push_clcab5.h" static inline uint16_t nvk_cmd_buffer_copy_cls(struct nvk_cmd_buffer *cmd) @@ -171,16 +171,18 @@ to_90b5_remap_num_comps(uint8_t num_comps) } static uint32_t -nil_to_nvc9b5_gob_type(enum nil_gob_type gob_type) +nil_to_nvcab5_gob_type(enum nil_gob_type gob_type) { +#define NVCAB5_GOB_KIND(NV) NVCAB5_SET_SRC_BLOCK_SIZE_KIND_BPP_BL_##NV switch (gob_type) { - case NIL_GOB_TYPE_TURING_COLOR2_D: return 0; - case NIL_GOB_TYPE_BLACKWELL8_BIT: return 1; - case NIL_GOB_TYPE_BLACKWELL16_BIT: return 2; - case NIL_GOB_TYPE_BLACKWELL_Z24: return 3; + case NIL_GOB_TYPE_TURING_COLOR2_D: return NVCAB5_GOB_KIND(32); + case NIL_GOB_TYPE_BLACKWELL8_BIT: return NVCAB5_GOB_KIND(8); + case NIL_GOB_TYPE_BLACKWELL16_BIT: return NVCAB5_GOB_KIND(16); + case NIL_GOB_TYPE_BLACKWELL_Z24: return NVCAB5_GOB_KIND(24); default: unreachable("Invalid GOB type on Blackwell+"); } +#undef NVCAB5_GOB_KIND } static void @@ -257,13 +259,13 @@ nouveau_copy_rect(struct nvk_cmd_buffer *cmd, struct nouveau_copy *copy) P_MTHD(p, NV90B5, SET_SRC_BLOCK_SIZE); assert(nil_gob_type_height(copy->src.tiling.gob_type) == 8); - if (nvk_cmd_buffer_copy_cls(cmd) >= BLACKWELL_DMA_COPY_A) { - P_NVC9B5_SET_SRC_BLOCK_SIZE(p, { + if (nvk_cmd_buffer_copy_cls(cmd) >= BLACKWELL_DMA_COPY_B) { + P_NVCAB5_SET_SRC_BLOCK_SIZE(p, { .width = 0, /* Tiles are always 1 GOB wide */ .height = copy->src.tiling.y_log2, .depth = copy->src.tiling.z_log2, .gob_height = GOB_HEIGHT_GOB_HEIGHT_FERMI_8, - .gob_kind = nil_to_nvc9b5_gob_type(copy->src.tiling.gob_type), + .kind_bpp = nil_to_nvcab5_gob_type(copy->src.tiling.gob_type), }); } else { P_NV90B5_SET_SRC_BLOCK_SIZE(p, { @@ -307,13 +309,13 @@ nouveau_copy_rect(struct nvk_cmd_buffer *cmd, struct nouveau_copy *copy) if (copy->dst.tiling.gob_type != NIL_GOB_TYPE_LINEAR) { P_MTHD(p, NV90B5, SET_DST_BLOCK_SIZE); assert(nil_gob_type_height(copy->dst.tiling.gob_type) == 8); - if (nvk_cmd_buffer_copy_cls(cmd) >= BLACKWELL_DMA_COPY_A) { - P_NVC9B5_SET_DST_BLOCK_SIZE(p, { + if (nvk_cmd_buffer_copy_cls(cmd) >= BLACKWELL_DMA_COPY_B) { + P_NVCAB5_SET_DST_BLOCK_SIZE(p, { .width = 0, /* Tiles are always 1 GOB wide */ .height = copy->dst.tiling.y_log2, .depth = copy->dst.tiling.z_log2, .gob_height = GOB_HEIGHT_GOB_HEIGHT_FERMI_8, - .gob_kind = nil_to_nvc9b5_gob_type(copy->dst.tiling.gob_type), + .kind_bpp = nil_to_nvcab5_gob_type(copy->dst.tiling.gob_type), }); } else { P_NV90B5_SET_DST_BLOCK_SIZE(p, {