From 18e1c9c542325b2fa108cd362120097abafcc524 Mon Sep 17 00:00:00 2001 From: Caio Oliveira Date: Tue, 18 May 2021 10:58:26 -0700 Subject: [PATCH] intel/compiler: Don't stage Task/Mesh outputs in registers Since the outputs are shared among the whole workgroup, these can't be staged in registers as they will not be always visible for all the invocations (to read/flush). If they ever need to be staged, we should use SLM for that. Reviewed-by: Lionel Landwerlin Part-of: --- src/intel/compiler/brw_fs_nir.cpp | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index a6b13456ce5..c69c73f0c9f 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++ b/src/intel/compiler/brw_fs_nir.cpp @@ -53,7 +53,10 @@ fs_visitor::emit_nir_code() void fs_visitor::nir_setup_outputs() { - if (stage == MESA_SHADER_TESS_CTRL || stage == MESA_SHADER_FRAGMENT) + if (stage == MESA_SHADER_TESS_CTRL || + stage == MESA_SHADER_TASK || + stage == MESA_SHADER_MESH || + stage == MESA_SHADER_FRAGMENT) return; unsigned vec4s[VARYING_SLOT_TESS_MAX] = { 0, };