aco: Skip 2nd read of merged wave info when TCS in/out vertices are equal.
When TCS has an equal number of input and output, it means that the number of VS and TCS invocations (LS and HS) are the same; and that the HS invocations operate on the same vertices as the LS. When this is the case, this commit removes the else-if between the merged VS and TCS halves, making it possible to schedule and optimize the code accross the two halves. Totals: SGPRS: 5577367 -> 5581735 (0.08 %) VGPRS: 3958592 -> 3960752 (0.05 %) Code Size: 254867144 -> 254838244 (-0.01 %) bytes Max Waves: 1053887 -> 1053747 (-0.01 %) Totals from affected shaders: SGPRS: 29032 -> 33400 (15.05 %) VGPRS: 35664 -> 37824 (6.06 %) Code Size: 1979028 -> 1950128 (-1.46 %) bytes Max Waves: 7310 -> 7170 (-1.92 %) Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Rhys Perry <pendingchaos02@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4165>
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@@ -100,6 +100,7 @@ struct isel_context {
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unsigned tcs_tess_lvl_in_loc;
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uint32_t tcs_num_inputs;
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uint32_t tcs_num_patches;
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bool tcs_in_out_eq = false;
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/* VS, FS or GS output information */
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output_state outputs;
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@@ -899,6 +900,15 @@ setup_tcs_variables(isel_context *ctx, nir_shader *nir)
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unreachable("Unsupported TCS shader stage");
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}
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/* When the number of TCS input and output vertices are the same (typically 3):
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* - There is an equal amount of LS and HS invocations
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* - In case of merged LSHS shaders, the LS and HS halves of the shader
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* always process the exact same vertex. We can use this knowledge to optimize them.
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*/
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ctx->tcs_in_out_eq =
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ctx->stage == vertex_tess_control_hs &&
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ctx->args->options->key.tcs.input_vertices == nir->info.tess.tcs_vertices_out;
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ctx->tcs_num_patches = get_tcs_num_patches(
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ctx->args->options->key.tcs.input_vertices,
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nir->info.tess.tcs_vertices_out,
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