aco: Skip 2nd read of merged wave info when TCS in/out vertices are equal.

When TCS has an equal number of input and output, it means that the
number of VS and TCS invocations (LS and HS) are the same; and that
the HS invocations operate on the same vertices as the LS.

When this is the case, this commit removes the else-if between
the merged VS and TCS halves, making it possible to schedule
and optimize the code accross the two halves.

Totals:
SGPRS: 5577367 -> 5581735 (0.08 %)
VGPRS: 3958592 -> 3960752 (0.05 %)
Code Size: 254867144 -> 254838244 (-0.01 %) bytes
Max Waves: 1053887 -> 1053747 (-0.01 %)

Totals from affected shaders:
SGPRS: 29032 -> 33400 (15.05 %)
VGPRS: 35664 -> 37824 (6.06 %)
Code Size: 1979028 -> 1950128 (-1.46 %) bytes
Max Waves: 7310 -> 7170 (-1.92 %)

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4165>
This commit is contained in:
Timur Kristóf
2020-03-12 19:54:16 +01:00
committed by Marge Bot
parent 4ec48440a0
commit 17c779ab9e
2 changed files with 18 additions and 6 deletions
@@ -100,6 +100,7 @@ struct isel_context {
unsigned tcs_tess_lvl_in_loc;
uint32_t tcs_num_inputs;
uint32_t tcs_num_patches;
bool tcs_in_out_eq = false;
/* VS, FS or GS output information */
output_state outputs;
@@ -899,6 +900,15 @@ setup_tcs_variables(isel_context *ctx, nir_shader *nir)
unreachable("Unsupported TCS shader stage");
}
/* When the number of TCS input and output vertices are the same (typically 3):
* - There is an equal amount of LS and HS invocations
* - In case of merged LSHS shaders, the LS and HS halves of the shader
* always process the exact same vertex. We can use this knowledge to optimize them.
*/
ctx->tcs_in_out_eq =
ctx->stage == vertex_tess_control_hs &&
ctx->args->options->key.tcs.input_vertices == nir->info.tess.tcs_vertices_out;
ctx->tcs_num_patches = get_tcs_num_patches(
ctx->args->options->key.tcs.input_vertices,
nir->info.tess.tcs_vertices_out,