From 17c20ceda7550e65985c0e0e2f59cef913ba72bd Mon Sep 17 00:00:00 2001 From: Peyton Lee Date: Thu, 12 Oct 2023 14:04:31 +0800 Subject: [PATCH] amd,radeonsi: add libvpe Signed-off-by: Peyton Lee Signed-off-by: Alan Liu Acked-by: Leo Liu Part-of: --- src/amd/meson.build | 4 + src/amd/vpelib/README.md | 33 + src/amd/vpelib/inc/vpe_hw_types.h | 256 + src/amd/vpelib/inc/vpe_types.h | 626 ++ src/amd/vpelib/inc/vpe_version.h | 55 + src/amd/vpelib/inc/vpelib.h | 106 + src/amd/vpelib/meson.build | 146 + .../inc/asic/bringup_vpe_6_1_0_default.h | 872 ++ .../vpe10/inc/asic/bringup_vpe_6_1_0_offset.h | 1663 ++++ .../inc/asic/bringup_vpe_6_1_0_sh_mask.h | 4796 +++++++++++ .../src/chip/vpe10/inc/asic/vpe_1_0_offset.h | 111 + .../src/chip/vpe10/inc/vpe10_background.h | 37 + src/amd/vpelib/src/chip/vpe10/inc/vpe10_cdc.h | 201 + .../src/chip/vpe10/inc/vpe10_cm_common.h | 135 + .../src/chip/vpe10/inc/vpe10_cmd_builder.h | 44 + src/amd/vpelib/src/chip/vpe10/inc/vpe10_dpp.h | 887 +++ src/amd/vpelib/src/chip/vpe10/inc/vpe10_mpc.h | 1460 ++++ src/amd/vpelib/src/chip/vpe10/inc/vpe10_opp.h | 182 + .../src/chip/vpe10/inc/vpe10_resource.h | 80 + .../vpelib/src/chip/vpe10/inc/vpe10_vpec.h | 44 + .../vpelib/src/chip/vpe10/vpe10_background.c | 66 + src/amd/vpelib/src/chip/vpe10/vpe10_cdc.c | 317 + .../vpelib/src/chip/vpe10/vpe10_cm_common.c | 674 ++ .../vpelib/src/chip/vpe10/vpe10_cmd_builder.c | 334 + src/amd/vpelib/src/chip/vpe10/vpe10_dpp.c | 434 + src/amd/vpelib/src/chip/vpe10/vpe10_dpp_cm.c | 289 + .../vpelib/src/chip/vpe10/vpe10_dpp_dscl.c | 383 + src/amd/vpelib/src/chip/vpe10/vpe10_mpc.c | 1321 +++ src/amd/vpelib/src/chip/vpe10/vpe10_opp.c | 220 + .../vpelib/src/chip/vpe10/vpe10_resource.c | 1085 +++ src/amd/vpelib/src/chip/vpe10/vpe10_vpec.c | 63 + src/amd/vpelib/src/core/3dlut_builder.c | 117 + src/amd/vpelib/src/core/background.c | 214 + src/amd/vpelib/src/core/color.c | 887 +++ src/amd/vpelib/src/core/color_bg.c | 363 + src/amd/vpelib/src/core/color_cs.c | 744 ++ src/amd/vpelib/src/core/color_gamma.c | 623 ++ src/amd/vpelib/src/core/color_gamut.c | 459 ++ src/amd/vpelib/src/core/color_table.c | 64 + src/amd/vpelib/src/core/color_test_values.c | 7092 +++++++++++++++++ src/amd/vpelib/src/core/common.c | 591 ++ src/amd/vpelib/src/core/config_writer.c | 256 + src/amd/vpelib/src/core/inc/3dlut_builder.h | 34 + src/amd/vpelib/src/core/inc/background.h | 42 + src/amd/vpelib/src/core/inc/cdc.h | 67 + src/amd/vpelib/src/core/inc/cmd_builder.h | 50 + src/amd/vpelib/src/core/inc/color.h | 247 + src/amd/vpelib/src/core/inc/color_bg.h | 33 + src/amd/vpelib/src/core/inc/color_cs.h | 58 + src/amd/vpelib/src/core/inc/color_gamma.h | 64 + src/amd/vpelib/src/core/inc/color_gamut.h | 40 + src/amd/vpelib/src/core/inc/color_pwl.h | 2330 ++++++ src/amd/vpelib/src/core/inc/color_table.h | 66 + .../vpelib/src/core/inc/color_test_values.h | 48 + src/amd/vpelib/src/core/inc/common.h | 91 + src/amd/vpelib/src/core/inc/config_writer.h | 167 + src/amd/vpelib/src/core/inc/diag_reg_helper.h | 60 + src/amd/vpelib/src/core/inc/dpp.h | 121 + src/amd/vpelib/src/core/inc/hw_shared.h | 193 + src/amd/vpelib/src/core/inc/mpc.h | 183 + src/amd/vpelib/src/core/inc/opp.h | 128 + .../vpelib/src/core/inc/plane_desc_writer.h | 101 + src/amd/vpelib/src/core/inc/reg_helper.h | 275 + src/amd/vpelib/src/core/inc/resource.h | 160 + src/amd/vpelib/src/core/inc/shaper_builder.h | 40 + src/amd/vpelib/src/core/inc/transform.h | 113 + src/amd/vpelib/src/core/inc/vpe_assert.h | 52 + src/amd/vpelib/src/core/inc/vpe_command.h | 206 + src/amd/vpelib/src/core/inc/vpe_desc_writer.h | 70 + src/amd/vpelib/src/core/inc/vpe_priv.h | 262 + .../vpelib/src/core/inc/vpe_visual_confirm.h | 43 + src/amd/vpelib/src/core/inc/vpec.h | 51 + src/amd/vpelib/src/core/mpc.c | 179 + src/amd/vpelib/src/core/plane_desc_writer.c | 143 + src/amd/vpelib/src/core/resource.c | 660 ++ src/amd/vpelib/src/core/shaper_builder.c | 272 + src/amd/vpelib/src/core/vpe_desc_writer.c | 129 + src/amd/vpelib/src/core/vpe_scl_filters.c | 429 + src/amd/vpelib/src/core/vpe_visual_confirm.c | 217 + src/amd/vpelib/src/core/vpelib.c | 658 ++ src/amd/vpelib/src/utils/conversion.c | 100 + src/amd/vpelib/src/utils/custom_float.c | 155 + src/amd/vpelib/src/utils/custom_fp16.c | 312 + src/amd/vpelib/src/utils/fixpt31_32.c | 429 + src/amd/vpelib/src/utils/inc/calc_u64.h | 65 + src/amd/vpelib/src/utils/inc/conversion.h | 43 + src/amd/vpelib/src/utils/inc/custom_float.h | 46 + src/amd/vpelib/src/utils/inc/custom_fp16.h | 59 + src/amd/vpelib/src/utils/inc/fixed31_32.h | 548 ++ src/gallium/drivers/radeonsi/meson.build | 4 +- 90 files changed, 38175 insertions(+), 2 deletions(-) create mode 100644 src/amd/vpelib/README.md create mode 100644 src/amd/vpelib/inc/vpe_hw_types.h create mode 100644 src/amd/vpelib/inc/vpe_types.h create mode 100644 src/amd/vpelib/inc/vpe_version.h create mode 100644 src/amd/vpelib/inc/vpelib.h create mode 100644 src/amd/vpelib/meson.build create mode 100644 src/amd/vpelib/src/chip/vpe10/inc/asic/bringup_vpe_6_1_0_default.h create mode 100644 src/amd/vpelib/src/chip/vpe10/inc/asic/bringup_vpe_6_1_0_offset.h create mode 100644 src/amd/vpelib/src/chip/vpe10/inc/asic/bringup_vpe_6_1_0_sh_mask.h create mode 100644 src/amd/vpelib/src/chip/vpe10/inc/asic/vpe_1_0_offset.h create mode 100644 src/amd/vpelib/src/chip/vpe10/inc/vpe10_background.h create mode 100644 src/amd/vpelib/src/chip/vpe10/inc/vpe10_cdc.h create mode 100644 src/amd/vpelib/src/chip/vpe10/inc/vpe10_cm_common.h create mode 100644 src/amd/vpelib/src/chip/vpe10/inc/vpe10_cmd_builder.h create mode 100644 src/amd/vpelib/src/chip/vpe10/inc/vpe10_dpp.h create mode 100644 src/amd/vpelib/src/chip/vpe10/inc/vpe10_mpc.h create mode 100644 src/amd/vpelib/src/chip/vpe10/inc/vpe10_opp.h create mode 100644 src/amd/vpelib/src/chip/vpe10/inc/vpe10_resource.h create mode 100644 src/amd/vpelib/src/chip/vpe10/inc/vpe10_vpec.h create mode 100644 src/amd/vpelib/src/chip/vpe10/vpe10_background.c create mode 100644 src/amd/vpelib/src/chip/vpe10/vpe10_cdc.c create mode 100644 src/amd/vpelib/src/chip/vpe10/vpe10_cm_common.c create mode 100644 src/amd/vpelib/src/chip/vpe10/vpe10_cmd_builder.c create mode 100644 src/amd/vpelib/src/chip/vpe10/vpe10_dpp.c create mode 100644 src/amd/vpelib/src/chip/vpe10/vpe10_dpp_cm.c create mode 100644 src/amd/vpelib/src/chip/vpe10/vpe10_dpp_dscl.c create mode 100644 src/amd/vpelib/src/chip/vpe10/vpe10_mpc.c create mode 100644 src/amd/vpelib/src/chip/vpe10/vpe10_opp.c create mode 100644 src/amd/vpelib/src/chip/vpe10/vpe10_resource.c create mode 100644 src/amd/vpelib/src/chip/vpe10/vpe10_vpec.c create mode 100644 src/amd/vpelib/src/core/3dlut_builder.c create mode 100644 src/amd/vpelib/src/core/background.c create mode 100644 src/amd/vpelib/src/core/color.c create mode 100644 src/amd/vpelib/src/core/color_bg.c create mode 100644 src/amd/vpelib/src/core/color_cs.c create mode 100644 src/amd/vpelib/src/core/color_gamma.c create mode 100644 src/amd/vpelib/src/core/color_gamut.c create mode 100644 src/amd/vpelib/src/core/color_table.c create mode 100644 src/amd/vpelib/src/core/color_test_values.c create mode 100644 src/amd/vpelib/src/core/common.c create mode 100644 src/amd/vpelib/src/core/config_writer.c create mode 100644 src/amd/vpelib/src/core/inc/3dlut_builder.h create mode 100644 src/amd/vpelib/src/core/inc/background.h create mode 100644 src/amd/vpelib/src/core/inc/cdc.h create mode 100644 src/amd/vpelib/src/core/inc/cmd_builder.h create mode 100644 src/amd/vpelib/src/core/inc/color.h create mode 100644 src/amd/vpelib/src/core/inc/color_bg.h create mode 100644 src/amd/vpelib/src/core/inc/color_cs.h create mode 100644 src/amd/vpelib/src/core/inc/color_gamma.h create mode 100644 src/amd/vpelib/src/core/inc/color_gamut.h create mode 100644 src/amd/vpelib/src/core/inc/color_pwl.h create mode 100644 src/amd/vpelib/src/core/inc/color_table.h create mode 100644 src/amd/vpelib/src/core/inc/color_test_values.h create mode 100644 src/amd/vpelib/src/core/inc/common.h create mode 100644 src/amd/vpelib/src/core/inc/config_writer.h create mode 100644 src/amd/vpelib/src/core/inc/diag_reg_helper.h create mode 100644 src/amd/vpelib/src/core/inc/dpp.h create mode 100644 src/amd/vpelib/src/core/inc/hw_shared.h create mode 100644 src/amd/vpelib/src/core/inc/mpc.h create mode 100644 src/amd/vpelib/src/core/inc/opp.h create mode 100644 src/amd/vpelib/src/core/inc/plane_desc_writer.h create mode 100644 src/amd/vpelib/src/core/inc/reg_helper.h create mode 100644 src/amd/vpelib/src/core/inc/resource.h create mode 100644 src/amd/vpelib/src/core/inc/shaper_builder.h create mode 100644 src/amd/vpelib/src/core/inc/transform.h create mode 100644 src/amd/vpelib/src/core/inc/vpe_assert.h create mode 100644 src/amd/vpelib/src/core/inc/vpe_command.h create mode 100644 src/amd/vpelib/src/core/inc/vpe_desc_writer.h create mode 100644 src/amd/vpelib/src/core/inc/vpe_priv.h create mode 100644 src/amd/vpelib/src/core/inc/vpe_visual_confirm.h create mode 100644 src/amd/vpelib/src/core/inc/vpec.h create mode 100644 src/amd/vpelib/src/core/mpc.c create mode 100644 src/amd/vpelib/src/core/plane_desc_writer.c create mode 100644 src/amd/vpelib/src/core/resource.c create mode 100644 src/amd/vpelib/src/core/shaper_builder.c create mode 100644 src/amd/vpelib/src/core/vpe_desc_writer.c create mode 100644 src/amd/vpelib/src/core/vpe_scl_filters.c create mode 100644 src/amd/vpelib/src/core/vpe_visual_confirm.c create mode 100644 src/amd/vpelib/src/core/vpelib.c create mode 100644 src/amd/vpelib/src/utils/conversion.c create mode 100644 src/amd/vpelib/src/utils/custom_float.c create mode 100644 src/amd/vpelib/src/utils/custom_fp16.c create mode 100644 src/amd/vpelib/src/utils/fixpt31_32.c create mode 100644 src/amd/vpelib/src/utils/inc/calc_u64.h create mode 100644 src/amd/vpelib/src/utils/inc/conversion.h create mode 100644 src/amd/vpelib/src/utils/inc/custom_float.h create mode 100644 src/amd/vpelib/src/utils/inc/custom_fp16.h create mode 100644 src/amd/vpelib/src/utils/inc/fixed31_32.h diff --git a/src/amd/meson.build b/src/amd/meson.build index f1e378154a3..4c0bd4abc5d 100644 --- a/src/amd/meson.build +++ b/src/amd/meson.build @@ -41,3 +41,7 @@ endif if with_tools.contains('drm-shim') subdir('drm-shim') endif + +if with_gallium_radeonsi + subdir('vpelib') +endif diff --git a/src/amd/vpelib/README.md b/src/amd/vpelib/README.md new file mode 100644 index 00000000000..27c7e5ff103 --- /dev/null +++ b/src/amd/vpelib/README.md @@ -0,0 +1,33 @@ +# VPE-LIB + +VPE C library for AMD drivers + +Folder Architecture +=================== +```text +[root] + | + +-- [inc] ## public header to external modules + | + +-- [src] ##internal implementation + | + +-- [chip] ## store chip specific files + | | + | +-- [vpeXX] ## asic specific files e.g. vpe10 + | | + | +-- [inc] ## all headers for vpe[XX] + | | + | +-- [asic] ## store all headers that + | ## could conflict with headers in other asics + | ## src file has to explicitly include the files here + | ## without relying the compilation include directory path + | + | + + -- [core] ## files that share for all asics + | | + | +-- [inc] ## define the base functions that each vpe[xx] should implement + | + -- [utils] ## utility functions like fixed point or u64 calculation + | + +-- [inc] ## utils headers +``` diff --git a/src/amd/vpelib/inc/vpe_hw_types.h b/src/amd/vpelib/inc/vpe_hw_types.h new file mode 100644 index 00000000000..725260688fa --- /dev/null +++ b/src/amd/vpelib/inc/vpe_hw_types.h @@ -0,0 +1,256 @@ +/* Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#pragma once + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*********************************************************************** + * Note: do *not* add any types which are *not* used for HW programming. + * this will ensure separation of Logic layer from HW layer + ***********************************************************************/ +union large_integer { + struct { + uint32_t low_part; + int32_t high_part; + }; + + struct { + uint32_t low_part; + int32_t high_part; + } u; + + int64_t quad_part; +}; + +#define PHYSICAL_ADDRESS_LOC union large_integer + +enum vpe_plane_addr_type { + VPE_PLN_ADDR_TYPE_GRAPHICS = 0, + VPE_PLN_ADDR_TYPE_VIDEO_PROGRESSIVE +}; + +struct vpe_plane_address { + enum vpe_plane_addr_type type; + bool tmz_surface; + union { + struct { + PHYSICAL_ADDRESS_LOC addr; + PHYSICAL_ADDRESS_LOC meta_addr; + union large_integer dcc_const_color; + } grph; + + /*video progressive*/ + struct { + PHYSICAL_ADDRESS_LOC luma_addr; + PHYSICAL_ADDRESS_LOC luma_meta_addr; + union large_integer luma_dcc_const_color; + + PHYSICAL_ADDRESS_LOC chroma_addr; + PHYSICAL_ADDRESS_LOC chroma_meta_addr; + union large_integer chroma_dcc_const_color; + } video_progressive; + }; +}; + +/* Rotation angle */ +enum vpe_rotation_angle { + VPE_ROTATION_ANGLE_0 = 0, + VPE_ROTATION_ANGLE_90, + VPE_ROTATION_ANGLE_180, + VPE_ROTATION_ANGLE_270, + VPE_ROTATION_ANGLE_COUNT +}; + +/* mirror */ +enum vpe_mirror { + VPE_MIRROR_NONE, + VPE_MIRROR_HORIZONTAL, + VPE_MIRROR_VERTICAL +}; + +enum vpe_scan_direction { + VPE_SCAN_DIRECTION_UNKNOWN = 0, + VPE_SCAN_DIRECTION_HORIZONTAL = 1, /* 0, 180 rotation */ + VPE_SCAN_DIRECTION_VERTICAL = 2, /* 90, 270 rotation */ +}; + +struct vpe_size { + uint32_t width; + uint32_t height; +}; + +struct vpe_rect { + int32_t x; + int32_t y; + uint32_t width; + uint32_t height; +}; + +struct vpe_plane_size { + struct vpe_rect surface_size; + struct vpe_rect chroma_size; + + // actual aligned pitch and height + uint32_t surface_pitch; + uint32_t chroma_pitch; + + uint32_t surface_aligned_height; + uint32_t chrome_aligned_height; +}; + +struct vpe_plane_dcc_param { + bool enable; + + uint32_t meta_pitch; + bool independent_64b_blks; + uint8_t dcc_ind_blk; + + uint32_t meta_pitch_c; + bool independent_64b_blks_c; + uint8_t dcc_ind_blk_c; +}; + +/** Displayable pixel format in fb */ +enum vpe_surface_pixel_format { + VPE_SURFACE_PIXEL_FORMAT_GRPH_BEGIN = 0, + /*16 bpp*/ + VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB1555, + /*16 bpp*/ + VPE_SURFACE_PIXEL_FORMAT_GRPH_RGB565, + /*32 bpp*/ + VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB8888, + /*32 bpp swaped*/ + VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR8888, + /*32 bpp alpha rotated*/ + VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBA8888, + /*32 bpp swaped & alpha rotated*/ + VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA8888, + + VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010, + /*swaped*/ + VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010, + /*alpha rotated*/ + VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBA1010102, + /*swaped & alpha rotated*/ + VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA1010102, + + /*64 bpp */ + VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616, + /*float*/ + VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F, + /*swaped & float*/ + VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F, + /*alpha rotated*/ + VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBA16161616F, + /*swaped & alpha rotated*/ + VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA16161616F, + + VPE_SURFACE_PIXEL_FORMAT_GRPH_XRGB8888, + /*swaped*/ + VPE_SURFACE_PIXEL_FORMAT_GRPH_XBGR8888, + /*rotated*/ + VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBX8888, + /*swaped & rotated*/ + VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRX8888, + /*grow graphics here if necessary */ + VPE_SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX, + VPE_SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX, + VPE_SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT, + VPE_SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT, + VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBE, + VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA, + VPE_SURFACE_PIXEL_FORMAT_VIDEO_BEGIN, + VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr = VPE_SURFACE_PIXEL_FORMAT_VIDEO_BEGIN, + VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb, + VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr, + VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb, + VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_16bpc_YCrCb, + VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_CrYCbY, + VPE_SURFACE_PIXEL_FORMAT_SUBSAMPLE_END = VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_CrYCbY, + VPE_SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010, + VPE_SURFACE_PIXEL_FORMAT_VIDEO_CrYCbA1010102, + VPE_SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888, + VPE_SURFACE_PIXEL_FORMAT_VIDEO_AYCbCr8888, + VPE_SURFACE_PIXEL_FORMAT_VIDEO_END = VPE_SURFACE_PIXEL_FORMAT_VIDEO_AYCbCr8888, + VPE_SURFACE_PIXEL_FORMAT_INVALID + + /*grow 444 video here if necessary */ +}; + +enum vpe_swizzle_mode_values { + VPE_SW_LINEAR = 0, + VPE_SW_256B_S = 1, + VPE_SW_256B_D = 2, + VPE_SW_256B_R = 3, + VPE_SW_4KB_Z = 4, + VPE_SW_4KB_S = 5, + VPE_SW_4KB_D = 6, + VPE_SW_4KB_R = 7, + VPE_SW_64KB_Z = 8, + VPE_SW_64KB_S = 9, + VPE_SW_64KB_D = 10, + VPE_SW_64KB_R = 11, + VPE_SW_VAR_Z = 12, + VPE_SW_VAR_S = 13, + VPE_SW_VAR_D = 14, + VPE_SW_VAR_R = 15, + VPE_SW_64KB_Z_T = 16, + VPE_SW_64KB_S_T = 17, + VPE_SW_64KB_D_T = 18, + VPE_SW_64KB_R_T = 19, + VPE_SW_4KB_Z_X = 20, + VPE_SW_4KB_S_X = 21, + VPE_SW_4KB_D_X = 22, + VPE_SW_4KB_R_X = 23, + VPE_SW_64KB_Z_X = 24, + VPE_SW_64KB_S_X = 25, + VPE_SW_64KB_D_X = 26, + VPE_SW_64KB_R_X = 27, + VPE_SW_VAR_Z_X = 28, + VPE_SW_VAR_S_X = 29, + VPE_SW_VAR_D_X = 30, + VPE_SW_VAR_R_X = 31, + VPE_SW_MAX = 32, + VPE_SW_UNKNOWN = VPE_SW_MAX +}; + +/** specify the number of taps. + * if 0 is specified, it will use 4 taps by default */ +struct vpe_scaling_taps { + uint32_t v_taps; + uint32_t h_taps; + uint32_t v_taps_c; + uint32_t h_taps_c; +}; + +#ifdef __cplusplus +} +#endif diff --git a/src/amd/vpelib/inc/vpe_types.h b/src/amd/vpelib/inc/vpe_types.h new file mode 100644 index 00000000000..80e5c8c089f --- /dev/null +++ b/src/amd/vpelib/inc/vpe_types.h @@ -0,0 +1,626 @@ +/* Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#pragma once + +#include +#include +#include +#include +#include "vpe_hw_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct vpe; + +#define MAX_NB_POLYPHASE_COEFFS \ + (8 * 33) /* currently vpe supports up to 8 taps and 64 phases, only (32+1) phases needed*/ + +enum vpe_status { + VPE_STATUS_OK = 1, + VPE_STATUS_ERROR, + VPE_STATUS_NO_MEMORY, + + // errors for not supported operations + VPE_STATUS_NOT_SUPPORTED, + VPE_STATUS_DCC_NOT_SUPPORTED, + VPE_STATUS_SWIZZLE_NOT_SUPPORTED, + VPE_STATUS_NUM_STREAM_NOT_SUPPORTED, + VPE_STATUS_PIXEL_FORMAT_NOT_SUPPORTED, + VPE_STATUS_COLOR_SPACE_VALUE_NOT_SUPPORTED, + VPE_STATUS_SCALING_RATIO_NOT_SUPPORTED, + VPE_STATUS_PITCH_ALIGNMENT_NOT_SUPPORTED, + VPE_STATUS_ROTATION_NOT_SUPPORTED, + VPE_STATUS_MIRROR_NOT_SUPPORTED, + VPE_STATUS_ALPHA_BLENDING_NOT_SUPPORTED, + VPE_STATUS_VIEWPORT_SIZE_NOT_SUPPORTED, + VPE_STATUS_LUMA_KEYING_NOT_SUPPORTED, + VPE_STATUS_PLANE_ADDR_NOT_SUPPORTED, + VPE_STATUS_ADJUSTMENT_NOT_SUPPORTED, + VPE_STATUS_CMD_OVERFLOW_ERROR, + VPE_STATUS_SEGMENT_WIDTH_ERROR, + VPE_STATUS_PARAM_CHECK_ERROR, + VPE_STATUS_TONE_MAP_NOT_SUPPORTED, + VPE_STATUS_BAD_TONE_MAP_PARAMS, + VPE_STATUS_BAD_HDR_METADATA, + VPE_STATUS_BUFFER_OVERFLOW, + VPE_STATUS_BUFFER_UNDERRUN, + VPE_STATUS_BG_COLOR_OUT_OF_RANGE, + VPE_STATUS_REPEAT_ITEM, + VPE_STATUS_PATCH_OVER_MAXSIZE, + VPE_STATUS_INVALID_BUFFER_SIZE, + VPE_STATUS_SCALER_NOT_SET +}; + +/** HW IP level */ +enum vpe_ip_level { + VPE_IP_LEVEL_UNKNOWN = (-1), + VPE_IP_LEVEL_1_0, +}; + +/**************************************** + * Plane Caps + ****************************************/ +struct vpe_pixel_format_support { + uint32_t argb_packed_32b : 1; + uint32_t nv12 : 1; + uint32_t fp16 : 1; + uint32_t p010 : 1; /**< planar 4:2:0 10-bit */ + uint32_t p016 : 1; /**< planar 4:2:0 16-bit */ + uint32_t ayuv : 1; /**< packed 4:4:4 */ + uint32_t yuy2 : 1; /**< packed 4:2:2 */ +}; + +struct vpe_plane_caps { + uint32_t per_pixel_alpha : 1; + + struct vpe_pixel_format_support input_pixel_format_support; + struct vpe_pixel_format_support output_pixel_format_support; + + /* max upscaling factor x 1000 + * upscaling factors are always >= 1 + * e.g. 1080p -> 8K is 4.0 => 4000 + */ + uint32_t max_upscale_factor; + + /* max downscale factor x1000 + * downscale factors are always <= 1 + * e.g 8K -> 1080p is 0.25 => 250 + */ + uint32_t max_downscale_factor; + + uint32_t pitch_alignment; /**< alignment in bytes */ + uint32_t addr_alignment; /**< alignment in bytes */ + uint32_t max_viewport_width; +}; + +/************************* + * Color management caps + *************************/ +struct vpe_rom_curve_caps { + uint32_t srgb : 1; + uint32_t bt2020 : 1; + uint32_t gamma2_2 : 1; + uint32_t pq : 1; + uint32_t hlg : 1; +}; + +struct dpp_color_caps { + uint32_t pre_csc : 1; + uint32_t luma_key : 1; + uint32_t dgam_ram : 1; + uint32_t post_csc : 1; /**< before gamut remap */ + uint32_t gamma_corr : 1; + uint32_t hw_3dlut : 1; + uint32_t ogam_ram : 1; + uint32_t ocsc : 1; + struct vpe_rom_curve_caps dgam_rom_caps; +}; + +struct mpc_color_caps { + uint32_t gamut_remap : 1; + uint32_t ogam_ram : 1; + uint32_t ocsc : 1; + uint32_t shared_3d_lut : 1; /**< can be in either dpp or mpc, but single instance */ + uint32_t global_alpha : 1; /**< e.g. top plane 30 %. bottom 70 % */ + uint32_t top_bottom_blending : 1; /**< two-layer blending */ +}; + +struct vpe_color_caps { + struct dpp_color_caps dpp; + struct mpc_color_caps mpc; +}; + +/************************************************** + * VPE Capabilities. + * + * Those depend on the condition like input format + * shall be queried by vpe_cap_funcs + **************************************************/ +struct vpe_caps { + uint32_t max_downscale_ratio; /**< max downscaling ratio in hundred. + ratio as src/dest x 100. e.g 600 */ + uint64_t lut_size; /**< 3dlut size */ + + uint32_t rotation_support : 1; + uint32_t h_mirror_support : 1; + uint32_t v_mirror_support : 1; + uint32_t is_apu : 1; + uint32_t bg_color_check_support : 1; + struct { + int num_dpp; + int num_opp; + int num_mpc_3dlut; + + int num_queue; /**< num of hw queue */ + } resource_caps; + + struct vpe_color_caps color_caps; + struct vpe_plane_caps plane_caps; +}; + +/*********************************** + * Conditional Capabilities + ***********************************/ +/** DCC CAP */ +struct vpe_dcc_surface_param { + struct vpe_size surface_size; + enum vpe_surface_pixel_format format; + enum vpe_swizzle_mode_values swizzle_mode; + enum vpe_scan_direction scan; +}; + +struct vpe_dcc_setting { + unsigned int max_compressed_blk_size; + unsigned int max_uncompressed_blk_size; + bool independent_64b_blks; + + struct { + uint32_t dcc_256_64_64 : 1; + uint32_t dcc_128_128_uncontrained : 1; + uint32_t dcc_256_128_128 : 1; + uint32_t dcc_256_256_unconstrained : 1; + } dcc_controls; +}; + +struct vpe_surface_dcc_cap { + union { + struct { + struct vpe_dcc_setting rgb; + } grph; + + struct { + struct vpe_dcc_setting luma; + struct vpe_dcc_setting chroma; + } video; + }; + + bool capable; + bool const_color_support; +}; + +/** Conditional Capability functions */ +struct vpe_cap_funcs { + /** + * Get DCC support and setting according to the format, + * scan direction and swizzle mdoe. + * + * @param[in] vpe vpe instance + * @param[in] input surface and scan properties + * @param[in/out] output dcc capable result and related settings + * @return true if supported + */ + bool (*get_dcc_compression_cap)(const struct vpe *vpe, + const struct vpe_dcc_surface_param *input, struct vpe_surface_dcc_cap *output); +}; + +/**************************************** + * VPE Init Param + ****************************************/ +/** Log function + * @param[in] log_ctx given in the struct vpe_init_params + * @param[in] fmt format string + */ +typedef void (*vpe_log_func_t)(void *log_ctx, const char *fmt, ...); + +/** system memory zalloc, allocated memory initailized with 0 + * + * @param[in] mem_ctx given in the struct vpe_init_params + * @param[in] size number of bytes + * @return allocated memory + */ +typedef void *(*vpe_zalloc_func_t)(void *mem_ctx, size_t size); + +/** system memory free + * @param[in] mem_ctx given in the struct vpe_init_params + * @param[in] ptr number of bytes + */ +typedef void (*vpe_free_func_t)(void *mem_ctx, void *ptr); + +struct vpe_callback_funcs { + void *log_ctx; /**< optional. provided by the caller and pass back to callback */ + vpe_log_func_t log; + + void *mem_ctx; /**< optional. provided by the caller and pass back to callback */ + vpe_zalloc_func_t zalloc; + vpe_free_func_t free; +}; + +struct vpe_mem_low_power_enable_options { + // override flags + struct { + uint32_t dscl : 1; + uint32_t cm : 1; + uint32_t mpc : 1; + } flags; + + struct { + uint32_t dscl : 1; + uint32_t cm : 1; + uint32_t mpc : 1; + } bits; +}; + +enum vpe_expansion_mode { + VPE_EXPANSION_MODE_DYNAMIC, + VPE_EXPANSION_MODE_ZERO +}; + +enum vpe_clamping_range { + VPE_CLAMPING_FULL_RANGE = 0, /* No Clamping */ + VPE_CLAMPING_LIMITED_RANGE_8BPC, /* 8 bpc: Clamping 1 to FE */ + VPE_CLAMPING_LIMITED_RANGE_10BPC, /* 10 bpc: Clamping 4 to 3FB */ + VPE_CLAMPING_LIMITED_RANGE_12BPC, /* 12 bpc: Clamping 10 to FEF */ + /* Use programmable clampping value on FMT_CLAMP_COMPONENT_R/G/B. */ + VPE_CLAMPING_LIMITED_RANGE_PROGRAMMABLE +}; + +struct vpe_clamping_params { + enum vpe_clamping_range clamping_range; + uint32_t r_clamp_component_upper; + uint32_t b_clamp_component_upper; + uint32_t g_clamp_component_upper; + uint32_t r_clamp_component_lower; + uint32_t b_clamp_component_lower; + uint32_t g_clamp_component_lower; +}; + +struct vpe_visual_confirm { + union { + struct { + uint32_t input_format : 1; + uint32_t output_format : 1; + uint32_t reserved : 30; + }; + uint32_t value; + }; +}; + +/** configurable params for debugging purpose */ +struct vpe_debug_options { + // override flags + struct { + uint32_t cm_in_bypass : 1; + uint32_t vpcnvc_bypass : 1; + uint32_t mpc_bypass : 1; + uint32_t identity_3dlut : 1; + uint32_t sce_3dlut : 1; + uint32_t disable_reuse_bit : 1; + uint32_t bg_color_fill_only : 1; + uint32_t assert_when_not_support : 1; + uint32_t bypass_gamcor : 1; + uint32_t bypass_ogam : 1; + uint32_t force_tf_calculation : 1; + uint32_t bypass_dpp_gamut_remap : 1; + uint32_t bypass_post_csc : 1; + uint32_t clamping_setting : 1; + uint32_t expansion_mode : 1; + uint32_t bypass_per_pixel_alpha : 1; + uint32_t dpp_crc_ctrl : 1; + uint32_t opp_pipe_crc_ctrl : 1; + uint32_t mpc_crc_ctrl : 1; + uint32_t bg_bit_depth : 1; + uint32_t visual_confirm : 1; + } flags; + + // valid only if the corresponding flag is set + uint32_t cm_in_bypass : 1; + uint32_t vpcnvc_bypass : 1; + uint32_t mpc_bypass : 1; + uint32_t identity_3dlut : 1; + uint32_t sce_3dlut : 1; + uint32_t disable_reuse_bit : 1; + uint32_t bg_color_fill_only : 1; + uint32_t assert_when_not_support : 1; + uint32_t bypass_gamcor : 1; + uint32_t bypass_ogam : 1; + uint32_t force_tf_calculation : 1; + uint32_t bypass_dpp_gamut_remap : 1; + uint32_t bypass_post_csc : 1; + uint32_t clamping_setting : 1; + uint32_t bypass_per_pixel_alpha : 1; + uint32_t dpp_crc_ctrl : 1; + uint32_t opp_pipe_crc_ctrl : 1; + uint32_t mpc_crc_ctrl : 1; + uint32_t bg_bit_depth; + + struct vpe_mem_low_power_enable_options enable_mem_low_power; + enum vpe_expansion_mode expansion_mode; + struct vpe_clamping_params clamping_params; + struct vpe_visual_confirm visual_confirm_params; +}; + +struct vpe_init_data { + /** vpe ip info */ + uint8_t ver_major; + uint8_t ver_minor; + uint8_t ver_rev; + + /** function callbacks */ + struct vpe_callback_funcs funcs; + + /** debug options */ + struct vpe_debug_options debug; +}; + +/** VPE instance created through vpelib entry function vpe_create() */ +struct vpe { + uint32_t version; /**< API version */ + enum vpe_ip_level level; /**< HW IP level */ + + struct vpe_caps *caps; /**< general static chip caps */ + struct vpe_cap_funcs *cap_funcs; /**< conditional caps */ +}; + +/***************************************************** + * Structures for build VPE command + *****************************************************/ +enum vpe_pixel_encoding { + VPE_PIXEL_ENCODING_YCbCr, + VPE_PIXEL_ENCODING_RGB, + VPE_PIXEL_ENCODING_COUNT +}; + +enum vpe_color_range { + VPE_COLOR_RANGE_FULL, + VPE_COLOR_RANGE_STUDIO, + VPE_COLOR_RANGE_COUNT +}; + +enum vpe_chroma_cositing { + VPE_CHROMA_COSITING_NONE, + VPE_CHROMA_COSITING_LEFT, + VPE_CHROMA_COSITING_TOPLEFT, + VPE_CHROMA_COSITING_COUNT +}; + +enum vpe_color_primaries { + VPE_PRIMARIES_BT601, + VPE_PRIMARIES_BT709, + VPE_PRIMARIES_BT2020, + VPE_PRIMARIES_JFIF, + VPE_PRIMARIES_COUNT +}; + +enum vpe_transfer_function { + VPE_TF_G22, + VPE_TF_G24, + VPE_TF_G10, + VPE_TF_PQ, + VPE_TF_PQ_NORMALIZED, + VPE_TF_HLG, + VPE_TF_COUNT +}; + +enum vpe_alpha_mode { + VPE_ALPHA_OPAQUE, + VPE_ALPHA_BGCOLOR +}; + +struct vpe_color_space { + enum vpe_pixel_encoding encoding; + enum vpe_color_range range; + enum vpe_transfer_function tf; + enum vpe_chroma_cositing cositing; + enum vpe_color_primaries primaries; +}; + +/* component values are in the range: 0 - 1.0f */ +struct vpe_color_rgba { + float r; + float g; + float b; + float a; +}; + +struct vpe_color_ycbcra { + float y; + float cb; + float cr; + float a; +}; + +struct vpe_color { + bool is_ycbcr; + union { + struct vpe_color_rgba rgba; + struct vpe_color_ycbcra ycbcra; + }; +}; + +/** + * Adjustment Min Max default step + * Brightness -100.0f, 100.0f, 0.0f, 0.1f + * Contrast 0.0f, 2.0f, 1.0f, 0.01f + * Hue -180.0f, 180.0f, 0.0f, 1.0f + * Saturation 0.0f, 3.0f, 1.0f, 0.01f + * + */ +struct vpe_color_adjust { + float brightness; + float contrast; + float hue; + float saturation; +}; + +struct vpe_surface_info { + + /** surface addressing info */ + struct vpe_plane_address address; + enum vpe_swizzle_mode_values swizzle; + + /** surface properties */ + struct vpe_plane_size plane_size; /**< pitch */ + struct vpe_plane_dcc_param dcc; + enum vpe_surface_pixel_format format; + + struct vpe_color_space cs; +}; + +struct vpe_blend_info { + bool blending; /**< enable blending */ + bool pre_multiplied_alpha; /**< is the pixel value pre-multiplied with alpha */ + bool global_alpha; /**< enable global alpha */ + float global_alpha_value; /**< global alpha value, should be 0.0~1.0 */ +}; + +struct vpe_scaling_info { + + struct vpe_rect src_rect; + struct vpe_rect dst_rect; + struct vpe_scaling_taps taps; +}; + +struct vpe_scaling_filter_coeffs { + + struct vpe_scaling_taps taps; + unsigned int nb_phases; + uint16_t horiz_polyphase_coeffs[MAX_NB_POLYPHASE_COEFFS]; /*max nb of taps is 4, max nb of + phases 33 = (32+1)*/ + uint16_t vert_polyphase_coeffs[MAX_NB_POLYPHASE_COEFFS]; /*max nb of taps is 4, max nb of phases + 33 = (32+1)*/ +}; + +struct vpe_hdr_metadata { + uint16_t redX; + uint16_t redY; + uint16_t greenX; + uint16_t greenY; + uint16_t blueX; + uint16_t blueY; + uint16_t whiteX; + uint16_t whiteY; + + uint32_t min_mastering; // luminance in 1/10000 nits + uint32_t max_mastering; // luminance in nits + uint32_t max_content; + uint32_t avg_content; +}; + +struct vpe_tonemap_params { + enum vpe_transfer_function shaper_tf; + enum vpe_transfer_function lut_out_tf; + enum vpe_color_primaries lut_in_gamut; + enum vpe_color_primaries lut_out_gamut; + uint16_t lut_dim; + uint16_t *lut_data; + + bool update_3dlut; + bool enable_3dlut; +}; + +struct vpe_stream { + struct vpe_surface_info surface_info; + struct vpe_scaling_info scaling_info; + struct vpe_blend_info blend_info; + struct vpe_color_adjust color_adj; + struct vpe_tonemap_params tm_params; + struct vpe_hdr_metadata hdr_metadata; + struct vpe_scaling_filter_coeffs polyphase_scaling_coeffs; + enum vpe_rotation_angle rotation; + bool horizontal_mirror; + bool vertical_mirror; + bool use_external_scaling_coeffs; + bool enable_luma_key; + float lower_luma_bound; + float upper_luma_bound; + + struct { + uint32_t hdr_metadata : 1; + uint32_t reserved : 31; + } flags; +}; + +struct vpe_build_param { + /** source */ + uint32_t num_streams; + struct vpe_stream *streams; + + /** destination */ + struct vpe_surface_info dst_surface; + struct vpe_rect target_rect; /**< rectangle in target surface to be blt'd. Ranges out of rect + won't be touched */ + struct vpe_color bg_color; + enum vpe_alpha_mode alpha_mode; + struct vpe_hdr_metadata hdr_metadata; + + // data flags + struct { + uint32_t hdr_metadata : 1; + uint32_t reserved : 31; + } flags; + +}; + +/** reported through vpe_check_support() + * Once the operation is supported, + * it returns the required memory for storing + * 1. command buffer + * 2. embedded buffer + * - Pointed by the command buffer content. + * - Shall be free'ed together with command buffer once + * command is finished. + */ +struct vpe_bufs_req { + uint64_t cmd_buf_size; /**< total command buffer size for all vpe commands */ + uint64_t emb_buf_size; /**< total size for storing all embedded data */ +}; + +struct vpe_buf { + uint64_t gpu_va; /**< GPU start address of the buffer */ + uint64_t cpu_va; + int64_t size; + bool tmz; /**< allocated from tmz */ +}; + +struct vpe_build_bufs { + struct vpe_buf cmd_buf; /**< Command buffer. gpu_va is optional */ + struct vpe_buf emb_buf; /**< Embedded buffer */ +}; + +#ifdef __cplusplus +} +#endif diff --git a/src/amd/vpelib/inc/vpe_version.h b/src/amd/vpelib/inc/vpe_version.h new file mode 100644 index 00000000000..d1fe2182c4c --- /dev/null +++ b/src/amd/vpelib/inc/vpe_version.h @@ -0,0 +1,55 @@ +/* Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#define VPELIB_API_VERSION_MAJOR 0 +#define VPELIB_API_VERSION_MINOR 3 + +#define VPELIB_API_VERSION_MAJOR_SHIFT 16 +#define VPELIB_API_VERSION_MINOR_SHIFT 0 +#define VPELIB_API_VERSION_MAJOR_MASK 0xFFFF0000 +#define VPELIB_API_VERSION_MINOR_MASK 0x0000FFFF + +#define VPELIB_GET_API_MAJOR(version) \ + ((version & VPELIB_API_VERSION_MAJOR_MASK) >> VPELIB_API_VERSION_MAJOR_SHIFT) + +#define VPELIB_GET_API_MINOR(version) \ + ((version & VPELIB_API_VERSION_MINOR_MASK) >> VPELIB_API_VERSION_MINOR_SHIFT) + + +#define VPE_VERSION(mj, mn, rv) (((mj) << 16) | ((mn) << 8) | (rv)) +#define VPE_VERSION_MAJ(ver) ((ver) >> 16) +#define VPE_VERSION_MIN(ver) (((ver) >> 8) & 0xFF) +#define VPE_VERSION_REV(ver) ((ver) & 0xFF) +#define VPE_VERSION_6_1_0(ver) ((ver) == VPE_VERSION(6, 1, 0)) +#define VPE_VERSION_6_1_1(ver) ((ver) == VPE_VERSION(6, 1, 1)) + +#ifdef __cplusplus +} +#endif diff --git a/src/amd/vpelib/inc/vpelib.h b/src/amd/vpelib/inc/vpelib.h new file mode 100644 index 00000000000..b4831735fe8 --- /dev/null +++ b/src/amd/vpelib/inc/vpelib.h @@ -0,0 +1,106 @@ +/* Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#pragma once + +#include "vpe_types.h" +#include "vpe_version.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* @brief Create the VPE lib instance. + * + * Caler provides the current asic info, + * logging and system memory APIs. + * It initializes all the necessary resources for the asic + * and returns the general capabilities of the engines. + * + * For capabilities based on conditions, + * shall be done by vpe->cap_funcs.* + * + * + * @param[in] params provide the asic version, APIs for logging and memory + * @return vpe instance if supported. NULL otherwise + */ +struct vpe *vpe_create(const struct vpe_init_data *params); + +/* @brief Destroy the VPE lib instance and resources + * + * @param[in] vpe the vpe instance created by vpe_create + */ +void vpe_destroy(struct vpe **vpe); + +/** + * @brief Check if the VPE operation is supported. + * + * Caller must call this to check if the VPE supports + * the requested operation before calling vpe_build_commands(). + * If operation is supported, it returns the memory requirement. + * + * The caller has to prepare those required memories + * and pass them to the vpe_build_commands(). + * + * @param[in] vpe vpe instance returned by vpe_initialize() + * @param[in] param build params + * @param[out] req memory required for the command buffer and + embedded data if return VPE_OK. + caller has to alloc them and provide it to build_vpbilts API. + * @return VPE_OK if supported + */ +enum vpe_status vpe_check_support( + struct vpe *vpe, const struct vpe_build_param *param, struct vpe_bufs_req *req); + +/************************************ + * Command building functions + ************************************/ +/** + * Build the command descriptors for No-Op operation + * @param[in] vpe vpe instance created by vpe_create() + * @param[in] num_dwords number of noops + * @param[in,out] ppcmd_space in: dword aligned command buffer start address + * out: dword aligned next good write address + * @return status + */ +enum vpe_status vpe_build_noops(struct vpe *vpe, uint32_t num_dwords, uint32_t **ppcmd_space); + +/** + * build the command descriptors for the given param. + * caller must call vpe_check_support() before this function, + * unexpected result otherwise. + * + * @param[in] vpe vpe instance created by vpe_create() + * @param[in] param vpe build params + * @param[in,out] bufs [in] memory allocated for the command buffer, embedded buffer and 3dlut. + * If size is 0, it reports the required size for this checked + * operation. [out] the next write address and the filled sizes. + * @return status + */ +enum vpe_status vpe_build_commands( + struct vpe *vpe, const struct vpe_build_param *param, struct vpe_build_bufs *bufs); + +#ifdef __cplusplus +} +#endif diff --git a/src/amd/vpelib/meson.build b/src/amd/vpelib/meson.build new file mode 100644 index 00000000000..55c3dcee937 --- /dev/null +++ b/src/amd/vpelib/meson.build @@ -0,0 +1,146 @@ +# Copyright 2022 Advanced Micro Devices, Inc. +# All Rights Reserved. + +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: + +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. + +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +# SOFTWARE. + +c_args_vpe = cc.get_supported_arguments([ + '-Wall', + '-Wextra', + '-Wno-unused', + '-Wno-unused-parameter', + '-Wno-unused-command-line-argument', + '-Wno-ignored-qualifiers', + '-Wno-missing-field-initializers', + '-Wno-self-assign', + '-Wno-implicit-fallthrough', + '-Werror=comment', + '-Werror=missing-braces', + '-Werror=override-init', + '-Werror=enum-conversion', + '-Werror=enum-compare', + '-Werror=maybe-uninitialized', +]) + +c_args_vpe += [ + '-DLITTLEENDIAN_CPU', + '-DVPE_BUILD_1_0', + '-DVPE_BUILD_1_X', +] + +vpe_files = files( + 'src/core/inc/reg_helper.h', + 'src/core/inc/vpe_priv.h', + 'src/core/inc/vpe_command.h', + 'src/core/inc/color_pwl.h', + 'src/core/inc/color_gamut.h', + 'src/core/inc/vpe_assert.h', + 'src/core/inc/vpec.h', + 'src/core/inc/plane_desc_writer.h', + 'src/core/inc/color_table.h', + 'src/core/inc/hw_shared.h', + 'src/core/inc/cdc.h', + 'src/core/inc/dpp.h', + 'src/core/inc/color_test_values.h', + 'src/core/inc/vpe_visual_confirm.h', + 'src/core/inc/color_cs.h', + 'src/core/inc/diag_reg_helper.h', + 'src/core/inc/shaper_builder.h', + 'src/core/inc/color_bg.h', + 'src/core/inc/transform.h', + 'src/core/inc/common.h', + 'src/core/inc/color.h', + 'src/core/inc/mpc.h', + 'src/core/inc/3dlut_builder.h', + 'src/core/inc/cmd_builder.h', + 'src/core/inc/background.h', + 'src/core/inc/color_gamma.h', + 'src/core/inc/opp.h', + 'src/core/inc/resource.h', + 'src/core/inc/vpe_desc_writer.h', + 'src/core/inc/config_writer.h', + 'src/core/color_gamma.c', + 'src/core/color_bg.c', + 'src/core/vpe_scl_filters.c', + 'src/core/background.c', + 'src/core/vpe_visual_confirm.c', + 'src/core/mpc.c', + 'src/core/config_writer.c', + 'src/core/plane_desc_writer.c', + 'src/core/color_gamut.c', + 'src/core/vpelib.c', + 'src/core/vpe_desc_writer.c', + 'src/core/3dlut_builder.c', + 'src/core/color_test_values.c', + 'src/core/resource.c', + 'src/core/color_table.c', + 'src/core/color.c', + 'src/core/color_cs.c', + 'src/core/common.c', + 'src/core/shaper_builder.c', + 'src/utils/inc/custom_fp16.h', + 'src/utils/inc/custom_float.h', + 'src/utils/inc/fixed31_32.h', + 'src/utils/inc/conversion.h', + 'src/utils/inc/calc_u64.h', + 'src/utils/custom_fp16.c', + 'src/utils/custom_float.c', + 'src/utils/conversion.c', + 'src/utils/fixpt31_32.c', + 'src/chip/vpe10/inc/vpe10_background.h', + 'src/chip/vpe10/inc/vpe10_cm_common.h', + 'src/chip/vpe10/inc/vpe10_vpec.h', + 'src/chip/vpe10/inc/vpe10_mpc.h', + 'src/chip/vpe10/inc/vpe10_cmd_builder.h', + 'src/chip/vpe10/inc/vpe10_opp.h', + 'src/chip/vpe10/inc/asic/bringup_vpe_6_1_0_default.h', + 'src/chip/vpe10/inc/asic/bringup_vpe_6_1_0_offset.h', + 'src/chip/vpe10/inc/asic/bringup_vpe_6_1_0_sh_mask.h', + 'src/chip/vpe10/inc/asic/vpe_1_0_offset.h', + 'src/chip/vpe10/inc/vpe10_resource.h', + 'src/chip/vpe10/inc/vpe10_cdc.h', + 'src/chip/vpe10/inc/vpe10_dpp.h', + 'src/chip/vpe10/vpe10_cm_common.c', + 'src/chip/vpe10/vpe10_dpp.c', + 'src/chip/vpe10/vpe10_resource.c', + 'src/chip/vpe10/vpe10_mpc.c', + 'src/chip/vpe10/vpe10_cmd_builder.c', + 'src/chip/vpe10/vpe10_dpp_dscl.c', + 'src/chip/vpe10/vpe10_dpp_cm.c', + 'src/chip/vpe10/vpe10_opp.c', + 'src/chip/vpe10/vpe10_background.c', + 'src/chip/vpe10/vpe10_cdc.c', + 'src/chip/vpe10/vpe10_vpec.c', +) + +inc_amd_vpe = include_directories( + 'inc', + 'src', + 'src/core/inc', + 'src/chip', + 'src/utils/inc', + 'src/chip/vpe10/inc', +) + +libvpe = static_library( + 'libvpe.a', + vpe_files, + install : false, + c_args : c_args_vpe, + include_directories : inc_amd_vpe +) diff --git a/src/amd/vpelib/src/chip/vpe10/inc/asic/bringup_vpe_6_1_0_default.h b/src/amd/vpelib/src/chip/vpe10/inc/asic/bringup_vpe_6_1_0_default.h new file mode 100644 index 00000000000..d036015a5fa --- /dev/null +++ b/src/amd/vpelib/src/chip/vpe10/inc/asic/bringup_vpe_6_1_0_default.h @@ -0,0 +1,872 @@ +// Headers from LSDp CL1744173 +#ifndef _vpe_6_1_0_DEFAULT_HEADER +#define _vpe_6_1_0_DEFAULT_HEADER + + +// addressBlock: vpe_vpedec +#define regVPEC_DEC_START_DEFAULT 0x00000000 +#define regVPEC_UCODE_ADDR_DEFAULT 0x00000000 +#define regVPEC_UCODE_DATA_DEFAULT 0x00000000 +#define regVPEC_F32_CNTL_DEFAULT 0x08084001 +#define regVPEC_MMHUB_CNTL_DEFAULT 0x00000000 +#define regVPEC_MMHUB_TRUSTLVL_DEFAULT 0x77777777 +#define regVPEC_VPEP_CTRL_DEFAULT 0x00000002 +#define regVPEC_CLK_CTRL_DEFAULT 0x00000000 +#define regVPEC_PG_CNTL_DEFAULT 0x00000015 +#define regVPEC_POWER_CNTL_DEFAULT 0x00000000 +#define regVPEC_CNTL_DEFAULT 0x0150c401 +#define regVPEC_CNTL1_DEFAULT 0x05001000 +#define regVPEC_CNTL2_DEFAULT 0x400400c9 +#define regVPEC_GB_ADDR_CONFIG_DEFAULT 0x00000242 +#define regVPEC_GB_ADDR_CONFIG_READ_DEFAULT 0x00000242 +#define regVPEC_PROCESS_QUANTUM0_DEFAULT 0x00000000 +#define regVPEC_PROCESS_QUANTUM1_DEFAULT 0x00000000 +#define regVPEC_CONTEXT_SWITCH_THRESHOLD_DEFAULT 0x0000006b +#define regVPEC_GLOBAL_QUANTUM_DEFAULT 0x00000000 +#define regVPEC_WATCHDOG_CNTL_DEFAULT 0x00000000 +#define regVPEC_ATOMIC_CNTL_DEFAULT 0x00000200 +#define regVPEC_UCODE_VERSION_DEFAULT 0x00000000 +#define regVPEC_MEMREQ_BURST_CNTL_DEFAULT 0x000006ff +#define regVPEC_TIMESTAMP_CNTL_DEFAULT 0x00000000 +#define regVPEC_GLOBAL_TIMESTAMP_LO_DEFAULT 0x00000000 +#define regVPEC_GLOBAL_TIMESTAMP_HI_DEFAULT 0x00000000 +#define regVPEC_FREEZE_DEFAULT 0x00000000 +#define regVPEC_CE_CTRL_DEFAULT 0x00000000 +#define regVPEC_RELAX_ORDERING_LUT_DEFAULT 0xc0000806 +#define regVPEC_CREDIT_CNTL_DEFAULT 0x00014840 +#define regVPEC_SCRATCH_RAM_DATA_DEFAULT 0x00000000 +#define regVPEC_SCRATCH_RAM_ADDR_DEFAULT 0x00000000 +#define regVPEC_QUEUE_RESET_REQ_DEFAULT 0x00000000 +#define regVPEC_PERFCNT_PERFCOUNTER0_CFG_DEFAULT 0x0000ffff +#define regVPEC_PERFCNT_PERFCOUNTER1_CFG_DEFAULT 0x0000ffff +#define regVPEC_PERFCNT_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 +#define regVPEC_PERFCNT_MISC_CNTL_DEFAULT 0x00010000 +#define regVPEC_PERFCNT_PERFCOUNTER_LO_DEFAULT 0x00000000 +#define regVPEC_PERFCNT_PERFCOUNTER_HI_DEFAULT 0x00000000 +#define regVPEC_DEBUG_INDEX_DEFAULT 0x00000000 +#define regVPEC_DEBUG_DATA_DEFAULT 0x00000000 +#define regVPEC_CRC_CTRL_DEFAULT 0x00000000 +#define regVPEC_CRC_DATA_DEFAULT 0x00000000 +#define regVPEC_PUB_DUMMY0_DEFAULT 0x00000000 +#define regVPEC_PUB_DUMMY1_DEFAULT 0x00000000 +#define regVPEC_PUB_DUMMY2_DEFAULT 0x00000000 +#define regVPEC_PUB_DUMMY3_DEFAULT 0x00000000 +#define regVPEC_PUB_DUMMY4_DEFAULT 0x00000000 +#define regVPEC_PUB_DUMMY5_DEFAULT 0x00000000 +#define regVPEC_PUB_DUMMY6_DEFAULT 0x00000000 +#define regVPEC_PUB_DUMMY7_DEFAULT 0x00000000 +#define regVPEC_UCODE1_CHECKSUM_DEFAULT 0x00000000 +#define regVPEC_VERSION_DEFAULT 0x00000601 +#define regVPEC_UCODE_CHECKSUM_DEFAULT 0x00000000 +#define regVPEC_CLOCK_GATING_STATUS_DEFAULT 0x00000000 +#define regVPEC_RB_RPTR_FETCH_DEFAULT 0x00000000 +#define regVPEC_RB_RPTR_FETCH_HI_DEFAULT 0x00000000 +#define regVPEC_IB_OFFSET_FETCH_DEFAULT 0x00000000 +#define regVPEC_CMDIB_OFFSET_FETCH_DEFAULT 0x00000000 +#define regVPEC_ATOMIC_PREOP_LO_DEFAULT 0x00000000 +#define regVPEC_ATOMIC_PREOP_HI_DEFAULT 0x00000000 +#define regVPEC_CE_BUSY_DEFAULT 0x00000000 +#define regVPEC_F32_COUNTER_DEFAULT 0x00000000 +#define regVPEC_HOLE_ADDR_LO_DEFAULT 0x00000000 +#define regVPEC_HOLE_ADDR_HI_DEFAULT 0x00000000 +#define regVPEC_ERROR_LOG_DEFAULT 0x0000000f +#define regVPEC_INT_STATUS_DEFAULT 0x00000000 +#define regVPEC_STATUS_DEFAULT 0x46dee557 +#define regVPEC_STATUS1_DEFAULT 0x0003ffff +#define regVPEC_STATUS2_DEFAULT 0x00000000 +#define regVPEC_STATUS3_DEFAULT 0x03f00000 +#define regVPEC_STATUS4_DEFAULT 0x00000001 +#define regVPEC_STATUS5_DEFAULT 0x00000000 +#define regVPEC_STATUS6_DEFAULT 0x00000000 +#define regVPEC_STATUS7_DEFAULT 0x00000000 +#define regVPEC_INST_DEFAULT 0x00000000 +#define regVPEC_QUEUE_STATUS0_DEFAULT 0x22222222 +#define regVPEC_QUEUE_HANG_STATUS_DEFAULT 0x00000000 +#define regVPEC_QUEUE0_RB_CNTL_DEFAULT 0x00040800 +#define regVPEC_QUEUE0_SCHEDULE_CNTL_DEFAULT 0x00000000 +#define regVPEC_QUEUE0_RB_BASE_DEFAULT 0x00000000 +#define regVPEC_QUEUE0_RB_BASE_HI_DEFAULT 0x00000000 +#define regVPEC_QUEUE0_RB_RPTR_DEFAULT 0x00000000 +#define regVPEC_QUEUE0_RB_RPTR_HI_DEFAULT 0x00000000 +#define regVPEC_QUEUE0_RB_WPTR_DEFAULT 0x00000000 +#define regVPEC_QUEUE0_RB_WPTR_HI_DEFAULT 0x00000000 +#define regVPEC_QUEUE0_RB_RPTR_ADDR_HI_DEFAULT 0x00000000 +#define regVPEC_QUEUE0_RB_RPTR_ADDR_LO_DEFAULT 0x00000000 +#define regVPEC_QUEUE0_RB_AQL_CNTL_DEFAULT 0x00004000 +#define regVPEC_QUEUE0_MINOR_PTR_UPDATE_DEFAULT 0x00000000 +#define regVPEC_QUEUE0_CD_INFO_DEFAULT 0x00000000 +#define regVPEC_QUEUE0_RB_PREEMPT_DEFAULT 0x00000000 +#define regVPEC_QUEUE0_SKIP_CNTL_DEFAULT 0x00000000 +#define regVPEC_QUEUE0_DOORBELL_DEFAULT 0x00000000 +#define regVPEC_QUEUE0_DOORBELL_OFFSET_DEFAULT 0x00000000 +#define regVPEC_QUEUE0_DUMMY0_DEFAULT 0x0000000f +#define regVPEC_QUEUE0_DUMMY1_DEFAULT 0x00000000 +#define regVPEC_QUEUE0_DUMMY2_DEFAULT 0x00000000 +#define regVPEC_QUEUE0_DUMMY3_DEFAULT 0x00000000 +#define regVPEC_QUEUE0_DUMMY4_DEFAULT 0x00000000 +#define regVPEC_QUEUE0_IB_CNTL_DEFAULT 0x00000100 +#define regVPEC_QUEUE0_IB_RPTR_DEFAULT 0x00000000 +#define regVPEC_QUEUE0_IB_OFFSET_DEFAULT 0x00000000 +#define regVPEC_QUEUE0_IB_BASE_LO_DEFAULT 0x00000000 +#define regVPEC_QUEUE0_IB_BASE_HI_DEFAULT 0x00000000 +#define regVPEC_QUEUE0_IB_SIZE_DEFAULT 0x00000000 +#define regVPEC_QUEUE0_CMDIB_CNTL_DEFAULT 0x00000101 +#define regVPEC_QUEUE0_CMDIB_RPTR_DEFAULT 0x00000000 +#define regVPEC_QUEUE0_CMDIB_OFFSET_DEFAULT 0x00000000 +#define regVPEC_QUEUE0_CMDIB_BASE_LO_DEFAULT 0x00000000 +#define regVPEC_QUEUE0_CMDIB_BASE_HI_DEFAULT 0x00000000 +#define regVPEC_QUEUE0_CMDIB_SIZE_DEFAULT 0x00000000 +#define regVPEC_QUEUE0_CSA_ADDR_LO_DEFAULT 0x00000000 +#define regVPEC_QUEUE0_CSA_ADDR_HI_DEFAULT 0x00000000 +#define regVPEC_QUEUE0_CONTEXT_STATUS_DEFAULT 0x00000804 +#define regVPEC_QUEUE0_DOORBELL_LOG_DEFAULT 0x00000000 +#define regVPEC_QUEUE0_IB_SUB_REMAIN_DEFAULT 0x00000000 +#define regVPEC_QUEUE0_PREEMPT_DEFAULT 0x00000000 +#define regVPEC_QUEUE1_RB_CNTL_DEFAULT 0x00040800 +#define regVPEC_QUEUE1_SCHEDULE_CNTL_DEFAULT 0x00000000 +#define regVPEC_QUEUE1_RB_BASE_DEFAULT 0x00000000 +#define regVPEC_QUEUE1_RB_BASE_HI_DEFAULT 0x00000000 +#define regVPEC_QUEUE1_RB_RPTR_DEFAULT 0x00000000 +#define regVPEC_QUEUE1_RB_RPTR_HI_DEFAULT 0x00000000 +#define regVPEC_QUEUE1_RB_WPTR_DEFAULT 0x00000000 +#define regVPEC_QUEUE1_RB_WPTR_HI_DEFAULT 0x00000000 +#define regVPEC_QUEUE1_RB_RPTR_ADDR_HI_DEFAULT 0x00000000 +#define regVPEC_QUEUE1_RB_RPTR_ADDR_LO_DEFAULT 0x00000000 +#define regVPEC_QUEUE1_RB_AQL_CNTL_DEFAULT 0x00004000 +#define regVPEC_QUEUE1_MINOR_PTR_UPDATE_DEFAULT 0x00000000 +#define regVPEC_QUEUE1_CD_INFO_DEFAULT 0x00000000 +#define regVPEC_QUEUE1_RB_PREEMPT_DEFAULT 0x00000000 +#define regVPEC_QUEUE1_SKIP_CNTL_DEFAULT 0x00000000 +#define regVPEC_QUEUE1_DOORBELL_DEFAULT 0x00000000 +#define regVPEC_QUEUE1_DOORBELL_OFFSET_DEFAULT 0x00000000 +#define regVPEC_QUEUE1_DUMMY0_DEFAULT 0x0000000f +#define regVPEC_QUEUE1_DUMMY1_DEFAULT 0x00000000 +#define regVPEC_QUEUE1_DUMMY2_DEFAULT 0x00000000 +#define regVPEC_QUEUE1_DUMMY3_DEFAULT 0x00000000 +#define regVPEC_QUEUE1_DUMMY4_DEFAULT 0x00000000 +#define regVPEC_QUEUE1_IB_CNTL_DEFAULT 0x00000100 +#define regVPEC_QUEUE1_IB_RPTR_DEFAULT 0x00000000 +#define regVPEC_QUEUE1_IB_OFFSET_DEFAULT 0x00000000 +#define regVPEC_QUEUE1_IB_BASE_LO_DEFAULT 0x00000000 +#define regVPEC_QUEUE1_IB_BASE_HI_DEFAULT 0x00000000 +#define regVPEC_QUEUE1_IB_SIZE_DEFAULT 0x00000000 +#define regVPEC_QUEUE1_CMDIB_CNTL_DEFAULT 0x00000101 +#define regVPEC_QUEUE1_CMDIB_RPTR_DEFAULT 0x00000000 +#define regVPEC_QUEUE1_CMDIB_OFFSET_DEFAULT 0x00000000 +#define regVPEC_QUEUE1_CMDIB_BASE_LO_DEFAULT 0x00000000 +#define regVPEC_QUEUE1_CMDIB_BASE_HI_DEFAULT 0x00000000 +#define regVPEC_QUEUE1_CMDIB_SIZE_DEFAULT 0x00000000 +#define regVPEC_QUEUE1_CSA_ADDR_LO_DEFAULT 0x00000000 +#define regVPEC_QUEUE1_CSA_ADDR_HI_DEFAULT 0x00000000 +#define regVPEC_QUEUE1_CONTEXT_STATUS_DEFAULT 0x00000804 +#define regVPEC_QUEUE1_DOORBELL_LOG_DEFAULT 0x00000000 +#define regVPEC_QUEUE1_IB_SUB_REMAIN_DEFAULT 0x00000000 +#define regVPEC_QUEUE1_PREEMPT_DEFAULT 0x00000000 +#define regVPEC_QUEUE2_RB_CNTL_DEFAULT 0x00040800 +#define regVPEC_QUEUE2_SCHEDULE_CNTL_DEFAULT 0x00000000 +#define regVPEC_QUEUE2_RB_BASE_DEFAULT 0x00000000 +#define regVPEC_QUEUE2_RB_BASE_HI_DEFAULT 0x00000000 +#define regVPEC_QUEUE2_RB_RPTR_DEFAULT 0x00000000 +#define regVPEC_QUEUE2_RB_RPTR_HI_DEFAULT 0x00000000 +#define regVPEC_QUEUE2_RB_WPTR_DEFAULT 0x00000000 +#define regVPEC_QUEUE2_RB_WPTR_HI_DEFAULT 0x00000000 +#define regVPEC_QUEUE2_RB_RPTR_ADDR_HI_DEFAULT 0x00000000 +#define regVPEC_QUEUE2_RB_RPTR_ADDR_LO_DEFAULT 0x00000000 +#define regVPEC_QUEUE2_RB_AQL_CNTL_DEFAULT 0x00004000 +#define regVPEC_QUEUE2_MINOR_PTR_UPDATE_DEFAULT 0x00000000 +#define regVPEC_QUEUE2_CD_INFO_DEFAULT 0x00000000 +#define regVPEC_QUEUE2_RB_PREEMPT_DEFAULT 0x00000000 +#define regVPEC_QUEUE2_SKIP_CNTL_DEFAULT 0x00000000 +#define regVPEC_QUEUE2_DOORBELL_DEFAULT 0x00000000 +#define regVPEC_QUEUE2_DOORBELL_OFFSET_DEFAULT 0x00000000 +#define regVPEC_QUEUE2_DUMMY0_DEFAULT 0x0000000f +#define regVPEC_QUEUE2_DUMMY1_DEFAULT 0x00000000 +#define regVPEC_QUEUE2_DUMMY2_DEFAULT 0x00000000 +#define regVPEC_QUEUE2_DUMMY3_DEFAULT 0x00000000 +#define regVPEC_QUEUE2_DUMMY4_DEFAULT 0x00000000 +#define regVPEC_QUEUE2_IB_CNTL_DEFAULT 0x00000100 +#define regVPEC_QUEUE2_IB_RPTR_DEFAULT 0x00000000 +#define regVPEC_QUEUE2_IB_OFFSET_DEFAULT 0x00000000 +#define regVPEC_QUEUE2_IB_BASE_LO_DEFAULT 0x00000000 +#define regVPEC_QUEUE2_IB_BASE_HI_DEFAULT 0x00000000 +#define regVPEC_QUEUE2_IB_SIZE_DEFAULT 0x00000000 +#define regVPEC_QUEUE2_CMDIB_CNTL_DEFAULT 0x00000101 +#define regVPEC_QUEUE2_CMDIB_RPTR_DEFAULT 0x00000000 +#define regVPEC_QUEUE2_CMDIB_OFFSET_DEFAULT 0x00000000 +#define regVPEC_QUEUE2_CMDIB_BASE_LO_DEFAULT 0x00000000 +#define regVPEC_QUEUE2_CMDIB_BASE_HI_DEFAULT 0x00000000 +#define regVPEC_QUEUE2_CMDIB_SIZE_DEFAULT 0x00000000 +#define regVPEC_QUEUE2_CSA_ADDR_LO_DEFAULT 0x00000000 +#define regVPEC_QUEUE2_CSA_ADDR_HI_DEFAULT 0x00000000 +#define regVPEC_QUEUE2_CONTEXT_STATUS_DEFAULT 0x00000804 +#define regVPEC_QUEUE2_DOORBELL_LOG_DEFAULT 0x00000000 +#define regVPEC_QUEUE2_IB_SUB_REMAIN_DEFAULT 0x00000000 +#define regVPEC_QUEUE2_PREEMPT_DEFAULT 0x00000000 +#define regVPEC_QUEUE3_RB_CNTL_DEFAULT 0x00040800 +#define regVPEC_QUEUE3_SCHEDULE_CNTL_DEFAULT 0x00000000 +#define regVPEC_QUEUE3_RB_BASE_DEFAULT 0x00000000 +#define regVPEC_QUEUE3_RB_BASE_HI_DEFAULT 0x00000000 +#define regVPEC_QUEUE3_RB_RPTR_DEFAULT 0x00000000 +#define regVPEC_QUEUE3_RB_RPTR_HI_DEFAULT 0x00000000 +#define regVPEC_QUEUE3_RB_WPTR_DEFAULT 0x00000000 +#define regVPEC_QUEUE3_RB_WPTR_HI_DEFAULT 0x00000000 +#define regVPEC_QUEUE3_RB_RPTR_ADDR_HI_DEFAULT 0x00000000 +#define regVPEC_QUEUE3_RB_RPTR_ADDR_LO_DEFAULT 0x00000000 +#define regVPEC_QUEUE3_RB_AQL_CNTL_DEFAULT 0x00004000 +#define regVPEC_QUEUE3_MINOR_PTR_UPDATE_DEFAULT 0x00000000 +#define regVPEC_QUEUE3_CD_INFO_DEFAULT 0x00000000 +#define regVPEC_QUEUE3_RB_PREEMPT_DEFAULT 0x00000000 +#define regVPEC_QUEUE3_SKIP_CNTL_DEFAULT 0x00000000 +#define regVPEC_QUEUE3_DOORBELL_DEFAULT 0x00000000 +#define regVPEC_QUEUE3_DOORBELL_OFFSET_DEFAULT 0x00000000 +#define regVPEC_QUEUE3_DUMMY0_DEFAULT 0x0000000f +#define regVPEC_QUEUE3_DUMMY1_DEFAULT 0x00000000 +#define regVPEC_QUEUE3_DUMMY2_DEFAULT 0x00000000 +#define regVPEC_QUEUE3_DUMMY3_DEFAULT 0x00000000 +#define regVPEC_QUEUE3_DUMMY4_DEFAULT 0x00000000 +#define regVPEC_QUEUE3_IB_CNTL_DEFAULT 0x00000100 +#define regVPEC_QUEUE3_IB_RPTR_DEFAULT 0x00000000 +#define regVPEC_QUEUE3_IB_OFFSET_DEFAULT 0x00000000 +#define regVPEC_QUEUE3_IB_BASE_LO_DEFAULT 0x00000000 +#define regVPEC_QUEUE3_IB_BASE_HI_DEFAULT 0x00000000 +#define regVPEC_QUEUE3_IB_SIZE_DEFAULT 0x00000000 +#define regVPEC_QUEUE3_CMDIB_CNTL_DEFAULT 0x00000101 +#define regVPEC_QUEUE3_CMDIB_RPTR_DEFAULT 0x00000000 +#define regVPEC_QUEUE3_CMDIB_OFFSET_DEFAULT 0x00000000 +#define regVPEC_QUEUE3_CMDIB_BASE_LO_DEFAULT 0x00000000 +#define regVPEC_QUEUE3_CMDIB_BASE_HI_DEFAULT 0x00000000 +#define regVPEC_QUEUE3_CMDIB_SIZE_DEFAULT 0x00000000 +#define regVPEC_QUEUE3_CSA_ADDR_LO_DEFAULT 0x00000000 +#define regVPEC_QUEUE3_CSA_ADDR_HI_DEFAULT 0x00000000 +#define regVPEC_QUEUE3_CONTEXT_STATUS_DEFAULT 0x00000804 +#define regVPEC_QUEUE3_DOORBELL_LOG_DEFAULT 0x00000000 +#define regVPEC_QUEUE3_IB_SUB_REMAIN_DEFAULT 0x00000000 +#define regVPEC_QUEUE3_PREEMPT_DEFAULT 0x00000000 +#define regVPEC_QUEUE4_RB_CNTL_DEFAULT 0x00040800 +#define regVPEC_QUEUE4_SCHEDULE_CNTL_DEFAULT 0x00000000 +#define regVPEC_QUEUE4_RB_BASE_DEFAULT 0x00000000 +#define regVPEC_QUEUE4_RB_BASE_HI_DEFAULT 0x00000000 +#define regVPEC_QUEUE4_RB_RPTR_DEFAULT 0x00000000 +#define regVPEC_QUEUE4_RB_RPTR_HI_DEFAULT 0x00000000 +#define regVPEC_QUEUE4_RB_WPTR_DEFAULT 0x00000000 +#define regVPEC_QUEUE4_RB_WPTR_HI_DEFAULT 0x00000000 +#define regVPEC_QUEUE4_RB_RPTR_ADDR_HI_DEFAULT 0x00000000 +#define regVPEC_QUEUE4_RB_RPTR_ADDR_LO_DEFAULT 0x00000000 +#define regVPEC_QUEUE4_RB_AQL_CNTL_DEFAULT 0x00004000 +#define regVPEC_QUEUE4_MINOR_PTR_UPDATE_DEFAULT 0x00000000 +#define regVPEC_QUEUE4_CD_INFO_DEFAULT 0x00000000 +#define regVPEC_QUEUE4_RB_PREEMPT_DEFAULT 0x00000000 +#define regVPEC_QUEUE4_SKIP_CNTL_DEFAULT 0x00000000 +#define regVPEC_QUEUE4_DOORBELL_DEFAULT 0x00000000 +#define regVPEC_QUEUE4_DOORBELL_OFFSET_DEFAULT 0x00000000 +#define regVPEC_QUEUE4_DUMMY0_DEFAULT 0x0000000f +#define regVPEC_QUEUE4_DUMMY1_DEFAULT 0x00000000 +#define regVPEC_QUEUE4_DUMMY2_DEFAULT 0x00000000 +#define regVPEC_QUEUE4_DUMMY3_DEFAULT 0x00000000 +#define regVPEC_QUEUE4_DUMMY4_DEFAULT 0x00000000 +#define regVPEC_QUEUE4_IB_CNTL_DEFAULT 0x00000100 +#define regVPEC_QUEUE4_IB_RPTR_DEFAULT 0x00000000 +#define regVPEC_QUEUE4_IB_OFFSET_DEFAULT 0x00000000 +#define regVPEC_QUEUE4_IB_BASE_LO_DEFAULT 0x00000000 +#define regVPEC_QUEUE4_IB_BASE_HI_DEFAULT 0x00000000 +#define regVPEC_QUEUE4_IB_SIZE_DEFAULT 0x00000000 +#define regVPEC_QUEUE4_CMDIB_CNTL_DEFAULT 0x00000101 +#define regVPEC_QUEUE4_CMDIB_RPTR_DEFAULT 0x00000000 +#define regVPEC_QUEUE4_CMDIB_OFFSET_DEFAULT 0x00000000 +#define regVPEC_QUEUE4_CMDIB_BASE_LO_DEFAULT 0x00000000 +#define regVPEC_QUEUE4_CMDIB_BASE_HI_DEFAULT 0x00000000 +#define regVPEC_QUEUE4_CMDIB_SIZE_DEFAULT 0x00000000 +#define regVPEC_QUEUE4_CSA_ADDR_LO_DEFAULT 0x00000000 +#define regVPEC_QUEUE4_CSA_ADDR_HI_DEFAULT 0x00000000 +#define regVPEC_QUEUE4_CONTEXT_STATUS_DEFAULT 0x00000804 +#define regVPEC_QUEUE4_DOORBELL_LOG_DEFAULT 0x00000000 +#define regVPEC_QUEUE4_IB_SUB_REMAIN_DEFAULT 0x00000000 +#define regVPEC_QUEUE4_PREEMPT_DEFAULT 0x00000000 +#define regVPEC_QUEUE5_RB_CNTL_DEFAULT 0x00040800 +#define regVPEC_QUEUE5_SCHEDULE_CNTL_DEFAULT 0x00000000 +#define regVPEC_QUEUE5_RB_BASE_DEFAULT 0x00000000 +#define regVPEC_QUEUE5_RB_BASE_HI_DEFAULT 0x00000000 +#define regVPEC_QUEUE5_RB_RPTR_DEFAULT 0x00000000 +#define regVPEC_QUEUE5_RB_RPTR_HI_DEFAULT 0x00000000 +#define regVPEC_QUEUE5_RB_WPTR_DEFAULT 0x00000000 +#define regVPEC_QUEUE5_RB_WPTR_HI_DEFAULT 0x00000000 +#define regVPEC_QUEUE5_RB_RPTR_ADDR_HI_DEFAULT 0x00000000 +#define regVPEC_QUEUE5_RB_RPTR_ADDR_LO_DEFAULT 0x00000000 +#define regVPEC_QUEUE5_RB_AQL_CNTL_DEFAULT 0x00004000 +#define regVPEC_QUEUE5_MINOR_PTR_UPDATE_DEFAULT 0x00000000 +#define regVPEC_QUEUE5_CD_INFO_DEFAULT 0x00000000 +#define regVPEC_QUEUE5_RB_PREEMPT_DEFAULT 0x00000000 +#define regVPEC_QUEUE5_SKIP_CNTL_DEFAULT 0x00000000 +#define regVPEC_QUEUE5_DOORBELL_DEFAULT 0x00000000 +#define regVPEC_QUEUE5_DOORBELL_OFFSET_DEFAULT 0x00000000 +#define regVPEC_QUEUE5_DUMMY0_DEFAULT 0x0000000f +#define regVPEC_QUEUE5_DUMMY1_DEFAULT 0x00000000 +#define regVPEC_QUEUE5_DUMMY2_DEFAULT 0x00000000 +#define regVPEC_QUEUE5_DUMMY3_DEFAULT 0x00000000 +#define regVPEC_QUEUE5_DUMMY4_DEFAULT 0x00000000 +#define regVPEC_QUEUE5_IB_CNTL_DEFAULT 0x00000100 +#define regVPEC_QUEUE5_IB_RPTR_DEFAULT 0x00000000 +#define regVPEC_QUEUE5_IB_OFFSET_DEFAULT 0x00000000 +#define regVPEC_QUEUE5_IB_BASE_LO_DEFAULT 0x00000000 +#define regVPEC_QUEUE5_IB_BASE_HI_DEFAULT 0x00000000 +#define regVPEC_QUEUE5_IB_SIZE_DEFAULT 0x00000000 +#define regVPEC_QUEUE5_CMDIB_CNTL_DEFAULT 0x00000101 +#define regVPEC_QUEUE5_CMDIB_RPTR_DEFAULT 0x00000000 +#define regVPEC_QUEUE5_CMDIB_OFFSET_DEFAULT 0x00000000 +#define regVPEC_QUEUE5_CMDIB_BASE_LO_DEFAULT 0x00000000 +#define regVPEC_QUEUE5_CMDIB_BASE_HI_DEFAULT 0x00000000 +#define regVPEC_QUEUE5_CMDIB_SIZE_DEFAULT 0x00000000 +#define regVPEC_QUEUE5_CSA_ADDR_LO_DEFAULT 0x00000000 +#define regVPEC_QUEUE5_CSA_ADDR_HI_DEFAULT 0x00000000 +#define regVPEC_QUEUE5_CONTEXT_STATUS_DEFAULT 0x00000804 +#define regVPEC_QUEUE5_DOORBELL_LOG_DEFAULT 0x00000000 +#define regVPEC_QUEUE5_IB_SUB_REMAIN_DEFAULT 0x00000000 +#define regVPEC_QUEUE5_PREEMPT_DEFAULT 0x00000000 +#define regVPEC_QUEUE6_RB_CNTL_DEFAULT 0x00040800 +#define regVPEC_QUEUE6_SCHEDULE_CNTL_DEFAULT 0x00000000 +#define regVPEC_QUEUE6_RB_BASE_DEFAULT 0x00000000 +#define regVPEC_QUEUE6_RB_BASE_HI_DEFAULT 0x00000000 +#define regVPEC_QUEUE6_RB_RPTR_DEFAULT 0x00000000 +#define regVPEC_QUEUE6_RB_RPTR_HI_DEFAULT 0x00000000 +#define regVPEC_QUEUE6_RB_WPTR_DEFAULT 0x00000000 +#define regVPEC_QUEUE6_RB_WPTR_HI_DEFAULT 0x00000000 +#define regVPEC_QUEUE6_RB_RPTR_ADDR_HI_DEFAULT 0x00000000 +#define regVPEC_QUEUE6_RB_RPTR_ADDR_LO_DEFAULT 0x00000000 +#define regVPEC_QUEUE6_RB_AQL_CNTL_DEFAULT 0x00004000 +#define regVPEC_QUEUE6_MINOR_PTR_UPDATE_DEFAULT 0x00000000 +#define regVPEC_QUEUE6_CD_INFO_DEFAULT 0x00000000 +#define regVPEC_QUEUE6_RB_PREEMPT_DEFAULT 0x00000000 +#define regVPEC_QUEUE6_SKIP_CNTL_DEFAULT 0x00000000 +#define regVPEC_QUEUE6_DOORBELL_DEFAULT 0x00000000 +#define regVPEC_QUEUE6_DOORBELL_OFFSET_DEFAULT 0x00000000 +#define regVPEC_QUEUE6_DUMMY0_DEFAULT 0x0000000f +#define regVPEC_QUEUE6_DUMMY1_DEFAULT 0x00000000 +#define regVPEC_QUEUE6_DUMMY2_DEFAULT 0x00000000 +#define regVPEC_QUEUE6_DUMMY3_DEFAULT 0x00000000 +#define regVPEC_QUEUE6_DUMMY4_DEFAULT 0x00000000 +#define regVPEC_QUEUE6_IB_CNTL_DEFAULT 0x00000100 +#define regVPEC_QUEUE6_IB_RPTR_DEFAULT 0x00000000 +#define regVPEC_QUEUE6_IB_OFFSET_DEFAULT 0x00000000 +#define regVPEC_QUEUE6_IB_BASE_LO_DEFAULT 0x00000000 +#define regVPEC_QUEUE6_IB_BASE_HI_DEFAULT 0x00000000 +#define regVPEC_QUEUE6_IB_SIZE_DEFAULT 0x00000000 +#define regVPEC_QUEUE6_CMDIB_CNTL_DEFAULT 0x00000101 +#define regVPEC_QUEUE6_CMDIB_RPTR_DEFAULT 0x00000000 +#define regVPEC_QUEUE6_CMDIB_OFFSET_DEFAULT 0x00000000 +#define regVPEC_QUEUE6_CMDIB_BASE_LO_DEFAULT 0x00000000 +#define regVPEC_QUEUE6_CMDIB_BASE_HI_DEFAULT 0x00000000 +#define regVPEC_QUEUE6_CMDIB_SIZE_DEFAULT 0x00000000 +#define regVPEC_QUEUE6_CSA_ADDR_LO_DEFAULT 0x00000000 +#define regVPEC_QUEUE6_CSA_ADDR_HI_DEFAULT 0x00000000 +#define regVPEC_QUEUE6_CONTEXT_STATUS_DEFAULT 0x00000804 +#define regVPEC_QUEUE6_DOORBELL_LOG_DEFAULT 0x00000000 +#define regVPEC_QUEUE6_IB_SUB_REMAIN_DEFAULT 0x00000000 +#define regVPEC_QUEUE6_PREEMPT_DEFAULT 0x00000000 +#define regVPEC_QUEUE7_RB_CNTL_DEFAULT 0x00040800 +#define regVPEC_QUEUE7_SCHEDULE_CNTL_DEFAULT 0x00000000 +#define regVPEC_QUEUE7_RB_BASE_DEFAULT 0x00000000 +#define regVPEC_QUEUE7_RB_BASE_HI_DEFAULT 0x00000000 +#define regVPEC_QUEUE7_RB_RPTR_DEFAULT 0x00000000 +#define regVPEC_QUEUE7_RB_RPTR_HI_DEFAULT 0x00000000 +#define regVPEC_QUEUE7_RB_WPTR_DEFAULT 0x00000000 +#define regVPEC_QUEUE7_RB_WPTR_HI_DEFAULT 0x00000000 +#define regVPEC_QUEUE7_RB_RPTR_ADDR_HI_DEFAULT 0x00000000 +#define regVPEC_QUEUE7_RB_RPTR_ADDR_LO_DEFAULT 0x00000000 +#define regVPEC_QUEUE7_RB_AQL_CNTL_DEFAULT 0x00004000 +#define regVPEC_QUEUE7_MINOR_PTR_UPDATE_DEFAULT 0x00000000 +#define regVPEC_QUEUE7_CD_INFO_DEFAULT 0x00000000 +#define regVPEC_QUEUE7_RB_PREEMPT_DEFAULT 0x00000000 +#define regVPEC_QUEUE7_SKIP_CNTL_DEFAULT 0x00000000 +#define regVPEC_QUEUE7_DOORBELL_DEFAULT 0x00000000 +#define regVPEC_QUEUE7_DOORBELL_OFFSET_DEFAULT 0x00000000 +#define regVPEC_QUEUE7_DUMMY0_DEFAULT 0x0000000f +#define regVPEC_QUEUE7_DUMMY1_DEFAULT 0x00000000 +#define regVPEC_QUEUE7_DUMMY2_DEFAULT 0x00000000 +#define regVPEC_QUEUE7_DUMMY3_DEFAULT 0x00000000 +#define regVPEC_QUEUE7_DUMMY4_DEFAULT 0x00000000 +#define regVPEC_QUEUE7_IB_CNTL_DEFAULT 0x00000100 +#define regVPEC_QUEUE7_IB_RPTR_DEFAULT 0x00000000 +#define regVPEC_QUEUE7_IB_OFFSET_DEFAULT 0x00000000 +#define regVPEC_QUEUE7_IB_BASE_LO_DEFAULT 0x00000000 +#define regVPEC_QUEUE7_IB_BASE_HI_DEFAULT 0x00000000 +#define regVPEC_QUEUE7_IB_SIZE_DEFAULT 0x00000000 +#define regVPEC_QUEUE7_CMDIB_CNTL_DEFAULT 0x00000101 +#define regVPEC_QUEUE7_CMDIB_RPTR_DEFAULT 0x00000000 +#define regVPEC_QUEUE7_CMDIB_OFFSET_DEFAULT 0x00000000 +#define regVPEC_QUEUE7_CMDIB_BASE_LO_DEFAULT 0x00000000 +#define regVPEC_QUEUE7_CMDIB_BASE_HI_DEFAULT 0x00000000 +#define regVPEC_QUEUE7_CMDIB_SIZE_DEFAULT 0x00000000 +#define regVPEC_QUEUE7_CSA_ADDR_LO_DEFAULT 0x00000000 +#define regVPEC_QUEUE7_CSA_ADDR_HI_DEFAULT 0x00000000 +#define regVPEC_QUEUE7_CONTEXT_STATUS_DEFAULT 0x00000804 +#define regVPEC_QUEUE7_DOORBELL_LOG_DEFAULT 0x00000000 +#define regVPEC_QUEUE7_IB_SUB_REMAIN_DEFAULT 0x00000000 +#define regVPEC_QUEUE7_PREEMPT_DEFAULT 0x00000000 + + +// addressBlock: vpe_vpep_vpdpp0_dispdec_vpcnvc_cfg_dispdec +#define regVPCNVC_SURFACE_PIXEL_FORMAT_DEFAULT 0x00000008 +#define regVPCNVC_FORMAT_CONTROL_DEFAULT 0x00000000 +#define regVPCNVC_FCNV_FP_BIAS_R_DEFAULT 0x00000000 +#define regVPCNVC_FCNV_FP_BIAS_G_DEFAULT 0x00000000 +#define regVPCNVC_FCNV_FP_BIAS_B_DEFAULT 0x00000000 +#define regVPCNVC_FCNV_FP_SCALE_R_DEFAULT 0x0001f000 +#define regVPCNVC_FCNV_FP_SCALE_G_DEFAULT 0x0001f000 +#define regVPCNVC_FCNV_FP_SCALE_B_DEFAULT 0x0001f000 +#define regVPCNVC_COLOR_KEYER_CONTROL_DEFAULT 0x00000000 +#define regVPCNVC_COLOR_KEYER_ALPHA_DEFAULT 0x00000000 +#define regVPCNVC_COLOR_KEYER_RED_DEFAULT 0x00000000 +#define regVPCNVC_COLOR_KEYER_GREEN_DEFAULT 0x00000000 +#define regVPCNVC_COLOR_KEYER_BLUE_DEFAULT 0x00000000 +#define regVPCNVC_ALPHA_2BIT_LUT_DEFAULT 0xffaa5500 +#define regVPCNVC_PRE_DEALPHA_DEFAULT 0x00000000 +#define regVPCNVC_PRE_CSC_MODE_DEFAULT 0x00000000 +#define regVPCNVC_PRE_CSC_C11_C12_DEFAULT 0x00002000 +#define regVPCNVC_PRE_CSC_C13_C14_DEFAULT 0x00000000 +#define regVPCNVC_PRE_CSC_C21_C22_DEFAULT 0x20000000 +#define regVPCNVC_PRE_CSC_C23_C24_DEFAULT 0x00000000 +#define regVPCNVC_PRE_CSC_C31_C32_DEFAULT 0x00000000 +#define regVPCNVC_PRE_CSC_C33_C34_DEFAULT 0x00002000 +#define regVPCNVC_COEF_FORMAT_DEFAULT 0x00000000 +#define regVPCNVC_PRE_DEGAM_DEFAULT 0x00000000 +#define regVPCNVC_PRE_REALPHA_DEFAULT 0x00000000 +#define regVPCNVC_CFG_TEST_DEBUG_INDEX_DEFAULT 0x00000000 +#define regVPCNVC_CFG_TEST_DEBUG_DATA_DEFAULT 0x00000000 + + +// addressBlock: vpe_vpep_vpdpp0_dispdec_vpdscl_dispdec +#define regVPDSCL_COEF_RAM_TAP_SELECT_DEFAULT 0x00000000 +#define regVPDSCL_COEF_RAM_TAP_DATA_DEFAULT 0x00000000 +#define regVPDSCL_MODE_DEFAULT 0x00000000 +#define regVPDSCL_TAP_CONTROL_DEFAULT 0x00000000 +#define regVPDSCL_CONTROL_DEFAULT 0x00000000 +#define regVPDSCL_2TAP_CONTROL_DEFAULT 0x01000100 +#define regVPDSCL_MANUAL_REPLICATE_CONTROL_DEFAULT 0x00000000 +#define regVPDSCL_HORZ_FILTER_SCALE_RATIO_DEFAULT 0x00000000 +#define regVPDSCL_HORZ_FILTER_INIT_DEFAULT 0x01000000 +#define regVPDSCL_HORZ_FILTER_SCALE_RATIO_C_DEFAULT 0x00000000 +#define regVPDSCL_HORZ_FILTER_INIT_C_DEFAULT 0x01000000 +#define regVPDSCL_VERT_FILTER_SCALE_RATIO_DEFAULT 0x00000000 +#define regVPDSCL_VERT_FILTER_INIT_DEFAULT 0x01000000 +#define regVPDSCL_VERT_FILTER_INIT_BOT_DEFAULT 0x01000000 +#define regVPDSCL_VERT_FILTER_SCALE_RATIO_C_DEFAULT 0x00000000 +#define regVPDSCL_VERT_FILTER_INIT_C_DEFAULT 0x01000000 +#define regVPDSCL_VERT_FILTER_INIT_BOT_C_DEFAULT 0x01000000 +#define regVPDSCL_BLACK_COLOR_DEFAULT 0x3c000000 +#define regVPDSCL_UPDATE_DEFAULT 0x00000000 +#define regVPDSCL_AUTOCAL_DEFAULT 0x00000000 +#define regVPDSCL_EXT_OVERSCAN_LEFT_RIGHT_DEFAULT 0x00000000 +#define regVPDSCL_EXT_OVERSCAN_TOP_BOTTOM_DEFAULT 0x00000000 +#define regVPOTG_H_BLANK_DEFAULT 0x00000000 +#define regVPOTG_V_BLANK_DEFAULT 0x00000000 +#define regVPDSCL_RECOUT_START_DEFAULT 0x00000000 +#define regVPDSCL_RECOUT_SIZE_DEFAULT 0x00000000 +#define regVPMPC_SIZE_DEFAULT 0x00000000 +#define regVPLB_DATA_FORMAT_DEFAULT 0x00000000 +#define regVPLB_MEMORY_CTRL_DEFAULT 0x00003f00 +#define regVPLB_V_COUNTER_DEFAULT 0x00000000 +#define regVPDSCL_MEM_PWR_CTRL_DEFAULT 0x00000000 +#define regVPDSCL_MEM_PWR_STATUS_DEFAULT 0x00000000 +#define regVPDSCL_DEBUG_DEFAULT 0x00000000 +#define regVPDSCL_TEST_DEBUG_INDEX_DEFAULT 0x00000000 +#define regVPDSCL_TEST_DEBUG_DATA_DEFAULT 0x00000000 + + +// addressBlock: vpe_vpep_vpdpp0_dispdec_vpcm_dispdec +#define regVPCM_CONTROL_DEFAULT 0x00000000 +#define regVPCM_POST_CSC_CONTROL_DEFAULT 0x00000000 +#define regVPCM_POST_CSC_C11_C12_DEFAULT 0x00002000 +#define regVPCM_POST_CSC_C13_C14_DEFAULT 0x00000000 +#define regVPCM_POST_CSC_C21_C22_DEFAULT 0x20000000 +#define regVPCM_POST_CSC_C23_C24_DEFAULT 0x00000000 +#define regVPCM_POST_CSC_C31_C32_DEFAULT 0x00000000 +#define regVPCM_POST_CSC_C33_C34_DEFAULT 0x00002000 +#define regVPCM_GAMUT_REMAP_CONTROL_DEFAULT 0x00000000 +#define regVPCM_GAMUT_REMAP_C11_C12_DEFAULT 0x00002000 +#define regVPCM_GAMUT_REMAP_C13_C14_DEFAULT 0x00000000 +#define regVPCM_GAMUT_REMAP_C21_C22_DEFAULT 0x20000000 +#define regVPCM_GAMUT_REMAP_C23_C24_DEFAULT 0x00000000 +#define regVPCM_GAMUT_REMAP_C31_C32_DEFAULT 0x00000000 +#define regVPCM_GAMUT_REMAP_C33_C34_DEFAULT 0x00002000 +#define regVPCM_BIAS_CR_R_DEFAULT 0x00000000 +#define regVPCM_BIAS_Y_G_CB_B_DEFAULT 0x00000000 +#define regVPCM_GAMCOR_CONTROL_DEFAULT 0x00000000 +#define regVPCM_GAMCOR_LUT_INDEX_DEFAULT 0x00000000 +#define regVPCM_GAMCOR_LUT_DATA_DEFAULT 0x00000000 +#define regVPCM_GAMCOR_LUT_CONTROL_DEFAULT 0x00000007 +#define regVPCM_GAMCOR_RAMA_START_CNTL_B_DEFAULT 0x00000000 +#define regVPCM_GAMCOR_RAMA_START_CNTL_G_DEFAULT 0x00000000 +#define regVPCM_GAMCOR_RAMA_START_CNTL_R_DEFAULT 0x00000000 +#define regVPCM_GAMCOR_RAMA_START_SLOPE_CNTL_B_DEFAULT 0x00000000 +#define regVPCM_GAMCOR_RAMA_START_SLOPE_CNTL_G_DEFAULT 0x00000000 +#define regVPCM_GAMCOR_RAMA_START_SLOPE_CNTL_R_DEFAULT 0x00000000 +#define regVPCM_GAMCOR_RAMA_START_BASE_CNTL_B_DEFAULT 0x00000000 +#define regVPCM_GAMCOR_RAMA_START_BASE_CNTL_G_DEFAULT 0x00000000 +#define regVPCM_GAMCOR_RAMA_START_BASE_CNTL_R_DEFAULT 0x00000000 +#define regVPCM_GAMCOR_RAMA_END_CNTL1_B_DEFAULT 0x00000000 +#define regVPCM_GAMCOR_RAMA_END_CNTL2_B_DEFAULT 0x00000000 +#define regVPCM_GAMCOR_RAMA_END_CNTL1_G_DEFAULT 0x00000000 +#define regVPCM_GAMCOR_RAMA_END_CNTL2_G_DEFAULT 0x00000000 +#define regVPCM_GAMCOR_RAMA_END_CNTL1_R_DEFAULT 0x00000000 +#define regVPCM_GAMCOR_RAMA_END_CNTL2_R_DEFAULT 0x00000000 +#define regVPCM_GAMCOR_RAMA_OFFSET_B_DEFAULT 0x00000000 +#define regVPCM_GAMCOR_RAMA_OFFSET_G_DEFAULT 0x00000000 +#define regVPCM_GAMCOR_RAMA_OFFSET_R_DEFAULT 0x00000000 +#define regVPCM_GAMCOR_RAMA_REGION_0_1_DEFAULT 0x00000000 +#define regVPCM_GAMCOR_RAMA_REGION_2_3_DEFAULT 0x00000000 +#define regVPCM_GAMCOR_RAMA_REGION_4_5_DEFAULT 0x00000000 +#define regVPCM_GAMCOR_RAMA_REGION_6_7_DEFAULT 0x00000000 +#define regVPCM_GAMCOR_RAMA_REGION_8_9_DEFAULT 0x00000000 +#define regVPCM_GAMCOR_RAMA_REGION_10_11_DEFAULT 0x00000000 +#define regVPCM_GAMCOR_RAMA_REGION_12_13_DEFAULT 0x00000000 +#define regVPCM_GAMCOR_RAMA_REGION_14_15_DEFAULT 0x00000000 +#define regVPCM_GAMCOR_RAMA_REGION_16_17_DEFAULT 0x00000000 +#define regVPCM_GAMCOR_RAMA_REGION_18_19_DEFAULT 0x00000000 +#define regVPCM_GAMCOR_RAMA_REGION_20_21_DEFAULT 0x00000000 +#define regVPCM_GAMCOR_RAMA_REGION_22_23_DEFAULT 0x00000000 +#define regVPCM_GAMCOR_RAMA_REGION_24_25_DEFAULT 0x00000000 +#define regVPCM_GAMCOR_RAMA_REGION_26_27_DEFAULT 0x00000000 +#define regVPCM_GAMCOR_RAMA_REGION_28_29_DEFAULT 0x00000000 +#define regVPCM_GAMCOR_RAMA_REGION_30_31_DEFAULT 0x00000000 +#define regVPCM_GAMCOR_RAMA_REGION_32_33_DEFAULT 0x00000000 +#define regVPCM_HDR_MULT_COEF_DEFAULT 0x0001f000 +#define regVPCM_MEM_PWR_CTRL_DEFAULT 0x00000000 +#define regVPCM_MEM_PWR_STATUS_DEFAULT 0x00000000 +#define regVPCM_DEALPHA_DEFAULT 0x00000000 +#define regVPCM_COEF_FORMAT_DEFAULT 0x00000000 +#define regVPCM_TEST_DEBUG_INDEX_DEFAULT 0x00000000 +#define regVPCM_TEST_DEBUG_DATA_DEFAULT 0x00000000 + + +// addressBlock: vpe_vpep_vpdpp0_dispdec_vpdpp_top_dispdec +#define regVPDPP_CONTROL_DEFAULT 0x70000000 +#define regVPDPP_SOFT_RESET_DEFAULT 0x00000000 +#define regVPDPP_CRC_VAL_R_G_DEFAULT 0x00000000 +#define regVPDPP_CRC_VAL_B_A_DEFAULT 0x00000000 +#define regVPDPP_CRC_CTRL_DEFAULT 0x00000000 +#define regVPHOST_READ_CONTROL_DEFAULT 0x00000000 +#define regVPDPP_DEBUG_SEL_DEFAULT 0x00000000 +#define regVPDPP_DEBUG_SPARE_DEFAULT 0x00000000 +#define regVPDPP_TEST_DEBUG_INDEX_DEFAULT 0x00000000 +#define regVPDPP_TEST_DEBUG_DATA_DEFAULT 0x00000000 + + +// addressBlock: vpe_vpep_vpmpc_vpmpcc0_dispdec +#define regVPMPCC_TOP_SEL_DEFAULT 0x0000000f +#define regVPMPCC_BOT_SEL_DEFAULT 0x0000000f +#define regVPMPCC_VPOPP_ID_DEFAULT 0x0000000f +#define regVPMPCC_CONTROL_DEFAULT 0xffff0461 +#define regVPMPCC_TOP_GAIN_DEFAULT 0x0001f000 +#define regVPMPCC_BOT_GAIN_INSIDE_DEFAULT 0x0001f000 +#define regVPMPCC_BOT_GAIN_OUTSIDE_DEFAULT 0x0001f000 +#define regVPMPCC_MOVABLE_CM_LOCATION_CONTROL_DEFAULT 0x00000001 +#define regVPMPCC_BG_R_CR_DEFAULT 0x00000000 +#define regVPMPCC_BG_G_Y_DEFAULT 0x00000000 +#define regVPMPCC_BG_B_CB_DEFAULT 0x00000000 +#define regVPMPCC_MEM_PWR_CTRL_DEFAULT 0x00000010 +#define regVPMPCC_STATUS_DEFAULT 0x00000000 +#define regVPMPCC_TEST_DEBUG_INDEX_DEFAULT 0x00000000 +#define regVPMPCC_TEST_DEBUG_DATA_DEFAULT 0x00000000 + + +// addressBlock: vpe_vpep_vpmpc_vpmpc_cfg_dispdec +#define regVPMPC_CLOCK_CONTROL_DEFAULT 0x00000000 +#define regVPMPC_SOFT_RESET_DEFAULT 0x00000000 +#define regVPMPC_CRC_CTRL_DEFAULT 0x00000000 +#define regVPMPC_CRC_SEL_CONTROL_DEFAULT 0x00000000 +#define regVPMPC_CRC_RESULT_AR_DEFAULT 0x00000000 +#define regVPMPC_CRC_RESULT_GB_DEFAULT 0x00000000 +#define regVPMPC_CRC_RESULT_C_DEFAULT 0x00000000 +#define regVPMPC_DEBUG_CONTROL_DEFAULT 0x0000ff00 +#define regVPMPCC_DEBUG_DATA_SELECT_DEFAULT 0x3f2f1f0f +#define regVPMPC_BYPASS_BG_AR_DEFAULT 0x00000000 +#define regVPMPC_BYPASS_BG_GB_DEFAULT 0x00000000 +#define regVPMPC_HOST_READ_CONTROL_DEFAULT 0x00000000 +#define regVPMPC_PENDING_STATUS_MISC_DEFAULT 0x00000000 +#define regVPMPC_CFG_TEST_DEBUG_INDEX_DEFAULT 0x00000000 +#define regVPMPC_CFG_TEST_DEBUG_DATA_DEFAULT 0x00000000 + + +// addressBlock: vpe_vpep_vpmpc_vpmpcc_ogam0_dispdec +#define regVPMPCC_OGAM_CONTROL_DEFAULT 0x00000000 +#define regVPMPCC_OGAM_LUT_INDEX_DEFAULT 0x00000000 +#define regVPMPCC_OGAM_LUT_DATA_DEFAULT 0x00000000 +#define regVPMPCC_OGAM_LUT_CONTROL_DEFAULT 0x00000007 +#define regVPMPCC_OGAM_RAMA_START_CNTL_B_DEFAULT 0x00000000 +#define regVPMPCC_OGAM_RAMA_START_CNTL_G_DEFAULT 0x00000000 +#define regVPMPCC_OGAM_RAMA_START_CNTL_R_DEFAULT 0x00000000 +#define regVPMPCC_OGAM_RAMA_START_SLOPE_CNTL_B_DEFAULT 0x00000000 +#define regVPMPCC_OGAM_RAMA_START_SLOPE_CNTL_G_DEFAULT 0x00000000 +#define regVPMPCC_OGAM_RAMA_START_SLOPE_CNTL_R_DEFAULT 0x00000000 +#define regVPMPCC_OGAM_RAMA_START_BASE_CNTL_B_DEFAULT 0x00000000 +#define regVPMPCC_OGAM_RAMA_START_BASE_CNTL_G_DEFAULT 0x00000000 +#define regVPMPCC_OGAM_RAMA_START_BASE_CNTL_R_DEFAULT 0x00000000 +#define regVPMPCC_OGAM_RAMA_END_CNTL1_B_DEFAULT 0x00000000 +#define regVPMPCC_OGAM_RAMA_END_CNTL2_B_DEFAULT 0x00000000 +#define regVPMPCC_OGAM_RAMA_END_CNTL1_G_DEFAULT 0x00000000 +#define regVPMPCC_OGAM_RAMA_END_CNTL2_G_DEFAULT 0x00000000 +#define regVPMPCC_OGAM_RAMA_END_CNTL1_R_DEFAULT 0x00000000 +#define regVPMPCC_OGAM_RAMA_END_CNTL2_R_DEFAULT 0x00000000 +#define regVPMPCC_OGAM_RAMA_OFFSET_B_DEFAULT 0x00000000 +#define regVPMPCC_OGAM_RAMA_OFFSET_G_DEFAULT 0x00000000 +#define regVPMPCC_OGAM_RAMA_OFFSET_R_DEFAULT 0x00000000 +#define regVPMPCC_OGAM_RAMA_REGION_0_1_DEFAULT 0x00000000 +#define regVPMPCC_OGAM_RAMA_REGION_2_3_DEFAULT 0x00000000 +#define regVPMPCC_OGAM_RAMA_REGION_4_5_DEFAULT 0x00000000 +#define regVPMPCC_OGAM_RAMA_REGION_6_7_DEFAULT 0x00000000 +#define regVPMPCC_OGAM_RAMA_REGION_8_9_DEFAULT 0x00000000 +#define regVPMPCC_OGAM_RAMA_REGION_10_11_DEFAULT 0x00000000 +#define regVPMPCC_OGAM_RAMA_REGION_12_13_DEFAULT 0x00000000 +#define regVPMPCC_OGAM_RAMA_REGION_14_15_DEFAULT 0x00000000 +#define regVPMPCC_OGAM_RAMA_REGION_16_17_DEFAULT 0x00000000 +#define regVPMPCC_OGAM_RAMA_REGION_18_19_DEFAULT 0x00000000 +#define regVPMPCC_OGAM_RAMA_REGION_20_21_DEFAULT 0x00000000 +#define regVPMPCC_OGAM_RAMA_REGION_22_23_DEFAULT 0x00000000 +#define regVPMPCC_OGAM_RAMA_REGION_24_25_DEFAULT 0x00000000 +#define regVPMPCC_OGAM_RAMA_REGION_26_27_DEFAULT 0x00000000 +#define regVPMPCC_OGAM_RAMA_REGION_28_29_DEFAULT 0x00000000 +#define regVPMPCC_OGAM_RAMA_REGION_30_31_DEFAULT 0x00000000 +#define regVPMPCC_OGAM_RAMA_REGION_32_33_DEFAULT 0x00000000 +#define regVPMPCC_GAMUT_REMAP_COEF_FORMAT_DEFAULT 0x00000000 +#define regVPMPCC_GAMUT_REMAP_MODE_DEFAULT 0x00000000 +#define regVPMPC_GAMUT_REMAP_C11_C12_A_DEFAULT 0x00000000 +#define regVPMPC_GAMUT_REMAP_C13_C14_A_DEFAULT 0x00000000 +#define regVPMPC_GAMUT_REMAP_C21_C22_A_DEFAULT 0x00000000 +#define regVPMPC_GAMUT_REMAP_C23_C24_A_DEFAULT 0x00000000 +#define regVPMPC_GAMUT_REMAP_C31_C32_A_DEFAULT 0x00000000 +#define regVPMPC_GAMUT_REMAP_C33_C34_A_DEFAULT 0x00000000 +#define regVPMPCC_OGAM_TEST_DEBUG_INDEX_DEFAULT 0x00000000 +#define regVPMPCC_OGAM_TEST_DEBUG_DATA_DEFAULT 0x00000000 + + +// addressBlock: vpe_vpep_vpmpc_vpmpcc_mcm0_dispdec +#define regVPMPCC_MCM_SHAPER_CONTROL_DEFAULT 0x00000000 +#define regVPMPCC_MCM_SHAPER_OFFSET_R_DEFAULT 0x00000000 +#define regVPMPCC_MCM_SHAPER_OFFSET_G_DEFAULT 0x00000000 +#define regVPMPCC_MCM_SHAPER_OFFSET_B_DEFAULT 0x00000000 +#define regVPMPCC_MCM_SHAPER_SCALE_R_DEFAULT 0x00007000 +#define regVPMPCC_MCM_SHAPER_SCALE_G_B_DEFAULT 0x70007000 +#define regVPMPCC_MCM_SHAPER_LUT_INDEX_DEFAULT 0x00000000 +#define regVPMPCC_MCM_SHAPER_LUT_DATA_DEFAULT 0x00000000 +#define regVPMPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_DEFAULT 0x00000007 +#define regVPMPCC_MCM_SHAPER_RAMA_START_CNTL_B_DEFAULT 0x00000000 +#define regVPMPCC_MCM_SHAPER_RAMA_START_CNTL_G_DEFAULT 0x00000000 +#define regVPMPCC_MCM_SHAPER_RAMA_START_CNTL_R_DEFAULT 0x00000000 +#define regVPMPCC_MCM_SHAPER_RAMA_END_CNTL_B_DEFAULT 0x00000000 +#define regVPMPCC_MCM_SHAPER_RAMA_END_CNTL_G_DEFAULT 0x00000000 +#define regVPMPCC_MCM_SHAPER_RAMA_END_CNTL_R_DEFAULT 0x00000000 +#define regVPMPCC_MCM_SHAPER_RAMA_REGION_0_1_DEFAULT 0x00000000 +#define regVPMPCC_MCM_SHAPER_RAMA_REGION_2_3_DEFAULT 0x00000000 +#define regVPMPCC_MCM_SHAPER_RAMA_REGION_4_5_DEFAULT 0x00000000 +#define regVPMPCC_MCM_SHAPER_RAMA_REGION_6_7_DEFAULT 0x00000000 +#define regVPMPCC_MCM_SHAPER_RAMA_REGION_8_9_DEFAULT 0x00000000 +#define regVPMPCC_MCM_SHAPER_RAMA_REGION_10_11_DEFAULT 0x00000000 +#define regVPMPCC_MCM_SHAPER_RAMA_REGION_12_13_DEFAULT 0x00000000 +#define regVPMPCC_MCM_SHAPER_RAMA_REGION_14_15_DEFAULT 0x00000000 +#define regVPMPCC_MCM_SHAPER_RAMA_REGION_16_17_DEFAULT 0x00000000 +#define regVPMPCC_MCM_SHAPER_RAMA_REGION_18_19_DEFAULT 0x00000000 +#define regVPMPCC_MCM_SHAPER_RAMA_REGION_20_21_DEFAULT 0x00000000 +#define regVPMPCC_MCM_SHAPER_RAMA_REGION_22_23_DEFAULT 0x00000000 +#define regVPMPCC_MCM_SHAPER_RAMA_REGION_24_25_DEFAULT 0x00000000 +#define regVPMPCC_MCM_SHAPER_RAMA_REGION_26_27_DEFAULT 0x00000000 +#define regVPMPCC_MCM_SHAPER_RAMA_REGION_28_29_DEFAULT 0x00000000 +#define regVPMPCC_MCM_SHAPER_RAMA_REGION_30_31_DEFAULT 0x00000000 +#define regVPMPCC_MCM_SHAPER_RAMA_REGION_32_33_DEFAULT 0x00000000 +#define regVPMPCC_MCM_3DLUT_MODE_DEFAULT 0x00000000 +#define regVPMPCC_MCM_3DLUT_INDEX_DEFAULT 0x00000000 +#define regVPMPCC_MCM_3DLUT_DATA_DEFAULT 0x00000000 +#define regVPMPCC_MCM_3DLUT_DATA_30BIT_DEFAULT 0x00000000 +#define regVPMPCC_MCM_3DLUT_READ_WRITE_CONTROL_DEFAULT 0x0000000f +#define regVPMPCC_MCM_3DLUT_OUT_NORM_FACTOR_DEFAULT 0x00008008 +#define regVPMPCC_MCM_3DLUT_OUT_OFFSET_R_DEFAULT 0x3c000000 +#define regVPMPCC_MCM_3DLUT_OUT_OFFSET_G_DEFAULT 0x3c000000 +#define regVPMPCC_MCM_3DLUT_OUT_OFFSET_B_DEFAULT 0x3c000000 +#define regVPMPCC_MCM_1DLUT_CONTROL_DEFAULT 0x00000000 +#define regVPMPCC_MCM_1DLUT_LUT_INDEX_DEFAULT 0x00000000 +#define regVPMPCC_MCM_1DLUT_LUT_DATA_DEFAULT 0x00000000 +#define regVPMPCC_MCM_1DLUT_LUT_CONTROL_DEFAULT 0x00000007 +#define regVPMPCC_MCM_1DLUT_RAMA_START_CNTL_B_DEFAULT 0x00000000 +#define regVPMPCC_MCM_1DLUT_RAMA_START_CNTL_G_DEFAULT 0x00000000 +#define regVPMPCC_MCM_1DLUT_RAMA_START_CNTL_R_DEFAULT 0x00000000 +#define regVPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B_DEFAULT 0x00000000 +#define regVPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G_DEFAULT 0x00000000 +#define regVPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R_DEFAULT 0x00000000 +#define regVPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B_DEFAULT 0x00000000 +#define regVPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G_DEFAULT 0x00000000 +#define regVPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R_DEFAULT 0x00000000 +#define regVPMPCC_MCM_1DLUT_RAMA_END_CNTL1_B_DEFAULT 0x00000000 +#define regVPMPCC_MCM_1DLUT_RAMA_END_CNTL2_B_DEFAULT 0x00000000 +#define regVPMPCC_MCM_1DLUT_RAMA_END_CNTL1_G_DEFAULT 0x00000000 +#define regVPMPCC_MCM_1DLUT_RAMA_END_CNTL2_G_DEFAULT 0x00000000 +#define regVPMPCC_MCM_1DLUT_RAMA_END_CNTL1_R_DEFAULT 0x00000000 +#define regVPMPCC_MCM_1DLUT_RAMA_END_CNTL2_R_DEFAULT 0x00000000 +#define regVPMPCC_MCM_1DLUT_RAMA_OFFSET_B_DEFAULT 0x00000000 +#define regVPMPCC_MCM_1DLUT_RAMA_OFFSET_G_DEFAULT 0x00000000 +#define regVPMPCC_MCM_1DLUT_RAMA_OFFSET_R_DEFAULT 0x00000000 +#define regVPMPCC_MCM_1DLUT_RAMA_REGION_0_1_DEFAULT 0x00000000 +#define regVPMPCC_MCM_1DLUT_RAMA_REGION_2_3_DEFAULT 0x00000000 +#define regVPMPCC_MCM_1DLUT_RAMA_REGION_4_5_DEFAULT 0x00000000 +#define regVPMPCC_MCM_1DLUT_RAMA_REGION_6_7_DEFAULT 0x00000000 +#define regVPMPCC_MCM_1DLUT_RAMA_REGION_8_9_DEFAULT 0x00000000 +#define regVPMPCC_MCM_1DLUT_RAMA_REGION_10_11_DEFAULT 0x00000000 +#define regVPMPCC_MCM_1DLUT_RAMA_REGION_12_13_DEFAULT 0x00000000 +#define regVPMPCC_MCM_1DLUT_RAMA_REGION_14_15_DEFAULT 0x00000000 +#define regVPMPCC_MCM_1DLUT_RAMA_REGION_16_17_DEFAULT 0x00000000 +#define regVPMPCC_MCM_1DLUT_RAMA_REGION_18_19_DEFAULT 0x00000000 +#define regVPMPCC_MCM_1DLUT_RAMA_REGION_20_21_DEFAULT 0x00000000 +#define regVPMPCC_MCM_1DLUT_RAMA_REGION_22_23_DEFAULT 0x00000000 +#define regVPMPCC_MCM_1DLUT_RAMA_REGION_24_25_DEFAULT 0x00000000 +#define regVPMPCC_MCM_1DLUT_RAMA_REGION_26_27_DEFAULT 0x00000000 +#define regVPMPCC_MCM_1DLUT_RAMA_REGION_28_29_DEFAULT 0x00000000 +#define regVPMPCC_MCM_1DLUT_RAMA_REGION_30_31_DEFAULT 0x00000000 +#define regVPMPCC_MCM_1DLUT_RAMA_REGION_32_33_DEFAULT 0x00000000 +#define regVPMPCC_MCM_MEM_PWR_CTRL_DEFAULT 0x00101010 +#define regVPMPCC_MCM_TEST_DEBUG_INDEX_DEFAULT 0x00000000 +#define regVPMPCC_MCM_TEST_DEBUG_DATA_DEFAULT 0x00000000 + + +// addressBlock: vpe_vpep_vpmpc_vpmpc_ocsc_dispdec +#define regVPMPC_OUT0_MUX_DEFAULT 0x0000000f +#define regVPMPC_OUT0_FLOAT_CONTROL_DEFAULT 0x00000000 +#define regVPMPC_OUT0_DENORM_CONTROL_DEFAULT 0x00fff000 +#define regVPMPC_OUT0_DENORM_CLAMP_G_Y_DEFAULT 0x00fff000 +#define regVPMPC_OUT0_DENORM_CLAMP_B_CB_DEFAULT 0x00fff000 +#define regVPMPC_OUT_CSC_COEF_FORMAT_DEFAULT 0x00000000 +#define regVPMPC_OUT0_CSC_MODE_DEFAULT 0x00000000 +#define regVPMPC_OUT0_CSC_C11_C12_A_DEFAULT 0x00000000 +#define regVPMPC_OUT0_CSC_C13_C14_A_DEFAULT 0x00000000 +#define regVPMPC_OUT0_CSC_C21_C22_A_DEFAULT 0x00000000 +#define regVPMPC_OUT0_CSC_C23_C24_A_DEFAULT 0x00000000 +#define regVPMPC_OUT0_CSC_C31_C32_A_DEFAULT 0x00000000 +#define regVPMPC_OUT0_CSC_C33_C34_A_DEFAULT 0x00000000 +#define regVPMPC_OCSC_TEST_DEBUG_INDEX_DEFAULT 0x00000000 +#define regVPMPC_OCSC_TEST_DEBUG_DATA_DEFAULT 0x00000000 + + +// addressBlock: vpe_vpep_vpopp_vpfmt0_dispdec +#define regVPFMT_CLAMP_COMPONENT_R_DEFAULT 0x00000000 +#define regVPFMT_CLAMP_COMPONENT_G_DEFAULT 0x00000000 +#define regVPFMT_CLAMP_COMPONENT_B_DEFAULT 0x00000000 +#define regVPFMT_DYNAMIC_EXP_CNTL_DEFAULT 0x00000000 +#define regVPFMT_CONTROL_DEFAULT 0x00000000 +#define regVPFMT_BIT_DEPTH_CONTROL_DEFAULT 0x00000000 +#define regVPFMT_DITHER_RAND_R_SEED_DEFAULT 0x00000000 +#define regVPFMT_DITHER_RAND_G_SEED_DEFAULT 0x00000099 +#define regVPFMT_DITHER_RAND_B_SEED_DEFAULT 0x000000dd +#define regVPFMT_CLAMP_CNTL_DEFAULT 0x00000000 +#define regVPFMT_DEBUG_CNTL_DEFAULT 0x00000000 +#define regVPFMT_TEST_DEBUG_INDEX_DEFAULT 0x00000000 +#define regVPFMT_TEST_DEBUG_DATA_DEFAULT 0x00000000 + + +// addressBlock: vpe_vpep_vpopp_vpopp_pipe0_dispdec +#define regVPOPP_PIPE_CONTROL_DEFAULT 0x00000000 +#define regVPOPP_PIPE_SPARE_DEBUG_DEFAULT 0x00000000 +#define regVPOPP_PIPE_TEST_DEBUG_INDEX_DEFAULT 0x00000000 +#define regVPOPP_PIPE_TEST_DEBUG_DATA_DEFAULT 0x00000000 + + +// addressBlock: vpe_vpep_vpopp_vpopp_pipe_crc0_dispdec +#define regVPOPP_PIPE_CRC_CONTROL_DEFAULT 0x00000000 +#define regVPOPP_PIPE_CRC_MASK_DEFAULT 0x0000ffff +#define regVPOPP_PIPE_CRC_RESULT0_DEFAULT 0x00000000 +#define regVPOPP_PIPE_CRC_RESULT1_DEFAULT 0x00000000 +#define regVPOPP_PIPE_CRC_RESULT2_DEFAULT 0x00000000 + + +// addressBlock: vpe_vpep_vpopp_vpopp_top_dispdec +#define regVPOPP_TOP_CLK_CONTROL_DEFAULT 0x00000000 +#define regVPOPP_DEBUG_CONTROL_DEFAULT 0x00000000 +#define regVPOPP_TOP_SPARE_DEBUG_DEFAULT 0x00000000 +#define regVPOPP_TOP_TEST_DEBUG_INDEX_DEFAULT 0x00000000 +#define regVPOPP_TOP_TEST_DEBUG_DATA_DEFAULT 0x00000000 + + +// addressBlock: vpe_vpep_vpcdc_cdc_dispdec +#define regVPEP_MGCG_CNTL_DEFAULT 0x00000000 +#define regVPCDC_SOFT_RESET_DEFAULT 0x00000000 +#define regVPCDC_FE0_SURFACE_CONFIG_DEFAULT 0x00000000 +#define regVPCDC_FE0_CROSSBAR_CONFIG_DEFAULT 0x00000000 +#define regVPCDC_FE0_VIEWPORT_START_CONFIG_DEFAULT 0x00000000 +#define regVPCDC_FE0_VIEWPORT_DIMENSION_CONFIG_DEFAULT 0x00000000 +#define regVPCDC_FE0_VIEWPORT_START_C_CONFIG_DEFAULT 0x00000000 +#define regVPCDC_FE0_VIEWPORT_DIMENSION_C_CONFIG_DEFAULT 0x00000000 +#define regVPCDC_BE0_P2B_CONFIG_DEFAULT 0x00000036 +#define regVPCDC_BE0_GLOBAL_SYNC_CONFIG_DEFAULT 0x00000000 +#define regVPCDC_GLOBAL_SYNC_TRIGGER_DEFAULT 0x00000000 +#define regVPCDC_VREADY_STATUS_DEFAULT 0x00000000 +#define regVPEP_MEM_GLOBAL_PWR_REQ_CNTL_DEFAULT 0x00000000 +#define regVPFE_MEM_PWR_CNTL_DEFAULT 0x00000000 +#define regVPBE_MEM_PWR_CNTL_DEFAULT 0x00000000 +#define regVPEP_RBBMIF_TIMEOUT_DEFAULT 0x01f00100 +#define regVPEP_RBBMIF_STATUS_DEFAULT 0x00000000 +#define regVPEP_RBBMIF_TIMEOUT_DIS_DEFAULT 0x00000000 +#define regVPCDC_DEBUG_CTRL0_DEFAULT 0x00000000 +#define regVPCDC_DEBUG_CTRL1_DEFAULT 0x00000000 +#define regVPCDC_TEST_DEBUG_INDEX_DEFAULT 0x00000000 +#define regVPCDC_TEST_DEBUG_DATA_DEFAULT 0x00000000 + + +// addressBlock: vpe_vpep_vpcdc_vpcdc_dcperfmon_dc_perfmon_dispdec +#define regPERFCOUNTER_CNTL_DEFAULT 0x00000000 +#define regPERFCOUNTER_CNTL2_DEFAULT 0x00000000 +#define regPERFCOUNTER_STATE_DEFAULT 0x00000000 +#define regPERFMON_CNTL_DEFAULT 0x00000100 +#define regPERFMON_CNTL2_DEFAULT 0x00000000 +#define regPERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 +#define regPERFMON_CVALUE_LOW_DEFAULT 0x00000000 +#define regPERFMON_HI_DEFAULT 0x00000000 +#define regPERFMON_LOW_DEFAULT 0x00000000 +#define regPERFMON_TEST_DEBUG_INDEX_DEFAULT 0x00000000 +#define regPERFMON_TEST_DEBUG_DATA_DEFAULT 0x00000000 + + +// addressBlock: dc_perfmon_dc_perfmondebugind +#define ixPERFMON_DEBUG_ID_DEFAULT 0x00000000 +#define ixPERFMON_DEBUG01_DEFAULT 0x00000000 +#define ixPERFMON_DEBUG02_DEFAULT 0x00000000 +#define ixPERFMON_DEBUG03_DEFAULT 0x00000000 +#define ixPERFMON_DEBUG04_DEFAULT 0x00000000 +#define ixPERFMON_DEBUG05_DEFAULT 0x00000000 +#define ixPERFMON_DEBUG06_DEFAULT 0x00000000 +#define ixPERFMON_DEBUG07_DEFAULT 0x00000000 +#define ixPERFMON_DEBUG08_DEFAULT 0x00000000 +#define ixPERFMON_DEBUG09_DEFAULT 0x00000000 +#define ixPERFMON_DEBUG0A_DEFAULT 0x00000000 +#define ixPERFMON_DEBUG0B_DEFAULT 0x00000000 +#define ixPERFMON_DEBUG0C_DEFAULT 0x00000000 +#define ixPERFMON_DEBUG0D_DEFAULT 0x00000000 +#define ixPERFMON_DEBUG0E_DEFAULT 0x00000000 +#define ixPERFMON_DEBUG0F_DEFAULT 0x00000000 +#define ixPERFMON_DEBUG10_DEFAULT 0x00000000 +#define ixPERFMON_DEBUG11_DEFAULT 0x00000000 +#define ixPERFMON_DEBUG12_DEFAULT 0x00000000 + + +// addressBlock: vpfmt0_vpfmtdebugind +#define ixVPFMT_DEBUG_ID_DEFAULT 0x00000000 +#define ixVPFMT_DEBUG0_DEFAULT 0x00000000 +#define ixVPFMT_DEBUG1_DEFAULT 0x00000000 +#define ixVPFMT_DEBUG2_DEFAULT 0x00000000 +#define ixVPFMT_DEBUG3_DEFAULT 0x00000000 +#define ixVPFMT_DEBUG4_DEFAULT 0x00000000 +#define ixVPFMT_DEBUG5_DEFAULT 0x00000000 +#define ixVPFMT_DEBUG6_DEFAULT 0x00000000 +#define ixVPFMT_DEBUG7_DEFAULT 0x00000000 +#define ixVPFMT_DEBUG8_DEFAULT 0x00000000 +#define ixVPFMT_DEBUG9_DEFAULT 0x00000000 +#define ixVPFMT_DEBUG10_DEFAULT 0x00000000 +#define ixVPFMT_DEBUG11_DEFAULT 0x00000000 + + +// addressBlock: vpopp_pipe0_vpopppipedebugind +#define ixVPOPP_PIPE_DEBUG_ID_DEFAULT 0x00000000 +#define ixVPOPP_PIPE_DEBUG_0_DEFAULT 0x00000000 +#define ixVPOPP_PIPE_DEBUG_1_DEFAULT 0x00000000 +#define ixVPOPP_PIPE_DEBUG_2_DEFAULT 0x00000000 + + +// addressBlock: vpopp_top_vpopp_topdebugind +#define ixVPOPP_TOP_DEBUG_ID_DEFAULT 0x00000000 + +#endif diff --git a/src/amd/vpelib/src/chip/vpe10/inc/asic/bringup_vpe_6_1_0_offset.h b/src/amd/vpelib/src/chip/vpe10/inc/asic/bringup_vpe_6_1_0_offset.h new file mode 100644 index 00000000000..30fcfac7a5a --- /dev/null +++ b/src/amd/vpelib/src/chip/vpe10/inc/asic/bringup_vpe_6_1_0_offset.h @@ -0,0 +1,1663 @@ +// Headers from LSDp CL1744173 +#ifndef _vpe_6_1_0_OFFSET_HEADER +#define _vpe_6_1_0_OFFSET_HEADER + + + +// addressBlock: vpe_vpedec +// base address: 0x46000 +#define regVPEC_DEC_START 0x0000 +#define regVPEC_DEC_START_BASE_IDX 0 +#define regVPEC_UCODE_ADDR 0x0001 +#define regVPEC_UCODE_ADDR_BASE_IDX 0 +#define regVPEC_UCODE_DATA 0x0002 +#define regVPEC_UCODE_DATA_BASE_IDX 0 +#define regVPEC_F32_CNTL 0x0003 +#define regVPEC_F32_CNTL_BASE_IDX 0 +#define regVPEC_MMHUB_CNTL 0x0004 +#define regVPEC_MMHUB_CNTL_BASE_IDX 0 +#define regVPEC_MMHUB_TRUSTLVL 0x0005 +#define regVPEC_MMHUB_TRUSTLVL_BASE_IDX 0 +#define regVPEC_VPEP_CTRL 0x0010 +#define regVPEC_VPEP_CTRL_BASE_IDX 0 +#define regVPEC_CLK_CTRL 0x0011 +#define regVPEC_CLK_CTRL_BASE_IDX 0 +#define regVPEC_PG_CNTL 0x0012 +#define regVPEC_PG_CNTL_BASE_IDX 0 +#define regVPEC_POWER_CNTL 0x0013 +#define regVPEC_POWER_CNTL_BASE_IDX 0 +#define regVPEC_CNTL 0x0014 +#define regVPEC_CNTL_BASE_IDX 0 +#define regVPEC_CNTL1 0x0015 +#define regVPEC_CNTL1_BASE_IDX 0 +#define regVPEC_CNTL2 0x0016 +#define regVPEC_CNTL2_BASE_IDX 0 +#define regVPEC_GB_ADDR_CONFIG 0x0017 +#define regVPEC_GB_ADDR_CONFIG_BASE_IDX 0 +#define regVPEC_GB_ADDR_CONFIG_READ 0x0018 +#define regVPEC_GB_ADDR_CONFIG_READ_BASE_IDX 0 +#define regVPEC_PROCESS_QUANTUM0 0x0019 +#define regVPEC_PROCESS_QUANTUM0_BASE_IDX 0 +#define regVPEC_PROCESS_QUANTUM1 0x001a +#define regVPEC_PROCESS_QUANTUM1_BASE_IDX 0 +#define regVPEC_CONTEXT_SWITCH_THRESHOLD 0x001b +#define regVPEC_CONTEXT_SWITCH_THRESHOLD_BASE_IDX 0 +#define regVPEC_GLOBAL_QUANTUM 0x001c +#define regVPEC_GLOBAL_QUANTUM_BASE_IDX 0 +#define regVPEC_WATCHDOG_CNTL 0x001d +#define regVPEC_WATCHDOG_CNTL_BASE_IDX 0 +#define regVPEC_ATOMIC_CNTL 0x001e +#define regVPEC_ATOMIC_CNTL_BASE_IDX 0 +#define regVPEC_UCODE_VERSION 0x001f +#define regVPEC_UCODE_VERSION_BASE_IDX 0 +#define regVPEC_MEMREQ_BURST_CNTL 0x0020 +#define regVPEC_MEMREQ_BURST_CNTL_BASE_IDX 0 +#define regVPEC_TIMESTAMP_CNTL 0x0021 +#define regVPEC_TIMESTAMP_CNTL_BASE_IDX 0 +#define regVPEC_GLOBAL_TIMESTAMP_LO 0x0022 +#define regVPEC_GLOBAL_TIMESTAMP_LO_BASE_IDX 0 +#define regVPEC_GLOBAL_TIMESTAMP_HI 0x0023 +#define regVPEC_GLOBAL_TIMESTAMP_HI_BASE_IDX 0 +#define regVPEC_FREEZE 0x0024 +#define regVPEC_FREEZE_BASE_IDX 0 +#define regVPEC_CE_CTRL 0x0025 +#define regVPEC_CE_CTRL_BASE_IDX 0 +#define regVPEC_RELAX_ORDERING_LUT 0x0026 +#define regVPEC_RELAX_ORDERING_LUT_BASE_IDX 0 +#define regVPEC_CREDIT_CNTL 0x0027 +#define regVPEC_CREDIT_CNTL_BASE_IDX 0 +#define regVPEC_SCRATCH_RAM_DATA 0x0028 +#define regVPEC_SCRATCH_RAM_DATA_BASE_IDX 0 +#define regVPEC_SCRATCH_RAM_ADDR 0x0029 +#define regVPEC_SCRATCH_RAM_ADDR_BASE_IDX 0 +#define regVPEC_QUEUE_RESET_REQ 0x002a +#define regVPEC_QUEUE_RESET_REQ_BASE_IDX 0 +#define regVPEC_PERFCNT_PERFCOUNTER0_CFG 0x002b +#define regVPEC_PERFCNT_PERFCOUNTER0_CFG_BASE_IDX 0 +#define regVPEC_PERFCNT_PERFCOUNTER1_CFG 0x002c +#define regVPEC_PERFCNT_PERFCOUNTER1_CFG_BASE_IDX 0 +#define regVPEC_PERFCNT_PERFCOUNTER_RSLT_CNTL 0x002d +#define regVPEC_PERFCNT_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 +#define regVPEC_PERFCNT_MISC_CNTL 0x002e +#define regVPEC_PERFCNT_MISC_CNTL_BASE_IDX 0 +#define regVPEC_PERFCNT_PERFCOUNTER_LO 0x002f +#define regVPEC_PERFCNT_PERFCOUNTER_LO_BASE_IDX 0 +#define regVPEC_PERFCNT_PERFCOUNTER_HI 0x0030 +#define regVPEC_PERFCNT_PERFCOUNTER_HI_BASE_IDX 0 +#define regVPEC_DEBUG_INDEX 0x0031 +#define regVPEC_DEBUG_INDEX_BASE_IDX 0 +#define regVPEC_DEBUG_DATA 0x0032 +#define regVPEC_DEBUG_DATA_BASE_IDX 0 +#define regVPEC_CRC_CTRL 0x0033 +#define regVPEC_CRC_CTRL_BASE_IDX 0 +#define regVPEC_CRC_DATA 0x0034 +#define regVPEC_CRC_DATA_BASE_IDX 0 +#define regVPEC_PUB_DUMMY0 0x0035 +#define regVPEC_PUB_DUMMY0_BASE_IDX 0 +#define regVPEC_PUB_DUMMY1 0x0036 +#define regVPEC_PUB_DUMMY1_BASE_IDX 0 +#define regVPEC_PUB_DUMMY2 0x0037 +#define regVPEC_PUB_DUMMY2_BASE_IDX 0 +#define regVPEC_PUB_DUMMY3 0x0038 +#define regVPEC_PUB_DUMMY3_BASE_IDX 0 +#define regVPEC_PUB_DUMMY4 0x0039 +#define regVPEC_PUB_DUMMY4_BASE_IDX 0 +#define regVPEC_PUB_DUMMY5 0x003a +#define regVPEC_PUB_DUMMY5_BASE_IDX 0 +#define regVPEC_PUB_DUMMY6 0x003b +#define regVPEC_PUB_DUMMY6_BASE_IDX 0 +#define regVPEC_PUB_DUMMY7 0x003c +#define regVPEC_PUB_DUMMY7_BASE_IDX 0 +#define regVPEC_UCODE1_CHECKSUM 0x0040 +#define regVPEC_UCODE1_CHECKSUM_BASE_IDX 0 +#define regVPEC_VERSION 0x0041 +#define regVPEC_VERSION_BASE_IDX 0 +#define regVPEC_UCODE_CHECKSUM 0x0042 +#define regVPEC_UCODE_CHECKSUM_BASE_IDX 0 +#define regVPEC_CLOCK_GATING_STATUS 0x0043 +#define regVPEC_CLOCK_GATING_STATUS_BASE_IDX 0 +#define regVPEC_RB_RPTR_FETCH 0x0044 +#define regVPEC_RB_RPTR_FETCH_BASE_IDX 0 +#define regVPEC_RB_RPTR_FETCH_HI 0x0045 +#define regVPEC_RB_RPTR_FETCH_HI_BASE_IDX 0 +#define regVPEC_IB_OFFSET_FETCH 0x0046 +#define regVPEC_IB_OFFSET_FETCH_BASE_IDX 0 +#define regVPEC_CMDIB_OFFSET_FETCH 0x0047 +#define regVPEC_CMDIB_OFFSET_FETCH_BASE_IDX 0 +#define regVPEC_ATOMIC_PREOP_LO 0x0048 +#define regVPEC_ATOMIC_PREOP_LO_BASE_IDX 0 +#define regVPEC_ATOMIC_PREOP_HI 0x0049 +#define regVPEC_ATOMIC_PREOP_HI_BASE_IDX 0 +#define regVPEC_CE_BUSY 0x004a +#define regVPEC_CE_BUSY_BASE_IDX 0 +#define regVPEC_F32_COUNTER 0x004b +#define regVPEC_F32_COUNTER_BASE_IDX 0 +#define regVPEC_HOLE_ADDR_LO 0x004c +#define regVPEC_HOLE_ADDR_LO_BASE_IDX 0 +#define regVPEC_HOLE_ADDR_HI 0x004d +#define regVPEC_HOLE_ADDR_HI_BASE_IDX 0 +#define regVPEC_ERROR_LOG 0x004e +#define regVPEC_ERROR_LOG_BASE_IDX 0 +#define regVPEC_INT_STATUS 0x004f +#define regVPEC_INT_STATUS_BASE_IDX 0 +#define regVPEC_STATUS 0x0050 +#define regVPEC_STATUS_BASE_IDX 0 +#define regVPEC_STATUS1 0x0051 +#define regVPEC_STATUS1_BASE_IDX 0 +#define regVPEC_STATUS2 0x0052 +#define regVPEC_STATUS2_BASE_IDX 0 +#define regVPEC_STATUS3 0x0053 +#define regVPEC_STATUS3_BASE_IDX 0 +#define regVPEC_STATUS4 0x0054 +#define regVPEC_STATUS4_BASE_IDX 0 +#define regVPEC_STATUS5 0x0055 +#define regVPEC_STATUS5_BASE_IDX 0 +#define regVPEC_STATUS6 0x0056 +#define regVPEC_STATUS6_BASE_IDX 0 +#define regVPEC_STATUS7 0x0057 +#define regVPEC_STATUS7_BASE_IDX 0 +#define regVPEC_INST 0x0058 +#define regVPEC_INST_BASE_IDX 0 +#define regVPEC_QUEUE_STATUS0 0x0059 +#define regVPEC_QUEUE_STATUS0_BASE_IDX 0 +#define regVPEC_QUEUE_HANG_STATUS 0x005a +#define regVPEC_QUEUE_HANG_STATUS_BASE_IDX 0 +#define regVPEC_QUEUE0_RB_CNTL 0x0080 +#define regVPEC_QUEUE0_RB_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE0_SCHEDULE_CNTL 0x0081 +#define regVPEC_QUEUE0_SCHEDULE_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE0_RB_BASE 0x0082 +#define regVPEC_QUEUE0_RB_BASE_BASE_IDX 0 +#define regVPEC_QUEUE0_RB_BASE_HI 0x0083 +#define regVPEC_QUEUE0_RB_BASE_HI_BASE_IDX 0 +#define regVPEC_QUEUE0_RB_RPTR 0x0084 +#define regVPEC_QUEUE0_RB_RPTR_BASE_IDX 0 +#define regVPEC_QUEUE0_RB_RPTR_HI 0x0085 +#define regVPEC_QUEUE0_RB_RPTR_HI_BASE_IDX 0 +#define regVPEC_QUEUE0_RB_WPTR 0x0086 +#define regVPEC_QUEUE0_RB_WPTR_BASE_IDX 0 +#define regVPEC_QUEUE0_RB_WPTR_HI 0x0087 +#define regVPEC_QUEUE0_RB_WPTR_HI_BASE_IDX 0 +#define regVPEC_QUEUE0_RB_RPTR_ADDR_HI 0x0088 +#define regVPEC_QUEUE0_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regVPEC_QUEUE0_RB_RPTR_ADDR_LO 0x0089 +#define regVPEC_QUEUE0_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regVPEC_QUEUE0_RB_AQL_CNTL 0x008a +#define regVPEC_QUEUE0_RB_AQL_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE0_MINOR_PTR_UPDATE 0x008b +#define regVPEC_QUEUE0_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regVPEC_QUEUE0_CD_INFO 0x008c +#define regVPEC_QUEUE0_CD_INFO_BASE_IDX 0 +#define regVPEC_QUEUE0_RB_PREEMPT 0x008d +#define regVPEC_QUEUE0_RB_PREEMPT_BASE_IDX 0 +#define regVPEC_QUEUE0_SKIP_CNTL 0x008e +#define regVPEC_QUEUE0_SKIP_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE0_DOORBELL 0x008f +#define regVPEC_QUEUE0_DOORBELL_BASE_IDX 0 +#define regVPEC_QUEUE0_DOORBELL_OFFSET 0x0090 +#define regVPEC_QUEUE0_DOORBELL_OFFSET_BASE_IDX 0 +#define regVPEC_QUEUE0_DUMMY0 0x0091 +#define regVPEC_QUEUE0_DUMMY0_BASE_IDX 0 +#define regVPEC_QUEUE0_DUMMY1 0x0092 +#define regVPEC_QUEUE0_DUMMY1_BASE_IDX 0 +#define regVPEC_QUEUE0_DUMMY2 0x0093 +#define regVPEC_QUEUE0_DUMMY2_BASE_IDX 0 +#define regVPEC_QUEUE0_DUMMY3 0x0094 +#define regVPEC_QUEUE0_DUMMY3_BASE_IDX 0 +#define regVPEC_QUEUE0_DUMMY4 0x0095 +#define regVPEC_QUEUE0_DUMMY4_BASE_IDX 0 +#define regVPEC_QUEUE0_IB_CNTL 0x00ac +#define regVPEC_QUEUE0_IB_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE0_IB_RPTR 0x00ad +#define regVPEC_QUEUE0_IB_RPTR_BASE_IDX 0 +#define regVPEC_QUEUE0_IB_OFFSET 0x00ae +#define regVPEC_QUEUE0_IB_OFFSET_BASE_IDX 0 +#define regVPEC_QUEUE0_IB_BASE_LO 0x00af +#define regVPEC_QUEUE0_IB_BASE_LO_BASE_IDX 0 +#define regVPEC_QUEUE0_IB_BASE_HI 0x00b0 +#define regVPEC_QUEUE0_IB_BASE_HI_BASE_IDX 0 +#define regVPEC_QUEUE0_IB_SIZE 0x00b1 +#define regVPEC_QUEUE0_IB_SIZE_BASE_IDX 0 +#define regVPEC_QUEUE0_CMDIB_CNTL 0x00b2 +#define regVPEC_QUEUE0_CMDIB_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE0_CMDIB_RPTR 0x00b3 +#define regVPEC_QUEUE0_CMDIB_RPTR_BASE_IDX 0 +#define regVPEC_QUEUE0_CMDIB_OFFSET 0x00b4 +#define regVPEC_QUEUE0_CMDIB_OFFSET_BASE_IDX 0 +#define regVPEC_QUEUE0_CMDIB_BASE_LO 0x00b5 +#define regVPEC_QUEUE0_CMDIB_BASE_LO_BASE_IDX 0 +#define regVPEC_QUEUE0_CMDIB_BASE_HI 0x00b6 +#define regVPEC_QUEUE0_CMDIB_BASE_HI_BASE_IDX 0 +#define regVPEC_QUEUE0_CMDIB_SIZE 0x00b7 +#define regVPEC_QUEUE0_CMDIB_SIZE_BASE_IDX 0 +#define regVPEC_QUEUE0_CSA_ADDR_LO 0x00b8 +#define regVPEC_QUEUE0_CSA_ADDR_LO_BASE_IDX 0 +#define regVPEC_QUEUE0_CSA_ADDR_HI 0x00b9 +#define regVPEC_QUEUE0_CSA_ADDR_HI_BASE_IDX 0 +#define regVPEC_QUEUE0_CONTEXT_STATUS 0x00ba +#define regVPEC_QUEUE0_CONTEXT_STATUS_BASE_IDX 0 +#define regVPEC_QUEUE0_DOORBELL_LOG 0x00bb +#define regVPEC_QUEUE0_DOORBELL_LOG_BASE_IDX 0 +#define regVPEC_QUEUE0_IB_SUB_REMAIN 0x00bc +#define regVPEC_QUEUE0_IB_SUB_REMAIN_BASE_IDX 0 +#define regVPEC_QUEUE0_PREEMPT 0x00bd +#define regVPEC_QUEUE0_PREEMPT_BASE_IDX 0 +#define regVPEC_QUEUE1_RB_CNTL 0x00d8 +#define regVPEC_QUEUE1_RB_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE1_SCHEDULE_CNTL 0x00d9 +#define regVPEC_QUEUE1_SCHEDULE_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE1_RB_BASE 0x00da +#define regVPEC_QUEUE1_RB_BASE_BASE_IDX 0 +#define regVPEC_QUEUE1_RB_BASE_HI 0x00db +#define regVPEC_QUEUE1_RB_BASE_HI_BASE_IDX 0 +#define regVPEC_QUEUE1_RB_RPTR 0x00dc +#define regVPEC_QUEUE1_RB_RPTR_BASE_IDX 0 +#define regVPEC_QUEUE1_RB_RPTR_HI 0x00dd +#define regVPEC_QUEUE1_RB_RPTR_HI_BASE_IDX 0 +#define regVPEC_QUEUE1_RB_WPTR 0x00de +#define regVPEC_QUEUE1_RB_WPTR_BASE_IDX 0 +#define regVPEC_QUEUE1_RB_WPTR_HI 0x00df +#define regVPEC_QUEUE1_RB_WPTR_HI_BASE_IDX 0 +#define regVPEC_QUEUE1_RB_RPTR_ADDR_HI 0x00e0 +#define regVPEC_QUEUE1_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regVPEC_QUEUE1_RB_RPTR_ADDR_LO 0x00e1 +#define regVPEC_QUEUE1_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regVPEC_QUEUE1_RB_AQL_CNTL 0x00e2 +#define regVPEC_QUEUE1_RB_AQL_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE1_MINOR_PTR_UPDATE 0x00e3 +#define regVPEC_QUEUE1_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regVPEC_QUEUE1_CD_INFO 0x00e4 +#define regVPEC_QUEUE1_CD_INFO_BASE_IDX 0 +#define regVPEC_QUEUE1_RB_PREEMPT 0x00e5 +#define regVPEC_QUEUE1_RB_PREEMPT_BASE_IDX 0 +#define regVPEC_QUEUE1_SKIP_CNTL 0x00e6 +#define regVPEC_QUEUE1_SKIP_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE1_DOORBELL 0x00e7 +#define regVPEC_QUEUE1_DOORBELL_BASE_IDX 0 +#define regVPEC_QUEUE1_DOORBELL_OFFSET 0x00e8 +#define regVPEC_QUEUE1_DOORBELL_OFFSET_BASE_IDX 0 +#define regVPEC_QUEUE1_DUMMY0 0x00e9 +#define regVPEC_QUEUE1_DUMMY0_BASE_IDX 0 +#define regVPEC_QUEUE1_DUMMY1 0x00ea +#define regVPEC_QUEUE1_DUMMY1_BASE_IDX 0 +#define regVPEC_QUEUE1_DUMMY2 0x00eb +#define regVPEC_QUEUE1_DUMMY2_BASE_IDX 0 +#define regVPEC_QUEUE1_DUMMY3 0x00ec +#define regVPEC_QUEUE1_DUMMY3_BASE_IDX 0 +#define regVPEC_QUEUE1_DUMMY4 0x00ed +#define regVPEC_QUEUE1_DUMMY4_BASE_IDX 0 +#define regVPEC_QUEUE1_IB_CNTL 0x0104 +#define regVPEC_QUEUE1_IB_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE1_IB_RPTR 0x0105 +#define regVPEC_QUEUE1_IB_RPTR_BASE_IDX 0 +#define regVPEC_QUEUE1_IB_OFFSET 0x0106 +#define regVPEC_QUEUE1_IB_OFFSET_BASE_IDX 0 +#define regVPEC_QUEUE1_IB_BASE_LO 0x0107 +#define regVPEC_QUEUE1_IB_BASE_LO_BASE_IDX 0 +#define regVPEC_QUEUE1_IB_BASE_HI 0x0108 +#define regVPEC_QUEUE1_IB_BASE_HI_BASE_IDX 0 +#define regVPEC_QUEUE1_IB_SIZE 0x0109 +#define regVPEC_QUEUE1_IB_SIZE_BASE_IDX 0 +#define regVPEC_QUEUE1_CMDIB_CNTL 0x010a +#define regVPEC_QUEUE1_CMDIB_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE1_CMDIB_RPTR 0x010b +#define regVPEC_QUEUE1_CMDIB_RPTR_BASE_IDX 0 +#define regVPEC_QUEUE1_CMDIB_OFFSET 0x010c +#define regVPEC_QUEUE1_CMDIB_OFFSET_BASE_IDX 0 +#define regVPEC_QUEUE1_CMDIB_BASE_LO 0x010d +#define regVPEC_QUEUE1_CMDIB_BASE_LO_BASE_IDX 0 +#define regVPEC_QUEUE1_CMDIB_BASE_HI 0x010e +#define regVPEC_QUEUE1_CMDIB_BASE_HI_BASE_IDX 0 +#define regVPEC_QUEUE1_CMDIB_SIZE 0x010f +#define regVPEC_QUEUE1_CMDIB_SIZE_BASE_IDX 0 +#define regVPEC_QUEUE1_CSA_ADDR_LO 0x0110 +#define regVPEC_QUEUE1_CSA_ADDR_LO_BASE_IDX 0 +#define regVPEC_QUEUE1_CSA_ADDR_HI 0x0111 +#define regVPEC_QUEUE1_CSA_ADDR_HI_BASE_IDX 0 +#define regVPEC_QUEUE1_CONTEXT_STATUS 0x0112 +#define regVPEC_QUEUE1_CONTEXT_STATUS_BASE_IDX 0 +#define regVPEC_QUEUE1_DOORBELL_LOG 0x0113 +#define regVPEC_QUEUE1_DOORBELL_LOG_BASE_IDX 0 +#define regVPEC_QUEUE1_IB_SUB_REMAIN 0x0114 +#define regVPEC_QUEUE1_IB_SUB_REMAIN_BASE_IDX 0 +#define regVPEC_QUEUE1_PREEMPT 0x0115 +#define regVPEC_QUEUE1_PREEMPT_BASE_IDX 0 +#define regVPEC_QUEUE2_RB_CNTL 0x0130 +#define regVPEC_QUEUE2_RB_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE2_SCHEDULE_CNTL 0x0131 +#define regVPEC_QUEUE2_SCHEDULE_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE2_RB_BASE 0x0132 +#define regVPEC_QUEUE2_RB_BASE_BASE_IDX 0 +#define regVPEC_QUEUE2_RB_BASE_HI 0x0133 +#define regVPEC_QUEUE2_RB_BASE_HI_BASE_IDX 0 +#define regVPEC_QUEUE2_RB_RPTR 0x0134 +#define regVPEC_QUEUE2_RB_RPTR_BASE_IDX 0 +#define regVPEC_QUEUE2_RB_RPTR_HI 0x0135 +#define regVPEC_QUEUE2_RB_RPTR_HI_BASE_IDX 0 +#define regVPEC_QUEUE2_RB_WPTR 0x0136 +#define regVPEC_QUEUE2_RB_WPTR_BASE_IDX 0 +#define regVPEC_QUEUE2_RB_WPTR_HI 0x0137 +#define regVPEC_QUEUE2_RB_WPTR_HI_BASE_IDX 0 +#define regVPEC_QUEUE2_RB_RPTR_ADDR_HI 0x0138 +#define regVPEC_QUEUE2_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regVPEC_QUEUE2_RB_RPTR_ADDR_LO 0x0139 +#define regVPEC_QUEUE2_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regVPEC_QUEUE2_RB_AQL_CNTL 0x013a +#define regVPEC_QUEUE2_RB_AQL_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE2_MINOR_PTR_UPDATE 0x013b +#define regVPEC_QUEUE2_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regVPEC_QUEUE2_CD_INFO 0x013c +#define regVPEC_QUEUE2_CD_INFO_BASE_IDX 0 +#define regVPEC_QUEUE2_RB_PREEMPT 0x013d +#define regVPEC_QUEUE2_RB_PREEMPT_BASE_IDX 0 +#define regVPEC_QUEUE2_SKIP_CNTL 0x013e +#define regVPEC_QUEUE2_SKIP_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE2_DOORBELL 0x013f +#define regVPEC_QUEUE2_DOORBELL_BASE_IDX 0 +#define regVPEC_QUEUE2_DOORBELL_OFFSET 0x0140 +#define regVPEC_QUEUE2_DOORBELL_OFFSET_BASE_IDX 0 +#define regVPEC_QUEUE2_DUMMY0 0x0141 +#define regVPEC_QUEUE2_DUMMY0_BASE_IDX 0 +#define regVPEC_QUEUE2_DUMMY1 0x0142 +#define regVPEC_QUEUE2_DUMMY1_BASE_IDX 0 +#define regVPEC_QUEUE2_DUMMY2 0x0143 +#define regVPEC_QUEUE2_DUMMY2_BASE_IDX 0 +#define regVPEC_QUEUE2_DUMMY3 0x0144 +#define regVPEC_QUEUE2_DUMMY3_BASE_IDX 0 +#define regVPEC_QUEUE2_DUMMY4 0x0145 +#define regVPEC_QUEUE2_DUMMY4_BASE_IDX 0 +#define regVPEC_QUEUE2_IB_CNTL 0x015c +#define regVPEC_QUEUE2_IB_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE2_IB_RPTR 0x015d +#define regVPEC_QUEUE2_IB_RPTR_BASE_IDX 0 +#define regVPEC_QUEUE2_IB_OFFSET 0x015e +#define regVPEC_QUEUE2_IB_OFFSET_BASE_IDX 0 +#define regVPEC_QUEUE2_IB_BASE_LO 0x015f +#define regVPEC_QUEUE2_IB_BASE_LO_BASE_IDX 0 +#define regVPEC_QUEUE2_IB_BASE_HI 0x0160 +#define regVPEC_QUEUE2_IB_BASE_HI_BASE_IDX 0 +#define regVPEC_QUEUE2_IB_SIZE 0x0161 +#define regVPEC_QUEUE2_IB_SIZE_BASE_IDX 0 +#define regVPEC_QUEUE2_CMDIB_CNTL 0x0162 +#define regVPEC_QUEUE2_CMDIB_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE2_CMDIB_RPTR 0x0163 +#define regVPEC_QUEUE2_CMDIB_RPTR_BASE_IDX 0 +#define regVPEC_QUEUE2_CMDIB_OFFSET 0x0164 +#define regVPEC_QUEUE2_CMDIB_OFFSET_BASE_IDX 0 +#define regVPEC_QUEUE2_CMDIB_BASE_LO 0x0165 +#define regVPEC_QUEUE2_CMDIB_BASE_LO_BASE_IDX 0 +#define regVPEC_QUEUE2_CMDIB_BASE_HI 0x0166 +#define regVPEC_QUEUE2_CMDIB_BASE_HI_BASE_IDX 0 +#define regVPEC_QUEUE2_CMDIB_SIZE 0x0167 +#define regVPEC_QUEUE2_CMDIB_SIZE_BASE_IDX 0 +#define regVPEC_QUEUE2_CSA_ADDR_LO 0x0168 +#define regVPEC_QUEUE2_CSA_ADDR_LO_BASE_IDX 0 +#define regVPEC_QUEUE2_CSA_ADDR_HI 0x0169 +#define regVPEC_QUEUE2_CSA_ADDR_HI_BASE_IDX 0 +#define regVPEC_QUEUE2_CONTEXT_STATUS 0x016a +#define regVPEC_QUEUE2_CONTEXT_STATUS_BASE_IDX 0 +#define regVPEC_QUEUE2_DOORBELL_LOG 0x016b +#define regVPEC_QUEUE2_DOORBELL_LOG_BASE_IDX 0 +#define regVPEC_QUEUE2_IB_SUB_REMAIN 0x016c +#define regVPEC_QUEUE2_IB_SUB_REMAIN_BASE_IDX 0 +#define regVPEC_QUEUE2_PREEMPT 0x016d +#define regVPEC_QUEUE2_PREEMPT_BASE_IDX 0 +#define regVPEC_QUEUE3_RB_CNTL 0x0188 +#define regVPEC_QUEUE3_RB_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE3_SCHEDULE_CNTL 0x0189 +#define regVPEC_QUEUE3_SCHEDULE_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE3_RB_BASE 0x018a +#define regVPEC_QUEUE3_RB_BASE_BASE_IDX 0 +#define regVPEC_QUEUE3_RB_BASE_HI 0x018b +#define regVPEC_QUEUE3_RB_BASE_HI_BASE_IDX 0 +#define regVPEC_QUEUE3_RB_RPTR 0x018c +#define regVPEC_QUEUE3_RB_RPTR_BASE_IDX 0 +#define regVPEC_QUEUE3_RB_RPTR_HI 0x018d +#define regVPEC_QUEUE3_RB_RPTR_HI_BASE_IDX 0 +#define regVPEC_QUEUE3_RB_WPTR 0x018e +#define regVPEC_QUEUE3_RB_WPTR_BASE_IDX 0 +#define regVPEC_QUEUE3_RB_WPTR_HI 0x018f +#define regVPEC_QUEUE3_RB_WPTR_HI_BASE_IDX 0 +#define regVPEC_QUEUE3_RB_RPTR_ADDR_HI 0x0190 +#define regVPEC_QUEUE3_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regVPEC_QUEUE3_RB_RPTR_ADDR_LO 0x0191 +#define regVPEC_QUEUE3_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regVPEC_QUEUE3_RB_AQL_CNTL 0x0192 +#define regVPEC_QUEUE3_RB_AQL_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE3_MINOR_PTR_UPDATE 0x0193 +#define regVPEC_QUEUE3_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regVPEC_QUEUE3_CD_INFO 0x0194 +#define regVPEC_QUEUE3_CD_INFO_BASE_IDX 0 +#define regVPEC_QUEUE3_RB_PREEMPT 0x0195 +#define regVPEC_QUEUE3_RB_PREEMPT_BASE_IDX 0 +#define regVPEC_QUEUE3_SKIP_CNTL 0x0196 +#define regVPEC_QUEUE3_SKIP_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE3_DOORBELL 0x0197 +#define regVPEC_QUEUE3_DOORBELL_BASE_IDX 0 +#define regVPEC_QUEUE3_DOORBELL_OFFSET 0x0198 +#define regVPEC_QUEUE3_DOORBELL_OFFSET_BASE_IDX 0 +#define regVPEC_QUEUE3_DUMMY0 0x0199 +#define regVPEC_QUEUE3_DUMMY0_BASE_IDX 0 +#define regVPEC_QUEUE3_DUMMY1 0x019a +#define regVPEC_QUEUE3_DUMMY1_BASE_IDX 0 +#define regVPEC_QUEUE3_DUMMY2 0x019b +#define regVPEC_QUEUE3_DUMMY2_BASE_IDX 0 +#define regVPEC_QUEUE3_DUMMY3 0x019c +#define regVPEC_QUEUE3_DUMMY3_BASE_IDX 0 +#define regVPEC_QUEUE3_DUMMY4 0x019d +#define regVPEC_QUEUE3_DUMMY4_BASE_IDX 0 +#define regVPEC_QUEUE3_IB_CNTL 0x01b4 +#define regVPEC_QUEUE3_IB_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE3_IB_RPTR 0x01b5 +#define regVPEC_QUEUE3_IB_RPTR_BASE_IDX 0 +#define regVPEC_QUEUE3_IB_OFFSET 0x01b6 +#define regVPEC_QUEUE3_IB_OFFSET_BASE_IDX 0 +#define regVPEC_QUEUE3_IB_BASE_LO 0x01b7 +#define regVPEC_QUEUE3_IB_BASE_LO_BASE_IDX 0 +#define regVPEC_QUEUE3_IB_BASE_HI 0x01b8 +#define regVPEC_QUEUE3_IB_BASE_HI_BASE_IDX 0 +#define regVPEC_QUEUE3_IB_SIZE 0x01b9 +#define regVPEC_QUEUE3_IB_SIZE_BASE_IDX 0 +#define regVPEC_QUEUE3_CMDIB_CNTL 0x01ba +#define regVPEC_QUEUE3_CMDIB_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE3_CMDIB_RPTR 0x01bb +#define regVPEC_QUEUE3_CMDIB_RPTR_BASE_IDX 0 +#define regVPEC_QUEUE3_CMDIB_OFFSET 0x01bc +#define regVPEC_QUEUE3_CMDIB_OFFSET_BASE_IDX 0 +#define regVPEC_QUEUE3_CMDIB_BASE_LO 0x01bd +#define regVPEC_QUEUE3_CMDIB_BASE_LO_BASE_IDX 0 +#define regVPEC_QUEUE3_CMDIB_BASE_HI 0x01be +#define regVPEC_QUEUE3_CMDIB_BASE_HI_BASE_IDX 0 +#define regVPEC_QUEUE3_CMDIB_SIZE 0x01bf +#define regVPEC_QUEUE3_CMDIB_SIZE_BASE_IDX 0 +#define regVPEC_QUEUE3_CSA_ADDR_LO 0x01c0 +#define regVPEC_QUEUE3_CSA_ADDR_LO_BASE_IDX 0 +#define regVPEC_QUEUE3_CSA_ADDR_HI 0x01c1 +#define regVPEC_QUEUE3_CSA_ADDR_HI_BASE_IDX 0 +#define regVPEC_QUEUE3_CONTEXT_STATUS 0x01c2 +#define regVPEC_QUEUE3_CONTEXT_STATUS_BASE_IDX 0 +#define regVPEC_QUEUE3_DOORBELL_LOG 0x01c3 +#define regVPEC_QUEUE3_DOORBELL_LOG_BASE_IDX 0 +#define regVPEC_QUEUE3_IB_SUB_REMAIN 0x01c4 +#define regVPEC_QUEUE3_IB_SUB_REMAIN_BASE_IDX 0 +#define regVPEC_QUEUE3_PREEMPT 0x01c5 +#define regVPEC_QUEUE3_PREEMPT_BASE_IDX 0 +#define regVPEC_QUEUE4_RB_CNTL 0x01e0 +#define regVPEC_QUEUE4_RB_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE4_SCHEDULE_CNTL 0x01e1 +#define regVPEC_QUEUE4_SCHEDULE_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE4_RB_BASE 0x01e2 +#define regVPEC_QUEUE4_RB_BASE_BASE_IDX 0 +#define regVPEC_QUEUE4_RB_BASE_HI 0x01e3 +#define regVPEC_QUEUE4_RB_BASE_HI_BASE_IDX 0 +#define regVPEC_QUEUE4_RB_RPTR 0x01e4 +#define regVPEC_QUEUE4_RB_RPTR_BASE_IDX 0 +#define regVPEC_QUEUE4_RB_RPTR_HI 0x01e5 +#define regVPEC_QUEUE4_RB_RPTR_HI_BASE_IDX 0 +#define regVPEC_QUEUE4_RB_WPTR 0x01e6 +#define regVPEC_QUEUE4_RB_WPTR_BASE_IDX 0 +#define regVPEC_QUEUE4_RB_WPTR_HI 0x01e7 +#define regVPEC_QUEUE4_RB_WPTR_HI_BASE_IDX 0 +#define regVPEC_QUEUE4_RB_RPTR_ADDR_HI 0x01e8 +#define regVPEC_QUEUE4_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regVPEC_QUEUE4_RB_RPTR_ADDR_LO 0x01e9 +#define regVPEC_QUEUE4_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regVPEC_QUEUE4_RB_AQL_CNTL 0x01ea +#define regVPEC_QUEUE4_RB_AQL_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE4_MINOR_PTR_UPDATE 0x01eb +#define regVPEC_QUEUE4_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regVPEC_QUEUE4_CD_INFO 0x01ec +#define regVPEC_QUEUE4_CD_INFO_BASE_IDX 0 +#define regVPEC_QUEUE4_RB_PREEMPT 0x01ed +#define regVPEC_QUEUE4_RB_PREEMPT_BASE_IDX 0 +#define regVPEC_QUEUE4_SKIP_CNTL 0x01ee +#define regVPEC_QUEUE4_SKIP_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE4_DOORBELL 0x01ef +#define regVPEC_QUEUE4_DOORBELL_BASE_IDX 0 +#define regVPEC_QUEUE4_DOORBELL_OFFSET 0x01f0 +#define regVPEC_QUEUE4_DOORBELL_OFFSET_BASE_IDX 0 +#define regVPEC_QUEUE4_DUMMY0 0x01f1 +#define regVPEC_QUEUE4_DUMMY0_BASE_IDX 0 +#define regVPEC_QUEUE4_DUMMY1 0x01f2 +#define regVPEC_QUEUE4_DUMMY1_BASE_IDX 0 +#define regVPEC_QUEUE4_DUMMY2 0x01f3 +#define regVPEC_QUEUE4_DUMMY2_BASE_IDX 0 +#define regVPEC_QUEUE4_DUMMY3 0x01f4 +#define regVPEC_QUEUE4_DUMMY3_BASE_IDX 0 +#define regVPEC_QUEUE4_DUMMY4 0x01f5 +#define regVPEC_QUEUE4_DUMMY4_BASE_IDX 0 +#define regVPEC_QUEUE4_IB_CNTL 0x020c +#define regVPEC_QUEUE4_IB_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE4_IB_RPTR 0x020d +#define regVPEC_QUEUE4_IB_RPTR_BASE_IDX 0 +#define regVPEC_QUEUE4_IB_OFFSET 0x020e +#define regVPEC_QUEUE4_IB_OFFSET_BASE_IDX 0 +#define regVPEC_QUEUE4_IB_BASE_LO 0x020f +#define regVPEC_QUEUE4_IB_BASE_LO_BASE_IDX 0 +#define regVPEC_QUEUE4_IB_BASE_HI 0x0210 +#define regVPEC_QUEUE4_IB_BASE_HI_BASE_IDX 0 +#define regVPEC_QUEUE4_IB_SIZE 0x0211 +#define regVPEC_QUEUE4_IB_SIZE_BASE_IDX 0 +#define regVPEC_QUEUE4_CMDIB_CNTL 0x0212 +#define regVPEC_QUEUE4_CMDIB_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE4_CMDIB_RPTR 0x0213 +#define regVPEC_QUEUE4_CMDIB_RPTR_BASE_IDX 0 +#define regVPEC_QUEUE4_CMDIB_OFFSET 0x0214 +#define regVPEC_QUEUE4_CMDIB_OFFSET_BASE_IDX 0 +#define regVPEC_QUEUE4_CMDIB_BASE_LO 0x0215 +#define regVPEC_QUEUE4_CMDIB_BASE_LO_BASE_IDX 0 +#define regVPEC_QUEUE4_CMDIB_BASE_HI 0x0216 +#define regVPEC_QUEUE4_CMDIB_BASE_HI_BASE_IDX 0 +#define regVPEC_QUEUE4_CMDIB_SIZE 0x0217 +#define regVPEC_QUEUE4_CMDIB_SIZE_BASE_IDX 0 +#define regVPEC_QUEUE4_CSA_ADDR_LO 0x0218 +#define regVPEC_QUEUE4_CSA_ADDR_LO_BASE_IDX 0 +#define regVPEC_QUEUE4_CSA_ADDR_HI 0x0219 +#define regVPEC_QUEUE4_CSA_ADDR_HI_BASE_IDX 0 +#define regVPEC_QUEUE4_CONTEXT_STATUS 0x021a +#define regVPEC_QUEUE4_CONTEXT_STATUS_BASE_IDX 0 +#define regVPEC_QUEUE4_DOORBELL_LOG 0x021b +#define regVPEC_QUEUE4_DOORBELL_LOG_BASE_IDX 0 +#define regVPEC_QUEUE4_IB_SUB_REMAIN 0x021c +#define regVPEC_QUEUE4_IB_SUB_REMAIN_BASE_IDX 0 +#define regVPEC_QUEUE4_PREEMPT 0x021d +#define regVPEC_QUEUE4_PREEMPT_BASE_IDX 0 +#define regVPEC_QUEUE5_RB_CNTL 0x0238 +#define regVPEC_QUEUE5_RB_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE5_SCHEDULE_CNTL 0x0239 +#define regVPEC_QUEUE5_SCHEDULE_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE5_RB_BASE 0x023a +#define regVPEC_QUEUE5_RB_BASE_BASE_IDX 0 +#define regVPEC_QUEUE5_RB_BASE_HI 0x023b +#define regVPEC_QUEUE5_RB_BASE_HI_BASE_IDX 0 +#define regVPEC_QUEUE5_RB_RPTR 0x023c +#define regVPEC_QUEUE5_RB_RPTR_BASE_IDX 0 +#define regVPEC_QUEUE5_RB_RPTR_HI 0x023d +#define regVPEC_QUEUE5_RB_RPTR_HI_BASE_IDX 0 +#define regVPEC_QUEUE5_RB_WPTR 0x023e +#define regVPEC_QUEUE5_RB_WPTR_BASE_IDX 0 +#define regVPEC_QUEUE5_RB_WPTR_HI 0x023f +#define regVPEC_QUEUE5_RB_WPTR_HI_BASE_IDX 0 +#define regVPEC_QUEUE5_RB_RPTR_ADDR_HI 0x0240 +#define regVPEC_QUEUE5_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regVPEC_QUEUE5_RB_RPTR_ADDR_LO 0x0241 +#define regVPEC_QUEUE5_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regVPEC_QUEUE5_RB_AQL_CNTL 0x0242 +#define regVPEC_QUEUE5_RB_AQL_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE5_MINOR_PTR_UPDATE 0x0243 +#define regVPEC_QUEUE5_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regVPEC_QUEUE5_CD_INFO 0x0244 +#define regVPEC_QUEUE5_CD_INFO_BASE_IDX 0 +#define regVPEC_QUEUE5_RB_PREEMPT 0x0245 +#define regVPEC_QUEUE5_RB_PREEMPT_BASE_IDX 0 +#define regVPEC_QUEUE5_SKIP_CNTL 0x0246 +#define regVPEC_QUEUE5_SKIP_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE5_DOORBELL 0x0247 +#define regVPEC_QUEUE5_DOORBELL_BASE_IDX 0 +#define regVPEC_QUEUE5_DOORBELL_OFFSET 0x0248 +#define regVPEC_QUEUE5_DOORBELL_OFFSET_BASE_IDX 0 +#define regVPEC_QUEUE5_DUMMY0 0x0249 +#define regVPEC_QUEUE5_DUMMY0_BASE_IDX 0 +#define regVPEC_QUEUE5_DUMMY1 0x024a +#define regVPEC_QUEUE5_DUMMY1_BASE_IDX 0 +#define regVPEC_QUEUE5_DUMMY2 0x024b +#define regVPEC_QUEUE5_DUMMY2_BASE_IDX 0 +#define regVPEC_QUEUE5_DUMMY3 0x024c +#define regVPEC_QUEUE5_DUMMY3_BASE_IDX 0 +#define regVPEC_QUEUE5_DUMMY4 0x024d +#define regVPEC_QUEUE5_DUMMY4_BASE_IDX 0 +#define regVPEC_QUEUE5_IB_CNTL 0x0264 +#define regVPEC_QUEUE5_IB_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE5_IB_RPTR 0x0265 +#define regVPEC_QUEUE5_IB_RPTR_BASE_IDX 0 +#define regVPEC_QUEUE5_IB_OFFSET 0x0266 +#define regVPEC_QUEUE5_IB_OFFSET_BASE_IDX 0 +#define regVPEC_QUEUE5_IB_BASE_LO 0x0267 +#define regVPEC_QUEUE5_IB_BASE_LO_BASE_IDX 0 +#define regVPEC_QUEUE5_IB_BASE_HI 0x0268 +#define regVPEC_QUEUE5_IB_BASE_HI_BASE_IDX 0 +#define regVPEC_QUEUE5_IB_SIZE 0x0269 +#define regVPEC_QUEUE5_IB_SIZE_BASE_IDX 0 +#define regVPEC_QUEUE5_CMDIB_CNTL 0x026a +#define regVPEC_QUEUE5_CMDIB_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE5_CMDIB_RPTR 0x026b +#define regVPEC_QUEUE5_CMDIB_RPTR_BASE_IDX 0 +#define regVPEC_QUEUE5_CMDIB_OFFSET 0x026c +#define regVPEC_QUEUE5_CMDIB_OFFSET_BASE_IDX 0 +#define regVPEC_QUEUE5_CMDIB_BASE_LO 0x026d +#define regVPEC_QUEUE5_CMDIB_BASE_LO_BASE_IDX 0 +#define regVPEC_QUEUE5_CMDIB_BASE_HI 0x026e +#define regVPEC_QUEUE5_CMDIB_BASE_HI_BASE_IDX 0 +#define regVPEC_QUEUE5_CMDIB_SIZE 0x026f +#define regVPEC_QUEUE5_CMDIB_SIZE_BASE_IDX 0 +#define regVPEC_QUEUE5_CSA_ADDR_LO 0x0270 +#define regVPEC_QUEUE5_CSA_ADDR_LO_BASE_IDX 0 +#define regVPEC_QUEUE5_CSA_ADDR_HI 0x0271 +#define regVPEC_QUEUE5_CSA_ADDR_HI_BASE_IDX 0 +#define regVPEC_QUEUE5_CONTEXT_STATUS 0x0272 +#define regVPEC_QUEUE5_CONTEXT_STATUS_BASE_IDX 0 +#define regVPEC_QUEUE5_DOORBELL_LOG 0x0273 +#define regVPEC_QUEUE5_DOORBELL_LOG_BASE_IDX 0 +#define regVPEC_QUEUE5_IB_SUB_REMAIN 0x0274 +#define regVPEC_QUEUE5_IB_SUB_REMAIN_BASE_IDX 0 +#define regVPEC_QUEUE5_PREEMPT 0x0275 +#define regVPEC_QUEUE5_PREEMPT_BASE_IDX 0 +#define regVPEC_QUEUE6_RB_CNTL 0x0290 +#define regVPEC_QUEUE6_RB_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE6_SCHEDULE_CNTL 0x0291 +#define regVPEC_QUEUE6_SCHEDULE_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE6_RB_BASE 0x0292 +#define regVPEC_QUEUE6_RB_BASE_BASE_IDX 0 +#define regVPEC_QUEUE6_RB_BASE_HI 0x0293 +#define regVPEC_QUEUE6_RB_BASE_HI_BASE_IDX 0 +#define regVPEC_QUEUE6_RB_RPTR 0x0294 +#define regVPEC_QUEUE6_RB_RPTR_BASE_IDX 0 +#define regVPEC_QUEUE6_RB_RPTR_HI 0x0295 +#define regVPEC_QUEUE6_RB_RPTR_HI_BASE_IDX 0 +#define regVPEC_QUEUE6_RB_WPTR 0x0296 +#define regVPEC_QUEUE6_RB_WPTR_BASE_IDX 0 +#define regVPEC_QUEUE6_RB_WPTR_HI 0x0297 +#define regVPEC_QUEUE6_RB_WPTR_HI_BASE_IDX 0 +#define regVPEC_QUEUE6_RB_RPTR_ADDR_HI 0x0298 +#define regVPEC_QUEUE6_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regVPEC_QUEUE6_RB_RPTR_ADDR_LO 0x0299 +#define regVPEC_QUEUE6_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regVPEC_QUEUE6_RB_AQL_CNTL 0x029a +#define regVPEC_QUEUE6_RB_AQL_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE6_MINOR_PTR_UPDATE 0x029b +#define regVPEC_QUEUE6_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regVPEC_QUEUE6_CD_INFO 0x029c +#define regVPEC_QUEUE6_CD_INFO_BASE_IDX 0 +#define regVPEC_QUEUE6_RB_PREEMPT 0x029d +#define regVPEC_QUEUE6_RB_PREEMPT_BASE_IDX 0 +#define regVPEC_QUEUE6_SKIP_CNTL 0x029e +#define regVPEC_QUEUE6_SKIP_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE6_DOORBELL 0x029f +#define regVPEC_QUEUE6_DOORBELL_BASE_IDX 0 +#define regVPEC_QUEUE6_DOORBELL_OFFSET 0x02a0 +#define regVPEC_QUEUE6_DOORBELL_OFFSET_BASE_IDX 0 +#define regVPEC_QUEUE6_DUMMY0 0x02a1 +#define regVPEC_QUEUE6_DUMMY0_BASE_IDX 0 +#define regVPEC_QUEUE6_DUMMY1 0x02a2 +#define regVPEC_QUEUE6_DUMMY1_BASE_IDX 0 +#define regVPEC_QUEUE6_DUMMY2 0x02a3 +#define regVPEC_QUEUE6_DUMMY2_BASE_IDX 0 +#define regVPEC_QUEUE6_DUMMY3 0x02a4 +#define regVPEC_QUEUE6_DUMMY3_BASE_IDX 0 +#define regVPEC_QUEUE6_DUMMY4 0x02a5 +#define regVPEC_QUEUE6_DUMMY4_BASE_IDX 0 +#define regVPEC_QUEUE6_IB_CNTL 0x02bc +#define regVPEC_QUEUE6_IB_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE6_IB_RPTR 0x02bd +#define regVPEC_QUEUE6_IB_RPTR_BASE_IDX 0 +#define regVPEC_QUEUE6_IB_OFFSET 0x02be +#define regVPEC_QUEUE6_IB_OFFSET_BASE_IDX 0 +#define regVPEC_QUEUE6_IB_BASE_LO 0x02bf +#define regVPEC_QUEUE6_IB_BASE_LO_BASE_IDX 0 +#define regVPEC_QUEUE6_IB_BASE_HI 0x02c0 +#define regVPEC_QUEUE6_IB_BASE_HI_BASE_IDX 0 +#define regVPEC_QUEUE6_IB_SIZE 0x02c1 +#define regVPEC_QUEUE6_IB_SIZE_BASE_IDX 0 +#define regVPEC_QUEUE6_CMDIB_CNTL 0x02c2 +#define regVPEC_QUEUE6_CMDIB_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE6_CMDIB_RPTR 0x02c3 +#define regVPEC_QUEUE6_CMDIB_RPTR_BASE_IDX 0 +#define regVPEC_QUEUE6_CMDIB_OFFSET 0x02c4 +#define regVPEC_QUEUE6_CMDIB_OFFSET_BASE_IDX 0 +#define regVPEC_QUEUE6_CMDIB_BASE_LO 0x02c5 +#define regVPEC_QUEUE6_CMDIB_BASE_LO_BASE_IDX 0 +#define regVPEC_QUEUE6_CMDIB_BASE_HI 0x02c6 +#define regVPEC_QUEUE6_CMDIB_BASE_HI_BASE_IDX 0 +#define regVPEC_QUEUE6_CMDIB_SIZE 0x02c7 +#define regVPEC_QUEUE6_CMDIB_SIZE_BASE_IDX 0 +#define regVPEC_QUEUE6_CSA_ADDR_LO 0x02c8 +#define regVPEC_QUEUE6_CSA_ADDR_LO_BASE_IDX 0 +#define regVPEC_QUEUE6_CSA_ADDR_HI 0x02c9 +#define regVPEC_QUEUE6_CSA_ADDR_HI_BASE_IDX 0 +#define regVPEC_QUEUE6_CONTEXT_STATUS 0x02ca +#define regVPEC_QUEUE6_CONTEXT_STATUS_BASE_IDX 0 +#define regVPEC_QUEUE6_DOORBELL_LOG 0x02cb +#define regVPEC_QUEUE6_DOORBELL_LOG_BASE_IDX 0 +#define regVPEC_QUEUE6_IB_SUB_REMAIN 0x02cc +#define regVPEC_QUEUE6_IB_SUB_REMAIN_BASE_IDX 0 +#define regVPEC_QUEUE6_PREEMPT 0x02cd +#define regVPEC_QUEUE6_PREEMPT_BASE_IDX 0 +#define regVPEC_QUEUE7_RB_CNTL 0x02e8 +#define regVPEC_QUEUE7_RB_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE7_SCHEDULE_CNTL 0x02e9 +#define regVPEC_QUEUE7_SCHEDULE_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE7_RB_BASE 0x02ea +#define regVPEC_QUEUE7_RB_BASE_BASE_IDX 0 +#define regVPEC_QUEUE7_RB_BASE_HI 0x02eb +#define regVPEC_QUEUE7_RB_BASE_HI_BASE_IDX 0 +#define regVPEC_QUEUE7_RB_RPTR 0x02ec +#define regVPEC_QUEUE7_RB_RPTR_BASE_IDX 0 +#define regVPEC_QUEUE7_RB_RPTR_HI 0x02ed +#define regVPEC_QUEUE7_RB_RPTR_HI_BASE_IDX 0 +#define regVPEC_QUEUE7_RB_WPTR 0x02ee +#define regVPEC_QUEUE7_RB_WPTR_BASE_IDX 0 +#define regVPEC_QUEUE7_RB_WPTR_HI 0x02ef +#define regVPEC_QUEUE7_RB_WPTR_HI_BASE_IDX 0 +#define regVPEC_QUEUE7_RB_RPTR_ADDR_HI 0x02f0 +#define regVPEC_QUEUE7_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regVPEC_QUEUE7_RB_RPTR_ADDR_LO 0x02f1 +#define regVPEC_QUEUE7_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regVPEC_QUEUE7_RB_AQL_CNTL 0x02f2 +#define regVPEC_QUEUE7_RB_AQL_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE7_MINOR_PTR_UPDATE 0x02f3 +#define regVPEC_QUEUE7_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regVPEC_QUEUE7_CD_INFO 0x02f4 +#define regVPEC_QUEUE7_CD_INFO_BASE_IDX 0 +#define regVPEC_QUEUE7_RB_PREEMPT 0x02f5 +#define regVPEC_QUEUE7_RB_PREEMPT_BASE_IDX 0 +#define regVPEC_QUEUE7_SKIP_CNTL 0x02f6 +#define regVPEC_QUEUE7_SKIP_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE7_DOORBELL 0x02f7 +#define regVPEC_QUEUE7_DOORBELL_BASE_IDX 0 +#define regVPEC_QUEUE7_DOORBELL_OFFSET 0x02f8 +#define regVPEC_QUEUE7_DOORBELL_OFFSET_BASE_IDX 0 +#define regVPEC_QUEUE7_DUMMY0 0x02f9 +#define regVPEC_QUEUE7_DUMMY0_BASE_IDX 0 +#define regVPEC_QUEUE7_DUMMY1 0x02fa +#define regVPEC_QUEUE7_DUMMY1_BASE_IDX 0 +#define regVPEC_QUEUE7_DUMMY2 0x02fb +#define regVPEC_QUEUE7_DUMMY2_BASE_IDX 0 +#define regVPEC_QUEUE7_DUMMY3 0x02fc +#define regVPEC_QUEUE7_DUMMY3_BASE_IDX 0 +#define regVPEC_QUEUE7_DUMMY4 0x02fd +#define regVPEC_QUEUE7_DUMMY4_BASE_IDX 0 +#define regVPEC_QUEUE7_IB_CNTL 0x0314 +#define regVPEC_QUEUE7_IB_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE7_IB_RPTR 0x0315 +#define regVPEC_QUEUE7_IB_RPTR_BASE_IDX 0 +#define regVPEC_QUEUE7_IB_OFFSET 0x0316 +#define regVPEC_QUEUE7_IB_OFFSET_BASE_IDX 0 +#define regVPEC_QUEUE7_IB_BASE_LO 0x0317 +#define regVPEC_QUEUE7_IB_BASE_LO_BASE_IDX 0 +#define regVPEC_QUEUE7_IB_BASE_HI 0x0318 +#define regVPEC_QUEUE7_IB_BASE_HI_BASE_IDX 0 +#define regVPEC_QUEUE7_IB_SIZE 0x0319 +#define regVPEC_QUEUE7_IB_SIZE_BASE_IDX 0 +#define regVPEC_QUEUE7_CMDIB_CNTL 0x031a +#define regVPEC_QUEUE7_CMDIB_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE7_CMDIB_RPTR 0x031b +#define regVPEC_QUEUE7_CMDIB_RPTR_BASE_IDX 0 +#define regVPEC_QUEUE7_CMDIB_OFFSET 0x031c +#define regVPEC_QUEUE7_CMDIB_OFFSET_BASE_IDX 0 +#define regVPEC_QUEUE7_CMDIB_BASE_LO 0x031d +#define regVPEC_QUEUE7_CMDIB_BASE_LO_BASE_IDX 0 +#define regVPEC_QUEUE7_CMDIB_BASE_HI 0x031e +#define regVPEC_QUEUE7_CMDIB_BASE_HI_BASE_IDX 0 +#define regVPEC_QUEUE7_CMDIB_SIZE 0x031f +#define regVPEC_QUEUE7_CMDIB_SIZE_BASE_IDX 0 +#define regVPEC_QUEUE7_CSA_ADDR_LO 0x0320 +#define regVPEC_QUEUE7_CSA_ADDR_LO_BASE_IDX 0 +#define regVPEC_QUEUE7_CSA_ADDR_HI 0x0321 +#define regVPEC_QUEUE7_CSA_ADDR_HI_BASE_IDX 0 +#define regVPEC_QUEUE7_CONTEXT_STATUS 0x0322 +#define regVPEC_QUEUE7_CONTEXT_STATUS_BASE_IDX 0 +#define regVPEC_QUEUE7_DOORBELL_LOG 0x0323 +#define regVPEC_QUEUE7_DOORBELL_LOG_BASE_IDX 0 +#define regVPEC_QUEUE7_IB_SUB_REMAIN 0x0324 +#define regVPEC_QUEUE7_IB_SUB_REMAIN_BASE_IDX 0 +#define regVPEC_QUEUE7_PREEMPT 0x0325 +#define regVPEC_QUEUE7_PREEMPT_BASE_IDX 0 + + +// addressBlock: vpe_vpep_vpdpp0_dispdec_vpcnvc_cfg_dispdec +// base address: 0x0 +#define regVPCNVC_SURFACE_PIXEL_FORMAT 0x0744 +#define regVPCNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 0 +#define regVPCNVC_FORMAT_CONTROL 0x0745 +#define regVPCNVC_FORMAT_CONTROL_BASE_IDX 0 +#define regVPCNVC_FCNV_FP_BIAS_R 0x0746 +#define regVPCNVC_FCNV_FP_BIAS_R_BASE_IDX 0 +#define regVPCNVC_FCNV_FP_BIAS_G 0x0747 +#define regVPCNVC_FCNV_FP_BIAS_G_BASE_IDX 0 +#define regVPCNVC_FCNV_FP_BIAS_B 0x0748 +#define regVPCNVC_FCNV_FP_BIAS_B_BASE_IDX 0 +#define regVPCNVC_FCNV_FP_SCALE_R 0x0749 +#define regVPCNVC_FCNV_FP_SCALE_R_BASE_IDX 0 +#define regVPCNVC_FCNV_FP_SCALE_G 0x074a +#define regVPCNVC_FCNV_FP_SCALE_G_BASE_IDX 0 +#define regVPCNVC_FCNV_FP_SCALE_B 0x074b +#define regVPCNVC_FCNV_FP_SCALE_B_BASE_IDX 0 +#define regVPCNVC_COLOR_KEYER_CONTROL 0x074c +#define regVPCNVC_COLOR_KEYER_CONTROL_BASE_IDX 0 +#define regVPCNVC_COLOR_KEYER_ALPHA 0x074d +#define regVPCNVC_COLOR_KEYER_ALPHA_BASE_IDX 0 +#define regVPCNVC_COLOR_KEYER_RED 0x074e +#define regVPCNVC_COLOR_KEYER_RED_BASE_IDX 0 +#define regVPCNVC_COLOR_KEYER_GREEN 0x074f +#define regVPCNVC_COLOR_KEYER_GREEN_BASE_IDX 0 +#define regVPCNVC_COLOR_KEYER_BLUE 0x0750 +#define regVPCNVC_COLOR_KEYER_BLUE_BASE_IDX 0 +#define regVPCNVC_ALPHA_2BIT_LUT 0x0752 +#define regVPCNVC_ALPHA_2BIT_LUT_BASE_IDX 0 +#define regVPCNVC_PRE_DEALPHA 0x0753 +#define regVPCNVC_PRE_DEALPHA_BASE_IDX 0 +#define regVPCNVC_PRE_CSC_MODE 0x0754 +#define regVPCNVC_PRE_CSC_MODE_BASE_IDX 0 +#define regVPCNVC_PRE_CSC_C11_C12 0x0755 +#define regVPCNVC_PRE_CSC_C11_C12_BASE_IDX 0 +#define regVPCNVC_PRE_CSC_C13_C14 0x0756 +#define regVPCNVC_PRE_CSC_C13_C14_BASE_IDX 0 +#define regVPCNVC_PRE_CSC_C21_C22 0x0757 +#define regVPCNVC_PRE_CSC_C21_C22_BASE_IDX 0 +#define regVPCNVC_PRE_CSC_C23_C24 0x0758 +#define regVPCNVC_PRE_CSC_C23_C24_BASE_IDX 0 +#define regVPCNVC_PRE_CSC_C31_C32 0x0759 +#define regVPCNVC_PRE_CSC_C31_C32_BASE_IDX 0 +#define regVPCNVC_PRE_CSC_C33_C34 0x075a +#define regVPCNVC_PRE_CSC_C33_C34_BASE_IDX 0 +#define regVPCNVC_COEF_FORMAT 0x075b +#define regVPCNVC_COEF_FORMAT_BASE_IDX 0 +#define regVPCNVC_PRE_DEGAM 0x075c +#define regVPCNVC_PRE_DEGAM_BASE_IDX 0 +#define regVPCNVC_PRE_REALPHA 0x075d +#define regVPCNVC_PRE_REALPHA_BASE_IDX 0 +#define regVPCNVC_CFG_TEST_DEBUG_INDEX 0x075e +#define regVPCNVC_CFG_TEST_DEBUG_INDEX_BASE_IDX 0 +#define regVPCNVC_CFG_TEST_DEBUG_DATA 0x075f +#define regVPCNVC_CFG_TEST_DEBUG_DATA_BASE_IDX 0 + + +// addressBlock: vpe_vpep_vpdpp0_dispdec_vpdscl_dispdec +// base address: 0x0 +#define regVPDSCL_COEF_RAM_TAP_SELECT 0x0768 +#define regVPDSCL_COEF_RAM_TAP_SELECT_BASE_IDX 0 +#define regVPDSCL_COEF_RAM_TAP_DATA 0x0769 +#define regVPDSCL_COEF_RAM_TAP_DATA_BASE_IDX 0 +#define regVPDSCL_MODE 0x076a +#define regVPDSCL_MODE_BASE_IDX 0 +#define regVPDSCL_TAP_CONTROL 0x076b +#define regVPDSCL_TAP_CONTROL_BASE_IDX 0 +#define regVPDSCL_CONTROL 0x076c +#define regVPDSCL_CONTROL_BASE_IDX 0 +#define regVPDSCL_2TAP_CONTROL 0x076d +#define regVPDSCL_2TAP_CONTROL_BASE_IDX 0 +#define regVPDSCL_MANUAL_REPLICATE_CONTROL 0x076e +#define regVPDSCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 0 +#define regVPDSCL_HORZ_FILTER_SCALE_RATIO 0x076f +#define regVPDSCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 0 +#define regVPDSCL_HORZ_FILTER_INIT 0x0770 +#define regVPDSCL_HORZ_FILTER_INIT_BASE_IDX 0 +#define regVPDSCL_HORZ_FILTER_SCALE_RATIO_C 0x0771 +#define regVPDSCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 0 +#define regVPDSCL_HORZ_FILTER_INIT_C 0x0772 +#define regVPDSCL_HORZ_FILTER_INIT_C_BASE_IDX 0 +#define regVPDSCL_VERT_FILTER_SCALE_RATIO 0x0773 +#define regVPDSCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 0 +#define regVPDSCL_VERT_FILTER_INIT 0x0774 +#define regVPDSCL_VERT_FILTER_INIT_BASE_IDX 0 +#define regVPDSCL_VERT_FILTER_INIT_BOT 0x0775 +#define regVPDSCL_VERT_FILTER_INIT_BOT_BASE_IDX 0 +#define regVPDSCL_VERT_FILTER_SCALE_RATIO_C 0x0776 +#define regVPDSCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 0 +#define regVPDSCL_VERT_FILTER_INIT_C 0x0777 +#define regVPDSCL_VERT_FILTER_INIT_C_BASE_IDX 0 +#define regVPDSCL_VERT_FILTER_INIT_BOT_C 0x0778 +#define regVPDSCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 0 +#define regVPDSCL_BLACK_COLOR 0x0779 +#define regVPDSCL_BLACK_COLOR_BASE_IDX 0 +#define regVPDSCL_UPDATE 0x077a +#define regVPDSCL_UPDATE_BASE_IDX 0 +#define regVPDSCL_AUTOCAL 0x077b +#define regVPDSCL_AUTOCAL_BASE_IDX 0 +#define regVPDSCL_EXT_OVERSCAN_LEFT_RIGHT 0x077c +#define regVPDSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 0 +#define regVPDSCL_EXT_OVERSCAN_TOP_BOTTOM 0x077d +#define regVPDSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 0 +#define regVPOTG_H_BLANK 0x077e +#define regVPOTG_H_BLANK_BASE_IDX 0 +#define regVPOTG_V_BLANK 0x077f +#define regVPOTG_V_BLANK_BASE_IDX 0 +#define regVPDSCL_RECOUT_START 0x0780 +#define regVPDSCL_RECOUT_START_BASE_IDX 0 +#define regVPDSCL_RECOUT_SIZE 0x0781 +#define regVPDSCL_RECOUT_SIZE_BASE_IDX 0 +#define regVPMPC_SIZE 0x0782 +#define regVPMPC_SIZE_BASE_IDX 0 +#define regVPLB_DATA_FORMAT 0x0783 +#define regVPLB_DATA_FORMAT_BASE_IDX 0 +#define regVPLB_MEMORY_CTRL 0x0784 +#define regVPLB_MEMORY_CTRL_BASE_IDX 0 +#define regVPLB_V_COUNTER 0x0785 +#define regVPLB_V_COUNTER_BASE_IDX 0 +#define regVPDSCL_MEM_PWR_CTRL 0x0786 +#define regVPDSCL_MEM_PWR_CTRL_BASE_IDX 0 +#define regVPDSCL_MEM_PWR_STATUS 0x0787 +#define regVPDSCL_MEM_PWR_STATUS_BASE_IDX 0 +#define regVPDSCL_DEBUG 0x0788 +#define regVPDSCL_DEBUG_BASE_IDX 0 +#define regVPDSCL_TEST_DEBUG_INDEX 0x0789 +#define regVPDSCL_TEST_DEBUG_INDEX_BASE_IDX 0 +#define regVPDSCL_TEST_DEBUG_DATA 0x078a +#define regVPDSCL_TEST_DEBUG_DATA_BASE_IDX 0 + + +// addressBlock: vpe_vpep_vpdpp0_dispdec_vpcm_dispdec +// base address: 0x0 +#define regVPCM_CONTROL 0x07b8 +#define regVPCM_CONTROL_BASE_IDX 0 +#define regVPCM_POST_CSC_CONTROL 0x07b9 +#define regVPCM_POST_CSC_CONTROL_BASE_IDX 0 +#define regVPCM_POST_CSC_C11_C12 0x07ba +#define regVPCM_POST_CSC_C11_C12_BASE_IDX 0 +#define regVPCM_POST_CSC_C13_C14 0x07bb +#define regVPCM_POST_CSC_C13_C14_BASE_IDX 0 +#define regVPCM_POST_CSC_C21_C22 0x07bc +#define regVPCM_POST_CSC_C21_C22_BASE_IDX 0 +#define regVPCM_POST_CSC_C23_C24 0x07bd +#define regVPCM_POST_CSC_C23_C24_BASE_IDX 0 +#define regVPCM_POST_CSC_C31_C32 0x07be +#define regVPCM_POST_CSC_C31_C32_BASE_IDX 0 +#define regVPCM_POST_CSC_C33_C34 0x07bf +#define regVPCM_POST_CSC_C33_C34_BASE_IDX 0 +#define regVPCM_GAMUT_REMAP_CONTROL 0x07c0 +#define regVPCM_GAMUT_REMAP_CONTROL_BASE_IDX 0 +#define regVPCM_GAMUT_REMAP_C11_C12 0x07c1 +#define regVPCM_GAMUT_REMAP_C11_C12_BASE_IDX 0 +#define regVPCM_GAMUT_REMAP_C13_C14 0x07c2 +#define regVPCM_GAMUT_REMAP_C13_C14_BASE_IDX 0 +#define regVPCM_GAMUT_REMAP_C21_C22 0x07c3 +#define regVPCM_GAMUT_REMAP_C21_C22_BASE_IDX 0 +#define regVPCM_GAMUT_REMAP_C23_C24 0x07c4 +#define regVPCM_GAMUT_REMAP_C23_C24_BASE_IDX 0 +#define regVPCM_GAMUT_REMAP_C31_C32 0x07c5 +#define regVPCM_GAMUT_REMAP_C31_C32_BASE_IDX 0 +#define regVPCM_GAMUT_REMAP_C33_C34 0x07c6 +#define regVPCM_GAMUT_REMAP_C33_C34_BASE_IDX 0 +#define regVPCM_BIAS_CR_R 0x07c7 +#define regVPCM_BIAS_CR_R_BASE_IDX 0 +#define regVPCM_BIAS_Y_G_CB_B 0x07c8 +#define regVPCM_BIAS_Y_G_CB_B_BASE_IDX 0 +#define regVPCM_GAMCOR_CONTROL 0x07c9 +#define regVPCM_GAMCOR_CONTROL_BASE_IDX 0 +#define regVPCM_GAMCOR_LUT_INDEX 0x07ca +#define regVPCM_GAMCOR_LUT_INDEX_BASE_IDX 0 +#define regVPCM_GAMCOR_LUT_DATA 0x07cb +#define regVPCM_GAMCOR_LUT_DATA_BASE_IDX 0 +#define regVPCM_GAMCOR_LUT_CONTROL 0x07cc +#define regVPCM_GAMCOR_LUT_CONTROL_BASE_IDX 0 +#define regVPCM_GAMCOR_RAMA_START_CNTL_B 0x07cd +#define regVPCM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX 0 +#define regVPCM_GAMCOR_RAMA_START_CNTL_G 0x07ce +#define regVPCM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX 0 +#define regVPCM_GAMCOR_RAMA_START_CNTL_R 0x07cf +#define regVPCM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX 0 +#define regVPCM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x07d0 +#define regVPCM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX 0 +#define regVPCM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x07d1 +#define regVPCM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX 0 +#define regVPCM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x07d2 +#define regVPCM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX 0 +#define regVPCM_GAMCOR_RAMA_START_BASE_CNTL_B 0x07d3 +#define regVPCM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX 0 +#define regVPCM_GAMCOR_RAMA_START_BASE_CNTL_G 0x07d4 +#define regVPCM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX 0 +#define regVPCM_GAMCOR_RAMA_START_BASE_CNTL_R 0x07d5 +#define regVPCM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX 0 +#define regVPCM_GAMCOR_RAMA_END_CNTL1_B 0x07d6 +#define regVPCM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX 0 +#define regVPCM_GAMCOR_RAMA_END_CNTL2_B 0x07d7 +#define regVPCM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX 0 +#define regVPCM_GAMCOR_RAMA_END_CNTL1_G 0x07d8 +#define regVPCM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX 0 +#define regVPCM_GAMCOR_RAMA_END_CNTL2_G 0x07d9 +#define regVPCM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX 0 +#define regVPCM_GAMCOR_RAMA_END_CNTL1_R 0x07da +#define regVPCM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX 0 +#define regVPCM_GAMCOR_RAMA_END_CNTL2_R 0x07db +#define regVPCM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX 0 +#define regVPCM_GAMCOR_RAMA_OFFSET_B 0x07dc +#define regVPCM_GAMCOR_RAMA_OFFSET_B_BASE_IDX 0 +#define regVPCM_GAMCOR_RAMA_OFFSET_G 0x07dd +#define regVPCM_GAMCOR_RAMA_OFFSET_G_BASE_IDX 0 +#define regVPCM_GAMCOR_RAMA_OFFSET_R 0x07de +#define regVPCM_GAMCOR_RAMA_OFFSET_R_BASE_IDX 0 +#define regVPCM_GAMCOR_RAMA_REGION_0_1 0x07df +#define regVPCM_GAMCOR_RAMA_REGION_0_1_BASE_IDX 0 +#define regVPCM_GAMCOR_RAMA_REGION_2_3 0x07e0 +#define regVPCM_GAMCOR_RAMA_REGION_2_3_BASE_IDX 0 +#define regVPCM_GAMCOR_RAMA_REGION_4_5 0x07e1 +#define regVPCM_GAMCOR_RAMA_REGION_4_5_BASE_IDX 0 +#define regVPCM_GAMCOR_RAMA_REGION_6_7 0x07e2 +#define regVPCM_GAMCOR_RAMA_REGION_6_7_BASE_IDX 0 +#define regVPCM_GAMCOR_RAMA_REGION_8_9 0x07e3 +#define regVPCM_GAMCOR_RAMA_REGION_8_9_BASE_IDX 0 +#define regVPCM_GAMCOR_RAMA_REGION_10_11 0x07e4 +#define regVPCM_GAMCOR_RAMA_REGION_10_11_BASE_IDX 0 +#define regVPCM_GAMCOR_RAMA_REGION_12_13 0x07e5 +#define regVPCM_GAMCOR_RAMA_REGION_12_13_BASE_IDX 0 +#define regVPCM_GAMCOR_RAMA_REGION_14_15 0x07e6 +#define regVPCM_GAMCOR_RAMA_REGION_14_15_BASE_IDX 0 +#define regVPCM_GAMCOR_RAMA_REGION_16_17 0x07e7 +#define regVPCM_GAMCOR_RAMA_REGION_16_17_BASE_IDX 0 +#define regVPCM_GAMCOR_RAMA_REGION_18_19 0x07e8 +#define regVPCM_GAMCOR_RAMA_REGION_18_19_BASE_IDX 0 +#define regVPCM_GAMCOR_RAMA_REGION_20_21 0x07e9 +#define regVPCM_GAMCOR_RAMA_REGION_20_21_BASE_IDX 0 +#define regVPCM_GAMCOR_RAMA_REGION_22_23 0x07ea +#define regVPCM_GAMCOR_RAMA_REGION_22_23_BASE_IDX 0 +#define regVPCM_GAMCOR_RAMA_REGION_24_25 0x07eb +#define regVPCM_GAMCOR_RAMA_REGION_24_25_BASE_IDX 0 +#define regVPCM_GAMCOR_RAMA_REGION_26_27 0x07ec +#define regVPCM_GAMCOR_RAMA_REGION_26_27_BASE_IDX 0 +#define regVPCM_GAMCOR_RAMA_REGION_28_29 0x07ed +#define regVPCM_GAMCOR_RAMA_REGION_28_29_BASE_IDX 0 +#define regVPCM_GAMCOR_RAMA_REGION_30_31 0x07ee +#define regVPCM_GAMCOR_RAMA_REGION_30_31_BASE_IDX 0 +#define regVPCM_GAMCOR_RAMA_REGION_32_33 0x07ef +#define regVPCM_GAMCOR_RAMA_REGION_32_33_BASE_IDX 0 +#define regVPCM_HDR_MULT_COEF 0x07f0 +#define regVPCM_HDR_MULT_COEF_BASE_IDX 0 +#define regVPCM_MEM_PWR_CTRL 0x07f1 +#define regVPCM_MEM_PWR_CTRL_BASE_IDX 0 +#define regVPCM_MEM_PWR_STATUS 0x07f2 +#define regVPCM_MEM_PWR_STATUS_BASE_IDX 0 +#define regVPCM_DEALPHA 0x07f4 +#define regVPCM_DEALPHA_BASE_IDX 0 +#define regVPCM_COEF_FORMAT 0x07f5 +#define regVPCM_COEF_FORMAT_BASE_IDX 0 +#define regVPCM_TEST_DEBUG_INDEX 0x07f6 +#define regVPCM_TEST_DEBUG_INDEX_BASE_IDX 0 +#define regVPCM_TEST_DEBUG_DATA 0x07f7 +#define regVPCM_TEST_DEBUG_DATA_BASE_IDX 0 + + +// addressBlock: vpe_vpep_vpdpp0_dispdec_vpdpp_top_dispdec +// base address: 0x0 +#define regVPDPP_CONTROL 0x0738 +#define regVPDPP_CONTROL_BASE_IDX 0 +#define regVPDPP_SOFT_RESET 0x0739 +#define regVPDPP_SOFT_RESET_BASE_IDX 0 +#define regVPDPP_CRC_VAL_R_G 0x073a +#define regVPDPP_CRC_VAL_R_G_BASE_IDX 0 +#define regVPDPP_CRC_VAL_B_A 0x073b +#define regVPDPP_CRC_VAL_B_A_BASE_IDX 0 +#define regVPDPP_CRC_CTRL 0x073c +#define regVPDPP_CRC_CTRL_BASE_IDX 0 +#define regVPHOST_READ_CONTROL 0x073d +#define regVPHOST_READ_CONTROL_BASE_IDX 0 +#define regVPDPP_DEBUG_SEL 0x073e +#define regVPDPP_DEBUG_SEL_BASE_IDX 0 +#define regVPDPP_DEBUG_SPARE 0x073f +#define regVPDPP_DEBUG_SPARE_BASE_IDX 0 +#define regVPDPP_TEST_DEBUG_INDEX 0x0740 +#define regVPDPP_TEST_DEBUG_INDEX_BASE_IDX 0 +#define regVPDPP_TEST_DEBUG_DATA 0x0741 +#define regVPDPP_TEST_DEBUG_DATA_BASE_IDX 0 + + +// addressBlock: vpe_vpep_vpmpc_vpmpcc0_dispdec +// base address: 0x0 +#define regVPMPCC_TOP_SEL 0x0dc0 +#define regVPMPCC_TOP_SEL_BASE_IDX 0 +#define regVPMPCC_BOT_SEL 0x0dc1 +#define regVPMPCC_BOT_SEL_BASE_IDX 0 +#define regVPMPCC_VPOPP_ID 0x0dc2 +#define regVPMPCC_VPOPP_ID_BASE_IDX 0 +#define regVPMPCC_CONTROL 0x0dc3 +#define regVPMPCC_CONTROL_BASE_IDX 0 +#define regVPMPCC_TOP_GAIN 0x0dc4 +#define regVPMPCC_TOP_GAIN_BASE_IDX 0 +#define regVPMPCC_BOT_GAIN_INSIDE 0x0dc5 +#define regVPMPCC_BOT_GAIN_INSIDE_BASE_IDX 0 +#define regVPMPCC_BOT_GAIN_OUTSIDE 0x0dc6 +#define regVPMPCC_BOT_GAIN_OUTSIDE_BASE_IDX 0 +#define regVPMPCC_MOVABLE_CM_LOCATION_CONTROL 0x0dc7 +#define regVPMPCC_MOVABLE_CM_LOCATION_CONTROL_BASE_IDX 0 +#define regVPMPCC_BG_R_CR 0x0dc8 +#define regVPMPCC_BG_R_CR_BASE_IDX 0 +#define regVPMPCC_BG_G_Y 0x0dc9 +#define regVPMPCC_BG_G_Y_BASE_IDX 0 +#define regVPMPCC_BG_B_CB 0x0dca +#define regVPMPCC_BG_B_CB_BASE_IDX 0 +#define regVPMPCC_MEM_PWR_CTRL 0x0dcb +#define regVPMPCC_MEM_PWR_CTRL_BASE_IDX 0 +#define regVPMPCC_STATUS 0x0dcc +#define regVPMPCC_STATUS_BASE_IDX 0 +#define regVPMPCC_TEST_DEBUG_INDEX 0x0dce +#define regVPMPCC_TEST_DEBUG_INDEX_BASE_IDX 0 +#define regVPMPCC_TEST_DEBUG_DATA 0x0dcf +#define regVPMPCC_TEST_DEBUG_DATA_BASE_IDX 0 + + +// addressBlock: vpe_vpep_vpmpc_vpmpc_cfg_dispdec +// base address: 0x0 +#define regVPMPC_CLOCK_CONTROL 0x0f8c +#define regVPMPC_CLOCK_CONTROL_BASE_IDX 0 +#define regVPMPC_SOFT_RESET 0x0f8d +#define regVPMPC_SOFT_RESET_BASE_IDX 0 +#define regVPMPC_CRC_CTRL 0x0f8e +#define regVPMPC_CRC_CTRL_BASE_IDX 0 +#define regVPMPC_CRC_SEL_CONTROL 0x0f8f +#define regVPMPC_CRC_SEL_CONTROL_BASE_IDX 0 +#define regVPMPC_CRC_RESULT_AR 0x0f90 +#define regVPMPC_CRC_RESULT_AR_BASE_IDX 0 +#define regVPMPC_CRC_RESULT_GB 0x0f91 +#define regVPMPC_CRC_RESULT_GB_BASE_IDX 0 +#define regVPMPC_CRC_RESULT_C 0x0f92 +#define regVPMPC_CRC_RESULT_C_BASE_IDX 0 +#define regVPMPC_DEBUG_CONTROL 0x0f93 +#define regVPMPC_DEBUG_CONTROL_BASE_IDX 0 +#define regVPMPCC_DEBUG_DATA_SELECT 0x0f94 +#define regVPMPCC_DEBUG_DATA_SELECT_BASE_IDX 0 +#define regVPMPC_BYPASS_BG_AR 0x0f95 +#define regVPMPC_BYPASS_BG_AR_BASE_IDX 0 +#define regVPMPC_BYPASS_BG_GB 0x0f96 +#define regVPMPC_BYPASS_BG_GB_BASE_IDX 0 +#define regVPMPC_HOST_READ_CONTROL 0x0f97 +#define regVPMPC_HOST_READ_CONTROL_BASE_IDX 0 +#define regVPMPC_PENDING_STATUS_MISC 0x0f98 +#define regVPMPC_PENDING_STATUS_MISC_BASE_IDX 0 +#define regVPMPC_CFG_TEST_DEBUG_INDEX 0x0fbd +#define regVPMPC_CFG_TEST_DEBUG_INDEX_BASE_IDX 0 +#define regVPMPC_CFG_TEST_DEBUG_DATA 0x0fbe +#define regVPMPC_CFG_TEST_DEBUG_DATA_BASE_IDX 0 + + +// addressBlock: vpe_vpep_vpmpc_vpmpcc_ogam0_dispdec +// base address: 0x0 +#define regVPMPCC_OGAM_CONTROL 0x0e14 +#define regVPMPCC_OGAM_CONTROL_BASE_IDX 0 +#define regVPMPCC_OGAM_LUT_INDEX 0x0e15 +#define regVPMPCC_OGAM_LUT_INDEX_BASE_IDX 0 +#define regVPMPCC_OGAM_LUT_DATA 0x0e16 +#define regVPMPCC_OGAM_LUT_DATA_BASE_IDX 0 +#define regVPMPCC_OGAM_LUT_CONTROL 0x0e17 +#define regVPMPCC_OGAM_LUT_CONTROL_BASE_IDX 0 +#define regVPMPCC_OGAM_RAMA_START_CNTL_B 0x0e18 +#define regVPMPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 0 +#define regVPMPCC_OGAM_RAMA_START_CNTL_G 0x0e19 +#define regVPMPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 0 +#define regVPMPCC_OGAM_RAMA_START_CNTL_R 0x0e1a +#define regVPMPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 0 +#define regVPMPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x0e1b +#define regVPMPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 0 +#define regVPMPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x0e1c +#define regVPMPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 0 +#define regVPMPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x0e1d +#define regVPMPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 0 +#define regVPMPCC_OGAM_RAMA_START_BASE_CNTL_B 0x0e1e +#define regVPMPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 0 +#define regVPMPCC_OGAM_RAMA_START_BASE_CNTL_G 0x0e1f +#define regVPMPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 0 +#define regVPMPCC_OGAM_RAMA_START_BASE_CNTL_R 0x0e20 +#define regVPMPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 0 +#define regVPMPCC_OGAM_RAMA_END_CNTL1_B 0x0e21 +#define regVPMPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 0 +#define regVPMPCC_OGAM_RAMA_END_CNTL2_B 0x0e22 +#define regVPMPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 0 +#define regVPMPCC_OGAM_RAMA_END_CNTL1_G 0x0e23 +#define regVPMPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 0 +#define regVPMPCC_OGAM_RAMA_END_CNTL2_G 0x0e24 +#define regVPMPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 0 +#define regVPMPCC_OGAM_RAMA_END_CNTL1_R 0x0e25 +#define regVPMPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 0 +#define regVPMPCC_OGAM_RAMA_END_CNTL2_R 0x0e26 +#define regVPMPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 0 +#define regVPMPCC_OGAM_RAMA_OFFSET_B 0x0e27 +#define regVPMPCC_OGAM_RAMA_OFFSET_B_BASE_IDX 0 +#define regVPMPCC_OGAM_RAMA_OFFSET_G 0x0e28 +#define regVPMPCC_OGAM_RAMA_OFFSET_G_BASE_IDX 0 +#define regVPMPCC_OGAM_RAMA_OFFSET_R 0x0e29 +#define regVPMPCC_OGAM_RAMA_OFFSET_R_BASE_IDX 0 +#define regVPMPCC_OGAM_RAMA_REGION_0_1 0x0e2a +#define regVPMPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 0 +#define regVPMPCC_OGAM_RAMA_REGION_2_3 0x0e2b +#define regVPMPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 0 +#define regVPMPCC_OGAM_RAMA_REGION_4_5 0x0e2c +#define regVPMPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 0 +#define regVPMPCC_OGAM_RAMA_REGION_6_7 0x0e2d +#define regVPMPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 0 +#define regVPMPCC_OGAM_RAMA_REGION_8_9 0x0e2e +#define regVPMPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 0 +#define regVPMPCC_OGAM_RAMA_REGION_10_11 0x0e2f +#define regVPMPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 0 +#define regVPMPCC_OGAM_RAMA_REGION_12_13 0x0e30 +#define regVPMPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 0 +#define regVPMPCC_OGAM_RAMA_REGION_14_15 0x0e31 +#define regVPMPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 0 +#define regVPMPCC_OGAM_RAMA_REGION_16_17 0x0e32 +#define regVPMPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 0 +#define regVPMPCC_OGAM_RAMA_REGION_18_19 0x0e33 +#define regVPMPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 0 +#define regVPMPCC_OGAM_RAMA_REGION_20_21 0x0e34 +#define regVPMPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 0 +#define regVPMPCC_OGAM_RAMA_REGION_22_23 0x0e35 +#define regVPMPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 0 +#define regVPMPCC_OGAM_RAMA_REGION_24_25 0x0e36 +#define regVPMPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 0 +#define regVPMPCC_OGAM_RAMA_REGION_26_27 0x0e37 +#define regVPMPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 0 +#define regVPMPCC_OGAM_RAMA_REGION_28_29 0x0e38 +#define regVPMPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 0 +#define regVPMPCC_OGAM_RAMA_REGION_30_31 0x0e39 +#define regVPMPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 0 +#define regVPMPCC_OGAM_RAMA_REGION_32_33 0x0e3a +#define regVPMPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 0 +#define regVPMPCC_GAMUT_REMAP_COEF_FORMAT 0x0e3b +#define regVPMPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 0 +#define regVPMPCC_GAMUT_REMAP_MODE 0x0e3c +#define regVPMPCC_GAMUT_REMAP_MODE_BASE_IDX 0 +#define regVPMPC_GAMUT_REMAP_C11_C12_A 0x0e3d +#define regVPMPC_GAMUT_REMAP_C11_C12_A_BASE_IDX 0 +#define regVPMPC_GAMUT_REMAP_C13_C14_A 0x0e3e +#define regVPMPC_GAMUT_REMAP_C13_C14_A_BASE_IDX 0 +#define regVPMPC_GAMUT_REMAP_C21_C22_A 0x0e3f +#define regVPMPC_GAMUT_REMAP_C21_C22_A_BASE_IDX 0 +#define regVPMPC_GAMUT_REMAP_C23_C24_A 0x0e40 +#define regVPMPC_GAMUT_REMAP_C23_C24_A_BASE_IDX 0 +#define regVPMPC_GAMUT_REMAP_C31_C32_A 0x0e41 +#define regVPMPC_GAMUT_REMAP_C31_C32_A_BASE_IDX 0 +#define regVPMPC_GAMUT_REMAP_C33_C34_A 0x0e42 +#define regVPMPC_GAMUT_REMAP_C33_C34_A_BASE_IDX 0 +#define regVPMPCC_OGAM_TEST_DEBUG_INDEX 0x0e44 +#define regVPMPCC_OGAM_TEST_DEBUG_INDEX_BASE_IDX 0 +#define regVPMPCC_OGAM_TEST_DEBUG_DATA 0x0e45 +#define regVPMPCC_OGAM_TEST_DEBUG_DATA_BASE_IDX 0 + + +// addressBlock: vpe_vpep_vpmpc_vpmpcc_mcm0_dispdec +// base address: 0x0 +#define regVPMPCC_MCM_SHAPER_CONTROL 0x1059 +#define regVPMPCC_MCM_SHAPER_CONTROL_BASE_IDX 0 +#define regVPMPCC_MCM_SHAPER_OFFSET_R 0x105a +#define regVPMPCC_MCM_SHAPER_OFFSET_R_BASE_IDX 0 +#define regVPMPCC_MCM_SHAPER_OFFSET_G 0x105b +#define regVPMPCC_MCM_SHAPER_OFFSET_G_BASE_IDX 0 +#define regVPMPCC_MCM_SHAPER_OFFSET_B 0x105c +#define regVPMPCC_MCM_SHAPER_OFFSET_B_BASE_IDX 0 +#define regVPMPCC_MCM_SHAPER_SCALE_R 0x105d +#define regVPMPCC_MCM_SHAPER_SCALE_R_BASE_IDX 0 +#define regVPMPCC_MCM_SHAPER_SCALE_G_B 0x105e +#define regVPMPCC_MCM_SHAPER_SCALE_G_B_BASE_IDX 0 +#define regVPMPCC_MCM_SHAPER_LUT_INDEX 0x105f +#define regVPMPCC_MCM_SHAPER_LUT_INDEX_BASE_IDX 0 +#define regVPMPCC_MCM_SHAPER_LUT_DATA 0x1060 +#define regVPMPCC_MCM_SHAPER_LUT_DATA_BASE_IDX 0 +#define regVPMPCC_MCM_SHAPER_LUT_WRITE_EN_MASK 0x1061 +#define regVPMPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 0 +#define regVPMPCC_MCM_SHAPER_RAMA_START_CNTL_B 0x1062 +#define regVPMPCC_MCM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 0 +#define regVPMPCC_MCM_SHAPER_RAMA_START_CNTL_G 0x1063 +#define regVPMPCC_MCM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 0 +#define regVPMPCC_MCM_SHAPER_RAMA_START_CNTL_R 0x1064 +#define regVPMPCC_MCM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 0 +#define regVPMPCC_MCM_SHAPER_RAMA_END_CNTL_B 0x1065 +#define regVPMPCC_MCM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 0 +#define regVPMPCC_MCM_SHAPER_RAMA_END_CNTL_G 0x1066 +#define regVPMPCC_MCM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 0 +#define regVPMPCC_MCM_SHAPER_RAMA_END_CNTL_R 0x1067 +#define regVPMPCC_MCM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 0 +#define regVPMPCC_MCM_SHAPER_RAMA_REGION_0_1 0x1068 +#define regVPMPCC_MCM_SHAPER_RAMA_REGION_0_1_BASE_IDX 0 +#define regVPMPCC_MCM_SHAPER_RAMA_REGION_2_3 0x1069 +#define regVPMPCC_MCM_SHAPER_RAMA_REGION_2_3_BASE_IDX 0 +#define regVPMPCC_MCM_SHAPER_RAMA_REGION_4_5 0x106a +#define regVPMPCC_MCM_SHAPER_RAMA_REGION_4_5_BASE_IDX 0 +#define regVPMPCC_MCM_SHAPER_RAMA_REGION_6_7 0x106b +#define regVPMPCC_MCM_SHAPER_RAMA_REGION_6_7_BASE_IDX 0 +#define regVPMPCC_MCM_SHAPER_RAMA_REGION_8_9 0x106c +#define regVPMPCC_MCM_SHAPER_RAMA_REGION_8_9_BASE_IDX 0 +#define regVPMPCC_MCM_SHAPER_RAMA_REGION_10_11 0x106d +#define regVPMPCC_MCM_SHAPER_RAMA_REGION_10_11_BASE_IDX 0 +#define regVPMPCC_MCM_SHAPER_RAMA_REGION_12_13 0x106e +#define regVPMPCC_MCM_SHAPER_RAMA_REGION_12_13_BASE_IDX 0 +#define regVPMPCC_MCM_SHAPER_RAMA_REGION_14_15 0x106f +#define regVPMPCC_MCM_SHAPER_RAMA_REGION_14_15_BASE_IDX 0 +#define regVPMPCC_MCM_SHAPER_RAMA_REGION_16_17 0x1070 +#define regVPMPCC_MCM_SHAPER_RAMA_REGION_16_17_BASE_IDX 0 +#define regVPMPCC_MCM_SHAPER_RAMA_REGION_18_19 0x1071 +#define regVPMPCC_MCM_SHAPER_RAMA_REGION_18_19_BASE_IDX 0 +#define regVPMPCC_MCM_SHAPER_RAMA_REGION_20_21 0x1072 +#define regVPMPCC_MCM_SHAPER_RAMA_REGION_20_21_BASE_IDX 0 +#define regVPMPCC_MCM_SHAPER_RAMA_REGION_22_23 0x1073 +#define regVPMPCC_MCM_SHAPER_RAMA_REGION_22_23_BASE_IDX 0 +#define regVPMPCC_MCM_SHAPER_RAMA_REGION_24_25 0x1074 +#define regVPMPCC_MCM_SHAPER_RAMA_REGION_24_25_BASE_IDX 0 +#define regVPMPCC_MCM_SHAPER_RAMA_REGION_26_27 0x1075 +#define regVPMPCC_MCM_SHAPER_RAMA_REGION_26_27_BASE_IDX 0 +#define regVPMPCC_MCM_SHAPER_RAMA_REGION_28_29 0x1076 +#define regVPMPCC_MCM_SHAPER_RAMA_REGION_28_29_BASE_IDX 0 +#define regVPMPCC_MCM_SHAPER_RAMA_REGION_30_31 0x1077 +#define regVPMPCC_MCM_SHAPER_RAMA_REGION_30_31_BASE_IDX 0 +#define regVPMPCC_MCM_SHAPER_RAMA_REGION_32_33 0x1078 +#define regVPMPCC_MCM_SHAPER_RAMA_REGION_32_33_BASE_IDX 0 +#define regVPMPCC_MCM_3DLUT_MODE 0x1079 +#define regVPMPCC_MCM_3DLUT_MODE_BASE_IDX 0 +#define regVPMPCC_MCM_3DLUT_INDEX 0x107a +#define regVPMPCC_MCM_3DLUT_INDEX_BASE_IDX 0 +#define regVPMPCC_MCM_3DLUT_DATA 0x107b +#define regVPMPCC_MCM_3DLUT_DATA_BASE_IDX 0 +#define regVPMPCC_MCM_3DLUT_DATA_30BIT 0x107c +#define regVPMPCC_MCM_3DLUT_DATA_30BIT_BASE_IDX 0 +#define regVPMPCC_MCM_3DLUT_READ_WRITE_CONTROL 0x107d +#define regVPMPCC_MCM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 0 +#define regVPMPCC_MCM_3DLUT_OUT_NORM_FACTOR 0x107e +#define regVPMPCC_MCM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 0 +#define regVPMPCC_MCM_3DLUT_OUT_OFFSET_R 0x107f +#define regVPMPCC_MCM_3DLUT_OUT_OFFSET_R_BASE_IDX 0 +#define regVPMPCC_MCM_3DLUT_OUT_OFFSET_G 0x1080 +#define regVPMPCC_MCM_3DLUT_OUT_OFFSET_G_BASE_IDX 0 +#define regVPMPCC_MCM_3DLUT_OUT_OFFSET_B 0x1081 +#define regVPMPCC_MCM_3DLUT_OUT_OFFSET_B_BASE_IDX 0 +#define regVPMPCC_MCM_1DLUT_CONTROL 0x1082 +#define regVPMPCC_MCM_1DLUT_CONTROL_BASE_IDX 0 +#define regVPMPCC_MCM_1DLUT_LUT_INDEX 0x1083 +#define regVPMPCC_MCM_1DLUT_LUT_INDEX_BASE_IDX 0 +#define regVPMPCC_MCM_1DLUT_LUT_DATA 0x1084 +#define regVPMPCC_MCM_1DLUT_LUT_DATA_BASE_IDX 0 +#define regVPMPCC_MCM_1DLUT_LUT_CONTROL 0x1085 +#define regVPMPCC_MCM_1DLUT_LUT_CONTROL_BASE_IDX 0 +#define regVPMPCC_MCM_1DLUT_RAMA_START_CNTL_B 0x1086 +#define regVPMPCC_MCM_1DLUT_RAMA_START_CNTL_B_BASE_IDX 0 +#define regVPMPCC_MCM_1DLUT_RAMA_START_CNTL_G 0x1087 +#define regVPMPCC_MCM_1DLUT_RAMA_START_CNTL_G_BASE_IDX 0 +#define regVPMPCC_MCM_1DLUT_RAMA_START_CNTL_R 0x1088 +#define regVPMPCC_MCM_1DLUT_RAMA_START_CNTL_R_BASE_IDX 0 +#define regVPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B 0x1089 +#define regVPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B_BASE_IDX 0 +#define regVPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G 0x108a +#define regVPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G_BASE_IDX 0 +#define regVPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R 0x108b +#define regVPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R_BASE_IDX 0 +#define regVPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B 0x108c +#define regVPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B_BASE_IDX 0 +#define regVPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G 0x108d +#define regVPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G_BASE_IDX 0 +#define regVPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R 0x108e +#define regVPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R_BASE_IDX 0 +#define regVPMPCC_MCM_1DLUT_RAMA_END_CNTL1_B 0x108f +#define regVPMPCC_MCM_1DLUT_RAMA_END_CNTL1_B_BASE_IDX 0 +#define regVPMPCC_MCM_1DLUT_RAMA_END_CNTL2_B 0x1090 +#define regVPMPCC_MCM_1DLUT_RAMA_END_CNTL2_B_BASE_IDX 0 +#define regVPMPCC_MCM_1DLUT_RAMA_END_CNTL1_G 0x1091 +#define regVPMPCC_MCM_1DLUT_RAMA_END_CNTL1_G_BASE_IDX 0 +#define regVPMPCC_MCM_1DLUT_RAMA_END_CNTL2_G 0x1092 +#define regVPMPCC_MCM_1DLUT_RAMA_END_CNTL2_G_BASE_IDX 0 +#define regVPMPCC_MCM_1DLUT_RAMA_END_CNTL1_R 0x1093 +#define regVPMPCC_MCM_1DLUT_RAMA_END_CNTL1_R_BASE_IDX 0 +#define regVPMPCC_MCM_1DLUT_RAMA_END_CNTL2_R 0x1094 +#define regVPMPCC_MCM_1DLUT_RAMA_END_CNTL2_R_BASE_IDX 0 +#define regVPMPCC_MCM_1DLUT_RAMA_OFFSET_B 0x1095 +#define regVPMPCC_MCM_1DLUT_RAMA_OFFSET_B_BASE_IDX 0 +#define regVPMPCC_MCM_1DLUT_RAMA_OFFSET_G 0x1096 +#define regVPMPCC_MCM_1DLUT_RAMA_OFFSET_G_BASE_IDX 0 +#define regVPMPCC_MCM_1DLUT_RAMA_OFFSET_R 0x1097 +#define regVPMPCC_MCM_1DLUT_RAMA_OFFSET_R_BASE_IDX 0 +#define regVPMPCC_MCM_1DLUT_RAMA_REGION_0_1 0x1098 +#define regVPMPCC_MCM_1DLUT_RAMA_REGION_0_1_BASE_IDX 0 +#define regVPMPCC_MCM_1DLUT_RAMA_REGION_2_3 0x1099 +#define regVPMPCC_MCM_1DLUT_RAMA_REGION_2_3_BASE_IDX 0 +#define regVPMPCC_MCM_1DLUT_RAMA_REGION_4_5 0x109a +#define regVPMPCC_MCM_1DLUT_RAMA_REGION_4_5_BASE_IDX 0 +#define regVPMPCC_MCM_1DLUT_RAMA_REGION_6_7 0x109b +#define regVPMPCC_MCM_1DLUT_RAMA_REGION_6_7_BASE_IDX 0 +#define regVPMPCC_MCM_1DLUT_RAMA_REGION_8_9 0x109c +#define regVPMPCC_MCM_1DLUT_RAMA_REGION_8_9_BASE_IDX 0 +#define regVPMPCC_MCM_1DLUT_RAMA_REGION_10_11 0x109d +#define regVPMPCC_MCM_1DLUT_RAMA_REGION_10_11_BASE_IDX 0 +#define regVPMPCC_MCM_1DLUT_RAMA_REGION_12_13 0x109e +#define regVPMPCC_MCM_1DLUT_RAMA_REGION_12_13_BASE_IDX 0 +#define regVPMPCC_MCM_1DLUT_RAMA_REGION_14_15 0x109f +#define regVPMPCC_MCM_1DLUT_RAMA_REGION_14_15_BASE_IDX 0 +#define regVPMPCC_MCM_1DLUT_RAMA_REGION_16_17 0x10a0 +#define regVPMPCC_MCM_1DLUT_RAMA_REGION_16_17_BASE_IDX 0 +#define regVPMPCC_MCM_1DLUT_RAMA_REGION_18_19 0x10a1 +#define regVPMPCC_MCM_1DLUT_RAMA_REGION_18_19_BASE_IDX 0 +#define regVPMPCC_MCM_1DLUT_RAMA_REGION_20_21 0x10a2 +#define regVPMPCC_MCM_1DLUT_RAMA_REGION_20_21_BASE_IDX 0 +#define regVPMPCC_MCM_1DLUT_RAMA_REGION_22_23 0x10a3 +#define regVPMPCC_MCM_1DLUT_RAMA_REGION_22_23_BASE_IDX 0 +#define regVPMPCC_MCM_1DLUT_RAMA_REGION_24_25 0x10a4 +#define regVPMPCC_MCM_1DLUT_RAMA_REGION_24_25_BASE_IDX 0 +#define regVPMPCC_MCM_1DLUT_RAMA_REGION_26_27 0x10a5 +#define regVPMPCC_MCM_1DLUT_RAMA_REGION_26_27_BASE_IDX 0 +#define regVPMPCC_MCM_1DLUT_RAMA_REGION_28_29 0x10a6 +#define regVPMPCC_MCM_1DLUT_RAMA_REGION_28_29_BASE_IDX 0 +#define regVPMPCC_MCM_1DLUT_RAMA_REGION_30_31 0x10a7 +#define regVPMPCC_MCM_1DLUT_RAMA_REGION_30_31_BASE_IDX 0 +#define regVPMPCC_MCM_1DLUT_RAMA_REGION_32_33 0x10a8 +#define regVPMPCC_MCM_1DLUT_RAMA_REGION_32_33_BASE_IDX 0 +#define regVPMPCC_MCM_MEM_PWR_CTRL 0x10a9 +#define regVPMPCC_MCM_MEM_PWR_CTRL_BASE_IDX 0 +#define regVPMPCC_MCM_TEST_DEBUG_INDEX 0x10ab +#define regVPMPCC_MCM_TEST_DEBUG_INDEX_BASE_IDX 0 +#define regVPMPCC_MCM_TEST_DEBUG_DATA 0x10ac +#define regVPMPCC_MCM_TEST_DEBUG_DATA_BASE_IDX 0 + + +// addressBlock: vpe_vpep_vpmpc_vpmpc_ocsc_dispdec +// base address: 0x0 +#define regVPMPC_OUT0_MUX 0x0fcc +#define regVPMPC_OUT0_MUX_BASE_IDX 0 +#define regVPMPC_OUT0_FLOAT_CONTROL 0x0fcd +#define regVPMPC_OUT0_FLOAT_CONTROL_BASE_IDX 0 +#define regVPMPC_OUT0_DENORM_CONTROL 0x0fce +#define regVPMPC_OUT0_DENORM_CONTROL_BASE_IDX 0 +#define regVPMPC_OUT0_DENORM_CLAMP_G_Y 0x0fcf +#define regVPMPC_OUT0_DENORM_CLAMP_G_Y_BASE_IDX 0 +#define regVPMPC_OUT0_DENORM_CLAMP_B_CB 0x0fd0 +#define regVPMPC_OUT0_DENORM_CLAMP_B_CB_BASE_IDX 0 +#define regVPMPC_OUT_CSC_COEF_FORMAT 0x0fe4 +#define regVPMPC_OUT_CSC_COEF_FORMAT_BASE_IDX 0 +#define regVPMPC_OUT0_CSC_MODE 0x0fe5 +#define regVPMPC_OUT0_CSC_MODE_BASE_IDX 0 +#define regVPMPC_OUT0_CSC_C11_C12_A 0x0fe6 +#define regVPMPC_OUT0_CSC_C11_C12_A_BASE_IDX 0 +#define regVPMPC_OUT0_CSC_C13_C14_A 0x0fe7 +#define regVPMPC_OUT0_CSC_C13_C14_A_BASE_IDX 0 +#define regVPMPC_OUT0_CSC_C21_C22_A 0x0fe8 +#define regVPMPC_OUT0_CSC_C21_C22_A_BASE_IDX 0 +#define regVPMPC_OUT0_CSC_C23_C24_A 0x0fe9 +#define regVPMPC_OUT0_CSC_C23_C24_A_BASE_IDX 0 +#define regVPMPC_OUT0_CSC_C31_C32_A 0x0fea +#define regVPMPC_OUT0_CSC_C31_C32_A_BASE_IDX 0 +#define regVPMPC_OUT0_CSC_C33_C34_A 0x0feb +#define regVPMPC_OUT0_CSC_C33_C34_A_BASE_IDX 0 +#define regVPMPC_OCSC_TEST_DEBUG_INDEX 0x1035 +#define regVPMPC_OCSC_TEST_DEBUG_INDEX_BASE_IDX 0 +#define regVPMPC_OCSC_TEST_DEBUG_DATA 0x1036 +#define regVPMPC_OCSC_TEST_DEBUG_DATA_BASE_IDX 0 + + +// addressBlock: vpe_vpep_vpopp_vpfmt0_dispdec +// base address: 0x0 +#define regVPFMT_CLAMP_COMPONENT_R 0x12b0 +#define regVPFMT_CLAMP_COMPONENT_R_BASE_IDX 0 +#define regVPFMT_CLAMP_COMPONENT_G 0x12b1 +#define regVPFMT_CLAMP_COMPONENT_G_BASE_IDX 0 +#define regVPFMT_CLAMP_COMPONENT_B 0x12b2 +#define regVPFMT_CLAMP_COMPONENT_B_BASE_IDX 0 +#define regVPFMT_DYNAMIC_EXP_CNTL 0x12b3 +#define regVPFMT_DYNAMIC_EXP_CNTL_BASE_IDX 0 +#define regVPFMT_CONTROL 0x12b4 +#define regVPFMT_CONTROL_BASE_IDX 0 +#define regVPFMT_BIT_DEPTH_CONTROL 0x12b5 +#define regVPFMT_BIT_DEPTH_CONTROL_BASE_IDX 0 +#define regVPFMT_DITHER_RAND_R_SEED 0x12b6 +#define regVPFMT_DITHER_RAND_R_SEED_BASE_IDX 0 +#define regVPFMT_DITHER_RAND_G_SEED 0x12b7 +#define regVPFMT_DITHER_RAND_G_SEED_BASE_IDX 0 +#define regVPFMT_DITHER_RAND_B_SEED 0x12b8 +#define regVPFMT_DITHER_RAND_B_SEED_BASE_IDX 0 +#define regVPFMT_CLAMP_CNTL 0x12b9 +#define regVPFMT_CLAMP_CNTL_BASE_IDX 0 +#define regVPFMT_DEBUG_CNTL 0x12bc +#define regVPFMT_DEBUG_CNTL_BASE_IDX 0 +#define regVPFMT_TEST_DEBUG_INDEX 0x12be +#define regVPFMT_TEST_DEBUG_INDEX_BASE_IDX 0 +#define regVPFMT_TEST_DEBUG_DATA 0x12bf +#define regVPFMT_TEST_DEBUG_DATA_BASE_IDX 0 + + +// addressBlock: vpe_vpep_vpopp_vpopp_pipe0_dispdec +// base address: 0x0 +#define regVPOPP_PIPE_CONTROL 0x12e8 +#define regVPOPP_PIPE_CONTROL_BASE_IDX 0 +#define regVPOPP_PIPE_SPARE_DEBUG 0x12e9 +#define regVPOPP_PIPE_SPARE_DEBUG_BASE_IDX 0 +#define regVPOPP_PIPE_TEST_DEBUG_INDEX 0x12ea +#define regVPOPP_PIPE_TEST_DEBUG_INDEX_BASE_IDX 0 +#define regVPOPP_PIPE_TEST_DEBUG_DATA 0x12eb +#define regVPOPP_PIPE_TEST_DEBUG_DATA_BASE_IDX 0 + + +// addressBlock: vpe_vpep_vpopp_vpopp_pipe_crc0_dispdec +// base address: 0x0 +#define regVPOPP_PIPE_CRC_CONTROL 0x12ee +#define regVPOPP_PIPE_CRC_CONTROL_BASE_IDX 0 +#define regVPOPP_PIPE_CRC_MASK 0x12ef +#define regVPOPP_PIPE_CRC_MASK_BASE_IDX 0 +#define regVPOPP_PIPE_CRC_RESULT0 0x12f0 +#define regVPOPP_PIPE_CRC_RESULT0_BASE_IDX 0 +#define regVPOPP_PIPE_CRC_RESULT1 0x12f1 +#define regVPOPP_PIPE_CRC_RESULT1_BASE_IDX 0 +#define regVPOPP_PIPE_CRC_RESULT2 0x12f2 +#define regVPOPP_PIPE_CRC_RESULT2_BASE_IDX 0 + + +// addressBlock: vpe_vpep_vpopp_vpopp_top_dispdec +// base address: 0x0 +#define regVPOPP_TOP_CLK_CONTROL 0x13c2 +#define regVPOPP_TOP_CLK_CONTROL_BASE_IDX 0 +#define regVPOPP_DEBUG_CONTROL 0x13c3 +#define regVPOPP_DEBUG_CONTROL_BASE_IDX 0 +#define regVPOPP_TOP_SPARE_DEBUG 0x13c4 +#define regVPOPP_TOP_SPARE_DEBUG_BASE_IDX 0 +#define regVPOPP_TOP_TEST_DEBUG_INDEX 0x13c5 +#define regVPOPP_TOP_TEST_DEBUG_INDEX_BASE_IDX 0 +#define regVPOPP_TOP_TEST_DEBUG_DATA 0x13c6 +#define regVPOPP_TOP_TEST_DEBUG_DATA_BASE_IDX 0 + + +// addressBlock: vpe_vpep_vpcdc_cdc_dispdec +// base address: 0x0 +#define regVPEP_MGCG_CNTL 0x0600 +#define regVPEP_MGCG_CNTL_BASE_IDX 0 +#define regVPCDC_SOFT_RESET 0x0601 +#define regVPCDC_SOFT_RESET_BASE_IDX 0 +#define regVPCDC_FE0_SURFACE_CONFIG 0x0602 +#define regVPCDC_FE0_SURFACE_CONFIG_BASE_IDX 0 +#define regVPCDC_FE0_CROSSBAR_CONFIG 0x0603 +#define regVPCDC_FE0_CROSSBAR_CONFIG_BASE_IDX 0 +#define regVPCDC_FE0_VIEWPORT_START_CONFIG 0x0604 +#define regVPCDC_FE0_VIEWPORT_START_CONFIG_BASE_IDX 0 +#define regVPCDC_FE0_VIEWPORT_DIMENSION_CONFIG 0x0605 +#define regVPCDC_FE0_VIEWPORT_DIMENSION_CONFIG_BASE_IDX 0 +#define regVPCDC_FE0_VIEWPORT_START_C_CONFIG 0x0606 +#define regVPCDC_FE0_VIEWPORT_START_C_CONFIG_BASE_IDX 0 +#define regVPCDC_FE0_VIEWPORT_DIMENSION_C_CONFIG 0x0607 +#define regVPCDC_FE0_VIEWPORT_DIMENSION_C_CONFIG_BASE_IDX 0 +#define regVPCDC_BE0_P2B_CONFIG 0x0608 +#define regVPCDC_BE0_P2B_CONFIG_BASE_IDX 0 +#define regVPCDC_BE0_GLOBAL_SYNC_CONFIG 0x0609 +#define regVPCDC_BE0_GLOBAL_SYNC_CONFIG_BASE_IDX 0 +#define regVPCDC_GLOBAL_SYNC_TRIGGER 0x060a +#define regVPCDC_GLOBAL_SYNC_TRIGGER_BASE_IDX 0 +#define regVPCDC_VREADY_STATUS 0x060b +#define regVPCDC_VREADY_STATUS_BASE_IDX 0 +#define regVPEP_MEM_GLOBAL_PWR_REQ_CNTL 0x060c +#define regVPEP_MEM_GLOBAL_PWR_REQ_CNTL_BASE_IDX 0 +#define regVPFE_MEM_PWR_CNTL 0x060d +#define regVPFE_MEM_PWR_CNTL_BASE_IDX 0 +#define regVPBE_MEM_PWR_CNTL 0x060e +#define regVPBE_MEM_PWR_CNTL_BASE_IDX 0 +#define regVPEP_RBBMIF_TIMEOUT 0x060f +#define regVPEP_RBBMIF_TIMEOUT_BASE_IDX 0 +#define regVPEP_RBBMIF_STATUS 0x0610 +#define regVPEP_RBBMIF_STATUS_BASE_IDX 0 +#define regVPEP_RBBMIF_TIMEOUT_DIS 0x0611 +#define regVPEP_RBBMIF_TIMEOUT_DIS_BASE_IDX 0 +#define regVPCDC_DEBUG_CTRL0 0x0612 +#define regVPCDC_DEBUG_CTRL0_BASE_IDX 0 +#define regVPCDC_DEBUG_CTRL1 0x0613 +#define regVPCDC_DEBUG_CTRL1_BASE_IDX 0 +#define regVPCDC_TEST_DEBUG_INDEX 0x0614 +#define regVPCDC_TEST_DEBUG_INDEX_BASE_IDX 0 +#define regVPCDC_TEST_DEBUG_DATA 0x0615 +#define regVPCDC_TEST_DEBUG_DATA_BASE_IDX 0 + + +// addressBlock: vpe_vpep_vpcdc_vpcdc_dcperfmon_dc_perfmon_dispdec +// base address: 0x3a708 +#define regPERFCOUNTER_CNTL 0x0682 +#define regPERFCOUNTER_CNTL_BASE_IDX 0 +#define regPERFCOUNTER_CNTL2 0x0683 +#define regPERFCOUNTER_CNTL2_BASE_IDX 0 +#define regPERFCOUNTER_STATE 0x0684 +#define regPERFCOUNTER_STATE_BASE_IDX 0 +#define regPERFMON_CNTL 0x0685 +#define regPERFMON_CNTL_BASE_IDX 0 +#define regPERFMON_CNTL2 0x0686 +#define regPERFMON_CNTL2_BASE_IDX 0 +#define regPERFMON_CVALUE_INT_MISC 0x0687 +#define regPERFMON_CVALUE_INT_MISC_BASE_IDX 0 +#define regPERFMON_CVALUE_LOW 0x0688 +#define regPERFMON_CVALUE_LOW_BASE_IDX 0 +#define regPERFMON_HI 0x0689 +#define regPERFMON_HI_BASE_IDX 0 +#define regPERFMON_LOW 0x068a +#define regPERFMON_LOW_BASE_IDX 0 +#define regPERFMON_TEST_DEBUG_INDEX 0x068b +#define regPERFMON_TEST_DEBUG_INDEX_BASE_IDX 0 +#define regPERFMON_TEST_DEBUG_DATA 0x068c +#define regPERFMON_TEST_DEBUG_DATA_BASE_IDX 0 + + +// addressBlock: dc_perfmon_dc_perfmondebugind +// base address: 0x0 +#define ixPERFMON_DEBUG_ID 0x0000 +#define ixPERFMON_DEBUG01 0x0001 +#define ixPERFMON_DEBUG02 0x0002 +#define ixPERFMON_DEBUG03 0x0003 +#define ixPERFMON_DEBUG04 0x0004 +#define ixPERFMON_DEBUG05 0x0005 +#define ixPERFMON_DEBUG06 0x0006 +#define ixPERFMON_DEBUG07 0x0007 +#define ixPERFMON_DEBUG08 0x0008 +#define ixPERFMON_DEBUG09 0x0009 +#define ixPERFMON_DEBUG0A 0x000a +#define ixPERFMON_DEBUG0B 0x000b +#define ixPERFMON_DEBUG0C 0x000c +#define ixPERFMON_DEBUG0D 0x000d +#define ixPERFMON_DEBUG0E 0x000e +#define ixPERFMON_DEBUG0F 0x000f +#define ixPERFMON_DEBUG10 0x0010 +#define ixPERFMON_DEBUG11 0x0011 +#define ixPERFMON_DEBUG12 0x0012 + + +// addressBlock: vpfmt0_vpfmtdebugind +// base address: 0x0 +#define ixVPFMT_DEBUG_ID 0x0000 +#define ixVPFMT_DEBUG0 0x0001 +#define ixVPFMT_DEBUG1 0x0002 +#define ixVPFMT_DEBUG2 0x0003 +#define ixVPFMT_DEBUG3 0x0004 +#define ixVPFMT_DEBUG4 0x0005 +#define ixVPFMT_DEBUG5 0x0006 +#define ixVPFMT_DEBUG6 0x0007 +#define ixVPFMT_DEBUG7 0x0008 +#define ixVPFMT_DEBUG8 0x0009 +#define ixVPFMT_DEBUG9 0x000a +#define ixVPFMT_DEBUG10 0x000b +#define ixVPFMT_DEBUG11 0x000c + + +// addressBlock: vpopp_pipe0_vpopppipedebugind +// base address: 0x0 +#define ixVPOPP_PIPE_DEBUG_ID 0x0000 +#define ixVPOPP_PIPE_DEBUG_0 0x0001 +#define ixVPOPP_PIPE_DEBUG_1 0x0002 +#define ixVPOPP_PIPE_DEBUG_2 0x0003 + + +// addressBlock: vpopp_top_vpopp_topdebugind +// base address: 0x0 +#define ixVPOPP_TOP_DEBUG_ID 0x0000 + +#endif diff --git a/src/amd/vpelib/src/chip/vpe10/inc/asic/bringup_vpe_6_1_0_sh_mask.h b/src/amd/vpelib/src/chip/vpe10/inc/asic/bringup_vpe_6_1_0_sh_mask.h new file mode 100644 index 00000000000..f31df3b837f --- /dev/null +++ b/src/amd/vpelib/src/chip/vpe10/inc/asic/bringup_vpe_6_1_0_sh_mask.h @@ -0,0 +1,4796 @@ +// Headers from LSDp CL1744173 +#ifndef _vpe_6_1_0_SH_MASK_HEADER +#define _vpe_6_1_0_SH_MASK_HEADER + + +// addressBlock: vpe_vpedec +//VPEC_DEC_START +#define VPEC_DEC_START__START__SHIFT 0x0 +#define VPEC_DEC_START__START_MASK 0xFFFFFFFFL +//VPEC_UCODE_ADDR +#define VPEC_UCODE_ADDR__VALUE__SHIFT 0x0 +#define VPEC_UCODE_ADDR__THID__SHIFT 0xf +#define VPEC_UCODE_ADDR__VALUE_MASK 0x00001FFFL +#define VPEC_UCODE_ADDR__THID_MASK 0x00008000L +//VPEC_UCODE_DATA +#define VPEC_UCODE_DATA__VALUE__SHIFT 0x0 +#define VPEC_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL +//VPEC_F32_CNTL +#define VPEC_F32_CNTL__HALT__SHIFT 0x0 +#define VPEC_F32_CNTL__DBG_SELECT_BITS__SHIFT 0x2 +#define VPEC_F32_CNTL__TH0_CHECKSUM_CLR__SHIFT 0x8 +#define VPEC_F32_CNTL__TH0_RESET__SHIFT 0x9 +#define VPEC_F32_CNTL__TH0_ENABLE__SHIFT 0xa +#define VPEC_F32_CNTL__TH1_CHECKSUM_CLR__SHIFT 0xc +#define VPEC_F32_CNTL__TH1_RESET__SHIFT 0xd +#define VPEC_F32_CNTL__TH1_ENABLE__SHIFT 0xe +#define VPEC_F32_CNTL__TH0_PRIORITY__SHIFT 0x10 +#define VPEC_F32_CNTL__TH1_PRIORITY__SHIFT 0x18 +#define VPEC_F32_CNTL__HALT_MASK 0x00000001L +#define VPEC_F32_CNTL__DBG_SELECT_BITS_MASK 0x000000FCL +#define VPEC_F32_CNTL__TH0_CHECKSUM_CLR_MASK 0x00000100L +#define VPEC_F32_CNTL__TH0_RESET_MASK 0x00000200L +#define VPEC_F32_CNTL__TH0_ENABLE_MASK 0x00000400L +#define VPEC_F32_CNTL__TH1_CHECKSUM_CLR_MASK 0x00001000L +#define VPEC_F32_CNTL__TH1_RESET_MASK 0x00002000L +#define VPEC_F32_CNTL__TH1_ENABLE_MASK 0x00004000L +#define VPEC_F32_CNTL__TH0_PRIORITY_MASK 0x00FF0000L +#define VPEC_F32_CNTL__TH1_PRIORITY_MASK 0xFF000000L +//VPEC_MMHUB_CNTL +#define VPEC_MMHUB_CNTL__UNIT_ID__SHIFT 0x0 +#define VPEC_MMHUB_CNTL__UNIT_ID_MASK 0x0000003FL +//VPEC_MMHUB_TRUSTLVL +#define VPEC_MMHUB_TRUSTLVL__SECLVL0__SHIFT 0x0 +#define VPEC_MMHUB_TRUSTLVL__SECLVL1__SHIFT 0x4 +#define VPEC_MMHUB_TRUSTLVL__SECLVL2__SHIFT 0x8 +#define VPEC_MMHUB_TRUSTLVL__SECLVL3__SHIFT 0xc +#define VPEC_MMHUB_TRUSTLVL__SECLVL4__SHIFT 0x10 +#define VPEC_MMHUB_TRUSTLVL__SECLVL5__SHIFT 0x14 +#define VPEC_MMHUB_TRUSTLVL__SECLVL6__SHIFT 0x18 +#define VPEC_MMHUB_TRUSTLVL__SECLVL7__SHIFT 0x1c +#define VPEC_MMHUB_TRUSTLVL__SECLVL0_MASK 0x0000000FL +#define VPEC_MMHUB_TRUSTLVL__SECLVL1_MASK 0x000000F0L +#define VPEC_MMHUB_TRUSTLVL__SECLVL2_MASK 0x00000F00L +#define VPEC_MMHUB_TRUSTLVL__SECLVL3_MASK 0x0000F000L +#define VPEC_MMHUB_TRUSTLVL__SECLVL4_MASK 0x000F0000L +#define VPEC_MMHUB_TRUSTLVL__SECLVL5_MASK 0x00F00000L +#define VPEC_MMHUB_TRUSTLVL__SECLVL6_MASK 0x0F000000L +#define VPEC_MMHUB_TRUSTLVL__SECLVL7_MASK 0xF0000000L +//VPEC_VPEP_CTRL +#define VPEC_VPEP_CTRL__VPEP_SOCCLK_EN__SHIFT 0x0 +#define VPEC_VPEP_CTRL__VPEP_SW_RESETB__SHIFT 0x1 +#define VPEC_VPEP_CTRL__RESERVED__SHIFT 0x2 +#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_VPEP_SOCCLK__SHIFT 0x1e +#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_VPECLK__SHIFT 0x1f +#define VPEC_VPEP_CTRL__VPEP_SOCCLK_EN_MASK 0x00000001L +#define VPEC_VPEP_CTRL__VPEP_SW_RESETB_MASK 0x00000002L +#define VPEC_VPEP_CTRL__RESERVED_MASK 0x3FFFFFFCL +#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_VPEP_SOCCLK_MASK 0x40000000L +#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_VPECLK_MASK 0x80000000L +//VPEC_CLK_CTRL +#define VPEC_CLK_CTRL__VPECLK_EN__SHIFT 0x1 +#define VPEC_CLK_CTRL__RESERVED__SHIFT 0x2 +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_IP_PIPE0_CLK__SHIFT 0x18 +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_IP_PIPE1_CLK__SHIFT 0x19 +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_OP_PIPE0_CLK__SHIFT 0x1a +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_PERF_CLK__SHIFT 0x1b +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_CE_CLK__SHIFT 0x1c +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_F32_CLK__SHIFT 0x1d +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_DYN_CLK__SHIFT 0x1e +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_REG_CLK__SHIFT 0x1f +#define VPEC_CLK_CTRL__VPECLK_EN_MASK 0x00000002L +#define VPEC_CLK_CTRL__RESERVED_MASK 0x00FFFFFCL +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_IP_PIPE0_CLK_MASK 0x01000000L +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_IP_PIPE1_CLK_MASK 0x02000000L +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_OP_PIPE0_CLK_MASK 0x04000000L +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_PERF_CLK_MASK 0x08000000L +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_CE_CLK_MASK 0x10000000L +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_F32_CLK_MASK 0x20000000L +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_DYN_CLK_MASK 0x40000000L +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_REG_CLK_MASK 0x80000000L +//VPEC_PG_CNTL +#define VPEC_PG_CNTL__PG_EN__SHIFT 0x0 +#define VPEC_PG_CNTL__PG_HYSTERESIS__SHIFT 0x1 +#define VPEC_PG_CNTL__PG_EN_MASK 0x00000001L +#define VPEC_PG_CNTL__PG_HYSTERESIS_MASK 0x0000003EL +//VPEC_POWER_CNTL +#define VPEC_POWER_CNTL__LS_ENABLE__SHIFT 0x8 +#define VPEC_POWER_CNTL__LS_ENABLE_MASK 0x00000100L +//VPEC_CNTL +#define VPEC_CNTL__TRAP_ENABLE__SHIFT 0x0 +#define VPEC_CNTL__RESERVED_2_2__SHIFT 0x2 +#define VPEC_CNTL__DATA_SWAP__SHIFT 0x3 +#define VPEC_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x5 +#define VPEC_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x6 +#define VPEC_CNTL__TMZ_MIDCMD_PREEMPT_ENABLE__SHIFT 0x8 +#define VPEC_CNTL__MIDCMD_EXPIRE_ENABLE__SHIFT 0x9 +#define VPEC_CNTL__UMSCH_INT_ENABLE__SHIFT 0xa +#define VPEC_CNTL__RESERVED_13_11__SHIFT 0xb +#define VPEC_CNTL__NACK_GEN_ERR_INT_ENABLE__SHIFT 0xe +#define VPEC_CNTL__NACK_PRT_INT_ENABLE__SHIFT 0xf +#define VPEC_CNTL__RESERVED_16_16__SHIFT 0x10 +#define VPEC_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11 +#define VPEC_CNTL__RESERVED_19_19__SHIFT 0x13 +#define VPEC_CNTL__ZSTATES_ENABLE__SHIFT 0x14 +#define VPEC_CNTL__ZSTATES_HYSTERESIS__SHIFT 0x15 +#define VPEC_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c +#define VPEC_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d +#define VPEC_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e +#define VPEC_CNTL__RB_PREEMPT_INT_ENABLE__SHIFT 0x1f +#define VPEC_CNTL__TRAP_ENABLE_MASK 0x00000001L +#define VPEC_CNTL__RESERVED_2_2_MASK 0x00000004L +#define VPEC_CNTL__DATA_SWAP_MASK 0x00000018L +#define VPEC_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000020L +#define VPEC_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000040L +#define VPEC_CNTL__TMZ_MIDCMD_PREEMPT_ENABLE_MASK 0x00000100L +#define VPEC_CNTL__MIDCMD_EXPIRE_ENABLE_MASK 0x00000200L +#define VPEC_CNTL__UMSCH_INT_ENABLE_MASK 0x00000400L +#define VPEC_CNTL__RESERVED_13_11_MASK 0x00003800L +#define VPEC_CNTL__NACK_GEN_ERR_INT_ENABLE_MASK 0x00004000L +#define VPEC_CNTL__NACK_PRT_INT_ENABLE_MASK 0x00008000L +#define VPEC_CNTL__RESERVED_16_16_MASK 0x00010000L +#define VPEC_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L +#define VPEC_CNTL__RESERVED_19_19_MASK 0x00080000L +#define VPEC_CNTL__ZSTATES_ENABLE_MASK 0x00100000L +#define VPEC_CNTL__ZSTATES_HYSTERESIS_MASK 0x03E00000L +#define VPEC_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L +#define VPEC_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L +#define VPEC_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L +#define VPEC_CNTL__RB_PREEMPT_INT_ENABLE_MASK 0x80000000L +//VPEC_CNTL1 +#define VPEC_CNTL1__RESERVED_3_1__SHIFT 0x1 +#define VPEC_CNTL1__SRBM_POLL_RETRYING__SHIFT 0x5 +#define VPEC_CNTL1__RESERVED_23_10__SHIFT 0xa +#define VPEC_CNTL1__CG_STATUS_OUTPUT__SHIFT 0x18 +#define VPEC_CNTL1__SW_FREEZE_ENABLE__SHIFT 0x19 +#define VPEC_CNTL1__VPEP_CONFIG_INVALID_CHECK_ENABLE__SHIFT 0x1a +#define VPEC_CNTL1__RESERVED__SHIFT 0x1b +#define VPEC_CNTL1__RESERVED_3_1_MASK 0x0000000EL +#define VPEC_CNTL1__SRBM_POLL_RETRYING_MASK 0x00000020L +#define VPEC_CNTL1__RESERVED_23_10_MASK 0x00FFFC00L +#define VPEC_CNTL1__CG_STATUS_OUTPUT_MASK 0x01000000L +#define VPEC_CNTL1__SW_FREEZE_ENABLE_MASK 0x02000000L +#define VPEC_CNTL1__VPEP_CONFIG_INVALID_CHECK_ENABLE_MASK 0x04000000L +#define VPEC_CNTL1__RESERVED_MASK 0xF8000000L +//VPEC_CNTL2 +#define VPEC_CNTL2__F32_CMD_PROC_DELAY__SHIFT 0x0 +#define VPEC_CNTL2__F32_SEND_POSTCODE_EN__SHIFT 0x4 +#define VPEC_CNTL2__UCODE_BUF_DS_EN__SHIFT 0x6 +#define VPEC_CNTL2__UCODE_SELFLOAD_THREAD_OVERLAP__SHIFT 0x7 +#define VPEC_CNTL2__RESERVED_11_8__SHIFT 0x8 +#define VPEC_CNTL2__RESERVED_14_12__SHIFT 0xc +#define VPEC_CNTL2__RESERVED_15__SHIFT 0xf +#define VPEC_CNTL2__RB_FIFO_WATERMARK__SHIFT 0x10 +#define VPEC_CNTL2__IB_FIFO_WATERMARK__SHIFT 0x12 +#define VPEC_CNTL2__RESERVED_22_20__SHIFT 0x14 +#define VPEC_CNTL2__CH_RD_WATERMARK__SHIFT 0x17 +#define VPEC_CNTL2__CH_WR_WATERMARK__SHIFT 0x19 +#define VPEC_CNTL2__CH_WR_WATERMARK_LSB__SHIFT 0x1e +#define VPEC_CNTL2__F32_CMD_PROC_DELAY_MASK 0x0000000FL +#define VPEC_CNTL2__F32_SEND_POSTCODE_EN_MASK 0x00000010L +#define VPEC_CNTL2__UCODE_BUF_DS_EN_MASK 0x00000040L +#define VPEC_CNTL2__UCODE_SELFLOAD_THREAD_OVERLAP_MASK 0x00000080L +#define VPEC_CNTL2__RESERVED_11_8_MASK 0x00000F00L +#define VPEC_CNTL2__RESERVED_14_12_MASK 0x00007000L +#define VPEC_CNTL2__RESERVED_15_MASK 0x00008000L +#define VPEC_CNTL2__RB_FIFO_WATERMARK_MASK 0x00030000L +#define VPEC_CNTL2__IB_FIFO_WATERMARK_MASK 0x000C0000L +#define VPEC_CNTL2__RESERVED_22_20_MASK 0x00700000L +#define VPEC_CNTL2__CH_RD_WATERMARK_MASK 0x01800000L +#define VPEC_CNTL2__CH_WR_WATERMARK_MASK 0x3E000000L +#define VPEC_CNTL2__CH_WR_WATERMARK_LSB_MASK 0x40000000L +//VPEC_GB_ADDR_CONFIG +#define VPEC_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define VPEC_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 +#define VPEC_GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0x6 +#define VPEC_GB_ADDR_CONFIG__NUM_PKRS__SHIFT 0x8 +#define VPEC_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 +#define VPEC_GB_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT 0x1a +#define VPEC_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define VPEC_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L +#define VPEC_GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L +#define VPEC_GB_ADDR_CONFIG__NUM_PKRS_MASK 0x00000700L +#define VPEC_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L +#define VPEC_GB_ADDR_CONFIG__NUM_RB_PER_SE_MASK 0x0C000000L +//VPEC_GB_ADDR_CONFIG_READ +#define VPEC_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0 +#define VPEC_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 +#define VPEC_GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS__SHIFT 0x6 +#define VPEC_GB_ADDR_CONFIG_READ__NUM_PKRS__SHIFT 0x8 +#define VPEC_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13 +#define VPEC_GB_ADDR_CONFIG_READ__NUM_RB_PER_SE__SHIFT 0x1a +#define VPEC_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L +#define VPEC_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L +#define VPEC_GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L +#define VPEC_GB_ADDR_CONFIG_READ__NUM_PKRS_MASK 0x00000700L +#define VPEC_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L +#define VPEC_GB_ADDR_CONFIG_READ__NUM_RB_PER_SE_MASK 0x0C000000L +//VPEC_PROCESS_QUANTUM0 +#define VPEC_PROCESS_QUANTUM0__PROCESS0_QUANTUM__SHIFT 0x0 +#define VPEC_PROCESS_QUANTUM0__PROCESS1_QUANTUM__SHIFT 0x8 +#define VPEC_PROCESS_QUANTUM0__PROCESS2_QUANTUM__SHIFT 0x10 +#define VPEC_PROCESS_QUANTUM0__PROCESS3_QUANTUM__SHIFT 0x18 +#define VPEC_PROCESS_QUANTUM0__PROCESS0_QUANTUM_MASK 0x000000FFL +#define VPEC_PROCESS_QUANTUM0__PROCESS1_QUANTUM_MASK 0x0000FF00L +#define VPEC_PROCESS_QUANTUM0__PROCESS2_QUANTUM_MASK 0x00FF0000L +#define VPEC_PROCESS_QUANTUM0__PROCESS3_QUANTUM_MASK 0xFF000000L +//VPEC_PROCESS_QUANTUM1 +#define VPEC_PROCESS_QUANTUM1__PROCESS4_QUANTUM__SHIFT 0x0 +#define VPEC_PROCESS_QUANTUM1__PROCESS5_QUANTUM__SHIFT 0x8 +#define VPEC_PROCESS_QUANTUM1__PROCESS6_QUANTUM__SHIFT 0x10 +#define VPEC_PROCESS_QUANTUM1__PROCESS7_QUANTUM__SHIFT 0x18 +#define VPEC_PROCESS_QUANTUM1__PROCESS4_QUANTUM_MASK 0x000000FFL +#define VPEC_PROCESS_QUANTUM1__PROCESS5_QUANTUM_MASK 0x0000FF00L +#define VPEC_PROCESS_QUANTUM1__PROCESS6_QUANTUM_MASK 0x00FF0000L +#define VPEC_PROCESS_QUANTUM1__PROCESS7_QUANTUM_MASK 0xFF000000L +//VPEC_CONTEXT_SWITCH_THRESHOLD +#define VPEC_CONTEXT_SWITCH_THRESHOLD__REALTIME_THRESHOLD__SHIFT 0x0 +#define VPEC_CONTEXT_SWITCH_THRESHOLD__FOCUS_THRESHOLD__SHIFT 0x2 +#define VPEC_CONTEXT_SWITCH_THRESHOLD__NORMAL_THRESHOLD__SHIFT 0x4 +#define VPEC_CONTEXT_SWITCH_THRESHOLD__IDLE_THRESHOLD__SHIFT 0x6 +#define VPEC_CONTEXT_SWITCH_THRESHOLD__REALTIME_THRESHOLD_MASK 0x00000003L +#define VPEC_CONTEXT_SWITCH_THRESHOLD__FOCUS_THRESHOLD_MASK 0x0000000CL +#define VPEC_CONTEXT_SWITCH_THRESHOLD__NORMAL_THRESHOLD_MASK 0x00000030L +#define VPEC_CONTEXT_SWITCH_THRESHOLD__IDLE_THRESHOLD_MASK 0x000000C0L +//VPEC_GLOBAL_QUANTUM +#define VPEC_GLOBAL_QUANTUM__GLOBAL_FOCUS_QUANTUM__SHIFT 0x0 +#define VPEC_GLOBAL_QUANTUM__GLOBAL_NORMAL_QUANTUM__SHIFT 0x8 +#define VPEC_GLOBAL_QUANTUM__GLOBAL_FOCUS_QUANTUM_MASK 0x000000FFL +#define VPEC_GLOBAL_QUANTUM__GLOBAL_NORMAL_QUANTUM_MASK 0x0000FF00L +//VPEC_WATCHDOG_CNTL +#define VPEC_WATCHDOG_CNTL__QUEUE_HANG_COUNT__SHIFT 0x0 +#define VPEC_WATCHDOG_CNTL__CMD_TIMEOUT_COUNT__SHIFT 0x8 +#define VPEC_WATCHDOG_CNTL__QUEUE_HANG_COUNT_MASK 0x000000FFL +#define VPEC_WATCHDOG_CNTL__CMD_TIMEOUT_COUNT_MASK 0x0000FF00L +//VPEC_ATOMIC_CNTL +#define VPEC_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0 +#define VPEC_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f +#define VPEC_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL +#define VPEC_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L +//VPEC_UCODE_VERSION +#define VPEC_UCODE_VERSION__T0_UCODE_VERSION__SHIFT 0x0 +#define VPEC_UCODE_VERSION__T1_UCODE_VERSION__SHIFT 0x10 +#define VPEC_UCODE_VERSION__T0_UCODE_VERSION_MASK 0x0000FFFFL +#define VPEC_UCODE_VERSION__T1_UCODE_VERSION_MASK 0xFFFF0000L +//VPEC_MEMREQ_BURST_CNTL +#define VPEC_MEMREQ_BURST_CNTL__DATA_RD_BURST__SHIFT 0x0 +#define VPEC_MEMREQ_BURST_CNTL__DATA_WR_BURST__SHIFT 0x2 +#define VPEC_MEMREQ_BURST_CNTL__RB_RD_BURST__SHIFT 0x4 +#define VPEC_MEMREQ_BURST_CNTL__IB_RD_BURST__SHIFT 0x6 +#define VPEC_MEMREQ_BURST_CNTL__WR_BURST_WAIT_CYCLE__SHIFT 0x8 +#define VPEC_MEMREQ_BURST_CNTL__DATA_RD_BURST_MASK 0x00000003L +#define VPEC_MEMREQ_BURST_CNTL__DATA_WR_BURST_MASK 0x0000000CL +#define VPEC_MEMREQ_BURST_CNTL__RB_RD_BURST_MASK 0x00000030L +#define VPEC_MEMREQ_BURST_CNTL__IB_RD_BURST_MASK 0x000000C0L +#define VPEC_MEMREQ_BURST_CNTL__WR_BURST_WAIT_CYCLE_MASK 0x00000700L +//VPEC_TIMESTAMP_CNTL +#define VPEC_TIMESTAMP_CNTL__CAPTURE__SHIFT 0x0 +#define VPEC_TIMESTAMP_CNTL__CAPTURE_MASK 0x00000001L +//VPEC_GLOBAL_TIMESTAMP_LO +#define VPEC_GLOBAL_TIMESTAMP_LO__DATA__SHIFT 0x0 +#define VPEC_GLOBAL_TIMESTAMP_LO__DATA_MASK 0xFFFFFFFFL +//VPEC_GLOBAL_TIMESTAMP_HI +#define VPEC_GLOBAL_TIMESTAMP_HI__DATA__SHIFT 0x0 +#define VPEC_GLOBAL_TIMESTAMP_HI__DATA_MASK 0xFFFFFFFFL +//VPEC_FREEZE +#define VPEC_FREEZE__PREEMPT__SHIFT 0x0 +#define VPEC_FREEZE__FREEZE__SHIFT 0x4 +#define VPEC_FREEZE__FROZEN__SHIFT 0x5 +#define VPEC_FREEZE__F32_FREEZE__SHIFT 0x6 +#define VPEC_FREEZE__PREEMPT_MASK 0x00000001L +#define VPEC_FREEZE__FREEZE_MASK 0x00000010L +#define VPEC_FREEZE__FROZEN_MASK 0x00000020L +#define VPEC_FREEZE__F32_FREEZE_MASK 0x00000040L +//VPEC_CE_CTRL +#define VPEC_CE_CTRL__RD_LUT_WATERMARK__SHIFT 0x0 +#define VPEC_CE_CTRL__RD_LUT_DEPTH__SHIFT 0x3 +#define VPEC_CE_CTRL__WR_AFIFO_WATERMARK__SHIFT 0x5 +#define VPEC_CE_CTRL__RESERVED__SHIFT 0x8 +#define VPEC_CE_CTRL__RD_LUT_WATERMARK_MASK 0x00000007L +#define VPEC_CE_CTRL__RD_LUT_DEPTH_MASK 0x00000018L +#define VPEC_CE_CTRL__WR_AFIFO_WATERMARK_MASK 0x000000E0L +#define VPEC_CE_CTRL__RESERVED_MASK 0xFFFFFF00L +//VPEC_RELAX_ORDERING_LUT +#define VPEC_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0 +#define VPEC_RELAX_ORDERING_LUT__VPE__SHIFT 0x1 +#define VPEC_RELAX_ORDERING_LUT__RESERVED_2_2__SHIFT 0x2 +#define VPEC_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3 +#define VPEC_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4 +#define VPEC_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5 +#define VPEC_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6 +#define VPEC_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8 +#define VPEC_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9 +#define VPEC_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa +#define VPEC_RELAX_ORDERING_LUT__RESERVED_11_11__SHIFT 0xb +#define VPEC_RELAX_ORDERING_LUT__RESERVED_12_12__SHIFT 0xc +#define VPEC_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd +#define VPEC_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe +#define VPEC_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b +#define VPEC_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c +#define VPEC_RELAX_ORDERING_LUT__RESERVED_29_29__SHIFT 0x1d +#define VPEC_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e +#define VPEC_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f +#define VPEC_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L +#define VPEC_RELAX_ORDERING_LUT__VPE_MASK 0x00000002L +#define VPEC_RELAX_ORDERING_LUT__RESERVED_2_2_MASK 0x00000004L +#define VPEC_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L +#define VPEC_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L +#define VPEC_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L +#define VPEC_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L +#define VPEC_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L +#define VPEC_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L +#define VPEC_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L +#define VPEC_RELAX_ORDERING_LUT__RESERVED_11_11_MASK 0x00000800L +#define VPEC_RELAX_ORDERING_LUT__RESERVED_12_12_MASK 0x00001000L +#define VPEC_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L +#define VPEC_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L +#define VPEC_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L +#define VPEC_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L +#define VPEC_RELAX_ORDERING_LUT__RESERVED_29_29_MASK 0x20000000L +#define VPEC_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L +#define VPEC_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L +//VPEC_CREDIT_CNTL +#define VPEC_CREDIT_CNTL__DRM_CREDIT__SHIFT 0x0 +#define VPEC_CREDIT_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7 +#define VPEC_CREDIT_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd +#define VPEC_CREDIT_CNTL__DRM_CREDIT_MASK 0x0000007FL +#define VPEC_CREDIT_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L +#define VPEC_CREDIT_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L +//VPEC_SCRATCH_RAM_DATA +#define VPEC_SCRATCH_RAM_DATA__DATA__SHIFT 0x0 +#define VPEC_SCRATCH_RAM_DATA__DATA_MASK 0xFFFFFFFFL +//VPEC_SCRATCH_RAM_ADDR +#define VPEC_SCRATCH_RAM_ADDR__ADDR__SHIFT 0x0 +#define VPEC_SCRATCH_RAM_ADDR__ADDR_MASK 0x0000007FL +//VPEC_QUEUE_RESET_REQ +#define VPEC_QUEUE_RESET_REQ__QUEUE0_RESET__SHIFT 0x0 +#define VPEC_QUEUE_RESET_REQ__QUEUE1_RESET__SHIFT 0x1 +#define VPEC_QUEUE_RESET_REQ__QUEUE2_RESET__SHIFT 0x2 +#define VPEC_QUEUE_RESET_REQ__QUEUE3_RESET__SHIFT 0x3 +#define VPEC_QUEUE_RESET_REQ__QUEUE4_RESET__SHIFT 0x4 +#define VPEC_QUEUE_RESET_REQ__QUEUE5_RESET__SHIFT 0x5 +#define VPEC_QUEUE_RESET_REQ__QUEUE6_RESET__SHIFT 0x6 +#define VPEC_QUEUE_RESET_REQ__QUEUE7_RESET__SHIFT 0x7 +#define VPEC_QUEUE_RESET_REQ__RESERVED__SHIFT 0x8 +#define VPEC_QUEUE_RESET_REQ__QUEUE0_RESET_MASK 0x00000001L +#define VPEC_QUEUE_RESET_REQ__QUEUE1_RESET_MASK 0x00000002L +#define VPEC_QUEUE_RESET_REQ__QUEUE2_RESET_MASK 0x00000004L +#define VPEC_QUEUE_RESET_REQ__QUEUE3_RESET_MASK 0x00000008L +#define VPEC_QUEUE_RESET_REQ__QUEUE4_RESET_MASK 0x00000010L +#define VPEC_QUEUE_RESET_REQ__QUEUE5_RESET_MASK 0x00000020L +#define VPEC_QUEUE_RESET_REQ__QUEUE6_RESET_MASK 0x00000040L +#define VPEC_QUEUE_RESET_REQ__QUEUE7_RESET_MASK 0x00000080L +#define VPEC_QUEUE_RESET_REQ__RESERVED_MASK 0xFFFFFF00L +//VPEC_PERFCNT_PERFCOUNTER0_CFG +#define VPEC_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define VPEC_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define VPEC_PERFCNT_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define VPEC_PERFCNT_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define VPEC_PERFCNT_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define VPEC_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define VPEC_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define VPEC_PERFCNT_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define VPEC_PERFCNT_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define VPEC_PERFCNT_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//VPEC_PERFCNT_PERFCOUNTER1_CFG +#define VPEC_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define VPEC_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define VPEC_PERFCNT_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define VPEC_PERFCNT_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define VPEC_PERFCNT_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define VPEC_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define VPEC_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define VPEC_PERFCNT_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define VPEC_PERFCNT_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define VPEC_PERFCNT_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//VPEC_PERFCNT_PERFCOUNTER_RSLT_CNTL +#define VPEC_PERFCNT_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define VPEC_PERFCNT_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define VPEC_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define VPEC_PERFCNT_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define VPEC_PERFCNT_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define VPEC_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define VPEC_PERFCNT_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define VPEC_PERFCNT_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define VPEC_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define VPEC_PERFCNT_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define VPEC_PERFCNT_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define VPEC_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L +//VPEC_PERFCNT_MISC_CNTL +#define VPEC_PERFCNT_MISC_CNTL__CMD_OP__SHIFT 0x0 +#define VPEC_PERFCNT_MISC_CNTL__MMHUB_REQ_EVENT_SELECT__SHIFT 0x10 +#define VPEC_PERFCNT_MISC_CNTL__CMD_OP_MASK 0x0000FFFFL +#define VPEC_PERFCNT_MISC_CNTL__MMHUB_REQ_EVENT_SELECT_MASK 0x00010000L +//VPEC_PERFCNT_PERFCOUNTER_LO +#define VPEC_PERFCNT_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define VPEC_PERFCNT_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//VPEC_PERFCNT_PERFCOUNTER_HI +#define VPEC_PERFCNT_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define VPEC_PERFCNT_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define VPEC_PERFCNT_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define VPEC_PERFCNT_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L +//VPEC_DEBUG_INDEX +#define VPEC_DEBUG_INDEX__INDEX__SHIFT 0x0 +#define VPEC_DEBUG_INDEX__INDEX_MASK 0xFFFFFFFFL +//VPEC_DEBUG_DATA +#define VPEC_DEBUG_DATA__DATA__SHIFT 0x0 +#define VPEC_DEBUG_DATA__DATA_MASK 0xFFFFFFFFL +//VPEC_CRC_CTRL +#define VPEC_CRC_CTRL__INDEX__SHIFT 0x0 +#define VPEC_CRC_CTRL__START__SHIFT 0x1f +#define VPEC_CRC_CTRL__INDEX_MASK 0x0000FFFFL +#define VPEC_CRC_CTRL__START_MASK 0x80000000L +//VPEC_CRC_DATA +#define VPEC_CRC_DATA__DATA__SHIFT 0x0 +#define VPEC_CRC_DATA__DATA_MASK 0xFFFFFFFFL +//VPEC_PUB_DUMMY0 +#define VPEC_PUB_DUMMY0__VALUE__SHIFT 0x0 +#define VPEC_PUB_DUMMY0__VALUE_MASK 0xFFFFFFFFL +//VPEC_PUB_DUMMY1 +#define VPEC_PUB_DUMMY1__VALUE__SHIFT 0x0 +#define VPEC_PUB_DUMMY1__VALUE_MASK 0xFFFFFFFFL +//VPEC_PUB_DUMMY2 +#define VPEC_PUB_DUMMY2__VALUE__SHIFT 0x0 +#define VPEC_PUB_DUMMY2__VALUE_MASK 0xFFFFFFFFL +//VPEC_PUB_DUMMY3 +#define VPEC_PUB_DUMMY3__VALUE__SHIFT 0x0 +#define VPEC_PUB_DUMMY3__VALUE_MASK 0xFFFFFFFFL +//VPEC_PUB_DUMMY4 +#define VPEC_PUB_DUMMY4__VALUE__SHIFT 0x0 +#define VPEC_PUB_DUMMY4__VALUE_MASK 0xFFFFFFFFL +//VPEC_PUB_DUMMY5 +#define VPEC_PUB_DUMMY5__VALUE__SHIFT 0x0 +#define VPEC_PUB_DUMMY5__VALUE_MASK 0xFFFFFFFFL +//VPEC_PUB_DUMMY6 +#define VPEC_PUB_DUMMY6__VALUE__SHIFT 0x0 +#define VPEC_PUB_DUMMY6__VALUE_MASK 0xFFFFFFFFL +//VPEC_PUB_DUMMY7 +#define VPEC_PUB_DUMMY7__VALUE__SHIFT 0x0 +#define VPEC_PUB_DUMMY7__VALUE_MASK 0xFFFFFFFFL +//VPEC_UCODE1_CHECKSUM +#define VPEC_UCODE1_CHECKSUM__DATA__SHIFT 0x0 +#define VPEC_UCODE1_CHECKSUM__DATA_MASK 0xFFFFFFFFL +//VPEC_VERSION +#define VPEC_VERSION__MINVER__SHIFT 0x0 +#define VPEC_VERSION__MAJVER__SHIFT 0x8 +#define VPEC_VERSION__REV__SHIFT 0x10 +#define VPEC_VERSION__MINVER_MASK 0x0000007FL +#define VPEC_VERSION__MAJVER_MASK 0x00007F00L +#define VPEC_VERSION__REV_MASK 0x003F0000L +//VPEC_UCODE_CHECKSUM +#define VPEC_UCODE_CHECKSUM__DATA__SHIFT 0x0 +#define VPEC_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL +//VPEC_CLOCK_GATING_STATUS +#define VPEC_CLOCK_GATING_STATUS__DYN_CLK_GATE_STATUS__SHIFT 0x0 +#define VPEC_CLOCK_GATING_STATUS__IP_PIPE0_CLK_GATE_STATUS__SHIFT 0x2 +#define VPEC_CLOCK_GATING_STATUS__IP_PIPE1_CLK_GATE_STATUS__SHIFT 0x3 +#define VPEC_CLOCK_GATING_STATUS__OP_PIPE0_CLK_GATE_STATUS__SHIFT 0x4 +#define VPEC_CLOCK_GATING_STATUS__REG_CLK_GATE_STATUS__SHIFT 0x5 +#define VPEC_CLOCK_GATING_STATUS__F32_CLK_GATE_STATUS__SHIFT 0x6 +#define VPEC_CLOCK_GATING_STATUS__DYN_CLK_GATE_STATUS_MASK 0x00000001L +#define VPEC_CLOCK_GATING_STATUS__IP_PIPE0_CLK_GATE_STATUS_MASK 0x00000004L +#define VPEC_CLOCK_GATING_STATUS__IP_PIPE1_CLK_GATE_STATUS_MASK 0x00000008L +#define VPEC_CLOCK_GATING_STATUS__OP_PIPE0_CLK_GATE_STATUS_MASK 0x00000010L +#define VPEC_CLOCK_GATING_STATUS__REG_CLK_GATE_STATUS_MASK 0x00000020L +#define VPEC_CLOCK_GATING_STATUS__F32_CLK_GATE_STATUS_MASK 0x00000040L +//VPEC_RB_RPTR_FETCH +#define VPEC_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 +#define VPEC_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL +//VPEC_RB_RPTR_FETCH_HI +#define VPEC_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0 +#define VPEC_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL +//VPEC_IB_OFFSET_FETCH +#define VPEC_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 +#define VPEC_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL +//VPEC_CMDIB_OFFSET_FETCH +#define VPEC_CMDIB_OFFSET_FETCH__OFFSET__SHIFT 0x2 +#define VPEC_CMDIB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL +//VPEC_ATOMIC_PREOP_LO +#define VPEC_ATOMIC_PREOP_LO__DATA__SHIFT 0x0 +#define VPEC_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL +//VPEC_ATOMIC_PREOP_HI +#define VPEC_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 +#define VPEC_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL +//VPEC_CE_BUSY +#define VPEC_CE_BUSY__CE_IP_PIPE0_BUSY__SHIFT 0x0 +#define VPEC_CE_BUSY__CE_IP_PIPE1_BUSY__SHIFT 0x1 +#define VPEC_CE_BUSY__CE_OP_PIPE0_BUSY__SHIFT 0x10 +#define VPEC_CE_BUSY__CE_IP_PIPE0_BUSY_MASK 0x00000001L +#define VPEC_CE_BUSY__CE_IP_PIPE1_BUSY_MASK 0x00000002L +#define VPEC_CE_BUSY__CE_OP_PIPE0_BUSY_MASK 0x00010000L +//VPEC_F32_COUNTER +#define VPEC_F32_COUNTER__VALUE__SHIFT 0x0 +#define VPEC_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL +//VPEC_HOLE_ADDR_LO +#define VPEC_HOLE_ADDR_LO__VALUE__SHIFT 0x0 +#define VPEC_HOLE_ADDR_LO__VALUE_MASK 0xFFFFFFFFL +//VPEC_HOLE_ADDR_HI +#define VPEC_HOLE_ADDR_HI__VALUE__SHIFT 0x0 +#define VPEC_HOLE_ADDR_HI__VALUE_MASK 0xFFFFFFFFL +//VPEC_ERROR_LOG +#define VPEC_ERROR_LOG__OVERRIDE__SHIFT 0x0 +#define VPEC_ERROR_LOG__STATUS__SHIFT 0x10 +#define VPEC_ERROR_LOG__OVERRIDE_MASK 0x0000FFFFL +#define VPEC_ERROR_LOG__STATUS_MASK 0xFFFF0000L +//VPEC_INT_STATUS +#define VPEC_INT_STATUS__DATA__SHIFT 0x0 +#define VPEC_INT_STATUS__DATA_MASK 0xFFFFFFFFL +//VPEC_STATUS +#define VPEC_STATUS__IDLE__SHIFT 0x0 +#define VPEC_STATUS__REG_IDLE__SHIFT 0x1 +#define VPEC_STATUS__RB_EMPTY__SHIFT 0x2 +#define VPEC_STATUS__RB_FULL__SHIFT 0x3 +#define VPEC_STATUS__RB_CMD_IDLE__SHIFT 0x4 +#define VPEC_STATUS__RB_CMD_FULL__SHIFT 0x5 +#define VPEC_STATUS__IB_CMD_IDLE__SHIFT 0x6 +#define VPEC_STATUS__IB_CMD_FULL__SHIFT 0x7 +#define VPEC_STATUS__BLOCK_IDLE__SHIFT 0x8 +#define VPEC_STATUS__INSIDE_VPEP_CONFIG__SHIFT 0x9 +#define VPEC_STATUS__EX_IDLE__SHIFT 0xa +#define VPEC_STATUS__RESERVED_11_11__SHIFT 0xb +#define VPEC_STATUS__PACKET_READY__SHIFT 0xc +#define VPEC_STATUS__MC_WR_IDLE__SHIFT 0xd +#define VPEC_STATUS__SRBM_IDLE__SHIFT 0xe +#define VPEC_STATUS__CONTEXT_EMPTY__SHIFT 0xf +#define VPEC_STATUS__INSIDE_IB__SHIFT 0x10 +#define VPEC_STATUS__RB_MC_RREQ_IDLE__SHIFT 0x11 +#define VPEC_STATUS__IB_MC_RREQ_IDLE__SHIFT 0x12 +#define VPEC_STATUS__MC_RD_IDLE__SHIFT 0x13 +#define VPEC_STATUS__DELTA_RPTR_EMPTY__SHIFT 0x14 +#define VPEC_STATUS__MC_RD_RET_STALL__SHIFT 0x15 +#define VPEC_STATUS__RESERVED_22_22__SHIFT 0x16 +#define VPEC_STATUS__RESERVED_23_23__SHIFT 0x17 +#define VPEC_STATUS__RESERVED_24_24__SHIFT 0x18 +#define VPEC_STATUS__PREV_CMD_IDLE__SHIFT 0x19 +#define VPEC_STATUS__RESERVED_26_26__SHIFT 0x1a +#define VPEC_STATUS__RESERVED_27_27__SHIFT 0x1b +#define VPEC_STATUS__RESERVED_29_28__SHIFT 0x1c +#define VPEC_STATUS__INT_IDLE__SHIFT 0x1e +#define VPEC_STATUS__INT_REQ_STALL__SHIFT 0x1f +#define VPEC_STATUS__IDLE_MASK 0x00000001L +#define VPEC_STATUS__REG_IDLE_MASK 0x00000002L +#define VPEC_STATUS__RB_EMPTY_MASK 0x00000004L +#define VPEC_STATUS__RB_FULL_MASK 0x00000008L +#define VPEC_STATUS__RB_CMD_IDLE_MASK 0x00000010L +#define VPEC_STATUS__RB_CMD_FULL_MASK 0x00000020L +#define VPEC_STATUS__IB_CMD_IDLE_MASK 0x00000040L +#define VPEC_STATUS__IB_CMD_FULL_MASK 0x00000080L +#define VPEC_STATUS__BLOCK_IDLE_MASK 0x00000100L +#define VPEC_STATUS__INSIDE_VPEP_CONFIG_MASK 0x00000200L +#define VPEC_STATUS__EX_IDLE_MASK 0x00000400L +#define VPEC_STATUS__RESERVED_11_11_MASK 0x00000800L +#define VPEC_STATUS__PACKET_READY_MASK 0x00001000L +#define VPEC_STATUS__MC_WR_IDLE_MASK 0x00002000L +#define VPEC_STATUS__SRBM_IDLE_MASK 0x00004000L +#define VPEC_STATUS__CONTEXT_EMPTY_MASK 0x00008000L +#define VPEC_STATUS__INSIDE_IB_MASK 0x00010000L +#define VPEC_STATUS__RB_MC_RREQ_IDLE_MASK 0x00020000L +#define VPEC_STATUS__IB_MC_RREQ_IDLE_MASK 0x00040000L +#define VPEC_STATUS__MC_RD_IDLE_MASK 0x00080000L +#define VPEC_STATUS__DELTA_RPTR_EMPTY_MASK 0x00100000L +#define VPEC_STATUS__MC_RD_RET_STALL_MASK 0x00200000L +#define VPEC_STATUS__RESERVED_22_22_MASK 0x00400000L +#define VPEC_STATUS__RESERVED_23_23_MASK 0x00800000L +#define VPEC_STATUS__RESERVED_24_24_MASK 0x01000000L +#define VPEC_STATUS__PREV_CMD_IDLE_MASK 0x02000000L +#define VPEC_STATUS__RESERVED_26_26_MASK 0x04000000L +#define VPEC_STATUS__RESERVED_27_27_MASK 0x08000000L +#define VPEC_STATUS__RESERVED_29_28_MASK 0x30000000L +#define VPEC_STATUS__INT_IDLE_MASK 0x40000000L +#define VPEC_STATUS__INT_REQ_STALL_MASK 0x80000000L +//VPEC_STATUS1 +#define VPEC_STATUS1__CE_IP0_WREQ_IDLE__SHIFT 0x0 +#define VPEC_STATUS1__CE_IP0_WR_IDLE__SHIFT 0x1 +#define VPEC_STATUS1__CE_IP0_SPLIT_IDLE__SHIFT 0x2 +#define VPEC_STATUS1__CE_IP0_RREQ_IDLE__SHIFT 0x3 +#define VPEC_STATUS1__CE_IP0_OUT_IDLE__SHIFT 0x4 +#define VPEC_STATUS1__CE_IP0_IN_IDLE__SHIFT 0x5 +#define VPEC_STATUS1__CE_IP0_DST_IDLE__SHIFT 0x6 +#define VPEC_STATUS1__CE_IP0_CMD_IDLE__SHIFT 0x7 +#define VPEC_STATUS1__CE_IP1_WREQ_IDLE__SHIFT 0x8 +#define VPEC_STATUS1__CE_IP1_WR_IDLE__SHIFT 0x9 +#define VPEC_STATUS1__CE_IP1_SPLIT_IDLE__SHIFT 0xa +#define VPEC_STATUS1__CE_IP1_RREQ_IDLE__SHIFT 0xb +#define VPEC_STATUS1__CE_IP1_OUT_IDLE__SHIFT 0xc +#define VPEC_STATUS1__CE_IP1_IN_IDLE__SHIFT 0xd +#define VPEC_STATUS1__CE_IP1_DST_IDLE__SHIFT 0xe +#define VPEC_STATUS1__CE_IP1_CMD_IDLE__SHIFT 0xf +#define VPEC_STATUS1__CE_OP0_WR_IDLE__SHIFT 0x10 +#define VPEC_STATUS1__CE_OP0_CMD_IDLE__SHIFT 0x11 +#define VPEC_STATUS1__CE_IP0_AFIFO_FULL__SHIFT 0x12 +#define VPEC_STATUS1__CE_IP0_CMD_INFO_FULL__SHIFT 0x13 +#define VPEC_STATUS1__CE_IP0_CMD_INFO1_FULL__SHIFT 0x14 +#define VPEC_STATUS1__CE_IP1_AFIFO_FULL__SHIFT 0x15 +#define VPEC_STATUS1__CE_IP1_CMD_INFO_FULL__SHIFT 0x16 +#define VPEC_STATUS1__CE_IP1_CMD_INFO1_FULL__SHIFT 0x17 +#define VPEC_STATUS1__EX_START__SHIFT 0x18 +#define VPEC_STATUS1__CE_RD_STALL__SHIFT 0x19 +#define VPEC_STATUS1__CE_IP0_WR_STALL__SHIFT 0x1a +#define VPEC_STATUS1__CE_IP1_WR_STALL__SHIFT 0x1b +#define VPEC_STATUS1__RESERVED_28_28__SHIFT 0x1c +#define VPEC_STATUS1__VPEC_IDLE__SHIFT 0x1d +#define VPEC_STATUS1__PG_STATUS__SHIFT 0x1e +#define VPEC_STATUS1__CE_IP0_WREQ_IDLE_MASK 0x00000001L +#define VPEC_STATUS1__CE_IP0_WR_IDLE_MASK 0x00000002L +#define VPEC_STATUS1__CE_IP0_SPLIT_IDLE_MASK 0x00000004L +#define VPEC_STATUS1__CE_IP0_RREQ_IDLE_MASK 0x00000008L +#define VPEC_STATUS1__CE_IP0_OUT_IDLE_MASK 0x00000010L +#define VPEC_STATUS1__CE_IP0_IN_IDLE_MASK 0x00000020L +#define VPEC_STATUS1__CE_IP0_DST_IDLE_MASK 0x00000040L +#define VPEC_STATUS1__CE_IP0_CMD_IDLE_MASK 0x00000080L +#define VPEC_STATUS1__CE_IP1_WREQ_IDLE_MASK 0x00000100L +#define VPEC_STATUS1__CE_IP1_WR_IDLE_MASK 0x00000200L +#define VPEC_STATUS1__CE_IP1_SPLIT_IDLE_MASK 0x00000400L +#define VPEC_STATUS1__CE_IP1_RREQ_IDLE_MASK 0x00000800L +#define VPEC_STATUS1__CE_IP1_OUT_IDLE_MASK 0x00001000L +#define VPEC_STATUS1__CE_IP1_IN_IDLE_MASK 0x00002000L +#define VPEC_STATUS1__CE_IP1_DST_IDLE_MASK 0x00004000L +#define VPEC_STATUS1__CE_IP1_CMD_IDLE_MASK 0x00008000L +#define VPEC_STATUS1__CE_OP0_WR_IDLE_MASK 0x00010000L +#define VPEC_STATUS1__CE_OP0_CMD_IDLE_MASK 0x00020000L +#define VPEC_STATUS1__CE_IP0_AFIFO_FULL_MASK 0x00040000L +#define VPEC_STATUS1__CE_IP0_CMD_INFO_FULL_MASK 0x00080000L +#define VPEC_STATUS1__CE_IP0_CMD_INFO1_FULL_MASK 0x00100000L +#define VPEC_STATUS1__CE_IP1_AFIFO_FULL_MASK 0x00200000L +#define VPEC_STATUS1__CE_IP1_CMD_INFO_FULL_MASK 0x00400000L +#define VPEC_STATUS1__CE_IP1_CMD_INFO1_FULL_MASK 0x00800000L +#define VPEC_STATUS1__EX_START_MASK 0x01000000L +#define VPEC_STATUS1__CE_RD_STALL_MASK 0x02000000L +#define VPEC_STATUS1__CE_IP0_WR_STALL_MASK 0x04000000L +#define VPEC_STATUS1__CE_IP1_WR_STALL_MASK 0x08000000L +#define VPEC_STATUS1__RESERVED_28_28_MASK 0x10000000L +#define VPEC_STATUS1__VPEC_IDLE_MASK 0x20000000L +#define VPEC_STATUS1__PG_STATUS_MASK 0xC0000000L +//VPEC_STATUS2 +#define VPEC_STATUS2__ID__SHIFT 0x0 +#define VPEC_STATUS2__TH0F32_INSTR_PTR__SHIFT 0x2 +#define VPEC_STATUS2__CMD_OP__SHIFT 0x10 +#define VPEC_STATUS2__ID_MASK 0x00000003L +#define VPEC_STATUS2__TH0F32_INSTR_PTR_MASK 0x0000FFFCL +#define VPEC_STATUS2__CMD_OP_MASK 0xFFFF0000L +//VPEC_STATUS3 +#define VPEC_STATUS3__CMD_OP_STATUS__SHIFT 0x0 +#define VPEC_STATUS3__RESERVED_19_16__SHIFT 0x10 +#define VPEC_STATUS3__EXCEPTION_IDLE__SHIFT 0x14 +#define VPEC_STATUS3__RESERVED_21_21__SHIFT 0x15 +#define VPEC_STATUS3__RESERVED_22_22__SHIFT 0x16 +#define VPEC_STATUS3__RESERVED_23_23__SHIFT 0x17 +#define VPEC_STATUS3__RESERVED_24_24__SHIFT 0x18 +#define VPEC_STATUS3__RESERVED_25_25__SHIFT 0x19 +#define VPEC_STATUS3__INT_QUEUE_ID__SHIFT 0x1a +#define VPEC_STATUS3__RESERVED_31_30__SHIFT 0x1e +#define VPEC_STATUS3__CMD_OP_STATUS_MASK 0x0000FFFFL +#define VPEC_STATUS3__RESERVED_19_16_MASK 0x000F0000L +#define VPEC_STATUS3__EXCEPTION_IDLE_MASK 0x00100000L +#define VPEC_STATUS3__RESERVED_21_21_MASK 0x00200000L +#define VPEC_STATUS3__RESERVED_22_22_MASK 0x00400000L +#define VPEC_STATUS3__RESERVED_23_23_MASK 0x00800000L +#define VPEC_STATUS3__RESERVED_24_24_MASK 0x01000000L +#define VPEC_STATUS3__RESERVED_25_25_MASK 0x02000000L +#define VPEC_STATUS3__INT_QUEUE_ID_MASK 0x3C000000L +#define VPEC_STATUS3__RESERVED_31_30_MASK 0xC0000000L +//VPEC_STATUS4 +#define VPEC_STATUS4__IDLE__SHIFT 0x0 +#define VPEC_STATUS4__IH_OUTSTANDING__SHIFT 0x2 +#define VPEC_STATUS4__RESERVED_3_3__SHIFT 0x3 +#define VPEC_STATUS4__CH_RD_OUTSTANDING__SHIFT 0x4 +#define VPEC_STATUS4__CH_WR_OUTSTANDING__SHIFT 0x5 +#define VPEC_STATUS4__RESERVED_6_6__SHIFT 0x6 +#define VPEC_STATUS4__RESERVED_7_7__SHIFT 0x7 +#define VPEC_STATUS4__RESERVED_8_8__SHIFT 0x8 +#define VPEC_STATUS4__RESERVED_9_9__SHIFT 0x9 +#define VPEC_STATUS4__REG_POLLING__SHIFT 0xa +#define VPEC_STATUS4__MEM_POLLING__SHIFT 0xb +#define VPEC_STATUS4__VPEP_REG_RD_OUTSTANDING__SHIFT 0xc +#define VPEC_STATUS4__VPEP_REG_WR_OUTSTANDING__SHIFT 0xd +#define VPEC_STATUS4__RESERVED_15_14__SHIFT 0xe +#define VPEC_STATUS4__ACTIVE_QUEUE_ID__SHIFT 0x10 +#define VPEC_STATUS4__RESERVED_27_20__SHIFT 0x14 +#define VPEC_STATUS4__IDLE_MASK 0x00000001L +#define VPEC_STATUS4__IH_OUTSTANDING_MASK 0x00000004L +#define VPEC_STATUS4__RESERVED_3_3_MASK 0x00000008L +#define VPEC_STATUS4__CH_RD_OUTSTANDING_MASK 0x00000010L +#define VPEC_STATUS4__CH_WR_OUTSTANDING_MASK 0x00000020L +#define VPEC_STATUS4__RESERVED_6_6_MASK 0x00000040L +#define VPEC_STATUS4__RESERVED_7_7_MASK 0x00000080L +#define VPEC_STATUS4__RESERVED_8_8_MASK 0x00000100L +#define VPEC_STATUS4__RESERVED_9_9_MASK 0x00000200L +#define VPEC_STATUS4__REG_POLLING_MASK 0x00000400L +#define VPEC_STATUS4__MEM_POLLING_MASK 0x00000800L +#define VPEC_STATUS4__VPEP_REG_RD_OUTSTANDING_MASK 0x00001000L +#define VPEC_STATUS4__VPEP_REG_WR_OUTSTANDING_MASK 0x00002000L +#define VPEC_STATUS4__RESERVED_15_14_MASK 0x0000C000L +#define VPEC_STATUS4__ACTIVE_QUEUE_ID_MASK 0x000F0000L +#define VPEC_STATUS4__RESERVED_27_20_MASK 0x0FF00000L +//VPEC_STATUS5 +#define VPEC_STATUS5__QUEUE0_RB_ENABLE_STATUS__SHIFT 0x0 +#define VPEC_STATUS5__QUEUE1_RB_ENABLE_STATUS__SHIFT 0x1 +#define VPEC_STATUS5__QUEUE2_RB_ENABLE_STATUS__SHIFT 0x2 +#define VPEC_STATUS5__QUEUE3_RB_ENABLE_STATUS__SHIFT 0x3 +#define VPEC_STATUS5__QUEUE4_RB_ENABLE_STATUS__SHIFT 0x4 +#define VPEC_STATUS5__QUEUE5_RB_ENABLE_STATUS__SHIFT 0x5 +#define VPEC_STATUS5__QUEUE6_RB_ENABLE_STATUS__SHIFT 0x6 +#define VPEC_STATUS5__QUEUE7_RB_ENABLE_STATUS__SHIFT 0x7 +#define VPEC_STATUS5__RESERVED_27_16__SHIFT 0x10 +#define VPEC_STATUS5__QUEUE0_RB_ENABLE_STATUS_MASK 0x00000001L +#define VPEC_STATUS5__QUEUE1_RB_ENABLE_STATUS_MASK 0x00000002L +#define VPEC_STATUS5__QUEUE2_RB_ENABLE_STATUS_MASK 0x00000004L +#define VPEC_STATUS5__QUEUE3_RB_ENABLE_STATUS_MASK 0x00000008L +#define VPEC_STATUS5__QUEUE4_RB_ENABLE_STATUS_MASK 0x00000010L +#define VPEC_STATUS5__QUEUE5_RB_ENABLE_STATUS_MASK 0x00000020L +#define VPEC_STATUS5__QUEUE6_RB_ENABLE_STATUS_MASK 0x00000040L +#define VPEC_STATUS5__QUEUE7_RB_ENABLE_STATUS_MASK 0x00000080L +#define VPEC_STATUS5__RESERVED_27_16_MASK 0x000F0000L +//VPEC_STATUS6 +#define VPEC_STATUS6__ID__SHIFT 0x0 +#define VPEC_STATUS6__TH1F32_INSTR_PTR__SHIFT 0x2 +#define VPEC_STATUS6__TH1_EXCEPTION__SHIFT 0x10 +#define VPEC_STATUS6__ID_MASK 0x00000003L +#define VPEC_STATUS6__TH1F32_INSTR_PTR_MASK 0x0000FFFCL +#define VPEC_STATUS6__TH1_EXCEPTION_MASK 0xFFFF0000L +//VPEC_STATUS7 +#define VPEC_STATUS7__TH0_DBG_STATUS__SHIFT 0x0 +#define VPEC_STATUS7__TH0_DBG_STATUS_MASK 0xFFFFFFFFL +//VPEC_INST +#define VPEC_INST__ID__SHIFT 0x0 +#define VPEC_INST__RESERVED__SHIFT 0x1 +#define VPEC_INST__ID_MASK 0x00000001L +#define VPEC_INST__RESERVED_MASK 0xFFFFFFFEL +//VPEC_QUEUE_STATUS0 +#define VPEC_QUEUE_STATUS0__QUEUE0_STATUS__SHIFT 0x0 +#define VPEC_QUEUE_STATUS0__QUEUE1_STATUS__SHIFT 0x4 +#define VPEC_QUEUE_STATUS0__QUEUE2_STATUS__SHIFT 0x8 +#define VPEC_QUEUE_STATUS0__QUEUE3_STATUS__SHIFT 0xc +#define VPEC_QUEUE_STATUS0__QUEUE4_STATUS__SHIFT 0x10 +#define VPEC_QUEUE_STATUS0__QUEUE5_STATUS__SHIFT 0x14 +#define VPEC_QUEUE_STATUS0__QUEUE6_STATUS__SHIFT 0x18 +#define VPEC_QUEUE_STATUS0__QUEUE7_STATUS__SHIFT 0x1c +#define VPEC_QUEUE_STATUS0__QUEUE0_STATUS_MASK 0x0000000FL +#define VPEC_QUEUE_STATUS0__QUEUE1_STATUS_MASK 0x000000F0L +#define VPEC_QUEUE_STATUS0__QUEUE2_STATUS_MASK 0x00000F00L +#define VPEC_QUEUE_STATUS0__QUEUE3_STATUS_MASK 0x0000F000L +#define VPEC_QUEUE_STATUS0__QUEUE4_STATUS_MASK 0x000F0000L +#define VPEC_QUEUE_STATUS0__QUEUE5_STATUS_MASK 0x00F00000L +#define VPEC_QUEUE_STATUS0__QUEUE6_STATUS_MASK 0x0F000000L +#define VPEC_QUEUE_STATUS0__QUEUE7_STATUS_MASK 0xF0000000L +//VPEC_QUEUE_HANG_STATUS +#define VPEC_QUEUE_HANG_STATUS__F30T0_HANG__SHIFT 0x0 +#define VPEC_QUEUE_HANG_STATUS__CE_HANG__SHIFT 0x1 +#define VPEC_QUEUE_HANG_STATUS__EOF_MISMATCH__SHIFT 0x2 +#define VPEC_QUEUE_HANG_STATUS__INVALID_OPCODE__SHIFT 0x3 +#define VPEC_QUEUE_HANG_STATUS__INVALID_VPEP_CONFIG_ADDR__SHIFT 0x4 +#define VPEC_QUEUE_HANG_STATUS__F30T0_HANG_MASK 0x00000001L +#define VPEC_QUEUE_HANG_STATUS__CE_HANG_MASK 0x00000002L +#define VPEC_QUEUE_HANG_STATUS__EOF_MISMATCH_MASK 0x00000004L +#define VPEC_QUEUE_HANG_STATUS__INVALID_OPCODE_MASK 0x00000008L +#define VPEC_QUEUE_HANG_STATUS__INVALID_VPEP_CONFIG_ADDR_MASK 0x00000010L +//VPEC_QUEUE0_RB_CNTL +#define VPEC_QUEUE0_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE0_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define VPEC_QUEUE0_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 +#define VPEC_QUEUE0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define VPEC_QUEUE0_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa +#define VPEC_QUEUE0_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT 0xb +#define VPEC_QUEUE0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define VPEC_QUEUE0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define VPEC_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define VPEC_QUEUE0_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define VPEC_QUEUE0_RB_CNTL__RB_VMID__SHIFT 0x18 +#define VPEC_QUEUE0_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE0_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define VPEC_QUEUE0_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L +#define VPEC_QUEUE0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define VPEC_QUEUE0_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L +#define VPEC_QUEUE0_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK 0x00000800L +#define VPEC_QUEUE0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define VPEC_QUEUE0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define VPEC_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define VPEC_QUEUE0_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define VPEC_QUEUE0_RB_CNTL__RB_VMID_MASK 0x0F000000L +//VPEC_QUEUE0_SCHEDULE_CNTL +#define VPEC_QUEUE0_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 +#define VPEC_QUEUE0_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 +#define VPEC_QUEUE0_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 +#define VPEC_QUEUE0_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 +#define VPEC_QUEUE0_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L +#define VPEC_QUEUE0_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL +#define VPEC_QUEUE0_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L +#define VPEC_QUEUE0_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L +//VPEC_QUEUE0_RB_BASE +#define VPEC_QUEUE0_RB_BASE__ADDR__SHIFT 0x0 +#define VPEC_QUEUE0_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE0_RB_BASE_HI +#define VPEC_QUEUE0_RB_BASE_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//VPEC_QUEUE0_RB_RPTR +#define VPEC_QUEUE0_RB_RPTR__OFFSET__SHIFT 0x0 +#define VPEC_QUEUE0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//VPEC_QUEUE0_RB_RPTR_HI +#define VPEC_QUEUE0_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define VPEC_QUEUE0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//VPEC_QUEUE0_RB_WPTR +#define VPEC_QUEUE0_RB_WPTR__OFFSET__SHIFT 0x0 +#define VPEC_QUEUE0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//VPEC_QUEUE0_RB_WPTR_HI +#define VPEC_QUEUE0_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define VPEC_QUEUE0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//VPEC_QUEUE0_RB_RPTR_ADDR_HI +#define VPEC_QUEUE0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE0_RB_RPTR_ADDR_LO +#define VPEC_QUEUE0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define VPEC_QUEUE0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//VPEC_QUEUE0_RB_AQL_CNTL +#define VPEC_QUEUE0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define VPEC_QUEUE0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define VPEC_QUEUE0_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 +#define VPEC_QUEUE0_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 +#define VPEC_QUEUE0_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 +#define VPEC_QUEUE0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define VPEC_QUEUE0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +#define VPEC_QUEUE0_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L +#define VPEC_QUEUE0_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L +#define VPEC_QUEUE0_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L +//VPEC_QUEUE0_MINOR_PTR_UPDATE +#define VPEC_QUEUE0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define VPEC_QUEUE0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//VPEC_QUEUE0_CD_INFO +#define VPEC_QUEUE0_CD_INFO__CD_INFO__SHIFT 0x0 +#define VPEC_QUEUE0_CD_INFO__CD_INFO_MASK 0xFFFFFFFFL +//VPEC_QUEUE0_RB_PREEMPT +#define VPEC_QUEUE0_RB_PREEMPT__PREEMPT_REQ__SHIFT 0x0 +#define VPEC_QUEUE0_RB_PREEMPT__PREEMPT_REQ_MASK 0x00000001L +//VPEC_QUEUE0_SKIP_CNTL +#define VPEC_QUEUE0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define VPEC_QUEUE0_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//VPEC_QUEUE0_DOORBELL +#define VPEC_QUEUE0_DOORBELL__ENABLE__SHIFT 0x1c +#define VPEC_QUEUE0_DOORBELL__CAPTURED__SHIFT 0x1e +#define VPEC_QUEUE0_DOORBELL__ENABLE_MASK 0x10000000L +#define VPEC_QUEUE0_DOORBELL__CAPTURED_MASK 0x40000000L +//VPEC_QUEUE0_DOORBELL_OFFSET +#define VPEC_QUEUE0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//VPEC_QUEUE0_DUMMY0 +#define VPEC_QUEUE0_DUMMY0__DUMMY__SHIFT 0x0 +#define VPEC_QUEUE0_DUMMY0__DUMMY_MASK 0xFFFFFFFFL +//VPEC_QUEUE0_DUMMY1 +#define VPEC_QUEUE0_DUMMY1__VALUE__SHIFT 0x0 +#define VPEC_QUEUE0_DUMMY1__VALUE_MASK 0xFFFFFFFFL +//VPEC_QUEUE0_DUMMY2 +#define VPEC_QUEUE0_DUMMY2__VALUE__SHIFT 0x0 +#define VPEC_QUEUE0_DUMMY2__VALUE_MASK 0xFFFFFFFFL +//VPEC_QUEUE0_DUMMY3 +#define VPEC_QUEUE0_DUMMY3__VALUE__SHIFT 0x0 +#define VPEC_QUEUE0_DUMMY3__VALUE_MASK 0xFFFFFFFFL +//VPEC_QUEUE0_DUMMY4 +#define VPEC_QUEUE0_DUMMY4__VALUE__SHIFT 0x0 +#define VPEC_QUEUE0_DUMMY4__VALUE_MASK 0xFFFFFFFFL +//VPEC_QUEUE0_IB_CNTL +#define VPEC_QUEUE0_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define VPEC_QUEUE0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define VPEC_QUEUE0_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define VPEC_QUEUE0_IB_CNTL__IB_PRIV__SHIFT 0x1f +#define VPEC_QUEUE0_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define VPEC_QUEUE0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define VPEC_QUEUE0_IB_CNTL__CMD_VMID_MASK 0x000F0000L +#define VPEC_QUEUE0_IB_CNTL__IB_PRIV_MASK 0x80000000L +//VPEC_QUEUE0_IB_RPTR +#define VPEC_QUEUE0_IB_RPTR__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE0_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE0_IB_OFFSET +#define VPEC_QUEUE0_IB_OFFSET__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE0_IB_BASE_LO +#define VPEC_QUEUE0_IB_BASE_LO__ADDR__SHIFT 0x5 +#define VPEC_QUEUE0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//VPEC_QUEUE0_IB_BASE_HI +#define VPEC_QUEUE0_IB_BASE_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE0_IB_SIZE +#define VPEC_QUEUE0_IB_SIZE__SIZE__SHIFT 0x0 +#define VPEC_QUEUE0_IB_SIZE__SIZE_MASK 0x000FFFFFL +//VPEC_QUEUE0_CMDIB_CNTL +#define VPEC_QUEUE0_CMDIB_CNTL__IB_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE0_CMDIB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define VPEC_QUEUE0_CMDIB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define VPEC_QUEUE0_CMDIB_CNTL__CMD_VMID__SHIFT 0x10 +#define VPEC_QUEUE0_CMDIB_CNTL__IB_PRIV__SHIFT 0x1f +#define VPEC_QUEUE0_CMDIB_CNTL__IB_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE0_CMDIB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define VPEC_QUEUE0_CMDIB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define VPEC_QUEUE0_CMDIB_CNTL__CMD_VMID_MASK 0x000F0000L +#define VPEC_QUEUE0_CMDIB_CNTL__IB_PRIV_MASK 0x80000000L +//VPEC_QUEUE0_CMDIB_RPTR +#define VPEC_QUEUE0_CMDIB_RPTR__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE0_CMDIB_RPTR__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE0_CMDIB_OFFSET +#define VPEC_QUEUE0_CMDIB_OFFSET__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE0_CMDIB_OFFSET__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE0_CMDIB_BASE_LO +#define VPEC_QUEUE0_CMDIB_BASE_LO__ADDR__SHIFT 0x5 +#define VPEC_QUEUE0_CMDIB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//VPEC_QUEUE0_CMDIB_BASE_HI +#define VPEC_QUEUE0_CMDIB_BASE_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE0_CMDIB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE0_CMDIB_SIZE +#define VPEC_QUEUE0_CMDIB_SIZE__SIZE__SHIFT 0x0 +#define VPEC_QUEUE0_CMDIB_SIZE__SIZE_MASK 0x000FFFFFL +//VPEC_QUEUE0_CSA_ADDR_LO +#define VPEC_QUEUE0_CSA_ADDR_LO__ADDR__SHIFT 0x0 +#define VPEC_QUEUE0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE0_CSA_ADDR_HI +#define VPEC_QUEUE0_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE0_CONTEXT_STATUS +#define VPEC_QUEUE0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define VPEC_QUEUE0_CONTEXT_STATUS__USE_IB__SHIFT 0x1 +#define VPEC_QUEUE0_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define VPEC_QUEUE0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define VPEC_QUEUE0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define VPEC_QUEUE0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define VPEC_QUEUE0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define VPEC_QUEUE0_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb +#define VPEC_QUEUE0_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc +#define VPEC_QUEUE0_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 +#define VPEC_QUEUE0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define VPEC_QUEUE0_CONTEXT_STATUS__USE_IB_MASK 0x00000002L +#define VPEC_QUEUE0_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define VPEC_QUEUE0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define VPEC_QUEUE0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define VPEC_QUEUE0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define VPEC_QUEUE0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +#define VPEC_QUEUE0_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L +#define VPEC_QUEUE0_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L +#define VPEC_QUEUE0_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L +//VPEC_QUEUE0_DOORBELL_LOG +#define VPEC_QUEUE0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define VPEC_QUEUE0_DOORBELL_LOG__DATA__SHIFT 0x2 +#define VPEC_QUEUE0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define VPEC_QUEUE0_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//VPEC_QUEUE0_IB_SUB_REMAIN +#define VPEC_QUEUE0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define VPEC_QUEUE0_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//VPEC_QUEUE0_PREEMPT +#define VPEC_QUEUE0_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define VPEC_QUEUE0_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//VPEC_QUEUE1_RB_CNTL +#define VPEC_QUEUE1_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE1_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define VPEC_QUEUE1_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 +#define VPEC_QUEUE1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define VPEC_QUEUE1_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa +#define VPEC_QUEUE1_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT 0xb +#define VPEC_QUEUE1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define VPEC_QUEUE1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define VPEC_QUEUE1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define VPEC_QUEUE1_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define VPEC_QUEUE1_RB_CNTL__RB_VMID__SHIFT 0x18 +#define VPEC_QUEUE1_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE1_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define VPEC_QUEUE1_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L +#define VPEC_QUEUE1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define VPEC_QUEUE1_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L +#define VPEC_QUEUE1_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK 0x00000800L +#define VPEC_QUEUE1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define VPEC_QUEUE1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define VPEC_QUEUE1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define VPEC_QUEUE1_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define VPEC_QUEUE1_RB_CNTL__RB_VMID_MASK 0x0F000000L +//VPEC_QUEUE1_SCHEDULE_CNTL +#define VPEC_QUEUE1_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 +#define VPEC_QUEUE1_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 +#define VPEC_QUEUE1_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 +#define VPEC_QUEUE1_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 +#define VPEC_QUEUE1_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L +#define VPEC_QUEUE1_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL +#define VPEC_QUEUE1_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L +#define VPEC_QUEUE1_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L +//VPEC_QUEUE1_RB_BASE +#define VPEC_QUEUE1_RB_BASE__ADDR__SHIFT 0x0 +#define VPEC_QUEUE1_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE1_RB_BASE_HI +#define VPEC_QUEUE1_RB_BASE_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//VPEC_QUEUE1_RB_RPTR +#define VPEC_QUEUE1_RB_RPTR__OFFSET__SHIFT 0x0 +#define VPEC_QUEUE1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//VPEC_QUEUE1_RB_RPTR_HI +#define VPEC_QUEUE1_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define VPEC_QUEUE1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//VPEC_QUEUE1_RB_WPTR +#define VPEC_QUEUE1_RB_WPTR__OFFSET__SHIFT 0x0 +#define VPEC_QUEUE1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//VPEC_QUEUE1_RB_WPTR_HI +#define VPEC_QUEUE1_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define VPEC_QUEUE1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//VPEC_QUEUE1_RB_RPTR_ADDR_HI +#define VPEC_QUEUE1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE1_RB_RPTR_ADDR_LO +#define VPEC_QUEUE1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define VPEC_QUEUE1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//VPEC_QUEUE1_RB_AQL_CNTL +#define VPEC_QUEUE1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define VPEC_QUEUE1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define VPEC_QUEUE1_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 +#define VPEC_QUEUE1_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 +#define VPEC_QUEUE1_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 +#define VPEC_QUEUE1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define VPEC_QUEUE1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +#define VPEC_QUEUE1_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L +#define VPEC_QUEUE1_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L +#define VPEC_QUEUE1_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L +//VPEC_QUEUE1_MINOR_PTR_UPDATE +#define VPEC_QUEUE1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define VPEC_QUEUE1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//VPEC_QUEUE1_CD_INFO +#define VPEC_QUEUE1_CD_INFO__CD_INFO__SHIFT 0x0 +#define VPEC_QUEUE1_CD_INFO__CD_INFO_MASK 0xFFFFFFFFL +//VPEC_QUEUE1_RB_PREEMPT +#define VPEC_QUEUE1_RB_PREEMPT__PREEMPT_REQ__SHIFT 0x0 +#define VPEC_QUEUE1_RB_PREEMPT__PREEMPT_REQ_MASK 0x00000001L +//VPEC_QUEUE1_SKIP_CNTL +#define VPEC_QUEUE1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define VPEC_QUEUE1_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//VPEC_QUEUE1_DOORBELL +#define VPEC_QUEUE1_DOORBELL__ENABLE__SHIFT 0x1c +#define VPEC_QUEUE1_DOORBELL__CAPTURED__SHIFT 0x1e +#define VPEC_QUEUE1_DOORBELL__ENABLE_MASK 0x10000000L +#define VPEC_QUEUE1_DOORBELL__CAPTURED_MASK 0x40000000L +//VPEC_QUEUE1_DOORBELL_OFFSET +#define VPEC_QUEUE1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//VPEC_QUEUE1_DUMMY0 +#define VPEC_QUEUE1_DUMMY0__DUMMY__SHIFT 0x0 +#define VPEC_QUEUE1_DUMMY0__DUMMY_MASK 0xFFFFFFFFL +//VPEC_QUEUE1_DUMMY1 +#define VPEC_QUEUE1_DUMMY1__VALUE__SHIFT 0x0 +#define VPEC_QUEUE1_DUMMY1__VALUE_MASK 0xFFFFFFFFL +//VPEC_QUEUE1_DUMMY2 +#define VPEC_QUEUE1_DUMMY2__VALUE__SHIFT 0x0 +#define VPEC_QUEUE1_DUMMY2__VALUE_MASK 0xFFFFFFFFL +//VPEC_QUEUE1_DUMMY3 +#define VPEC_QUEUE1_DUMMY3__VALUE__SHIFT 0x0 +#define VPEC_QUEUE1_DUMMY3__VALUE_MASK 0xFFFFFFFFL +//VPEC_QUEUE1_DUMMY4 +#define VPEC_QUEUE1_DUMMY4__VALUE__SHIFT 0x0 +#define VPEC_QUEUE1_DUMMY4__VALUE_MASK 0xFFFFFFFFL +//VPEC_QUEUE1_IB_CNTL +#define VPEC_QUEUE1_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define VPEC_QUEUE1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define VPEC_QUEUE1_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define VPEC_QUEUE1_IB_CNTL__IB_PRIV__SHIFT 0x1f +#define VPEC_QUEUE1_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define VPEC_QUEUE1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define VPEC_QUEUE1_IB_CNTL__CMD_VMID_MASK 0x000F0000L +#define VPEC_QUEUE1_IB_CNTL__IB_PRIV_MASK 0x80000000L +//VPEC_QUEUE1_IB_RPTR +#define VPEC_QUEUE1_IB_RPTR__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE1_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE1_IB_OFFSET +#define VPEC_QUEUE1_IB_OFFSET__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE1_IB_BASE_LO +#define VPEC_QUEUE1_IB_BASE_LO__ADDR__SHIFT 0x5 +#define VPEC_QUEUE1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//VPEC_QUEUE1_IB_BASE_HI +#define VPEC_QUEUE1_IB_BASE_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE1_IB_SIZE +#define VPEC_QUEUE1_IB_SIZE__SIZE__SHIFT 0x0 +#define VPEC_QUEUE1_IB_SIZE__SIZE_MASK 0x000FFFFFL +//VPEC_QUEUE1_CMDIB_CNTL +#define VPEC_QUEUE1_CMDIB_CNTL__IB_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE1_CMDIB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define VPEC_QUEUE1_CMDIB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define VPEC_QUEUE1_CMDIB_CNTL__CMD_VMID__SHIFT 0x10 +#define VPEC_QUEUE1_CMDIB_CNTL__IB_PRIV__SHIFT 0x1f +#define VPEC_QUEUE1_CMDIB_CNTL__IB_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE1_CMDIB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define VPEC_QUEUE1_CMDIB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define VPEC_QUEUE1_CMDIB_CNTL__CMD_VMID_MASK 0x000F0000L +#define VPEC_QUEUE1_CMDIB_CNTL__IB_PRIV_MASK 0x80000000L +//VPEC_QUEUE1_CMDIB_RPTR +#define VPEC_QUEUE1_CMDIB_RPTR__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE1_CMDIB_RPTR__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE1_CMDIB_OFFSET +#define VPEC_QUEUE1_CMDIB_OFFSET__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE1_CMDIB_OFFSET__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE1_CMDIB_BASE_LO +#define VPEC_QUEUE1_CMDIB_BASE_LO__ADDR__SHIFT 0x5 +#define VPEC_QUEUE1_CMDIB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//VPEC_QUEUE1_CMDIB_BASE_HI +#define VPEC_QUEUE1_CMDIB_BASE_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE1_CMDIB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE1_CMDIB_SIZE +#define VPEC_QUEUE1_CMDIB_SIZE__SIZE__SHIFT 0x0 +#define VPEC_QUEUE1_CMDIB_SIZE__SIZE_MASK 0x000FFFFFL +//VPEC_QUEUE1_CSA_ADDR_LO +#define VPEC_QUEUE1_CSA_ADDR_LO__ADDR__SHIFT 0x0 +#define VPEC_QUEUE1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE1_CSA_ADDR_HI +#define VPEC_QUEUE1_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE1_CONTEXT_STATUS +#define VPEC_QUEUE1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define VPEC_QUEUE1_CONTEXT_STATUS__USE_IB__SHIFT 0x1 +#define VPEC_QUEUE1_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define VPEC_QUEUE1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define VPEC_QUEUE1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define VPEC_QUEUE1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define VPEC_QUEUE1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define VPEC_QUEUE1_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb +#define VPEC_QUEUE1_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc +#define VPEC_QUEUE1_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 +#define VPEC_QUEUE1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define VPEC_QUEUE1_CONTEXT_STATUS__USE_IB_MASK 0x00000002L +#define VPEC_QUEUE1_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define VPEC_QUEUE1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define VPEC_QUEUE1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define VPEC_QUEUE1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define VPEC_QUEUE1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +#define VPEC_QUEUE1_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L +#define VPEC_QUEUE1_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L +#define VPEC_QUEUE1_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L +//VPEC_QUEUE1_DOORBELL_LOG +#define VPEC_QUEUE1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define VPEC_QUEUE1_DOORBELL_LOG__DATA__SHIFT 0x2 +#define VPEC_QUEUE1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define VPEC_QUEUE1_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//VPEC_QUEUE1_IB_SUB_REMAIN +#define VPEC_QUEUE1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define VPEC_QUEUE1_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//VPEC_QUEUE1_PREEMPT +#define VPEC_QUEUE1_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define VPEC_QUEUE1_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//VPEC_QUEUE2_RB_CNTL +#define VPEC_QUEUE2_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE2_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define VPEC_QUEUE2_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 +#define VPEC_QUEUE2_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define VPEC_QUEUE2_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa +#define VPEC_QUEUE2_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT 0xb +#define VPEC_QUEUE2_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define VPEC_QUEUE2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define VPEC_QUEUE2_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define VPEC_QUEUE2_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define VPEC_QUEUE2_RB_CNTL__RB_VMID__SHIFT 0x18 +#define VPEC_QUEUE2_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE2_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define VPEC_QUEUE2_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L +#define VPEC_QUEUE2_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define VPEC_QUEUE2_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L +#define VPEC_QUEUE2_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK 0x00000800L +#define VPEC_QUEUE2_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define VPEC_QUEUE2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define VPEC_QUEUE2_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define VPEC_QUEUE2_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define VPEC_QUEUE2_RB_CNTL__RB_VMID_MASK 0x0F000000L +//VPEC_QUEUE2_SCHEDULE_CNTL +#define VPEC_QUEUE2_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 +#define VPEC_QUEUE2_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 +#define VPEC_QUEUE2_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 +#define VPEC_QUEUE2_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 +#define VPEC_QUEUE2_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L +#define VPEC_QUEUE2_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL +#define VPEC_QUEUE2_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L +#define VPEC_QUEUE2_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L +//VPEC_QUEUE2_RB_BASE +#define VPEC_QUEUE2_RB_BASE__ADDR__SHIFT 0x0 +#define VPEC_QUEUE2_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE2_RB_BASE_HI +#define VPEC_QUEUE2_RB_BASE_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE2_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//VPEC_QUEUE2_RB_RPTR +#define VPEC_QUEUE2_RB_RPTR__OFFSET__SHIFT 0x0 +#define VPEC_QUEUE2_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//VPEC_QUEUE2_RB_RPTR_HI +#define VPEC_QUEUE2_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define VPEC_QUEUE2_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//VPEC_QUEUE2_RB_WPTR +#define VPEC_QUEUE2_RB_WPTR__OFFSET__SHIFT 0x0 +#define VPEC_QUEUE2_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//VPEC_QUEUE2_RB_WPTR_HI +#define VPEC_QUEUE2_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define VPEC_QUEUE2_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//VPEC_QUEUE2_RB_RPTR_ADDR_HI +#define VPEC_QUEUE2_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE2_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE2_RB_RPTR_ADDR_LO +#define VPEC_QUEUE2_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define VPEC_QUEUE2_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//VPEC_QUEUE2_RB_AQL_CNTL +#define VPEC_QUEUE2_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE2_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define VPEC_QUEUE2_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define VPEC_QUEUE2_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 +#define VPEC_QUEUE2_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 +#define VPEC_QUEUE2_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 +#define VPEC_QUEUE2_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE2_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define VPEC_QUEUE2_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +#define VPEC_QUEUE2_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L +#define VPEC_QUEUE2_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L +#define VPEC_QUEUE2_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L +//VPEC_QUEUE2_MINOR_PTR_UPDATE +#define VPEC_QUEUE2_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define VPEC_QUEUE2_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//VPEC_QUEUE2_CD_INFO +#define VPEC_QUEUE2_CD_INFO__CD_INFO__SHIFT 0x0 +#define VPEC_QUEUE2_CD_INFO__CD_INFO_MASK 0xFFFFFFFFL +//VPEC_QUEUE2_RB_PREEMPT +#define VPEC_QUEUE2_RB_PREEMPT__PREEMPT_REQ__SHIFT 0x0 +#define VPEC_QUEUE2_RB_PREEMPT__PREEMPT_REQ_MASK 0x00000001L +//VPEC_QUEUE2_SKIP_CNTL +#define VPEC_QUEUE2_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define VPEC_QUEUE2_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//VPEC_QUEUE2_DOORBELL +#define VPEC_QUEUE2_DOORBELL__ENABLE__SHIFT 0x1c +#define VPEC_QUEUE2_DOORBELL__CAPTURED__SHIFT 0x1e +#define VPEC_QUEUE2_DOORBELL__ENABLE_MASK 0x10000000L +#define VPEC_QUEUE2_DOORBELL__CAPTURED_MASK 0x40000000L +//VPEC_QUEUE2_DOORBELL_OFFSET +#define VPEC_QUEUE2_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE2_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//VPEC_QUEUE2_DUMMY0 +#define VPEC_QUEUE2_DUMMY0__DUMMY__SHIFT 0x0 +#define VPEC_QUEUE2_DUMMY0__DUMMY_MASK 0xFFFFFFFFL +//VPEC_QUEUE2_DUMMY1 +#define VPEC_QUEUE2_DUMMY1__VALUE__SHIFT 0x0 +#define VPEC_QUEUE2_DUMMY1__VALUE_MASK 0xFFFFFFFFL +//VPEC_QUEUE2_DUMMY2 +#define VPEC_QUEUE2_DUMMY2__VALUE__SHIFT 0x0 +#define VPEC_QUEUE2_DUMMY2__VALUE_MASK 0xFFFFFFFFL +//VPEC_QUEUE2_DUMMY3 +#define VPEC_QUEUE2_DUMMY3__VALUE__SHIFT 0x0 +#define VPEC_QUEUE2_DUMMY3__VALUE_MASK 0xFFFFFFFFL +//VPEC_QUEUE2_DUMMY4 +#define VPEC_QUEUE2_DUMMY4__VALUE__SHIFT 0x0 +#define VPEC_QUEUE2_DUMMY4__VALUE_MASK 0xFFFFFFFFL +//VPEC_QUEUE2_IB_CNTL +#define VPEC_QUEUE2_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE2_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define VPEC_QUEUE2_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define VPEC_QUEUE2_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define VPEC_QUEUE2_IB_CNTL__IB_PRIV__SHIFT 0x1f +#define VPEC_QUEUE2_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE2_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define VPEC_QUEUE2_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define VPEC_QUEUE2_IB_CNTL__CMD_VMID_MASK 0x000F0000L +#define VPEC_QUEUE2_IB_CNTL__IB_PRIV_MASK 0x80000000L +//VPEC_QUEUE2_IB_RPTR +#define VPEC_QUEUE2_IB_RPTR__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE2_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE2_IB_OFFSET +#define VPEC_QUEUE2_IB_OFFSET__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE2_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE2_IB_BASE_LO +#define VPEC_QUEUE2_IB_BASE_LO__ADDR__SHIFT 0x5 +#define VPEC_QUEUE2_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//VPEC_QUEUE2_IB_BASE_HI +#define VPEC_QUEUE2_IB_BASE_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE2_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE2_IB_SIZE +#define VPEC_QUEUE2_IB_SIZE__SIZE__SHIFT 0x0 +#define VPEC_QUEUE2_IB_SIZE__SIZE_MASK 0x000FFFFFL +//VPEC_QUEUE2_CMDIB_CNTL +#define VPEC_QUEUE2_CMDIB_CNTL__IB_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE2_CMDIB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define VPEC_QUEUE2_CMDIB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define VPEC_QUEUE2_CMDIB_CNTL__CMD_VMID__SHIFT 0x10 +#define VPEC_QUEUE2_CMDIB_CNTL__IB_PRIV__SHIFT 0x1f +#define VPEC_QUEUE2_CMDIB_CNTL__IB_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE2_CMDIB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define VPEC_QUEUE2_CMDIB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define VPEC_QUEUE2_CMDIB_CNTL__CMD_VMID_MASK 0x000F0000L +#define VPEC_QUEUE2_CMDIB_CNTL__IB_PRIV_MASK 0x80000000L +//VPEC_QUEUE2_CMDIB_RPTR +#define VPEC_QUEUE2_CMDIB_RPTR__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE2_CMDIB_RPTR__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE2_CMDIB_OFFSET +#define VPEC_QUEUE2_CMDIB_OFFSET__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE2_CMDIB_OFFSET__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE2_CMDIB_BASE_LO +#define VPEC_QUEUE2_CMDIB_BASE_LO__ADDR__SHIFT 0x5 +#define VPEC_QUEUE2_CMDIB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//VPEC_QUEUE2_CMDIB_BASE_HI +#define VPEC_QUEUE2_CMDIB_BASE_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE2_CMDIB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE2_CMDIB_SIZE +#define VPEC_QUEUE2_CMDIB_SIZE__SIZE__SHIFT 0x0 +#define VPEC_QUEUE2_CMDIB_SIZE__SIZE_MASK 0x000FFFFFL +//VPEC_QUEUE2_CSA_ADDR_LO +#define VPEC_QUEUE2_CSA_ADDR_LO__ADDR__SHIFT 0x0 +#define VPEC_QUEUE2_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE2_CSA_ADDR_HI +#define VPEC_QUEUE2_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE2_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE2_CONTEXT_STATUS +#define VPEC_QUEUE2_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define VPEC_QUEUE2_CONTEXT_STATUS__USE_IB__SHIFT 0x1 +#define VPEC_QUEUE2_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define VPEC_QUEUE2_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define VPEC_QUEUE2_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define VPEC_QUEUE2_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define VPEC_QUEUE2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define VPEC_QUEUE2_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb +#define VPEC_QUEUE2_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc +#define VPEC_QUEUE2_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 +#define VPEC_QUEUE2_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define VPEC_QUEUE2_CONTEXT_STATUS__USE_IB_MASK 0x00000002L +#define VPEC_QUEUE2_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define VPEC_QUEUE2_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define VPEC_QUEUE2_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define VPEC_QUEUE2_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define VPEC_QUEUE2_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +#define VPEC_QUEUE2_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L +#define VPEC_QUEUE2_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L +#define VPEC_QUEUE2_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L +//VPEC_QUEUE2_DOORBELL_LOG +#define VPEC_QUEUE2_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define VPEC_QUEUE2_DOORBELL_LOG__DATA__SHIFT 0x2 +#define VPEC_QUEUE2_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define VPEC_QUEUE2_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//VPEC_QUEUE2_IB_SUB_REMAIN +#define VPEC_QUEUE2_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define VPEC_QUEUE2_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//VPEC_QUEUE2_PREEMPT +#define VPEC_QUEUE2_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define VPEC_QUEUE2_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//VPEC_QUEUE3_RB_CNTL +#define VPEC_QUEUE3_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE3_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define VPEC_QUEUE3_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 +#define VPEC_QUEUE3_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define VPEC_QUEUE3_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa +#define VPEC_QUEUE3_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT 0xb +#define VPEC_QUEUE3_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define VPEC_QUEUE3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define VPEC_QUEUE3_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define VPEC_QUEUE3_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define VPEC_QUEUE3_RB_CNTL__RB_VMID__SHIFT 0x18 +#define VPEC_QUEUE3_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE3_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define VPEC_QUEUE3_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L +#define VPEC_QUEUE3_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define VPEC_QUEUE3_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L +#define VPEC_QUEUE3_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK 0x00000800L +#define VPEC_QUEUE3_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define VPEC_QUEUE3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define VPEC_QUEUE3_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define VPEC_QUEUE3_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define VPEC_QUEUE3_RB_CNTL__RB_VMID_MASK 0x0F000000L +//VPEC_QUEUE3_SCHEDULE_CNTL +#define VPEC_QUEUE3_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 +#define VPEC_QUEUE3_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 +#define VPEC_QUEUE3_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 +#define VPEC_QUEUE3_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 +#define VPEC_QUEUE3_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L +#define VPEC_QUEUE3_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL +#define VPEC_QUEUE3_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L +#define VPEC_QUEUE3_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L +//VPEC_QUEUE3_RB_BASE +#define VPEC_QUEUE3_RB_BASE__ADDR__SHIFT 0x0 +#define VPEC_QUEUE3_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE3_RB_BASE_HI +#define VPEC_QUEUE3_RB_BASE_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE3_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//VPEC_QUEUE3_RB_RPTR +#define VPEC_QUEUE3_RB_RPTR__OFFSET__SHIFT 0x0 +#define VPEC_QUEUE3_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//VPEC_QUEUE3_RB_RPTR_HI +#define VPEC_QUEUE3_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define VPEC_QUEUE3_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//VPEC_QUEUE3_RB_WPTR +#define VPEC_QUEUE3_RB_WPTR__OFFSET__SHIFT 0x0 +#define VPEC_QUEUE3_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//VPEC_QUEUE3_RB_WPTR_HI +#define VPEC_QUEUE3_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define VPEC_QUEUE3_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//VPEC_QUEUE3_RB_RPTR_ADDR_HI +#define VPEC_QUEUE3_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE3_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE3_RB_RPTR_ADDR_LO +#define VPEC_QUEUE3_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define VPEC_QUEUE3_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//VPEC_QUEUE3_RB_AQL_CNTL +#define VPEC_QUEUE3_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE3_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define VPEC_QUEUE3_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define VPEC_QUEUE3_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 +#define VPEC_QUEUE3_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 +#define VPEC_QUEUE3_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 +#define VPEC_QUEUE3_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE3_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define VPEC_QUEUE3_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +#define VPEC_QUEUE3_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L +#define VPEC_QUEUE3_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L +#define VPEC_QUEUE3_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L +//VPEC_QUEUE3_MINOR_PTR_UPDATE +#define VPEC_QUEUE3_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define VPEC_QUEUE3_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//VPEC_QUEUE3_CD_INFO +#define VPEC_QUEUE3_CD_INFO__CD_INFO__SHIFT 0x0 +#define VPEC_QUEUE3_CD_INFO__CD_INFO_MASK 0xFFFFFFFFL +//VPEC_QUEUE3_RB_PREEMPT +#define VPEC_QUEUE3_RB_PREEMPT__PREEMPT_REQ__SHIFT 0x0 +#define VPEC_QUEUE3_RB_PREEMPT__PREEMPT_REQ_MASK 0x00000001L +//VPEC_QUEUE3_SKIP_CNTL +#define VPEC_QUEUE3_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define VPEC_QUEUE3_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//VPEC_QUEUE3_DOORBELL +#define VPEC_QUEUE3_DOORBELL__ENABLE__SHIFT 0x1c +#define VPEC_QUEUE3_DOORBELL__CAPTURED__SHIFT 0x1e +#define VPEC_QUEUE3_DOORBELL__ENABLE_MASK 0x10000000L +#define VPEC_QUEUE3_DOORBELL__CAPTURED_MASK 0x40000000L +//VPEC_QUEUE3_DOORBELL_OFFSET +#define VPEC_QUEUE3_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE3_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//VPEC_QUEUE3_DUMMY0 +#define VPEC_QUEUE3_DUMMY0__DUMMY__SHIFT 0x0 +#define VPEC_QUEUE3_DUMMY0__DUMMY_MASK 0xFFFFFFFFL +//VPEC_QUEUE3_DUMMY1 +#define VPEC_QUEUE3_DUMMY1__VALUE__SHIFT 0x0 +#define VPEC_QUEUE3_DUMMY1__VALUE_MASK 0xFFFFFFFFL +//VPEC_QUEUE3_DUMMY2 +#define VPEC_QUEUE3_DUMMY2__VALUE__SHIFT 0x0 +#define VPEC_QUEUE3_DUMMY2__VALUE_MASK 0xFFFFFFFFL +//VPEC_QUEUE3_DUMMY3 +#define VPEC_QUEUE3_DUMMY3__VALUE__SHIFT 0x0 +#define VPEC_QUEUE3_DUMMY3__VALUE_MASK 0xFFFFFFFFL +//VPEC_QUEUE3_DUMMY4 +#define VPEC_QUEUE3_DUMMY4__VALUE__SHIFT 0x0 +#define VPEC_QUEUE3_DUMMY4__VALUE_MASK 0xFFFFFFFFL +//VPEC_QUEUE3_IB_CNTL +#define VPEC_QUEUE3_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE3_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define VPEC_QUEUE3_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define VPEC_QUEUE3_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define VPEC_QUEUE3_IB_CNTL__IB_PRIV__SHIFT 0x1f +#define VPEC_QUEUE3_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE3_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define VPEC_QUEUE3_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define VPEC_QUEUE3_IB_CNTL__CMD_VMID_MASK 0x000F0000L +#define VPEC_QUEUE3_IB_CNTL__IB_PRIV_MASK 0x80000000L +//VPEC_QUEUE3_IB_RPTR +#define VPEC_QUEUE3_IB_RPTR__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE3_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE3_IB_OFFSET +#define VPEC_QUEUE3_IB_OFFSET__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE3_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE3_IB_BASE_LO +#define VPEC_QUEUE3_IB_BASE_LO__ADDR__SHIFT 0x5 +#define VPEC_QUEUE3_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//VPEC_QUEUE3_IB_BASE_HI +#define VPEC_QUEUE3_IB_BASE_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE3_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE3_IB_SIZE +#define VPEC_QUEUE3_IB_SIZE__SIZE__SHIFT 0x0 +#define VPEC_QUEUE3_IB_SIZE__SIZE_MASK 0x000FFFFFL +//VPEC_QUEUE3_CMDIB_CNTL +#define VPEC_QUEUE3_CMDIB_CNTL__IB_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE3_CMDIB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define VPEC_QUEUE3_CMDIB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define VPEC_QUEUE3_CMDIB_CNTL__CMD_VMID__SHIFT 0x10 +#define VPEC_QUEUE3_CMDIB_CNTL__IB_PRIV__SHIFT 0x1f +#define VPEC_QUEUE3_CMDIB_CNTL__IB_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE3_CMDIB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define VPEC_QUEUE3_CMDIB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define VPEC_QUEUE3_CMDIB_CNTL__CMD_VMID_MASK 0x000F0000L +#define VPEC_QUEUE3_CMDIB_CNTL__IB_PRIV_MASK 0x80000000L +//VPEC_QUEUE3_CMDIB_RPTR +#define VPEC_QUEUE3_CMDIB_RPTR__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE3_CMDIB_RPTR__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE3_CMDIB_OFFSET +#define VPEC_QUEUE3_CMDIB_OFFSET__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE3_CMDIB_OFFSET__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE3_CMDIB_BASE_LO +#define VPEC_QUEUE3_CMDIB_BASE_LO__ADDR__SHIFT 0x5 +#define VPEC_QUEUE3_CMDIB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//VPEC_QUEUE3_CMDIB_BASE_HI +#define VPEC_QUEUE3_CMDIB_BASE_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE3_CMDIB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE3_CMDIB_SIZE +#define VPEC_QUEUE3_CMDIB_SIZE__SIZE__SHIFT 0x0 +#define VPEC_QUEUE3_CMDIB_SIZE__SIZE_MASK 0x000FFFFFL +//VPEC_QUEUE3_CSA_ADDR_LO +#define VPEC_QUEUE3_CSA_ADDR_LO__ADDR__SHIFT 0x0 +#define VPEC_QUEUE3_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE3_CSA_ADDR_HI +#define VPEC_QUEUE3_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE3_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE3_CONTEXT_STATUS +#define VPEC_QUEUE3_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define VPEC_QUEUE3_CONTEXT_STATUS__USE_IB__SHIFT 0x1 +#define VPEC_QUEUE3_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define VPEC_QUEUE3_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define VPEC_QUEUE3_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define VPEC_QUEUE3_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define VPEC_QUEUE3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define VPEC_QUEUE3_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb +#define VPEC_QUEUE3_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc +#define VPEC_QUEUE3_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 +#define VPEC_QUEUE3_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define VPEC_QUEUE3_CONTEXT_STATUS__USE_IB_MASK 0x00000002L +#define VPEC_QUEUE3_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define VPEC_QUEUE3_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define VPEC_QUEUE3_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define VPEC_QUEUE3_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define VPEC_QUEUE3_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +#define VPEC_QUEUE3_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L +#define VPEC_QUEUE3_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L +#define VPEC_QUEUE3_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L +//VPEC_QUEUE3_DOORBELL_LOG +#define VPEC_QUEUE3_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define VPEC_QUEUE3_DOORBELL_LOG__DATA__SHIFT 0x2 +#define VPEC_QUEUE3_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define VPEC_QUEUE3_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//VPEC_QUEUE3_IB_SUB_REMAIN +#define VPEC_QUEUE3_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define VPEC_QUEUE3_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//VPEC_QUEUE3_PREEMPT +#define VPEC_QUEUE3_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define VPEC_QUEUE3_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//VPEC_QUEUE4_RB_CNTL +#define VPEC_QUEUE4_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE4_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define VPEC_QUEUE4_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 +#define VPEC_QUEUE4_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define VPEC_QUEUE4_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa +#define VPEC_QUEUE4_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT 0xb +#define VPEC_QUEUE4_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define VPEC_QUEUE4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define VPEC_QUEUE4_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define VPEC_QUEUE4_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define VPEC_QUEUE4_RB_CNTL__RB_VMID__SHIFT 0x18 +#define VPEC_QUEUE4_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE4_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define VPEC_QUEUE4_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L +#define VPEC_QUEUE4_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define VPEC_QUEUE4_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L +#define VPEC_QUEUE4_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK 0x00000800L +#define VPEC_QUEUE4_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define VPEC_QUEUE4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define VPEC_QUEUE4_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define VPEC_QUEUE4_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define VPEC_QUEUE4_RB_CNTL__RB_VMID_MASK 0x0F000000L +//VPEC_QUEUE4_SCHEDULE_CNTL +#define VPEC_QUEUE4_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 +#define VPEC_QUEUE4_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 +#define VPEC_QUEUE4_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 +#define VPEC_QUEUE4_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 +#define VPEC_QUEUE4_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L +#define VPEC_QUEUE4_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL +#define VPEC_QUEUE4_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L +#define VPEC_QUEUE4_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L +//VPEC_QUEUE4_RB_BASE +#define VPEC_QUEUE4_RB_BASE__ADDR__SHIFT 0x0 +#define VPEC_QUEUE4_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE4_RB_BASE_HI +#define VPEC_QUEUE4_RB_BASE_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE4_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//VPEC_QUEUE4_RB_RPTR +#define VPEC_QUEUE4_RB_RPTR__OFFSET__SHIFT 0x0 +#define VPEC_QUEUE4_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//VPEC_QUEUE4_RB_RPTR_HI +#define VPEC_QUEUE4_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define VPEC_QUEUE4_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//VPEC_QUEUE4_RB_WPTR +#define VPEC_QUEUE4_RB_WPTR__OFFSET__SHIFT 0x0 +#define VPEC_QUEUE4_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//VPEC_QUEUE4_RB_WPTR_HI +#define VPEC_QUEUE4_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define VPEC_QUEUE4_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//VPEC_QUEUE4_RB_RPTR_ADDR_HI +#define VPEC_QUEUE4_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE4_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE4_RB_RPTR_ADDR_LO +#define VPEC_QUEUE4_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define VPEC_QUEUE4_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//VPEC_QUEUE4_RB_AQL_CNTL +#define VPEC_QUEUE4_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE4_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define VPEC_QUEUE4_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define VPEC_QUEUE4_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 +#define VPEC_QUEUE4_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 +#define VPEC_QUEUE4_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 +#define VPEC_QUEUE4_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE4_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define VPEC_QUEUE4_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +#define VPEC_QUEUE4_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L +#define VPEC_QUEUE4_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L +#define VPEC_QUEUE4_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L +//VPEC_QUEUE4_MINOR_PTR_UPDATE +#define VPEC_QUEUE4_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define VPEC_QUEUE4_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//VPEC_QUEUE4_CD_INFO +#define VPEC_QUEUE4_CD_INFO__CD_INFO__SHIFT 0x0 +#define VPEC_QUEUE4_CD_INFO__CD_INFO_MASK 0xFFFFFFFFL +//VPEC_QUEUE4_RB_PREEMPT +#define VPEC_QUEUE4_RB_PREEMPT__PREEMPT_REQ__SHIFT 0x0 +#define VPEC_QUEUE4_RB_PREEMPT__PREEMPT_REQ_MASK 0x00000001L +//VPEC_QUEUE4_SKIP_CNTL +#define VPEC_QUEUE4_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define VPEC_QUEUE4_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//VPEC_QUEUE4_DOORBELL +#define VPEC_QUEUE4_DOORBELL__ENABLE__SHIFT 0x1c +#define VPEC_QUEUE4_DOORBELL__CAPTURED__SHIFT 0x1e +#define VPEC_QUEUE4_DOORBELL__ENABLE_MASK 0x10000000L +#define VPEC_QUEUE4_DOORBELL__CAPTURED_MASK 0x40000000L +//VPEC_QUEUE4_DOORBELL_OFFSET +#define VPEC_QUEUE4_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE4_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//VPEC_QUEUE4_DUMMY0 +#define VPEC_QUEUE4_DUMMY0__DUMMY__SHIFT 0x0 +#define VPEC_QUEUE4_DUMMY0__DUMMY_MASK 0xFFFFFFFFL +//VPEC_QUEUE4_DUMMY1 +#define VPEC_QUEUE4_DUMMY1__VALUE__SHIFT 0x0 +#define VPEC_QUEUE4_DUMMY1__VALUE_MASK 0xFFFFFFFFL +//VPEC_QUEUE4_DUMMY2 +#define VPEC_QUEUE4_DUMMY2__VALUE__SHIFT 0x0 +#define VPEC_QUEUE4_DUMMY2__VALUE_MASK 0xFFFFFFFFL +//VPEC_QUEUE4_DUMMY3 +#define VPEC_QUEUE4_DUMMY3__VALUE__SHIFT 0x0 +#define VPEC_QUEUE4_DUMMY3__VALUE_MASK 0xFFFFFFFFL +//VPEC_QUEUE4_DUMMY4 +#define VPEC_QUEUE4_DUMMY4__VALUE__SHIFT 0x0 +#define VPEC_QUEUE4_DUMMY4__VALUE_MASK 0xFFFFFFFFL +//VPEC_QUEUE4_IB_CNTL +#define VPEC_QUEUE4_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE4_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define VPEC_QUEUE4_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define VPEC_QUEUE4_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define VPEC_QUEUE4_IB_CNTL__IB_PRIV__SHIFT 0x1f +#define VPEC_QUEUE4_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE4_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define VPEC_QUEUE4_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define VPEC_QUEUE4_IB_CNTL__CMD_VMID_MASK 0x000F0000L +#define VPEC_QUEUE4_IB_CNTL__IB_PRIV_MASK 0x80000000L +//VPEC_QUEUE4_IB_RPTR +#define VPEC_QUEUE4_IB_RPTR__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE4_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE4_IB_OFFSET +#define VPEC_QUEUE4_IB_OFFSET__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE4_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE4_IB_BASE_LO +#define VPEC_QUEUE4_IB_BASE_LO__ADDR__SHIFT 0x5 +#define VPEC_QUEUE4_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//VPEC_QUEUE4_IB_BASE_HI +#define VPEC_QUEUE4_IB_BASE_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE4_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE4_IB_SIZE +#define VPEC_QUEUE4_IB_SIZE__SIZE__SHIFT 0x0 +#define VPEC_QUEUE4_IB_SIZE__SIZE_MASK 0x000FFFFFL +//VPEC_QUEUE4_CMDIB_CNTL +#define VPEC_QUEUE4_CMDIB_CNTL__IB_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE4_CMDIB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define VPEC_QUEUE4_CMDIB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define VPEC_QUEUE4_CMDIB_CNTL__CMD_VMID__SHIFT 0x10 +#define VPEC_QUEUE4_CMDIB_CNTL__IB_PRIV__SHIFT 0x1f +#define VPEC_QUEUE4_CMDIB_CNTL__IB_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE4_CMDIB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define VPEC_QUEUE4_CMDIB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define VPEC_QUEUE4_CMDIB_CNTL__CMD_VMID_MASK 0x000F0000L +#define VPEC_QUEUE4_CMDIB_CNTL__IB_PRIV_MASK 0x80000000L +//VPEC_QUEUE4_CMDIB_RPTR +#define VPEC_QUEUE4_CMDIB_RPTR__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE4_CMDIB_RPTR__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE4_CMDIB_OFFSET +#define VPEC_QUEUE4_CMDIB_OFFSET__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE4_CMDIB_OFFSET__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE4_CMDIB_BASE_LO +#define VPEC_QUEUE4_CMDIB_BASE_LO__ADDR__SHIFT 0x5 +#define VPEC_QUEUE4_CMDIB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//VPEC_QUEUE4_CMDIB_BASE_HI +#define VPEC_QUEUE4_CMDIB_BASE_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE4_CMDIB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE4_CMDIB_SIZE +#define VPEC_QUEUE4_CMDIB_SIZE__SIZE__SHIFT 0x0 +#define VPEC_QUEUE4_CMDIB_SIZE__SIZE_MASK 0x000FFFFFL +//VPEC_QUEUE4_CSA_ADDR_LO +#define VPEC_QUEUE4_CSA_ADDR_LO__ADDR__SHIFT 0x0 +#define VPEC_QUEUE4_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE4_CSA_ADDR_HI +#define VPEC_QUEUE4_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE4_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE4_CONTEXT_STATUS +#define VPEC_QUEUE4_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define VPEC_QUEUE4_CONTEXT_STATUS__USE_IB__SHIFT 0x1 +#define VPEC_QUEUE4_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define VPEC_QUEUE4_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define VPEC_QUEUE4_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define VPEC_QUEUE4_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define VPEC_QUEUE4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define VPEC_QUEUE4_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb +#define VPEC_QUEUE4_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc +#define VPEC_QUEUE4_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 +#define VPEC_QUEUE4_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define VPEC_QUEUE4_CONTEXT_STATUS__USE_IB_MASK 0x00000002L +#define VPEC_QUEUE4_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define VPEC_QUEUE4_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define VPEC_QUEUE4_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define VPEC_QUEUE4_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define VPEC_QUEUE4_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +#define VPEC_QUEUE4_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L +#define VPEC_QUEUE4_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L +#define VPEC_QUEUE4_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L +//VPEC_QUEUE4_DOORBELL_LOG +#define VPEC_QUEUE4_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define VPEC_QUEUE4_DOORBELL_LOG__DATA__SHIFT 0x2 +#define VPEC_QUEUE4_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define VPEC_QUEUE4_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//VPEC_QUEUE4_IB_SUB_REMAIN +#define VPEC_QUEUE4_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define VPEC_QUEUE4_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//VPEC_QUEUE4_PREEMPT +#define VPEC_QUEUE4_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define VPEC_QUEUE4_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//VPEC_QUEUE5_RB_CNTL +#define VPEC_QUEUE5_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE5_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define VPEC_QUEUE5_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 +#define VPEC_QUEUE5_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define VPEC_QUEUE5_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa +#define VPEC_QUEUE5_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT 0xb +#define VPEC_QUEUE5_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define VPEC_QUEUE5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define VPEC_QUEUE5_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define VPEC_QUEUE5_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define VPEC_QUEUE5_RB_CNTL__RB_VMID__SHIFT 0x18 +#define VPEC_QUEUE5_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE5_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define VPEC_QUEUE5_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L +#define VPEC_QUEUE5_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define VPEC_QUEUE5_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L +#define VPEC_QUEUE5_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK 0x00000800L +#define VPEC_QUEUE5_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define VPEC_QUEUE5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define VPEC_QUEUE5_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define VPEC_QUEUE5_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define VPEC_QUEUE5_RB_CNTL__RB_VMID_MASK 0x0F000000L +//VPEC_QUEUE5_SCHEDULE_CNTL +#define VPEC_QUEUE5_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 +#define VPEC_QUEUE5_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 +#define VPEC_QUEUE5_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 +#define VPEC_QUEUE5_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 +#define VPEC_QUEUE5_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L +#define VPEC_QUEUE5_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL +#define VPEC_QUEUE5_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L +#define VPEC_QUEUE5_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L +//VPEC_QUEUE5_RB_BASE +#define VPEC_QUEUE5_RB_BASE__ADDR__SHIFT 0x0 +#define VPEC_QUEUE5_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE5_RB_BASE_HI +#define VPEC_QUEUE5_RB_BASE_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE5_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//VPEC_QUEUE5_RB_RPTR +#define VPEC_QUEUE5_RB_RPTR__OFFSET__SHIFT 0x0 +#define VPEC_QUEUE5_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//VPEC_QUEUE5_RB_RPTR_HI +#define VPEC_QUEUE5_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define VPEC_QUEUE5_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//VPEC_QUEUE5_RB_WPTR +#define VPEC_QUEUE5_RB_WPTR__OFFSET__SHIFT 0x0 +#define VPEC_QUEUE5_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//VPEC_QUEUE5_RB_WPTR_HI +#define VPEC_QUEUE5_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define VPEC_QUEUE5_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//VPEC_QUEUE5_RB_RPTR_ADDR_HI +#define VPEC_QUEUE5_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE5_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE5_RB_RPTR_ADDR_LO +#define VPEC_QUEUE5_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define VPEC_QUEUE5_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//VPEC_QUEUE5_RB_AQL_CNTL +#define VPEC_QUEUE5_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE5_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define VPEC_QUEUE5_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define VPEC_QUEUE5_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 +#define VPEC_QUEUE5_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 +#define VPEC_QUEUE5_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 +#define VPEC_QUEUE5_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE5_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define VPEC_QUEUE5_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +#define VPEC_QUEUE5_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L +#define VPEC_QUEUE5_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L +#define VPEC_QUEUE5_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L +//VPEC_QUEUE5_MINOR_PTR_UPDATE +#define VPEC_QUEUE5_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define VPEC_QUEUE5_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//VPEC_QUEUE5_CD_INFO +#define VPEC_QUEUE5_CD_INFO__CD_INFO__SHIFT 0x0 +#define VPEC_QUEUE5_CD_INFO__CD_INFO_MASK 0xFFFFFFFFL +//VPEC_QUEUE5_RB_PREEMPT +#define VPEC_QUEUE5_RB_PREEMPT__PREEMPT_REQ__SHIFT 0x0 +#define VPEC_QUEUE5_RB_PREEMPT__PREEMPT_REQ_MASK 0x00000001L +//VPEC_QUEUE5_SKIP_CNTL +#define VPEC_QUEUE5_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define VPEC_QUEUE5_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//VPEC_QUEUE5_DOORBELL +#define VPEC_QUEUE5_DOORBELL__ENABLE__SHIFT 0x1c +#define VPEC_QUEUE5_DOORBELL__CAPTURED__SHIFT 0x1e +#define VPEC_QUEUE5_DOORBELL__ENABLE_MASK 0x10000000L +#define VPEC_QUEUE5_DOORBELL__CAPTURED_MASK 0x40000000L +//VPEC_QUEUE5_DOORBELL_OFFSET +#define VPEC_QUEUE5_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE5_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//VPEC_QUEUE5_DUMMY0 +#define VPEC_QUEUE5_DUMMY0__DUMMY__SHIFT 0x0 +#define VPEC_QUEUE5_DUMMY0__DUMMY_MASK 0xFFFFFFFFL +//VPEC_QUEUE5_DUMMY1 +#define VPEC_QUEUE5_DUMMY1__VALUE__SHIFT 0x0 +#define VPEC_QUEUE5_DUMMY1__VALUE_MASK 0xFFFFFFFFL +//VPEC_QUEUE5_DUMMY2 +#define VPEC_QUEUE5_DUMMY2__VALUE__SHIFT 0x0 +#define VPEC_QUEUE5_DUMMY2__VALUE_MASK 0xFFFFFFFFL +//VPEC_QUEUE5_DUMMY3 +#define VPEC_QUEUE5_DUMMY3__VALUE__SHIFT 0x0 +#define VPEC_QUEUE5_DUMMY3__VALUE_MASK 0xFFFFFFFFL +//VPEC_QUEUE5_DUMMY4 +#define VPEC_QUEUE5_DUMMY4__VALUE__SHIFT 0x0 +#define VPEC_QUEUE5_DUMMY4__VALUE_MASK 0xFFFFFFFFL +//VPEC_QUEUE5_IB_CNTL +#define VPEC_QUEUE5_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE5_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define VPEC_QUEUE5_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define VPEC_QUEUE5_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define VPEC_QUEUE5_IB_CNTL__IB_PRIV__SHIFT 0x1f +#define VPEC_QUEUE5_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE5_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define VPEC_QUEUE5_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define VPEC_QUEUE5_IB_CNTL__CMD_VMID_MASK 0x000F0000L +#define VPEC_QUEUE5_IB_CNTL__IB_PRIV_MASK 0x80000000L +//VPEC_QUEUE5_IB_RPTR +#define VPEC_QUEUE5_IB_RPTR__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE5_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE5_IB_OFFSET +#define VPEC_QUEUE5_IB_OFFSET__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE5_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE5_IB_BASE_LO +#define VPEC_QUEUE5_IB_BASE_LO__ADDR__SHIFT 0x5 +#define VPEC_QUEUE5_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//VPEC_QUEUE5_IB_BASE_HI +#define VPEC_QUEUE5_IB_BASE_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE5_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE5_IB_SIZE +#define VPEC_QUEUE5_IB_SIZE__SIZE__SHIFT 0x0 +#define VPEC_QUEUE5_IB_SIZE__SIZE_MASK 0x000FFFFFL +//VPEC_QUEUE5_CMDIB_CNTL +#define VPEC_QUEUE5_CMDIB_CNTL__IB_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE5_CMDIB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define VPEC_QUEUE5_CMDIB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define VPEC_QUEUE5_CMDIB_CNTL__CMD_VMID__SHIFT 0x10 +#define VPEC_QUEUE5_CMDIB_CNTL__IB_PRIV__SHIFT 0x1f +#define VPEC_QUEUE5_CMDIB_CNTL__IB_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE5_CMDIB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define VPEC_QUEUE5_CMDIB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define VPEC_QUEUE5_CMDIB_CNTL__CMD_VMID_MASK 0x000F0000L +#define VPEC_QUEUE5_CMDIB_CNTL__IB_PRIV_MASK 0x80000000L +//VPEC_QUEUE5_CMDIB_RPTR +#define VPEC_QUEUE5_CMDIB_RPTR__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE5_CMDIB_RPTR__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE5_CMDIB_OFFSET +#define VPEC_QUEUE5_CMDIB_OFFSET__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE5_CMDIB_OFFSET__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE5_CMDIB_BASE_LO +#define VPEC_QUEUE5_CMDIB_BASE_LO__ADDR__SHIFT 0x5 +#define VPEC_QUEUE5_CMDIB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//VPEC_QUEUE5_CMDIB_BASE_HI +#define VPEC_QUEUE5_CMDIB_BASE_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE5_CMDIB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE5_CMDIB_SIZE +#define VPEC_QUEUE5_CMDIB_SIZE__SIZE__SHIFT 0x0 +#define VPEC_QUEUE5_CMDIB_SIZE__SIZE_MASK 0x000FFFFFL +//VPEC_QUEUE5_CSA_ADDR_LO +#define VPEC_QUEUE5_CSA_ADDR_LO__ADDR__SHIFT 0x0 +#define VPEC_QUEUE5_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE5_CSA_ADDR_HI +#define VPEC_QUEUE5_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE5_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE5_CONTEXT_STATUS +#define VPEC_QUEUE5_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define VPEC_QUEUE5_CONTEXT_STATUS__USE_IB__SHIFT 0x1 +#define VPEC_QUEUE5_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define VPEC_QUEUE5_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define VPEC_QUEUE5_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define VPEC_QUEUE5_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define VPEC_QUEUE5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define VPEC_QUEUE5_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb +#define VPEC_QUEUE5_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc +#define VPEC_QUEUE5_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 +#define VPEC_QUEUE5_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define VPEC_QUEUE5_CONTEXT_STATUS__USE_IB_MASK 0x00000002L +#define VPEC_QUEUE5_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define VPEC_QUEUE5_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define VPEC_QUEUE5_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define VPEC_QUEUE5_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define VPEC_QUEUE5_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +#define VPEC_QUEUE5_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L +#define VPEC_QUEUE5_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L +#define VPEC_QUEUE5_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L +//VPEC_QUEUE5_DOORBELL_LOG +#define VPEC_QUEUE5_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define VPEC_QUEUE5_DOORBELL_LOG__DATA__SHIFT 0x2 +#define VPEC_QUEUE5_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define VPEC_QUEUE5_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//VPEC_QUEUE5_IB_SUB_REMAIN +#define VPEC_QUEUE5_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define VPEC_QUEUE5_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//VPEC_QUEUE5_PREEMPT +#define VPEC_QUEUE5_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define VPEC_QUEUE5_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//VPEC_QUEUE6_RB_CNTL +#define VPEC_QUEUE6_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE6_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define VPEC_QUEUE6_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 +#define VPEC_QUEUE6_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define VPEC_QUEUE6_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa +#define VPEC_QUEUE6_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT 0xb +#define VPEC_QUEUE6_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define VPEC_QUEUE6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define VPEC_QUEUE6_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define VPEC_QUEUE6_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define VPEC_QUEUE6_RB_CNTL__RB_VMID__SHIFT 0x18 +#define VPEC_QUEUE6_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE6_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define VPEC_QUEUE6_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L +#define VPEC_QUEUE6_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define VPEC_QUEUE6_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L +#define VPEC_QUEUE6_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK 0x00000800L +#define VPEC_QUEUE6_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define VPEC_QUEUE6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define VPEC_QUEUE6_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define VPEC_QUEUE6_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define VPEC_QUEUE6_RB_CNTL__RB_VMID_MASK 0x0F000000L +//VPEC_QUEUE6_SCHEDULE_CNTL +#define VPEC_QUEUE6_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 +#define VPEC_QUEUE6_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 +#define VPEC_QUEUE6_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 +#define VPEC_QUEUE6_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 +#define VPEC_QUEUE6_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L +#define VPEC_QUEUE6_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL +#define VPEC_QUEUE6_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L +#define VPEC_QUEUE6_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L +//VPEC_QUEUE6_RB_BASE +#define VPEC_QUEUE6_RB_BASE__ADDR__SHIFT 0x0 +#define VPEC_QUEUE6_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE6_RB_BASE_HI +#define VPEC_QUEUE6_RB_BASE_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE6_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//VPEC_QUEUE6_RB_RPTR +#define VPEC_QUEUE6_RB_RPTR__OFFSET__SHIFT 0x0 +#define VPEC_QUEUE6_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//VPEC_QUEUE6_RB_RPTR_HI +#define VPEC_QUEUE6_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define VPEC_QUEUE6_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//VPEC_QUEUE6_RB_WPTR +#define VPEC_QUEUE6_RB_WPTR__OFFSET__SHIFT 0x0 +#define VPEC_QUEUE6_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//VPEC_QUEUE6_RB_WPTR_HI +#define VPEC_QUEUE6_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define VPEC_QUEUE6_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//VPEC_QUEUE6_RB_RPTR_ADDR_HI +#define VPEC_QUEUE6_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE6_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE6_RB_RPTR_ADDR_LO +#define VPEC_QUEUE6_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define VPEC_QUEUE6_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//VPEC_QUEUE6_RB_AQL_CNTL +#define VPEC_QUEUE6_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE6_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define VPEC_QUEUE6_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define VPEC_QUEUE6_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 +#define VPEC_QUEUE6_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 +#define VPEC_QUEUE6_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 +#define VPEC_QUEUE6_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE6_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define VPEC_QUEUE6_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +#define VPEC_QUEUE6_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L +#define VPEC_QUEUE6_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L +#define VPEC_QUEUE6_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L +//VPEC_QUEUE6_MINOR_PTR_UPDATE +#define VPEC_QUEUE6_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define VPEC_QUEUE6_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//VPEC_QUEUE6_CD_INFO +#define VPEC_QUEUE6_CD_INFO__CD_INFO__SHIFT 0x0 +#define VPEC_QUEUE6_CD_INFO__CD_INFO_MASK 0xFFFFFFFFL +//VPEC_QUEUE6_RB_PREEMPT +#define VPEC_QUEUE6_RB_PREEMPT__PREEMPT_REQ__SHIFT 0x0 +#define VPEC_QUEUE6_RB_PREEMPT__PREEMPT_REQ_MASK 0x00000001L +//VPEC_QUEUE6_SKIP_CNTL +#define VPEC_QUEUE6_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define VPEC_QUEUE6_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//VPEC_QUEUE6_DOORBELL +#define VPEC_QUEUE6_DOORBELL__ENABLE__SHIFT 0x1c +#define VPEC_QUEUE6_DOORBELL__CAPTURED__SHIFT 0x1e +#define VPEC_QUEUE6_DOORBELL__ENABLE_MASK 0x10000000L +#define VPEC_QUEUE6_DOORBELL__CAPTURED_MASK 0x40000000L +//VPEC_QUEUE6_DOORBELL_OFFSET +#define VPEC_QUEUE6_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE6_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//VPEC_QUEUE6_DUMMY0 +#define VPEC_QUEUE6_DUMMY0__DUMMY__SHIFT 0x0 +#define VPEC_QUEUE6_DUMMY0__DUMMY_MASK 0xFFFFFFFFL +//VPEC_QUEUE6_DUMMY1 +#define VPEC_QUEUE6_DUMMY1__VALUE__SHIFT 0x0 +#define VPEC_QUEUE6_DUMMY1__VALUE_MASK 0xFFFFFFFFL +//VPEC_QUEUE6_DUMMY2 +#define VPEC_QUEUE6_DUMMY2__VALUE__SHIFT 0x0 +#define VPEC_QUEUE6_DUMMY2__VALUE_MASK 0xFFFFFFFFL +//VPEC_QUEUE6_DUMMY3 +#define VPEC_QUEUE6_DUMMY3__VALUE__SHIFT 0x0 +#define VPEC_QUEUE6_DUMMY3__VALUE_MASK 0xFFFFFFFFL +//VPEC_QUEUE6_DUMMY4 +#define VPEC_QUEUE6_DUMMY4__VALUE__SHIFT 0x0 +#define VPEC_QUEUE6_DUMMY4__VALUE_MASK 0xFFFFFFFFL +//VPEC_QUEUE6_IB_CNTL +#define VPEC_QUEUE6_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE6_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define VPEC_QUEUE6_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define VPEC_QUEUE6_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define VPEC_QUEUE6_IB_CNTL__IB_PRIV__SHIFT 0x1f +#define VPEC_QUEUE6_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE6_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define VPEC_QUEUE6_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define VPEC_QUEUE6_IB_CNTL__CMD_VMID_MASK 0x000F0000L +#define VPEC_QUEUE6_IB_CNTL__IB_PRIV_MASK 0x80000000L +//VPEC_QUEUE6_IB_RPTR +#define VPEC_QUEUE6_IB_RPTR__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE6_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE6_IB_OFFSET +#define VPEC_QUEUE6_IB_OFFSET__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE6_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE6_IB_BASE_LO +#define VPEC_QUEUE6_IB_BASE_LO__ADDR__SHIFT 0x5 +#define VPEC_QUEUE6_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//VPEC_QUEUE6_IB_BASE_HI +#define VPEC_QUEUE6_IB_BASE_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE6_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE6_IB_SIZE +#define VPEC_QUEUE6_IB_SIZE__SIZE__SHIFT 0x0 +#define VPEC_QUEUE6_IB_SIZE__SIZE_MASK 0x000FFFFFL +//VPEC_QUEUE6_CMDIB_CNTL +#define VPEC_QUEUE6_CMDIB_CNTL__IB_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE6_CMDIB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define VPEC_QUEUE6_CMDIB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define VPEC_QUEUE6_CMDIB_CNTL__CMD_VMID__SHIFT 0x10 +#define VPEC_QUEUE6_CMDIB_CNTL__IB_PRIV__SHIFT 0x1f +#define VPEC_QUEUE6_CMDIB_CNTL__IB_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE6_CMDIB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define VPEC_QUEUE6_CMDIB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define VPEC_QUEUE6_CMDIB_CNTL__CMD_VMID_MASK 0x000F0000L +#define VPEC_QUEUE6_CMDIB_CNTL__IB_PRIV_MASK 0x80000000L +//VPEC_QUEUE6_CMDIB_RPTR +#define VPEC_QUEUE6_CMDIB_RPTR__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE6_CMDIB_RPTR__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE6_CMDIB_OFFSET +#define VPEC_QUEUE6_CMDIB_OFFSET__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE6_CMDIB_OFFSET__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE6_CMDIB_BASE_LO +#define VPEC_QUEUE6_CMDIB_BASE_LO__ADDR__SHIFT 0x5 +#define VPEC_QUEUE6_CMDIB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//VPEC_QUEUE6_CMDIB_BASE_HI +#define VPEC_QUEUE6_CMDIB_BASE_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE6_CMDIB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE6_CMDIB_SIZE +#define VPEC_QUEUE6_CMDIB_SIZE__SIZE__SHIFT 0x0 +#define VPEC_QUEUE6_CMDIB_SIZE__SIZE_MASK 0x000FFFFFL +//VPEC_QUEUE6_CSA_ADDR_LO +#define VPEC_QUEUE6_CSA_ADDR_LO__ADDR__SHIFT 0x0 +#define VPEC_QUEUE6_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE6_CSA_ADDR_HI +#define VPEC_QUEUE6_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE6_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE6_CONTEXT_STATUS +#define VPEC_QUEUE6_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define VPEC_QUEUE6_CONTEXT_STATUS__USE_IB__SHIFT 0x1 +#define VPEC_QUEUE6_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define VPEC_QUEUE6_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define VPEC_QUEUE6_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define VPEC_QUEUE6_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define VPEC_QUEUE6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define VPEC_QUEUE6_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb +#define VPEC_QUEUE6_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc +#define VPEC_QUEUE6_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 +#define VPEC_QUEUE6_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define VPEC_QUEUE6_CONTEXT_STATUS__USE_IB_MASK 0x00000002L +#define VPEC_QUEUE6_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define VPEC_QUEUE6_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define VPEC_QUEUE6_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define VPEC_QUEUE6_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define VPEC_QUEUE6_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +#define VPEC_QUEUE6_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L +#define VPEC_QUEUE6_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L +#define VPEC_QUEUE6_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L +//VPEC_QUEUE6_DOORBELL_LOG +#define VPEC_QUEUE6_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define VPEC_QUEUE6_DOORBELL_LOG__DATA__SHIFT 0x2 +#define VPEC_QUEUE6_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define VPEC_QUEUE6_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//VPEC_QUEUE6_IB_SUB_REMAIN +#define VPEC_QUEUE6_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define VPEC_QUEUE6_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//VPEC_QUEUE6_PREEMPT +#define VPEC_QUEUE6_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define VPEC_QUEUE6_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//VPEC_QUEUE7_RB_CNTL +#define VPEC_QUEUE7_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE7_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define VPEC_QUEUE7_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 +#define VPEC_QUEUE7_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define VPEC_QUEUE7_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa +#define VPEC_QUEUE7_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT 0xb +#define VPEC_QUEUE7_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define VPEC_QUEUE7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define VPEC_QUEUE7_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define VPEC_QUEUE7_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define VPEC_QUEUE7_RB_CNTL__RB_VMID__SHIFT 0x18 +#define VPEC_QUEUE7_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE7_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define VPEC_QUEUE7_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L +#define VPEC_QUEUE7_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define VPEC_QUEUE7_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L +#define VPEC_QUEUE7_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK 0x00000800L +#define VPEC_QUEUE7_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define VPEC_QUEUE7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define VPEC_QUEUE7_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define VPEC_QUEUE7_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define VPEC_QUEUE7_RB_CNTL__RB_VMID_MASK 0x0F000000L +//VPEC_QUEUE7_SCHEDULE_CNTL +#define VPEC_QUEUE7_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 +#define VPEC_QUEUE7_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 +#define VPEC_QUEUE7_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 +#define VPEC_QUEUE7_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 +#define VPEC_QUEUE7_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L +#define VPEC_QUEUE7_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL +#define VPEC_QUEUE7_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L +#define VPEC_QUEUE7_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L +//VPEC_QUEUE7_RB_BASE +#define VPEC_QUEUE7_RB_BASE__ADDR__SHIFT 0x0 +#define VPEC_QUEUE7_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE7_RB_BASE_HI +#define VPEC_QUEUE7_RB_BASE_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE7_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//VPEC_QUEUE7_RB_RPTR +#define VPEC_QUEUE7_RB_RPTR__OFFSET__SHIFT 0x0 +#define VPEC_QUEUE7_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//VPEC_QUEUE7_RB_RPTR_HI +#define VPEC_QUEUE7_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define VPEC_QUEUE7_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//VPEC_QUEUE7_RB_WPTR +#define VPEC_QUEUE7_RB_WPTR__OFFSET__SHIFT 0x0 +#define VPEC_QUEUE7_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//VPEC_QUEUE7_RB_WPTR_HI +#define VPEC_QUEUE7_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define VPEC_QUEUE7_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//VPEC_QUEUE7_RB_RPTR_ADDR_HI +#define VPEC_QUEUE7_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE7_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE7_RB_RPTR_ADDR_LO +#define VPEC_QUEUE7_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define VPEC_QUEUE7_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//VPEC_QUEUE7_RB_AQL_CNTL +#define VPEC_QUEUE7_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE7_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define VPEC_QUEUE7_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define VPEC_QUEUE7_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 +#define VPEC_QUEUE7_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 +#define VPEC_QUEUE7_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 +#define VPEC_QUEUE7_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE7_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define VPEC_QUEUE7_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +#define VPEC_QUEUE7_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L +#define VPEC_QUEUE7_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L +#define VPEC_QUEUE7_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L +//VPEC_QUEUE7_MINOR_PTR_UPDATE +#define VPEC_QUEUE7_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define VPEC_QUEUE7_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//VPEC_QUEUE7_CD_INFO +#define VPEC_QUEUE7_CD_INFO__CD_INFO__SHIFT 0x0 +#define VPEC_QUEUE7_CD_INFO__CD_INFO_MASK 0xFFFFFFFFL +//VPEC_QUEUE7_RB_PREEMPT +#define VPEC_QUEUE7_RB_PREEMPT__PREEMPT_REQ__SHIFT 0x0 +#define VPEC_QUEUE7_RB_PREEMPT__PREEMPT_REQ_MASK 0x00000001L +//VPEC_QUEUE7_SKIP_CNTL +#define VPEC_QUEUE7_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define VPEC_QUEUE7_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//VPEC_QUEUE7_DOORBELL +#define VPEC_QUEUE7_DOORBELL__ENABLE__SHIFT 0x1c +#define VPEC_QUEUE7_DOORBELL__CAPTURED__SHIFT 0x1e +#define VPEC_QUEUE7_DOORBELL__ENABLE_MASK 0x10000000L +#define VPEC_QUEUE7_DOORBELL__CAPTURED_MASK 0x40000000L +//VPEC_QUEUE7_DOORBELL_OFFSET +#define VPEC_QUEUE7_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE7_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//VPEC_QUEUE7_DUMMY0 +#define VPEC_QUEUE7_DUMMY0__DUMMY__SHIFT 0x0 +#define VPEC_QUEUE7_DUMMY0__DUMMY_MASK 0xFFFFFFFFL +//VPEC_QUEUE7_DUMMY1 +#define VPEC_QUEUE7_DUMMY1__VALUE__SHIFT 0x0 +#define VPEC_QUEUE7_DUMMY1__VALUE_MASK 0xFFFFFFFFL +//VPEC_QUEUE7_DUMMY2 +#define VPEC_QUEUE7_DUMMY2__VALUE__SHIFT 0x0 +#define VPEC_QUEUE7_DUMMY2__VALUE_MASK 0xFFFFFFFFL +//VPEC_QUEUE7_DUMMY3 +#define VPEC_QUEUE7_DUMMY3__VALUE__SHIFT 0x0 +#define VPEC_QUEUE7_DUMMY3__VALUE_MASK 0xFFFFFFFFL +//VPEC_QUEUE7_DUMMY4 +#define VPEC_QUEUE7_DUMMY4__VALUE__SHIFT 0x0 +#define VPEC_QUEUE7_DUMMY4__VALUE_MASK 0xFFFFFFFFL +//VPEC_QUEUE7_IB_CNTL +#define VPEC_QUEUE7_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE7_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define VPEC_QUEUE7_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define VPEC_QUEUE7_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define VPEC_QUEUE7_IB_CNTL__IB_PRIV__SHIFT 0x1f +#define VPEC_QUEUE7_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE7_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define VPEC_QUEUE7_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define VPEC_QUEUE7_IB_CNTL__CMD_VMID_MASK 0x000F0000L +#define VPEC_QUEUE7_IB_CNTL__IB_PRIV_MASK 0x80000000L +//VPEC_QUEUE7_IB_RPTR +#define VPEC_QUEUE7_IB_RPTR__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE7_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE7_IB_OFFSET +#define VPEC_QUEUE7_IB_OFFSET__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE7_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE7_IB_BASE_LO +#define VPEC_QUEUE7_IB_BASE_LO__ADDR__SHIFT 0x5 +#define VPEC_QUEUE7_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//VPEC_QUEUE7_IB_BASE_HI +#define VPEC_QUEUE7_IB_BASE_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE7_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE7_IB_SIZE +#define VPEC_QUEUE7_IB_SIZE__SIZE__SHIFT 0x0 +#define VPEC_QUEUE7_IB_SIZE__SIZE_MASK 0x000FFFFFL +//VPEC_QUEUE7_CMDIB_CNTL +#define VPEC_QUEUE7_CMDIB_CNTL__IB_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE7_CMDIB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define VPEC_QUEUE7_CMDIB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define VPEC_QUEUE7_CMDIB_CNTL__CMD_VMID__SHIFT 0x10 +#define VPEC_QUEUE7_CMDIB_CNTL__IB_PRIV__SHIFT 0x1f +#define VPEC_QUEUE7_CMDIB_CNTL__IB_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE7_CMDIB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define VPEC_QUEUE7_CMDIB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define VPEC_QUEUE7_CMDIB_CNTL__CMD_VMID_MASK 0x000F0000L +#define VPEC_QUEUE7_CMDIB_CNTL__IB_PRIV_MASK 0x80000000L +//VPEC_QUEUE7_CMDIB_RPTR +#define VPEC_QUEUE7_CMDIB_RPTR__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE7_CMDIB_RPTR__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE7_CMDIB_OFFSET +#define VPEC_QUEUE7_CMDIB_OFFSET__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE7_CMDIB_OFFSET__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE7_CMDIB_BASE_LO +#define VPEC_QUEUE7_CMDIB_BASE_LO__ADDR__SHIFT 0x5 +#define VPEC_QUEUE7_CMDIB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//VPEC_QUEUE7_CMDIB_BASE_HI +#define VPEC_QUEUE7_CMDIB_BASE_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE7_CMDIB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE7_CMDIB_SIZE +#define VPEC_QUEUE7_CMDIB_SIZE__SIZE__SHIFT 0x0 +#define VPEC_QUEUE7_CMDIB_SIZE__SIZE_MASK 0x000FFFFFL +//VPEC_QUEUE7_CSA_ADDR_LO +#define VPEC_QUEUE7_CSA_ADDR_LO__ADDR__SHIFT 0x0 +#define VPEC_QUEUE7_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE7_CSA_ADDR_HI +#define VPEC_QUEUE7_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE7_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE7_CONTEXT_STATUS +#define VPEC_QUEUE7_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define VPEC_QUEUE7_CONTEXT_STATUS__USE_IB__SHIFT 0x1 +#define VPEC_QUEUE7_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define VPEC_QUEUE7_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define VPEC_QUEUE7_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define VPEC_QUEUE7_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define VPEC_QUEUE7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define VPEC_QUEUE7_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb +#define VPEC_QUEUE7_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc +#define VPEC_QUEUE7_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 +#define VPEC_QUEUE7_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define VPEC_QUEUE7_CONTEXT_STATUS__USE_IB_MASK 0x00000002L +#define VPEC_QUEUE7_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define VPEC_QUEUE7_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define VPEC_QUEUE7_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define VPEC_QUEUE7_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define VPEC_QUEUE7_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +#define VPEC_QUEUE7_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L +#define VPEC_QUEUE7_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L +#define VPEC_QUEUE7_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L +//VPEC_QUEUE7_DOORBELL_LOG +#define VPEC_QUEUE7_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define VPEC_QUEUE7_DOORBELL_LOG__DATA__SHIFT 0x2 +#define VPEC_QUEUE7_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define VPEC_QUEUE7_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//VPEC_QUEUE7_IB_SUB_REMAIN +#define VPEC_QUEUE7_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define VPEC_QUEUE7_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//VPEC_QUEUE7_PREEMPT +#define VPEC_QUEUE7_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define VPEC_QUEUE7_PREEMPT__IB_PREEMPT_MASK 0x00000001L + + +// addressBlock: vpe_vpep_vpdpp0_dispdec_vpcnvc_cfg_dispdec +//VPCNVC_SURFACE_PIXEL_FORMAT +#define VPCNVC_SURFACE_PIXEL_FORMAT__VPCNVC_SURFACE_PIXEL_FORMAT__SHIFT 0x0 +#define VPCNVC_SURFACE_PIXEL_FORMAT__VPCNVC_SURFACE_PIXEL_FORMAT_MASK 0x0000007FL +//VPCNVC_FORMAT_CONTROL +#define VPCNVC_FORMAT_CONTROL__FORMAT_EXPANSION_MODE__SHIFT 0x0 +#define VPCNVC_FORMAT_CONTROL__FORMAT_CNV16__SHIFT 0x4 +#define VPCNVC_FORMAT_CONTROL__ALPHA_EN__SHIFT 0x8 +#define VPCNVC_FORMAT_CONTROL__VPCNVC_BYPASS__SHIFT 0xc +#define VPCNVC_FORMAT_CONTROL__VPCNVC_BYPASS_MSB_ALIGN__SHIFT 0xd +#define VPCNVC_FORMAT_CONTROL__CLAMP_POSITIVE__SHIFT 0x10 +#define VPCNVC_FORMAT_CONTROL__CLAMP_POSITIVE_C__SHIFT 0x11 +#define VPCNVC_FORMAT_CONTROL__VPCNVC_UPDATE_PENDING__SHIFT 0x14 +#define VPCNVC_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK 0x00000001L +#define VPCNVC_FORMAT_CONTROL__FORMAT_CNV16_MASK 0x00000010L +#define VPCNVC_FORMAT_CONTROL__ALPHA_EN_MASK 0x00000100L +#define VPCNVC_FORMAT_CONTROL__VPCNVC_BYPASS_MASK 0x00001000L +#define VPCNVC_FORMAT_CONTROL__VPCNVC_BYPASS_MSB_ALIGN_MASK 0x00002000L +#define VPCNVC_FORMAT_CONTROL__CLAMP_POSITIVE_MASK 0x00010000L +#define VPCNVC_FORMAT_CONTROL__CLAMP_POSITIVE_C_MASK 0x00020000L +#define VPCNVC_FORMAT_CONTROL__VPCNVC_UPDATE_PENDING_MASK 0x00100000L +//VPCNVC_FCNV_FP_BIAS_R +#define VPCNVC_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R__SHIFT 0x0 +#define VPCNVC_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R_MASK 0x0007FFFFL +//VPCNVC_FCNV_FP_BIAS_G +#define VPCNVC_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G__SHIFT 0x0 +#define VPCNVC_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G_MASK 0x0007FFFFL +//VPCNVC_FCNV_FP_BIAS_B +#define VPCNVC_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B__SHIFT 0x0 +#define VPCNVC_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B_MASK 0x0007FFFFL +//VPCNVC_FCNV_FP_SCALE_R +#define VPCNVC_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R__SHIFT 0x0 +#define VPCNVC_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R_MASK 0x0007FFFFL +//VPCNVC_FCNV_FP_SCALE_G +#define VPCNVC_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G__SHIFT 0x0 +#define VPCNVC_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G_MASK 0x0007FFFFL +//VPCNVC_FCNV_FP_SCALE_B +#define VPCNVC_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B__SHIFT 0x0 +#define VPCNVC_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B_MASK 0x0007FFFFL +//VPCNVC_COLOR_KEYER_CONTROL +#define VPCNVC_COLOR_KEYER_CONTROL__COLOR_KEYER_EN__SHIFT 0x0 +#define VPCNVC_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE__SHIFT 0x4 +#define VPCNVC_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK 0x00000001L +#define VPCNVC_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK 0x00000030L +//VPCNVC_COLOR_KEYER_ALPHA +#define VPCNVC_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW__SHIFT 0x0 +#define VPCNVC_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH__SHIFT 0x10 +#define VPCNVC_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK 0x0000FFFFL +#define VPCNVC_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK 0xFFFF0000L +//VPCNVC_COLOR_KEYER_RED +#define VPCNVC_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW__SHIFT 0x0 +#define VPCNVC_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH__SHIFT 0x10 +#define VPCNVC_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK 0x0000FFFFL +#define VPCNVC_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK 0xFFFF0000L +//VPCNVC_COLOR_KEYER_GREEN +#define VPCNVC_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW__SHIFT 0x0 +#define VPCNVC_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH__SHIFT 0x10 +#define VPCNVC_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK 0x0000FFFFL +#define VPCNVC_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK 0xFFFF0000L +//VPCNVC_COLOR_KEYER_BLUE +#define VPCNVC_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW__SHIFT 0x0 +#define VPCNVC_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH__SHIFT 0x10 +#define VPCNVC_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK 0x0000FFFFL +#define VPCNVC_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK 0xFFFF0000L +//VPCNVC_ALPHA_2BIT_LUT +#define VPCNVC_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0__SHIFT 0x0 +#define VPCNVC_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1__SHIFT 0x8 +#define VPCNVC_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2__SHIFT 0x10 +#define VPCNVC_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3__SHIFT 0x18 +#define VPCNVC_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0_MASK 0x000000FFL +#define VPCNVC_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1_MASK 0x0000FF00L +#define VPCNVC_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2_MASK 0x00FF0000L +#define VPCNVC_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3_MASK 0xFF000000L +//VPCNVC_PRE_DEALPHA +#define VPCNVC_PRE_DEALPHA__PRE_DEALPHA_EN__SHIFT 0x0 +#define VPCNVC_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN__SHIFT 0x4 +#define VPCNVC_PRE_DEALPHA__PRE_DEALPHA_EN_MASK 0x00000001L +#define VPCNVC_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN_MASK 0x00000010L +//VPCNVC_PRE_CSC_MODE +#define VPCNVC_PRE_CSC_MODE__PRE_CSC_MODE__SHIFT 0x0 +#define VPCNVC_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT__SHIFT 0x2 +#define VPCNVC_PRE_CSC_MODE__PRE_CSC_MODE_MASK 0x00000001L +#define VPCNVC_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT_MASK 0x00000004L +//VPCNVC_PRE_CSC_C11_C12 +#define VPCNVC_PRE_CSC_C11_C12__PRE_CSC_C11__SHIFT 0x0 +#define VPCNVC_PRE_CSC_C11_C12__PRE_CSC_C12__SHIFT 0x10 +#define VPCNVC_PRE_CSC_C11_C12__PRE_CSC_C11_MASK 0x0000FFFFL +#define VPCNVC_PRE_CSC_C11_C12__PRE_CSC_C12_MASK 0xFFFF0000L +//VPCNVC_PRE_CSC_C13_C14 +#define VPCNVC_PRE_CSC_C13_C14__PRE_CSC_C13__SHIFT 0x0 +#define VPCNVC_PRE_CSC_C13_C14__PRE_CSC_C14__SHIFT 0x10 +#define VPCNVC_PRE_CSC_C13_C14__PRE_CSC_C13_MASK 0x0000FFFFL +#define VPCNVC_PRE_CSC_C13_C14__PRE_CSC_C14_MASK 0xFFFF0000L +//VPCNVC_PRE_CSC_C21_C22 +#define VPCNVC_PRE_CSC_C21_C22__PRE_CSC_C21__SHIFT 0x0 +#define VPCNVC_PRE_CSC_C21_C22__PRE_CSC_C22__SHIFT 0x10 +#define VPCNVC_PRE_CSC_C21_C22__PRE_CSC_C21_MASK 0x0000FFFFL +#define VPCNVC_PRE_CSC_C21_C22__PRE_CSC_C22_MASK 0xFFFF0000L +//VPCNVC_PRE_CSC_C23_C24 +#define VPCNVC_PRE_CSC_C23_C24__PRE_CSC_C23__SHIFT 0x0 +#define VPCNVC_PRE_CSC_C23_C24__PRE_CSC_C24__SHIFT 0x10 +#define VPCNVC_PRE_CSC_C23_C24__PRE_CSC_C23_MASK 0x0000FFFFL +#define VPCNVC_PRE_CSC_C23_C24__PRE_CSC_C24_MASK 0xFFFF0000L +//VPCNVC_PRE_CSC_C31_C32 +#define VPCNVC_PRE_CSC_C31_C32__PRE_CSC_C31__SHIFT 0x0 +#define VPCNVC_PRE_CSC_C31_C32__PRE_CSC_C32__SHIFT 0x10 +#define VPCNVC_PRE_CSC_C31_C32__PRE_CSC_C31_MASK 0x0000FFFFL +#define VPCNVC_PRE_CSC_C31_C32__PRE_CSC_C32_MASK 0xFFFF0000L +//VPCNVC_PRE_CSC_C33_C34 +#define VPCNVC_PRE_CSC_C33_C34__PRE_CSC_C33__SHIFT 0x0 +#define VPCNVC_PRE_CSC_C33_C34__PRE_CSC_C34__SHIFT 0x10 +#define VPCNVC_PRE_CSC_C33_C34__PRE_CSC_C33_MASK 0x0000FFFFL +#define VPCNVC_PRE_CSC_C33_C34__PRE_CSC_C34_MASK 0xFFFF0000L +//VPCNVC_COEF_FORMAT +#define VPCNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT__SHIFT 0x0 +#define VPCNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT_MASK 0x00000001L +//VPCNVC_PRE_DEGAM +#define VPCNVC_PRE_DEGAM__PRE_DEGAM_MODE__SHIFT 0x0 +#define VPCNVC_PRE_DEGAM__PRE_DEGAM_SELECT__SHIFT 0x4 +#define VPCNVC_PRE_DEGAM__PRE_DEGAM_MODE_MASK 0x00000003L +#define VPCNVC_PRE_DEGAM__PRE_DEGAM_SELECT_MASK 0x00000070L +//VPCNVC_PRE_REALPHA +#define VPCNVC_PRE_REALPHA__PRE_REALPHA_EN__SHIFT 0x0 +#define VPCNVC_PRE_REALPHA__PRE_REALPHA_ABLND_EN__SHIFT 0x4 +#define VPCNVC_PRE_REALPHA__PRE_REALPHA_EN_MASK 0x00000001L +#define VPCNVC_PRE_REALPHA__PRE_REALPHA_ABLND_EN_MASK 0x00000010L +//VPCNVC_CFG_TEST_DEBUG_INDEX +#define VPCNVC_CFG_TEST_DEBUG_INDEX__VPCNVC_CFG_TEST_DEBUG_INDEX__SHIFT 0x0 +#define VPCNVC_CFG_TEST_DEBUG_INDEX__VPCNVC_CFG_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define VPCNVC_CFG_TEST_DEBUG_INDEX__VPCNVC_CFG_TEST_DEBUG_INDEX_MASK 0x000000FFL +#define VPCNVC_CFG_TEST_DEBUG_INDEX__VPCNVC_CFG_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +//VPCNVC_CFG_TEST_DEBUG_DATA +#define VPCNVC_CFG_TEST_DEBUG_DATA__VPCNVC_CFG_TEST_DEBUG_DATA__SHIFT 0x0 +#define VPCNVC_CFG_TEST_DEBUG_DATA__VPCNVC_CFG_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: vpe_vpep_vpdpp0_dispdec_vpdscl_dispdec +//VPDSCL_COEF_RAM_TAP_SELECT +#define VPDSCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT 0x0 +#define VPDSCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT 0x8 +#define VPDSCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT 0x10 +#define VPDSCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK 0x00000003L +#define VPDSCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK 0x00003F00L +#define VPDSCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK 0x00030000L +//VPDSCL_COEF_RAM_TAP_DATA +#define VPDSCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT 0x0 +#define VPDSCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf +#define VPDSCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT 0x10 +#define VPDSCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f +#define VPDSCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK 0x00003FFFL +#define VPDSCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK 0x00008000L +#define VPDSCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK 0x3FFF0000L +#define VPDSCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK 0x80000000L +//VPDSCL_MODE +#define VPDSCL_MODE__VPDSCL_MODE__SHIFT 0x0 +#define VPDSCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT 0xc +#define VPDSCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT 0x10 +#define VPDSCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT 0x14 +#define VPDSCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT 0x18 +#define VPDSCL_MODE__VPDSCL_MODE_MASK 0x00000007L +#define VPDSCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK 0x00001000L +#define VPDSCL_MODE__SCL_CHROMA_COEF_MODE_MASK 0x00010000L +#define VPDSCL_MODE__SCL_ALPHA_COEF_MODE_MASK 0x00100000L +#define VPDSCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK 0x01000000L +//VPDSCL_TAP_CONTROL +#define VPDSCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT 0x0 +#define VPDSCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT 0x4 +#define VPDSCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT 0x8 +#define VPDSCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT 0xc +#define VPDSCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK 0x00000007L +#define VPDSCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK 0x00000070L +#define VPDSCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK 0x00000700L +#define VPDSCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK 0x00007000L +//VPDSCL_CONTROL +#define VPDSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x0 +#define VPDSCL_CONTROL__SCL_BOUNDARY_MODE_MASK 0x00000001L +//VPDSCL_2TAP_CONTROL +#define VPDSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x0 +#define VPDSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT 0x4 +#define VPDSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT 0x8 +#define VPDSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x10 +#define VPDSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT 0x14 +#define VPDSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT 0x18 +#define VPDSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x00000001L +#define VPDSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK 0x00000010L +#define VPDSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK 0x00000700L +#define VPDSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x00010000L +#define VPDSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK 0x00100000L +#define VPDSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK 0x07000000L +//VPDSCL_MANUAL_REPLICATE_CONTROL +#define VPDSCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x0 +#define VPDSCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x8 +#define VPDSCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0x0000000FL +#define VPDSCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0x00000F00L +//VPDSCL_HORZ_FILTER_SCALE_RATIO +#define VPDSCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x0 +#define VPDSCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x07FFFFFFL +//VPDSCL_HORZ_FILTER_INIT +#define VPDSCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x0 +#define VPDSCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x18 +#define VPDSCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0x00FFFFFFL +#define VPDSCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0x0F000000L +//VPDSCL_HORZ_FILTER_SCALE_RATIO_C +#define VPDSCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT 0x0 +#define VPDSCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK 0x07FFFFFFL +//VPDSCL_HORZ_FILTER_INIT_C +#define VPDSCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT 0x0 +#define VPDSCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT 0x18 +#define VPDSCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK 0x00FFFFFFL +#define VPDSCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK 0x0F000000L +//VPDSCL_VERT_FILTER_SCALE_RATIO +#define VPDSCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x0 +#define VPDSCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x07FFFFFFL +//VPDSCL_VERT_FILTER_INIT +#define VPDSCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x0 +#define VPDSCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x18 +#define VPDSCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0x00FFFFFFL +#define VPDSCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x0F000000L +//VPDSCL_VERT_FILTER_INIT_BOT +#define VPDSCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x0 +#define VPDSCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x18 +#define VPDSCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0x00FFFFFFL +#define VPDSCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x0F000000L +//VPDSCL_VERT_FILTER_SCALE_RATIO_C +#define VPDSCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT 0x0 +#define VPDSCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK 0x07FFFFFFL +//VPDSCL_VERT_FILTER_INIT_C +#define VPDSCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT 0x0 +#define VPDSCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT 0x18 +#define VPDSCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK 0x00FFFFFFL +#define VPDSCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK 0x0F000000L +//VPDSCL_VERT_FILTER_INIT_BOT_C +#define VPDSCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT 0x0 +#define VPDSCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT 0x18 +#define VPDSCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK 0x00FFFFFFL +#define VPDSCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK 0x0F000000L +//VPDSCL_BLACK_COLOR +#define VPDSCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y__SHIFT 0x0 +#define VPDSCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR__SHIFT 0x10 +#define VPDSCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y_MASK 0x0000FFFFL +#define VPDSCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR_MASK 0xFFFF0000L +//VPDSCL_UPDATE +#define VPDSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x0 +#define VPDSCL_UPDATE__SCL_UPDATE_PENDING_MASK 0x00000001L +//VPDSCL_AUTOCAL +#define VPDSCL_AUTOCAL__AUTOCAL_MODE__SHIFT 0x0 +#define VPDSCL_AUTOCAL__AUTOCAL_MODE_MASK 0x00000003L +//VPDSCL_EXT_OVERSCAN_LEFT_RIGHT +#define VPDSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x0 +#define VPDSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x10 +#define VPDSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x00001FFFL +#define VPDSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x1FFF0000L +//VPDSCL_EXT_OVERSCAN_TOP_BOTTOM +#define VPDSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x0 +#define VPDSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x10 +#define VPDSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x00001FFFL +#define VPDSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x1FFF0000L +//VPOTG_H_BLANK +#define VPOTG_H_BLANK__OTG_H_BLANK_START__SHIFT 0x0 +#define VPOTG_H_BLANK__OTG_H_BLANK_END__SHIFT 0x10 +#define VPOTG_H_BLANK__OTG_H_BLANK_START_MASK 0x00003FFFL +#define VPOTG_H_BLANK__OTG_H_BLANK_END_MASK 0x3FFF0000L +//VPOTG_V_BLANK +#define VPOTG_V_BLANK__OTG_V_BLANK_START__SHIFT 0x0 +#define VPOTG_V_BLANK__OTG_V_BLANK_END__SHIFT 0x10 +#define VPOTG_V_BLANK__OTG_V_BLANK_START_MASK 0x00003FFFL +#define VPOTG_V_BLANK__OTG_V_BLANK_END_MASK 0x3FFF0000L +//VPDSCL_RECOUT_START +#define VPDSCL_RECOUT_START__RECOUT_START_X__SHIFT 0x0 +#define VPDSCL_RECOUT_START__RECOUT_START_Y__SHIFT 0x10 +#define VPDSCL_RECOUT_START__RECOUT_START_X_MASK 0x00001FFFL +#define VPDSCL_RECOUT_START__RECOUT_START_Y_MASK 0x1FFF0000L +//VPDSCL_RECOUT_SIZE +#define VPDSCL_RECOUT_SIZE__RECOUT_WIDTH__SHIFT 0x0 +#define VPDSCL_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT 0x10 +#define VPDSCL_RECOUT_SIZE__RECOUT_WIDTH_MASK 0x00003FFFL +#define VPDSCL_RECOUT_SIZE__RECOUT_HEIGHT_MASK 0x3FFF0000L +//VPMPC_SIZE +#define VPMPC_SIZE__VPMPC_WIDTH__SHIFT 0x0 +#define VPMPC_SIZE__VPMPC_HEIGHT__SHIFT 0x10 +#define VPMPC_SIZE__VPMPC_WIDTH_MASK 0x00003FFFL +#define VPMPC_SIZE__VPMPC_HEIGHT_MASK 0x3FFF0000L +//VPLB_DATA_FORMAT +#define VPLB_DATA_FORMAT__ALPHA_EN__SHIFT 0x4 +#define VPLB_DATA_FORMAT__ALPHA_EN_MASK 0x00000010L +//VPLB_MEMORY_CTRL +#define VPLB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT 0x0 +#define VPLB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT 0x8 +#define VPLB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x10 +#define VPLB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT 0x18 +#define VPLB_MEMORY_CTRL__MEMORY_CONFIG_MASK 0x00000003L +#define VPLB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK 0x00003F00L +#define VPLB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0x007F0000L +#define VPLB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK 0x7F000000L +//VPLB_V_COUNTER +#define VPLB_V_COUNTER__V_COUNTER__SHIFT 0x0 +#define VPLB_V_COUNTER__V_COUNTER_C__SHIFT 0x10 +#define VPLB_V_COUNTER__V_COUNTER_MASK 0x00001FFFL +#define VPLB_V_COUNTER__V_COUNTER_C_MASK 0x1FFF0000L +//VPDSCL_MEM_PWR_CTRL +#define VPDSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT 0x0 +#define VPDSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT 0x2 +#define VPDSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT 0x4 +#define VPDSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT 0x6 +#define VPDSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT 0x8 +#define VPDSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT 0xa +#define VPDSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE__SHIFT 0x1c +#define VPDSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK 0x00000003L +#define VPDSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK 0x00000004L +#define VPDSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK 0x00000030L +#define VPDSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK 0x00000040L +#define VPDSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK 0x00000300L +#define VPDSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK 0x00000400L +#define VPDSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE_MASK 0x10000000L +//VPDSCL_MEM_PWR_STATUS +#define VPDSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT 0x0 +#define VPDSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT 0x2 +#define VPDSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT 0x4 +#define VPDSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK 0x00000003L +#define VPDSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK 0x0000000CL +#define VPDSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK 0x00000030L +//VPDSCL_DEBUG +#define VPDSCL_DEBUG__SCL_DEBUG__SHIFT 0x0 +#define VPDSCL_DEBUG__SCL_DEBUG_MASK 0xFFFFFFFFL +//VPDSCL_TEST_DEBUG_INDEX +#define VPDSCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_INDEX__SHIFT 0x0 +#define VPDSCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define VPDSCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_INDEX_MASK 0x000000FFL +#define VPDSCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +//VPDSCL_TEST_DEBUG_DATA +#define VPDSCL_TEST_DEBUG_DATA__SCL_TEST_DEBUG_DATA__SHIFT 0x0 +#define VPDSCL_TEST_DEBUG_DATA__SCL_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: vpe_vpep_vpdpp0_dispdec_vpcm_dispdec +//VPCM_CONTROL +#define VPCM_CONTROL__VPCM_BYPASS__SHIFT 0x0 +#define VPCM_CONTROL__VPCM_UPDATE_PENDING__SHIFT 0x8 +#define VPCM_CONTROL__VPCM_BYPASS_MASK 0x00000001L +#define VPCM_CONTROL__VPCM_UPDATE_PENDING_MASK 0x00000100L +//VPCM_POST_CSC_CONTROL +#define VPCM_POST_CSC_CONTROL__VPCM_POST_CSC_MODE__SHIFT 0x0 +#define VPCM_POST_CSC_CONTROL__VPCM_POST_CSC_MODE_CURRENT__SHIFT 0x2 +#define VPCM_POST_CSC_CONTROL__VPCM_POST_CSC_MODE_MASK 0x00000001L +#define VPCM_POST_CSC_CONTROL__VPCM_POST_CSC_MODE_CURRENT_MASK 0x00000004L +//VPCM_POST_CSC_C11_C12 +#define VPCM_POST_CSC_C11_C12__VPCM_POST_CSC_C11__SHIFT 0x0 +#define VPCM_POST_CSC_C11_C12__VPCM_POST_CSC_C12__SHIFT 0x10 +#define VPCM_POST_CSC_C11_C12__VPCM_POST_CSC_C11_MASK 0x0000FFFFL +#define VPCM_POST_CSC_C11_C12__VPCM_POST_CSC_C12_MASK 0xFFFF0000L +//VPCM_POST_CSC_C13_C14 +#define VPCM_POST_CSC_C13_C14__VPCM_POST_CSC_C13__SHIFT 0x0 +#define VPCM_POST_CSC_C13_C14__VPCM_POST_CSC_C14__SHIFT 0x10 +#define VPCM_POST_CSC_C13_C14__VPCM_POST_CSC_C13_MASK 0x0000FFFFL +#define VPCM_POST_CSC_C13_C14__VPCM_POST_CSC_C14_MASK 0xFFFF0000L +//VPCM_POST_CSC_C21_C22 +#define VPCM_POST_CSC_C21_C22__VPCM_POST_CSC_C21__SHIFT 0x0 +#define VPCM_POST_CSC_C21_C22__VPCM_POST_CSC_C22__SHIFT 0x10 +#define VPCM_POST_CSC_C21_C22__VPCM_POST_CSC_C21_MASK 0x0000FFFFL +#define VPCM_POST_CSC_C21_C22__VPCM_POST_CSC_C22_MASK 0xFFFF0000L +//VPCM_POST_CSC_C23_C24 +#define VPCM_POST_CSC_C23_C24__VPCM_POST_CSC_C23__SHIFT 0x0 +#define VPCM_POST_CSC_C23_C24__VPCM_POST_CSC_C24__SHIFT 0x10 +#define VPCM_POST_CSC_C23_C24__VPCM_POST_CSC_C23_MASK 0x0000FFFFL +#define VPCM_POST_CSC_C23_C24__VPCM_POST_CSC_C24_MASK 0xFFFF0000L +//VPCM_POST_CSC_C31_C32 +#define VPCM_POST_CSC_C31_C32__VPCM_POST_CSC_C31__SHIFT 0x0 +#define VPCM_POST_CSC_C31_C32__VPCM_POST_CSC_C32__SHIFT 0x10 +#define VPCM_POST_CSC_C31_C32__VPCM_POST_CSC_C31_MASK 0x0000FFFFL +#define VPCM_POST_CSC_C31_C32__VPCM_POST_CSC_C32_MASK 0xFFFF0000L +//VPCM_POST_CSC_C33_C34 +#define VPCM_POST_CSC_C33_C34__VPCM_POST_CSC_C33__SHIFT 0x0 +#define VPCM_POST_CSC_C33_C34__VPCM_POST_CSC_C34__SHIFT 0x10 +#define VPCM_POST_CSC_C33_C34__VPCM_POST_CSC_C33_MASK 0x0000FFFFL +#define VPCM_POST_CSC_C33_C34__VPCM_POST_CSC_C34_MASK 0xFFFF0000L +//VPCM_GAMUT_REMAP_CONTROL +#define VPCM_GAMUT_REMAP_CONTROL__VPCM_GAMUT_REMAP_MODE__SHIFT 0x0 +#define VPCM_GAMUT_REMAP_CONTROL__VPCM_GAMUT_REMAP_MODE_CURRENT__SHIFT 0x2 +#define VPCM_GAMUT_REMAP_CONTROL__VPCM_GAMUT_REMAP_MODE_MASK 0x00000001L +#define VPCM_GAMUT_REMAP_CONTROL__VPCM_GAMUT_REMAP_MODE_CURRENT_MASK 0x00000004L +//VPCM_GAMUT_REMAP_C11_C12 +#define VPCM_GAMUT_REMAP_C11_C12__VPCM_GAMUT_REMAP_C11__SHIFT 0x0 +#define VPCM_GAMUT_REMAP_C11_C12__VPCM_GAMUT_REMAP_C12__SHIFT 0x10 +#define VPCM_GAMUT_REMAP_C11_C12__VPCM_GAMUT_REMAP_C11_MASK 0x0000FFFFL +#define VPCM_GAMUT_REMAP_C11_C12__VPCM_GAMUT_REMAP_C12_MASK 0xFFFF0000L +//VPCM_GAMUT_REMAP_C13_C14 +#define VPCM_GAMUT_REMAP_C13_C14__VPCM_GAMUT_REMAP_C13__SHIFT 0x0 +#define VPCM_GAMUT_REMAP_C13_C14__VPCM_GAMUT_REMAP_C14__SHIFT 0x10 +#define VPCM_GAMUT_REMAP_C13_C14__VPCM_GAMUT_REMAP_C13_MASK 0x0000FFFFL +#define VPCM_GAMUT_REMAP_C13_C14__VPCM_GAMUT_REMAP_C14_MASK 0xFFFF0000L +//VPCM_GAMUT_REMAP_C21_C22 +#define VPCM_GAMUT_REMAP_C21_C22__VPCM_GAMUT_REMAP_C21__SHIFT 0x0 +#define VPCM_GAMUT_REMAP_C21_C22__VPCM_GAMUT_REMAP_C22__SHIFT 0x10 +#define VPCM_GAMUT_REMAP_C21_C22__VPCM_GAMUT_REMAP_C21_MASK 0x0000FFFFL +#define VPCM_GAMUT_REMAP_C21_C22__VPCM_GAMUT_REMAP_C22_MASK 0xFFFF0000L +//VPCM_GAMUT_REMAP_C23_C24 +#define VPCM_GAMUT_REMAP_C23_C24__VPCM_GAMUT_REMAP_C23__SHIFT 0x0 +#define VPCM_GAMUT_REMAP_C23_C24__VPCM_GAMUT_REMAP_C24__SHIFT 0x10 +#define VPCM_GAMUT_REMAP_C23_C24__VPCM_GAMUT_REMAP_C23_MASK 0x0000FFFFL +#define VPCM_GAMUT_REMAP_C23_C24__VPCM_GAMUT_REMAP_C24_MASK 0xFFFF0000L +//VPCM_GAMUT_REMAP_C31_C32 +#define VPCM_GAMUT_REMAP_C31_C32__VPCM_GAMUT_REMAP_C31__SHIFT 0x0 +#define VPCM_GAMUT_REMAP_C31_C32__VPCM_GAMUT_REMAP_C32__SHIFT 0x10 +#define VPCM_GAMUT_REMAP_C31_C32__VPCM_GAMUT_REMAP_C31_MASK 0x0000FFFFL +#define VPCM_GAMUT_REMAP_C31_C32__VPCM_GAMUT_REMAP_C32_MASK 0xFFFF0000L +//VPCM_GAMUT_REMAP_C33_C34 +#define VPCM_GAMUT_REMAP_C33_C34__VPCM_GAMUT_REMAP_C33__SHIFT 0x0 +#define VPCM_GAMUT_REMAP_C33_C34__VPCM_GAMUT_REMAP_C34__SHIFT 0x10 +#define VPCM_GAMUT_REMAP_C33_C34__VPCM_GAMUT_REMAP_C33_MASK 0x0000FFFFL +#define VPCM_GAMUT_REMAP_C33_C34__VPCM_GAMUT_REMAP_C34_MASK 0xFFFF0000L +//VPCM_BIAS_CR_R +#define VPCM_BIAS_CR_R__VPCM_BIAS_CR_R__SHIFT 0x0 +#define VPCM_BIAS_CR_R__VPCM_BIAS_CR_R_MASK 0x0000FFFFL +//VPCM_BIAS_Y_G_CB_B +#define VPCM_BIAS_Y_G_CB_B__VPCM_BIAS_Y_G__SHIFT 0x0 +#define VPCM_BIAS_Y_G_CB_B__VPCM_BIAS_CB_B__SHIFT 0x10 +#define VPCM_BIAS_Y_G_CB_B__VPCM_BIAS_Y_G_MASK 0x0000FFFFL +#define VPCM_BIAS_Y_G_CB_B__VPCM_BIAS_CB_B_MASK 0xFFFF0000L +//VPCM_GAMCOR_CONTROL +#define VPCM_GAMCOR_CONTROL__VPCM_GAMCOR_MODE__SHIFT 0x0 +#define VPCM_GAMCOR_CONTROL__VPCM_GAMCOR_PWL_DISABLE__SHIFT 0x3 +#define VPCM_GAMCOR_CONTROL__VPCM_GAMCOR_MODE_CURRENT__SHIFT 0x4 +#define VPCM_GAMCOR_CONTROL__VPCM_GAMCOR_SELECT_CURRENT__SHIFT 0x6 +#define VPCM_GAMCOR_CONTROL__VPCM_GAMCOR_MODE_MASK 0x00000003L +#define VPCM_GAMCOR_CONTROL__VPCM_GAMCOR_PWL_DISABLE_MASK 0x00000008L +#define VPCM_GAMCOR_CONTROL__VPCM_GAMCOR_MODE_CURRENT_MASK 0x00000030L +#define VPCM_GAMCOR_CONTROL__VPCM_GAMCOR_SELECT_CURRENT_MASK 0x00000040L +//VPCM_GAMCOR_LUT_INDEX +#define VPCM_GAMCOR_LUT_INDEX__VPCM_GAMCOR_LUT_INDEX__SHIFT 0x0 +#define VPCM_GAMCOR_LUT_INDEX__VPCM_GAMCOR_LUT_INDEX_MASK 0x000001FFL +//VPCM_GAMCOR_LUT_DATA +#define VPCM_GAMCOR_LUT_DATA__VPCM_GAMCOR_LUT_DATA__SHIFT 0x0 +#define VPCM_GAMCOR_LUT_DATA__VPCM_GAMCOR_LUT_DATA_MASK 0x0003FFFFL +//VPCM_GAMCOR_LUT_CONTROL +#define VPCM_GAMCOR_LUT_CONTROL__VPCM_GAMCOR_LUT_WRITE_COLOR_MASK__SHIFT 0x0 +#define VPCM_GAMCOR_LUT_CONTROL__VPCM_GAMCOR_LUT_READ_COLOR_SEL__SHIFT 0x3 +#define VPCM_GAMCOR_LUT_CONTROL__VPCM_GAMCOR_LUT_READ_DBG__SHIFT 0x5 +#define VPCM_GAMCOR_LUT_CONTROL__VPCM_GAMCOR_LUT_HOST_SEL__SHIFT 0x6 +#define VPCM_GAMCOR_LUT_CONTROL__VPCM_GAMCOR_LUT_CONFIG_MODE__SHIFT 0x7 +#define VPCM_GAMCOR_LUT_CONTROL__VPCM_GAMCOR_LUT_WRITE_COLOR_MASK_MASK 0x00000007L +#define VPCM_GAMCOR_LUT_CONTROL__VPCM_GAMCOR_LUT_READ_COLOR_SEL_MASK 0x00000018L +#define VPCM_GAMCOR_LUT_CONTROL__VPCM_GAMCOR_LUT_READ_DBG_MASK 0x00000020L +#define VPCM_GAMCOR_LUT_CONTROL__VPCM_GAMCOR_LUT_HOST_SEL_MASK 0x00000040L +#define VPCM_GAMCOR_LUT_CONTROL__VPCM_GAMCOR_LUT_CONFIG_MODE_MASK 0x00000080L +//VPCM_GAMCOR_RAMA_START_CNTL_B +#define VPCM_GAMCOR_RAMA_START_CNTL_B__VPCM_GAMCOR_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define VPCM_GAMCOR_RAMA_START_CNTL_B__VPCM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define VPCM_GAMCOR_RAMA_START_CNTL_B__VPCM_GAMCOR_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define VPCM_GAMCOR_RAMA_START_CNTL_B__VPCM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//VPCM_GAMCOR_RAMA_START_CNTL_G +#define VPCM_GAMCOR_RAMA_START_CNTL_G__VPCM_GAMCOR_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define VPCM_GAMCOR_RAMA_START_CNTL_G__VPCM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define VPCM_GAMCOR_RAMA_START_CNTL_G__VPCM_GAMCOR_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define VPCM_GAMCOR_RAMA_START_CNTL_G__VPCM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//VPCM_GAMCOR_RAMA_START_CNTL_R +#define VPCM_GAMCOR_RAMA_START_CNTL_R__VPCM_GAMCOR_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define VPCM_GAMCOR_RAMA_START_CNTL_R__VPCM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define VPCM_GAMCOR_RAMA_START_CNTL_R__VPCM_GAMCOR_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define VPCM_GAMCOR_RAMA_START_CNTL_R__VPCM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_B +#define VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_B__VPCM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_B__VPCM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_G +#define VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_G__VPCM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_G__VPCM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_R +#define VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_R__VPCM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_R__VPCM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//VPCM_GAMCOR_RAMA_START_BASE_CNTL_B +#define VPCM_GAMCOR_RAMA_START_BASE_CNTL_B__VPCM_GAMCOR_RAMA_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define VPCM_GAMCOR_RAMA_START_BASE_CNTL_B__VPCM_GAMCOR_RAMA_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//VPCM_GAMCOR_RAMA_START_BASE_CNTL_G +#define VPCM_GAMCOR_RAMA_START_BASE_CNTL_G__VPCM_GAMCOR_RAMA_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define VPCM_GAMCOR_RAMA_START_BASE_CNTL_G__VPCM_GAMCOR_RAMA_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//VPCM_GAMCOR_RAMA_START_BASE_CNTL_R +#define VPCM_GAMCOR_RAMA_START_BASE_CNTL_R__VPCM_GAMCOR_RAMA_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define VPCM_GAMCOR_RAMA_START_BASE_CNTL_R__VPCM_GAMCOR_RAMA_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//VPCM_GAMCOR_RAMA_END_CNTL1_B +#define VPCM_GAMCOR_RAMA_END_CNTL1_B__VPCM_GAMCOR_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define VPCM_GAMCOR_RAMA_END_CNTL1_B__VPCM_GAMCOR_RAMA_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//VPCM_GAMCOR_RAMA_END_CNTL2_B +#define VPCM_GAMCOR_RAMA_END_CNTL2_B__VPCM_GAMCOR_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define VPCM_GAMCOR_RAMA_END_CNTL2_B__VPCM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define VPCM_GAMCOR_RAMA_END_CNTL2_B__VPCM_GAMCOR_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define VPCM_GAMCOR_RAMA_END_CNTL2_B__VPCM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//VPCM_GAMCOR_RAMA_END_CNTL1_G +#define VPCM_GAMCOR_RAMA_END_CNTL1_G__VPCM_GAMCOR_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define VPCM_GAMCOR_RAMA_END_CNTL1_G__VPCM_GAMCOR_RAMA_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//VPCM_GAMCOR_RAMA_END_CNTL2_G +#define VPCM_GAMCOR_RAMA_END_CNTL2_G__VPCM_GAMCOR_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define VPCM_GAMCOR_RAMA_END_CNTL2_G__VPCM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define VPCM_GAMCOR_RAMA_END_CNTL2_G__VPCM_GAMCOR_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define VPCM_GAMCOR_RAMA_END_CNTL2_G__VPCM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//VPCM_GAMCOR_RAMA_END_CNTL1_R +#define VPCM_GAMCOR_RAMA_END_CNTL1_R__VPCM_GAMCOR_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define VPCM_GAMCOR_RAMA_END_CNTL1_R__VPCM_GAMCOR_RAMA_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//VPCM_GAMCOR_RAMA_END_CNTL2_R +#define VPCM_GAMCOR_RAMA_END_CNTL2_R__VPCM_GAMCOR_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define VPCM_GAMCOR_RAMA_END_CNTL2_R__VPCM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define VPCM_GAMCOR_RAMA_END_CNTL2_R__VPCM_GAMCOR_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define VPCM_GAMCOR_RAMA_END_CNTL2_R__VPCM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//VPCM_GAMCOR_RAMA_OFFSET_B +#define VPCM_GAMCOR_RAMA_OFFSET_B__VPCM_GAMCOR_RAMA_OFFSET_B__SHIFT 0x0 +#define VPCM_GAMCOR_RAMA_OFFSET_B__VPCM_GAMCOR_RAMA_OFFSET_B_MASK 0x0007FFFFL +//VPCM_GAMCOR_RAMA_OFFSET_G +#define VPCM_GAMCOR_RAMA_OFFSET_G__VPCM_GAMCOR_RAMA_OFFSET_G__SHIFT 0x0 +#define VPCM_GAMCOR_RAMA_OFFSET_G__VPCM_GAMCOR_RAMA_OFFSET_G_MASK 0x0007FFFFL +//VPCM_GAMCOR_RAMA_OFFSET_R +#define VPCM_GAMCOR_RAMA_OFFSET_R__VPCM_GAMCOR_RAMA_OFFSET_R__SHIFT 0x0 +#define VPCM_GAMCOR_RAMA_OFFSET_R__VPCM_GAMCOR_RAMA_OFFSET_R_MASK 0x0007FFFFL +//VPCM_GAMCOR_RAMA_REGION_0_1 +#define VPCM_GAMCOR_RAMA_REGION_0_1__VPCM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define VPCM_GAMCOR_RAMA_REGION_0_1__VPCM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define VPCM_GAMCOR_RAMA_REGION_0_1__VPCM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define VPCM_GAMCOR_RAMA_REGION_0_1__VPCM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define VPCM_GAMCOR_RAMA_REGION_0_1__VPCM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define VPCM_GAMCOR_RAMA_REGION_0_1__VPCM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define VPCM_GAMCOR_RAMA_REGION_0_1__VPCM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define VPCM_GAMCOR_RAMA_REGION_0_1__VPCM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//VPCM_GAMCOR_RAMA_REGION_2_3 +#define VPCM_GAMCOR_RAMA_REGION_2_3__VPCM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define VPCM_GAMCOR_RAMA_REGION_2_3__VPCM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define VPCM_GAMCOR_RAMA_REGION_2_3__VPCM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define VPCM_GAMCOR_RAMA_REGION_2_3__VPCM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define VPCM_GAMCOR_RAMA_REGION_2_3__VPCM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define VPCM_GAMCOR_RAMA_REGION_2_3__VPCM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define VPCM_GAMCOR_RAMA_REGION_2_3__VPCM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define VPCM_GAMCOR_RAMA_REGION_2_3__VPCM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//VPCM_GAMCOR_RAMA_REGION_4_5 +#define VPCM_GAMCOR_RAMA_REGION_4_5__VPCM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define VPCM_GAMCOR_RAMA_REGION_4_5__VPCM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define VPCM_GAMCOR_RAMA_REGION_4_5__VPCM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define VPCM_GAMCOR_RAMA_REGION_4_5__VPCM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define VPCM_GAMCOR_RAMA_REGION_4_5__VPCM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define VPCM_GAMCOR_RAMA_REGION_4_5__VPCM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define VPCM_GAMCOR_RAMA_REGION_4_5__VPCM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define VPCM_GAMCOR_RAMA_REGION_4_5__VPCM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//VPCM_GAMCOR_RAMA_REGION_6_7 +#define VPCM_GAMCOR_RAMA_REGION_6_7__VPCM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define VPCM_GAMCOR_RAMA_REGION_6_7__VPCM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define VPCM_GAMCOR_RAMA_REGION_6_7__VPCM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define VPCM_GAMCOR_RAMA_REGION_6_7__VPCM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define VPCM_GAMCOR_RAMA_REGION_6_7__VPCM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define VPCM_GAMCOR_RAMA_REGION_6_7__VPCM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define VPCM_GAMCOR_RAMA_REGION_6_7__VPCM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define VPCM_GAMCOR_RAMA_REGION_6_7__VPCM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//VPCM_GAMCOR_RAMA_REGION_8_9 +#define VPCM_GAMCOR_RAMA_REGION_8_9__VPCM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define VPCM_GAMCOR_RAMA_REGION_8_9__VPCM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define VPCM_GAMCOR_RAMA_REGION_8_9__VPCM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define VPCM_GAMCOR_RAMA_REGION_8_9__VPCM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define VPCM_GAMCOR_RAMA_REGION_8_9__VPCM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define VPCM_GAMCOR_RAMA_REGION_8_9__VPCM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define VPCM_GAMCOR_RAMA_REGION_8_9__VPCM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define VPCM_GAMCOR_RAMA_REGION_8_9__VPCM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//VPCM_GAMCOR_RAMA_REGION_10_11 +#define VPCM_GAMCOR_RAMA_REGION_10_11__VPCM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define VPCM_GAMCOR_RAMA_REGION_10_11__VPCM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define VPCM_GAMCOR_RAMA_REGION_10_11__VPCM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define VPCM_GAMCOR_RAMA_REGION_10_11__VPCM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define VPCM_GAMCOR_RAMA_REGION_10_11__VPCM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define VPCM_GAMCOR_RAMA_REGION_10_11__VPCM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define VPCM_GAMCOR_RAMA_REGION_10_11__VPCM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define VPCM_GAMCOR_RAMA_REGION_10_11__VPCM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//VPCM_GAMCOR_RAMA_REGION_12_13 +#define VPCM_GAMCOR_RAMA_REGION_12_13__VPCM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define VPCM_GAMCOR_RAMA_REGION_12_13__VPCM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define VPCM_GAMCOR_RAMA_REGION_12_13__VPCM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define VPCM_GAMCOR_RAMA_REGION_12_13__VPCM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define VPCM_GAMCOR_RAMA_REGION_12_13__VPCM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define VPCM_GAMCOR_RAMA_REGION_12_13__VPCM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define VPCM_GAMCOR_RAMA_REGION_12_13__VPCM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define VPCM_GAMCOR_RAMA_REGION_12_13__VPCM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//VPCM_GAMCOR_RAMA_REGION_14_15 +#define VPCM_GAMCOR_RAMA_REGION_14_15__VPCM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define VPCM_GAMCOR_RAMA_REGION_14_15__VPCM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define VPCM_GAMCOR_RAMA_REGION_14_15__VPCM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define VPCM_GAMCOR_RAMA_REGION_14_15__VPCM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define VPCM_GAMCOR_RAMA_REGION_14_15__VPCM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define VPCM_GAMCOR_RAMA_REGION_14_15__VPCM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define VPCM_GAMCOR_RAMA_REGION_14_15__VPCM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define VPCM_GAMCOR_RAMA_REGION_14_15__VPCM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//VPCM_GAMCOR_RAMA_REGION_16_17 +#define VPCM_GAMCOR_RAMA_REGION_16_17__VPCM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define VPCM_GAMCOR_RAMA_REGION_16_17__VPCM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define VPCM_GAMCOR_RAMA_REGION_16_17__VPCM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define VPCM_GAMCOR_RAMA_REGION_16_17__VPCM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define VPCM_GAMCOR_RAMA_REGION_16_17__VPCM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define VPCM_GAMCOR_RAMA_REGION_16_17__VPCM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define VPCM_GAMCOR_RAMA_REGION_16_17__VPCM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define VPCM_GAMCOR_RAMA_REGION_16_17__VPCM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//VPCM_GAMCOR_RAMA_REGION_18_19 +#define VPCM_GAMCOR_RAMA_REGION_18_19__VPCM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define VPCM_GAMCOR_RAMA_REGION_18_19__VPCM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define VPCM_GAMCOR_RAMA_REGION_18_19__VPCM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define VPCM_GAMCOR_RAMA_REGION_18_19__VPCM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define VPCM_GAMCOR_RAMA_REGION_18_19__VPCM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define VPCM_GAMCOR_RAMA_REGION_18_19__VPCM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define VPCM_GAMCOR_RAMA_REGION_18_19__VPCM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define VPCM_GAMCOR_RAMA_REGION_18_19__VPCM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//VPCM_GAMCOR_RAMA_REGION_20_21 +#define VPCM_GAMCOR_RAMA_REGION_20_21__VPCM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define VPCM_GAMCOR_RAMA_REGION_20_21__VPCM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define VPCM_GAMCOR_RAMA_REGION_20_21__VPCM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define VPCM_GAMCOR_RAMA_REGION_20_21__VPCM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define VPCM_GAMCOR_RAMA_REGION_20_21__VPCM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define VPCM_GAMCOR_RAMA_REGION_20_21__VPCM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define VPCM_GAMCOR_RAMA_REGION_20_21__VPCM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define VPCM_GAMCOR_RAMA_REGION_20_21__VPCM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//VPCM_GAMCOR_RAMA_REGION_22_23 +#define VPCM_GAMCOR_RAMA_REGION_22_23__VPCM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define VPCM_GAMCOR_RAMA_REGION_22_23__VPCM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define VPCM_GAMCOR_RAMA_REGION_22_23__VPCM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define VPCM_GAMCOR_RAMA_REGION_22_23__VPCM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define VPCM_GAMCOR_RAMA_REGION_22_23__VPCM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define VPCM_GAMCOR_RAMA_REGION_22_23__VPCM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define VPCM_GAMCOR_RAMA_REGION_22_23__VPCM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define VPCM_GAMCOR_RAMA_REGION_22_23__VPCM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//VPCM_GAMCOR_RAMA_REGION_24_25 +#define VPCM_GAMCOR_RAMA_REGION_24_25__VPCM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define VPCM_GAMCOR_RAMA_REGION_24_25__VPCM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define VPCM_GAMCOR_RAMA_REGION_24_25__VPCM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define VPCM_GAMCOR_RAMA_REGION_24_25__VPCM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define VPCM_GAMCOR_RAMA_REGION_24_25__VPCM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define VPCM_GAMCOR_RAMA_REGION_24_25__VPCM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define VPCM_GAMCOR_RAMA_REGION_24_25__VPCM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define VPCM_GAMCOR_RAMA_REGION_24_25__VPCM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//VPCM_GAMCOR_RAMA_REGION_26_27 +#define VPCM_GAMCOR_RAMA_REGION_26_27__VPCM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define VPCM_GAMCOR_RAMA_REGION_26_27__VPCM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define VPCM_GAMCOR_RAMA_REGION_26_27__VPCM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define VPCM_GAMCOR_RAMA_REGION_26_27__VPCM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define VPCM_GAMCOR_RAMA_REGION_26_27__VPCM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define VPCM_GAMCOR_RAMA_REGION_26_27__VPCM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define VPCM_GAMCOR_RAMA_REGION_26_27__VPCM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define VPCM_GAMCOR_RAMA_REGION_26_27__VPCM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//VPCM_GAMCOR_RAMA_REGION_28_29 +#define VPCM_GAMCOR_RAMA_REGION_28_29__VPCM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define VPCM_GAMCOR_RAMA_REGION_28_29__VPCM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define VPCM_GAMCOR_RAMA_REGION_28_29__VPCM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define VPCM_GAMCOR_RAMA_REGION_28_29__VPCM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define VPCM_GAMCOR_RAMA_REGION_28_29__VPCM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define VPCM_GAMCOR_RAMA_REGION_28_29__VPCM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define VPCM_GAMCOR_RAMA_REGION_28_29__VPCM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define VPCM_GAMCOR_RAMA_REGION_28_29__VPCM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//VPCM_GAMCOR_RAMA_REGION_30_31 +#define VPCM_GAMCOR_RAMA_REGION_30_31__VPCM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define VPCM_GAMCOR_RAMA_REGION_30_31__VPCM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define VPCM_GAMCOR_RAMA_REGION_30_31__VPCM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define VPCM_GAMCOR_RAMA_REGION_30_31__VPCM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define VPCM_GAMCOR_RAMA_REGION_30_31__VPCM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define VPCM_GAMCOR_RAMA_REGION_30_31__VPCM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define VPCM_GAMCOR_RAMA_REGION_30_31__VPCM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define VPCM_GAMCOR_RAMA_REGION_30_31__VPCM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//VPCM_GAMCOR_RAMA_REGION_32_33 +#define VPCM_GAMCOR_RAMA_REGION_32_33__VPCM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define VPCM_GAMCOR_RAMA_REGION_32_33__VPCM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define VPCM_GAMCOR_RAMA_REGION_32_33__VPCM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define VPCM_GAMCOR_RAMA_REGION_32_33__VPCM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define VPCM_GAMCOR_RAMA_REGION_32_33__VPCM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define VPCM_GAMCOR_RAMA_REGION_32_33__VPCM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define VPCM_GAMCOR_RAMA_REGION_32_33__VPCM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define VPCM_GAMCOR_RAMA_REGION_32_33__VPCM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//VPCM_HDR_MULT_COEF +#define VPCM_HDR_MULT_COEF__VPCM_HDR_MULT_COEF__SHIFT 0x0 +#define VPCM_HDR_MULT_COEF__VPCM_HDR_MULT_COEF_MASK 0x0007FFFFL +//VPCM_MEM_PWR_CTRL +#define VPCM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE__SHIFT 0x0 +#define VPCM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS__SHIFT 0x2 +#define VPCM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE_MASK 0x00000003L +#define VPCM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS_MASK 0x00000004L +//VPCM_MEM_PWR_STATUS +#define VPCM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE__SHIFT 0x0 +#define VPCM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE_MASK 0x00000003L +//VPCM_DEALPHA +#define VPCM_DEALPHA__VPCM_DEALPHA_EN__SHIFT 0x0 +#define VPCM_DEALPHA__VPCM_DEALPHA_ABLND__SHIFT 0x1 +#define VPCM_DEALPHA__VPCM_DEALPHA_EN_MASK 0x00000001L +#define VPCM_DEALPHA__VPCM_DEALPHA_ABLND_MASK 0x00000002L +//VPCM_COEF_FORMAT +#define VPCM_COEF_FORMAT__VPCM_BIAS_FORMAT__SHIFT 0x0 +#define VPCM_COEF_FORMAT__VPCM_POST_CSC_COEF_FORMAT__SHIFT 0x4 +#define VPCM_COEF_FORMAT__VPCM_GAMUT_REMAP_COEF_FORMAT__SHIFT 0x8 +#define VPCM_COEF_FORMAT__VPCM_BIAS_FORMAT_MASK 0x00000001L +#define VPCM_COEF_FORMAT__VPCM_POST_CSC_COEF_FORMAT_MASK 0x00000010L +#define VPCM_COEF_FORMAT__VPCM_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000100L +//VPCM_TEST_DEBUG_INDEX +#define VPCM_TEST_DEBUG_INDEX__VPCM_TEST_DEBUG_INDEX__SHIFT 0x0 +#define VPCM_TEST_DEBUG_INDEX__VPCM_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define VPCM_TEST_DEBUG_INDEX__VPCM_TEST_DEBUG_INDEX_MASK 0x000000FFL +#define VPCM_TEST_DEBUG_INDEX__VPCM_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +//VPCM_TEST_DEBUG_DATA +#define VPCM_TEST_DEBUG_DATA__VPCM_TEST_DEBUG_DATA__SHIFT 0x0 +#define VPCM_TEST_DEBUG_DATA__VPCM_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: vpe_vpep_vpdpp0_dispdec_vpdpp_top_dispdec +//VPDPP_CONTROL +#define VPDPP_CONTROL__VPDPP_CLOCK_ENABLE__SHIFT 0x4 +#define VPDPP_CONTROL__VPECLK_G_GATE_DISABLE__SHIFT 0x8 +#define VPDPP_CONTROL__VPECLK_G_DYN_GATE_DISABLE__SHIFT 0xa +#define VPDPP_CONTROL__VPECLK_G_VPDSCL_GATE_DISABLE__SHIFT 0xc +#define VPDPP_CONTROL__VPECLK_R_GATE_DISABLE__SHIFT 0xe +#define VPDPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT 0x10 +#define VPDPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT 0x12 +#define VPDPP_CONTROL__VPDPP_FGCG_REP_DIS__SHIFT 0x18 +#define VPDPP_CONTROL__VPDPP_TEST_CLK_SEL__SHIFT 0x1c +#define VPDPP_CONTROL__VPDPP_CLOCK_ENABLE_MASK 0x00000010L +#define VPDPP_CONTROL__VPECLK_G_GATE_DISABLE_MASK 0x00000100L +#define VPDPP_CONTROL__VPECLK_G_DYN_GATE_DISABLE_MASK 0x00000400L +#define VPDPP_CONTROL__VPECLK_G_VPDSCL_GATE_DISABLE_MASK 0x00001000L +#define VPDPP_CONTROL__VPECLK_R_GATE_DISABLE_MASK 0x00004000L +#define VPDPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK 0x00010000L +#define VPDPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK 0x00040000L +#define VPDPP_CONTROL__VPDPP_FGCG_REP_DIS_MASK 0x01000000L +#define VPDPP_CONTROL__VPDPP_TEST_CLK_SEL_MASK 0x70000000L +//VPDPP_SOFT_RESET +#define VPDPP_SOFT_RESET__VPCNVC_SOFT_RESET__SHIFT 0x0 +#define VPDPP_SOFT_RESET__VPDSCL_SOFT_RESET__SHIFT 0x4 +#define VPDPP_SOFT_RESET__VPCM_SOFT_RESET__SHIFT 0x8 +#define VPDPP_SOFT_RESET__VPOBUF_SOFT_RESET__SHIFT 0xc +#define VPDPP_SOFT_RESET__VPCNVC_SOFT_RESET_MASK 0x00000001L +#define VPDPP_SOFT_RESET__VPDSCL_SOFT_RESET_MASK 0x00000010L +#define VPDPP_SOFT_RESET__VPCM_SOFT_RESET_MASK 0x00000100L +#define VPDPP_SOFT_RESET__VPOBUF_SOFT_RESET_MASK 0x00001000L +//VPDPP_CRC_VAL_R_G +#define VPDPP_CRC_VAL_R_G__VPDPP_CRC_R_CR__SHIFT 0x0 +#define VPDPP_CRC_VAL_R_G__VPDPP_CRC_G_Y__SHIFT 0x10 +#define VPDPP_CRC_VAL_R_G__VPDPP_CRC_R_CR_MASK 0x0000FFFFL +#define VPDPP_CRC_VAL_R_G__VPDPP_CRC_G_Y_MASK 0xFFFF0000L +//VPDPP_CRC_VAL_B_A +#define VPDPP_CRC_VAL_B_A__VPDPP_CRC_B_CB__SHIFT 0x0 +#define VPDPP_CRC_VAL_B_A__VPDPP_CRC_ALPHA__SHIFT 0x10 +#define VPDPP_CRC_VAL_B_A__VPDPP_CRC_B_CB_MASK 0x0000FFFFL +#define VPDPP_CRC_VAL_B_A__VPDPP_CRC_ALPHA_MASK 0xFFFF0000L +//VPDPP_CRC_CTRL +#define VPDPP_CRC_CTRL__VPDPP_CRC_EN__SHIFT 0x0 +#define VPDPP_CRC_CTRL__VPDPP_CRC_CONT_EN__SHIFT 0x1 +#define VPDPP_CRC_CTRL__VPDPP_CRC_ONE_SHOT_PENDING__SHIFT 0x2 +#define VPDPP_CRC_CTRL__VPDPP_CRC_420_COMP_SEL__SHIFT 0x3 +#define VPDPP_CRC_CTRL__VPDPP_CRC_SRC_SEL__SHIFT 0x4 +#define VPDPP_CRC_CTRL__VPDPP_CRC_PIX_FORMAT_SEL__SHIFT 0xb +#define VPDPP_CRC_CTRL__VPDPP_CRC_MASK__SHIFT 0x10 +#define VPDPP_CRC_CTRL__VPDPP_CRC_EN_MASK 0x00000001L +#define VPDPP_CRC_CTRL__VPDPP_CRC_CONT_EN_MASK 0x00000002L +#define VPDPP_CRC_CTRL__VPDPP_CRC_ONE_SHOT_PENDING_MASK 0x00000004L +#define VPDPP_CRC_CTRL__VPDPP_CRC_420_COMP_SEL_MASK 0x00000008L +#define VPDPP_CRC_CTRL__VPDPP_CRC_SRC_SEL_MASK 0x00000030L +#define VPDPP_CRC_CTRL__VPDPP_CRC_PIX_FORMAT_SEL_MASK 0x00003800L +#define VPDPP_CRC_CTRL__VPDPP_CRC_MASK_MASK 0xFFFF0000L +//VPHOST_READ_CONTROL +#define VPHOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT 0x0 +#define VPHOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK 0x000000FFL +//VPDPP_DEBUG_SEL +#define VPDPP_DEBUG_SEL__VPDPP_VPECLK_DEBUG_BUS_SEL__SHIFT 0x0 +#define VPDPP_DEBUG_SEL__VPDPP_DBG_EN__SHIFT 0x1f +#define VPDPP_DEBUG_SEL__VPDPP_VPECLK_DEBUG_BUS_SEL_MASK 0x00000007L +#define VPDPP_DEBUG_SEL__VPDPP_DBG_EN_MASK 0x80000000L +//VPDPP_DEBUG_SPARE +#define VPDPP_DEBUG_SPARE__VPDPP_DEBUG_SPARE__SHIFT 0x0 +#define VPDPP_DEBUG_SPARE__VPDPP_DEBUG_SPARE_MASK 0xFFFFFFFFL +//VPDPP_TEST_DEBUG_INDEX +#define VPDPP_TEST_DEBUG_INDEX__VPDPP_TEST_DEBUG_INDEX__SHIFT 0x0 +#define VPDPP_TEST_DEBUG_INDEX__VPDPP_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define VPDPP_TEST_DEBUG_INDEX__VPDPP_TEST_DEBUG_INDEX_MASK 0x000000FFL +#define VPDPP_TEST_DEBUG_INDEX__VPDPP_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +//VPDPP_TEST_DEBUG_DATA +#define VPDPP_TEST_DEBUG_DATA__VPDPP_TEST_DEBUG_DATA__SHIFT 0x0 +#define VPDPP_TEST_DEBUG_DATA__VPDPP_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: vpe_vpep_vpmpc_vpmpcc0_dispdec +//VPMPCC_TOP_SEL +#define VPMPCC_TOP_SEL__VPMPCC_TOP_SEL__SHIFT 0x0 +#define VPMPCC_TOP_SEL__VPMPCC_TOP_SEL_MASK 0x0000000FL +//VPMPCC_BOT_SEL +#define VPMPCC_BOT_SEL__VPMPCC_BOT_SEL__SHIFT 0x0 +#define VPMPCC_BOT_SEL__VPMPCC_BOT_SEL_MASK 0x0000000FL +//VPMPCC_VPOPP_ID +#define VPMPCC_VPOPP_ID__VPMPCC_VPOPP_ID__SHIFT 0x0 +#define VPMPCC_VPOPP_ID__VPMPCC_VPOPP_ID_MASK 0x0000000FL +//VPMPCC_CONTROL +#define VPMPCC_CONTROL__VPMPCC_MODE__SHIFT 0x0 +#define VPMPCC_CONTROL__VPMPCC_ALPHA_BLND_MODE__SHIFT 0x4 +#define VPMPCC_CONTROL__VPMPCC_ALPHA_MULTIPLIED_MODE__SHIFT 0x6 +#define VPMPCC_CONTROL__VPMPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT 0x7 +#define VPMPCC_CONTROL__VPMPCC_BG_BPC__SHIFT 0x8 +#define VPMPCC_CONTROL__VPMPCC_BOT_GAIN_MODE__SHIFT 0xb +#define VPMPCC_CONTROL__VPMPCC_GLOBAL_ALPHA__SHIFT 0x10 +#define VPMPCC_CONTROL__VPMPCC_GLOBAL_GAIN__SHIFT 0x18 +#define VPMPCC_CONTROL__VPMPCC_MODE_MASK 0x00000003L +#define VPMPCC_CONTROL__VPMPCC_ALPHA_BLND_MODE_MASK 0x00000030L +#define VPMPCC_CONTROL__VPMPCC_ALPHA_MULTIPLIED_MODE_MASK 0x00000040L +#define VPMPCC_CONTROL__VPMPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK 0x00000080L +#define VPMPCC_CONTROL__VPMPCC_BG_BPC_MASK 0x00000700L +#define VPMPCC_CONTROL__VPMPCC_BOT_GAIN_MODE_MASK 0x00000800L +#define VPMPCC_CONTROL__VPMPCC_GLOBAL_ALPHA_MASK 0x00FF0000L +#define VPMPCC_CONTROL__VPMPCC_GLOBAL_GAIN_MASK 0xFF000000L +//VPMPCC_TOP_GAIN +#define VPMPCC_TOP_GAIN__VPMPCC_TOP_GAIN__SHIFT 0x0 +#define VPMPCC_TOP_GAIN__VPMPCC_TOP_GAIN_MASK 0x0007FFFFL +//VPMPCC_BOT_GAIN_INSIDE +#define VPMPCC_BOT_GAIN_INSIDE__VPMPCC_BOT_GAIN_INSIDE__SHIFT 0x0 +#define VPMPCC_BOT_GAIN_INSIDE__VPMPCC_BOT_GAIN_INSIDE_MASK 0x0007FFFFL +//VPMPCC_BOT_GAIN_OUTSIDE +#define VPMPCC_BOT_GAIN_OUTSIDE__VPMPCC_BOT_GAIN_OUTSIDE__SHIFT 0x0 +#define VPMPCC_BOT_GAIN_OUTSIDE__VPMPCC_BOT_GAIN_OUTSIDE_MASK 0x0007FFFFL +//VPMPCC_MOVABLE_CM_LOCATION_CONTROL +#define VPMPCC_MOVABLE_CM_LOCATION_CONTROL__VPMPCC_MOVABLE_CM_LOCATION_CNTL__SHIFT 0x0 +#define VPMPCC_MOVABLE_CM_LOCATION_CONTROL__VPMPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT__SHIFT 0x4 +#define VPMPCC_MOVABLE_CM_LOCATION_CONTROL__VPMPCC_MOVABLE_CM_LOCATION_CNTL_MASK 0x00000001L +#define VPMPCC_MOVABLE_CM_LOCATION_CONTROL__VPMPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT_MASK 0x00000010L +//VPMPCC_BG_R_CR +#define VPMPCC_BG_R_CR__VPMPCC_BG_R_CR__SHIFT 0x0 +#define VPMPCC_BG_R_CR__VPMPCC_BG_R_CR_MASK 0x00000FFFL +//VPMPCC_BG_G_Y +#define VPMPCC_BG_G_Y__VPMPCC_BG_G_Y__SHIFT 0x0 +#define VPMPCC_BG_G_Y__VPMPCC_BG_G_Y_MASK 0x00000FFFL +//VPMPCC_BG_B_CB +#define VPMPCC_BG_B_CB__VPMPCC_BG_B_CB__SHIFT 0x0 +#define VPMPCC_BG_B_CB__VPMPCC_BG_B_CB_MASK 0x00000FFFL +//VPMPCC_MEM_PWR_CTRL +#define VPMPCC_MEM_PWR_CTRL__VPMPCC_OGAM_MEM_PWR_FORCE__SHIFT 0x0 +#define VPMPCC_MEM_PWR_CTRL__VPMPCC_OGAM_MEM_PWR_DIS__SHIFT 0x2 +#define VPMPCC_MEM_PWR_CTRL__VPMPCC_OGAM_MEM_LOW_PWR_MODE__SHIFT 0x4 +#define VPMPCC_MEM_PWR_CTRL__VPMPCC_OGAM_MEM_PWR_STATE__SHIFT 0x8 +#define VPMPCC_MEM_PWR_CTRL__VPMPCC_OGAM_MEM_PWR_FORCE_MASK 0x00000003L +#define VPMPCC_MEM_PWR_CTRL__VPMPCC_OGAM_MEM_PWR_DIS_MASK 0x00000004L +#define VPMPCC_MEM_PWR_CTRL__VPMPCC_OGAM_MEM_LOW_PWR_MODE_MASK 0x00000030L +#define VPMPCC_MEM_PWR_CTRL__VPMPCC_OGAM_MEM_PWR_STATE_MASK 0x00000300L +//VPMPCC_STATUS +#define VPMPCC_STATUS__VPMPCC_IDLE__SHIFT 0x0 +#define VPMPCC_STATUS__VPMPCC_BUSY__SHIFT 0x1 +#define VPMPCC_STATUS__VPMPCC_DISABLED__SHIFT 0x2 +#define VPMPCC_STATUS__VPMPCC_IDLE_MASK 0x00000001L +#define VPMPCC_STATUS__VPMPCC_BUSY_MASK 0x00000002L +#define VPMPCC_STATUS__VPMPCC_DISABLED_MASK 0x00000004L +//VPMPCC_TEST_DEBUG_INDEX +#define VPMPCC_TEST_DEBUG_INDEX__VPMPCC_TEST_DEBUG_INDEX__SHIFT 0x0 +#define VPMPCC_TEST_DEBUG_INDEX__VPMPCC_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define VPMPCC_TEST_DEBUG_INDEX__VPMPCC_TEST_DEBUG_INDEX_MASK 0x000000FFL +#define VPMPCC_TEST_DEBUG_INDEX__VPMPCC_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +//VPMPCC_TEST_DEBUG_DATA +#define VPMPCC_TEST_DEBUG_DATA__VPMPCC_TEST_DEBUG_DATA__SHIFT 0x0 +#define VPMPCC_TEST_DEBUG_DATA__VPMPCC_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: vpe_vpep_vpmpc_vpmpc_cfg_dispdec +//VPMPC_CLOCK_CONTROL +#define VPMPC_CLOCK_CONTROL__VPECLK_R_GATE_DISABLE__SHIFT 0x1 +#define VPMPC_CLOCK_CONTROL__VPMPC_TEST_CLK_SEL__SHIFT 0x4 +#define VPMPC_CLOCK_CONTROL__VPECLK_R_GATE_DISABLE_MASK 0x00000002L +#define VPMPC_CLOCK_CONTROL__VPMPC_TEST_CLK_SEL_MASK 0x00000030L +//VPMPC_SOFT_RESET +#define VPMPC_SOFT_RESET__VPMPCC0_SOFT_RESET__SHIFT 0x0 +#define VPMPC_SOFT_RESET__VPMPC_SFR0_SOFT_RESET__SHIFT 0xa +#define VPMPC_SOFT_RESET__VPMPC_SFT0_SOFT_RESET__SHIFT 0x14 +#define VPMPC_SOFT_RESET__VPMPC_SOFT_RESET__SHIFT 0x1f +#define VPMPC_SOFT_RESET__VPMPCC0_SOFT_RESET_MASK 0x00000001L +#define VPMPC_SOFT_RESET__VPMPC_SFR0_SOFT_RESET_MASK 0x00000400L +#define VPMPC_SOFT_RESET__VPMPC_SFT0_SOFT_RESET_MASK 0x00100000L +#define VPMPC_SOFT_RESET__VPMPC_SOFT_RESET_MASK 0x80000000L +//VPMPC_CRC_CTRL +#define VPMPC_CRC_CTRL__VPMPC_CRC_EN__SHIFT 0x0 +#define VPMPC_CRC_CTRL__VPMPC_CRC_CONT_EN__SHIFT 0x4 +#define VPMPC_CRC_CTRL__VPMPC_CRC_SRC_SEL__SHIFT 0x18 +#define VPMPC_CRC_CTRL__VPMPC_CRC_ONE_SHOT_PENDING__SHIFT 0x1c +#define VPMPC_CRC_CTRL__VPMPC_CRC_UPDATE_ENABLED__SHIFT 0x1e +#define VPMPC_CRC_CTRL__VPMPC_CRC_UPDATE_LOCK__SHIFT 0x1f +#define VPMPC_CRC_CTRL__VPMPC_CRC_EN_MASK 0x00000001L +#define VPMPC_CRC_CTRL__VPMPC_CRC_CONT_EN_MASK 0x00000010L +#define VPMPC_CRC_CTRL__VPMPC_CRC_SRC_SEL_MASK 0x03000000L +#define VPMPC_CRC_CTRL__VPMPC_CRC_ONE_SHOT_PENDING_MASK 0x10000000L +#define VPMPC_CRC_CTRL__VPMPC_CRC_UPDATE_ENABLED_MASK 0x40000000L +#define VPMPC_CRC_CTRL__VPMPC_CRC_UPDATE_LOCK_MASK 0x80000000L +//VPMPC_CRC_SEL_CONTROL +#define VPMPC_CRC_SEL_CONTROL__VPMPC_CRC_VPDPP_SEL__SHIFT 0x0 +#define VPMPC_CRC_SEL_CONTROL__VPMPC_CRC_VPOPP_SEL__SHIFT 0x4 +#define VPMPC_CRC_SEL_CONTROL__VPMPC_CRC_MASK__SHIFT 0x10 +#define VPMPC_CRC_SEL_CONTROL__VPMPC_CRC_VPDPP_SEL_MASK 0x0000000FL +#define VPMPC_CRC_SEL_CONTROL__VPMPC_CRC_VPOPP_SEL_MASK 0x000000F0L +#define VPMPC_CRC_SEL_CONTROL__VPMPC_CRC_MASK_MASK 0xFFFF0000L +//VPMPC_CRC_RESULT_AR +#define VPMPC_CRC_RESULT_AR__VPMPC_CRC_RESULT_A__SHIFT 0x0 +#define VPMPC_CRC_RESULT_AR__VPMPC_CRC_RESULT_R__SHIFT 0x10 +#define VPMPC_CRC_RESULT_AR__VPMPC_CRC_RESULT_A_MASK 0x0000FFFFL +#define VPMPC_CRC_RESULT_AR__VPMPC_CRC_RESULT_R_MASK 0xFFFF0000L +//VPMPC_CRC_RESULT_GB +#define VPMPC_CRC_RESULT_GB__VPMPC_CRC_RESULT_G__SHIFT 0x0 +#define VPMPC_CRC_RESULT_GB__VPMPC_CRC_RESULT_B__SHIFT 0x10 +#define VPMPC_CRC_RESULT_GB__VPMPC_CRC_RESULT_G_MASK 0x0000FFFFL +#define VPMPC_CRC_RESULT_GB__VPMPC_CRC_RESULT_B_MASK 0xFFFF0000L +//VPMPC_CRC_RESULT_C +#define VPMPC_CRC_RESULT_C__VPMPC_CRC_RESULT_C__SHIFT 0x0 +#define VPMPC_CRC_RESULT_C__VPMPC_CRC_RESULT_C_MASK 0x0000FFFFL +//VPMPC_DEBUG_CONTROL +#define VPMPC_DEBUG_CONTROL__VPMPC_DEBUG_DATA_EN__SHIFT 0x0 +#define VPMPC_DEBUG_CONTROL__VPMPC_DEBUG_TOP_DATA_SELECT__SHIFT 0x1 +#define VPMPC_DEBUG_CONTROL__VPMPC_DEBUG_DATA_DIRECT_OUT_SELECT__SHIFT 0x4 +#define VPMPC_DEBUG_CONTROL__VPMPC_DEBUG_DATA_DIRECT_OUT_SFR_SELECT__SHIFT 0x8 +#define VPMPC_DEBUG_CONTROL__VPMPC_DEBUG_DATA_DIRECT_OUT_SFT_SELECT__SHIFT 0xc +#define VPMPC_DEBUG_CONTROL__VPMPC_DEBUG_DATA_EN_MASK 0x00000001L +#define VPMPC_DEBUG_CONTROL__VPMPC_DEBUG_TOP_DATA_SELECT_MASK 0x00000006L +#define VPMPC_DEBUG_CONTROL__VPMPC_DEBUG_DATA_DIRECT_OUT_SELECT_MASK 0x00000070L +#define VPMPC_DEBUG_CONTROL__VPMPC_DEBUG_DATA_DIRECT_OUT_SFR_SELECT_MASK 0x00000F00L +#define VPMPC_DEBUG_CONTROL__VPMPC_DEBUG_DATA_DIRECT_OUT_SFT_SELECT_MASK 0x0000F000L +//VPMPCC_DEBUG_DATA_SELECT +#define VPMPCC_DEBUG_DATA_SELECT__VPMPCC_DEBUG_DATA_VPMPCC_SELECT0__SHIFT 0x0 +#define VPMPCC_DEBUG_DATA_SELECT__VPMPCC_DEBUG_DATA_VPMPCC_BYTE_SELECT0__SHIFT 0x4 +#define VPMPCC_DEBUG_DATA_SELECT__VPMPCC_DEBUG_DATA_VPMPCC_OGAM_SELECT0__SHIFT 0x6 +#define VPMPCC_DEBUG_DATA_SELECT__VPMPCC_DEBUG_DATA_VPMPCC_SELECT1__SHIFT 0x8 +#define VPMPCC_DEBUG_DATA_SELECT__VPMPCC_DEBUG_DATA_VPMPCC_BYTE_SELECT1__SHIFT 0xc +#define VPMPCC_DEBUG_DATA_SELECT__VPMPCC_DEBUG_DATA_VPMPCC_OGAM_SELECT1__SHIFT 0xe +#define VPMPCC_DEBUG_DATA_SELECT__VPMPCC_DEBUG_DATA_VPMPCC_SELECT2__SHIFT 0x10 +#define VPMPCC_DEBUG_DATA_SELECT__VPMPCC_DEBUG_DATA_VPMPCC_BYTE_SELECT2__SHIFT 0x14 +#define VPMPCC_DEBUG_DATA_SELECT__VPMPCC_DEBUG_DATA_VPMPCC_OGAM_SELECT2__SHIFT 0x16 +#define VPMPCC_DEBUG_DATA_SELECT__VPMPCC_DEBUG_DATA_VPMPCC_SELECT3__SHIFT 0x18 +#define VPMPCC_DEBUG_DATA_SELECT__VPMPCC_DEBUG_DATA_VPMPCC_BYTE_SELECT3__SHIFT 0x1c +#define VPMPCC_DEBUG_DATA_SELECT__VPMPCC_DEBUG_DATA_VPMPCC_OGAM_SELECT3__SHIFT 0x1e +#define VPMPCC_DEBUG_DATA_SELECT__VPMPCC_DEBUG_DATA_VPMPCC_SELECT0_MASK 0x0000000FL +#define VPMPCC_DEBUG_DATA_SELECT__VPMPCC_DEBUG_DATA_VPMPCC_BYTE_SELECT0_MASK 0x00000030L +#define VPMPCC_DEBUG_DATA_SELECT__VPMPCC_DEBUG_DATA_VPMPCC_OGAM_SELECT0_MASK 0x000000C0L +#define VPMPCC_DEBUG_DATA_SELECT__VPMPCC_DEBUG_DATA_VPMPCC_SELECT1_MASK 0x00000F00L +#define VPMPCC_DEBUG_DATA_SELECT__VPMPCC_DEBUG_DATA_VPMPCC_BYTE_SELECT1_MASK 0x00003000L +#define VPMPCC_DEBUG_DATA_SELECT__VPMPCC_DEBUG_DATA_VPMPCC_OGAM_SELECT1_MASK 0x0000C000L +#define VPMPCC_DEBUG_DATA_SELECT__VPMPCC_DEBUG_DATA_VPMPCC_SELECT2_MASK 0x000F0000L +#define VPMPCC_DEBUG_DATA_SELECT__VPMPCC_DEBUG_DATA_VPMPCC_BYTE_SELECT2_MASK 0x00300000L +#define VPMPCC_DEBUG_DATA_SELECT__VPMPCC_DEBUG_DATA_VPMPCC_OGAM_SELECT2_MASK 0x00C00000L +#define VPMPCC_DEBUG_DATA_SELECT__VPMPCC_DEBUG_DATA_VPMPCC_SELECT3_MASK 0x0F000000L +#define VPMPCC_DEBUG_DATA_SELECT__VPMPCC_DEBUG_DATA_VPMPCC_BYTE_SELECT3_MASK 0x30000000L +#define VPMPCC_DEBUG_DATA_SELECT__VPMPCC_DEBUG_DATA_VPMPCC_OGAM_SELECT3_MASK 0xC0000000L +//VPMPC_BYPASS_BG_AR +#define VPMPC_BYPASS_BG_AR__VPMPC_BYPASS_BG_ALPHA__SHIFT 0x0 +#define VPMPC_BYPASS_BG_AR__VPMPC_BYPASS_BG_R_CR__SHIFT 0x10 +#define VPMPC_BYPASS_BG_AR__VPMPC_BYPASS_BG_ALPHA_MASK 0x0000FFFFL +#define VPMPC_BYPASS_BG_AR__VPMPC_BYPASS_BG_R_CR_MASK 0xFFFF0000L +//VPMPC_BYPASS_BG_GB +#define VPMPC_BYPASS_BG_GB__VPMPC_BYPASS_BG_G_Y__SHIFT 0x0 +#define VPMPC_BYPASS_BG_GB__VPMPC_BYPASS_BG_B_CB__SHIFT 0x10 +#define VPMPC_BYPASS_BG_GB__VPMPC_BYPASS_BG_G_Y_MASK 0x0000FFFFL +#define VPMPC_BYPASS_BG_GB__VPMPC_BYPASS_BG_B_CB_MASK 0xFFFF0000L +//VPMPC_HOST_READ_CONTROL +#define VPMPC_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT 0x0 +#define VPMPC_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK 0x000000FFL +//VPMPC_PENDING_STATUS_MISC +#define VPMPC_PENDING_STATUS_MISC__VPMPCC0_CONFIG_UPDATE_PENDING__SHIFT 0x8 +#define VPMPC_PENDING_STATUS_MISC__VPMPCC0_CONFIG_UPDATE_PENDING_MASK 0x00000100L +//VPMPC_CFG_TEST_DEBUG_INDEX +#define VPMPC_CFG_TEST_DEBUG_INDEX__VPMPC_CFG_TEST_DEBUG_INDEX__SHIFT 0x0 +#define VPMPC_CFG_TEST_DEBUG_INDEX__VPMPC_CFG_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define VPMPC_CFG_TEST_DEBUG_INDEX__VPMPC_CFG_TEST_DEBUG_INDEX_MASK 0x000000FFL +#define VPMPC_CFG_TEST_DEBUG_INDEX__VPMPC_CFG_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +//VPMPC_CFG_TEST_DEBUG_DATA +#define VPMPC_CFG_TEST_DEBUG_DATA__VPMPC_CFG_TEST_DEBUG_DATA__SHIFT 0x0 +#define VPMPC_CFG_TEST_DEBUG_DATA__VPMPC_CFG_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: vpe_vpep_vpmpc_vpmpcc_ogam0_dispdec +//VPMPCC_OGAM_CONTROL +#define VPMPCC_OGAM_CONTROL__VPMPCC_OGAM_MODE__SHIFT 0x0 +#define VPMPCC_OGAM_CONTROL__VPMPCC_OGAM_PWL_DISABLE__SHIFT 0x3 +#define VPMPCC_OGAM_CONTROL__VPMPCC_OGAM_MODE_CURRENT__SHIFT 0x7 +#define VPMPCC_OGAM_CONTROL__VPMPCC_OGAM_SELECT_CURRENT__SHIFT 0x9 +#define VPMPCC_OGAM_CONTROL__VPMPCC_OGAM_MODE_MASK 0x00000003L +#define VPMPCC_OGAM_CONTROL__VPMPCC_OGAM_PWL_DISABLE_MASK 0x00000008L +#define VPMPCC_OGAM_CONTROL__VPMPCC_OGAM_MODE_CURRENT_MASK 0x00000180L +#define VPMPCC_OGAM_CONTROL__VPMPCC_OGAM_SELECT_CURRENT_MASK 0x00000200L +//VPMPCC_OGAM_LUT_INDEX +#define VPMPCC_OGAM_LUT_INDEX__VPMPCC_OGAM_LUT_INDEX__SHIFT 0x0 +#define VPMPCC_OGAM_LUT_INDEX__VPMPCC_OGAM_LUT_INDEX_MASK 0x000001FFL +//VPMPCC_OGAM_LUT_DATA +#define VPMPCC_OGAM_LUT_DATA__VPMPCC_OGAM_LUT_DATA__SHIFT 0x0 +#define VPMPCC_OGAM_LUT_DATA__VPMPCC_OGAM_LUT_DATA_MASK 0x0003FFFFL +//VPMPCC_OGAM_LUT_CONTROL +#define VPMPCC_OGAM_LUT_CONTROL__VPMPCC_OGAM_LUT_WRITE_COLOR_MASK__SHIFT 0x0 +#define VPMPCC_OGAM_LUT_CONTROL__VPMPCC_OGAM_LUT_READ_COLOR_SEL__SHIFT 0x3 +#define VPMPCC_OGAM_LUT_CONTROL__VPMPCC_OGAM_LUT_READ_DBG__SHIFT 0x5 +#define VPMPCC_OGAM_LUT_CONTROL__VPMPCC_OGAM_LUT_HOST_SEL__SHIFT 0x6 +#define VPMPCC_OGAM_LUT_CONTROL__VPMPCC_OGAM_LUT_CONFIG_MODE__SHIFT 0x7 +#define VPMPCC_OGAM_LUT_CONTROL__VPMPCC_OGAM_LUT_WRITE_COLOR_MASK_MASK 0x00000007L +#define VPMPCC_OGAM_LUT_CONTROL__VPMPCC_OGAM_LUT_READ_COLOR_SEL_MASK 0x00000018L +#define VPMPCC_OGAM_LUT_CONTROL__VPMPCC_OGAM_LUT_READ_DBG_MASK 0x00000020L +#define VPMPCC_OGAM_LUT_CONTROL__VPMPCC_OGAM_LUT_HOST_SEL_MASK 0x00000040L +#define VPMPCC_OGAM_LUT_CONTROL__VPMPCC_OGAM_LUT_CONFIG_MODE_MASK 0x00000080L +//VPMPCC_OGAM_RAMA_START_CNTL_B +#define VPMPCC_OGAM_RAMA_START_CNTL_B__VPMPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define VPMPCC_OGAM_RAMA_START_CNTL_B__VPMPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define VPMPCC_OGAM_RAMA_START_CNTL_B__VPMPCC_OGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define VPMPCC_OGAM_RAMA_START_CNTL_B__VPMPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//VPMPCC_OGAM_RAMA_START_CNTL_G +#define VPMPCC_OGAM_RAMA_START_CNTL_G__VPMPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define VPMPCC_OGAM_RAMA_START_CNTL_G__VPMPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define VPMPCC_OGAM_RAMA_START_CNTL_G__VPMPCC_OGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define VPMPCC_OGAM_RAMA_START_CNTL_G__VPMPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//VPMPCC_OGAM_RAMA_START_CNTL_R +#define VPMPCC_OGAM_RAMA_START_CNTL_R__VPMPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define VPMPCC_OGAM_RAMA_START_CNTL_R__VPMPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define VPMPCC_OGAM_RAMA_START_CNTL_R__VPMPCC_OGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define VPMPCC_OGAM_RAMA_START_CNTL_R__VPMPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_B +#define VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_B__VPMPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_B__VPMPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_G +#define VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_G__VPMPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_G__VPMPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_R +#define VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_R__VPMPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_R__VPMPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//VPMPCC_OGAM_RAMA_START_BASE_CNTL_B +#define VPMPCC_OGAM_RAMA_START_BASE_CNTL_B__VPMPCC_OGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define VPMPCC_OGAM_RAMA_START_BASE_CNTL_B__VPMPCC_OGAM_RAMA_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//VPMPCC_OGAM_RAMA_START_BASE_CNTL_G +#define VPMPCC_OGAM_RAMA_START_BASE_CNTL_G__VPMPCC_OGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define VPMPCC_OGAM_RAMA_START_BASE_CNTL_G__VPMPCC_OGAM_RAMA_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//VPMPCC_OGAM_RAMA_START_BASE_CNTL_R +#define VPMPCC_OGAM_RAMA_START_BASE_CNTL_R__VPMPCC_OGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define VPMPCC_OGAM_RAMA_START_BASE_CNTL_R__VPMPCC_OGAM_RAMA_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//VPMPCC_OGAM_RAMA_END_CNTL1_B +#define VPMPCC_OGAM_RAMA_END_CNTL1_B__VPMPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define VPMPCC_OGAM_RAMA_END_CNTL1_B__VPMPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//VPMPCC_OGAM_RAMA_END_CNTL2_B +#define VPMPCC_OGAM_RAMA_END_CNTL2_B__VPMPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define VPMPCC_OGAM_RAMA_END_CNTL2_B__VPMPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define VPMPCC_OGAM_RAMA_END_CNTL2_B__VPMPCC_OGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define VPMPCC_OGAM_RAMA_END_CNTL2_B__VPMPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//VPMPCC_OGAM_RAMA_END_CNTL1_G +#define VPMPCC_OGAM_RAMA_END_CNTL1_G__VPMPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define VPMPCC_OGAM_RAMA_END_CNTL1_G__VPMPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//VPMPCC_OGAM_RAMA_END_CNTL2_G +#define VPMPCC_OGAM_RAMA_END_CNTL2_G__VPMPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define VPMPCC_OGAM_RAMA_END_CNTL2_G__VPMPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define VPMPCC_OGAM_RAMA_END_CNTL2_G__VPMPCC_OGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define VPMPCC_OGAM_RAMA_END_CNTL2_G__VPMPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//VPMPCC_OGAM_RAMA_END_CNTL1_R +#define VPMPCC_OGAM_RAMA_END_CNTL1_R__VPMPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define VPMPCC_OGAM_RAMA_END_CNTL1_R__VPMPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//VPMPCC_OGAM_RAMA_END_CNTL2_R +#define VPMPCC_OGAM_RAMA_END_CNTL2_R__VPMPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define VPMPCC_OGAM_RAMA_END_CNTL2_R__VPMPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define VPMPCC_OGAM_RAMA_END_CNTL2_R__VPMPCC_OGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define VPMPCC_OGAM_RAMA_END_CNTL2_R__VPMPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//VPMPCC_OGAM_RAMA_OFFSET_B +#define VPMPCC_OGAM_RAMA_OFFSET_B__VPMPCC_OGAM_RAMA_OFFSET_B__SHIFT 0x0 +#define VPMPCC_OGAM_RAMA_OFFSET_B__VPMPCC_OGAM_RAMA_OFFSET_B_MASK 0x0007FFFFL +//VPMPCC_OGAM_RAMA_OFFSET_G +#define VPMPCC_OGAM_RAMA_OFFSET_G__VPMPCC_OGAM_RAMA_OFFSET_G__SHIFT 0x0 +#define VPMPCC_OGAM_RAMA_OFFSET_G__VPMPCC_OGAM_RAMA_OFFSET_G_MASK 0x0007FFFFL +//VPMPCC_OGAM_RAMA_OFFSET_R +#define VPMPCC_OGAM_RAMA_OFFSET_R__VPMPCC_OGAM_RAMA_OFFSET_R__SHIFT 0x0 +#define VPMPCC_OGAM_RAMA_OFFSET_R__VPMPCC_OGAM_RAMA_OFFSET_R_MASK 0x0007FFFFL +//VPMPCC_OGAM_RAMA_REGION_0_1 +#define VPMPCC_OGAM_RAMA_REGION_0_1__VPMPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define VPMPCC_OGAM_RAMA_REGION_0_1__VPMPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define VPMPCC_OGAM_RAMA_REGION_0_1__VPMPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define VPMPCC_OGAM_RAMA_REGION_0_1__VPMPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define VPMPCC_OGAM_RAMA_REGION_0_1__VPMPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define VPMPCC_OGAM_RAMA_REGION_0_1__VPMPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define VPMPCC_OGAM_RAMA_REGION_0_1__VPMPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define VPMPCC_OGAM_RAMA_REGION_0_1__VPMPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//VPMPCC_OGAM_RAMA_REGION_2_3 +#define VPMPCC_OGAM_RAMA_REGION_2_3__VPMPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define VPMPCC_OGAM_RAMA_REGION_2_3__VPMPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define VPMPCC_OGAM_RAMA_REGION_2_3__VPMPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define VPMPCC_OGAM_RAMA_REGION_2_3__VPMPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define VPMPCC_OGAM_RAMA_REGION_2_3__VPMPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define VPMPCC_OGAM_RAMA_REGION_2_3__VPMPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define VPMPCC_OGAM_RAMA_REGION_2_3__VPMPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define VPMPCC_OGAM_RAMA_REGION_2_3__VPMPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//VPMPCC_OGAM_RAMA_REGION_4_5 +#define VPMPCC_OGAM_RAMA_REGION_4_5__VPMPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define VPMPCC_OGAM_RAMA_REGION_4_5__VPMPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define VPMPCC_OGAM_RAMA_REGION_4_5__VPMPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define VPMPCC_OGAM_RAMA_REGION_4_5__VPMPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define VPMPCC_OGAM_RAMA_REGION_4_5__VPMPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define VPMPCC_OGAM_RAMA_REGION_4_5__VPMPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define VPMPCC_OGAM_RAMA_REGION_4_5__VPMPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define VPMPCC_OGAM_RAMA_REGION_4_5__VPMPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//VPMPCC_OGAM_RAMA_REGION_6_7 +#define VPMPCC_OGAM_RAMA_REGION_6_7__VPMPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define VPMPCC_OGAM_RAMA_REGION_6_7__VPMPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define VPMPCC_OGAM_RAMA_REGION_6_7__VPMPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define VPMPCC_OGAM_RAMA_REGION_6_7__VPMPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define VPMPCC_OGAM_RAMA_REGION_6_7__VPMPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define VPMPCC_OGAM_RAMA_REGION_6_7__VPMPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define VPMPCC_OGAM_RAMA_REGION_6_7__VPMPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define VPMPCC_OGAM_RAMA_REGION_6_7__VPMPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//VPMPCC_OGAM_RAMA_REGION_8_9 +#define VPMPCC_OGAM_RAMA_REGION_8_9__VPMPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define VPMPCC_OGAM_RAMA_REGION_8_9__VPMPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define VPMPCC_OGAM_RAMA_REGION_8_9__VPMPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define VPMPCC_OGAM_RAMA_REGION_8_9__VPMPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define VPMPCC_OGAM_RAMA_REGION_8_9__VPMPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define VPMPCC_OGAM_RAMA_REGION_8_9__VPMPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define VPMPCC_OGAM_RAMA_REGION_8_9__VPMPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define VPMPCC_OGAM_RAMA_REGION_8_9__VPMPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//VPMPCC_OGAM_RAMA_REGION_10_11 +#define VPMPCC_OGAM_RAMA_REGION_10_11__VPMPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define VPMPCC_OGAM_RAMA_REGION_10_11__VPMPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define VPMPCC_OGAM_RAMA_REGION_10_11__VPMPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define VPMPCC_OGAM_RAMA_REGION_10_11__VPMPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define VPMPCC_OGAM_RAMA_REGION_10_11__VPMPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define VPMPCC_OGAM_RAMA_REGION_10_11__VPMPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define VPMPCC_OGAM_RAMA_REGION_10_11__VPMPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define VPMPCC_OGAM_RAMA_REGION_10_11__VPMPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//VPMPCC_OGAM_RAMA_REGION_12_13 +#define VPMPCC_OGAM_RAMA_REGION_12_13__VPMPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define VPMPCC_OGAM_RAMA_REGION_12_13__VPMPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define VPMPCC_OGAM_RAMA_REGION_12_13__VPMPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define VPMPCC_OGAM_RAMA_REGION_12_13__VPMPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define VPMPCC_OGAM_RAMA_REGION_12_13__VPMPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define VPMPCC_OGAM_RAMA_REGION_12_13__VPMPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define VPMPCC_OGAM_RAMA_REGION_12_13__VPMPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define VPMPCC_OGAM_RAMA_REGION_12_13__VPMPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//VPMPCC_OGAM_RAMA_REGION_14_15 +#define VPMPCC_OGAM_RAMA_REGION_14_15__VPMPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define VPMPCC_OGAM_RAMA_REGION_14_15__VPMPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define VPMPCC_OGAM_RAMA_REGION_14_15__VPMPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define VPMPCC_OGAM_RAMA_REGION_14_15__VPMPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define VPMPCC_OGAM_RAMA_REGION_14_15__VPMPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define VPMPCC_OGAM_RAMA_REGION_14_15__VPMPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define VPMPCC_OGAM_RAMA_REGION_14_15__VPMPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define VPMPCC_OGAM_RAMA_REGION_14_15__VPMPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//VPMPCC_OGAM_RAMA_REGION_16_17 +#define VPMPCC_OGAM_RAMA_REGION_16_17__VPMPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define VPMPCC_OGAM_RAMA_REGION_16_17__VPMPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define VPMPCC_OGAM_RAMA_REGION_16_17__VPMPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define VPMPCC_OGAM_RAMA_REGION_16_17__VPMPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define VPMPCC_OGAM_RAMA_REGION_16_17__VPMPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define VPMPCC_OGAM_RAMA_REGION_16_17__VPMPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define VPMPCC_OGAM_RAMA_REGION_16_17__VPMPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define VPMPCC_OGAM_RAMA_REGION_16_17__VPMPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//VPMPCC_OGAM_RAMA_REGION_18_19 +#define VPMPCC_OGAM_RAMA_REGION_18_19__VPMPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define VPMPCC_OGAM_RAMA_REGION_18_19__VPMPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define VPMPCC_OGAM_RAMA_REGION_18_19__VPMPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define VPMPCC_OGAM_RAMA_REGION_18_19__VPMPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define VPMPCC_OGAM_RAMA_REGION_18_19__VPMPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define VPMPCC_OGAM_RAMA_REGION_18_19__VPMPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define VPMPCC_OGAM_RAMA_REGION_18_19__VPMPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define VPMPCC_OGAM_RAMA_REGION_18_19__VPMPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//VPMPCC_OGAM_RAMA_REGION_20_21 +#define VPMPCC_OGAM_RAMA_REGION_20_21__VPMPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define VPMPCC_OGAM_RAMA_REGION_20_21__VPMPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define VPMPCC_OGAM_RAMA_REGION_20_21__VPMPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define VPMPCC_OGAM_RAMA_REGION_20_21__VPMPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define VPMPCC_OGAM_RAMA_REGION_20_21__VPMPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define VPMPCC_OGAM_RAMA_REGION_20_21__VPMPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define VPMPCC_OGAM_RAMA_REGION_20_21__VPMPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define VPMPCC_OGAM_RAMA_REGION_20_21__VPMPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//VPMPCC_OGAM_RAMA_REGION_22_23 +#define VPMPCC_OGAM_RAMA_REGION_22_23__VPMPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define VPMPCC_OGAM_RAMA_REGION_22_23__VPMPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define VPMPCC_OGAM_RAMA_REGION_22_23__VPMPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define VPMPCC_OGAM_RAMA_REGION_22_23__VPMPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define VPMPCC_OGAM_RAMA_REGION_22_23__VPMPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define VPMPCC_OGAM_RAMA_REGION_22_23__VPMPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define VPMPCC_OGAM_RAMA_REGION_22_23__VPMPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define VPMPCC_OGAM_RAMA_REGION_22_23__VPMPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//VPMPCC_OGAM_RAMA_REGION_24_25 +#define VPMPCC_OGAM_RAMA_REGION_24_25__VPMPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define VPMPCC_OGAM_RAMA_REGION_24_25__VPMPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define VPMPCC_OGAM_RAMA_REGION_24_25__VPMPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define VPMPCC_OGAM_RAMA_REGION_24_25__VPMPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define VPMPCC_OGAM_RAMA_REGION_24_25__VPMPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define VPMPCC_OGAM_RAMA_REGION_24_25__VPMPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define VPMPCC_OGAM_RAMA_REGION_24_25__VPMPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define VPMPCC_OGAM_RAMA_REGION_24_25__VPMPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//VPMPCC_OGAM_RAMA_REGION_26_27 +#define VPMPCC_OGAM_RAMA_REGION_26_27__VPMPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define VPMPCC_OGAM_RAMA_REGION_26_27__VPMPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define VPMPCC_OGAM_RAMA_REGION_26_27__VPMPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define VPMPCC_OGAM_RAMA_REGION_26_27__VPMPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define VPMPCC_OGAM_RAMA_REGION_26_27__VPMPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define VPMPCC_OGAM_RAMA_REGION_26_27__VPMPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define VPMPCC_OGAM_RAMA_REGION_26_27__VPMPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define VPMPCC_OGAM_RAMA_REGION_26_27__VPMPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//VPMPCC_OGAM_RAMA_REGION_28_29 +#define VPMPCC_OGAM_RAMA_REGION_28_29__VPMPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define VPMPCC_OGAM_RAMA_REGION_28_29__VPMPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define VPMPCC_OGAM_RAMA_REGION_28_29__VPMPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define VPMPCC_OGAM_RAMA_REGION_28_29__VPMPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define VPMPCC_OGAM_RAMA_REGION_28_29__VPMPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define VPMPCC_OGAM_RAMA_REGION_28_29__VPMPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define VPMPCC_OGAM_RAMA_REGION_28_29__VPMPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define VPMPCC_OGAM_RAMA_REGION_28_29__VPMPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//VPMPCC_OGAM_RAMA_REGION_30_31 +#define VPMPCC_OGAM_RAMA_REGION_30_31__VPMPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define VPMPCC_OGAM_RAMA_REGION_30_31__VPMPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define VPMPCC_OGAM_RAMA_REGION_30_31__VPMPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define VPMPCC_OGAM_RAMA_REGION_30_31__VPMPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define VPMPCC_OGAM_RAMA_REGION_30_31__VPMPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define VPMPCC_OGAM_RAMA_REGION_30_31__VPMPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define VPMPCC_OGAM_RAMA_REGION_30_31__VPMPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define VPMPCC_OGAM_RAMA_REGION_30_31__VPMPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//VPMPCC_OGAM_RAMA_REGION_32_33 +#define VPMPCC_OGAM_RAMA_REGION_32_33__VPMPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define VPMPCC_OGAM_RAMA_REGION_32_33__VPMPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define VPMPCC_OGAM_RAMA_REGION_32_33__VPMPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define VPMPCC_OGAM_RAMA_REGION_32_33__VPMPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define VPMPCC_OGAM_RAMA_REGION_32_33__VPMPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define VPMPCC_OGAM_RAMA_REGION_32_33__VPMPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define VPMPCC_OGAM_RAMA_REGION_32_33__VPMPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define VPMPCC_OGAM_RAMA_REGION_32_33__VPMPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//VPMPCC_GAMUT_REMAP_COEF_FORMAT +#define VPMPCC_GAMUT_REMAP_COEF_FORMAT__VPMPCC_GAMUT_REMAP_COEF_FORMAT__SHIFT 0x0 +#define VPMPCC_GAMUT_REMAP_COEF_FORMAT__VPMPCC_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000001L +//VPMPCC_GAMUT_REMAP_MODE +#define VPMPCC_GAMUT_REMAP_MODE__VPMPCC_GAMUT_REMAP_MODE__SHIFT 0x0 +#define VPMPCC_GAMUT_REMAP_MODE__VPMPCC_GAMUT_REMAP_MODE_CURRENT__SHIFT 0x7 +#define VPMPCC_GAMUT_REMAP_MODE__VPMPCC_GAMUT_REMAP_MODE_MASK 0x00000001L +#define VPMPCC_GAMUT_REMAP_MODE__VPMPCC_GAMUT_REMAP_MODE_CURRENT_MASK 0x00000080L +//VPMPC_GAMUT_REMAP_C11_C12_A +#define VPMPC_GAMUT_REMAP_C11_C12_A__VPMPCC_GAMUT_REMAP_C11_A__SHIFT 0x0 +#define VPMPC_GAMUT_REMAP_C11_C12_A__VPMPCC_GAMUT_REMAP_C12_A__SHIFT 0x10 +#define VPMPC_GAMUT_REMAP_C11_C12_A__VPMPCC_GAMUT_REMAP_C11_A_MASK 0x0000FFFFL +#define VPMPC_GAMUT_REMAP_C11_C12_A__VPMPCC_GAMUT_REMAP_C12_A_MASK 0xFFFF0000L +//VPMPC_GAMUT_REMAP_C13_C14_A +#define VPMPC_GAMUT_REMAP_C13_C14_A__VPMPCC_GAMUT_REMAP_C13_A__SHIFT 0x0 +#define VPMPC_GAMUT_REMAP_C13_C14_A__VPMPCC_GAMUT_REMAP_C14_A__SHIFT 0x10 +#define VPMPC_GAMUT_REMAP_C13_C14_A__VPMPCC_GAMUT_REMAP_C13_A_MASK 0x0000FFFFL +#define VPMPC_GAMUT_REMAP_C13_C14_A__VPMPCC_GAMUT_REMAP_C14_A_MASK 0xFFFF0000L +//VPMPC_GAMUT_REMAP_C21_C22_A +#define VPMPC_GAMUT_REMAP_C21_C22_A__VPMPCC_GAMUT_REMAP_C21_A__SHIFT 0x0 +#define VPMPC_GAMUT_REMAP_C21_C22_A__VPMPCC_GAMUT_REMAP_C22_A__SHIFT 0x10 +#define VPMPC_GAMUT_REMAP_C21_C22_A__VPMPCC_GAMUT_REMAP_C21_A_MASK 0x0000FFFFL +#define VPMPC_GAMUT_REMAP_C21_C22_A__VPMPCC_GAMUT_REMAP_C22_A_MASK 0xFFFF0000L +//VPMPC_GAMUT_REMAP_C23_C24_A +#define VPMPC_GAMUT_REMAP_C23_C24_A__VPMPCC_GAMUT_REMAP_C23_A__SHIFT 0x0 +#define VPMPC_GAMUT_REMAP_C23_C24_A__VPMPCC_GAMUT_REMAP_C24_A__SHIFT 0x10 +#define VPMPC_GAMUT_REMAP_C23_C24_A__VPMPCC_GAMUT_REMAP_C23_A_MASK 0x0000FFFFL +#define VPMPC_GAMUT_REMAP_C23_C24_A__VPMPCC_GAMUT_REMAP_C24_A_MASK 0xFFFF0000L +//VPMPC_GAMUT_REMAP_C31_C32_A +#define VPMPC_GAMUT_REMAP_C31_C32_A__VPMPCC_GAMUT_REMAP_C31_A__SHIFT 0x0 +#define VPMPC_GAMUT_REMAP_C31_C32_A__VPMPCC_GAMUT_REMAP_C32_A__SHIFT 0x10 +#define VPMPC_GAMUT_REMAP_C31_C32_A__VPMPCC_GAMUT_REMAP_C31_A_MASK 0x0000FFFFL +#define VPMPC_GAMUT_REMAP_C31_C32_A__VPMPCC_GAMUT_REMAP_C32_A_MASK 0xFFFF0000L +//VPMPC_GAMUT_REMAP_C33_C34_A +#define VPMPC_GAMUT_REMAP_C33_C34_A__VPMPCC_GAMUT_REMAP_C33_A__SHIFT 0x0 +#define VPMPC_GAMUT_REMAP_C33_C34_A__VPMPCC_GAMUT_REMAP_C34_A__SHIFT 0x10 +#define VPMPC_GAMUT_REMAP_C33_C34_A__VPMPCC_GAMUT_REMAP_C33_A_MASK 0x0000FFFFL +#define VPMPC_GAMUT_REMAP_C33_C34_A__VPMPCC_GAMUT_REMAP_C34_A_MASK 0xFFFF0000L +//VPMPCC_OGAM_TEST_DEBUG_INDEX +#define VPMPCC_OGAM_TEST_DEBUG_INDEX__VPMPCC_OGAM_TEST_DEBUG_INDEX__SHIFT 0x0 +#define VPMPCC_OGAM_TEST_DEBUG_INDEX__VPMPCC_OGAM_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define VPMPCC_OGAM_TEST_DEBUG_INDEX__VPMPCC_OGAM_TEST_DEBUG_INDEX_MASK 0x000000FFL +#define VPMPCC_OGAM_TEST_DEBUG_INDEX__VPMPCC_OGAM_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +//VPMPCC_OGAM_TEST_DEBUG_DATA +#define VPMPCC_OGAM_TEST_DEBUG_DATA__VPMPCC_OGAM_TEST_DEBUG_DATA__SHIFT 0x0 +#define VPMPCC_OGAM_TEST_DEBUG_DATA__VPMPCC_OGAM_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: vpe_vpep_vpmpc_vpmpcc_mcm0_dispdec +//VPMPCC_MCM_SHAPER_CONTROL +#define VPMPCC_MCM_SHAPER_CONTROL__VPMPCC_MCM_SHAPER_LUT_MODE__SHIFT 0x0 +#define VPMPCC_MCM_SHAPER_CONTROL__VPMPCC_MCM_SHAPER_MODE_CURRENT__SHIFT 0x2 +#define VPMPCC_MCM_SHAPER_CONTROL__VPMPCC_MCM_SHAPER_SELECT_CURRENT__SHIFT 0x4 +#define VPMPCC_MCM_SHAPER_CONTROL__VPMPCC_MCM_SHAPER_LUT_MODE_MASK 0x00000003L +#define VPMPCC_MCM_SHAPER_CONTROL__VPMPCC_MCM_SHAPER_MODE_CURRENT_MASK 0x0000000CL +#define VPMPCC_MCM_SHAPER_CONTROL__VPMPCC_MCM_SHAPER_SELECT_CURRENT_MASK 0x00000010L +//VPMPCC_MCM_SHAPER_OFFSET_R +#define VPMPCC_MCM_SHAPER_OFFSET_R__VPMPCC_MCM_SHAPER_OFFSET_R__SHIFT 0x0 +#define VPMPCC_MCM_SHAPER_OFFSET_R__VPMPCC_MCM_SHAPER_OFFSET_R_MASK 0x0007FFFFL +//VPMPCC_MCM_SHAPER_OFFSET_G +#define VPMPCC_MCM_SHAPER_OFFSET_G__VPMPCC_MCM_SHAPER_OFFSET_G__SHIFT 0x0 +#define VPMPCC_MCM_SHAPER_OFFSET_G__VPMPCC_MCM_SHAPER_OFFSET_G_MASK 0x0007FFFFL +//VPMPCC_MCM_SHAPER_OFFSET_B +#define VPMPCC_MCM_SHAPER_OFFSET_B__VPMPCC_MCM_SHAPER_OFFSET_B__SHIFT 0x0 +#define VPMPCC_MCM_SHAPER_OFFSET_B__VPMPCC_MCM_SHAPER_OFFSET_B_MASK 0x0007FFFFL +//VPMPCC_MCM_SHAPER_SCALE_R +#define VPMPCC_MCM_SHAPER_SCALE_R__VPMPCC_MCM_SHAPER_SCALE_R__SHIFT 0x0 +#define VPMPCC_MCM_SHAPER_SCALE_R__VPMPCC_MCM_SHAPER_SCALE_R_MASK 0x0000FFFFL +//VPMPCC_MCM_SHAPER_SCALE_G_B +#define VPMPCC_MCM_SHAPER_SCALE_G_B__VPMPCC_MCM_SHAPER_SCALE_G__SHIFT 0x0 +#define VPMPCC_MCM_SHAPER_SCALE_G_B__VPMPCC_MCM_SHAPER_SCALE_B__SHIFT 0x10 +#define VPMPCC_MCM_SHAPER_SCALE_G_B__VPMPCC_MCM_SHAPER_SCALE_G_MASK 0x0000FFFFL +#define VPMPCC_MCM_SHAPER_SCALE_G_B__VPMPCC_MCM_SHAPER_SCALE_B_MASK 0xFFFF0000L +//VPMPCC_MCM_SHAPER_LUT_INDEX +#define VPMPCC_MCM_SHAPER_LUT_INDEX__VPMPCC_MCM_SHAPER_LUT_INDEX__SHIFT 0x0 +#define VPMPCC_MCM_SHAPER_LUT_INDEX__VPMPCC_MCM_SHAPER_LUT_INDEX_MASK 0x000000FFL +//VPMPCC_MCM_SHAPER_LUT_DATA +#define VPMPCC_MCM_SHAPER_LUT_DATA__VPMPCC_MCM_SHAPER_LUT_DATA__SHIFT 0x0 +#define VPMPCC_MCM_SHAPER_LUT_DATA__VPMPCC_MCM_SHAPER_LUT_DATA_MASK 0x00FFFFFFL +//VPMPCC_MCM_SHAPER_LUT_WRITE_EN_MASK +#define VPMPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__VPMPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__SHIFT 0x0 +#define VPMPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__VPMPCC_MCM_SHAPER_LUT_WRITE_SEL__SHIFT 0x4 +#define VPMPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__VPMPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_MASK 0x00000007L +#define VPMPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__VPMPCC_MCM_SHAPER_LUT_WRITE_SEL_MASK 0x00000010L +//VPMPCC_MCM_SHAPER_RAMA_START_CNTL_B +#define VPMPCC_MCM_SHAPER_RAMA_START_CNTL_B__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define VPMPCC_MCM_SHAPER_RAMA_START_CNTL_B__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define VPMPCC_MCM_SHAPER_RAMA_START_CNTL_B__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define VPMPCC_MCM_SHAPER_RAMA_START_CNTL_B__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//VPMPCC_MCM_SHAPER_RAMA_START_CNTL_G +#define VPMPCC_MCM_SHAPER_RAMA_START_CNTL_G__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define VPMPCC_MCM_SHAPER_RAMA_START_CNTL_G__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define VPMPCC_MCM_SHAPER_RAMA_START_CNTL_G__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define VPMPCC_MCM_SHAPER_RAMA_START_CNTL_G__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//VPMPCC_MCM_SHAPER_RAMA_START_CNTL_R +#define VPMPCC_MCM_SHAPER_RAMA_START_CNTL_R__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define VPMPCC_MCM_SHAPER_RAMA_START_CNTL_R__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define VPMPCC_MCM_SHAPER_RAMA_START_CNTL_R__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define VPMPCC_MCM_SHAPER_RAMA_START_CNTL_R__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//VPMPCC_MCM_SHAPER_RAMA_END_CNTL_B +#define VPMPCC_MCM_SHAPER_RAMA_END_CNTL_B__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define VPMPCC_MCM_SHAPER_RAMA_END_CNTL_B__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define VPMPCC_MCM_SHAPER_RAMA_END_CNTL_B__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define VPMPCC_MCM_SHAPER_RAMA_END_CNTL_B__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK 0x3FFF0000L +//VPMPCC_MCM_SHAPER_RAMA_END_CNTL_G +#define VPMPCC_MCM_SHAPER_RAMA_END_CNTL_G__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define VPMPCC_MCM_SHAPER_RAMA_END_CNTL_G__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define VPMPCC_MCM_SHAPER_RAMA_END_CNTL_G__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define VPMPCC_MCM_SHAPER_RAMA_END_CNTL_G__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK 0x3FFF0000L +//VPMPCC_MCM_SHAPER_RAMA_END_CNTL_R +#define VPMPCC_MCM_SHAPER_RAMA_END_CNTL_R__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define VPMPCC_MCM_SHAPER_RAMA_END_CNTL_R__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define VPMPCC_MCM_SHAPER_RAMA_END_CNTL_R__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define VPMPCC_MCM_SHAPER_RAMA_END_CNTL_R__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK 0x3FFF0000L +//VPMPCC_MCM_SHAPER_RAMA_REGION_0_1 +#define VPMPCC_MCM_SHAPER_RAMA_REGION_0_1__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define VPMPCC_MCM_SHAPER_RAMA_REGION_0_1__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define VPMPCC_MCM_SHAPER_RAMA_REGION_0_1__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define VPMPCC_MCM_SHAPER_RAMA_REGION_0_1__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define VPMPCC_MCM_SHAPER_RAMA_REGION_0_1__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define VPMPCC_MCM_SHAPER_RAMA_REGION_0_1__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define VPMPCC_MCM_SHAPER_RAMA_REGION_0_1__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define VPMPCC_MCM_SHAPER_RAMA_REGION_0_1__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//VPMPCC_MCM_SHAPER_RAMA_REGION_2_3 +#define VPMPCC_MCM_SHAPER_RAMA_REGION_2_3__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define VPMPCC_MCM_SHAPER_RAMA_REGION_2_3__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define VPMPCC_MCM_SHAPER_RAMA_REGION_2_3__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define VPMPCC_MCM_SHAPER_RAMA_REGION_2_3__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define VPMPCC_MCM_SHAPER_RAMA_REGION_2_3__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define VPMPCC_MCM_SHAPER_RAMA_REGION_2_3__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define VPMPCC_MCM_SHAPER_RAMA_REGION_2_3__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define VPMPCC_MCM_SHAPER_RAMA_REGION_2_3__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//VPMPCC_MCM_SHAPER_RAMA_REGION_4_5 +#define VPMPCC_MCM_SHAPER_RAMA_REGION_4_5__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define VPMPCC_MCM_SHAPER_RAMA_REGION_4_5__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define VPMPCC_MCM_SHAPER_RAMA_REGION_4_5__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define VPMPCC_MCM_SHAPER_RAMA_REGION_4_5__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define VPMPCC_MCM_SHAPER_RAMA_REGION_4_5__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define VPMPCC_MCM_SHAPER_RAMA_REGION_4_5__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define VPMPCC_MCM_SHAPER_RAMA_REGION_4_5__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define VPMPCC_MCM_SHAPER_RAMA_REGION_4_5__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//VPMPCC_MCM_SHAPER_RAMA_REGION_6_7 +#define VPMPCC_MCM_SHAPER_RAMA_REGION_6_7__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define VPMPCC_MCM_SHAPER_RAMA_REGION_6_7__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define VPMPCC_MCM_SHAPER_RAMA_REGION_6_7__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define VPMPCC_MCM_SHAPER_RAMA_REGION_6_7__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define VPMPCC_MCM_SHAPER_RAMA_REGION_6_7__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define VPMPCC_MCM_SHAPER_RAMA_REGION_6_7__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define VPMPCC_MCM_SHAPER_RAMA_REGION_6_7__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define VPMPCC_MCM_SHAPER_RAMA_REGION_6_7__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//VPMPCC_MCM_SHAPER_RAMA_REGION_8_9 +#define VPMPCC_MCM_SHAPER_RAMA_REGION_8_9__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define VPMPCC_MCM_SHAPER_RAMA_REGION_8_9__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define VPMPCC_MCM_SHAPER_RAMA_REGION_8_9__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define VPMPCC_MCM_SHAPER_RAMA_REGION_8_9__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define VPMPCC_MCM_SHAPER_RAMA_REGION_8_9__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define VPMPCC_MCM_SHAPER_RAMA_REGION_8_9__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define VPMPCC_MCM_SHAPER_RAMA_REGION_8_9__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define VPMPCC_MCM_SHAPER_RAMA_REGION_8_9__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//VPMPCC_MCM_SHAPER_RAMA_REGION_10_11 +#define VPMPCC_MCM_SHAPER_RAMA_REGION_10_11__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define VPMPCC_MCM_SHAPER_RAMA_REGION_10_11__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define VPMPCC_MCM_SHAPER_RAMA_REGION_10_11__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define VPMPCC_MCM_SHAPER_RAMA_REGION_10_11__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define VPMPCC_MCM_SHAPER_RAMA_REGION_10_11__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define VPMPCC_MCM_SHAPER_RAMA_REGION_10_11__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define VPMPCC_MCM_SHAPER_RAMA_REGION_10_11__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define VPMPCC_MCM_SHAPER_RAMA_REGION_10_11__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//VPMPCC_MCM_SHAPER_RAMA_REGION_12_13 +#define VPMPCC_MCM_SHAPER_RAMA_REGION_12_13__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define VPMPCC_MCM_SHAPER_RAMA_REGION_12_13__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define VPMPCC_MCM_SHAPER_RAMA_REGION_12_13__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define VPMPCC_MCM_SHAPER_RAMA_REGION_12_13__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define VPMPCC_MCM_SHAPER_RAMA_REGION_12_13__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define VPMPCC_MCM_SHAPER_RAMA_REGION_12_13__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define VPMPCC_MCM_SHAPER_RAMA_REGION_12_13__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define VPMPCC_MCM_SHAPER_RAMA_REGION_12_13__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//VPMPCC_MCM_SHAPER_RAMA_REGION_14_15 +#define VPMPCC_MCM_SHAPER_RAMA_REGION_14_15__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define VPMPCC_MCM_SHAPER_RAMA_REGION_14_15__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define VPMPCC_MCM_SHAPER_RAMA_REGION_14_15__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define VPMPCC_MCM_SHAPER_RAMA_REGION_14_15__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define VPMPCC_MCM_SHAPER_RAMA_REGION_14_15__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define VPMPCC_MCM_SHAPER_RAMA_REGION_14_15__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define VPMPCC_MCM_SHAPER_RAMA_REGION_14_15__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define VPMPCC_MCM_SHAPER_RAMA_REGION_14_15__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//VPMPCC_MCM_SHAPER_RAMA_REGION_16_17 +#define VPMPCC_MCM_SHAPER_RAMA_REGION_16_17__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define VPMPCC_MCM_SHAPER_RAMA_REGION_16_17__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define VPMPCC_MCM_SHAPER_RAMA_REGION_16_17__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define VPMPCC_MCM_SHAPER_RAMA_REGION_16_17__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define VPMPCC_MCM_SHAPER_RAMA_REGION_16_17__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define VPMPCC_MCM_SHAPER_RAMA_REGION_16_17__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define VPMPCC_MCM_SHAPER_RAMA_REGION_16_17__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define VPMPCC_MCM_SHAPER_RAMA_REGION_16_17__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//VPMPCC_MCM_SHAPER_RAMA_REGION_18_19 +#define VPMPCC_MCM_SHAPER_RAMA_REGION_18_19__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define VPMPCC_MCM_SHAPER_RAMA_REGION_18_19__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define VPMPCC_MCM_SHAPER_RAMA_REGION_18_19__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define VPMPCC_MCM_SHAPER_RAMA_REGION_18_19__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define VPMPCC_MCM_SHAPER_RAMA_REGION_18_19__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define VPMPCC_MCM_SHAPER_RAMA_REGION_18_19__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define VPMPCC_MCM_SHAPER_RAMA_REGION_18_19__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define VPMPCC_MCM_SHAPER_RAMA_REGION_18_19__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//VPMPCC_MCM_SHAPER_RAMA_REGION_20_21 +#define VPMPCC_MCM_SHAPER_RAMA_REGION_20_21__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define VPMPCC_MCM_SHAPER_RAMA_REGION_20_21__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define VPMPCC_MCM_SHAPER_RAMA_REGION_20_21__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define VPMPCC_MCM_SHAPER_RAMA_REGION_20_21__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define VPMPCC_MCM_SHAPER_RAMA_REGION_20_21__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define VPMPCC_MCM_SHAPER_RAMA_REGION_20_21__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define VPMPCC_MCM_SHAPER_RAMA_REGION_20_21__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define VPMPCC_MCM_SHAPER_RAMA_REGION_20_21__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//VPMPCC_MCM_SHAPER_RAMA_REGION_22_23 +#define VPMPCC_MCM_SHAPER_RAMA_REGION_22_23__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define VPMPCC_MCM_SHAPER_RAMA_REGION_22_23__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define VPMPCC_MCM_SHAPER_RAMA_REGION_22_23__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define VPMPCC_MCM_SHAPER_RAMA_REGION_22_23__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define VPMPCC_MCM_SHAPER_RAMA_REGION_22_23__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define VPMPCC_MCM_SHAPER_RAMA_REGION_22_23__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define VPMPCC_MCM_SHAPER_RAMA_REGION_22_23__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define VPMPCC_MCM_SHAPER_RAMA_REGION_22_23__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//VPMPCC_MCM_SHAPER_RAMA_REGION_24_25 +#define VPMPCC_MCM_SHAPER_RAMA_REGION_24_25__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define VPMPCC_MCM_SHAPER_RAMA_REGION_24_25__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define VPMPCC_MCM_SHAPER_RAMA_REGION_24_25__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define VPMPCC_MCM_SHAPER_RAMA_REGION_24_25__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define VPMPCC_MCM_SHAPER_RAMA_REGION_24_25__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define VPMPCC_MCM_SHAPER_RAMA_REGION_24_25__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define VPMPCC_MCM_SHAPER_RAMA_REGION_24_25__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define VPMPCC_MCM_SHAPER_RAMA_REGION_24_25__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//VPMPCC_MCM_SHAPER_RAMA_REGION_26_27 +#define VPMPCC_MCM_SHAPER_RAMA_REGION_26_27__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define VPMPCC_MCM_SHAPER_RAMA_REGION_26_27__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define VPMPCC_MCM_SHAPER_RAMA_REGION_26_27__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define VPMPCC_MCM_SHAPER_RAMA_REGION_26_27__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define VPMPCC_MCM_SHAPER_RAMA_REGION_26_27__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define VPMPCC_MCM_SHAPER_RAMA_REGION_26_27__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define VPMPCC_MCM_SHAPER_RAMA_REGION_26_27__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define VPMPCC_MCM_SHAPER_RAMA_REGION_26_27__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//VPMPCC_MCM_SHAPER_RAMA_REGION_28_29 +#define VPMPCC_MCM_SHAPER_RAMA_REGION_28_29__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define VPMPCC_MCM_SHAPER_RAMA_REGION_28_29__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define VPMPCC_MCM_SHAPER_RAMA_REGION_28_29__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define VPMPCC_MCM_SHAPER_RAMA_REGION_28_29__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define VPMPCC_MCM_SHAPER_RAMA_REGION_28_29__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define VPMPCC_MCM_SHAPER_RAMA_REGION_28_29__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define VPMPCC_MCM_SHAPER_RAMA_REGION_28_29__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define VPMPCC_MCM_SHAPER_RAMA_REGION_28_29__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//VPMPCC_MCM_SHAPER_RAMA_REGION_30_31 +#define VPMPCC_MCM_SHAPER_RAMA_REGION_30_31__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define VPMPCC_MCM_SHAPER_RAMA_REGION_30_31__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define VPMPCC_MCM_SHAPER_RAMA_REGION_30_31__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define VPMPCC_MCM_SHAPER_RAMA_REGION_30_31__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define VPMPCC_MCM_SHAPER_RAMA_REGION_30_31__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define VPMPCC_MCM_SHAPER_RAMA_REGION_30_31__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define VPMPCC_MCM_SHAPER_RAMA_REGION_30_31__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define VPMPCC_MCM_SHAPER_RAMA_REGION_30_31__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//VPMPCC_MCM_SHAPER_RAMA_REGION_32_33 +#define VPMPCC_MCM_SHAPER_RAMA_REGION_32_33__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define VPMPCC_MCM_SHAPER_RAMA_REGION_32_33__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define VPMPCC_MCM_SHAPER_RAMA_REGION_32_33__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define VPMPCC_MCM_SHAPER_RAMA_REGION_32_33__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define VPMPCC_MCM_SHAPER_RAMA_REGION_32_33__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define VPMPCC_MCM_SHAPER_RAMA_REGION_32_33__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define VPMPCC_MCM_SHAPER_RAMA_REGION_32_33__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define VPMPCC_MCM_SHAPER_RAMA_REGION_32_33__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//VPMPCC_MCM_3DLUT_MODE +#define VPMPCC_MCM_3DLUT_MODE__VPMPCC_MCM_3DLUT_MODE__SHIFT 0x0 +#define VPMPCC_MCM_3DLUT_MODE__VPMPCC_MCM_3DLUT_SIZE__SHIFT 0x4 +#define VPMPCC_MCM_3DLUT_MODE__VPMPCC_MCM_3DLUT_MODE_CURRENT__SHIFT 0x8 +#define VPMPCC_MCM_3DLUT_MODE__VPMPCC_MCM_3DLUT_SELECT_CURRENT__SHIFT 0xa +#define VPMPCC_MCM_3DLUT_MODE__VPMPCC_MCM_3DLUT_MODE_MASK 0x00000003L +#define VPMPCC_MCM_3DLUT_MODE__VPMPCC_MCM_3DLUT_SIZE_MASK 0x00000010L +#define VPMPCC_MCM_3DLUT_MODE__VPMPCC_MCM_3DLUT_MODE_CURRENT_MASK 0x00000300L +#define VPMPCC_MCM_3DLUT_MODE__VPMPCC_MCM_3DLUT_SELECT_CURRENT_MASK 0x00000400L +//VPMPCC_MCM_3DLUT_INDEX +#define VPMPCC_MCM_3DLUT_INDEX__VPMPCC_MCM_3DLUT_INDEX__SHIFT 0x0 +#define VPMPCC_MCM_3DLUT_INDEX__VPMPCC_MCM_3DLUT_INDEX_MASK 0x000007FFL +//VPMPCC_MCM_3DLUT_DATA +#define VPMPCC_MCM_3DLUT_DATA__VPMPCC_MCM_3DLUT_DATA0__SHIFT 0x0 +#define VPMPCC_MCM_3DLUT_DATA__VPMPCC_MCM_3DLUT_DATA1__SHIFT 0x10 +#define VPMPCC_MCM_3DLUT_DATA__VPMPCC_MCM_3DLUT_DATA0_MASK 0x0000FFFFL +#define VPMPCC_MCM_3DLUT_DATA__VPMPCC_MCM_3DLUT_DATA1_MASK 0xFFFF0000L +//VPMPCC_MCM_3DLUT_DATA_30BIT +#define VPMPCC_MCM_3DLUT_DATA_30BIT__VPMPCC_MCM_3DLUT_DATA_30BIT__SHIFT 0x2 +#define VPMPCC_MCM_3DLUT_DATA_30BIT__VPMPCC_MCM_3DLUT_DATA_30BIT_MASK 0xFFFFFFFCL +//VPMPCC_MCM_3DLUT_READ_WRITE_CONTROL +#define VPMPCC_MCM_3DLUT_READ_WRITE_CONTROL__VPMPCC_MCM_3DLUT_WRITE_EN_MASK__SHIFT 0x0 +#define VPMPCC_MCM_3DLUT_READ_WRITE_CONTROL__VPMPCC_MCM_3DLUT_RAM_SEL__SHIFT 0x4 +#define VPMPCC_MCM_3DLUT_READ_WRITE_CONTROL__VPMPCC_MCM_3DLUT_30BIT_EN__SHIFT 0x8 +#define VPMPCC_MCM_3DLUT_READ_WRITE_CONTROL__VPMPCC_MCM_3DLUT_READ_SEL__SHIFT 0x10 +#define VPMPCC_MCM_3DLUT_READ_WRITE_CONTROL__VPMPCC_MCM_3DLUT_WRITE_EN_MASK_MASK 0x0000000FL +#define VPMPCC_MCM_3DLUT_READ_WRITE_CONTROL__VPMPCC_MCM_3DLUT_RAM_SEL_MASK 0x00000010L +#define VPMPCC_MCM_3DLUT_READ_WRITE_CONTROL__VPMPCC_MCM_3DLUT_30BIT_EN_MASK 0x00000100L +#define VPMPCC_MCM_3DLUT_READ_WRITE_CONTROL__VPMPCC_MCM_3DLUT_READ_SEL_MASK 0x00030000L +//VPMPCC_MCM_3DLUT_OUT_NORM_FACTOR +#define VPMPCC_MCM_3DLUT_OUT_NORM_FACTOR__VPMPCC_MCM_3DLUT_OUT_NORM_FACTOR__SHIFT 0x0 +#define VPMPCC_MCM_3DLUT_OUT_NORM_FACTOR__VPMPCC_MCM_3DLUT_OUT_NORM_FACTOR_MASK 0x0000FFFFL +//VPMPCC_MCM_3DLUT_OUT_OFFSET_R +#define VPMPCC_MCM_3DLUT_OUT_OFFSET_R__VPMPCC_MCM_3DLUT_OUT_OFFSET_R__SHIFT 0x0 +#define VPMPCC_MCM_3DLUT_OUT_OFFSET_R__VPMPCC_MCM_3DLUT_OUT_SCALE_R__SHIFT 0x10 +#define VPMPCC_MCM_3DLUT_OUT_OFFSET_R__VPMPCC_MCM_3DLUT_OUT_OFFSET_R_MASK 0x0000FFFFL +#define VPMPCC_MCM_3DLUT_OUT_OFFSET_R__VPMPCC_MCM_3DLUT_OUT_SCALE_R_MASK 0xFFFF0000L +//VPMPCC_MCM_3DLUT_OUT_OFFSET_G +#define VPMPCC_MCM_3DLUT_OUT_OFFSET_G__VPMPCC_MCM_3DLUT_OUT_OFFSET_G__SHIFT 0x0 +#define VPMPCC_MCM_3DLUT_OUT_OFFSET_G__VPMPCC_MCM_3DLUT_OUT_SCALE_G__SHIFT 0x10 +#define VPMPCC_MCM_3DLUT_OUT_OFFSET_G__VPMPCC_MCM_3DLUT_OUT_OFFSET_G_MASK 0x0000FFFFL +#define VPMPCC_MCM_3DLUT_OUT_OFFSET_G__VPMPCC_MCM_3DLUT_OUT_SCALE_G_MASK 0xFFFF0000L +//VPMPCC_MCM_3DLUT_OUT_OFFSET_B +#define VPMPCC_MCM_3DLUT_OUT_OFFSET_B__VPMPCC_MCM_3DLUT_OUT_OFFSET_B__SHIFT 0x0 +#define VPMPCC_MCM_3DLUT_OUT_OFFSET_B__VPMPCC_MCM_3DLUT_OUT_SCALE_B__SHIFT 0x10 +#define VPMPCC_MCM_3DLUT_OUT_OFFSET_B__VPMPCC_MCM_3DLUT_OUT_OFFSET_B_MASK 0x0000FFFFL +#define VPMPCC_MCM_3DLUT_OUT_OFFSET_B__VPMPCC_MCM_3DLUT_OUT_SCALE_B_MASK 0xFFFF0000L +//VPMPCC_MCM_1DLUT_CONTROL +#define VPMPCC_MCM_1DLUT_CONTROL__VPMPCC_MCM_1DLUT_MODE__SHIFT 0x0 +#define VPMPCC_MCM_1DLUT_CONTROL__VPMPCC_MCM_1DLUT_PWL_DISABLE__SHIFT 0x3 +#define VPMPCC_MCM_1DLUT_CONTROL__VPMPCC_MCM_1DLUT_MODE_CURRENT__SHIFT 0x4 +#define VPMPCC_MCM_1DLUT_CONTROL__VPMPCC_MCM_1DLUT_SELECT_CURRENT__SHIFT 0x6 +#define VPMPCC_MCM_1DLUT_CONTROL__VPMPCC_MCM_1DLUT_MODE_MASK 0x00000003L +#define VPMPCC_MCM_1DLUT_CONTROL__VPMPCC_MCM_1DLUT_PWL_DISABLE_MASK 0x00000008L +#define VPMPCC_MCM_1DLUT_CONTROL__VPMPCC_MCM_1DLUT_MODE_CURRENT_MASK 0x00000030L +#define VPMPCC_MCM_1DLUT_CONTROL__VPMPCC_MCM_1DLUT_SELECT_CURRENT_MASK 0x00000040L +//VPMPCC_MCM_1DLUT_LUT_INDEX +#define VPMPCC_MCM_1DLUT_LUT_INDEX__VPMPCC_MCM_1DLUT_LUT_INDEX__SHIFT 0x0 +#define VPMPCC_MCM_1DLUT_LUT_INDEX__VPMPCC_MCM_1DLUT_LUT_INDEX_MASK 0x000001FFL +//VPMPCC_MCM_1DLUT_LUT_DATA +#define VPMPCC_MCM_1DLUT_LUT_DATA__VPMPCC_MCM_1DLUT_LUT_DATA__SHIFT 0x0 +#define VPMPCC_MCM_1DLUT_LUT_DATA__VPMPCC_MCM_1DLUT_LUT_DATA_MASK 0x0003FFFFL +//VPMPCC_MCM_1DLUT_LUT_CONTROL +#define VPMPCC_MCM_1DLUT_LUT_CONTROL__VPMPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK__SHIFT 0x0 +#define VPMPCC_MCM_1DLUT_LUT_CONTROL__VPMPCC_MCM_1DLUT_LUT_READ_COLOR_SEL__SHIFT 0x3 +#define VPMPCC_MCM_1DLUT_LUT_CONTROL__VPMPCC_MCM_1DLUT_LUT_READ_DBG__SHIFT 0x5 +#define VPMPCC_MCM_1DLUT_LUT_CONTROL__VPMPCC_MCM_1DLUT_LUT_HOST_SEL__SHIFT 0x6 +#define VPMPCC_MCM_1DLUT_LUT_CONTROL__VPMPCC_MCM_1DLUT_LUT_CONFIG_MODE__SHIFT 0x7 +#define VPMPCC_MCM_1DLUT_LUT_CONTROL__VPMPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK_MASK 0x00000007L +#define VPMPCC_MCM_1DLUT_LUT_CONTROL__VPMPCC_MCM_1DLUT_LUT_READ_COLOR_SEL_MASK 0x00000018L +#define VPMPCC_MCM_1DLUT_LUT_CONTROL__VPMPCC_MCM_1DLUT_LUT_READ_DBG_MASK 0x00000020L +#define VPMPCC_MCM_1DLUT_LUT_CONTROL__VPMPCC_MCM_1DLUT_LUT_HOST_SEL_MASK 0x00000040L +#define VPMPCC_MCM_1DLUT_LUT_CONTROL__VPMPCC_MCM_1DLUT_LUT_CONFIG_MODE_MASK 0x00000080L +//VPMPCC_MCM_1DLUT_RAMA_START_CNTL_B +#define VPMPCC_MCM_1DLUT_RAMA_START_CNTL_B__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define VPMPCC_MCM_1DLUT_RAMA_START_CNTL_B__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define VPMPCC_MCM_1DLUT_RAMA_START_CNTL_B__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define VPMPCC_MCM_1DLUT_RAMA_START_CNTL_B__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//VPMPCC_MCM_1DLUT_RAMA_START_CNTL_G +#define VPMPCC_MCM_1DLUT_RAMA_START_CNTL_G__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define VPMPCC_MCM_1DLUT_RAMA_START_CNTL_G__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define VPMPCC_MCM_1DLUT_RAMA_START_CNTL_G__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define VPMPCC_MCM_1DLUT_RAMA_START_CNTL_G__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//VPMPCC_MCM_1DLUT_RAMA_START_CNTL_R +#define VPMPCC_MCM_1DLUT_RAMA_START_CNTL_R__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define VPMPCC_MCM_1DLUT_RAMA_START_CNTL_R__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define VPMPCC_MCM_1DLUT_RAMA_START_CNTL_R__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define VPMPCC_MCM_1DLUT_RAMA_START_CNTL_R__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B +#define VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G +#define VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R +#define VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B +#define VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G +#define VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R +#define VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_B +#define VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_B__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_B__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_B +#define VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_B__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_B__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_B__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_B__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_G +#define VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_G__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_G__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_G +#define VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_G__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_G__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_G__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_G__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_R +#define VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_R__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_R__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_R +#define VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_R__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_R__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_R__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_R__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//VPMPCC_MCM_1DLUT_RAMA_OFFSET_B +#define VPMPCC_MCM_1DLUT_RAMA_OFFSET_B__VPMPCC_MCM_1DLUT_RAMA_OFFSET_B__SHIFT 0x0 +#define VPMPCC_MCM_1DLUT_RAMA_OFFSET_B__VPMPCC_MCM_1DLUT_RAMA_OFFSET_B_MASK 0x0007FFFFL +//VPMPCC_MCM_1DLUT_RAMA_OFFSET_G +#define VPMPCC_MCM_1DLUT_RAMA_OFFSET_G__VPMPCC_MCM_1DLUT_RAMA_OFFSET_G__SHIFT 0x0 +#define VPMPCC_MCM_1DLUT_RAMA_OFFSET_G__VPMPCC_MCM_1DLUT_RAMA_OFFSET_G_MASK 0x0007FFFFL +//VPMPCC_MCM_1DLUT_RAMA_OFFSET_R +#define VPMPCC_MCM_1DLUT_RAMA_OFFSET_R__VPMPCC_MCM_1DLUT_RAMA_OFFSET_R__SHIFT 0x0 +#define VPMPCC_MCM_1DLUT_RAMA_OFFSET_R__VPMPCC_MCM_1DLUT_RAMA_OFFSET_R_MASK 0x0007FFFFL +//VPMPCC_MCM_1DLUT_RAMA_REGION_0_1 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_0_1__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_0_1__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define VPMPCC_MCM_1DLUT_RAMA_REGION_0_1__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_0_1__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define VPMPCC_MCM_1DLUT_RAMA_REGION_0_1__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_0_1__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define VPMPCC_MCM_1DLUT_RAMA_REGION_0_1__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define VPMPCC_MCM_1DLUT_RAMA_REGION_0_1__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//VPMPCC_MCM_1DLUT_RAMA_REGION_2_3 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_2_3__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_2_3__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define VPMPCC_MCM_1DLUT_RAMA_REGION_2_3__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_2_3__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define VPMPCC_MCM_1DLUT_RAMA_REGION_2_3__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_2_3__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define VPMPCC_MCM_1DLUT_RAMA_REGION_2_3__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define VPMPCC_MCM_1DLUT_RAMA_REGION_2_3__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//VPMPCC_MCM_1DLUT_RAMA_REGION_4_5 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_4_5__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_4_5__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define VPMPCC_MCM_1DLUT_RAMA_REGION_4_5__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_4_5__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define VPMPCC_MCM_1DLUT_RAMA_REGION_4_5__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_4_5__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define VPMPCC_MCM_1DLUT_RAMA_REGION_4_5__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define VPMPCC_MCM_1DLUT_RAMA_REGION_4_5__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//VPMPCC_MCM_1DLUT_RAMA_REGION_6_7 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_6_7__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_6_7__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define VPMPCC_MCM_1DLUT_RAMA_REGION_6_7__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_6_7__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define VPMPCC_MCM_1DLUT_RAMA_REGION_6_7__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_6_7__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define VPMPCC_MCM_1DLUT_RAMA_REGION_6_7__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define VPMPCC_MCM_1DLUT_RAMA_REGION_6_7__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//VPMPCC_MCM_1DLUT_RAMA_REGION_8_9 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_8_9__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_8_9__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define VPMPCC_MCM_1DLUT_RAMA_REGION_8_9__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_8_9__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define VPMPCC_MCM_1DLUT_RAMA_REGION_8_9__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_8_9__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define VPMPCC_MCM_1DLUT_RAMA_REGION_8_9__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define VPMPCC_MCM_1DLUT_RAMA_REGION_8_9__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//VPMPCC_MCM_1DLUT_RAMA_REGION_10_11 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_10_11__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_10_11__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define VPMPCC_MCM_1DLUT_RAMA_REGION_10_11__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_10_11__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define VPMPCC_MCM_1DLUT_RAMA_REGION_10_11__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_10_11__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define VPMPCC_MCM_1DLUT_RAMA_REGION_10_11__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define VPMPCC_MCM_1DLUT_RAMA_REGION_10_11__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//VPMPCC_MCM_1DLUT_RAMA_REGION_12_13 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_12_13__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_12_13__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define VPMPCC_MCM_1DLUT_RAMA_REGION_12_13__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_12_13__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define VPMPCC_MCM_1DLUT_RAMA_REGION_12_13__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_12_13__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define VPMPCC_MCM_1DLUT_RAMA_REGION_12_13__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define VPMPCC_MCM_1DLUT_RAMA_REGION_12_13__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//VPMPCC_MCM_1DLUT_RAMA_REGION_14_15 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_14_15__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_14_15__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define VPMPCC_MCM_1DLUT_RAMA_REGION_14_15__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_14_15__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define VPMPCC_MCM_1DLUT_RAMA_REGION_14_15__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_14_15__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define VPMPCC_MCM_1DLUT_RAMA_REGION_14_15__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define VPMPCC_MCM_1DLUT_RAMA_REGION_14_15__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//VPMPCC_MCM_1DLUT_RAMA_REGION_16_17 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_16_17__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_16_17__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define VPMPCC_MCM_1DLUT_RAMA_REGION_16_17__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_16_17__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define VPMPCC_MCM_1DLUT_RAMA_REGION_16_17__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_16_17__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define VPMPCC_MCM_1DLUT_RAMA_REGION_16_17__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define VPMPCC_MCM_1DLUT_RAMA_REGION_16_17__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//VPMPCC_MCM_1DLUT_RAMA_REGION_18_19 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_18_19__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_18_19__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define VPMPCC_MCM_1DLUT_RAMA_REGION_18_19__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_18_19__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define VPMPCC_MCM_1DLUT_RAMA_REGION_18_19__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_18_19__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define VPMPCC_MCM_1DLUT_RAMA_REGION_18_19__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define VPMPCC_MCM_1DLUT_RAMA_REGION_18_19__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//VPMPCC_MCM_1DLUT_RAMA_REGION_20_21 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_20_21__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_20_21__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define VPMPCC_MCM_1DLUT_RAMA_REGION_20_21__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_20_21__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define VPMPCC_MCM_1DLUT_RAMA_REGION_20_21__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_20_21__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define VPMPCC_MCM_1DLUT_RAMA_REGION_20_21__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define VPMPCC_MCM_1DLUT_RAMA_REGION_20_21__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//VPMPCC_MCM_1DLUT_RAMA_REGION_22_23 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_22_23__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_22_23__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define VPMPCC_MCM_1DLUT_RAMA_REGION_22_23__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_22_23__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define VPMPCC_MCM_1DLUT_RAMA_REGION_22_23__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_22_23__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define VPMPCC_MCM_1DLUT_RAMA_REGION_22_23__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define VPMPCC_MCM_1DLUT_RAMA_REGION_22_23__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//VPMPCC_MCM_1DLUT_RAMA_REGION_24_25 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_24_25__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_24_25__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define VPMPCC_MCM_1DLUT_RAMA_REGION_24_25__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_24_25__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define VPMPCC_MCM_1DLUT_RAMA_REGION_24_25__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_24_25__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define VPMPCC_MCM_1DLUT_RAMA_REGION_24_25__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define VPMPCC_MCM_1DLUT_RAMA_REGION_24_25__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//VPMPCC_MCM_1DLUT_RAMA_REGION_26_27 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_26_27__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_26_27__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define VPMPCC_MCM_1DLUT_RAMA_REGION_26_27__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_26_27__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define VPMPCC_MCM_1DLUT_RAMA_REGION_26_27__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_26_27__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define VPMPCC_MCM_1DLUT_RAMA_REGION_26_27__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define VPMPCC_MCM_1DLUT_RAMA_REGION_26_27__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//VPMPCC_MCM_1DLUT_RAMA_REGION_28_29 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_28_29__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_28_29__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define VPMPCC_MCM_1DLUT_RAMA_REGION_28_29__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_28_29__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define VPMPCC_MCM_1DLUT_RAMA_REGION_28_29__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_28_29__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define VPMPCC_MCM_1DLUT_RAMA_REGION_28_29__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define VPMPCC_MCM_1DLUT_RAMA_REGION_28_29__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//VPMPCC_MCM_1DLUT_RAMA_REGION_30_31 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_30_31__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_30_31__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define VPMPCC_MCM_1DLUT_RAMA_REGION_30_31__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_30_31__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define VPMPCC_MCM_1DLUT_RAMA_REGION_30_31__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_30_31__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define VPMPCC_MCM_1DLUT_RAMA_REGION_30_31__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define VPMPCC_MCM_1DLUT_RAMA_REGION_30_31__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//VPMPCC_MCM_1DLUT_RAMA_REGION_32_33 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_32_33__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_32_33__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define VPMPCC_MCM_1DLUT_RAMA_REGION_32_33__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_32_33__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define VPMPCC_MCM_1DLUT_RAMA_REGION_32_33__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_32_33__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define VPMPCC_MCM_1DLUT_RAMA_REGION_32_33__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define VPMPCC_MCM_1DLUT_RAMA_REGION_32_33__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//VPMPCC_MCM_MEM_PWR_CTRL +#define VPMPCC_MCM_MEM_PWR_CTRL__VPMPCC_MCM_SHAPER_MEM_PWR_FORCE__SHIFT 0x0 +#define VPMPCC_MCM_MEM_PWR_CTRL__VPMPCC_MCM_SHAPER_MEM_PWR_DIS__SHIFT 0x2 +#define VPMPCC_MCM_MEM_PWR_CTRL__VPMPCC_MCM_SHAPER_MEM_LOW_PWR_MODE__SHIFT 0x4 +#define VPMPCC_MCM_MEM_PWR_CTRL__VPMPCC_MCM_3DLUT_MEM_PWR_FORCE__SHIFT 0x8 +#define VPMPCC_MCM_MEM_PWR_CTRL__VPMPCC_MCM_3DLUT_MEM_PWR_DIS__SHIFT 0xa +#define VPMPCC_MCM_MEM_PWR_CTRL__VPMPCC_MCM_3DLUT_MEM_LOW_PWR_MODE__SHIFT 0xc +#define VPMPCC_MCM_MEM_PWR_CTRL__VPMPCC_MCM_1DLUT_MEM_PWR_FORCE__SHIFT 0x10 +#define VPMPCC_MCM_MEM_PWR_CTRL__VPMPCC_MCM_1DLUT_MEM_PWR_DIS__SHIFT 0x12 +#define VPMPCC_MCM_MEM_PWR_CTRL__VPMPCC_MCM_1DLUT_MEM_LOW_PWR_MODE__SHIFT 0x14 +#define VPMPCC_MCM_MEM_PWR_CTRL__VPMPCC_MCM_SHAPER_MEM_PWR_STATE__SHIFT 0x18 +#define VPMPCC_MCM_MEM_PWR_CTRL__VPMPCC_MCM_3DLUT_MEM_PWR_STATE__SHIFT 0x1a +#define VPMPCC_MCM_MEM_PWR_CTRL__VPMPCC_MCM_1DLUT_MEM_PWR_STATE__SHIFT 0x1c +#define VPMPCC_MCM_MEM_PWR_CTRL__VPMPCC_MCM_SHAPER_MEM_PWR_FORCE_MASK 0x00000003L +#define VPMPCC_MCM_MEM_PWR_CTRL__VPMPCC_MCM_SHAPER_MEM_PWR_DIS_MASK 0x00000004L +#define VPMPCC_MCM_MEM_PWR_CTRL__VPMPCC_MCM_SHAPER_MEM_LOW_PWR_MODE_MASK 0x00000030L +#define VPMPCC_MCM_MEM_PWR_CTRL__VPMPCC_MCM_3DLUT_MEM_PWR_FORCE_MASK 0x00000300L +#define VPMPCC_MCM_MEM_PWR_CTRL__VPMPCC_MCM_3DLUT_MEM_PWR_DIS_MASK 0x00000400L +#define VPMPCC_MCM_MEM_PWR_CTRL__VPMPCC_MCM_3DLUT_MEM_LOW_PWR_MODE_MASK 0x00003000L +#define VPMPCC_MCM_MEM_PWR_CTRL__VPMPCC_MCM_1DLUT_MEM_PWR_FORCE_MASK 0x00030000L +#define VPMPCC_MCM_MEM_PWR_CTRL__VPMPCC_MCM_1DLUT_MEM_PWR_DIS_MASK 0x00040000L +#define VPMPCC_MCM_MEM_PWR_CTRL__VPMPCC_MCM_1DLUT_MEM_LOW_PWR_MODE_MASK 0x00300000L +#define VPMPCC_MCM_MEM_PWR_CTRL__VPMPCC_MCM_SHAPER_MEM_PWR_STATE_MASK 0x03000000L +#define VPMPCC_MCM_MEM_PWR_CTRL__VPMPCC_MCM_3DLUT_MEM_PWR_STATE_MASK 0x0C000000L +#define VPMPCC_MCM_MEM_PWR_CTRL__VPMPCC_MCM_1DLUT_MEM_PWR_STATE_MASK 0x30000000L +//VPMPCC_MCM_TEST_DEBUG_INDEX +#define VPMPCC_MCM_TEST_DEBUG_INDEX__VPMPCC_MCM_TEST_DEBUG_INDEX__SHIFT 0x0 +#define VPMPCC_MCM_TEST_DEBUG_INDEX__VPMPCC_MCM_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define VPMPCC_MCM_TEST_DEBUG_INDEX__VPMPCC_MCM_TEST_DEBUG_INDEX_MASK 0x000000FFL +#define VPMPCC_MCM_TEST_DEBUG_INDEX__VPMPCC_MCM_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +//VPMPCC_MCM_TEST_DEBUG_DATA +#define VPMPCC_MCM_TEST_DEBUG_DATA__VPMPCC_MCM_TEST_DEBUG_DATA__SHIFT 0x0 +#define VPMPCC_MCM_TEST_DEBUG_DATA__VPMPCC_MCM_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: vpe_vpep_vpmpc_vpmpc_ocsc_dispdec +//VPMPC_OUT0_MUX +#define VPMPC_OUT0_MUX__VPMPC_OUT_MUX__SHIFT 0x0 +#define VPMPC_OUT0_MUX__VPMPC_OUT_MUX_MASK 0x0000000FL +//VPMPC_OUT0_FLOAT_CONTROL +#define VPMPC_OUT0_FLOAT_CONTROL__VPMPC_OUT_FLOAT_EN__SHIFT 0x0 +#define VPMPC_OUT0_FLOAT_CONTROL__VPMPC_OUT_FLOAT_EN_MASK 0x00000001L +//VPMPC_OUT0_DENORM_CONTROL +#define VPMPC_OUT0_DENORM_CONTROL__VPMPC_OUT_DENORM_CLAMP_MIN_R_CR__SHIFT 0x0 +#define VPMPC_OUT0_DENORM_CONTROL__VPMPC_OUT_DENORM_CLAMP_MAX_R_CR__SHIFT 0xc +#define VPMPC_OUT0_DENORM_CONTROL__VPMPC_OUT_DENORM_MODE__SHIFT 0x18 +#define VPMPC_OUT0_DENORM_CONTROL__VPMPC_OUT_DENORM_CLAMP_MIN_R_CR_MASK 0x00000FFFL +#define VPMPC_OUT0_DENORM_CONTROL__VPMPC_OUT_DENORM_CLAMP_MAX_R_CR_MASK 0x00FFF000L +#define VPMPC_OUT0_DENORM_CONTROL__VPMPC_OUT_DENORM_MODE_MASK 0x07000000L +//VPMPC_OUT0_DENORM_CLAMP_G_Y +#define VPMPC_OUT0_DENORM_CLAMP_G_Y__VPMPC_OUT_DENORM_CLAMP_MIN_G_Y__SHIFT 0x0 +#define VPMPC_OUT0_DENORM_CLAMP_G_Y__VPMPC_OUT_DENORM_CLAMP_MAX_G_Y__SHIFT 0xc +#define VPMPC_OUT0_DENORM_CLAMP_G_Y__VPMPC_OUT_DENORM_CLAMP_MIN_G_Y_MASK 0x00000FFFL +#define VPMPC_OUT0_DENORM_CLAMP_G_Y__VPMPC_OUT_DENORM_CLAMP_MAX_G_Y_MASK 0x00FFF000L +//VPMPC_OUT0_DENORM_CLAMP_B_CB +#define VPMPC_OUT0_DENORM_CLAMP_B_CB__VPMPC_OUT_DENORM_CLAMP_MIN_B_CB__SHIFT 0x0 +#define VPMPC_OUT0_DENORM_CLAMP_B_CB__VPMPC_OUT_DENORM_CLAMP_MAX_B_CB__SHIFT 0xc +#define VPMPC_OUT0_DENORM_CLAMP_B_CB__VPMPC_OUT_DENORM_CLAMP_MIN_B_CB_MASK 0x00000FFFL +#define VPMPC_OUT0_DENORM_CLAMP_B_CB__VPMPC_OUT_DENORM_CLAMP_MAX_B_CB_MASK 0x00FFF000L +//VPMPC_OUT_CSC_COEF_FORMAT +#define VPMPC_OUT_CSC_COEF_FORMAT__VPMPC_OCSC0_COEF_FORMAT__SHIFT 0x0 +#define VPMPC_OUT_CSC_COEF_FORMAT__VPMPC_OCSC0_COEF_FORMAT_MASK 0x00000001L +//VPMPC_OUT0_CSC_MODE +#define VPMPC_OUT0_CSC_MODE__VPMPC_OCSC_MODE__SHIFT 0x0 +#define VPMPC_OUT0_CSC_MODE__VPMPC_OCSC_MODE_CURRENT__SHIFT 0x7 +#define VPMPC_OUT0_CSC_MODE__VPMPC_OCSC_MODE_MASK 0x00000001L +#define VPMPC_OUT0_CSC_MODE__VPMPC_OCSC_MODE_CURRENT_MASK 0x00000080L +//VPMPC_OUT0_CSC_C11_C12_A +#define VPMPC_OUT0_CSC_C11_C12_A__VPMPC_OCSC_C11_A__SHIFT 0x0 +#define VPMPC_OUT0_CSC_C11_C12_A__VPMPC_OCSC_C12_A__SHIFT 0x10 +#define VPMPC_OUT0_CSC_C11_C12_A__VPMPC_OCSC_C11_A_MASK 0x0000FFFFL +#define VPMPC_OUT0_CSC_C11_C12_A__VPMPC_OCSC_C12_A_MASK 0xFFFF0000L +//VPMPC_OUT0_CSC_C13_C14_A +#define VPMPC_OUT0_CSC_C13_C14_A__VPMPC_OCSC_C13_A__SHIFT 0x0 +#define VPMPC_OUT0_CSC_C13_C14_A__VPMPC_OCSC_C14_A__SHIFT 0x10 +#define VPMPC_OUT0_CSC_C13_C14_A__VPMPC_OCSC_C13_A_MASK 0x0000FFFFL +#define VPMPC_OUT0_CSC_C13_C14_A__VPMPC_OCSC_C14_A_MASK 0xFFFF0000L +//VPMPC_OUT0_CSC_C21_C22_A +#define VPMPC_OUT0_CSC_C21_C22_A__VPMPC_OCSC_C21_A__SHIFT 0x0 +#define VPMPC_OUT0_CSC_C21_C22_A__VPMPC_OCSC_C22_A__SHIFT 0x10 +#define VPMPC_OUT0_CSC_C21_C22_A__VPMPC_OCSC_C21_A_MASK 0x0000FFFFL +#define VPMPC_OUT0_CSC_C21_C22_A__VPMPC_OCSC_C22_A_MASK 0xFFFF0000L +//VPMPC_OUT0_CSC_C23_C24_A +#define VPMPC_OUT0_CSC_C23_C24_A__VPMPC_OCSC_C23_A__SHIFT 0x0 +#define VPMPC_OUT0_CSC_C23_C24_A__VPMPC_OCSC_C24_A__SHIFT 0x10 +#define VPMPC_OUT0_CSC_C23_C24_A__VPMPC_OCSC_C23_A_MASK 0x0000FFFFL +#define VPMPC_OUT0_CSC_C23_C24_A__VPMPC_OCSC_C24_A_MASK 0xFFFF0000L +//VPMPC_OUT0_CSC_C31_C32_A +#define VPMPC_OUT0_CSC_C31_C32_A__VPMPC_OCSC_C31_A__SHIFT 0x0 +#define VPMPC_OUT0_CSC_C31_C32_A__VPMPC_OCSC_C32_A__SHIFT 0x10 +#define VPMPC_OUT0_CSC_C31_C32_A__VPMPC_OCSC_C31_A_MASK 0x0000FFFFL +#define VPMPC_OUT0_CSC_C31_C32_A__VPMPC_OCSC_C32_A_MASK 0xFFFF0000L +//VPMPC_OUT0_CSC_C33_C34_A +#define VPMPC_OUT0_CSC_C33_C34_A__VPMPC_OCSC_C33_A__SHIFT 0x0 +#define VPMPC_OUT0_CSC_C33_C34_A__VPMPC_OCSC_C34_A__SHIFT 0x10 +#define VPMPC_OUT0_CSC_C33_C34_A__VPMPC_OCSC_C33_A_MASK 0x0000FFFFL +#define VPMPC_OUT0_CSC_C33_C34_A__VPMPC_OCSC_C34_A_MASK 0xFFFF0000L +//VPMPC_OCSC_TEST_DEBUG_INDEX +#define VPMPC_OCSC_TEST_DEBUG_INDEX__VPMPC_OCSC_TEST_DEBUG_INDEX__SHIFT 0x0 +#define VPMPC_OCSC_TEST_DEBUG_INDEX__VPMPC_OCSC_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define VPMPC_OCSC_TEST_DEBUG_INDEX__VPMPC_OCSC_TEST_DEBUG_INDEX_MASK 0x000000FFL +#define VPMPC_OCSC_TEST_DEBUG_INDEX__VPMPC_OCSC_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +//VPMPC_OCSC_TEST_DEBUG_DATA +#define VPMPC_OCSC_TEST_DEBUG_DATA__VPMPC_OCSC_TEST_DEBUG_DATA__SHIFT 0x0 +#define VPMPC_OCSC_TEST_DEBUG_DATA__VPMPC_OCSC_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: vpe_vpep_vpopp_vpfmt0_dispdec +//VPFMT_CLAMP_COMPONENT_R +#define VPFMT_CLAMP_COMPONENT_R__VPFMT_CLAMP_LOWER_R__SHIFT 0x0 +#define VPFMT_CLAMP_COMPONENT_R__VPFMT_CLAMP_UPPER_R__SHIFT 0x10 +#define VPFMT_CLAMP_COMPONENT_R__VPFMT_CLAMP_LOWER_R_MASK 0x0000FFFFL +#define VPFMT_CLAMP_COMPONENT_R__VPFMT_CLAMP_UPPER_R_MASK 0xFFFF0000L +//VPFMT_CLAMP_COMPONENT_G +#define VPFMT_CLAMP_COMPONENT_G__VPFMT_CLAMP_LOWER_G__SHIFT 0x0 +#define VPFMT_CLAMP_COMPONENT_G__VPFMT_CLAMP_UPPER_G__SHIFT 0x10 +#define VPFMT_CLAMP_COMPONENT_G__VPFMT_CLAMP_LOWER_G_MASK 0x0000FFFFL +#define VPFMT_CLAMP_COMPONENT_G__VPFMT_CLAMP_UPPER_G_MASK 0xFFFF0000L +//VPFMT_CLAMP_COMPONENT_B +#define VPFMT_CLAMP_COMPONENT_B__VPFMT_CLAMP_LOWER_B__SHIFT 0x0 +#define VPFMT_CLAMP_COMPONENT_B__VPFMT_CLAMP_UPPER_B__SHIFT 0x10 +#define VPFMT_CLAMP_COMPONENT_B__VPFMT_CLAMP_LOWER_B_MASK 0x0000FFFFL +#define VPFMT_CLAMP_COMPONENT_B__VPFMT_CLAMP_UPPER_B_MASK 0xFFFF0000L +//VPFMT_DYNAMIC_EXP_CNTL +#define VPFMT_DYNAMIC_EXP_CNTL__VPFMT_DYNAMIC_EXP_EN__SHIFT 0x0 +#define VPFMT_DYNAMIC_EXP_CNTL__VPFMT_DYNAMIC_EXP_MODE__SHIFT 0x4 +#define VPFMT_DYNAMIC_EXP_CNTL__VPFMT_DYNAMIC_EXP_EN_MASK 0x00000001L +#define VPFMT_DYNAMIC_EXP_CNTL__VPFMT_DYNAMIC_EXP_MODE_MASK 0x00000010L +//VPFMT_CONTROL +#define VPFMT_CONTROL__VPFMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT 0x8 +#define VPFMT_CONTROL__VPFMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT 0xc +#define VPFMT_CONTROL__VPFMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT 0x15 +#define VPFMT_CONTROL__VPFMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x18 +#define VPFMT_CONTROL__VPFMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK 0x00000F00L +#define VPFMT_CONTROL__VPFMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK 0x00003000L +#define VPFMT_CONTROL__VPFMT_CBCR_BIT_REDUCTION_BYPASS_MASK 0x00200000L +#define VPFMT_CONTROL__VPFMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000L +//VPFMT_BIT_DEPTH_CONTROL +#define VPFMT_BIT_DEPTH_CONTROL__VPFMT_TRUNCATE_EN__SHIFT 0x0 +#define VPFMT_BIT_DEPTH_CONTROL__VPFMT_TRUNCATE_MODE__SHIFT 0x1 +#define VPFMT_BIT_DEPTH_CONTROL__VPFMT_TRUNCATE_DEPTH__SHIFT 0x4 +#define VPFMT_BIT_DEPTH_CONTROL__VPFMT_SPATIAL_DITHER_EN__SHIFT 0x8 +#define VPFMT_BIT_DEPTH_CONTROL__VPFMT_SPATIAL_DITHER_MODE__SHIFT 0x9 +#define VPFMT_BIT_DEPTH_CONTROL__VPFMT_SPATIAL_DITHER_DEPTH__SHIFT 0xb +#define VPFMT_BIT_DEPTH_CONTROL__VPFMT_FRAME_RANDOM_ENABLE__SHIFT 0xd +#define VPFMT_BIT_DEPTH_CONTROL__VPFMT_RGB_RANDOM_ENABLE__SHIFT 0xe +#define VPFMT_BIT_DEPTH_CONTROL__VPFMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0xf +#define VPFMT_BIT_DEPTH_CONTROL__VPFMT_TRUNCATE_EN_MASK 0x00000001L +#define VPFMT_BIT_DEPTH_CONTROL__VPFMT_TRUNCATE_MODE_MASK 0x00000002L +#define VPFMT_BIT_DEPTH_CONTROL__VPFMT_TRUNCATE_DEPTH_MASK 0x00000030L +#define VPFMT_BIT_DEPTH_CONTROL__VPFMT_SPATIAL_DITHER_EN_MASK 0x00000100L +#define VPFMT_BIT_DEPTH_CONTROL__VPFMT_SPATIAL_DITHER_MODE_MASK 0x00000600L +#define VPFMT_BIT_DEPTH_CONTROL__VPFMT_SPATIAL_DITHER_DEPTH_MASK 0x00001800L +#define VPFMT_BIT_DEPTH_CONTROL__VPFMT_FRAME_RANDOM_ENABLE_MASK 0x00002000L +#define VPFMT_BIT_DEPTH_CONTROL__VPFMT_RGB_RANDOM_ENABLE_MASK 0x00004000L +#define VPFMT_BIT_DEPTH_CONTROL__VPFMT_HIGHPASS_RANDOM_ENABLE_MASK 0x00008000L +//VPFMT_DITHER_RAND_R_SEED +#define VPFMT_DITHER_RAND_R_SEED__VPFMT_RAND_R_SEED__SHIFT 0x0 +#define VPFMT_DITHER_RAND_R_SEED__VPFMT_OFFSET_R_CR__SHIFT 0x10 +#define VPFMT_DITHER_RAND_R_SEED__VPFMT_RAND_R_SEED_MASK 0x000000FFL +#define VPFMT_DITHER_RAND_R_SEED__VPFMT_OFFSET_R_CR_MASK 0xFFFF0000L +//VPFMT_DITHER_RAND_G_SEED +#define VPFMT_DITHER_RAND_G_SEED__VPFMT_RAND_G_SEED__SHIFT 0x0 +#define VPFMT_DITHER_RAND_G_SEED__VPFMT_OFFSET_G_Y__SHIFT 0x10 +#define VPFMT_DITHER_RAND_G_SEED__VPFMT_RAND_G_SEED_MASK 0x000000FFL +#define VPFMT_DITHER_RAND_G_SEED__VPFMT_OFFSET_G_Y_MASK 0xFFFF0000L +//VPFMT_DITHER_RAND_B_SEED +#define VPFMT_DITHER_RAND_B_SEED__VPFMT_RAND_B_SEED__SHIFT 0x0 +#define VPFMT_DITHER_RAND_B_SEED__VPFMT_OFFSET_B_CB__SHIFT 0x10 +#define VPFMT_DITHER_RAND_B_SEED__VPFMT_RAND_B_SEED_MASK 0x000000FFL +#define VPFMT_DITHER_RAND_B_SEED__VPFMT_OFFSET_B_CB_MASK 0xFFFF0000L +//VPFMT_CLAMP_CNTL +#define VPFMT_CLAMP_CNTL__VPFMT_CLAMP_DATA_EN__SHIFT 0x0 +#define VPFMT_CLAMP_CNTL__VPFMT_CLAMP_COLOR_FORMAT__SHIFT 0x10 +#define VPFMT_CLAMP_CNTL__VPFMT_CLAMP_DATA_EN_MASK 0x00000001L +#define VPFMT_CLAMP_CNTL__VPFMT_CLAMP_COLOR_FORMAT_MASK 0x00070000L +//VPFMT_DEBUG_CNTL +#define VPFMT_DEBUG_CNTL__VPFMT_DEBUG_COLOR_SELECT__SHIFT 0x0 +#define VPFMT_DEBUG_CNTL__VPFMT_DEBUG_COLOR_SELECT_MASK 0x00000003L +//VPFMT_TEST_DEBUG_INDEX +#define VPFMT_TEST_DEBUG_INDEX__VPFMT_TEST_DEBUG_INDEX__SHIFT 0x0 +#define VPFMT_TEST_DEBUG_INDEX__VPFMT_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define VPFMT_TEST_DEBUG_INDEX__VPFMT_TEST_DEBUG_INDEX_MASK 0x000000FFL +#define VPFMT_TEST_DEBUG_INDEX__VPFMT_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +//VPFMT_TEST_DEBUG_DATA +#define VPFMT_TEST_DEBUG_DATA__VPFMT_TEST_DEBUG_DATA__SHIFT 0x0 +#define VPFMT_TEST_DEBUG_DATA__VPFMT_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: vpe_vpep_vpopp_vpopp_pipe0_dispdec +//VPOPP_PIPE_CONTROL +#define VPOPP_PIPE_CONTROL__VPOPP_PIPE_CLOCK_ON__SHIFT 0x1 +#define VPOPP_PIPE_CONTROL__VPOPP_PIPE_DIGITAL_BYPASS_EN__SHIFT 0x4 +#define VPOPP_PIPE_CONTROL__VPOPP_PIPE_ALPHA__SHIFT 0x10 +#define VPOPP_PIPE_CONTROL__VPOPP_PIPE_CLOCK_ON_MASK 0x00000002L +#define VPOPP_PIPE_CONTROL__VPOPP_PIPE_DIGITAL_BYPASS_EN_MASK 0x00000010L +#define VPOPP_PIPE_CONTROL__VPOPP_PIPE_ALPHA_MASK 0xFFFF0000L +//VPOPP_PIPE_SPARE_DEBUG +#define VPOPP_PIPE_SPARE_DEBUG__VPOPP_PIPE_SPARE_DEBUG__SHIFT 0x0 +#define VPOPP_PIPE_SPARE_DEBUG__VPOPP_PIPE_SPARE_DEBUG_MASK 0xFFFFFFFFL +//VPOPP_PIPE_TEST_DEBUG_INDEX +#define VPOPP_PIPE_TEST_DEBUG_INDEX__VPOPP_PIPE_TEST_DEBUG_INDEX__SHIFT 0x0 +#define VPOPP_PIPE_TEST_DEBUG_INDEX__VPOPP_PIPE_TEST_DEBUG_INDEX_MASK 0x000000FFL +//VPOPP_PIPE_TEST_DEBUG_DATA +#define VPOPP_PIPE_TEST_DEBUG_DATA__VPOPP_PIPE_TEST_DEBUG_DATA__SHIFT 0x0 +#define VPOPP_PIPE_TEST_DEBUG_DATA__VPOPP_PIPE_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: vpe_vpep_vpopp_vpopp_pipe_crc0_dispdec +//VPOPP_PIPE_CRC_CONTROL +#define VPOPP_PIPE_CRC_CONTROL__VPOPP_PIPE_CRC_EN__SHIFT 0x0 +#define VPOPP_PIPE_CRC_CONTROL__VPOPP_PIPE_CRC_CONT_EN__SHIFT 0x4 +#define VPOPP_PIPE_CRC_CONTROL__VPOPP_PIPE_CRC_PIXEL_SELECT__SHIFT 0x14 +#define VPOPP_PIPE_CRC_CONTROL__VPOPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT 0x1c +#define VPOPP_PIPE_CRC_CONTROL__VPOPP_PIPE_CRC_EN_MASK 0x00000001L +#define VPOPP_PIPE_CRC_CONTROL__VPOPP_PIPE_CRC_CONT_EN_MASK 0x00000010L +#define VPOPP_PIPE_CRC_CONTROL__VPOPP_PIPE_CRC_PIXEL_SELECT_MASK 0x00300000L +#define VPOPP_PIPE_CRC_CONTROL__VPOPP_PIPE_CRC_ONE_SHOT_PENDING_MASK 0x10000000L +//VPOPP_PIPE_CRC_MASK +#define VPOPP_PIPE_CRC_MASK__VPOPP_PIPE_CRC_MASK__SHIFT 0x0 +#define VPOPP_PIPE_CRC_MASK__VPOPP_PIPE_CRC_MASK_MASK 0x0000FFFFL +//VPOPP_PIPE_CRC_RESULT0 +#define VPOPP_PIPE_CRC_RESULT0__VPOPP_PIPE_CRC_RESULT_A__SHIFT 0x0 +#define VPOPP_PIPE_CRC_RESULT0__VPOPP_PIPE_CRC_RESULT_R__SHIFT 0x10 +#define VPOPP_PIPE_CRC_RESULT0__VPOPP_PIPE_CRC_RESULT_A_MASK 0x0000FFFFL +#define VPOPP_PIPE_CRC_RESULT0__VPOPP_PIPE_CRC_RESULT_R_MASK 0xFFFF0000L +//VPOPP_PIPE_CRC_RESULT1 +#define VPOPP_PIPE_CRC_RESULT1__VPOPP_PIPE_CRC_RESULT_G__SHIFT 0x0 +#define VPOPP_PIPE_CRC_RESULT1__VPOPP_PIPE_CRC_RESULT_B__SHIFT 0x10 +#define VPOPP_PIPE_CRC_RESULT1__VPOPP_PIPE_CRC_RESULT_G_MASK 0x0000FFFFL +#define VPOPP_PIPE_CRC_RESULT1__VPOPP_PIPE_CRC_RESULT_B_MASK 0xFFFF0000L +//VPOPP_PIPE_CRC_RESULT2 +#define VPOPP_PIPE_CRC_RESULT2__VPOPP_PIPE_CRC_RESULT_C__SHIFT 0x0 +#define VPOPP_PIPE_CRC_RESULT2__VPOPP_PIPE_CRC_RESULT_C_MASK 0x0000FFFFL + + +// addressBlock: vpe_vpep_vpopp_vpopp_top_dispdec +//VPOPP_TOP_CLK_CONTROL +#define VPOPP_TOP_CLK_CONTROL__VPOPP_VPECLK_R_GATE_DIS__SHIFT 0x0 +#define VPOPP_TOP_CLK_CONTROL__VPOPP_VPECLK_G_GATE_DIS__SHIFT 0x1 +#define VPOPP_TOP_CLK_CONTROL__VPOPP_VPECLK_R_GATE_DIS_MASK 0x00000001L +#define VPOPP_TOP_CLK_CONTROL__VPOPP_VPECLK_G_GATE_DIS_MASK 0x00000002L +//VPOPP_DEBUG_CONTROL +#define VPOPP_DEBUG_CONTROL__VPOPP_DBG_EN__SHIFT 0x0 +#define VPOPP_DEBUG_CONTROL__VPOPP_VPFMT_DEBUG_BUS_SELECT__SHIFT 0x4 +#define VPOPP_DEBUG_CONTROL__VPOPP_VPOPP_PIPE_DEBUG_BUS_SELECT__SHIFT 0x10 +#define VPOPP_DEBUG_CONTROL__VPOPP_DBG_EN_MASK 0x00000001L +#define VPOPP_DEBUG_CONTROL__VPOPP_VPFMT_DEBUG_BUS_SELECT_MASK 0x000000F0L +#define VPOPP_DEBUG_CONTROL__VPOPP_VPOPP_PIPE_DEBUG_BUS_SELECT_MASK 0x00070000L +//VPOPP_TOP_SPARE_DEBUG +#define VPOPP_TOP_SPARE_DEBUG__VPOPP_TOP_SPARE_DEBUG__SHIFT 0x0 +#define VPOPP_TOP_SPARE_DEBUG__VPOPP_TOP_SPARE_DEBUG_MASK 0xFFFFFFFFL +//VPOPP_TOP_TEST_DEBUG_INDEX +#define VPOPP_TOP_TEST_DEBUG_INDEX__VPOPP_TOP_TEST_DEBUG_INDEX__SHIFT 0x0 +#define VPOPP_TOP_TEST_DEBUG_INDEX__VPOPP_TOP_TEST_DEBUG_INDEX_MASK 0x000000FFL +//VPOPP_TOP_TEST_DEBUG_DATA +#define VPOPP_TOP_TEST_DEBUG_DATA__VPOPP_TOP_TEST_DEBUG_DATA__SHIFT 0x0 +#define VPOPP_TOP_TEST_DEBUG_DATA__VPOPP_TOP_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: vpe_vpep_vpcdc_cdc_dispdec +//VPEP_MGCG_CNTL +#define VPEP_MGCG_CNTL__VPDPP0_CLK_GATE_DIS__SHIFT 0x0 +#define VPEP_MGCG_CNTL__VPMPC_CLK_GATE_DIS__SHIFT 0xc +#define VPEP_MGCG_CNTL__VPOPP_CLK_GATE_DIS__SHIFT 0x12 +#define VPEP_MGCG_CNTL__VPCDC_SOCCLK_G_GATE_DIS__SHIFT 0x14 +#define VPEP_MGCG_CNTL__VPCDC_SOCCLK_R_GATE_DIS__SHIFT 0x15 +#define VPEP_MGCG_CNTL__VPCDC_VPECLK_G_GATE_DIS__SHIFT 0x16 +#define VPEP_MGCG_CNTL__VPCDC_VPECLK_R_GATE_DIS__SHIFT 0x17 +#define VPEP_MGCG_CNTL__VPDPP0_CLK_GATE_DIS_MASK 0x00000007L +#define VPEP_MGCG_CNTL__VPMPC_CLK_GATE_DIS_MASK 0x00003000L +#define VPEP_MGCG_CNTL__VPOPP_CLK_GATE_DIS_MASK 0x000C0000L +#define VPEP_MGCG_CNTL__VPCDC_SOCCLK_G_GATE_DIS_MASK 0x00100000L +#define VPEP_MGCG_CNTL__VPCDC_SOCCLK_R_GATE_DIS_MASK 0x00200000L +#define VPEP_MGCG_CNTL__VPCDC_VPECLK_G_GATE_DIS_MASK 0x00400000L +#define VPEP_MGCG_CNTL__VPCDC_VPECLK_R_GATE_DIS_MASK 0x00800000L +//VPCDC_SOFT_RESET +#define VPCDC_SOFT_RESET__VPCDC_SOCCLK_SOFT_RESET__SHIFT 0x0 +#define VPCDC_SOFT_RESET__VPCDC_VPECLK_SOFT_RESET__SHIFT 0x1 +#define VPCDC_SOFT_RESET__VPCDC_SOCCLK_SOFT_RESET_MASK 0x00000001L +#define VPCDC_SOFT_RESET__VPCDC_VPECLK_SOFT_RESET_MASK 0x00000002L +//VPCDC_FE0_SURFACE_CONFIG +#define VPCDC_FE0_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_FE0__SHIFT 0x0 +#define VPCDC_FE0_SURFACE_CONFIG__ROTATION_ANGLE_FE0__SHIFT 0x8 +#define VPCDC_FE0_SURFACE_CONFIG__H_MIRROR_EN_FE0__SHIFT 0xa +#define VPCDC_FE0_SURFACE_CONFIG__PIX_SURFACE_LINEAR_FE0__SHIFT 0xb +#define VPCDC_FE0_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_FE0_MASK 0x0000007FL +#define VPCDC_FE0_SURFACE_CONFIG__ROTATION_ANGLE_FE0_MASK 0x00000300L +#define VPCDC_FE0_SURFACE_CONFIG__H_MIRROR_EN_FE0_MASK 0x00000400L +#define VPCDC_FE0_SURFACE_CONFIG__PIX_SURFACE_LINEAR_FE0_MASK 0x00000800L +//VPCDC_FE0_CROSSBAR_CONFIG +#define VPCDC_FE0_CROSSBAR_CONFIG__CROSSBAR_SRC_ALPHA_FE0__SHIFT 0x0 +#define VPCDC_FE0_CROSSBAR_CONFIG__CROSSBAR_SRC_Y_G_FE0__SHIFT 0x2 +#define VPCDC_FE0_CROSSBAR_CONFIG__CROSSBAR_SRC_CB_B_FE0__SHIFT 0x4 +#define VPCDC_FE0_CROSSBAR_CONFIG__CROSSBAR_SRC_CR_R_FE0__SHIFT 0x6 +#define VPCDC_FE0_CROSSBAR_CONFIG__CROSSBAR_SRC_ALPHA_FE0_MASK 0x00000003L +#define VPCDC_FE0_CROSSBAR_CONFIG__CROSSBAR_SRC_Y_G_FE0_MASK 0x0000000CL +#define VPCDC_FE0_CROSSBAR_CONFIG__CROSSBAR_SRC_CB_B_FE0_MASK 0x00000030L +#define VPCDC_FE0_CROSSBAR_CONFIG__CROSSBAR_SRC_CR_R_FE0_MASK 0x000000C0L +//VPCDC_FE0_VIEWPORT_START_CONFIG +#define VPCDC_FE0_VIEWPORT_START_CONFIG__VIEWPORT_X_START_FE0__SHIFT 0x0 +#define VPCDC_FE0_VIEWPORT_START_CONFIG__VIEWPORT_Y_START_FE0__SHIFT 0x10 +#define VPCDC_FE0_VIEWPORT_START_CONFIG__VIEWPORT_X_START_FE0_MASK 0x00003FFFL +#define VPCDC_FE0_VIEWPORT_START_CONFIG__VIEWPORT_Y_START_FE0_MASK 0x3FFF0000L +//VPCDC_FE0_VIEWPORT_DIMENSION_CONFIG +#define VPCDC_FE0_VIEWPORT_DIMENSION_CONFIG__VIEWPORT_WIDTH_FE0__SHIFT 0x0 +#define VPCDC_FE0_VIEWPORT_DIMENSION_CONFIG__VIEWPORT_HEIGHT_FE0__SHIFT 0x10 +#define VPCDC_FE0_VIEWPORT_DIMENSION_CONFIG__VIEWPORT_WIDTH_FE0_MASK 0x00003FFFL +#define VPCDC_FE0_VIEWPORT_DIMENSION_CONFIG__VIEWPORT_HEIGHT_FE0_MASK 0x3FFF0000L +//VPCDC_FE0_VIEWPORT_START_C_CONFIG +#define VPCDC_FE0_VIEWPORT_START_C_CONFIG__VIEWPORT_X_START_C_FE0__SHIFT 0x0 +#define VPCDC_FE0_VIEWPORT_START_C_CONFIG__VIEWPORT_Y_START_C_FE0__SHIFT 0x10 +#define VPCDC_FE0_VIEWPORT_START_C_CONFIG__VIEWPORT_X_START_C_FE0_MASK 0x00003FFFL +#define VPCDC_FE0_VIEWPORT_START_C_CONFIG__VIEWPORT_Y_START_C_FE0_MASK 0x3FFF0000L +//VPCDC_FE0_VIEWPORT_DIMENSION_C_CONFIG +#define VPCDC_FE0_VIEWPORT_DIMENSION_C_CONFIG__VIEWPORT_WIDTH_C_FE0__SHIFT 0x0 +#define VPCDC_FE0_VIEWPORT_DIMENSION_C_CONFIG__VIEWPORT_HEIGHT_C_FE0__SHIFT 0x10 +#define VPCDC_FE0_VIEWPORT_DIMENSION_C_CONFIG__VIEWPORT_WIDTH_C_FE0_MASK 0x00003FFFL +#define VPCDC_FE0_VIEWPORT_DIMENSION_C_CONFIG__VIEWPORT_HEIGHT_C_FE0_MASK 0x3FFF0000L +//VPCDC_BE0_P2B_CONFIG +#define VPCDC_BE0_P2B_CONFIG__VPCDC_BE0_P2B_XBAR_SEL0__SHIFT 0x0 +#define VPCDC_BE0_P2B_CONFIG__VPCDC_BE0_P2B_XBAR_SEL1__SHIFT 0x2 +#define VPCDC_BE0_P2B_CONFIG__VPCDC_BE0_P2B_XBAR_SEL2__SHIFT 0x4 +#define VPCDC_BE0_P2B_CONFIG__VPCDC_BE0_P2B_XBAR_SEL3__SHIFT 0x6 +#define VPCDC_BE0_P2B_CONFIG__VPCDC_BE0_P2B_FORMAT_SEL__SHIFT 0x8 +#define VPCDC_BE0_P2B_CONFIG__VPCDC_BE0_P2B_XBAR_SEL0_MASK 0x00000003L +#define VPCDC_BE0_P2B_CONFIG__VPCDC_BE0_P2B_XBAR_SEL1_MASK 0x0000000CL +#define VPCDC_BE0_P2B_CONFIG__VPCDC_BE0_P2B_XBAR_SEL2_MASK 0x00000030L +#define VPCDC_BE0_P2B_CONFIG__VPCDC_BE0_P2B_XBAR_SEL3_MASK 0x000000C0L +#define VPCDC_BE0_P2B_CONFIG__VPCDC_BE0_P2B_FORMAT_SEL_MASK 0x00000300L +//VPCDC_BE0_GLOBAL_SYNC_CONFIG +#define VPCDC_BE0_GLOBAL_SYNC_CONFIG__BE0_VUPDATE_OFFSET__SHIFT 0x0 +#define VPCDC_BE0_GLOBAL_SYNC_CONFIG__BE0_VUPDATE_WIDTH__SHIFT 0xa +#define VPCDC_BE0_GLOBAL_SYNC_CONFIG__BE0_VREADY_OFFSET__SHIFT 0x14 +#define VPCDC_BE0_GLOBAL_SYNC_CONFIG__BE0_VUPDATE_OFFSET_MASK 0x000003FFL +#define VPCDC_BE0_GLOBAL_SYNC_CONFIG__BE0_VUPDATE_WIDTH_MASK 0x000FFC00L +#define VPCDC_BE0_GLOBAL_SYNC_CONFIG__BE0_VREADY_OFFSET_MASK 0x3FF00000L +//VPCDC_GLOBAL_SYNC_TRIGGER +#define VPCDC_GLOBAL_SYNC_TRIGGER__VPBE_GS_TRIG__SHIFT 0x0 +#define VPCDC_GLOBAL_SYNC_TRIGGER__VPBE_GS_TRIG_MASK 0x00000003L +//VPCDC_VREADY_STATUS +#define VPCDC_VREADY_STATUS__VPFE_VR_STATUS__SHIFT 0x0 +#define VPCDC_VREADY_STATUS__VPFE_VR_STATUS_MASK 0x00000003L +//VPEP_MEM_GLOBAL_PWR_REQ_CNTL +#define VPEP_MEM_GLOBAL_PWR_REQ_CNTL__MEM_GLOBAL_PWR_REQ_DIS__SHIFT 0x0 +#define VPEP_MEM_GLOBAL_PWR_REQ_CNTL__MEM_GLOBAL_PWR_REQ_DIS_MASK 0x00000001L +//VPFE_MEM_PWR_CNTL +#define VPFE_MEM_PWR_CNTL__VPFE0_MEM_PWR_FORCE__SHIFT 0x0 +#define VPFE_MEM_PWR_CNTL__VPFE0_MEM_PWR_MODE__SHIFT 0x2 +#define VPFE_MEM_PWR_CNTL__VPFE0_MEM_PWR_STATE__SHIFT 0x4 +#define VPFE_MEM_PWR_CNTL__VPFE0_MEM_PWR_DIS__SHIFT 0x6 +#define VPFE_MEM_PWR_CNTL__VPFE0_MEM_PWR_FORCE_MASK 0x00000003L +#define VPFE_MEM_PWR_CNTL__VPFE0_MEM_PWR_MODE_MASK 0x0000000CL +#define VPFE_MEM_PWR_CNTL__VPFE0_MEM_PWR_STATE_MASK 0x00000030L +#define VPFE_MEM_PWR_CNTL__VPFE0_MEM_PWR_DIS_MASK 0x00000040L +//VPBE_MEM_PWR_CNTL +#define VPBE_MEM_PWR_CNTL__VPBE0_MEM_PWR_FORCE__SHIFT 0x0 +#define VPBE_MEM_PWR_CNTL__VPBE0_MEM_PWR_MODE__SHIFT 0x2 +#define VPBE_MEM_PWR_CNTL__VPBE0_MEM_PWR_STATE__SHIFT 0x4 +#define VPBE_MEM_PWR_CNTL__VPBE0_MEM_PWR_DIS__SHIFT 0x6 +#define VPBE_MEM_PWR_CNTL__VPBE0_MEM_PWR_FORCE_MASK 0x00000003L +#define VPBE_MEM_PWR_CNTL__VPBE0_MEM_PWR_MODE_MASK 0x0000000CL +#define VPBE_MEM_PWR_CNTL__VPBE0_MEM_PWR_STATE_MASK 0x00000030L +#define VPBE_MEM_PWR_CNTL__VPBE0_MEM_PWR_DIS_MASK 0x00000040L +//VPEP_RBBMIF_TIMEOUT +#define VPEP_RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_DELAY__SHIFT 0x0 +#define VPEP_RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_HOLD__SHIFT 0x14 +#define VPEP_RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_DELAY_MASK 0x000FFFFFL +#define VPEP_RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_HOLD_MASK 0xFFF00000L +//VPEP_RBBMIF_STATUS +#define VPEP_RBBMIF_STATUS__RBBMIF_TIMEOUT_CLIENTS_DEC__SHIFT 0x0 +#define VPEP_RBBMIF_STATUS__RBBMIF_TIMEOUT_OP__SHIFT 0x1c +#define VPEP_RBBMIF_STATUS__RBBMIF_TIMEOUT_RDWR_STATUS__SHIFT 0x1d +#define VPEP_RBBMIF_STATUS__RBBMIF_TIMEOUT_ACK__SHIFT 0x1e +#define VPEP_RBBMIF_STATUS__RBBMIF_TIMEOUT_MASK__SHIFT 0x1f +#define VPEP_RBBMIF_STATUS__RBBMIF_TIMEOUT_CLIENTS_DEC_MASK 0x0000000FL +#define VPEP_RBBMIF_STATUS__RBBMIF_TIMEOUT_OP_MASK 0x10000000L +#define VPEP_RBBMIF_STATUS__RBBMIF_TIMEOUT_RDWR_STATUS_MASK 0x20000000L +#define VPEP_RBBMIF_STATUS__RBBMIF_TIMEOUT_ACK_MASK 0x40000000L +#define VPEP_RBBMIF_STATUS__RBBMIF_TIMEOUT_MASK_MASK 0x80000000L +//VPEP_RBBMIF_TIMEOUT_DIS +#define VPEP_RBBMIF_TIMEOUT_DIS__CLIENT0_TIMEOUT_DIS__SHIFT 0x0 +#define VPEP_RBBMIF_TIMEOUT_DIS__CLIENT1_TIMEOUT_DIS__SHIFT 0x1 +#define VPEP_RBBMIF_TIMEOUT_DIS__CLIENT2_TIMEOUT_DIS__SHIFT 0x2 +#define VPEP_RBBMIF_TIMEOUT_DIS__CLIENT3_TIMEOUT_DIS__SHIFT 0x3 +#define VPEP_RBBMIF_TIMEOUT_DIS__CLIENT0_TIMEOUT_DIS_MASK 0x00000001L +#define VPEP_RBBMIF_TIMEOUT_DIS__CLIENT1_TIMEOUT_DIS_MASK 0x00000002L +#define VPEP_RBBMIF_TIMEOUT_DIS__CLIENT2_TIMEOUT_DIS_MASK 0x00000004L +#define VPEP_RBBMIF_TIMEOUT_DIS__CLIENT3_TIMEOUT_DIS_MASK 0x00000008L +//VPCDC_DEBUG_CTRL0 +#define VPCDC_DEBUG_CTRL0__VPCDC_DBG_EN__SHIFT 0x0 +#define VPCDC_DEBUG_CTRL0__VPCDC_DBGMUX_OUT_0_SEL_SOCCLK__SHIFT 0x14 +#define VPCDC_DEBUG_CTRL0__VPCDC_DBG_EN_MASK 0x00000001L +#define VPCDC_DEBUG_CTRL0__VPCDC_DBGMUX_OUT_0_SEL_SOCCLK_MASK 0x00700000L +//VPCDC_DEBUG_CTRL1 +#define VPCDC_DEBUG_CTRL1__VPCDC_DBGMUX_OUT_0_SEL_VPECLK__SHIFT 0x0 +#define VPCDC_DEBUG_CTRL1__VPCDC_DBGMUX_OUT_1_SEL_VPECLK__SHIFT 0x8 +#define VPCDC_DEBUG_CTRL1__VPCDC_DBGMUX_OUT_2_SEL_VPECLK__SHIFT 0x10 +#define VPCDC_DEBUG_CTRL1__VPCDC_DBGMUX_OUT_3_SEL_VPECLK__SHIFT 0x18 +#define VPCDC_DEBUG_CTRL1__VPCDC_DBGMUX_OUT_0_SEL_VPECLK_MASK 0x0000001FL +#define VPCDC_DEBUG_CTRL1__VPCDC_DBGMUX_OUT_1_SEL_VPECLK_MASK 0x00001F00L +#define VPCDC_DEBUG_CTRL1__VPCDC_DBGMUX_OUT_2_SEL_VPECLK_MASK 0x001F0000L +#define VPCDC_DEBUG_CTRL1__VPCDC_DBGMUX_OUT_3_SEL_VPECLK_MASK 0x1F000000L +//VPCDC_TEST_DEBUG_INDEX +#define VPCDC_TEST_DEBUG_INDEX__VPCDC_TEST_DEBUG_INDEX__SHIFT 0x0 +#define VPCDC_TEST_DEBUG_INDEX__VPCDC_TEST_DEBUG_INDEX_MASK 0x000000FFL +//VPCDC_TEST_DEBUG_DATA +#define VPCDC_TEST_DEBUG_DATA__VPCDC_TEST_DEBUG_DATA__SHIFT 0x0 +#define VPCDC_TEST_DEBUG_DATA__VPCDC_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: vpe_vpep_vpcdc_vpcdc_dcperfmon_dc_perfmon_dispdec +//PERFCOUNTER_CNTL +#define PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//PERFCOUNTER_CNTL2 +#define PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//PERFCOUNTER_STATE +#define PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//PERFMON_CNTL +#define PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//PERFMON_CNTL2 +#define PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//PERFMON_CVALUE_INT_MISC +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//PERFMON_CVALUE_LOW +#define PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//PERFMON_HI +#define PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//PERFMON_LOW +#define PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL +//PERFMON_TEST_DEBUG_INDEX +#define PERFMON_TEST_DEBUG_INDEX__PERFMON_TEST_DEBUG_INDEX__SHIFT 0x0 +#define PERFMON_TEST_DEBUG_INDEX__PERFMON_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define PERFMON_TEST_DEBUG_INDEX__PERFMON_TEST_DEBUG_INDEX_MASK 0x000000FFL +#define PERFMON_TEST_DEBUG_INDEX__PERFMON_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +//PERFMON_TEST_DEBUG_DATA +#define PERFMON_TEST_DEBUG_DATA__PERFMON_TEST_DEBUG_DATA__SHIFT 0x0 +#define PERFMON_TEST_DEBUG_DATA__PERFMON_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dc_perfmon_dc_perfmondebugind +//PERFMON_DEBUG_ID +#define PERFMON_DEBUG_ID__PERFMON_DEBUG_ID__SHIFT 0x0 +#define PERFMON_DEBUG_ID__PERFMON_DEBUG_ID_MASK 0xFFFFFFFFL +//PERFMON_DEBUG01 +#define PERFMON_DEBUG01__CLK0_PERFCOUNTER_LOW__SHIFT 0x0 +#define PERFMON_DEBUG01__CLK0_PERFCOUNTER_LOW_MASK 0xFFFFFFFFL +//PERFMON_DEBUG02 +#define PERFMON_DEBUG02__CLK0_PERFCOUNTER_HI__SHIFT 0x0 +#define PERFMON_DEBUG02__CLK0_PERFCOUNTER_EVENT__SHIFT 0x10 +#define PERFMON_DEBUG02__CLK0_PERFCOUNTER_HI_MASK 0x0000FFFFL +#define PERFMON_DEBUG02__CLK0_PERFCOUNTER_EVENT_MASK 0x001F0000L +//PERFMON_DEBUG03 +#define PERFMON_DEBUG03__CLK1_PERFCOUNTER_LOW__SHIFT 0x0 +#define PERFMON_DEBUG03__CLK1_PERFCOUNTER_LOW_MASK 0xFFFFFFFFL +//PERFMON_DEBUG04 +#define PERFMON_DEBUG04__CLK1_PERFCOUNTER_HI__SHIFT 0x0 +#define PERFMON_DEBUG04__CLK1_PERFCOUNTER_EVENT__SHIFT 0x10 +#define PERFMON_DEBUG04__CLK1_PERFCOUNTER_HI_MASK 0x0000FFFFL +#define PERFMON_DEBUG04__CLK1_PERFCOUNTER_EVENT_MASK 0x001F0000L +//PERFMON_DEBUG05 +#define PERFMON_DEBUG05__CLK2_PERFCOUNTER_LOW__SHIFT 0x0 +#define PERFMON_DEBUG05__CLK2_PERFCOUNTER_LOW_MASK 0xFFFFFFFFL +//PERFMON_DEBUG06 +#define PERFMON_DEBUG06__CLK2_PERFCOUNTER_HI__SHIFT 0x0 +#define PERFMON_DEBUG06__CLK2_PERFCOUNTER_EVENT__SHIFT 0x10 +#define PERFMON_DEBUG06__CLK2_PERFCOUNTER_HI_MASK 0x0000FFFFL +#define PERFMON_DEBUG06__CLK2_PERFCOUNTER_EVENT_MASK 0x001F0000L +//PERFMON_DEBUG07 +#define PERFMON_DEBUG07__CLK3_PERFCOUNTER_LOW__SHIFT 0x0 +#define PERFMON_DEBUG07__CLK3_PERFCOUNTER_LOW_MASK 0xFFFFFFFFL +//PERFMON_DEBUG08 +#define PERFMON_DEBUG08__CLK3_PERFCOUNTER_HI__SHIFT 0x0 +#define PERFMON_DEBUG08__CLK3_PERFCOUNTER_EVENT__SHIFT 0x10 +#define PERFMON_DEBUG08__CLK3_PERFCOUNTER_HI_MASK 0x0000FFFFL +#define PERFMON_DEBUG08__CLK3_PERFCOUNTER_EVENT_MASK 0x001F0000L +//PERFMON_DEBUG09 +#define PERFMON_DEBUG09__PERFMON_EN_EVENT_START__SHIFT 0x0 +#define PERFMON_DEBUG09__PERFMON_EN_EVENT_STOP__SHIFT 0x1 +#define PERFMON_DEBUG09__PERFMON_EN_EVENT_START_MASK 0x00000001L +#define PERFMON_DEBUG09__PERFMON_EN_EVENT_STOP_MASK 0x00000002L +//PERFMON_DEBUG0A +#define PERFMON_DEBUG0A__CLK4_PERFCOUNTER_LOW__SHIFT 0x0 +#define PERFMON_DEBUG0A__CLK4_PERFCOUNTER_LOW_MASK 0xFFFFFFFFL +//PERFMON_DEBUG0B +#define PERFMON_DEBUG0B__CLK4_PERFCOUNTER_HI__SHIFT 0x0 +#define PERFMON_DEBUG0B__CLK4_PERFCOUNTER_EVENT__SHIFT 0x10 +#define PERFMON_DEBUG0B__CLK4_PERFCOUNTER_HI_MASK 0x0000FFFFL +#define PERFMON_DEBUG0B__CLK4_PERFCOUNTER_EVENT_MASK 0x001F0000L +//PERFMON_DEBUG0C +#define PERFMON_DEBUG0C__CLK5_PERFCOUNTER_LOW__SHIFT 0x0 +#define PERFMON_DEBUG0C__CLK5_PERFCOUNTER_LOW_MASK 0xFFFFFFFFL +//PERFMON_DEBUG0D +#define PERFMON_DEBUG0D__CLK5_PERFCOUNTER_HI__SHIFT 0x0 +#define PERFMON_DEBUG0D__CLK5_PERFCOUNTER_EVENT__SHIFT 0x10 +#define PERFMON_DEBUG0D__CLK5_PERFCOUNTER_HI_MASK 0x0000FFFFL +#define PERFMON_DEBUG0D__CLK5_PERFCOUNTER_EVENT_MASK 0x001F0000L +//PERFMON_DEBUG0E +#define PERFMON_DEBUG0E__CLK6_PERFCOUNTER_LOW__SHIFT 0x0 +#define PERFMON_DEBUG0E__CLK6_PERFCOUNTER_LOW_MASK 0xFFFFFFFFL +//PERFMON_DEBUG0F +#define PERFMON_DEBUG0F__CLK6_PERFCOUNTER_HI__SHIFT 0x0 +#define PERFMON_DEBUG0F__CLK6_PERFCOUNTER_EVENT__SHIFT 0x10 +#define PERFMON_DEBUG0F__CLK6_PERFCOUNTER_HI_MASK 0x0000FFFFL +#define PERFMON_DEBUG0F__CLK6_PERFCOUNTER_EVENT_MASK 0x001F0000L +//PERFMON_DEBUG10 +#define PERFMON_DEBUG10__CLK7_PERFCOUNTER_LOW__SHIFT 0x0 +#define PERFMON_DEBUG10__CLK7_PERFCOUNTER_LOW_MASK 0xFFFFFFFFL +//PERFMON_DEBUG11 +#define PERFMON_DEBUG11__CLK7_PERFCOUNTER_HI__SHIFT 0x0 +#define PERFMON_DEBUG11__CLK7_PERFCOUNTER_EVENT__SHIFT 0x10 +#define PERFMON_DEBUG11__CLK7_PERFCOUNTER_HI_MASK 0x0000FFFFL +#define PERFMON_DEBUG11__CLK7_PERFCOUNTER_EVENT_MASK 0x001F0000L +//PERFMON_DEBUG12 +#define PERFMON_DEBUG12__CLK0_PERFCOUNTER_OFF__SHIFT 0x0 +#define PERFMON_DEBUG12__CLK1_PERFCOUNTER_OFF__SHIFT 0x1 +#define PERFMON_DEBUG12__CLK2_PERFCOUNTER_OFF__SHIFT 0x2 +#define PERFMON_DEBUG12__CLK3_PERFCOUNTER_OFF__SHIFT 0x3 +#define PERFMON_DEBUG12__CLK4_PERFCOUNTER_OFF__SHIFT 0x4 +#define PERFMON_DEBUG12__CLK5_PERFCOUNTER_OFF__SHIFT 0x5 +#define PERFMON_DEBUG12__CLK6_PERFCOUNTER_OFF__SHIFT 0x6 +#define PERFMON_DEBUG12__CLK7_PERFCOUNTER_OFF__SHIFT 0x7 +#define PERFMON_DEBUG12__PERFCOUNTER_OFF__SHIFT 0x8 +#define PERFMON_DEBUG12__CLK0_PERFCOUNTER_OFF_MASK 0x00000001L +#define PERFMON_DEBUG12__CLK1_PERFCOUNTER_OFF_MASK 0x00000002L +#define PERFMON_DEBUG12__CLK2_PERFCOUNTER_OFF_MASK 0x00000004L +#define PERFMON_DEBUG12__CLK3_PERFCOUNTER_OFF_MASK 0x00000008L +#define PERFMON_DEBUG12__CLK4_PERFCOUNTER_OFF_MASK 0x00000010L +#define PERFMON_DEBUG12__CLK5_PERFCOUNTER_OFF_MASK 0x00000020L +#define PERFMON_DEBUG12__CLK6_PERFCOUNTER_OFF_MASK 0x00000040L +#define PERFMON_DEBUG12__CLK7_PERFCOUNTER_OFF_MASK 0x00000080L +#define PERFMON_DEBUG12__PERFCOUNTER_OFF_MASK 0x00000100L + + +// addressBlock: vpfmt0_vpfmtdebugind +//VPFMT_DEBUG_ID +#define VPFMT_DEBUG_ID__VPFMT_DEBUG_ID__SHIFT 0x0 +#define VPFMT_DEBUG_ID__VPFMT_DEBUG_ID_MASK 0xFFFFFFFFL +//VPFMT_DEBUG0 +#define VPFMT_DEBUG0__VPFMT_DEBUG0__SHIFT 0x0 +#define VPFMT_DEBUG0__VPFMT_DEBUG0_MASK 0xFFFFFFFFL +//VPFMT_DEBUG1 +#define VPFMT_DEBUG1__VPFMT_DEBUG1__SHIFT 0x0 +#define VPFMT_DEBUG1__VPFMT_DEBUG1_MASK 0xFFFFFFFFL +//VPFMT_DEBUG2 +#define VPFMT_DEBUG2__VPFMT_DEBUG2__SHIFT 0x0 +#define VPFMT_DEBUG2__VPFMT_DEBUG2_MASK 0xFFFFFFFFL +//VPFMT_DEBUG3 +#define VPFMT_DEBUG3__VPFMT_DEBUG3__SHIFT 0x0 +#define VPFMT_DEBUG3__VPFMT_DEBUG3_MASK 0xFFFFFFFFL +//VPFMT_DEBUG4 +#define VPFMT_DEBUG4__VPFMT_DEBUG4__SHIFT 0x0 +#define VPFMT_DEBUG4__VPFMT_DEBUG4_MASK 0xFFFFFFFFL +//VPFMT_DEBUG5 +#define VPFMT_DEBUG5__VPFMT_DEBUG5__SHIFT 0x0 +#define VPFMT_DEBUG5__VPFMT_DEBUG5_MASK 0xFFFFFFFFL +//VPFMT_DEBUG6 +#define VPFMT_DEBUG6__VPFMT_DEBUG6__SHIFT 0x0 +#define VPFMT_DEBUG6__VPFMT_DEBUG6_MASK 0xFFFFFFFFL +//VPFMT_DEBUG7 +#define VPFMT_DEBUG7__VPFMT_DEBUG7__SHIFT 0x0 +#define VPFMT_DEBUG7__VPFMT_DEBUG7_MASK 0xFFFFFFFFL +//VPFMT_DEBUG8 +#define VPFMT_DEBUG8__VPFMT_DEBUG8__SHIFT 0x0 +#define VPFMT_DEBUG8__VPFMT_DEBUG8_MASK 0xFFFFFFFFL +//VPFMT_DEBUG9 +#define VPFMT_DEBUG9__VPFMT_DEBUG9__SHIFT 0x0 +#define VPFMT_DEBUG9__VPFMT_DEBUG9_MASK 0xFFFFFFFFL +//VPFMT_DEBUG10 +#define VPFMT_DEBUG10__VPFMT_DEBUG10__SHIFT 0x0 +#define VPFMT_DEBUG10__VPFMT_DEBUG10_MASK 0xFFFFFFFFL +//VPFMT_DEBUG11 +#define VPFMT_DEBUG11__VPFMT_DEBUG11__SHIFT 0x0 +#define VPFMT_DEBUG11__VPFMT_DEBUG11_MASK 0xFFFFFFFFL + + +// addressBlock: vpopp_pipe0_vpopppipedebugind +//VPOPP_PIPE_DEBUG_ID +#define VPOPP_PIPE_DEBUG_ID__VPOPP_PIPE_DEBUG_ID__SHIFT 0x0 +#define VPOPP_PIPE_DEBUG_ID__VPOPP_PIPE_DEBUG_ID_MASK 0xFFFFFFFFL +//VPOPP_PIPE_DEBUG_0 +#define VPOPP_PIPE_DEBUG_0__VPOPP_PIPE_DEBUG_0__SHIFT 0x0 +#define VPOPP_PIPE_DEBUG_0__VPOPP_PIPE_DEBUG_0_MASK 0xFFFFFFFFL +//VPOPP_PIPE_DEBUG_1 +#define VPOPP_PIPE_DEBUG_1__VPOPP_PIPE_DEBUG_1__SHIFT 0x0 +#define VPOPP_PIPE_DEBUG_1__VPOPP_PIPE_DEBUG_1_MASK 0xFFFFFFFFL +//VPOPP_PIPE_DEBUG_2 +#define VPOPP_PIPE_DEBUG_2__VPOPP_PIPE_DEBUG_2__SHIFT 0x0 +#define VPOPP_PIPE_DEBUG_2__VPOPP_PIPE_DEBUG_2_MASK 0xFFFFFFFFL + + +// addressBlock: vpopp_top_vpopp_topdebugind +//VPOPP_TOP_DEBUG_ID +#define VPOPP_TOP_DEBUG_ID__VPOPP_TOP_DEBUG_ID__SHIFT 0x0 +#define VPOPP_TOP_DEBUG_ID__VPOPP_TOP_DEBUG_ID_MASK 0xFFFFFFFFL + +#endif diff --git a/src/amd/vpelib/src/chip/vpe10/inc/asic/vpe_1_0_offset.h b/src/amd/vpelib/src/chip/vpe10/inc/asic/vpe_1_0_offset.h new file mode 100644 index 00000000000..153bbe464e6 --- /dev/null +++ b/src/amd/vpelib/src/chip/vpe10/inc/asic/vpe_1_0_offset.h @@ -0,0 +1,111 @@ +#ifndef VPE_1_0_OFFSET_H +#define VPE_1_0_OFFSET_H + + +#define MAX_INSTANCE 9 +#define MAX_SEGMENT 7 + + +struct IP_BASE_INSTANCE +{ + unsigned int segment[MAX_SEGMENT]; +}; + +struct IP_BASE +{ + struct IP_BASE_INSTANCE instance[MAX_INSTANCE]; +}; + + +struct IP_SIZE +{ + unsigned int segment[1][MAX_SEGMENT]; +}; + + +static const struct IP_BASE VPE_BASE = { { { { 0x00011800, 0x02456C00, 0x3C56C000, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_SIZE VPE_SIZE = { { { 0x00001400, 0x00000400, 0x00004000, 0, 0, 0, 0 } } }; + + + +#define VPE_BASE__INST0_SEG0 0x00011800 +#define VPE_BASE__INST0_SEG1 0x02456C00 +#define VPE_BASE__INST0_SEG2 0x3C56C000 +#define VPE_BASE__INST0_SEG3 0 +#define VPE_BASE__INST0_SEG4 0 +#define VPE_BASE__INST0_SEG5 0 +#define VPE_BASE__INST0_SEG6 0 + +#define VPE_BASE__INST1_SEG0 0 +#define VPE_BASE__INST1_SEG1 0 +#define VPE_BASE__INST1_SEG2 0 +#define VPE_BASE__INST1_SEG3 0 +#define VPE_BASE__INST1_SEG4 0 +#define VPE_BASE__INST1_SEG5 0 +#define VPE_BASE__INST1_SEG6 0 + +#define VPE_BASE__INST2_SEG0 0 +#define VPE_BASE__INST2_SEG1 0 +#define VPE_BASE__INST2_SEG2 0 +#define VPE_BASE__INST2_SEG3 0 +#define VPE_BASE__INST2_SEG4 0 +#define VPE_BASE__INST2_SEG5 0 +#define VPE_BASE__INST2_SEG6 0 + +#define VPE_BASE__INST3_SEG0 0 +#define VPE_BASE__INST3_SEG1 0 +#define VPE_BASE__INST3_SEG2 0 +#define VPE_BASE__INST3_SEG3 0 +#define VPE_BASE__INST3_SEG4 0 +#define VPE_BASE__INST3_SEG5 0 +#define VPE_BASE__INST3_SEG6 0 + +#define VPE_BASE__INST4_SEG0 0 +#define VPE_BASE__INST4_SEG1 0 +#define VPE_BASE__INST4_SEG2 0 +#define VPE_BASE__INST4_SEG3 0 +#define VPE_BASE__INST4_SEG4 0 +#define VPE_BASE__INST4_SEG5 0 +#define VPE_BASE__INST4_SEG6 0 + +#define VPE_BASE__INST5_SEG0 0 +#define VPE_BASE__INST5_SEG1 0 +#define VPE_BASE__INST5_SEG2 0 +#define VPE_BASE__INST5_SEG3 0 +#define VPE_BASE__INST5_SEG4 0 +#define VPE_BASE__INST5_SEG5 0 +#define VPE_BASE__INST5_SEG6 0 + +#define VPE_BASE__INST6_SEG0 0 +#define VPE_BASE__INST6_SEG1 0 +#define VPE_BASE__INST6_SEG2 0 +#define VPE_BASE__INST6_SEG3 0 +#define VPE_BASE__INST6_SEG4 0 +#define VPE_BASE__INST6_SEG5 0 +#define VPE_BASE__INST6_SEG6 0 + +#define VPE_BASE__INST7_SEG0 0 +#define VPE_BASE__INST7_SEG1 0 +#define VPE_BASE__INST7_SEG2 0 +#define VPE_BASE__INST7_SEG3 0 +#define VPE_BASE__INST7_SEG4 0 +#define VPE_BASE__INST7_SEG5 0 +#define VPE_BASE__INST7_SEG6 0 + +#define VPE_BASE__INST8_SEG0 0 +#define VPE_BASE__INST8_SEG1 0 +#define VPE_BASE__INST8_SEG2 0 +#define VPE_BASE__INST8_SEG3 0 +#define VPE_BASE__INST8_SEG4 0 +#define VPE_BASE__INST8_SEG5 0 +#define VPE_BASE__INST8_SEG6 0 + +#endif diff --git a/src/amd/vpelib/src/chip/vpe10/inc/vpe10_background.h b/src/amd/vpelib/src/chip/vpe10/inc/vpe10_background.h new file mode 100644 index 00000000000..4454936e524 --- /dev/null +++ b/src/amd/vpelib/src/chip/vpe10/inc/vpe10_background.h @@ -0,0 +1,37 @@ +/* Copyright 2023 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ +#pragma once + +#include "resource.h" + +#ifdef __cplusplus +extern "C" { +#endif + +bool vpe10_split_bg_gap(struct vpe_rect *gaps, const struct vpe_rect *target_rect, + uint32_t max_width, uint16_t max_gaps, uint16_t *num_gaps, uint16_t num_multiple); + +#ifdef __cplusplus +} +#endif diff --git a/src/amd/vpelib/src/chip/vpe10/inc/vpe10_cdc.h b/src/amd/vpelib/src/chip/vpe10/inc/vpe10_cdc.h new file mode 100644 index 00000000000..710c5e93235 --- /dev/null +++ b/src/amd/vpelib/src/chip/vpe10/inc/vpe10_cdc.h @@ -0,0 +1,201 @@ +/* Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ +#pragma once + +#include "cdc.h" +#include "reg_helper.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define VPE10_CDC_VUPDATE_OFFSET_DEFAULT (21) +#define VPE10_CDC_VUPDATE_WIDTH_DEFAULT (60) +#define VPE10_CDC_VREADY_OFFSET_DEFAULT (150) + +/* macros for filing variable or field list + SRI, SFRB should be defined in the resource file */ +#define CDC_REG_LIST_VPE10(id) \ + SRIDFVL(VPEP_MGCG_CNTL, CDC, id), SRIDFVL(VPCDC_SOFT_RESET, CDC, id), \ + SRIDFVL(VPCDC_FE0_SURFACE_CONFIG, CDC, id), SRIDFVL(VPCDC_FE0_CROSSBAR_CONFIG, CDC, id), \ + SRIDFVL(VPCDC_FE0_VIEWPORT_START_CONFIG, CDC, id), \ + SRIDFVL(VPCDC_FE0_VIEWPORT_DIMENSION_CONFIG, CDC, id), \ + SRIDFVL(VPCDC_FE0_VIEWPORT_START_C_CONFIG, CDC, id), \ + SRIDFVL(VPCDC_FE0_VIEWPORT_DIMENSION_C_CONFIG, CDC, id), \ + SRIDFVL(VPCDC_BE0_P2B_CONFIG, CDC, id), SRIDFVL(VPCDC_BE0_GLOBAL_SYNC_CONFIG, CDC, id), \ + SRIDFVL(VPCDC_GLOBAL_SYNC_TRIGGER, CDC, id), \ + SRIDFVL(VPEP_MEM_GLOBAL_PWR_REQ_CNTL, CDC, id), SRIDFVL(VPFE_MEM_PWR_CNTL, CDC, id), \ + SRIDFVL(VPBE_MEM_PWR_CNTL, CDC, id) + +#define CDC_FLIED_LIST_VPE10(post_fix) \ + SFRB(VPDPP0_CLK_GATE_DIS, VPEP_MGCG_CNTL, post_fix), \ + SFRB(VPMPC_CLK_GATE_DIS, VPEP_MGCG_CNTL, post_fix), \ + SFRB(VPOPP_CLK_GATE_DIS, VPEP_MGCG_CNTL, post_fix), \ + SFRB(VPCDC_SOCCLK_G_GATE_DIS, VPEP_MGCG_CNTL, post_fix), \ + SFRB(VPCDC_SOCCLK_R_GATE_DIS, VPEP_MGCG_CNTL, post_fix), \ + SFRB(VPCDC_VPECLK_G_GATE_DIS, VPEP_MGCG_CNTL, post_fix), \ + SFRB(VPCDC_VPECLK_R_GATE_DIS, VPEP_MGCG_CNTL, post_fix), \ + SFRB(VPCDC_SOCCLK_SOFT_RESET, VPCDC_SOFT_RESET, post_fix), \ + SFRB(VPCDC_VPECLK_SOFT_RESET, VPCDC_SOFT_RESET, post_fix), \ + SFRB(SURFACE_PIXEL_FORMAT_FE0, VPCDC_FE0_SURFACE_CONFIG, post_fix), \ + SFRB(ROTATION_ANGLE_FE0, VPCDC_FE0_SURFACE_CONFIG, post_fix), \ + SFRB(H_MIRROR_EN_FE0, VPCDC_FE0_SURFACE_CONFIG, post_fix), \ + SFRB(PIX_SURFACE_LINEAR_FE0, VPCDC_FE0_SURFACE_CONFIG, post_fix), \ + SFRB(CROSSBAR_SRC_ALPHA_FE0, VPCDC_FE0_CROSSBAR_CONFIG, post_fix), \ + SFRB(CROSSBAR_SRC_Y_G_FE0, VPCDC_FE0_CROSSBAR_CONFIG, post_fix), \ + SFRB(CROSSBAR_SRC_CB_B_FE0, VPCDC_FE0_CROSSBAR_CONFIG, post_fix), \ + SFRB(CROSSBAR_SRC_CR_R_FE0, VPCDC_FE0_CROSSBAR_CONFIG, post_fix), \ + SFRB(VIEWPORT_X_START_FE0, VPCDC_FE0_VIEWPORT_START_CONFIG, post_fix), \ + SFRB(VIEWPORT_Y_START_FE0, VPCDC_FE0_VIEWPORT_START_CONFIG, post_fix), \ + SFRB(VIEWPORT_WIDTH_FE0, VPCDC_FE0_VIEWPORT_DIMENSION_CONFIG, post_fix), \ + SFRB(VIEWPORT_HEIGHT_FE0, VPCDC_FE0_VIEWPORT_DIMENSION_CONFIG, post_fix), \ + SFRB(VIEWPORT_X_START_C_FE0, VPCDC_FE0_VIEWPORT_START_C_CONFIG, post_fix), \ + SFRB(VIEWPORT_Y_START_C_FE0, VPCDC_FE0_VIEWPORT_START_C_CONFIG, post_fix), \ + SFRB(VIEWPORT_WIDTH_C_FE0, VPCDC_FE0_VIEWPORT_DIMENSION_C_CONFIG, post_fix), \ + SFRB(VIEWPORT_HEIGHT_C_FE0, VPCDC_FE0_VIEWPORT_DIMENSION_C_CONFIG, post_fix), \ + SFRB(VPCDC_BE0_P2B_XBAR_SEL0, VPCDC_BE0_P2B_CONFIG, post_fix), \ + SFRB(VPCDC_BE0_P2B_XBAR_SEL1, VPCDC_BE0_P2B_CONFIG, post_fix), \ + SFRB(VPCDC_BE0_P2B_XBAR_SEL2, VPCDC_BE0_P2B_CONFIG, post_fix), \ + SFRB(VPCDC_BE0_P2B_XBAR_SEL3, VPCDC_BE0_P2B_CONFIG, post_fix), \ + SFRB(VPCDC_BE0_P2B_FORMAT_SEL, VPCDC_BE0_P2B_CONFIG, post_fix), \ + SFRB(BE0_VUPDATE_OFFSET, VPCDC_BE0_GLOBAL_SYNC_CONFIG, post_fix), \ + SFRB(BE0_VUPDATE_WIDTH, VPCDC_BE0_GLOBAL_SYNC_CONFIG, post_fix), \ + SFRB(BE0_VREADY_OFFSET, VPCDC_BE0_GLOBAL_SYNC_CONFIG, post_fix), \ + SFRB(VPBE_GS_TRIG, VPCDC_GLOBAL_SYNC_TRIGGER, post_fix), \ + SFRB(VPFE_VR_STATUS, VPCDC_VREADY_STATUS, post_fix), \ + SFRB(MEM_GLOBAL_PWR_REQ_DIS, VPEP_MEM_GLOBAL_PWR_REQ_CNTL, post_fix), \ + SFRB(VPFE0_MEM_PWR_FORCE, VPFE_MEM_PWR_CNTL, post_fix), \ + SFRB(VPFE0_MEM_PWR_MODE, VPFE_MEM_PWR_CNTL, post_fix), \ + SFRB(VPFE0_MEM_PWR_STATE, VPFE_MEM_PWR_CNTL, post_fix), \ + SFRB(VPFE0_MEM_PWR_DIS, VPFE_MEM_PWR_CNTL, post_fix), \ + SFRB(VPBE0_MEM_PWR_FORCE, VPBE_MEM_PWR_CNTL, post_fix), \ + SFRB(VPBE0_MEM_PWR_MODE, VPBE_MEM_PWR_CNTL, post_fix), \ + SFRB(VPBE0_MEM_PWR_STATE, VPBE_MEM_PWR_CNTL, post_fix), \ + SFRB(VPBE0_MEM_PWR_DIS, VPBE_MEM_PWR_CNTL, post_fix) + +/* define all structure register variables below */ +#define CDC_REG_VARIABLE_LIST_VPE10 \ + reg_id_val VPEP_MGCG_CNTL; \ + reg_id_val VPCDC_SOFT_RESET; \ + reg_id_val VPCDC_FE0_SURFACE_CONFIG; \ + reg_id_val VPCDC_FE0_CROSSBAR_CONFIG; \ + reg_id_val VPCDC_FE0_VIEWPORT_START_CONFIG; \ + reg_id_val VPCDC_FE0_VIEWPORT_DIMENSION_CONFIG; \ + reg_id_val VPCDC_FE0_VIEWPORT_START_C_CONFIG; \ + reg_id_val VPCDC_FE0_VIEWPORT_DIMENSION_C_CONFIG; \ + reg_id_val VPCDC_BE0_P2B_CONFIG; \ + reg_id_val VPCDC_BE0_GLOBAL_SYNC_CONFIG; \ + reg_id_val VPCDC_GLOBAL_SYNC_TRIGGER; \ + reg_id_val VPEP_MEM_GLOBAL_PWR_REQ_CNTL; \ + reg_id_val VPFE_MEM_PWR_CNTL; \ + reg_id_val VPBE_MEM_PWR_CNTL; + +#define CDC_FIELD_VARIABLE_LIST_VPE10(type) \ + type VPDPP0_CLK_GATE_DIS; \ + type VPMPC_CLK_GATE_DIS; \ + type VPOPP_CLK_GATE_DIS; \ + type VPCDC_SOCCLK_G_GATE_DIS; \ + type VPCDC_SOCCLK_R_GATE_DIS; \ + type VPCDC_VPECLK_G_GATE_DIS; \ + type VPCDC_VPECLK_R_GATE_DIS; \ + type VPCDC_SOCCLK_SOFT_RESET; \ + type VPCDC_VPECLK_SOFT_RESET; \ + type SURFACE_PIXEL_FORMAT_FE0; \ + type ROTATION_ANGLE_FE0; \ + type H_MIRROR_EN_FE0; \ + type PIX_SURFACE_LINEAR_FE0; \ + type CROSSBAR_SRC_ALPHA_FE0; \ + type CROSSBAR_SRC_Y_G_FE0; \ + type CROSSBAR_SRC_CB_B_FE0; \ + type CROSSBAR_SRC_CR_R_FE0; \ + type VIEWPORT_X_START_FE0; \ + type VIEWPORT_Y_START_FE0; \ + type VIEWPORT_WIDTH_FE0; \ + type VIEWPORT_HEIGHT_FE0; \ + type VIEWPORT_X_START_C_FE0; \ + type VIEWPORT_Y_START_C_FE0; \ + type VIEWPORT_WIDTH_C_FE0; \ + type VIEWPORT_HEIGHT_C_FE0; \ + type VPCDC_BE0_P2B_XBAR_SEL0; \ + type VPCDC_BE0_P2B_XBAR_SEL1; \ + type VPCDC_BE0_P2B_XBAR_SEL2; \ + type VPCDC_BE0_P2B_XBAR_SEL3; \ + type VPCDC_BE0_P2B_FORMAT_SEL; \ + type BE0_VUPDATE_OFFSET; \ + type BE0_VUPDATE_WIDTH; \ + type BE0_VREADY_OFFSET; \ + type VPBE_GS_TRIG; \ + type VPFE_VR_STATUS; \ + type MEM_GLOBAL_PWR_REQ_DIS; \ + type VPFE0_MEM_PWR_FORCE; \ + type VPFE0_MEM_PWR_MODE; \ + type VPFE0_MEM_PWR_STATE; \ + type VPFE0_MEM_PWR_DIS; \ + type VPBE0_MEM_PWR_FORCE; \ + type VPBE0_MEM_PWR_MODE; \ + type VPBE0_MEM_PWR_STATE; \ + type VPBE0_MEM_PWR_DIS; + +struct vpe10_cdc_registers { + CDC_REG_VARIABLE_LIST_VPE10 +}; + +struct vpe10_cdc_shift { + CDC_FIELD_VARIABLE_LIST_VPE10(uint8_t) +}; + +struct vpe10_cdc_mask { + CDC_FIELD_VARIABLE_LIST_VPE10(uint32_t) +}; + +struct vpe10_cdc { + struct cdc base; // base class, must be the first field + struct vpe10_cdc_registers *regs; + const struct vpe10_cdc_shift *shift; + const struct vpe10_cdc_mask *mask; +}; + +void vpe10_construct_cdc(struct vpe_priv *vpe_priv, struct cdc *cdc); + +bool vpe10_cdc_check_input_format(struct cdc *cdc, enum vpe_surface_pixel_format format); + +bool vpe10_cdc_check_output_format(struct cdc *cdc, enum vpe_surface_pixel_format format); + +void vpe10_cdc_program_surface_config(struct cdc *cdc, enum vpe_surface_pixel_format format, + enum vpe_rotation_angle rotation, bool horizontal_mirror, enum vpe_swizzle_mode_values swizzle); + +void vpe10_cdc_program_crossbar_config(struct cdc *cdc, enum vpe_surface_pixel_format format); + +void vpe10_cdc_program_global_sync( + struct cdc *cdc, uint32_t vupdate_offset, uint32_t vupdate_width, uint32_t vready_offset); + +void vpe10_cdc_program_p2b_config(struct cdc *cdc, enum vpe_surface_pixel_format format); + +/***** segment register programming *****/ +void vpe10_cdc_program_viewport( + struct cdc *cdc, const struct vpe_rect *viewport, const struct vpe_rect *viewport_c); + +#ifdef __cplusplus +} +#endif diff --git a/src/amd/vpelib/src/chip/vpe10/inc/vpe10_cm_common.h b/src/amd/vpelib/src/chip/vpe10/inc/vpe10_cm_common.h new file mode 100644 index 00000000000..85773d2f12e --- /dev/null +++ b/src/amd/vpelib/src/chip/vpe10/inc/vpe10_cm_common.h @@ -0,0 +1,135 @@ +/* Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ +#pragma once + +#include "color.h" +#include "hw_shared.h" +#include "color_pwl.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct config_writer; + +#define TF_HELPER_REG_FIELD_LIST(type) \ + type exp_region0_lut_offset; \ + type exp_region0_num_segments; \ + type exp_region1_lut_offset; \ + type exp_region1_num_segments; \ + type field_region_end; \ + type field_region_end_slope; \ + type field_region_end_base; \ + type exp_region_start; \ + type exp_region_start_segment; \ + type field_region_linear_slope; \ + type field_region_start_base; \ + type field_offset + +#define TF_HELPER_REG_LIST \ + uint32_t start_cntl_b; \ + uint32_t start_cntl_g; \ + uint32_t start_cntl_r; \ + uint32_t start_slope_cntl_b; \ + uint32_t start_slope_cntl_g; \ + uint32_t start_slope_cntl_r; \ + uint32_t start_end_cntl1_b; \ + uint32_t start_end_cntl2_b; \ + uint32_t start_end_cntl1_g; \ + uint32_t start_end_cntl2_g; \ + uint32_t start_end_cntl1_r; \ + uint32_t start_end_cntl2_r; \ + uint32_t region_start; \ + uint32_t region_end + +struct vpe10_xfer_func_shift { + TF_HELPER_REG_FIELD_LIST(uint8_t); +}; + +struct vpe10_xfer_func_mask { + TF_HELPER_REG_FIELD_LIST(uint32_t); +}; + +struct vpe10_xfer_func_reg { + struct vpe10_xfer_func_shift shifts; + struct vpe10_xfer_func_mask masks; + + TF_HELPER_REG_LIST; + uint32_t offset_b; + uint32_t offset_g; + uint32_t offset_r; + uint32_t start_base_cntl_b; + uint32_t start_base_cntl_g; + uint32_t start_base_cntl_r; +}; + +#define TF_CM_REG_FIELD_LIST(type) \ + type csc_c11; \ + type csc_c12 + +struct cm_color_matrix_shift { + TF_CM_REG_FIELD_LIST(uint8_t); +}; + +struct cm_color_matrix_mask { + TF_CM_REG_FIELD_LIST(uint32_t); +}; + +struct color_matrices_reg { + struct cm_color_matrix_shift shifts; + struct cm_color_matrix_mask masks; + + uint32_t csc_c11_c12; + uint32_t csc_c33_c34; +}; + +enum cm_rgb_channel { + CM_PWL_R, + CM_PWL_G, + CM_PWL_B +}; + +void vpe10_cm_helper_program_pwl(struct config_writer *config_writer, + const struct pwl_result_data *rgb, uint32_t last_base_value, uint32_t num, + uint32_t lut_data_reg_offset, uint8_t lut_data_reg_shift, uint32_t lut_data_reg_mask, + enum cm_rgb_channel channel); + +void vpe10_cm_helper_program_color_matrices(struct config_writer *config_writer, + const uint16_t *regval, const struct color_matrices_reg *reg); + +void vpe10_cm_helper_program_gamcor_xfer_func(struct config_writer *config_writer, + const struct pwl_params *params, const struct vpe10_xfer_func_reg *reg); + +bool vpe10_cm_helper_translate_curve_to_hw_format( + const struct transfer_func *output_tf, struct pwl_params *lut_params, bool fixpoint); + +bool vpe10_cm_helper_translate_curve_to_degamma_hw_format( + const struct transfer_func *output_tf, struct pwl_params *lut_params); + +void vpe10_cm_get_tf_pwl_params(const struct transfer_func *output_tf, + struct pwl_params **lut_params, enum cm_type vpe_cm_type); + +#ifdef __cplusplus +} +#endif diff --git a/src/amd/vpelib/src/chip/vpe10/inc/vpe10_cmd_builder.h b/src/amd/vpelib/src/chip/vpe10/inc/vpe10_cmd_builder.h new file mode 100644 index 00000000000..6445eba29e7 --- /dev/null +++ b/src/amd/vpelib/src/chip/vpe10/inc/vpe10_cmd_builder.h @@ -0,0 +1,44 @@ +/* Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ +#pragma once + +#include "cmd_builder.h" + +#ifdef __cplusplus +extern "C" { +#endif + +void vpe10_construct_cmd_builder(struct vpe_priv *vpe_priv, struct cmd_builder *cmd_builder); + +enum vpe_status vpe10_build_noops(struct vpe_priv *vpe_priv, uint32_t **ppbuf, uint32_t num_dwords); + +enum vpe_status vpe10_build_vpe_cmd( + struct vpe_priv *vpe_priv, struct vpe_build_bufs *cur_bufs, uint32_t cmd_idx); + +enum vpe_status vpe10_build_plane_descriptor( + struct vpe_priv *vpe_priv, struct vpe_buf *buf, uint32_t cmd_idx); + +#ifdef __cplusplus +} +#endif diff --git a/src/amd/vpelib/src/chip/vpe10/inc/vpe10_dpp.h b/src/amd/vpelib/src/chip/vpe10/inc/vpe10_dpp.h new file mode 100644 index 00000000000..72db58e8e98 --- /dev/null +++ b/src/amd/vpelib/src/chip/vpe10/inc/vpe10_dpp.h @@ -0,0 +1,887 @@ +/* Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ +#pragma once + +#include "dpp.h" +#include "transform.h" +#include "reg_helper.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// Used to resolve corner case +#define DPP_SFRB(field_name, reg_name, post_fix) .field_name = reg_name##_##field_name##post_fix + +#define DPP_REG_LIST_VPE10(id) \ + SRIDFVL(VPCNVC_SURFACE_PIXEL_FORMAT, VPCNVC_CFG, id), \ + SRIDFVL(VPCNVC_FORMAT_CONTROL, VPCNVC_CFG, id), \ + SRIDFVL(VPCNVC_FCNV_FP_BIAS_R, VPCNVC_CFG, id), \ + SRIDFVL(VPCNVC_FCNV_FP_BIAS_G, VPCNVC_CFG, id), \ + SRIDFVL(VPCNVC_FCNV_FP_BIAS_B, VPCNVC_CFG, id), \ + SRIDFVL(VPCNVC_FCNV_FP_SCALE_R, VPCNVC_CFG, id), \ + SRIDFVL(VPCNVC_FCNV_FP_SCALE_G, VPCNVC_CFG, id), \ + SRIDFVL(VPCNVC_FCNV_FP_SCALE_B, VPCNVC_CFG, id), \ + SRIDFVL(VPCNVC_COLOR_KEYER_CONTROL, VPCNVC_CFG, id), \ + SRIDFVL(VPCNVC_COLOR_KEYER_ALPHA, VPCNVC_CFG, id), \ + SRIDFVL(VPCNVC_COLOR_KEYER_RED, VPCNVC_CFG, id), \ + SRIDFVL(VPCNVC_COLOR_KEYER_GREEN, VPCNVC_CFG, id), \ + SRIDFVL(VPCNVC_COLOR_KEYER_BLUE, VPCNVC_CFG, id), \ + SRIDFVL(VPCNVC_ALPHA_2BIT_LUT, VPCNVC_CFG, id), \ + SRIDFVL(VPCNVC_PRE_DEALPHA, VPCNVC_CFG, id), SRIDFVL(VPCNVC_PRE_CSC_MODE, VPCNVC_CFG, id), \ + SRIDFVL(VPCNVC_PRE_CSC_C11_C12, VPCNVC_CFG, id), \ + SRIDFVL(VPCNVC_PRE_CSC_C13_C14, VPCNVC_CFG, id), \ + SRIDFVL(VPCNVC_PRE_CSC_C21_C22, VPCNVC_CFG, id), \ + SRIDFVL(VPCNVC_PRE_CSC_C23_C24, VPCNVC_CFG, id), \ + SRIDFVL(VPCNVC_PRE_CSC_C31_C32, VPCNVC_CFG, id), \ + SRIDFVL(VPCNVC_PRE_CSC_C33_C34, VPCNVC_CFG, id), \ + SRIDFVL(VPCNVC_COEF_FORMAT, VPCNVC_CFG, id), SRIDFVL(VPCNVC_PRE_DEGAM, VPCNVC_CFG, id), \ + SRIDFVL(VPCNVC_PRE_REALPHA, VPCNVC_CFG, id), \ + SRIDFVL(VPDSCL_COEF_RAM_TAP_SELECT, VPDSCL, id), \ + SRIDFVL(VPDSCL_COEF_RAM_TAP_DATA, VPDSCL, id), SRIDFVL(VPDSCL_MODE, VPDSCL, id), \ + SRIDFVL(VPDSCL_TAP_CONTROL, VPDSCL, id), SRIDFVL(VPDSCL_CONTROL, VPDSCL, id), \ + SRIDFVL(VPDSCL_2TAP_CONTROL, VPDSCL, id), \ + SRIDFVL(VPDSCL_MANUAL_REPLICATE_CONTROL, VPDSCL, id), \ + SRIDFVL(VPDSCL_HORZ_FILTER_SCALE_RATIO, VPDSCL, id), \ + SRIDFVL(VPDSCL_HORZ_FILTER_INIT, VPDSCL, id), \ + SRIDFVL(VPDSCL_HORZ_FILTER_SCALE_RATIO_C, VPDSCL, id), \ + SRIDFVL(VPDSCL_HORZ_FILTER_INIT_C, VPDSCL, id), \ + SRIDFVL(VPDSCL_VERT_FILTER_SCALE_RATIO, VPDSCL, id), \ + SRIDFVL(VPDSCL_VERT_FILTER_INIT, VPDSCL, id), \ + SRIDFVL(VPDSCL_VERT_FILTER_SCALE_RATIO_C, VPDSCL, id), \ + SRIDFVL(VPDSCL_VERT_FILTER_INIT_C, VPDSCL, id), SRIDFVL(VPDSCL_BLACK_COLOR, VPDSCL, id), \ + SRIDFVL(VPDSCL_UPDATE, VPDSCL, id), SRIDFVL(VPDSCL_AUTOCAL, VPDSCL, id), \ + SRIDFVL(VPDSCL_EXT_OVERSCAN_LEFT_RIGHT, VPDSCL, id), \ + SRIDFVL(VPDSCL_EXT_OVERSCAN_TOP_BOTTOM, VPDSCL, id), SRIDFVL(VPOTG_H_BLANK, VPDSCL, id), \ + SRIDFVL(VPOTG_V_BLANK, VPDSCL, id), SRIDFVL(VPDSCL_RECOUT_START, VPDSCL, id), \ + SRIDFVL(VPDSCL_RECOUT_SIZE, VPDSCL, id), SRIDFVL(VPMPC_SIZE, VPDSCL, id), \ + SRIDFVL(VPLB_DATA_FORMAT, VPDSCL, id), SRIDFVL(VPLB_MEMORY_CTRL, VPDSCL, id), \ + SRIDFVL(VPLB_V_COUNTER, VPDSCL, id), SRIDFVL(VPDSCL_MEM_PWR_CTRL, VPDSCL, id), \ + SRIDFVL(VPDSCL_MEM_PWR_STATUS, VPDSCL, id), SRIDFVL(VPCM_CONTROL, VPCM, id), \ + SRIDFVL(VPCM_POST_CSC_CONTROL, VPCM, id), SRIDFVL(VPCM_POST_CSC_C11_C12, VPCM, id), \ + SRIDFVL(VPCM_POST_CSC_C13_C14, VPCM, id), SRIDFVL(VPCM_POST_CSC_C21_C22, VPCM, id), \ + SRIDFVL(VPCM_POST_CSC_C23_C24, VPCM, id), SRIDFVL(VPCM_POST_CSC_C31_C32, VPCM, id), \ + SRIDFVL(VPCM_POST_CSC_C33_C34, VPCM, id), SRIDFVL(VPCM_GAMUT_REMAP_CONTROL, VPCM, id), \ + SRIDFVL(VPCM_GAMUT_REMAP_C11_C12, VPCM, id), SRIDFVL(VPCM_GAMUT_REMAP_C13_C14, VPCM, id), \ + SRIDFVL(VPCM_GAMUT_REMAP_C21_C22, VPCM, id), SRIDFVL(VPCM_GAMUT_REMAP_C23_C24, VPCM, id), \ + SRIDFVL(VPCM_GAMUT_REMAP_C31_C32, VPCM, id), SRIDFVL(VPCM_GAMUT_REMAP_C33_C34, VPCM, id), \ + SRIDFVL(VPCM_BIAS_CR_R, VPCM, id), SRIDFVL(VPCM_BIAS_Y_G_CB_B, VPCM, id), \ + SRIDFVL(VPCM_GAMCOR_CONTROL, VPCM, id), SRIDFVL(VPCM_GAMCOR_LUT_INDEX, VPCM, id), \ + SRIDFVL(VPCM_GAMCOR_LUT_DATA, VPCM, id), SRIDFVL(VPCM_GAMCOR_LUT_CONTROL, VPCM, id), \ + SRIDFVL(VPCM_GAMCOR_RAMA_START_CNTL_B, VPCM, id), \ + SRIDFVL(VPCM_GAMCOR_RAMA_START_CNTL_G, VPCM, id), \ + SRIDFVL(VPCM_GAMCOR_RAMA_START_CNTL_R, VPCM, id), \ + SRIDFVL(VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_B, VPCM, id), \ + SRIDFVL(VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_G, VPCM, id), \ + SRIDFVL(VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_R, VPCM, id), \ + SRIDFVL(VPCM_GAMCOR_RAMA_START_BASE_CNTL_B, VPCM, id), \ + SRIDFVL(VPCM_GAMCOR_RAMA_START_BASE_CNTL_G, VPCM, id), \ + SRIDFVL(VPCM_GAMCOR_RAMA_START_BASE_CNTL_R, VPCM, id), \ + SRIDFVL(VPCM_GAMCOR_RAMA_END_CNTL1_B, VPCM, id), \ + SRIDFVL(VPCM_GAMCOR_RAMA_END_CNTL2_B, VPCM, id), \ + SRIDFVL(VPCM_GAMCOR_RAMA_END_CNTL1_G, VPCM, id), \ + SRIDFVL(VPCM_GAMCOR_RAMA_END_CNTL2_G, VPCM, id), \ + SRIDFVL(VPCM_GAMCOR_RAMA_END_CNTL1_R, VPCM, id), \ + SRIDFVL(VPCM_GAMCOR_RAMA_END_CNTL2_R, VPCM, id), \ + SRIDFVL(VPCM_GAMCOR_RAMA_OFFSET_B, VPCM, id), \ + SRIDFVL(VPCM_GAMCOR_RAMA_OFFSET_G, VPCM, id), \ + SRIDFVL(VPCM_GAMCOR_RAMA_OFFSET_R, VPCM, id), \ + SRIDFVL(VPCM_GAMCOR_RAMA_REGION_0_1, VPCM, id), \ + SRIDFVL(VPCM_GAMCOR_RAMA_REGION_2_3, VPCM, id), \ + SRIDFVL(VPCM_GAMCOR_RAMA_REGION_4_5, VPCM, id), \ + SRIDFVL(VPCM_GAMCOR_RAMA_REGION_6_7, VPCM, id), \ + SRIDFVL(VPCM_GAMCOR_RAMA_REGION_8_9, VPCM, id), \ + SRIDFVL(VPCM_GAMCOR_RAMA_REGION_10_11, VPCM, id), \ + SRIDFVL(VPCM_GAMCOR_RAMA_REGION_12_13, VPCM, id), \ + SRIDFVL(VPCM_GAMCOR_RAMA_REGION_14_15, VPCM, id), \ + SRIDFVL(VPCM_GAMCOR_RAMA_REGION_16_17, VPCM, id), \ + SRIDFVL(VPCM_GAMCOR_RAMA_REGION_18_19, VPCM, id), \ + SRIDFVL(VPCM_GAMCOR_RAMA_REGION_20_21, VPCM, id), \ + SRIDFVL(VPCM_GAMCOR_RAMA_REGION_22_23, VPCM, id), \ + SRIDFVL(VPCM_GAMCOR_RAMA_REGION_24_25, VPCM, id), \ + SRIDFVL(VPCM_GAMCOR_RAMA_REGION_26_27, VPCM, id), \ + SRIDFVL(VPCM_GAMCOR_RAMA_REGION_28_29, VPCM, id), \ + SRIDFVL(VPCM_GAMCOR_RAMA_REGION_30_31, VPCM, id), \ + SRIDFVL(VPCM_GAMCOR_RAMA_REGION_32_33, VPCM, id), SRIDFVL(VPCM_HDR_MULT_COEF, VPCM, id), \ + SRIDFVL(VPCM_MEM_PWR_CTRL, VPCM, id), SRIDFVL(VPCM_MEM_PWR_STATUS, VPCM, id), \ + SRIDFVL(VPCM_DEALPHA, VPCM, id), SRIDFVL(VPCM_COEF_FORMAT, VPCM, id), \ + SRIDFVL(VPDPP_CONTROL, VPDPP_TOP, id), SRIDFVL(VPDPP_CRC_CTRL, VPDPP_TOP, id), + +#define DPP_FIELD_LIST_VPE10(post_fix) \ + SFRB(VPCNVC_SURFACE_PIXEL_FORMAT, VPCNVC_SURFACE_PIXEL_FORMAT, post_fix), \ + SFRB(FORMAT_EXPANSION_MODE, VPCNVC_FORMAT_CONTROL, post_fix), \ + SFRB(FORMAT_CNV16, VPCNVC_FORMAT_CONTROL, post_fix), \ + DPP_SFRB(FORMAT_CONTROL__ALPHA_EN, VPCNVC, post_fix), \ + SFRB(VPCNVC_BYPASS, VPCNVC_FORMAT_CONTROL, post_fix), \ + SFRB(VPCNVC_BYPASS_MSB_ALIGN, VPCNVC_FORMAT_CONTROL, post_fix), \ + SFRB(CLAMP_POSITIVE, VPCNVC_FORMAT_CONTROL, post_fix), \ + SFRB(CLAMP_POSITIVE_C, VPCNVC_FORMAT_CONTROL, post_fix), \ + SFRB(VPCNVC_UPDATE_PENDING, VPCNVC_FORMAT_CONTROL, post_fix), \ + SFRB(FCNV_FP_BIAS_R, VPCNVC_FCNV_FP_BIAS_R, post_fix), \ + SFRB(FCNV_FP_BIAS_G, VPCNVC_FCNV_FP_BIAS_G, post_fix), \ + SFRB(FCNV_FP_BIAS_B, VPCNVC_FCNV_FP_BIAS_B, post_fix), \ + SFRB(FCNV_FP_SCALE_R, VPCNVC_FCNV_FP_SCALE_R, post_fix), \ + SFRB(FCNV_FP_SCALE_G, VPCNVC_FCNV_FP_SCALE_G, post_fix), \ + SFRB(FCNV_FP_SCALE_B, VPCNVC_FCNV_FP_SCALE_B, post_fix), \ + SFRB(COLOR_KEYER_EN, VPCNVC_COLOR_KEYER_CONTROL, post_fix), \ + SFRB(COLOR_KEYER_MODE, VPCNVC_COLOR_KEYER_CONTROL, post_fix), \ + SFRB(COLOR_KEYER_ALPHA_LOW, VPCNVC_COLOR_KEYER_ALPHA, post_fix), \ + SFRB(COLOR_KEYER_ALPHA_HIGH, VPCNVC_COLOR_KEYER_ALPHA, post_fix), \ + SFRB(COLOR_KEYER_RED_LOW, VPCNVC_COLOR_KEYER_RED, post_fix), \ + SFRB(COLOR_KEYER_RED_HIGH, VPCNVC_COLOR_KEYER_RED, post_fix), \ + SFRB(COLOR_KEYER_GREEN_LOW, VPCNVC_COLOR_KEYER_GREEN, post_fix), \ + SFRB(COLOR_KEYER_GREEN_HIGH, VPCNVC_COLOR_KEYER_GREEN, post_fix), \ + SFRB(COLOR_KEYER_BLUE_LOW, VPCNVC_COLOR_KEYER_BLUE, post_fix), \ + SFRB(COLOR_KEYER_BLUE_HIGH, VPCNVC_COLOR_KEYER_BLUE, post_fix), \ + SFRB(ALPHA_2BIT_LUT0, VPCNVC_ALPHA_2BIT_LUT, post_fix), \ + SFRB(ALPHA_2BIT_LUT1, VPCNVC_ALPHA_2BIT_LUT, post_fix), \ + SFRB(ALPHA_2BIT_LUT2, VPCNVC_ALPHA_2BIT_LUT, post_fix), \ + SFRB(ALPHA_2BIT_LUT3, VPCNVC_ALPHA_2BIT_LUT, post_fix), \ + SFRB(PRE_DEALPHA_EN, VPCNVC_PRE_DEALPHA, post_fix), \ + SFRB(PRE_DEALPHA_ABLND_EN, VPCNVC_PRE_DEALPHA, post_fix), \ + SFRB(PRE_CSC_MODE, VPCNVC_PRE_CSC_MODE, post_fix), \ + SFRB(PRE_CSC_MODE_CURRENT, VPCNVC_PRE_CSC_MODE, post_fix), \ + SFRB(PRE_CSC_C11, VPCNVC_PRE_CSC_C11_C12, post_fix), \ + SFRB(PRE_CSC_C12, VPCNVC_PRE_CSC_C11_C12, post_fix), \ + SFRB(PRE_CSC_C13, VPCNVC_PRE_CSC_C13_C14, post_fix), \ + SFRB(PRE_CSC_C14, VPCNVC_PRE_CSC_C13_C14, post_fix), \ + SFRB(PRE_CSC_C21, VPCNVC_PRE_CSC_C21_C22, post_fix), \ + SFRB(PRE_CSC_C22, VPCNVC_PRE_CSC_C21_C22, post_fix), \ + SFRB(PRE_CSC_C23, VPCNVC_PRE_CSC_C23_C24, post_fix), \ + SFRB(PRE_CSC_C24, VPCNVC_PRE_CSC_C23_C24, post_fix), \ + SFRB(PRE_CSC_C31, VPCNVC_PRE_CSC_C31_C32, post_fix), \ + SFRB(PRE_CSC_C32, VPCNVC_PRE_CSC_C31_C32, post_fix), \ + SFRB(PRE_CSC_C33, VPCNVC_PRE_CSC_C33_C34, post_fix), \ + SFRB(PRE_CSC_C34, VPCNVC_PRE_CSC_C33_C34, post_fix), \ + SFRB(PRE_CSC_COEF_FORMAT, VPCNVC_COEF_FORMAT, post_fix), \ + SFRB(PRE_DEGAM_MODE, VPCNVC_PRE_DEGAM, post_fix), \ + SFRB(PRE_DEGAM_SELECT, VPCNVC_PRE_DEGAM, post_fix), \ + SFRB(PRE_REALPHA_EN, VPCNVC_PRE_REALPHA, post_fix), \ + SFRB(PRE_REALPHA_ABLND_EN, VPCNVC_PRE_REALPHA, post_fix), \ + SFRB(SCL_COEF_RAM_TAP_PAIR_IDX, VPDSCL_COEF_RAM_TAP_SELECT, post_fix), \ + SFRB(SCL_COEF_RAM_PHASE, VPDSCL_COEF_RAM_TAP_SELECT, post_fix), \ + SFRB(SCL_COEF_RAM_FILTER_TYPE, VPDSCL_COEF_RAM_TAP_SELECT, post_fix), \ + SFRB(SCL_COEF_RAM_EVEN_TAP_COEF, VPDSCL_COEF_RAM_TAP_DATA, post_fix), \ + SFRB(SCL_COEF_RAM_EVEN_TAP_COEF_EN, VPDSCL_COEF_RAM_TAP_DATA, post_fix), \ + SFRB(SCL_COEF_RAM_ODD_TAP_COEF, VPDSCL_COEF_RAM_TAP_DATA, post_fix), \ + SFRB(SCL_COEF_RAM_ODD_TAP_COEF_EN, VPDSCL_COEF_RAM_TAP_DATA, post_fix), \ + SFRB(VPDSCL_MODE, VPDSCL_MODE, post_fix), \ + SFRB(SCL_COEF_RAM_SELECT_CURRENT, VPDSCL_MODE, post_fix), \ + SFRB(SCL_CHROMA_COEF_MODE, VPDSCL_MODE, post_fix), \ + SFRB(SCL_ALPHA_COEF_MODE, VPDSCL_MODE, post_fix), \ + SFRB(SCL_COEF_RAM_SELECT_RD, VPDSCL_MODE, post_fix), \ + SFRB(SCL_V_NUM_TAPS, VPDSCL_TAP_CONTROL, post_fix), \ + SFRB(SCL_H_NUM_TAPS, VPDSCL_TAP_CONTROL, post_fix), \ + SFRB(SCL_V_NUM_TAPS_C, VPDSCL_TAP_CONTROL, post_fix), \ + SFRB(SCL_H_NUM_TAPS_C, VPDSCL_TAP_CONTROL, post_fix), \ + SFRB(SCL_BOUNDARY_MODE, VPDSCL_CONTROL, post_fix), \ + SFRB(SCL_H_2TAP_HARDCODE_COEF_EN, VPDSCL_2TAP_CONTROL, post_fix), \ + SFRB(SCL_H_2TAP_SHARP_EN, VPDSCL_2TAP_CONTROL, post_fix), \ + SFRB(SCL_H_2TAP_SHARP_FACTOR, VPDSCL_2TAP_CONTROL, post_fix), \ + SFRB(SCL_V_2TAP_HARDCODE_COEF_EN, VPDSCL_2TAP_CONTROL, post_fix), \ + SFRB(SCL_V_2TAP_SHARP_EN, VPDSCL_2TAP_CONTROL, post_fix), \ + SFRB(SCL_V_2TAP_SHARP_FACTOR, VPDSCL_2TAP_CONTROL, post_fix), \ + SFRB(SCL_V_MANUAL_REPLICATE_FACTOR, VPDSCL_MANUAL_REPLICATE_CONTROL, post_fix), \ + SFRB(SCL_H_MANUAL_REPLICATE_FACTOR, VPDSCL_MANUAL_REPLICATE_CONTROL, post_fix), \ + SFRB(SCL_H_SCALE_RATIO, VPDSCL_HORZ_FILTER_SCALE_RATIO, post_fix), \ + SFRB(SCL_H_INIT_FRAC, VPDSCL_HORZ_FILTER_INIT, post_fix), \ + SFRB(SCL_H_INIT_INT, VPDSCL_HORZ_FILTER_INIT, post_fix), \ + SFRB(SCL_H_SCALE_RATIO_C, VPDSCL_HORZ_FILTER_SCALE_RATIO_C, post_fix), \ + SFRB(SCL_H_INIT_FRAC_C, VPDSCL_HORZ_FILTER_INIT_C, post_fix), \ + SFRB(SCL_H_INIT_INT_C, VPDSCL_HORZ_FILTER_INIT_C, post_fix), \ + SFRB(SCL_V_SCALE_RATIO, VPDSCL_VERT_FILTER_SCALE_RATIO, post_fix), \ + SFRB(SCL_V_INIT_FRAC, VPDSCL_VERT_FILTER_INIT, post_fix), \ + SFRB(SCL_V_INIT_INT, VPDSCL_VERT_FILTER_INIT, post_fix), \ + SFRB(SCL_V_SCALE_RATIO_C, VPDSCL_VERT_FILTER_SCALE_RATIO_C, post_fix), \ + SFRB(SCL_V_INIT_FRAC_C, VPDSCL_VERT_FILTER_INIT_C, post_fix), \ + SFRB(SCL_V_INIT_INT_C, VPDSCL_VERT_FILTER_INIT_C, post_fix), \ + SFRB(SCL_BLACK_COLOR_RGB_Y, VPDSCL_BLACK_COLOR, post_fix), \ + SFRB(SCL_BLACK_COLOR_CBCR, VPDSCL_BLACK_COLOR, post_fix), \ + SFRB(SCL_UPDATE_PENDING, VPDSCL_UPDATE, post_fix), \ + SFRB(AUTOCAL_MODE, VPDSCL_AUTOCAL, post_fix), \ + SFRB(EXT_OVERSCAN_RIGHT, VPDSCL_EXT_OVERSCAN_LEFT_RIGHT, post_fix), \ + SFRB(EXT_OVERSCAN_LEFT, VPDSCL_EXT_OVERSCAN_LEFT_RIGHT, post_fix), \ + SFRB(EXT_OVERSCAN_BOTTOM, VPDSCL_EXT_OVERSCAN_TOP_BOTTOM, post_fix), \ + SFRB(EXT_OVERSCAN_TOP, VPDSCL_EXT_OVERSCAN_TOP_BOTTOM, post_fix), \ + SFRB(OTG_H_BLANK_START, VPOTG_H_BLANK, post_fix), \ + SFRB(OTG_H_BLANK_END, VPOTG_H_BLANK, post_fix), \ + SFRB(OTG_V_BLANK_START, VPOTG_V_BLANK, post_fix), \ + SFRB(OTG_V_BLANK_END, VPOTG_V_BLANK, post_fix), \ + SFRB(RECOUT_START_X, VPDSCL_RECOUT_START, post_fix), \ + SFRB(RECOUT_START_Y, VPDSCL_RECOUT_START, post_fix), \ + SFRB(RECOUT_WIDTH, VPDSCL_RECOUT_SIZE, post_fix), \ + SFRB(RECOUT_HEIGHT, VPDSCL_RECOUT_SIZE, post_fix), \ + SFRB(VPMPC_WIDTH, VPMPC_SIZE, post_fix), SFRB(VPMPC_HEIGHT, VPMPC_SIZE, post_fix), \ + SFRB(ALPHA_EN, VPLB_DATA_FORMAT, post_fix), \ + SFRB(MEMORY_CONFIG, VPLB_MEMORY_CTRL, post_fix), \ + SFRB(LB_MAX_PARTITIONS, VPLB_MEMORY_CTRL, post_fix), \ + SFRB(LB_NUM_PARTITIONS, VPLB_MEMORY_CTRL, post_fix), \ + SFRB(LB_NUM_PARTITIONS_C, VPLB_MEMORY_CTRL, post_fix), \ + SFRB(V_COUNTER, VPLB_V_COUNTER, post_fix), SFRB(V_COUNTER_C, VPLB_V_COUNTER, post_fix), \ + SFRB(LUT_MEM_PWR_FORCE, VPDSCL_MEM_PWR_CTRL, post_fix), \ + SFRB(LUT_MEM_PWR_DIS, VPDSCL_MEM_PWR_CTRL, post_fix), \ + SFRB(LB_G1_MEM_PWR_FORCE, VPDSCL_MEM_PWR_CTRL, post_fix), \ + SFRB(LB_G1_MEM_PWR_DIS, VPDSCL_MEM_PWR_CTRL, post_fix), \ + SFRB(LB_G2_MEM_PWR_FORCE, VPDSCL_MEM_PWR_CTRL, post_fix), \ + SFRB(LB_G2_MEM_PWR_DIS, VPDSCL_MEM_PWR_CTRL, post_fix), \ + SFRB(LB_MEM_PWR_MODE, VPDSCL_MEM_PWR_CTRL, post_fix), \ + SFRB(LUT_MEM_PWR_STATE, VPDSCL_MEM_PWR_STATUS, post_fix), \ + SFRB(LB_G1_MEM_PWR_STATE, VPDSCL_MEM_PWR_STATUS, post_fix), \ + SFRB(LB_G2_MEM_PWR_STATE, VPDSCL_MEM_PWR_STATUS, post_fix), \ + SFRB(VPCM_BYPASS, VPCM_CONTROL, post_fix), \ + SFRB(VPCM_UPDATE_PENDING, VPCM_CONTROL, post_fix), \ + SFRB(VPCM_POST_CSC_MODE, VPCM_POST_CSC_CONTROL, post_fix), \ + SFRB(VPCM_POST_CSC_MODE_CURRENT, VPCM_POST_CSC_CONTROL, post_fix), \ + SFRB(VPCM_POST_CSC_C11, VPCM_POST_CSC_C11_C12, post_fix), \ + SFRB(VPCM_POST_CSC_C12, VPCM_POST_CSC_C11_C12, post_fix), \ + SFRB(VPCM_POST_CSC_C13, VPCM_POST_CSC_C13_C14, post_fix), \ + SFRB(VPCM_POST_CSC_C14, VPCM_POST_CSC_C13_C14, post_fix), \ + SFRB(VPCM_POST_CSC_C21, VPCM_POST_CSC_C21_C22, post_fix), \ + SFRB(VPCM_POST_CSC_C22, VPCM_POST_CSC_C21_C22, post_fix), \ + SFRB(VPCM_POST_CSC_C23, VPCM_POST_CSC_C23_C24, post_fix), \ + SFRB(VPCM_POST_CSC_C24, VPCM_POST_CSC_C23_C24, post_fix), \ + SFRB(VPCM_POST_CSC_C31, VPCM_POST_CSC_C31_C32, post_fix), \ + SFRB(VPCM_POST_CSC_C32, VPCM_POST_CSC_C31_C32, post_fix), \ + SFRB(VPCM_POST_CSC_C33, VPCM_POST_CSC_C33_C34, post_fix), \ + SFRB(VPCM_POST_CSC_C34, VPCM_POST_CSC_C33_C34, post_fix), \ + SFRB(VPCM_GAMUT_REMAP_MODE, VPCM_GAMUT_REMAP_CONTROL, post_fix), \ + SFRB(VPCM_GAMUT_REMAP_MODE_CURRENT, VPCM_GAMUT_REMAP_CONTROL, post_fix), \ + SFRB(VPCM_GAMUT_REMAP_C11, VPCM_GAMUT_REMAP_C11_C12, post_fix), \ + SFRB(VPCM_GAMUT_REMAP_C12, VPCM_GAMUT_REMAP_C11_C12, post_fix), \ + SFRB(VPCM_GAMUT_REMAP_C13, VPCM_GAMUT_REMAP_C13_C14, post_fix), \ + SFRB(VPCM_GAMUT_REMAP_C14, VPCM_GAMUT_REMAP_C13_C14, post_fix), \ + SFRB(VPCM_GAMUT_REMAP_C21, VPCM_GAMUT_REMAP_C21_C22, post_fix), \ + SFRB(VPCM_GAMUT_REMAP_C22, VPCM_GAMUT_REMAP_C21_C22, post_fix), \ + SFRB(VPCM_GAMUT_REMAP_C23, VPCM_GAMUT_REMAP_C23_C24, post_fix), \ + SFRB(VPCM_GAMUT_REMAP_C24, VPCM_GAMUT_REMAP_C23_C24, post_fix), \ + SFRB(VPCM_GAMUT_REMAP_C31, VPCM_GAMUT_REMAP_C31_C32, post_fix), \ + SFRB(VPCM_GAMUT_REMAP_C32, VPCM_GAMUT_REMAP_C31_C32, post_fix), \ + SFRB(VPCM_GAMUT_REMAP_C33, VPCM_GAMUT_REMAP_C33_C34, post_fix), \ + SFRB(VPCM_GAMUT_REMAP_C34, VPCM_GAMUT_REMAP_C33_C34, post_fix), \ + SFRB(VPCM_BIAS_CR_R, VPCM_BIAS_CR_R, post_fix), \ + SFRB(VPCM_BIAS_Y_G, VPCM_BIAS_Y_G_CB_B, post_fix), \ + SFRB(VPCM_BIAS_CB_B, VPCM_BIAS_Y_G_CB_B, post_fix), \ + SFRB(VPCM_GAMCOR_MODE, VPCM_GAMCOR_CONTROL, post_fix), \ + SFRB(VPCM_GAMCOR_PWL_DISABLE, VPCM_GAMCOR_CONTROL, post_fix), \ + SFRB(VPCM_GAMCOR_MODE_CURRENT, VPCM_GAMCOR_CONTROL, post_fix), \ + SFRB(VPCM_GAMCOR_SELECT_CURRENT, VPCM_GAMCOR_CONTROL, post_fix), \ + SFRB(VPCM_GAMCOR_LUT_INDEX, VPCM_GAMCOR_LUT_INDEX, post_fix), \ + SFRB(VPCM_GAMCOR_LUT_DATA, VPCM_GAMCOR_LUT_DATA, post_fix), \ + SFRB(VPCM_GAMCOR_LUT_WRITE_COLOR_MASK, VPCM_GAMCOR_LUT_CONTROL, post_fix), \ + SFRB(VPCM_GAMCOR_LUT_READ_COLOR_SEL, VPCM_GAMCOR_LUT_CONTROL, post_fix), \ + SFRB(VPCM_GAMCOR_LUT_READ_DBG, VPCM_GAMCOR_LUT_CONTROL, post_fix), \ + SFRB(VPCM_GAMCOR_LUT_HOST_SEL, VPCM_GAMCOR_LUT_CONTROL, post_fix), \ + SFRB(VPCM_GAMCOR_LUT_CONFIG_MODE, VPCM_GAMCOR_LUT_CONTROL, post_fix), \ + SFRB(VPCM_GAMCOR_RAMA_EXP_REGION_START_B, VPCM_GAMCOR_RAMA_START_CNTL_B, post_fix), \ + SFRB( \ + VPCM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B, VPCM_GAMCOR_RAMA_START_CNTL_B, post_fix), \ + SFRB(VPCM_GAMCOR_RAMA_EXP_REGION_START_G, VPCM_GAMCOR_RAMA_START_CNTL_G, post_fix), \ + SFRB( \ + VPCM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G, VPCM_GAMCOR_RAMA_START_CNTL_G, post_fix), \ + SFRB(VPCM_GAMCOR_RAMA_EXP_REGION_START_R, VPCM_GAMCOR_RAMA_START_CNTL_R, post_fix), \ + SFRB( \ + VPCM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R, VPCM_GAMCOR_RAMA_START_CNTL_R, post_fix), \ + SFRB(VPCM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B, VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_B, \ + post_fix), \ + SFRB(VPCM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G, VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_G, \ + post_fix), \ + SFRB(VPCM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R, VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_R, \ + post_fix), \ + SFRB(VPCM_GAMCOR_RAMA_EXP_REGION_START_BASE_B, VPCM_GAMCOR_RAMA_START_BASE_CNTL_B, \ + post_fix), \ + SFRB(VPCM_GAMCOR_RAMA_EXP_REGION_START_BASE_G, VPCM_GAMCOR_RAMA_START_BASE_CNTL_G, \ + post_fix), \ + SFRB(VPCM_GAMCOR_RAMA_EXP_REGION_START_BASE_R, VPCM_GAMCOR_RAMA_START_BASE_CNTL_R, \ + post_fix), \ + SFRB(VPCM_GAMCOR_RAMA_EXP_REGION_END_BASE_B, VPCM_GAMCOR_RAMA_END_CNTL1_B, post_fix), \ + SFRB(VPCM_GAMCOR_RAMA_EXP_REGION_END_B, VPCM_GAMCOR_RAMA_END_CNTL2_B, post_fix), \ + SFRB(VPCM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B, VPCM_GAMCOR_RAMA_END_CNTL2_B, post_fix), \ + SFRB(VPCM_GAMCOR_RAMA_EXP_REGION_END_BASE_G, VPCM_GAMCOR_RAMA_END_CNTL1_G, post_fix), \ + SFRB(VPCM_GAMCOR_RAMA_EXP_REGION_END_G, VPCM_GAMCOR_RAMA_END_CNTL2_G, post_fix), \ + SFRB(VPCM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G, VPCM_GAMCOR_RAMA_END_CNTL2_G, post_fix), \ + SFRB(VPCM_GAMCOR_RAMA_EXP_REGION_END_BASE_R, VPCM_GAMCOR_RAMA_END_CNTL1_R, post_fix), \ + SFRB(VPCM_GAMCOR_RAMA_EXP_REGION_END_R, VPCM_GAMCOR_RAMA_END_CNTL2_R, post_fix), \ + SFRB(VPCM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R, VPCM_GAMCOR_RAMA_END_CNTL2_R, post_fix), \ + SFRB(VPCM_GAMCOR_RAMA_OFFSET_B, VPCM_GAMCOR_RAMA_OFFSET_B, post_fix), \ + SFRB(VPCM_GAMCOR_RAMA_OFFSET_G, VPCM_GAMCOR_RAMA_OFFSET_G, post_fix), \ + SFRB(VPCM_GAMCOR_RAMA_OFFSET_R, VPCM_GAMCOR_RAMA_OFFSET_R, post_fix), \ + SFRB(VPCM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET, VPCM_GAMCOR_RAMA_REGION_0_1, post_fix), \ + SFRB(VPCM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS, VPCM_GAMCOR_RAMA_REGION_0_1, post_fix), \ + SFRB(VPCM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET, VPCM_GAMCOR_RAMA_REGION_0_1, post_fix), \ + SFRB(VPCM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS, VPCM_GAMCOR_RAMA_REGION_0_1, post_fix), \ + SFRB(VPCM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET, VPCM_GAMCOR_RAMA_REGION_2_3, post_fix), \ + SFRB(VPCM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS, VPCM_GAMCOR_RAMA_REGION_2_3, post_fix), \ + SFRB(VPCM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET, VPCM_GAMCOR_RAMA_REGION_2_3, post_fix), \ + SFRB(VPCM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS, VPCM_GAMCOR_RAMA_REGION_2_3, post_fix), \ + SFRB(VPCM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET, VPCM_GAMCOR_RAMA_REGION_4_5, post_fix), \ + SFRB(VPCM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS, VPCM_GAMCOR_RAMA_REGION_4_5, post_fix), \ + SFRB(VPCM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET, VPCM_GAMCOR_RAMA_REGION_4_5, post_fix), \ + SFRB(VPCM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS, VPCM_GAMCOR_RAMA_REGION_4_5, post_fix), \ + SFRB(VPCM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET, VPCM_GAMCOR_RAMA_REGION_6_7, post_fix), \ + SFRB(VPCM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS, VPCM_GAMCOR_RAMA_REGION_6_7, post_fix), \ + SFRB(VPCM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET, VPCM_GAMCOR_RAMA_REGION_6_7, post_fix), \ + SFRB(VPCM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS, VPCM_GAMCOR_RAMA_REGION_6_7, post_fix), \ + SFRB(VPCM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET, VPCM_GAMCOR_RAMA_REGION_8_9, post_fix), \ + SFRB(VPCM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS, VPCM_GAMCOR_RAMA_REGION_8_9, post_fix), \ + SFRB(VPCM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET, VPCM_GAMCOR_RAMA_REGION_8_9, post_fix), \ + SFRB(VPCM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS, VPCM_GAMCOR_RAMA_REGION_8_9, post_fix), \ + SFRB(VPCM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET, VPCM_GAMCOR_RAMA_REGION_10_11, post_fix), \ + SFRB(VPCM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS, VPCM_GAMCOR_RAMA_REGION_10_11, post_fix), \ + SFRB(VPCM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET, VPCM_GAMCOR_RAMA_REGION_10_11, post_fix), \ + SFRB(VPCM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS, VPCM_GAMCOR_RAMA_REGION_10_11, post_fix), \ + SFRB(VPCM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET, VPCM_GAMCOR_RAMA_REGION_12_13, post_fix), \ + SFRB(VPCM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS, VPCM_GAMCOR_RAMA_REGION_12_13, post_fix), \ + SFRB(VPCM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET, VPCM_GAMCOR_RAMA_REGION_12_13, post_fix), \ + SFRB(VPCM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS, VPCM_GAMCOR_RAMA_REGION_12_13, post_fix), \ + SFRB(VPCM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET, VPCM_GAMCOR_RAMA_REGION_14_15, post_fix), \ + SFRB(VPCM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS, VPCM_GAMCOR_RAMA_REGION_14_15, post_fix), \ + SFRB(VPCM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET, VPCM_GAMCOR_RAMA_REGION_14_15, post_fix), \ + SFRB(VPCM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS, VPCM_GAMCOR_RAMA_REGION_14_15, post_fix), \ + SFRB(VPCM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET, VPCM_GAMCOR_RAMA_REGION_16_17, post_fix), \ + SFRB(VPCM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS, VPCM_GAMCOR_RAMA_REGION_16_17, post_fix), \ + SFRB(VPCM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET, VPCM_GAMCOR_RAMA_REGION_16_17, post_fix), \ + SFRB(VPCM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS, VPCM_GAMCOR_RAMA_REGION_16_17, post_fix), \ + SFRB(VPCM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET, VPCM_GAMCOR_RAMA_REGION_18_19, post_fix), \ + SFRB(VPCM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS, VPCM_GAMCOR_RAMA_REGION_18_19, post_fix), \ + SFRB(VPCM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET, VPCM_GAMCOR_RAMA_REGION_18_19, post_fix), \ + SFRB(VPCM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS, VPCM_GAMCOR_RAMA_REGION_18_19, post_fix), \ + SFRB(VPCM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET, VPCM_GAMCOR_RAMA_REGION_20_21, post_fix), \ + SFRB(VPCM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS, VPCM_GAMCOR_RAMA_REGION_20_21, post_fix), \ + SFRB(VPCM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET, VPCM_GAMCOR_RAMA_REGION_20_21, post_fix), \ + SFRB(VPCM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS, VPCM_GAMCOR_RAMA_REGION_20_21, post_fix), \ + SFRB(VPCM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET, VPCM_GAMCOR_RAMA_REGION_22_23, post_fix), \ + SFRB(VPCM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS, VPCM_GAMCOR_RAMA_REGION_22_23, post_fix), \ + SFRB(VPCM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET, VPCM_GAMCOR_RAMA_REGION_22_23, post_fix), \ + SFRB(VPCM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS, VPCM_GAMCOR_RAMA_REGION_22_23, post_fix), \ + SFRB(VPCM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET, VPCM_GAMCOR_RAMA_REGION_24_25, post_fix), \ + SFRB(VPCM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS, VPCM_GAMCOR_RAMA_REGION_24_25, post_fix), \ + SFRB(VPCM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET, VPCM_GAMCOR_RAMA_REGION_24_25, post_fix), \ + SFRB(VPCM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS, VPCM_GAMCOR_RAMA_REGION_24_25, post_fix), \ + SFRB(VPCM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET, VPCM_GAMCOR_RAMA_REGION_26_27, post_fix), \ + SFRB(VPCM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS, VPCM_GAMCOR_RAMA_REGION_26_27, post_fix), \ + SFRB(VPCM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET, VPCM_GAMCOR_RAMA_REGION_26_27, post_fix), \ + SFRB(VPCM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS, VPCM_GAMCOR_RAMA_REGION_26_27, post_fix), \ + SFRB(VPCM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET, VPCM_GAMCOR_RAMA_REGION_28_29, post_fix), \ + SFRB(VPCM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS, VPCM_GAMCOR_RAMA_REGION_28_29, post_fix), \ + SFRB(VPCM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET, VPCM_GAMCOR_RAMA_REGION_28_29, post_fix), \ + SFRB(VPCM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS, VPCM_GAMCOR_RAMA_REGION_28_29, post_fix), \ + SFRB(VPCM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET, VPCM_GAMCOR_RAMA_REGION_30_31, post_fix), \ + SFRB(VPCM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS, VPCM_GAMCOR_RAMA_REGION_30_31, post_fix), \ + SFRB(VPCM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET, VPCM_GAMCOR_RAMA_REGION_30_31, post_fix), \ + SFRB(VPCM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS, VPCM_GAMCOR_RAMA_REGION_30_31, post_fix), \ + SFRB(VPCM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET, VPCM_GAMCOR_RAMA_REGION_32_33, post_fix), \ + SFRB(VPCM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS, VPCM_GAMCOR_RAMA_REGION_32_33, post_fix), \ + SFRB(VPCM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET, VPCM_GAMCOR_RAMA_REGION_32_33, post_fix), \ + SFRB(VPCM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS, VPCM_GAMCOR_RAMA_REGION_32_33, post_fix), \ + SFRB(VPCM_HDR_MULT_COEF, VPCM_HDR_MULT_COEF, post_fix), \ + SFRB(GAMCOR_MEM_PWR_FORCE, VPCM_MEM_PWR_CTRL, post_fix), \ + SFRB(GAMCOR_MEM_PWR_DIS, VPCM_MEM_PWR_CTRL, post_fix), \ + SFRB(GAMCOR_MEM_PWR_STATE, VPCM_MEM_PWR_STATUS, post_fix), \ + SFRB(VPCM_DEALPHA_EN, VPCM_DEALPHA, post_fix), \ + SFRB(VPCM_DEALPHA_ABLND, VPCM_DEALPHA, post_fix), \ + SFRB(VPCM_BIAS_FORMAT, VPCM_COEF_FORMAT, post_fix), \ + SFRB(VPCM_POST_CSC_COEF_FORMAT, VPCM_COEF_FORMAT, post_fix), \ + SFRB(VPCM_GAMUT_REMAP_COEF_FORMAT, VPCM_COEF_FORMAT, post_fix), \ + SFRB(VPDPP_CLOCK_ENABLE, VPDPP_CONTROL, post_fix), \ + SFRB(VPECLK_G_GATE_DISABLE, VPDPP_CONTROL, post_fix), \ + SFRB(VPECLK_G_DYN_GATE_DISABLE, VPDPP_CONTROL, post_fix), \ + SFRB(VPECLK_G_VPDSCL_GATE_DISABLE, VPDPP_CONTROL, post_fix), \ + SFRB(VPECLK_R_GATE_DISABLE, VPDPP_CONTROL, post_fix), \ + SFRB(DISPCLK_R_GATE_DISABLE, VPDPP_CONTROL, post_fix), \ + SFRB(DISPCLK_G_GATE_DISABLE, VPDPP_CONTROL, post_fix), \ + SFRB(VPDPP_FGCG_REP_DIS, VPDPP_CONTROL, post_fix), \ + SFRB(VPDPP_TEST_CLK_SEL, VPDPP_CONTROL, post_fix), \ + SFRB(VPDPP_CRC_EN, VPDPP_CRC_CTRL, post_fix), \ + SFRB(VPDPP_CRC_CONT_EN, VPDPP_CRC_CTRL, post_fix), \ + SFRB(VPDPP_CRC_420_COMP_SEL, VPDPP_CRC_CTRL, post_fix), \ + SFRB(VPDPP_CRC_SRC_SEL, VPDPP_CRC_CTRL, post_fix), \ + SFRB(VPDPP_CRC_PIX_FORMAT_SEL, VPDPP_CRC_CTRL, post_fix), \ + SFRB(VPDPP_CRC_MASK, VPDPP_CRC_CTRL, post_fix) + +#define DPP_REG_VARIABLE_LIST_VPE10 \ + reg_id_val VPCNVC_SURFACE_PIXEL_FORMAT; \ + reg_id_val VPCNVC_FORMAT_CONTROL; \ + reg_id_val VPCNVC_FCNV_FP_BIAS_R; \ + reg_id_val VPCNVC_FCNV_FP_BIAS_G; \ + reg_id_val VPCNVC_FCNV_FP_BIAS_B; \ + reg_id_val VPCNVC_FCNV_FP_SCALE_R; \ + reg_id_val VPCNVC_FCNV_FP_SCALE_G; \ + reg_id_val VPCNVC_FCNV_FP_SCALE_B; \ + reg_id_val VPCNVC_COLOR_KEYER_CONTROL; \ + reg_id_val VPCNVC_COLOR_KEYER_ALPHA; \ + reg_id_val VPCNVC_COLOR_KEYER_RED; \ + reg_id_val VPCNVC_COLOR_KEYER_GREEN; \ + reg_id_val VPCNVC_COLOR_KEYER_BLUE; \ + reg_id_val VPCNVC_ALPHA_2BIT_LUT; \ + reg_id_val VPCNVC_PRE_DEALPHA; \ + reg_id_val VPCNVC_PRE_CSC_MODE; \ + reg_id_val VPCNVC_PRE_CSC_C11_C12; \ + reg_id_val VPCNVC_PRE_CSC_C13_C14; \ + reg_id_val VPCNVC_PRE_CSC_C21_C22; \ + reg_id_val VPCNVC_PRE_CSC_C23_C24; \ + reg_id_val VPCNVC_PRE_CSC_C31_C32; \ + reg_id_val VPCNVC_PRE_CSC_C33_C34; \ + reg_id_val VPCNVC_COEF_FORMAT; \ + reg_id_val VPCNVC_PRE_DEGAM; \ + reg_id_val VPCNVC_PRE_REALPHA; \ + reg_id_val VPDSCL_COEF_RAM_TAP_SELECT; \ + reg_id_val VPDSCL_COEF_RAM_TAP_DATA; \ + reg_id_val VPDSCL_MODE; \ + reg_id_val VPDSCL_TAP_CONTROL; \ + reg_id_val VPDSCL_CONTROL; \ + reg_id_val VPDSCL_2TAP_CONTROL; \ + reg_id_val VPDSCL_MANUAL_REPLICATE_CONTROL; \ + reg_id_val VPDSCL_HORZ_FILTER_SCALE_RATIO; \ + reg_id_val VPDSCL_HORZ_FILTER_INIT; \ + reg_id_val VPDSCL_HORZ_FILTER_SCALE_RATIO_C; \ + reg_id_val VPDSCL_HORZ_FILTER_INIT_C; \ + reg_id_val VPDSCL_VERT_FILTER_SCALE_RATIO; \ + reg_id_val VPDSCL_VERT_FILTER_INIT; \ + reg_id_val VPDSCL_VERT_FILTER_SCALE_RATIO_C; \ + reg_id_val VPDSCL_VERT_FILTER_INIT_C; \ + reg_id_val VPDSCL_BLACK_COLOR; \ + reg_id_val VPDSCL_UPDATE; \ + reg_id_val VPDSCL_AUTOCAL; \ + reg_id_val VPDSCL_EXT_OVERSCAN_LEFT_RIGHT; \ + reg_id_val VPDSCL_EXT_OVERSCAN_TOP_BOTTOM; \ + reg_id_val VPOTG_H_BLANK; \ + reg_id_val VPOTG_V_BLANK; \ + reg_id_val VPDSCL_RECOUT_START; \ + reg_id_val VPDSCL_RECOUT_SIZE; \ + reg_id_val VPMPC_SIZE; \ + reg_id_val VPLB_DATA_FORMAT; \ + reg_id_val VPLB_MEMORY_CTRL; \ + reg_id_val VPLB_V_COUNTER; \ + reg_id_val VPDSCL_MEM_PWR_CTRL; \ + reg_id_val VPDSCL_MEM_PWR_STATUS; \ + reg_id_val VPCM_CONTROL; \ + reg_id_val VPCM_POST_CSC_CONTROL; \ + reg_id_val VPCM_POST_CSC_C11_C12; \ + reg_id_val VPCM_POST_CSC_C13_C14; \ + reg_id_val VPCM_POST_CSC_C21_C22; \ + reg_id_val VPCM_POST_CSC_C23_C24; \ + reg_id_val VPCM_POST_CSC_C31_C32; \ + reg_id_val VPCM_POST_CSC_C33_C34; \ + reg_id_val VPCM_GAMUT_REMAP_CONTROL; \ + reg_id_val VPCM_GAMUT_REMAP_C11_C12; \ + reg_id_val VPCM_GAMUT_REMAP_C13_C14; \ + reg_id_val VPCM_GAMUT_REMAP_C21_C22; \ + reg_id_val VPCM_GAMUT_REMAP_C23_C24; \ + reg_id_val VPCM_GAMUT_REMAP_C31_C32; \ + reg_id_val VPCM_GAMUT_REMAP_C33_C34; \ + reg_id_val VPCM_BIAS_CR_R; \ + reg_id_val VPCM_BIAS_Y_G_CB_B; \ + reg_id_val VPCM_GAMCOR_CONTROL; \ + reg_id_val VPCM_GAMCOR_LUT_INDEX; \ + reg_id_val VPCM_GAMCOR_LUT_DATA; \ + reg_id_val VPCM_GAMCOR_LUT_CONTROL; \ + reg_id_val VPCM_GAMCOR_RAMA_START_CNTL_B; \ + reg_id_val VPCM_GAMCOR_RAMA_START_CNTL_G; \ + reg_id_val VPCM_GAMCOR_RAMA_START_CNTL_R; \ + reg_id_val VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_B; \ + reg_id_val VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_G; \ + reg_id_val VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_R; \ + reg_id_val VPCM_GAMCOR_RAMA_START_BASE_CNTL_B; \ + reg_id_val VPCM_GAMCOR_RAMA_START_BASE_CNTL_G; \ + reg_id_val VPCM_GAMCOR_RAMA_START_BASE_CNTL_R; \ + reg_id_val VPCM_GAMCOR_RAMA_END_CNTL1_B; \ + reg_id_val VPCM_GAMCOR_RAMA_END_CNTL2_B; \ + reg_id_val VPCM_GAMCOR_RAMA_END_CNTL1_G; \ + reg_id_val VPCM_GAMCOR_RAMA_END_CNTL2_G; \ + reg_id_val VPCM_GAMCOR_RAMA_END_CNTL1_R; \ + reg_id_val VPCM_GAMCOR_RAMA_END_CNTL2_R; \ + reg_id_val VPCM_GAMCOR_RAMA_OFFSET_B; \ + reg_id_val VPCM_GAMCOR_RAMA_OFFSET_G; \ + reg_id_val VPCM_GAMCOR_RAMA_OFFSET_R; \ + reg_id_val VPCM_GAMCOR_RAMA_REGION_0_1; \ + reg_id_val VPCM_GAMCOR_RAMA_REGION_2_3; \ + reg_id_val VPCM_GAMCOR_RAMA_REGION_4_5; \ + reg_id_val VPCM_GAMCOR_RAMA_REGION_6_7; \ + reg_id_val VPCM_GAMCOR_RAMA_REGION_8_9; \ + reg_id_val VPCM_GAMCOR_RAMA_REGION_10_11; \ + reg_id_val VPCM_GAMCOR_RAMA_REGION_12_13; \ + reg_id_val VPCM_GAMCOR_RAMA_REGION_14_15; \ + reg_id_val VPCM_GAMCOR_RAMA_REGION_16_17; \ + reg_id_val VPCM_GAMCOR_RAMA_REGION_18_19; \ + reg_id_val VPCM_GAMCOR_RAMA_REGION_20_21; \ + reg_id_val VPCM_GAMCOR_RAMA_REGION_22_23; \ + reg_id_val VPCM_GAMCOR_RAMA_REGION_24_25; \ + reg_id_val VPCM_GAMCOR_RAMA_REGION_26_27; \ + reg_id_val VPCM_GAMCOR_RAMA_REGION_28_29; \ + reg_id_val VPCM_GAMCOR_RAMA_REGION_30_31; \ + reg_id_val VPCM_GAMCOR_RAMA_REGION_32_33; \ + reg_id_val VPCM_HDR_MULT_COEF; \ + reg_id_val VPCM_MEM_PWR_CTRL; \ + reg_id_val VPCM_MEM_PWR_STATUS; \ + reg_id_val VPCM_DEALPHA; \ + reg_id_val VPCM_COEF_FORMAT; \ + reg_id_val VPDPP_CONTROL; \ + reg_id_val VPDPP_CRC_CTRL; + +#define DPP_FIELD_VARIABLE_LIST_VPE10(type) \ + type VPCNVC_SURFACE_PIXEL_FORMAT; \ + type FORMAT_EXPANSION_MODE; \ + type FORMAT_CNV16; \ + type FORMAT_CONTROL__ALPHA_EN; \ + type VPCNVC_BYPASS; \ + type VPCNVC_BYPASS_MSB_ALIGN; \ + type CLAMP_POSITIVE; \ + type CLAMP_POSITIVE_C; \ + type VPCNVC_UPDATE_PENDING; \ + type FCNV_FP_BIAS_R; \ + type FCNV_FP_BIAS_G; \ + type FCNV_FP_BIAS_B; \ + type FCNV_FP_SCALE_R; \ + type FCNV_FP_SCALE_G; \ + type FCNV_FP_SCALE_B; \ + type COLOR_KEYER_EN; \ + type COLOR_KEYER_MODE; \ + type COLOR_KEYER_ALPHA_LOW; \ + type COLOR_KEYER_ALPHA_HIGH; \ + type COLOR_KEYER_RED_LOW; \ + type COLOR_KEYER_RED_HIGH; \ + type COLOR_KEYER_GREEN_LOW; \ + type COLOR_KEYER_GREEN_HIGH; \ + type COLOR_KEYER_BLUE_LOW; \ + type COLOR_KEYER_BLUE_HIGH; \ + type ALPHA_2BIT_LUT0; \ + type ALPHA_2BIT_LUT1; \ + type ALPHA_2BIT_LUT2; \ + type ALPHA_2BIT_LUT3; \ + type PRE_DEALPHA_EN; \ + type PRE_DEALPHA_ABLND_EN; \ + type PRE_CSC_MODE; \ + type PRE_CSC_MODE_CURRENT; \ + type PRE_CSC_C11; \ + type PRE_CSC_C12; \ + type PRE_CSC_C13; \ + type PRE_CSC_C14; \ + type PRE_CSC_C21; \ + type PRE_CSC_C22; \ + type PRE_CSC_C23; \ + type PRE_CSC_C24; \ + type PRE_CSC_C31; \ + type PRE_CSC_C32; \ + type PRE_CSC_C33; \ + type PRE_CSC_C34; \ + type PRE_CSC_COEF_FORMAT; \ + type PRE_DEGAM_MODE; \ + type PRE_DEGAM_SELECT; \ + type PRE_REALPHA_EN; \ + type PRE_REALPHA_ABLND_EN; \ + type SCL_COEF_RAM_TAP_PAIR_IDX; \ + type SCL_COEF_RAM_PHASE; \ + type SCL_COEF_RAM_FILTER_TYPE; \ + type SCL_COEF_RAM_EVEN_TAP_COEF; \ + type SCL_COEF_RAM_EVEN_TAP_COEF_EN; \ + type SCL_COEF_RAM_ODD_TAP_COEF; \ + type SCL_COEF_RAM_ODD_TAP_COEF_EN; \ + type VPDSCL_MODE; \ + type SCL_COEF_RAM_SELECT_CURRENT; \ + type SCL_CHROMA_COEF_MODE; \ + type SCL_ALPHA_COEF_MODE; \ + type SCL_COEF_RAM_SELECT_RD; \ + type SCL_V_NUM_TAPS; \ + type SCL_H_NUM_TAPS; \ + type SCL_V_NUM_TAPS_C; \ + type SCL_H_NUM_TAPS_C; \ + type SCL_BOUNDARY_MODE; \ + type SCL_H_2TAP_HARDCODE_COEF_EN; \ + type SCL_H_2TAP_SHARP_EN; \ + type SCL_H_2TAP_SHARP_FACTOR; \ + type SCL_V_2TAP_HARDCODE_COEF_EN; \ + type SCL_V_2TAP_SHARP_EN; \ + type SCL_V_2TAP_SHARP_FACTOR; \ + type SCL_V_MANUAL_REPLICATE_FACTOR; \ + type SCL_H_MANUAL_REPLICATE_FACTOR; \ + type SCL_H_SCALE_RATIO; \ + type SCL_H_INIT_FRAC; \ + type SCL_H_INIT_INT; \ + type SCL_H_SCALE_RATIO_C; \ + type SCL_H_INIT_FRAC_C; \ + type SCL_H_INIT_INT_C; \ + type SCL_V_SCALE_RATIO; \ + type SCL_V_INIT_FRAC; \ + type SCL_V_INIT_INT; \ + type SCL_V_SCALE_RATIO_C; \ + type SCL_V_INIT_FRAC_C; \ + type SCL_V_INIT_INT_C; \ + type SCL_BLACK_COLOR_RGB_Y; \ + type SCL_BLACK_COLOR_CBCR; \ + type SCL_UPDATE_PENDING; \ + type AUTOCAL_MODE; \ + type EXT_OVERSCAN_RIGHT; \ + type EXT_OVERSCAN_LEFT; \ + type EXT_OVERSCAN_BOTTOM; \ + type EXT_OVERSCAN_TOP; \ + type OTG_H_BLANK_START; \ + type OTG_H_BLANK_END; \ + type OTG_V_BLANK_START; \ + type OTG_V_BLANK_END; \ + type RECOUT_START_X; \ + type RECOUT_START_Y; \ + type RECOUT_WIDTH; \ + type RECOUT_HEIGHT; \ + type VPMPC_WIDTH; \ + type VPMPC_HEIGHT; \ + type ALPHA_EN; \ + type MEMORY_CONFIG; \ + type LB_MAX_PARTITIONS; \ + type LB_NUM_PARTITIONS; \ + type LB_NUM_PARTITIONS_C; \ + type V_COUNTER; \ + type V_COUNTER_C; \ + type LUT_MEM_PWR_FORCE; \ + type LUT_MEM_PWR_DIS; \ + type LB_G1_MEM_PWR_FORCE; \ + type LB_G1_MEM_PWR_DIS; \ + type LB_G2_MEM_PWR_FORCE; \ + type LB_G2_MEM_PWR_DIS; \ + type LB_MEM_PWR_MODE; \ + type LUT_MEM_PWR_STATE; \ + type LB_G1_MEM_PWR_STATE; \ + type LB_G2_MEM_PWR_STATE; \ + type VPCM_BYPASS; \ + type VPCM_UPDATE_PENDING; \ + type VPCM_POST_CSC_MODE; \ + type VPCM_POST_CSC_MODE_CURRENT; \ + type VPCM_POST_CSC_C11; \ + type VPCM_POST_CSC_C12; \ + type VPCM_POST_CSC_C13; \ + type VPCM_POST_CSC_C14; \ + type VPCM_POST_CSC_C21; \ + type VPCM_POST_CSC_C22; \ + type VPCM_POST_CSC_C23; \ + type VPCM_POST_CSC_C24; \ + type VPCM_POST_CSC_C31; \ + type VPCM_POST_CSC_C32; \ + type VPCM_POST_CSC_C33; \ + type VPCM_POST_CSC_C34; \ + type VPCM_GAMUT_REMAP_MODE; \ + type VPCM_GAMUT_REMAP_MODE_CURRENT; \ + type VPCM_GAMUT_REMAP_C11; \ + type VPCM_GAMUT_REMAP_C12; \ + type VPCM_GAMUT_REMAP_C13; \ + type VPCM_GAMUT_REMAP_C14; \ + type VPCM_GAMUT_REMAP_C21; \ + type VPCM_GAMUT_REMAP_C22; \ + type VPCM_GAMUT_REMAP_C23; \ + type VPCM_GAMUT_REMAP_C24; \ + type VPCM_GAMUT_REMAP_C31; \ + type VPCM_GAMUT_REMAP_C32; \ + type VPCM_GAMUT_REMAP_C33; \ + type VPCM_GAMUT_REMAP_C34; \ + type VPCM_BIAS_CR_R; \ + type VPCM_BIAS_Y_G; \ + type VPCM_BIAS_CB_B; \ + type VPCM_GAMCOR_MODE; \ + type VPCM_GAMCOR_PWL_DISABLE; \ + type VPCM_GAMCOR_MODE_CURRENT; \ + type VPCM_GAMCOR_SELECT_CURRENT; \ + type VPCM_GAMCOR_LUT_INDEX; \ + type VPCM_GAMCOR_LUT_DATA; \ + type VPCM_GAMCOR_LUT_WRITE_COLOR_MASK; \ + type VPCM_GAMCOR_LUT_READ_COLOR_SEL; \ + type VPCM_GAMCOR_LUT_READ_DBG; \ + type VPCM_GAMCOR_LUT_HOST_SEL; \ + type VPCM_GAMCOR_LUT_CONFIG_MODE; \ + type VPCM_GAMCOR_RAMA_EXP_REGION_START_B; \ + type VPCM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B; \ + type VPCM_GAMCOR_RAMA_EXP_REGION_START_G; \ + type VPCM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G; \ + type VPCM_GAMCOR_RAMA_EXP_REGION_START_R; \ + type VPCM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R; \ + type VPCM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B; \ + type VPCM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G; \ + type VPCM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R; \ + type VPCM_GAMCOR_RAMA_EXP_REGION_START_BASE_B; \ + type VPCM_GAMCOR_RAMA_EXP_REGION_START_BASE_G; \ + type VPCM_GAMCOR_RAMA_EXP_REGION_START_BASE_R; \ + type VPCM_GAMCOR_RAMA_EXP_REGION_END_BASE_B; \ + type VPCM_GAMCOR_RAMA_EXP_REGION_END_B; \ + type VPCM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B; \ + type VPCM_GAMCOR_RAMA_EXP_REGION_END_BASE_G; \ + type VPCM_GAMCOR_RAMA_EXP_REGION_END_G; \ + type VPCM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G; \ + type VPCM_GAMCOR_RAMA_EXP_REGION_END_BASE_R; \ + type VPCM_GAMCOR_RAMA_EXP_REGION_END_R; \ + type VPCM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R; \ + type VPCM_GAMCOR_RAMA_OFFSET_B; \ + type VPCM_GAMCOR_RAMA_OFFSET_G; \ + type VPCM_GAMCOR_RAMA_OFFSET_R; \ + type VPCM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET; \ + type VPCM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS; \ + type VPCM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET; \ + type VPCM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS; \ + type VPCM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET; \ + type VPCM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS; \ + type VPCM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET; \ + type VPCM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS; \ + type VPCM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET; \ + type VPCM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS; \ + type VPCM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET; \ + type VPCM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS; \ + type VPCM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET; \ + type VPCM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS; \ + type VPCM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET; \ + type VPCM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS; \ + type VPCM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET; \ + type VPCM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS; \ + type VPCM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET; \ + type VPCM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS; \ + type VPCM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET; \ + type VPCM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS; \ + type VPCM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET; \ + type VPCM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS; \ + type VPCM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET; \ + type VPCM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS; \ + type VPCM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET; \ + type VPCM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS; \ + type VPCM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET; \ + type VPCM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS; \ + type VPCM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET; \ + type VPCM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS; \ + type VPCM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET; \ + type VPCM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS; \ + type VPCM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET; \ + type VPCM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS; \ + type VPCM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET; \ + type VPCM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS; \ + type VPCM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET; \ + type VPCM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS; \ + type VPCM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET; \ + type VPCM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS; \ + type VPCM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET; \ + type VPCM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS; \ + type VPCM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET; \ + type VPCM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS; \ + type VPCM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET; \ + type VPCM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS; \ + type VPCM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET; \ + type VPCM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS; \ + type VPCM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET; \ + type VPCM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS; \ + type VPCM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET; \ + type VPCM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS; \ + type VPCM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET; \ + type VPCM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS; \ + type VPCM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET; \ + type VPCM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS; \ + type VPCM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET; \ + type VPCM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS; \ + type VPCM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET; \ + type VPCM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS; \ + type VPCM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET; \ + type VPCM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS; \ + type VPCM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET; \ + type VPCM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS; \ + type VPCM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET; \ + type VPCM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS; \ + type VPCM_HDR_MULT_COEF; \ + type GAMCOR_MEM_PWR_FORCE; \ + type GAMCOR_MEM_PWR_DIS; \ + type GAMCOR_MEM_PWR_STATE; \ + type VPCM_DEALPHA_EN; \ + type VPCM_DEALPHA_ABLND; \ + type VPCM_BIAS_FORMAT; \ + type VPCM_POST_CSC_COEF_FORMAT; \ + type VPCM_GAMUT_REMAP_COEF_FORMAT; \ + type VPDPP_CLOCK_ENABLE; \ + type VPECLK_G_GATE_DISABLE; \ + type VPECLK_G_DYN_GATE_DISABLE; \ + type VPECLK_G_VPDSCL_GATE_DISABLE; \ + type VPECLK_R_GATE_DISABLE; \ + type DISPCLK_R_GATE_DISABLE; \ + type DISPCLK_G_GATE_DISABLE; \ + type VPDPP_FGCG_REP_DIS; \ + type VPDPP_TEST_CLK_SEL; \ + type VPDPP_CRC_EN; \ + type VPDPP_CRC_CONT_EN; \ + type VPDPP_CRC_420_COMP_SEL; \ + type VPDPP_CRC_SRC_SEL; \ + type VPDPP_CRC_PIX_FORMAT_SEL; \ + type VPDPP_CRC_MASK; + +#define IDENTITY_RATIO(ratio) (vpe_fixpt_u3d19(ratio) == (1 << 19)) + +struct vpe10_dpp_registers { + DPP_REG_VARIABLE_LIST_VPE10 +}; + +struct vpe10_dpp_shift { + DPP_FIELD_VARIABLE_LIST_VPE10(uint8_t) +}; + +struct vpe10_dpp_mask { + DPP_FIELD_VARIABLE_LIST_VPE10(uint32_t) +}; + +struct vpe10_dpp { + struct dpp base; // base class, must be the 1st field + struct vpe10_dpp_registers *regs; + const struct vpe10_dpp_shift *shift; + const struct vpe10_dpp_mask *mask; +}; + +void vpe10_construct_dpp(struct vpe_priv *vpe_priv, struct dpp *dpp); + +bool vpe10_dpp_get_optimal_number_of_taps( + struct dpp *dpp, struct scaler_data *scl_data, const struct vpe_scaling_taps *in_taps); + +void vpe10_dscl_calc_lb_num_partitions(const struct scaler_data *scl_data, + enum lb_memory_config lb_config, uint32_t *num_part_y, uint32_t *num_part_c); + +/***** share register programming *****/ +void vpe10_dpp_program_cnv( + struct dpp *dpp, enum vpe_surface_pixel_format format, enum vpe_expansion_mode mode); + +void vpe10_dpp_cnv_program_pre_dgam(struct dpp *dpp, enum color_transfer_func tr); + +void vpe10_dpp_program_cnv_bias_scale(struct dpp *dpp, struct bias_and_scale *bias_and_scale); + +void vpe10_dpp_cnv_program_alpha_keyer(struct dpp *dpp, struct cnv_color_keyer_params *color_keyer); + +void vpe10_dpp_program_input_transfer_func(struct dpp *dpp, struct transfer_func *input_tf); + +void vpe10_dpp_program_gamut_remap(struct dpp *dpp, struct colorspace_transform *gamut_remap); + +/*program post scaler scs block in dpp CM*/ +void vpe10_dpp_program_post_csc(struct dpp *dpp, enum color_space color_space, + enum input_csc_select input_select, struct vpe_csc_matrix *input_cs); + +void vpe10_dpp_set_hdr_multiplier(struct dpp *dpp, uint32_t multiplier); + +/*Program Scaler*/ +void vpe10_dpp_set_segment_scaler(struct dpp *dpp, const struct scaler_data *scl_data); + +void vpe10_dpp_set_frame_scaler(struct dpp *dpp, const struct scaler_data *scl_data); + +uint32_t vpe10_get_line_buffer_size(void); + +bool vpe10_dpp_validate_number_of_taps(struct dpp *dpp, struct scaler_data *scl_data); + +void vpe10_dpp_program_crc(struct dpp *dpp, bool enable); +#ifdef __cplusplus +} +#endif diff --git a/src/amd/vpelib/src/chip/vpe10/inc/vpe10_mpc.h b/src/amd/vpelib/src/chip/vpe10/inc/vpe10_mpc.h new file mode 100644 index 00000000000..3a4416c6c5c --- /dev/null +++ b/src/amd/vpelib/src/chip/vpe10/inc/vpe10_mpc.h @@ -0,0 +1,1460 @@ +/* Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ +#pragma once + +#include "mpc.h" +#include "reg_helper.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define MPC_REG_LIST_VPE10(id) \ + SRIDFVL(VPMPC_CLOCK_CONTROL, VPMPC_CFG, id), SRIDFVL(VPMPC_SOFT_RESET, VPMPC_CFG, id), \ + SRIDFVL(VPMPC_CRC_CTRL, VPMPC_CFG, id), SRIDFVL(VPMPC_CRC_SEL_CONTROL, VPMPC_CFG, id), \ + SRIDFVL(VPMPC_CRC_RESULT_AR, VPMPC_CFG, id), SRIDFVL(VPMPC_CRC_RESULT_GB, VPMPC_CFG, id), \ + SRIDFVL(VPMPC_CRC_RESULT_C, VPMPC_CFG, id), SRIDFVL(VPMPC_BYPASS_BG_AR, VPMPC_CFG, id), \ + SRIDFVL(VPMPC_BYPASS_BG_GB, VPMPC_CFG, id), \ + SRIDFVL(VPMPC_HOST_READ_CONTROL, VPMPC_CFG, id), \ + SRIDFVL(VPMPC_PENDING_STATUS_MISC, VPMPC_CFG, id), \ + SRIDFVL(VPMPC_OUT0_MUX, VPMPC_OCSC, id), \ + SRIDFVL(VPMPC_OUT0_FLOAT_CONTROL, VPMPC_OCSC, id), \ + SRIDFVL(VPMPC_OUT0_DENORM_CONTROL, VPMPC_OCSC, id), \ + SRIDFVL(VPMPC_OUT0_DENORM_CLAMP_G_Y, VPMPC_OCSC, id), \ + SRIDFVL(VPMPC_OUT0_DENORM_CLAMP_B_CB, VPMPC_OCSC, id), \ + SRIDFVL(VPMPC_OUT_CSC_COEF_FORMAT, VPMPC_OCSC, id), \ + SRIDFVL(VPMPC_OUT0_CSC_MODE, VPMPC_OCSC, id), \ + SRIDFVL(VPMPC_OUT0_CSC_C11_C12_A, VPMPC_OCSC, id), \ + SRIDFVL(VPMPC_OUT0_CSC_C13_C14_A, VPMPC_OCSC, id), \ + SRIDFVL(VPMPC_OUT0_CSC_C21_C22_A, VPMPC_OCSC, id), \ + SRIDFVL(VPMPC_OUT0_CSC_C23_C24_A, VPMPC_OCSC, id), \ + SRIDFVL(VPMPC_OUT0_CSC_C31_C32_A, VPMPC_OCSC, id), \ + SRIDFVL(VPMPC_OUT0_CSC_C33_C34_A, VPMPC_OCSC, id), SRIDFVL(VPMPCC_TOP_SEL, VPMPCC, id), \ + SRIDFVL(VPMPCC_BOT_SEL, VPMPCC, id), SRIDFVL(VPMPCC_VPOPP_ID, VPMPCC, id), \ + SRIDFVL(VPMPCC_CONTROL, VPMPCC, id), SRIDFVL(VPMPCC_TOP_GAIN, VPMPCC, id), \ + SRIDFVL(VPMPCC_BOT_GAIN_INSIDE, VPMPCC, id), SRIDFVL(VPMPCC_BOT_GAIN_OUTSIDE, VPMPCC, id), \ + SRIDFVL(VPMPCC_MOVABLE_CM_LOCATION_CONTROL, VPMPCC, id), \ + SRIDFVL(VPMPCC_BG_R_CR, VPMPCC, id), SRIDFVL(VPMPCC_BG_G_Y, VPMPCC, id), \ + SRIDFVL(VPMPCC_BG_B_CB, VPMPCC, id), SRIDFVL(VPMPCC_MEM_PWR_CTRL, VPMPCC, id), \ + SRIDFVL(VPMPCC_STATUS, VPMPCC, id), SRIDFVL(VPMPCC_OGAM_CONTROL, VPMPCC_OGAM, id), \ + SRIDFVL(VPMPCC_OGAM_LUT_INDEX, VPMPCC_OGAM, id), \ + SRIDFVL(VPMPCC_OGAM_LUT_DATA, VPMPCC_OGAM, id), \ + SRIDFVL(VPMPCC_OGAM_LUT_CONTROL, VPMPCC_OGAM, id), \ + SRIDFVL(VPMPCC_OGAM_RAMA_START_CNTL_B, VPMPCC_OGAM, id), \ + SRIDFVL(VPMPCC_OGAM_RAMA_START_CNTL_G, VPMPCC_OGAM, id), \ + SRIDFVL(VPMPCC_OGAM_RAMA_START_CNTL_R, VPMPCC_OGAM, id), \ + SRIDFVL(VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_B, VPMPCC_OGAM, id), \ + SRIDFVL(VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_G, VPMPCC_OGAM, id), \ + SRIDFVL(VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_R, VPMPCC_OGAM, id), \ + SRIDFVL(VPMPCC_OGAM_RAMA_START_BASE_CNTL_B, VPMPCC_OGAM, id), \ + SRIDFVL(VPMPCC_OGAM_RAMA_START_BASE_CNTL_G, VPMPCC_OGAM, id), \ + SRIDFVL(VPMPCC_OGAM_RAMA_START_BASE_CNTL_R, VPMPCC_OGAM, id), \ + SRIDFVL(VPMPCC_OGAM_RAMA_END_CNTL1_B, VPMPCC_OGAM, id), \ + SRIDFVL(VPMPCC_OGAM_RAMA_END_CNTL2_B, VPMPCC_OGAM, id), \ + SRIDFVL(VPMPCC_OGAM_RAMA_END_CNTL1_G, VPMPCC_OGAM, id), \ + SRIDFVL(VPMPCC_OGAM_RAMA_END_CNTL2_G, VPMPCC_OGAM, id), \ + SRIDFVL(VPMPCC_OGAM_RAMA_END_CNTL1_R, VPMPCC_OGAM, id), \ + SRIDFVL(VPMPCC_OGAM_RAMA_END_CNTL2_R, VPMPCC_OGAM, id), \ + SRIDFVL(VPMPCC_OGAM_RAMA_OFFSET_B, VPMPCC_OGAM, id), \ + SRIDFVL(VPMPCC_OGAM_RAMA_OFFSET_G, VPMPCC_OGAM, id), \ + SRIDFVL(VPMPCC_OGAM_RAMA_OFFSET_R, VPMPCC_OGAM, id), \ + SRIDFVL(VPMPCC_OGAM_RAMA_REGION_0_1, VPMPCC_OGAM, id), \ + SRIDFVL(VPMPCC_OGAM_RAMA_REGION_2_3, VPMPCC_OGAM, id), \ + SRIDFVL(VPMPCC_OGAM_RAMA_REGION_4_5, VPMPCC_OGAM, id), \ + SRIDFVL(VPMPCC_OGAM_RAMA_REGION_6_7, VPMPCC_OGAM, id), \ + SRIDFVL(VPMPCC_OGAM_RAMA_REGION_8_9, VPMPCC_OGAM, id), \ + SRIDFVL(VPMPCC_OGAM_RAMA_REGION_10_11, VPMPCC_OGAM, id), \ + SRIDFVL(VPMPCC_OGAM_RAMA_REGION_12_13, VPMPCC_OGAM, id), \ + SRIDFVL(VPMPCC_OGAM_RAMA_REGION_14_15, VPMPCC_OGAM, id), \ + SRIDFVL(VPMPCC_OGAM_RAMA_REGION_16_17, VPMPCC_OGAM, id), \ + SRIDFVL(VPMPCC_OGAM_RAMA_REGION_18_19, VPMPCC_OGAM, id), \ + SRIDFVL(VPMPCC_OGAM_RAMA_REGION_20_21, VPMPCC_OGAM, id), \ + SRIDFVL(VPMPCC_OGAM_RAMA_REGION_22_23, VPMPCC_OGAM, id), \ + SRIDFVL(VPMPCC_OGAM_RAMA_REGION_24_25, VPMPCC_OGAM, id), \ + SRIDFVL(VPMPCC_OGAM_RAMA_REGION_26_27, VPMPCC_OGAM, id), \ + SRIDFVL(VPMPCC_OGAM_RAMA_REGION_28_29, VPMPCC_OGAM, id), \ + SRIDFVL(VPMPCC_OGAM_RAMA_REGION_30_31, VPMPCC_OGAM, id), \ + SRIDFVL(VPMPCC_OGAM_RAMA_REGION_32_33, VPMPCC_OGAM, id), \ + SRIDFVL(VPMPCC_GAMUT_REMAP_COEF_FORMAT, VPMPCC_OGAM, id), \ + SRIDFVL(VPMPCC_GAMUT_REMAP_MODE, VPMPCC_OGAM, id), \ + SRIDFVL(VPMPC_GAMUT_REMAP_C11_C12_A, VPMPCC_OGAM, id), \ + SRIDFVL(VPMPC_GAMUT_REMAP_C13_C14_A, VPMPCC_OGAM, id), \ + SRIDFVL(VPMPC_GAMUT_REMAP_C21_C22_A, VPMPCC_OGAM, id), \ + SRIDFVL(VPMPC_GAMUT_REMAP_C23_C24_A, VPMPCC_OGAM, id), \ + SRIDFVL(VPMPC_GAMUT_REMAP_C31_C32_A, VPMPCC_OGAM, id), \ + SRIDFVL(VPMPC_GAMUT_REMAP_C33_C34_A, VPMPCC_OGAM, id), \ + SRIDFVL(VPMPCC_MCM_SHAPER_CONTROL, VPMPCC_MCM, id), \ + SRIDFVL(VPMPCC_MCM_SHAPER_OFFSET_R, VPMPCC_MCM, id), \ + SRIDFVL(VPMPCC_MCM_SHAPER_OFFSET_G, VPMPCC_MCM, id), \ + SRIDFVL(VPMPCC_MCM_SHAPER_OFFSET_B, VPMPCC_MCM, id), \ + SRIDFVL(VPMPCC_MCM_SHAPER_SCALE_R, VPMPCC_MCM, id), \ + SRIDFVL(VPMPCC_MCM_SHAPER_SCALE_G_B, VPMPCC_MCM, id), \ + SRIDFVL(VPMPCC_MCM_SHAPER_LUT_INDEX, VPMPCC_MCM, id), \ + SRIDFVL(VPMPCC_MCM_SHAPER_LUT_DATA, VPMPCC_MCM, id), \ + SRIDFVL(VPMPCC_MCM_SHAPER_LUT_WRITE_EN_MASK, VPMPCC_MCM, id), \ + SRIDFVL(VPMPCC_MCM_SHAPER_RAMA_START_CNTL_B, VPMPCC_MCM, id), \ + SRIDFVL(VPMPCC_MCM_SHAPER_RAMA_START_CNTL_G, VPMPCC_MCM, id), \ + SRIDFVL(VPMPCC_MCM_SHAPER_RAMA_START_CNTL_R, VPMPCC_MCM, id), \ + SRIDFVL(VPMPCC_MCM_SHAPER_RAMA_END_CNTL_B, VPMPCC_MCM, id), \ + SRIDFVL(VPMPCC_MCM_SHAPER_RAMA_END_CNTL_G, VPMPCC_MCM, id), \ + SRIDFVL(VPMPCC_MCM_SHAPER_RAMA_END_CNTL_R, VPMPCC_MCM, id), \ + SRIDFVL(VPMPCC_MCM_SHAPER_RAMA_REGION_0_1, VPMPCC_MCM, id), \ + SRIDFVL(VPMPCC_MCM_SHAPER_RAMA_REGION_2_3, VPMPCC_MCM, id), \ + SRIDFVL(VPMPCC_MCM_SHAPER_RAMA_REGION_4_5, VPMPCC_MCM, id), \ + SRIDFVL(VPMPCC_MCM_SHAPER_RAMA_REGION_6_7, VPMPCC_MCM, id), \ + SRIDFVL(VPMPCC_MCM_SHAPER_RAMA_REGION_8_9, VPMPCC_MCM, id), \ + SRIDFVL(VPMPCC_MCM_SHAPER_RAMA_REGION_10_11, VPMPCC_MCM, id), \ + SRIDFVL(VPMPCC_MCM_SHAPER_RAMA_REGION_12_13, VPMPCC_MCM, id), \ + SRIDFVL(VPMPCC_MCM_SHAPER_RAMA_REGION_14_15, VPMPCC_MCM, id), \ + SRIDFVL(VPMPCC_MCM_SHAPER_RAMA_REGION_16_17, VPMPCC_MCM, id), \ + SRIDFVL(VPMPCC_MCM_SHAPER_RAMA_REGION_18_19, VPMPCC_MCM, id), \ + SRIDFVL(VPMPCC_MCM_SHAPER_RAMA_REGION_20_21, VPMPCC_MCM, id), \ + SRIDFVL(VPMPCC_MCM_SHAPER_RAMA_REGION_22_23, VPMPCC_MCM, id), \ + SRIDFVL(VPMPCC_MCM_SHAPER_RAMA_REGION_24_25, VPMPCC_MCM, id), \ + SRIDFVL(VPMPCC_MCM_SHAPER_RAMA_REGION_26_27, VPMPCC_MCM, id), \ + SRIDFVL(VPMPCC_MCM_SHAPER_RAMA_REGION_28_29, VPMPCC_MCM, id), \ + SRIDFVL(VPMPCC_MCM_SHAPER_RAMA_REGION_30_31, VPMPCC_MCM, id), \ + SRIDFVL(VPMPCC_MCM_SHAPER_RAMA_REGION_32_33, VPMPCC_MCM, id), \ + SRIDFVL(VPMPCC_MCM_3DLUT_MODE, VPMPCC_MCM, id), \ + SRIDFVL(VPMPCC_MCM_3DLUT_INDEX, VPMPCC_MCM, id), \ + SRIDFVL(VPMPCC_MCM_3DLUT_DATA, VPMPCC_MCM, id), \ + SRIDFVL(VPMPCC_MCM_3DLUT_DATA_30BIT, VPMPCC_MCM, id), \ + SRIDFVL(VPMPCC_MCM_3DLUT_READ_WRITE_CONTROL, VPMPCC_MCM, id), \ + SRIDFVL(VPMPCC_MCM_3DLUT_OUT_NORM_FACTOR, VPMPCC_MCM, id), \ + SRIDFVL(VPMPCC_MCM_3DLUT_OUT_OFFSET_R, VPMPCC_MCM, id), \ + SRIDFVL(VPMPCC_MCM_3DLUT_OUT_OFFSET_G, VPMPCC_MCM, id), \ + SRIDFVL(VPMPCC_MCM_3DLUT_OUT_OFFSET_B, VPMPCC_MCM, id), \ + SRIDFVL(VPMPCC_MCM_1DLUT_CONTROL, VPMPCC_MCM, id), \ + SRIDFVL(VPMPCC_MCM_1DLUT_LUT_INDEX, VPMPCC_MCM, id), \ + SRIDFVL(VPMPCC_MCM_1DLUT_LUT_DATA, VPMPCC_MCM, id), \ + SRIDFVL(VPMPCC_MCM_1DLUT_LUT_CONTROL, VPMPCC_MCM, id), \ + SRIDFVL(VPMPCC_MCM_1DLUT_RAMA_START_CNTL_B, VPMPCC_MCM, id), \ + SRIDFVL(VPMPCC_MCM_1DLUT_RAMA_START_CNTL_G, VPMPCC_MCM, id), \ + SRIDFVL(VPMPCC_MCM_1DLUT_RAMA_START_CNTL_R, VPMPCC_MCM, id), \ + SRIDFVL(VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B, VPMPCC_MCM, id), \ + SRIDFVL(VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G, VPMPCC_MCM, id), \ + SRIDFVL(VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R, VPMPCC_MCM, id), \ + SRIDFVL(VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B, VPMPCC_MCM, id), \ + SRIDFVL(VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G, VPMPCC_MCM, id), \ + SRIDFVL(VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R, VPMPCC_MCM, id), \ + SRIDFVL(VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_B, VPMPCC_MCM, id), \ + SRIDFVL(VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_B, VPMPCC_MCM, id), \ + SRIDFVL(VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_G, VPMPCC_MCM, id), \ + SRIDFVL(VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_G, VPMPCC_MCM, id), \ + SRIDFVL(VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_R, VPMPCC_MCM, id), \ + SRIDFVL(VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_R, VPMPCC_MCM, id), \ + SRIDFVL(VPMPCC_MCM_1DLUT_RAMA_OFFSET_B, VPMPCC_MCM, id), \ + SRIDFVL(VPMPCC_MCM_1DLUT_RAMA_OFFSET_G, VPMPCC_MCM, id), \ + SRIDFVL(VPMPCC_MCM_1DLUT_RAMA_OFFSET_R, VPMPCC_MCM, id), \ + SRIDFVL(VPMPCC_MCM_1DLUT_RAMA_REGION_0_1, VPMPCC_MCM, id), \ + SRIDFVL(VPMPCC_MCM_1DLUT_RAMA_REGION_2_3, VPMPCC_MCM, id), \ + SRIDFVL(VPMPCC_MCM_1DLUT_RAMA_REGION_4_5, VPMPCC_MCM, id), \ + SRIDFVL(VPMPCC_MCM_1DLUT_RAMA_REGION_6_7, VPMPCC_MCM, id), \ + SRIDFVL(VPMPCC_MCM_1DLUT_RAMA_REGION_8_9, VPMPCC_MCM, id), \ + SRIDFVL(VPMPCC_MCM_1DLUT_RAMA_REGION_10_11, VPMPCC_MCM, id), \ + SRIDFVL(VPMPCC_MCM_1DLUT_RAMA_REGION_12_13, VPMPCC_MCM, id), \ + SRIDFVL(VPMPCC_MCM_1DLUT_RAMA_REGION_14_15, VPMPCC_MCM, id), \ + SRIDFVL(VPMPCC_MCM_1DLUT_RAMA_REGION_16_17, VPMPCC_MCM, id), \ + SRIDFVL(VPMPCC_MCM_1DLUT_RAMA_REGION_18_19, VPMPCC_MCM, id), \ + SRIDFVL(VPMPCC_MCM_1DLUT_RAMA_REGION_20_21, VPMPCC_MCM, id), \ + SRIDFVL(VPMPCC_MCM_1DLUT_RAMA_REGION_22_23, VPMPCC_MCM, id), \ + SRIDFVL(VPMPCC_MCM_1DLUT_RAMA_REGION_24_25, VPMPCC_MCM, id), \ + SRIDFVL(VPMPCC_MCM_1DLUT_RAMA_REGION_26_27, VPMPCC_MCM, id), \ + SRIDFVL(VPMPCC_MCM_1DLUT_RAMA_REGION_28_29, VPMPCC_MCM, id), \ + SRIDFVL(VPMPCC_MCM_1DLUT_RAMA_REGION_30_31, VPMPCC_MCM, id), \ + SRIDFVL(VPMPCC_MCM_1DLUT_RAMA_REGION_32_33, VPMPCC_MCM, id), \ + SRIDFVL(VPMPCC_MCM_MEM_PWR_CTRL, VPMPCC_MCM, id), + +#define MPC_FIELD_LIST_VPE10(post_fix) \ + SFRB(VPECLK_R_GATE_DISABLE, VPMPC_CLOCK_CONTROL, post_fix), \ + SFRB(VPMPC_TEST_CLK_SEL, VPMPC_CLOCK_CONTROL, post_fix), \ + SFRB(VPMPCC0_SOFT_RESET, VPMPC_SOFT_RESET, post_fix), \ + SFRB(VPMPC_SFR0_SOFT_RESET, VPMPC_SOFT_RESET, post_fix), \ + SFRB(VPMPC_SFT0_SOFT_RESET, VPMPC_SOFT_RESET, post_fix), \ + SFRB(VPMPC_SOFT_RESET, VPMPC_SOFT_RESET, post_fix), \ + SFRB(VPMPC_CRC_EN, VPMPC_CRC_CTRL, post_fix), \ + SFRB(VPMPC_CRC_CONT_EN, VPMPC_CRC_CTRL, post_fix), \ + SFRB(VPMPC_CRC_SRC_SEL, VPMPC_CRC_CTRL, post_fix), \ + SFRB(VPMPC_CRC_ONE_SHOT_PENDING, VPMPC_CRC_CTRL, post_fix), \ + SFRB(VPMPC_CRC_UPDATE_ENABLED, VPMPC_CRC_CTRL, post_fix), \ + SFRB(VPMPC_CRC_UPDATE_LOCK, VPMPC_CRC_CTRL, post_fix), \ + SFRB(VPMPC_CRC_VPDPP_SEL, VPMPC_CRC_SEL_CONTROL, post_fix), \ + SFRB(VPMPC_CRC_VPOPP_SEL, VPMPC_CRC_SEL_CONTROL, post_fix), \ + SFRB(VPMPC_CRC_MASK, VPMPC_CRC_SEL_CONTROL, post_fix), \ + SFRB(VPMPC_CRC_RESULT_A, VPMPC_CRC_RESULT_AR, post_fix), \ + SFRB(VPMPC_CRC_RESULT_R, VPMPC_CRC_RESULT_AR, post_fix), \ + SFRB(VPMPC_CRC_RESULT_G, VPMPC_CRC_RESULT_GB, post_fix), \ + SFRB(VPMPC_CRC_RESULT_B, VPMPC_CRC_RESULT_GB, post_fix), \ + SFRB(VPMPC_CRC_RESULT_C, VPMPC_CRC_RESULT_C, post_fix), \ + SFRB(VPMPC_BYPASS_BG_ALPHA, VPMPC_BYPASS_BG_AR, post_fix), \ + SFRB(VPMPC_BYPASS_BG_R_CR, VPMPC_BYPASS_BG_AR, post_fix), \ + SFRB(VPMPC_BYPASS_BG_G_Y, VPMPC_BYPASS_BG_GB, post_fix), \ + SFRB(VPMPC_BYPASS_BG_B_CB, VPMPC_BYPASS_BG_GB, post_fix), \ + SFRB(HOST_READ_RATE_CONTROL, VPMPC_HOST_READ_CONTROL, post_fix), \ + SFRB(VPMPCC0_CONFIG_UPDATE_PENDING, VPMPC_PENDING_STATUS_MISC, post_fix), \ + SFRB(VPMPC_OUT_MUX, VPMPC_OUT0_MUX, post_fix), \ + SFRB(VPMPC_OUT_FLOAT_EN, VPMPC_OUT0_FLOAT_CONTROL, post_fix), \ + SFRB(VPMPC_OUT_DENORM_CLAMP_MIN_R_CR, VPMPC_OUT0_DENORM_CONTROL, post_fix), \ + SFRB(VPMPC_OUT_DENORM_CLAMP_MAX_R_CR, VPMPC_OUT0_DENORM_CONTROL, post_fix), \ + SFRB(VPMPC_OUT_DENORM_MODE, VPMPC_OUT0_DENORM_CONTROL, post_fix), \ + SFRB(VPMPC_OUT_DENORM_CLAMP_MIN_G_Y, VPMPC_OUT0_DENORM_CLAMP_G_Y, post_fix), \ + SFRB(VPMPC_OUT_DENORM_CLAMP_MAX_G_Y, VPMPC_OUT0_DENORM_CLAMP_G_Y, post_fix), \ + SFRB(VPMPC_OUT_DENORM_CLAMP_MIN_B_CB, VPMPC_OUT0_DENORM_CLAMP_B_CB, post_fix), \ + SFRB(VPMPC_OUT_DENORM_CLAMP_MAX_B_CB, VPMPC_OUT0_DENORM_CLAMP_B_CB, post_fix), \ + SFRB(VPMPC_OCSC0_COEF_FORMAT, VPMPC_OUT_CSC_COEF_FORMAT, post_fix), \ + SFRB(VPMPC_OCSC_MODE, VPMPC_OUT0_CSC_MODE, post_fix), \ + SFRB(VPMPC_OCSC_MODE_CURRENT, VPMPC_OUT0_CSC_MODE, post_fix), \ + SFRB(VPMPC_OCSC_C11_A, VPMPC_OUT0_CSC_C11_C12_A, post_fix), \ + SFRB(VPMPC_OCSC_C12_A, VPMPC_OUT0_CSC_C11_C12_A, post_fix), \ + SFRB(VPMPC_OCSC_C13_A, VPMPC_OUT0_CSC_C13_C14_A, post_fix), \ + SFRB(VPMPC_OCSC_C14_A, VPMPC_OUT0_CSC_C13_C14_A, post_fix), \ + SFRB(VPMPC_OCSC_C21_A, VPMPC_OUT0_CSC_C21_C22_A, post_fix), \ + SFRB(VPMPC_OCSC_C22_A, VPMPC_OUT0_CSC_C21_C22_A, post_fix), \ + SFRB(VPMPC_OCSC_C23_A, VPMPC_OUT0_CSC_C23_C24_A, post_fix), \ + SFRB(VPMPC_OCSC_C24_A, VPMPC_OUT0_CSC_C23_C24_A, post_fix), \ + SFRB(VPMPC_OCSC_C31_A, VPMPC_OUT0_CSC_C31_C32_A, post_fix), \ + SFRB(VPMPC_OCSC_C32_A, VPMPC_OUT0_CSC_C31_C32_A, post_fix), \ + SFRB(VPMPC_OCSC_C33_A, VPMPC_OUT0_CSC_C33_C34_A, post_fix), \ + SFRB(VPMPC_OCSC_C34_A, VPMPC_OUT0_CSC_C33_C34_A, post_fix), \ + SFRB(VPMPCC_TOP_SEL, VPMPCC_TOP_SEL, post_fix), \ + SFRB(VPMPCC_BOT_SEL, VPMPCC_BOT_SEL, post_fix), \ + SFRB(VPMPCC_VPOPP_ID, VPMPCC_VPOPP_ID, post_fix), \ + SFRB(VPMPCC_MODE, VPMPCC_CONTROL, post_fix), \ + SFRB(VPMPCC_ALPHA_BLND_MODE, VPMPCC_CONTROL, post_fix), \ + SFRB(VPMPCC_ALPHA_MULTIPLIED_MODE, VPMPCC_CONTROL, post_fix), \ + SFRB(VPMPCC_BLND_ACTIVE_OVERLAP_ONLY, VPMPCC_CONTROL, post_fix), \ + SFRB(VPMPCC_BG_BPC, VPMPCC_CONTROL, post_fix), \ + SFRB(VPMPCC_BOT_GAIN_MODE, VPMPCC_CONTROL, post_fix), \ + SFRB(VPMPCC_GLOBAL_ALPHA, VPMPCC_CONTROL, post_fix), \ + SFRB(VPMPCC_GLOBAL_GAIN, VPMPCC_CONTROL, post_fix), \ + SFRB(VPMPCC_TOP_GAIN, VPMPCC_TOP_GAIN, post_fix), \ + SFRB(VPMPCC_BOT_GAIN_INSIDE, VPMPCC_BOT_GAIN_INSIDE, post_fix), \ + SFRB(VPMPCC_BOT_GAIN_OUTSIDE, VPMPCC_BOT_GAIN_OUTSIDE, post_fix), \ + SFRB(VPMPCC_MOVABLE_CM_LOCATION_CNTL, VPMPCC_MOVABLE_CM_LOCATION_CONTROL, post_fix), \ + SFRB(VPMPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT, VPMPCC_MOVABLE_CM_LOCATION_CONTROL, \ + post_fix), \ + SFRB(VPMPCC_BG_R_CR, VPMPCC_BG_R_CR, post_fix), \ + SFRB(VPMPCC_BG_G_Y, VPMPCC_BG_G_Y, post_fix), \ + SFRB(VPMPCC_BG_B_CB, VPMPCC_BG_B_CB, post_fix), \ + SFRB(VPMPCC_OGAM_MEM_PWR_FORCE, VPMPCC_MEM_PWR_CTRL, post_fix), \ + SFRB(VPMPCC_OGAM_MEM_PWR_DIS, VPMPCC_MEM_PWR_CTRL, post_fix), \ + SFRB(VPMPCC_OGAM_MEM_LOW_PWR_MODE, VPMPCC_MEM_PWR_CTRL, post_fix), \ + SFRB(VPMPCC_OGAM_MEM_PWR_STATE, VPMPCC_MEM_PWR_CTRL, post_fix), \ + SFRB(VPMPCC_IDLE, VPMPCC_STATUS, post_fix), SFRB(VPMPCC_BUSY, VPMPCC_STATUS, post_fix), \ + SFRB(VPMPCC_DISABLED, VPMPCC_STATUS, post_fix), \ + SFRB(VPMPCC_OGAM_MODE, VPMPCC_OGAM_CONTROL, post_fix), \ + SFRB(VPMPCC_OGAM_PWL_DISABLE, VPMPCC_OGAM_CONTROL, post_fix), \ + SFRB(VPMPCC_OGAM_MODE_CURRENT, VPMPCC_OGAM_CONTROL, post_fix), \ + SFRB(VPMPCC_OGAM_SELECT_CURRENT, VPMPCC_OGAM_CONTROL, post_fix), \ + SFRB(VPMPCC_OGAM_LUT_INDEX, VPMPCC_OGAM_LUT_INDEX, post_fix), \ + SFRB(VPMPCC_OGAM_LUT_DATA, VPMPCC_OGAM_LUT_DATA, post_fix), \ + SFRB(VPMPCC_OGAM_LUT_WRITE_COLOR_MASK, VPMPCC_OGAM_LUT_CONTROL, post_fix), \ + SFRB(VPMPCC_OGAM_LUT_READ_COLOR_SEL, VPMPCC_OGAM_LUT_CONTROL, post_fix), \ + SFRB(VPMPCC_OGAM_LUT_READ_DBG, VPMPCC_OGAM_LUT_CONTROL, post_fix), \ + SFRB(VPMPCC_OGAM_LUT_HOST_SEL, VPMPCC_OGAM_LUT_CONTROL, post_fix), \ + SFRB(VPMPCC_OGAM_LUT_CONFIG_MODE, VPMPCC_OGAM_LUT_CONTROL, post_fix), \ + SFRB(VPMPCC_OGAM_RAMA_EXP_REGION_START_B, VPMPCC_OGAM_RAMA_START_CNTL_B, post_fix), \ + SFRB( \ + VPMPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B, VPMPCC_OGAM_RAMA_START_CNTL_B, post_fix), \ + SFRB(VPMPCC_OGAM_RAMA_EXP_REGION_START_G, VPMPCC_OGAM_RAMA_START_CNTL_G, post_fix), \ + SFRB( \ + VPMPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G, VPMPCC_OGAM_RAMA_START_CNTL_G, post_fix), \ + SFRB(VPMPCC_OGAM_RAMA_EXP_REGION_START_R, VPMPCC_OGAM_RAMA_START_CNTL_R, post_fix), \ + SFRB( \ + VPMPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R, VPMPCC_OGAM_RAMA_START_CNTL_R, post_fix), \ + SFRB(VPMPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B, VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_B, \ + post_fix), \ + SFRB(VPMPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G, VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_G, \ + post_fix), \ + SFRB(VPMPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R, VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_R, \ + post_fix), \ + SFRB(VPMPCC_OGAM_RAMA_EXP_REGION_START_BASE_B, VPMPCC_OGAM_RAMA_START_BASE_CNTL_B, \ + post_fix), \ + SFRB(VPMPCC_OGAM_RAMA_EXP_REGION_START_BASE_G, VPMPCC_OGAM_RAMA_START_BASE_CNTL_G, \ + post_fix), \ + SFRB(VPMPCC_OGAM_RAMA_EXP_REGION_START_BASE_R, VPMPCC_OGAM_RAMA_START_BASE_CNTL_R, \ + post_fix), \ + SFRB(VPMPCC_OGAM_RAMA_EXP_REGION_END_BASE_B, VPMPCC_OGAM_RAMA_END_CNTL1_B, post_fix), \ + SFRB(VPMPCC_OGAM_RAMA_EXP_REGION_END_B, VPMPCC_OGAM_RAMA_END_CNTL2_B, post_fix), \ + SFRB(VPMPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B, VPMPCC_OGAM_RAMA_END_CNTL2_B, post_fix), \ + SFRB(VPMPCC_OGAM_RAMA_EXP_REGION_END_BASE_G, VPMPCC_OGAM_RAMA_END_CNTL1_G, post_fix), \ + SFRB(VPMPCC_OGAM_RAMA_EXP_REGION_END_G, VPMPCC_OGAM_RAMA_END_CNTL2_G, post_fix), \ + SFRB(VPMPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G, VPMPCC_OGAM_RAMA_END_CNTL2_G, post_fix), \ + SFRB(VPMPCC_OGAM_RAMA_EXP_REGION_END_BASE_R, VPMPCC_OGAM_RAMA_END_CNTL1_R, post_fix), \ + SFRB(VPMPCC_OGAM_RAMA_EXP_REGION_END_R, VPMPCC_OGAM_RAMA_END_CNTL2_R, post_fix), \ + SFRB(VPMPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R, VPMPCC_OGAM_RAMA_END_CNTL2_R, post_fix), \ + SFRB(VPMPCC_OGAM_RAMA_OFFSET_B, VPMPCC_OGAM_RAMA_OFFSET_B, post_fix), \ + SFRB(VPMPCC_OGAM_RAMA_OFFSET_G, VPMPCC_OGAM_RAMA_OFFSET_G, post_fix), \ + SFRB(VPMPCC_OGAM_RAMA_OFFSET_R, VPMPCC_OGAM_RAMA_OFFSET_R, post_fix), \ + SFRB(VPMPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET, VPMPCC_OGAM_RAMA_REGION_0_1, post_fix), \ + SFRB(VPMPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS, VPMPCC_OGAM_RAMA_REGION_0_1, post_fix), \ + SFRB(VPMPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET, VPMPCC_OGAM_RAMA_REGION_0_1, post_fix), \ + SFRB(VPMPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS, VPMPCC_OGAM_RAMA_REGION_0_1, post_fix), \ + SFRB(VPMPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET, VPMPCC_OGAM_RAMA_REGION_2_3, post_fix), \ + SFRB(VPMPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS, VPMPCC_OGAM_RAMA_REGION_2_3, post_fix), \ + SFRB(VPMPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET, VPMPCC_OGAM_RAMA_REGION_2_3, post_fix), \ + SFRB(VPMPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS, VPMPCC_OGAM_RAMA_REGION_2_3, post_fix), \ + SFRB(VPMPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET, VPMPCC_OGAM_RAMA_REGION_4_5, post_fix), \ + SFRB(VPMPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS, VPMPCC_OGAM_RAMA_REGION_4_5, post_fix), \ + SFRB(VPMPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET, VPMPCC_OGAM_RAMA_REGION_4_5, post_fix), \ + SFRB(VPMPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS, VPMPCC_OGAM_RAMA_REGION_4_5, post_fix), \ + SFRB(VPMPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET, VPMPCC_OGAM_RAMA_REGION_6_7, post_fix), \ + SFRB(VPMPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS, VPMPCC_OGAM_RAMA_REGION_6_7, post_fix), \ + SFRB(VPMPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET, VPMPCC_OGAM_RAMA_REGION_6_7, post_fix), \ + SFRB(VPMPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS, VPMPCC_OGAM_RAMA_REGION_6_7, post_fix), \ + SFRB(VPMPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET, VPMPCC_OGAM_RAMA_REGION_8_9, post_fix), \ + SFRB(VPMPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS, VPMPCC_OGAM_RAMA_REGION_8_9, post_fix), \ + SFRB(VPMPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET, VPMPCC_OGAM_RAMA_REGION_8_9, post_fix), \ + SFRB(VPMPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS, VPMPCC_OGAM_RAMA_REGION_8_9, post_fix), \ + SFRB(VPMPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET, VPMPCC_OGAM_RAMA_REGION_10_11, post_fix), \ + SFRB(VPMPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS, VPMPCC_OGAM_RAMA_REGION_10_11, post_fix), \ + SFRB(VPMPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET, VPMPCC_OGAM_RAMA_REGION_10_11, post_fix), \ + SFRB(VPMPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS, VPMPCC_OGAM_RAMA_REGION_10_11, post_fix), \ + SFRB(VPMPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET, VPMPCC_OGAM_RAMA_REGION_12_13, post_fix), \ + SFRB(VPMPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS, VPMPCC_OGAM_RAMA_REGION_12_13, post_fix), \ + SFRB(VPMPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET, VPMPCC_OGAM_RAMA_REGION_12_13, post_fix), \ + SFRB(VPMPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS, VPMPCC_OGAM_RAMA_REGION_12_13, post_fix), \ + SFRB(VPMPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET, VPMPCC_OGAM_RAMA_REGION_14_15, post_fix), \ + SFRB(VPMPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS, VPMPCC_OGAM_RAMA_REGION_14_15, post_fix), \ + SFRB(VPMPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET, VPMPCC_OGAM_RAMA_REGION_14_15, post_fix), \ + SFRB(VPMPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS, VPMPCC_OGAM_RAMA_REGION_14_15, post_fix), \ + SFRB(VPMPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET, VPMPCC_OGAM_RAMA_REGION_16_17, post_fix), \ + SFRB(VPMPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS, VPMPCC_OGAM_RAMA_REGION_16_17, post_fix), \ + SFRB(VPMPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET, VPMPCC_OGAM_RAMA_REGION_16_17, post_fix), \ + SFRB(VPMPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS, VPMPCC_OGAM_RAMA_REGION_16_17, post_fix), \ + SFRB(VPMPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET, VPMPCC_OGAM_RAMA_REGION_18_19, post_fix), \ + SFRB(VPMPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS, VPMPCC_OGAM_RAMA_REGION_18_19, post_fix), \ + SFRB(VPMPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET, VPMPCC_OGAM_RAMA_REGION_18_19, post_fix), \ + SFRB(VPMPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS, VPMPCC_OGAM_RAMA_REGION_18_19, post_fix), \ + SFRB(VPMPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET, VPMPCC_OGAM_RAMA_REGION_20_21, post_fix), \ + SFRB(VPMPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS, VPMPCC_OGAM_RAMA_REGION_20_21, post_fix), \ + SFRB(VPMPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET, VPMPCC_OGAM_RAMA_REGION_20_21, post_fix), \ + SFRB(VPMPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS, VPMPCC_OGAM_RAMA_REGION_20_21, post_fix), \ + SFRB(VPMPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET, VPMPCC_OGAM_RAMA_REGION_22_23, post_fix), \ + SFRB(VPMPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS, VPMPCC_OGAM_RAMA_REGION_22_23, post_fix), \ + SFRB(VPMPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET, VPMPCC_OGAM_RAMA_REGION_22_23, post_fix), \ + SFRB(VPMPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS, VPMPCC_OGAM_RAMA_REGION_22_23, post_fix), \ + SFRB(VPMPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET, VPMPCC_OGAM_RAMA_REGION_24_25, post_fix), \ + SFRB(VPMPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS, VPMPCC_OGAM_RAMA_REGION_24_25, post_fix), \ + SFRB(VPMPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET, VPMPCC_OGAM_RAMA_REGION_24_25, post_fix), \ + SFRB(VPMPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS, VPMPCC_OGAM_RAMA_REGION_24_25, post_fix), \ + SFRB(VPMPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET, VPMPCC_OGAM_RAMA_REGION_26_27, post_fix), \ + SFRB(VPMPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS, VPMPCC_OGAM_RAMA_REGION_26_27, post_fix), \ + SFRB(VPMPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET, VPMPCC_OGAM_RAMA_REGION_26_27, post_fix), \ + SFRB(VPMPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS, VPMPCC_OGAM_RAMA_REGION_26_27, post_fix), \ + SFRB(VPMPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET, VPMPCC_OGAM_RAMA_REGION_28_29, post_fix), \ + SFRB(VPMPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS, VPMPCC_OGAM_RAMA_REGION_28_29, post_fix), \ + SFRB(VPMPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET, VPMPCC_OGAM_RAMA_REGION_28_29, post_fix), \ + SFRB(VPMPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS, VPMPCC_OGAM_RAMA_REGION_28_29, post_fix), \ + SFRB(VPMPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET, VPMPCC_OGAM_RAMA_REGION_30_31, post_fix), \ + SFRB(VPMPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS, VPMPCC_OGAM_RAMA_REGION_30_31, post_fix), \ + SFRB(VPMPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET, VPMPCC_OGAM_RAMA_REGION_30_31, post_fix), \ + SFRB(VPMPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS, VPMPCC_OGAM_RAMA_REGION_30_31, post_fix), \ + SFRB(VPMPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET, VPMPCC_OGAM_RAMA_REGION_32_33, post_fix), \ + SFRB(VPMPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS, VPMPCC_OGAM_RAMA_REGION_32_33, post_fix), \ + SFRB(VPMPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET, VPMPCC_OGAM_RAMA_REGION_32_33, post_fix), \ + SFRB(VPMPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS, VPMPCC_OGAM_RAMA_REGION_32_33, post_fix), \ + SFRB(VPMPCC_GAMUT_REMAP_COEF_FORMAT, VPMPCC_GAMUT_REMAP_COEF_FORMAT, post_fix), \ + SFRB(VPMPCC_GAMUT_REMAP_MODE, VPMPCC_GAMUT_REMAP_MODE, post_fix), \ + SFRB(VPMPCC_GAMUT_REMAP_MODE_CURRENT, VPMPCC_GAMUT_REMAP_MODE, post_fix), \ + SFRB(VPMPCC_GAMUT_REMAP_C11_A, VPMPC_GAMUT_REMAP_C11_C12_A, post_fix), \ + SFRB(VPMPCC_GAMUT_REMAP_C12_A, VPMPC_GAMUT_REMAP_C11_C12_A, post_fix), \ + SFRB(VPMPCC_GAMUT_REMAP_C13_A, VPMPC_GAMUT_REMAP_C13_C14_A, post_fix), \ + SFRB(VPMPCC_GAMUT_REMAP_C14_A, VPMPC_GAMUT_REMAP_C13_C14_A, post_fix), \ + SFRB(VPMPCC_GAMUT_REMAP_C21_A, VPMPC_GAMUT_REMAP_C21_C22_A, post_fix), \ + SFRB(VPMPCC_GAMUT_REMAP_C22_A, VPMPC_GAMUT_REMAP_C21_C22_A, post_fix), \ + SFRB(VPMPCC_GAMUT_REMAP_C23_A, VPMPC_GAMUT_REMAP_C23_C24_A, post_fix), \ + SFRB(VPMPCC_GAMUT_REMAP_C24_A, VPMPC_GAMUT_REMAP_C23_C24_A, post_fix), \ + SFRB(VPMPCC_GAMUT_REMAP_C31_A, VPMPC_GAMUT_REMAP_C31_C32_A, post_fix), \ + SFRB(VPMPCC_GAMUT_REMAP_C32_A, VPMPC_GAMUT_REMAP_C31_C32_A, post_fix), \ + SFRB(VPMPCC_GAMUT_REMAP_C33_A, VPMPC_GAMUT_REMAP_C33_C34_A, post_fix), \ + SFRB(VPMPCC_GAMUT_REMAP_C34_A, VPMPC_GAMUT_REMAP_C33_C34_A, post_fix), \ + SFRB(VPMPCC_MCM_SHAPER_LUT_MODE, VPMPCC_MCM_SHAPER_CONTROL, post_fix), \ + SFRB(VPMPCC_MCM_SHAPER_MODE_CURRENT, VPMPCC_MCM_SHAPER_CONTROL, post_fix), \ + SFRB(VPMPCC_MCM_SHAPER_SELECT_CURRENT, VPMPCC_MCM_SHAPER_CONTROL, post_fix), \ + SFRB(VPMPCC_MCM_SHAPER_OFFSET_R, VPMPCC_MCM_SHAPER_OFFSET_R, post_fix), \ + SFRB(VPMPCC_MCM_SHAPER_OFFSET_G, VPMPCC_MCM_SHAPER_OFFSET_G, post_fix), \ + SFRB(VPMPCC_MCM_SHAPER_OFFSET_B, VPMPCC_MCM_SHAPER_OFFSET_B, post_fix), \ + SFRB(VPMPCC_MCM_SHAPER_SCALE_R, VPMPCC_MCM_SHAPER_SCALE_R, post_fix), \ + SFRB(VPMPCC_MCM_SHAPER_SCALE_G, VPMPCC_MCM_SHAPER_SCALE_G_B, post_fix), \ + SFRB(VPMPCC_MCM_SHAPER_SCALE_B, VPMPCC_MCM_SHAPER_SCALE_G_B, post_fix), \ + SFRB(VPMPCC_MCM_SHAPER_LUT_INDEX, VPMPCC_MCM_SHAPER_LUT_INDEX, post_fix), \ + SFRB(VPMPCC_MCM_SHAPER_LUT_DATA, VPMPCC_MCM_SHAPER_LUT_DATA, post_fix), \ + SFRB(VPMPCC_MCM_SHAPER_LUT_WRITE_EN_MASK, VPMPCC_MCM_SHAPER_LUT_WRITE_EN_MASK, post_fix), \ + SFRB(VPMPCC_MCM_SHAPER_LUT_WRITE_SEL, VPMPCC_MCM_SHAPER_LUT_WRITE_EN_MASK, post_fix), \ + SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B, VPMPCC_MCM_SHAPER_RAMA_START_CNTL_B, \ + post_fix), \ + SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, \ + VPMPCC_MCM_SHAPER_RAMA_START_CNTL_B, post_fix), \ + SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_START_G, VPMPCC_MCM_SHAPER_RAMA_START_CNTL_G, \ + post_fix), \ + SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G, \ + VPMPCC_MCM_SHAPER_RAMA_START_CNTL_G, post_fix), \ + SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_START_R, VPMPCC_MCM_SHAPER_RAMA_START_CNTL_R, \ + post_fix), \ + SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R, \ + VPMPCC_MCM_SHAPER_RAMA_START_CNTL_R, post_fix), \ + SFRB( \ + VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B, VPMPCC_MCM_SHAPER_RAMA_END_CNTL_B, post_fix), \ + SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B, VPMPCC_MCM_SHAPER_RAMA_END_CNTL_B, \ + post_fix), \ + SFRB( \ + VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_END_G, VPMPCC_MCM_SHAPER_RAMA_END_CNTL_G, post_fix), \ + SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_G, VPMPCC_MCM_SHAPER_RAMA_END_CNTL_G, \ + post_fix), \ + SFRB( \ + VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_END_R, VPMPCC_MCM_SHAPER_RAMA_END_CNTL_R, post_fix), \ + SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_R, VPMPCC_MCM_SHAPER_RAMA_END_CNTL_R, \ + post_fix), \ + SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, VPMPCC_MCM_SHAPER_RAMA_REGION_0_1, \ + post_fix), \ + SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, VPMPCC_MCM_SHAPER_RAMA_REGION_0_1, \ + post_fix), \ + SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, VPMPCC_MCM_SHAPER_RAMA_REGION_0_1, \ + post_fix), \ + SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, VPMPCC_MCM_SHAPER_RAMA_REGION_0_1, \ + post_fix), \ + SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET, VPMPCC_MCM_SHAPER_RAMA_REGION_2_3, \ + post_fix), \ + SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS, VPMPCC_MCM_SHAPER_RAMA_REGION_2_3, \ + post_fix), \ + SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET, VPMPCC_MCM_SHAPER_RAMA_REGION_2_3, \ + post_fix), \ + SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS, VPMPCC_MCM_SHAPER_RAMA_REGION_2_3, \ + post_fix), \ + SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET, VPMPCC_MCM_SHAPER_RAMA_REGION_4_5, \ + post_fix), \ + SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS, VPMPCC_MCM_SHAPER_RAMA_REGION_4_5, \ + post_fix), \ + SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET, VPMPCC_MCM_SHAPER_RAMA_REGION_4_5, \ + post_fix), \ + SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS, VPMPCC_MCM_SHAPER_RAMA_REGION_4_5, \ + post_fix), \ + SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET, VPMPCC_MCM_SHAPER_RAMA_REGION_6_7, \ + post_fix), \ + SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS, VPMPCC_MCM_SHAPER_RAMA_REGION_6_7, \ + post_fix), \ + SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET, VPMPCC_MCM_SHAPER_RAMA_REGION_6_7, \ + post_fix), \ + SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS, VPMPCC_MCM_SHAPER_RAMA_REGION_6_7, \ + post_fix), \ + SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET, VPMPCC_MCM_SHAPER_RAMA_REGION_8_9, \ + post_fix), \ + SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS, VPMPCC_MCM_SHAPER_RAMA_REGION_8_9, \ + post_fix), \ + SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET, VPMPCC_MCM_SHAPER_RAMA_REGION_8_9, \ + post_fix), \ + SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS, VPMPCC_MCM_SHAPER_RAMA_REGION_8_9, \ + post_fix), \ + SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET, VPMPCC_MCM_SHAPER_RAMA_REGION_10_11, \ + post_fix), \ + SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS, \ + VPMPCC_MCM_SHAPER_RAMA_REGION_10_11, post_fix), \ + SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET, VPMPCC_MCM_SHAPER_RAMA_REGION_10_11, \ + post_fix), \ + SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS, \ + VPMPCC_MCM_SHAPER_RAMA_REGION_10_11, post_fix), \ + SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET, VPMPCC_MCM_SHAPER_RAMA_REGION_12_13, \ + post_fix), \ + SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS, \ + VPMPCC_MCM_SHAPER_RAMA_REGION_12_13, post_fix), \ + SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET, VPMPCC_MCM_SHAPER_RAMA_REGION_12_13, \ + post_fix), \ + SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS, \ + VPMPCC_MCM_SHAPER_RAMA_REGION_12_13, post_fix), \ + SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET, VPMPCC_MCM_SHAPER_RAMA_REGION_14_15, \ + post_fix), \ + SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS, \ + VPMPCC_MCM_SHAPER_RAMA_REGION_14_15, post_fix), \ + SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET, VPMPCC_MCM_SHAPER_RAMA_REGION_14_15, \ + post_fix), \ + SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS, \ + VPMPCC_MCM_SHAPER_RAMA_REGION_14_15, post_fix), \ + SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET, VPMPCC_MCM_SHAPER_RAMA_REGION_16_17, \ + post_fix), \ + SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS, \ + VPMPCC_MCM_SHAPER_RAMA_REGION_16_17, post_fix), \ + SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET, VPMPCC_MCM_SHAPER_RAMA_REGION_16_17, \ + post_fix), \ + SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS, \ + VPMPCC_MCM_SHAPER_RAMA_REGION_16_17, post_fix), \ + SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET, VPMPCC_MCM_SHAPER_RAMA_REGION_18_19, \ + post_fix), \ + SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS, \ + VPMPCC_MCM_SHAPER_RAMA_REGION_18_19, post_fix), \ + SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET, VPMPCC_MCM_SHAPER_RAMA_REGION_18_19, \ + post_fix), \ + SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS, \ + VPMPCC_MCM_SHAPER_RAMA_REGION_18_19, post_fix), \ + SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET, VPMPCC_MCM_SHAPER_RAMA_REGION_20_21, \ + post_fix), \ + SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS, \ + VPMPCC_MCM_SHAPER_RAMA_REGION_20_21, post_fix), \ + SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET, VPMPCC_MCM_SHAPER_RAMA_REGION_20_21, \ + post_fix), \ + SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS, \ + VPMPCC_MCM_SHAPER_RAMA_REGION_20_21, post_fix), \ + SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET, VPMPCC_MCM_SHAPER_RAMA_REGION_22_23, \ + post_fix), \ + SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS, \ + VPMPCC_MCM_SHAPER_RAMA_REGION_22_23, post_fix), \ + SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET, VPMPCC_MCM_SHAPER_RAMA_REGION_22_23, \ + post_fix), \ + SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS, \ + VPMPCC_MCM_SHAPER_RAMA_REGION_22_23, post_fix), \ + SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET, VPMPCC_MCM_SHAPER_RAMA_REGION_24_25, \ + post_fix), \ + SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS, \ + VPMPCC_MCM_SHAPER_RAMA_REGION_24_25, post_fix), \ + SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET, VPMPCC_MCM_SHAPER_RAMA_REGION_24_25, \ + post_fix), \ + SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS, \ + VPMPCC_MCM_SHAPER_RAMA_REGION_24_25, post_fix), \ + SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET, VPMPCC_MCM_SHAPER_RAMA_REGION_26_27, \ + post_fix), \ + SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS, \ + VPMPCC_MCM_SHAPER_RAMA_REGION_26_27, post_fix), \ + SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET, VPMPCC_MCM_SHAPER_RAMA_REGION_26_27, \ + post_fix), \ + SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS, \ + VPMPCC_MCM_SHAPER_RAMA_REGION_26_27, post_fix), \ + SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET, VPMPCC_MCM_SHAPER_RAMA_REGION_28_29, \ + post_fix), \ + SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS, \ + VPMPCC_MCM_SHAPER_RAMA_REGION_28_29, post_fix), \ + SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET, VPMPCC_MCM_SHAPER_RAMA_REGION_28_29, \ + post_fix), \ + SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS, \ + VPMPCC_MCM_SHAPER_RAMA_REGION_28_29, post_fix), \ + SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET, VPMPCC_MCM_SHAPER_RAMA_REGION_30_31, \ + post_fix), \ + SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS, \ + VPMPCC_MCM_SHAPER_RAMA_REGION_30_31, post_fix), \ + SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET, VPMPCC_MCM_SHAPER_RAMA_REGION_30_31, \ + post_fix), \ + SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS, \ + VPMPCC_MCM_SHAPER_RAMA_REGION_30_31, post_fix), \ + SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET, VPMPCC_MCM_SHAPER_RAMA_REGION_32_33, \ + post_fix), \ + SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS, \ + VPMPCC_MCM_SHAPER_RAMA_REGION_32_33, post_fix), \ + SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET, VPMPCC_MCM_SHAPER_RAMA_REGION_32_33, \ + post_fix), \ + SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS, \ + VPMPCC_MCM_SHAPER_RAMA_REGION_32_33, post_fix), \ + SFRB(VPMPCC_MCM_3DLUT_MODE, VPMPCC_MCM_3DLUT_MODE, post_fix), \ + SFRB(VPMPCC_MCM_3DLUT_SIZE, VPMPCC_MCM_3DLUT_MODE, post_fix), \ + SFRB(VPMPCC_MCM_3DLUT_MODE_CURRENT, VPMPCC_MCM_3DLUT_MODE, post_fix), \ + SFRB(VPMPCC_MCM_3DLUT_SELECT_CURRENT, VPMPCC_MCM_3DLUT_MODE, post_fix), \ + SFRB(VPMPCC_MCM_3DLUT_INDEX, VPMPCC_MCM_3DLUT_INDEX, post_fix), \ + SFRB(VPMPCC_MCM_3DLUT_DATA0, VPMPCC_MCM_3DLUT_DATA, post_fix), \ + SFRB(VPMPCC_MCM_3DLUT_DATA1, VPMPCC_MCM_3DLUT_DATA, post_fix), \ + SFRB(VPMPCC_MCM_3DLUT_DATA_30BIT, VPMPCC_MCM_3DLUT_DATA_30BIT, post_fix), \ + SFRB(VPMPCC_MCM_3DLUT_WRITE_EN_MASK, VPMPCC_MCM_3DLUT_READ_WRITE_CONTROL, post_fix), \ + SFRB(VPMPCC_MCM_3DLUT_RAM_SEL, VPMPCC_MCM_3DLUT_READ_WRITE_CONTROL, post_fix), \ + SFRB(VPMPCC_MCM_3DLUT_30BIT_EN, VPMPCC_MCM_3DLUT_READ_WRITE_CONTROL, post_fix), \ + SFRB(VPMPCC_MCM_3DLUT_READ_SEL, VPMPCC_MCM_3DLUT_READ_WRITE_CONTROL, post_fix), \ + SFRB(VPMPCC_MCM_3DLUT_OUT_NORM_FACTOR, VPMPCC_MCM_3DLUT_OUT_NORM_FACTOR, post_fix), \ + SFRB(VPMPCC_MCM_3DLUT_OUT_OFFSET_R, VPMPCC_MCM_3DLUT_OUT_OFFSET_R, post_fix), \ + SFRB(VPMPCC_MCM_3DLUT_OUT_SCALE_R, VPMPCC_MCM_3DLUT_OUT_OFFSET_R, post_fix), \ + SFRB(VPMPCC_MCM_3DLUT_OUT_OFFSET_G, VPMPCC_MCM_3DLUT_OUT_OFFSET_G, post_fix), \ + SFRB(VPMPCC_MCM_3DLUT_OUT_SCALE_G, VPMPCC_MCM_3DLUT_OUT_OFFSET_G, post_fix), \ + SFRB(VPMPCC_MCM_3DLUT_OUT_OFFSET_B, VPMPCC_MCM_3DLUT_OUT_OFFSET_B, post_fix), \ + SFRB(VPMPCC_MCM_3DLUT_OUT_SCALE_B, VPMPCC_MCM_3DLUT_OUT_OFFSET_B, post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_MODE, VPMPCC_MCM_1DLUT_CONTROL, post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_PWL_DISABLE, VPMPCC_MCM_1DLUT_CONTROL, post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_MODE_CURRENT, VPMPCC_MCM_1DLUT_CONTROL, post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_SELECT_CURRENT, VPMPCC_MCM_1DLUT_CONTROL, post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_LUT_INDEX, VPMPCC_MCM_1DLUT_LUT_INDEX, post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_LUT_DATA, VPMPCC_MCM_1DLUT_LUT_DATA, post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK, VPMPCC_MCM_1DLUT_LUT_CONTROL, post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_LUT_READ_COLOR_SEL, VPMPCC_MCM_1DLUT_LUT_CONTROL, post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_LUT_READ_DBG, VPMPCC_MCM_1DLUT_LUT_CONTROL, post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_LUT_HOST_SEL, VPMPCC_MCM_1DLUT_LUT_CONTROL, post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_LUT_CONFIG_MODE, VPMPCC_MCM_1DLUT_LUT_CONTROL, post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B, VPMPCC_MCM_1DLUT_RAMA_START_CNTL_B, \ + post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B, VPMPCC_MCM_1DLUT_RAMA_START_CNTL_B, \ + post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_G, VPMPCC_MCM_1DLUT_RAMA_START_CNTL_G, \ + post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_G, VPMPCC_MCM_1DLUT_RAMA_START_CNTL_G, \ + post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_R, VPMPCC_MCM_1DLUT_RAMA_START_CNTL_R, \ + post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_R, VPMPCC_MCM_1DLUT_RAMA_START_CNTL_R, \ + post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B, \ + VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B, post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_G, \ + VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G, post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_R, \ + VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R, post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B, \ + VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B, post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_G, \ + VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G, post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_R, \ + VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R, post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B, VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_B, \ + post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B, VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_B, post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B, VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_B, \ + post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_G, VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_G, \ + post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_G, VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_G, post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_G, VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_G, \ + post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_R, VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_R, \ + post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_R, VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_R, post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_R, VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_R, \ + post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_RAMA_OFFSET_B, VPMPCC_MCM_1DLUT_RAMA_OFFSET_B, post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_RAMA_OFFSET_G, VPMPCC_MCM_1DLUT_RAMA_OFFSET_G, post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_RAMA_OFFSET_R, VPMPCC_MCM_1DLUT_RAMA_OFFSET_R, post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET, VPMPCC_MCM_1DLUT_RAMA_REGION_0_1, \ + post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS, VPMPCC_MCM_1DLUT_RAMA_REGION_0_1, \ + post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET, VPMPCC_MCM_1DLUT_RAMA_REGION_0_1, \ + post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS, VPMPCC_MCM_1DLUT_RAMA_REGION_0_1, \ + post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION2_LUT_OFFSET, VPMPCC_MCM_1DLUT_RAMA_REGION_2_3, \ + post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION2_NUM_SEGMENTS, VPMPCC_MCM_1DLUT_RAMA_REGION_2_3, \ + post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION3_LUT_OFFSET, VPMPCC_MCM_1DLUT_RAMA_REGION_2_3, \ + post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION3_NUM_SEGMENTS, VPMPCC_MCM_1DLUT_RAMA_REGION_2_3, \ + post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION4_LUT_OFFSET, VPMPCC_MCM_1DLUT_RAMA_REGION_4_5, \ + post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION4_NUM_SEGMENTS, VPMPCC_MCM_1DLUT_RAMA_REGION_4_5, \ + post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION5_LUT_OFFSET, VPMPCC_MCM_1DLUT_RAMA_REGION_4_5, \ + post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION5_NUM_SEGMENTS, VPMPCC_MCM_1DLUT_RAMA_REGION_4_5, \ + post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION6_LUT_OFFSET, VPMPCC_MCM_1DLUT_RAMA_REGION_6_7, \ + post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION6_NUM_SEGMENTS, VPMPCC_MCM_1DLUT_RAMA_REGION_6_7, \ + post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION7_LUT_OFFSET, VPMPCC_MCM_1DLUT_RAMA_REGION_6_7, \ + post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION7_NUM_SEGMENTS, VPMPCC_MCM_1DLUT_RAMA_REGION_6_7, \ + post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION8_LUT_OFFSET, VPMPCC_MCM_1DLUT_RAMA_REGION_8_9, \ + post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION8_NUM_SEGMENTS, VPMPCC_MCM_1DLUT_RAMA_REGION_8_9, \ + post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION9_LUT_OFFSET, VPMPCC_MCM_1DLUT_RAMA_REGION_8_9, \ + post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION9_NUM_SEGMENTS, VPMPCC_MCM_1DLUT_RAMA_REGION_8_9, \ + post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION10_LUT_OFFSET, VPMPCC_MCM_1DLUT_RAMA_REGION_10_11, \ + post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION10_NUM_SEGMENTS, VPMPCC_MCM_1DLUT_RAMA_REGION_10_11, \ + post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION11_LUT_OFFSET, VPMPCC_MCM_1DLUT_RAMA_REGION_10_11, \ + post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION11_NUM_SEGMENTS, VPMPCC_MCM_1DLUT_RAMA_REGION_10_11, \ + post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION12_LUT_OFFSET, VPMPCC_MCM_1DLUT_RAMA_REGION_12_13, \ + post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION12_NUM_SEGMENTS, VPMPCC_MCM_1DLUT_RAMA_REGION_12_13, \ + post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION13_LUT_OFFSET, VPMPCC_MCM_1DLUT_RAMA_REGION_12_13, \ + post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION13_NUM_SEGMENTS, VPMPCC_MCM_1DLUT_RAMA_REGION_12_13, \ + post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION14_LUT_OFFSET, VPMPCC_MCM_1DLUT_RAMA_REGION_14_15, \ + post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION14_NUM_SEGMENTS, VPMPCC_MCM_1DLUT_RAMA_REGION_14_15, \ + post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION15_LUT_OFFSET, VPMPCC_MCM_1DLUT_RAMA_REGION_14_15, \ + post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION15_NUM_SEGMENTS, VPMPCC_MCM_1DLUT_RAMA_REGION_14_15, \ + post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION16_LUT_OFFSET, VPMPCC_MCM_1DLUT_RAMA_REGION_16_17, \ + post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION16_NUM_SEGMENTS, VPMPCC_MCM_1DLUT_RAMA_REGION_16_17, \ + post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION17_LUT_OFFSET, VPMPCC_MCM_1DLUT_RAMA_REGION_16_17, \ + post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION17_NUM_SEGMENTS, VPMPCC_MCM_1DLUT_RAMA_REGION_16_17, \ + post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION18_LUT_OFFSET, VPMPCC_MCM_1DLUT_RAMA_REGION_18_19, \ + post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION18_NUM_SEGMENTS, VPMPCC_MCM_1DLUT_RAMA_REGION_18_19, \ + post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION19_LUT_OFFSET, VPMPCC_MCM_1DLUT_RAMA_REGION_18_19, \ + post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION19_NUM_SEGMENTS, VPMPCC_MCM_1DLUT_RAMA_REGION_18_19, \ + post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION20_LUT_OFFSET, VPMPCC_MCM_1DLUT_RAMA_REGION_20_21, \ + post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION20_NUM_SEGMENTS, VPMPCC_MCM_1DLUT_RAMA_REGION_20_21, \ + post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION21_LUT_OFFSET, VPMPCC_MCM_1DLUT_RAMA_REGION_20_21, \ + post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION21_NUM_SEGMENTS, VPMPCC_MCM_1DLUT_RAMA_REGION_20_21, \ + post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION22_LUT_OFFSET, VPMPCC_MCM_1DLUT_RAMA_REGION_22_23, \ + post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION22_NUM_SEGMENTS, VPMPCC_MCM_1DLUT_RAMA_REGION_22_23, \ + post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION23_LUT_OFFSET, VPMPCC_MCM_1DLUT_RAMA_REGION_22_23, \ + post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION23_NUM_SEGMENTS, VPMPCC_MCM_1DLUT_RAMA_REGION_22_23, \ + post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION24_LUT_OFFSET, VPMPCC_MCM_1DLUT_RAMA_REGION_24_25, \ + post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION24_NUM_SEGMENTS, VPMPCC_MCM_1DLUT_RAMA_REGION_24_25, \ + post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION25_LUT_OFFSET, VPMPCC_MCM_1DLUT_RAMA_REGION_24_25, \ + post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION25_NUM_SEGMENTS, VPMPCC_MCM_1DLUT_RAMA_REGION_24_25, \ + post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION26_LUT_OFFSET, VPMPCC_MCM_1DLUT_RAMA_REGION_26_27, \ + post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION26_NUM_SEGMENTS, VPMPCC_MCM_1DLUT_RAMA_REGION_26_27, \ + post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION27_LUT_OFFSET, VPMPCC_MCM_1DLUT_RAMA_REGION_26_27, \ + post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION27_NUM_SEGMENTS, VPMPCC_MCM_1DLUT_RAMA_REGION_26_27, \ + post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION28_LUT_OFFSET, VPMPCC_MCM_1DLUT_RAMA_REGION_28_29, \ + post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION28_NUM_SEGMENTS, VPMPCC_MCM_1DLUT_RAMA_REGION_28_29, \ + post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION29_LUT_OFFSET, VPMPCC_MCM_1DLUT_RAMA_REGION_28_29, \ + post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION29_NUM_SEGMENTS, VPMPCC_MCM_1DLUT_RAMA_REGION_28_29, \ + post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION30_LUT_OFFSET, VPMPCC_MCM_1DLUT_RAMA_REGION_30_31, \ + post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION30_NUM_SEGMENTS, VPMPCC_MCM_1DLUT_RAMA_REGION_30_31, \ + post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION31_LUT_OFFSET, VPMPCC_MCM_1DLUT_RAMA_REGION_30_31, \ + post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION31_NUM_SEGMENTS, VPMPCC_MCM_1DLUT_RAMA_REGION_30_31, \ + post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION32_LUT_OFFSET, VPMPCC_MCM_1DLUT_RAMA_REGION_32_33, \ + post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS, VPMPCC_MCM_1DLUT_RAMA_REGION_32_33, \ + post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET, VPMPCC_MCM_1DLUT_RAMA_REGION_32_33, \ + post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS, VPMPCC_MCM_1DLUT_RAMA_REGION_32_33, \ + post_fix), \ + SFRB(VPMPCC_MCM_SHAPER_MEM_PWR_FORCE, VPMPCC_MCM_MEM_PWR_CTRL, post_fix), \ + SFRB(VPMPCC_MCM_SHAPER_MEM_PWR_DIS, VPMPCC_MCM_MEM_PWR_CTRL, post_fix), \ + SFRB(VPMPCC_MCM_SHAPER_MEM_LOW_PWR_MODE, VPMPCC_MCM_MEM_PWR_CTRL, post_fix), \ + SFRB(VPMPCC_MCM_3DLUT_MEM_PWR_FORCE, VPMPCC_MCM_MEM_PWR_CTRL, post_fix), \ + SFRB(VPMPCC_MCM_3DLUT_MEM_PWR_DIS, VPMPCC_MCM_MEM_PWR_CTRL, post_fix), \ + SFRB(VPMPCC_MCM_3DLUT_MEM_LOW_PWR_MODE, VPMPCC_MCM_MEM_PWR_CTRL, post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_MEM_PWR_FORCE, VPMPCC_MCM_MEM_PWR_CTRL, post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_MEM_PWR_DIS, VPMPCC_MCM_MEM_PWR_CTRL, post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_MEM_LOW_PWR_MODE, VPMPCC_MCM_MEM_PWR_CTRL, post_fix), \ + SFRB(VPMPCC_MCM_SHAPER_MEM_PWR_STATE, VPMPCC_MCM_MEM_PWR_CTRL, post_fix), \ + SFRB(VPMPCC_MCM_3DLUT_MEM_PWR_STATE, VPMPCC_MCM_MEM_PWR_CTRL, post_fix), \ + SFRB(VPMPCC_MCM_1DLUT_MEM_PWR_STATE, VPMPCC_MCM_MEM_PWR_CTRL, post_fix) + +#define MPC_REG_VARIABLE_LIST_VPE10 \ + reg_id_val VPMPC_CLOCK_CONTROL; \ + reg_id_val VPMPC_SOFT_RESET; \ + reg_id_val VPMPC_CRC_CTRL; \ + reg_id_val VPMPC_CRC_SEL_CONTROL; \ + reg_id_val VPMPC_CRC_RESULT_AR; \ + reg_id_val VPMPC_CRC_RESULT_GB; \ + reg_id_val VPMPC_CRC_RESULT_C; \ + reg_id_val VPMPC_BYPASS_BG_AR; \ + reg_id_val VPMPC_BYPASS_BG_GB; \ + reg_id_val VPMPC_HOST_READ_CONTROL; \ + reg_id_val VPMPC_PENDING_STATUS_MISC; \ + reg_id_val VPMPC_OUT0_MUX; \ + reg_id_val VPMPC_OUT0_FLOAT_CONTROL; \ + reg_id_val VPMPC_OUT0_DENORM_CONTROL; \ + reg_id_val VPMPC_OUT0_DENORM_CLAMP_G_Y; \ + reg_id_val VPMPC_OUT0_DENORM_CLAMP_B_CB; \ + reg_id_val VPMPC_OUT_CSC_COEF_FORMAT; \ + reg_id_val VPMPC_OUT0_CSC_MODE; \ + reg_id_val VPMPC_OUT0_CSC_C11_C12_A; \ + reg_id_val VPMPC_OUT0_CSC_C13_C14_A; \ + reg_id_val VPMPC_OUT0_CSC_C21_C22_A; \ + reg_id_val VPMPC_OUT0_CSC_C23_C24_A; \ + reg_id_val VPMPC_OUT0_CSC_C31_C32_A; \ + reg_id_val VPMPC_OUT0_CSC_C33_C34_A; \ + reg_id_val VPMPCC_TOP_SEL; \ + reg_id_val VPMPCC_BOT_SEL; \ + reg_id_val VPMPCC_VPOPP_ID; \ + reg_id_val VPMPCC_CONTROL; \ + reg_id_val VPMPCC_TOP_GAIN; \ + reg_id_val VPMPCC_BOT_GAIN_INSIDE; \ + reg_id_val VPMPCC_BOT_GAIN_OUTSIDE; \ + reg_id_val VPMPCC_MOVABLE_CM_LOCATION_CONTROL; \ + reg_id_val VPMPCC_BG_R_CR; \ + reg_id_val VPMPCC_BG_G_Y; \ + reg_id_val VPMPCC_BG_B_CB; \ + reg_id_val VPMPCC_MEM_PWR_CTRL; \ + reg_id_val VPMPCC_STATUS; \ + reg_id_val VPMPCC_OGAM_CONTROL; \ + reg_id_val VPMPCC_OGAM_LUT_INDEX; \ + reg_id_val VPMPCC_OGAM_LUT_DATA; \ + reg_id_val VPMPCC_OGAM_LUT_CONTROL; \ + reg_id_val VPMPCC_OGAM_RAMA_START_CNTL_B; \ + reg_id_val VPMPCC_OGAM_RAMA_START_CNTL_G; \ + reg_id_val VPMPCC_OGAM_RAMA_START_CNTL_R; \ + reg_id_val VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_B; \ + reg_id_val VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_G; \ + reg_id_val VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_R; \ + reg_id_val VPMPCC_OGAM_RAMA_START_BASE_CNTL_B; \ + reg_id_val VPMPCC_OGAM_RAMA_START_BASE_CNTL_G; \ + reg_id_val VPMPCC_OGAM_RAMA_START_BASE_CNTL_R; \ + reg_id_val VPMPCC_OGAM_RAMA_END_CNTL1_B; \ + reg_id_val VPMPCC_OGAM_RAMA_END_CNTL2_B; \ + reg_id_val VPMPCC_OGAM_RAMA_END_CNTL1_G; \ + reg_id_val VPMPCC_OGAM_RAMA_END_CNTL2_G; \ + reg_id_val VPMPCC_OGAM_RAMA_END_CNTL1_R; \ + reg_id_val VPMPCC_OGAM_RAMA_END_CNTL2_R; \ + reg_id_val VPMPCC_OGAM_RAMA_OFFSET_B; \ + reg_id_val VPMPCC_OGAM_RAMA_OFFSET_G; \ + reg_id_val VPMPCC_OGAM_RAMA_OFFSET_R; \ + reg_id_val VPMPCC_OGAM_RAMA_REGION_0_1; \ + reg_id_val VPMPCC_OGAM_RAMA_REGION_2_3; \ + reg_id_val VPMPCC_OGAM_RAMA_REGION_4_5; \ + reg_id_val VPMPCC_OGAM_RAMA_REGION_6_7; \ + reg_id_val VPMPCC_OGAM_RAMA_REGION_8_9; \ + reg_id_val VPMPCC_OGAM_RAMA_REGION_10_11; \ + reg_id_val VPMPCC_OGAM_RAMA_REGION_12_13; \ + reg_id_val VPMPCC_OGAM_RAMA_REGION_14_15; \ + reg_id_val VPMPCC_OGAM_RAMA_REGION_16_17; \ + reg_id_val VPMPCC_OGAM_RAMA_REGION_18_19; \ + reg_id_val VPMPCC_OGAM_RAMA_REGION_20_21; \ + reg_id_val VPMPCC_OGAM_RAMA_REGION_22_23; \ + reg_id_val VPMPCC_OGAM_RAMA_REGION_24_25; \ + reg_id_val VPMPCC_OGAM_RAMA_REGION_26_27; \ + reg_id_val VPMPCC_OGAM_RAMA_REGION_28_29; \ + reg_id_val VPMPCC_OGAM_RAMA_REGION_30_31; \ + reg_id_val VPMPCC_OGAM_RAMA_REGION_32_33; \ + reg_id_val VPMPCC_GAMUT_REMAP_COEF_FORMAT; \ + reg_id_val VPMPCC_GAMUT_REMAP_MODE; \ + reg_id_val VPMPC_GAMUT_REMAP_C11_C12_A; \ + reg_id_val VPMPC_GAMUT_REMAP_C13_C14_A; \ + reg_id_val VPMPC_GAMUT_REMAP_C21_C22_A; \ + reg_id_val VPMPC_GAMUT_REMAP_C23_C24_A; \ + reg_id_val VPMPC_GAMUT_REMAP_C31_C32_A; \ + reg_id_val VPMPC_GAMUT_REMAP_C33_C34_A; \ + reg_id_val VPMPCC_MCM_SHAPER_CONTROL; \ + reg_id_val VPMPCC_MCM_SHAPER_OFFSET_R; \ + reg_id_val VPMPCC_MCM_SHAPER_OFFSET_G; \ + reg_id_val VPMPCC_MCM_SHAPER_OFFSET_B; \ + reg_id_val VPMPCC_MCM_SHAPER_SCALE_R; \ + reg_id_val VPMPCC_MCM_SHAPER_SCALE_G_B; \ + reg_id_val VPMPCC_MCM_SHAPER_LUT_INDEX; \ + reg_id_val VPMPCC_MCM_SHAPER_LUT_DATA; \ + reg_id_val VPMPCC_MCM_SHAPER_LUT_WRITE_EN_MASK; \ + reg_id_val VPMPCC_MCM_SHAPER_RAMA_START_CNTL_B; \ + reg_id_val VPMPCC_MCM_SHAPER_RAMA_START_CNTL_G; \ + reg_id_val VPMPCC_MCM_SHAPER_RAMA_START_CNTL_R; \ + reg_id_val VPMPCC_MCM_SHAPER_RAMA_END_CNTL_B; \ + reg_id_val VPMPCC_MCM_SHAPER_RAMA_END_CNTL_G; \ + reg_id_val VPMPCC_MCM_SHAPER_RAMA_END_CNTL_R; \ + reg_id_val VPMPCC_MCM_SHAPER_RAMA_REGION_0_1; \ + reg_id_val VPMPCC_MCM_SHAPER_RAMA_REGION_2_3; \ + reg_id_val VPMPCC_MCM_SHAPER_RAMA_REGION_4_5; \ + reg_id_val VPMPCC_MCM_SHAPER_RAMA_REGION_6_7; \ + reg_id_val VPMPCC_MCM_SHAPER_RAMA_REGION_8_9; \ + reg_id_val VPMPCC_MCM_SHAPER_RAMA_REGION_10_11; \ + reg_id_val VPMPCC_MCM_SHAPER_RAMA_REGION_12_13; \ + reg_id_val VPMPCC_MCM_SHAPER_RAMA_REGION_14_15; \ + reg_id_val VPMPCC_MCM_SHAPER_RAMA_REGION_16_17; \ + reg_id_val VPMPCC_MCM_SHAPER_RAMA_REGION_18_19; \ + reg_id_val VPMPCC_MCM_SHAPER_RAMA_REGION_20_21; \ + reg_id_val VPMPCC_MCM_SHAPER_RAMA_REGION_22_23; \ + reg_id_val VPMPCC_MCM_SHAPER_RAMA_REGION_24_25; \ + reg_id_val VPMPCC_MCM_SHAPER_RAMA_REGION_26_27; \ + reg_id_val VPMPCC_MCM_SHAPER_RAMA_REGION_28_29; \ + reg_id_val VPMPCC_MCM_SHAPER_RAMA_REGION_30_31; \ + reg_id_val VPMPCC_MCM_SHAPER_RAMA_REGION_32_33; \ + reg_id_val VPMPCC_MCM_3DLUT_MODE; \ + reg_id_val VPMPCC_MCM_3DLUT_INDEX; \ + reg_id_val VPMPCC_MCM_3DLUT_DATA; \ + reg_id_val VPMPCC_MCM_3DLUT_DATA_30BIT; \ + reg_id_val VPMPCC_MCM_3DLUT_READ_WRITE_CONTROL; \ + reg_id_val VPMPCC_MCM_3DLUT_OUT_NORM_FACTOR; \ + reg_id_val VPMPCC_MCM_3DLUT_OUT_OFFSET_R; \ + reg_id_val VPMPCC_MCM_3DLUT_OUT_OFFSET_G; \ + reg_id_val VPMPCC_MCM_3DLUT_OUT_OFFSET_B; \ + reg_id_val VPMPCC_MCM_1DLUT_CONTROL; \ + reg_id_val VPMPCC_MCM_1DLUT_LUT_INDEX; \ + reg_id_val VPMPCC_MCM_1DLUT_LUT_DATA; \ + reg_id_val VPMPCC_MCM_1DLUT_LUT_CONTROL; \ + reg_id_val VPMPCC_MCM_1DLUT_RAMA_START_CNTL_B; \ + reg_id_val VPMPCC_MCM_1DLUT_RAMA_START_CNTL_G; \ + reg_id_val VPMPCC_MCM_1DLUT_RAMA_START_CNTL_R; \ + reg_id_val VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B; \ + reg_id_val VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G; \ + reg_id_val VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R; \ + reg_id_val VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B; \ + reg_id_val VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G; \ + reg_id_val VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R; \ + reg_id_val VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_B; \ + reg_id_val VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_B; \ + reg_id_val VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_G; \ + reg_id_val VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_G; \ + reg_id_val VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_R; \ + reg_id_val VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_R; \ + reg_id_val VPMPCC_MCM_1DLUT_RAMA_OFFSET_B; \ + reg_id_val VPMPCC_MCM_1DLUT_RAMA_OFFSET_G; \ + reg_id_val VPMPCC_MCM_1DLUT_RAMA_OFFSET_R; \ + reg_id_val VPMPCC_MCM_1DLUT_RAMA_REGION_0_1; \ + reg_id_val VPMPCC_MCM_1DLUT_RAMA_REGION_2_3; \ + reg_id_val VPMPCC_MCM_1DLUT_RAMA_REGION_4_5; \ + reg_id_val VPMPCC_MCM_1DLUT_RAMA_REGION_6_7; \ + reg_id_val VPMPCC_MCM_1DLUT_RAMA_REGION_8_9; \ + reg_id_val VPMPCC_MCM_1DLUT_RAMA_REGION_10_11; \ + reg_id_val VPMPCC_MCM_1DLUT_RAMA_REGION_12_13; \ + reg_id_val VPMPCC_MCM_1DLUT_RAMA_REGION_14_15; \ + reg_id_val VPMPCC_MCM_1DLUT_RAMA_REGION_16_17; \ + reg_id_val VPMPCC_MCM_1DLUT_RAMA_REGION_18_19; \ + reg_id_val VPMPCC_MCM_1DLUT_RAMA_REGION_20_21; \ + reg_id_val VPMPCC_MCM_1DLUT_RAMA_REGION_22_23; \ + reg_id_val VPMPCC_MCM_1DLUT_RAMA_REGION_24_25; \ + reg_id_val VPMPCC_MCM_1DLUT_RAMA_REGION_26_27; \ + reg_id_val VPMPCC_MCM_1DLUT_RAMA_REGION_28_29; \ + reg_id_val VPMPCC_MCM_1DLUT_RAMA_REGION_30_31; \ + reg_id_val VPMPCC_MCM_1DLUT_RAMA_REGION_32_33; \ + reg_id_val VPMPCC_MCM_MEM_PWR_CTRL; + +#define MPC_FIELD_VARIABLE_LIST_VPE10(type) \ + type VPECLK_R_GATE_DISABLE; \ + type VPMPC_TEST_CLK_SEL; \ + type VPMPCC0_SOFT_RESET; \ + type VPMPC_SFR0_SOFT_RESET; \ + type VPMPC_SFT0_SOFT_RESET; \ + type VPMPC_SOFT_RESET; \ + type VPMPC_CRC_EN; \ + type VPMPC_CRC_CONT_EN; \ + type VPMPC_CRC_SRC_SEL; \ + type VPMPC_CRC_ONE_SHOT_PENDING; \ + type VPMPC_CRC_UPDATE_ENABLED; \ + type VPMPC_CRC_UPDATE_LOCK; \ + type VPMPC_CRC_VPDPP_SEL; \ + type VPMPC_CRC_VPOPP_SEL; \ + type VPMPC_CRC_MASK; \ + type VPMPC_CRC_RESULT_A; \ + type VPMPC_CRC_RESULT_R; \ + type VPMPC_CRC_RESULT_G; \ + type VPMPC_CRC_RESULT_B; \ + type VPMPC_CRC_RESULT_C; \ + type VPMPC_BYPASS_BG_ALPHA; \ + type VPMPC_BYPASS_BG_R_CR; \ + type VPMPC_BYPASS_BG_G_Y; \ + type VPMPC_BYPASS_BG_B_CB; \ + type HOST_READ_RATE_CONTROL; \ + type VPMPCC0_CONFIG_UPDATE_PENDING; \ + type VPMPC_OUT_MUX; \ + type VPMPC_OUT_FLOAT_EN; \ + type VPMPC_OUT_DENORM_CLAMP_MIN_R_CR; \ + type VPMPC_OUT_DENORM_CLAMP_MAX_R_CR; \ + type VPMPC_OUT_DENORM_MODE; \ + type VPMPC_OUT_DENORM_CLAMP_MIN_G_Y; \ + type VPMPC_OUT_DENORM_CLAMP_MAX_G_Y; \ + type VPMPC_OUT_DENORM_CLAMP_MIN_B_CB; \ + type VPMPC_OUT_DENORM_CLAMP_MAX_B_CB; \ + type VPMPC_OCSC0_COEF_FORMAT; \ + type VPMPC_OCSC_MODE; \ + type VPMPC_OCSC_MODE_CURRENT; \ + type VPMPC_OCSC_C11_A; \ + type VPMPC_OCSC_C12_A; \ + type VPMPC_OCSC_C13_A; \ + type VPMPC_OCSC_C14_A; \ + type VPMPC_OCSC_C21_A; \ + type VPMPC_OCSC_C22_A; \ + type VPMPC_OCSC_C23_A; \ + type VPMPC_OCSC_C24_A; \ + type VPMPC_OCSC_C31_A; \ + type VPMPC_OCSC_C32_A; \ + type VPMPC_OCSC_C33_A; \ + type VPMPC_OCSC_C34_A; \ + type VPMPCC_TOP_SEL; \ + type VPMPCC_BOT_SEL; \ + type VPMPCC_VPOPP_ID; \ + type VPMPCC_MODE; \ + type VPMPCC_ALPHA_BLND_MODE; \ + type VPMPCC_ALPHA_MULTIPLIED_MODE; \ + type VPMPCC_BLND_ACTIVE_OVERLAP_ONLY; \ + type VPMPCC_BG_BPC; \ + type VPMPCC_BOT_GAIN_MODE; \ + type VPMPCC_GLOBAL_ALPHA; \ + type VPMPCC_GLOBAL_GAIN; \ + type VPMPCC_TOP_GAIN; \ + type VPMPCC_BOT_GAIN_INSIDE; \ + type VPMPCC_BOT_GAIN_OUTSIDE; \ + type VPMPCC_MOVABLE_CM_LOCATION_CNTL; \ + type VPMPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT; \ + type VPMPCC_BG_R_CR; \ + type VPMPCC_BG_G_Y; \ + type VPMPCC_BG_B_CB; \ + type VPMPCC_OGAM_MEM_PWR_FORCE; \ + type VPMPCC_OGAM_MEM_PWR_DIS; \ + type VPMPCC_OGAM_MEM_LOW_PWR_MODE; \ + type VPMPCC_OGAM_MEM_PWR_STATE; \ + type VPMPCC_IDLE; \ + type VPMPCC_BUSY; \ + type VPMPCC_DISABLED; \ + type VPMPCC_OGAM_MODE; \ + type VPMPCC_OGAM_PWL_DISABLE; \ + type VPMPCC_OGAM_MODE_CURRENT; \ + type VPMPCC_OGAM_SELECT_CURRENT; \ + type VPMPCC_OGAM_LUT_INDEX; \ + type VPMPCC_OGAM_LUT_DATA; \ + type VPMPCC_OGAM_LUT_WRITE_COLOR_MASK; \ + type VPMPCC_OGAM_LUT_READ_COLOR_SEL; \ + type VPMPCC_OGAM_LUT_READ_DBG; \ + type VPMPCC_OGAM_LUT_HOST_SEL; \ + type VPMPCC_OGAM_LUT_CONFIG_MODE; \ + type VPMPCC_OGAM_RAMA_EXP_REGION_START_B; \ + type VPMPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B; \ + type VPMPCC_OGAM_RAMA_EXP_REGION_START_G; \ + type VPMPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G; \ + type VPMPCC_OGAM_RAMA_EXP_REGION_START_R; \ + type VPMPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R; \ + type VPMPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B; \ + type VPMPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G; \ + type VPMPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R; \ + type VPMPCC_OGAM_RAMA_EXP_REGION_START_BASE_B; \ + type VPMPCC_OGAM_RAMA_EXP_REGION_START_BASE_G; \ + type VPMPCC_OGAM_RAMA_EXP_REGION_START_BASE_R; \ + type VPMPCC_OGAM_RAMA_EXP_REGION_END_BASE_B; \ + type VPMPCC_OGAM_RAMA_EXP_REGION_END_B; \ + type VPMPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B; \ + type VPMPCC_OGAM_RAMA_EXP_REGION_END_BASE_G; \ + type VPMPCC_OGAM_RAMA_EXP_REGION_END_G; \ + type VPMPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G; \ + type VPMPCC_OGAM_RAMA_EXP_REGION_END_BASE_R; \ + type VPMPCC_OGAM_RAMA_EXP_REGION_END_R; \ + type VPMPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R; \ + type VPMPCC_OGAM_RAMA_OFFSET_B; \ + type VPMPCC_OGAM_RAMA_OFFSET_G; \ + type VPMPCC_OGAM_RAMA_OFFSET_R; \ + type VPMPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET; \ + type VPMPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; \ + type VPMPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET; \ + type VPMPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; \ + type VPMPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET; \ + type VPMPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS; \ + type VPMPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET; \ + type VPMPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS; \ + type VPMPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET; \ + type VPMPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS; \ + type VPMPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET; \ + type VPMPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS; \ + type VPMPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET; \ + type VPMPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS; \ + type VPMPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET; \ + type VPMPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS; \ + type VPMPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET; \ + type VPMPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS; \ + type VPMPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET; \ + type VPMPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS; \ + type VPMPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET; \ + type VPMPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS; \ + type VPMPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET; \ + type VPMPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS; \ + type VPMPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET; \ + type VPMPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS; \ + type VPMPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET; \ + type VPMPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS; \ + type VPMPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET; \ + type VPMPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS; \ + type VPMPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET; \ + type VPMPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS; \ + type VPMPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET; \ + type VPMPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS; \ + type VPMPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET; \ + type VPMPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS; \ + type VPMPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET; \ + type VPMPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS; \ + type VPMPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET; \ + type VPMPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS; \ + type VPMPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET; \ + type VPMPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS; \ + type VPMPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET; \ + type VPMPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS; \ + type VPMPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET; \ + type VPMPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS; \ + type VPMPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET; \ + type VPMPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS; \ + type VPMPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET; \ + type VPMPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS; \ + type VPMPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET; \ + type VPMPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS; \ + type VPMPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET; \ + type VPMPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS; \ + type VPMPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET; \ + type VPMPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS; \ + type VPMPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET; \ + type VPMPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS; \ + type VPMPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET; \ + type VPMPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS; \ + type VPMPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET; \ + type VPMPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS; \ + type VPMPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET; \ + type VPMPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS; \ + type VPMPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET; \ + type VPMPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS; \ + type VPMPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET; \ + type VPMPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS; \ + type VPMPCC_GAMUT_REMAP_COEF_FORMAT; \ + type VPMPCC_GAMUT_REMAP_MODE; \ + type VPMPCC_GAMUT_REMAP_MODE_CURRENT; \ + type VPMPCC_GAMUT_REMAP_C11_A; \ + type VPMPCC_GAMUT_REMAP_C12_A; \ + type VPMPCC_GAMUT_REMAP_C13_A; \ + type VPMPCC_GAMUT_REMAP_C14_A; \ + type VPMPCC_GAMUT_REMAP_C21_A; \ + type VPMPCC_GAMUT_REMAP_C22_A; \ + type VPMPCC_GAMUT_REMAP_C23_A; \ + type VPMPCC_GAMUT_REMAP_C24_A; \ + type VPMPCC_GAMUT_REMAP_C31_A; \ + type VPMPCC_GAMUT_REMAP_C32_A; \ + type VPMPCC_GAMUT_REMAP_C33_A; \ + type VPMPCC_GAMUT_REMAP_C34_A; \ + type VPMPCC_MCM_SHAPER_LUT_MODE; \ + type VPMPCC_MCM_SHAPER_MODE_CURRENT; \ + type VPMPCC_MCM_SHAPER_SELECT_CURRENT; \ + type VPMPCC_MCM_SHAPER_OFFSET_R; \ + type VPMPCC_MCM_SHAPER_OFFSET_G; \ + type VPMPCC_MCM_SHAPER_OFFSET_B; \ + type VPMPCC_MCM_SHAPER_SCALE_R; \ + type VPMPCC_MCM_SHAPER_SCALE_G; \ + type VPMPCC_MCM_SHAPER_SCALE_B; \ + type VPMPCC_MCM_SHAPER_LUT_INDEX; \ + type VPMPCC_MCM_SHAPER_LUT_DATA; \ + type VPMPCC_MCM_SHAPER_LUT_WRITE_EN_MASK; \ + type VPMPCC_MCM_SHAPER_LUT_WRITE_SEL; \ + type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B; \ + type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B; \ + type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_START_G; \ + type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G; \ + type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_START_R; \ + type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R; \ + type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B; \ + type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B; \ + type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_END_G; \ + type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_G; \ + type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_END_R; \ + type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_R; \ + type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET; \ + type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS; \ + type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET; \ + type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS; \ + type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET; \ + type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS; \ + type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET; \ + type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS; \ + type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET; \ + type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS; \ + type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET; \ + type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS; \ + type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET; \ + type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS; \ + type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET; \ + type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS; \ + type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET; \ + type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS; \ + type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET; \ + type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS; \ + type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET; \ + type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS; \ + type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET; \ + type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS; \ + type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET; \ + type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS; \ + type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET; \ + type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS; \ + type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET; \ + type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS; \ + type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET; \ + type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS; \ + type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET; \ + type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS; \ + type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET; \ + type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS; \ + type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET; \ + type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS; \ + type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET; \ + type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS; \ + type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET; \ + type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS; \ + type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET; \ + type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS; \ + type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET; \ + type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS; \ + type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET; \ + type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS; \ + type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET; \ + type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS; \ + type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET; \ + type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS; \ + type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET; \ + type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS; \ + type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET; \ + type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS; \ + type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET; \ + type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS; \ + type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET; \ + type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS; \ + type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET; \ + type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS; \ + type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET; \ + type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS; \ + type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET; \ + type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS; \ + type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET; \ + type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS; \ + type VPMPCC_MCM_3DLUT_MODE; \ + type VPMPCC_MCM_3DLUT_SIZE; \ + type VPMPCC_MCM_3DLUT_MODE_CURRENT; \ + type VPMPCC_MCM_3DLUT_SELECT_CURRENT; \ + type VPMPCC_MCM_3DLUT_INDEX; \ + type VPMPCC_MCM_3DLUT_DATA0; \ + type VPMPCC_MCM_3DLUT_DATA1; \ + type VPMPCC_MCM_3DLUT_DATA_30BIT; \ + type VPMPCC_MCM_3DLUT_WRITE_EN_MASK; \ + type VPMPCC_MCM_3DLUT_RAM_SEL; \ + type VPMPCC_MCM_3DLUT_30BIT_EN; \ + type VPMPCC_MCM_3DLUT_READ_SEL; \ + type VPMPCC_MCM_3DLUT_OUT_NORM_FACTOR; \ + type VPMPCC_MCM_3DLUT_OUT_OFFSET_R; \ + type VPMPCC_MCM_3DLUT_OUT_SCALE_R; \ + type VPMPCC_MCM_3DLUT_OUT_OFFSET_G; \ + type VPMPCC_MCM_3DLUT_OUT_SCALE_G; \ + type VPMPCC_MCM_3DLUT_OUT_OFFSET_B; \ + type VPMPCC_MCM_3DLUT_OUT_SCALE_B; \ + type VPMPCC_MCM_1DLUT_MODE; \ + type VPMPCC_MCM_1DLUT_PWL_DISABLE; \ + type VPMPCC_MCM_1DLUT_MODE_CURRENT; \ + type VPMPCC_MCM_1DLUT_SELECT_CURRENT; \ + type VPMPCC_MCM_1DLUT_LUT_INDEX; \ + type VPMPCC_MCM_1DLUT_LUT_DATA; \ + type VPMPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK; \ + type VPMPCC_MCM_1DLUT_LUT_READ_COLOR_SEL; \ + type VPMPCC_MCM_1DLUT_LUT_READ_DBG; \ + type VPMPCC_MCM_1DLUT_LUT_HOST_SEL; \ + type VPMPCC_MCM_1DLUT_LUT_CONFIG_MODE; \ + type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B; \ + type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B; \ + type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_G; \ + type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_G; \ + type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_R; \ + type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_R; \ + type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B; \ + type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_G; \ + type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_R; \ + type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B; \ + type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_G; \ + type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_R; \ + type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B; \ + type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B; \ + type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B; \ + type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_G; \ + type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_G; \ + type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_G; \ + type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_R; \ + type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_R; \ + type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_R; \ + type VPMPCC_MCM_1DLUT_RAMA_OFFSET_B; \ + type VPMPCC_MCM_1DLUT_RAMA_OFFSET_G; \ + type VPMPCC_MCM_1DLUT_RAMA_OFFSET_R; \ + type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET; \ + type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS; \ + type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET; \ + type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS; \ + type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION2_LUT_OFFSET; \ + type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION2_NUM_SEGMENTS; \ + type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION3_LUT_OFFSET; \ + type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION3_NUM_SEGMENTS; \ + type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION4_LUT_OFFSET; \ + type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION4_NUM_SEGMENTS; \ + type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION5_LUT_OFFSET; \ + type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION5_NUM_SEGMENTS; \ + type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION6_LUT_OFFSET; \ + type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION6_NUM_SEGMENTS; \ + type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION7_LUT_OFFSET; \ + type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION7_NUM_SEGMENTS; \ + type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION8_LUT_OFFSET; \ + type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION8_NUM_SEGMENTS; \ + type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION9_LUT_OFFSET; \ + type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION9_NUM_SEGMENTS; \ + type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION10_LUT_OFFSET; \ + type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION10_NUM_SEGMENTS; \ + type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION11_LUT_OFFSET; \ + type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION11_NUM_SEGMENTS; \ + type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION12_LUT_OFFSET; \ + type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION12_NUM_SEGMENTS; \ + type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION13_LUT_OFFSET; \ + type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION13_NUM_SEGMENTS; \ + type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION14_LUT_OFFSET; \ + type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION14_NUM_SEGMENTS; \ + type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION15_LUT_OFFSET; \ + type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION15_NUM_SEGMENTS; \ + type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION16_LUT_OFFSET; \ + type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION16_NUM_SEGMENTS; \ + type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION17_LUT_OFFSET; \ + type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION17_NUM_SEGMENTS; \ + type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION18_LUT_OFFSET; \ + type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION18_NUM_SEGMENTS; \ + type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION19_LUT_OFFSET; \ + type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION19_NUM_SEGMENTS; \ + type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION20_LUT_OFFSET; \ + type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION20_NUM_SEGMENTS; \ + type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION21_LUT_OFFSET; \ + type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION21_NUM_SEGMENTS; \ + type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION22_LUT_OFFSET; \ + type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION22_NUM_SEGMENTS; \ + type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION23_LUT_OFFSET; \ + type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION23_NUM_SEGMENTS; \ + type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION24_LUT_OFFSET; \ + type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION24_NUM_SEGMENTS; \ + type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION25_LUT_OFFSET; \ + type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION25_NUM_SEGMENTS; \ + type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION26_LUT_OFFSET; \ + type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION26_NUM_SEGMENTS; \ + type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION27_LUT_OFFSET; \ + type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION27_NUM_SEGMENTS; \ + type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION28_LUT_OFFSET; \ + type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION28_NUM_SEGMENTS; \ + type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION29_LUT_OFFSET; \ + type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION29_NUM_SEGMENTS; \ + type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION30_LUT_OFFSET; \ + type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION30_NUM_SEGMENTS; \ + type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION31_LUT_OFFSET; \ + type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION31_NUM_SEGMENTS; \ + type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION32_LUT_OFFSET; \ + type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS; \ + type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET; \ + type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS; \ + type VPMPCC_MCM_SHAPER_MEM_PWR_FORCE; \ + type VPMPCC_MCM_SHAPER_MEM_PWR_DIS; \ + type VPMPCC_MCM_SHAPER_MEM_LOW_PWR_MODE; \ + type VPMPCC_MCM_3DLUT_MEM_PWR_FORCE; \ + type VPMPCC_MCM_3DLUT_MEM_PWR_DIS; \ + type VPMPCC_MCM_3DLUT_MEM_LOW_PWR_MODE; \ + type VPMPCC_MCM_1DLUT_MEM_PWR_FORCE; \ + type VPMPCC_MCM_1DLUT_MEM_PWR_DIS; \ + type VPMPCC_MCM_1DLUT_MEM_LOW_PWR_MODE; \ + type VPMPCC_MCM_SHAPER_MEM_PWR_STATE; \ + type VPMPCC_MCM_3DLUT_MEM_PWR_STATE; \ + type VPMPCC_MCM_1DLUT_MEM_PWR_STATE; + +struct vpe10_mpc_registers { + MPC_REG_VARIABLE_LIST_VPE10 +}; + +struct vpe10_mpc_shift { + MPC_FIELD_VARIABLE_LIST_VPE10(uint8_t) +}; + +struct vpe10_mpc_mask { + MPC_FIELD_VARIABLE_LIST_VPE10(uint32_t) +}; + +struct vpe10_mpc { + struct mpc base; + struct vpe10_mpc_registers *regs; + const struct vpe10_mpc_shift *shift; + const struct vpe10_mpc_mask *mask; +}; + +void vpe10_construct_mpc(struct vpe_priv *vpe_priv, struct mpc *mpc); + +void vpe10_mpc_program_mpcc_mux(struct mpc *mpc, enum mpc_mpccid mpcc_idx, + enum mpc_mux_topsel topsel, enum mpc_mux_botsel botsel, enum mpc_mux_outmux outmux, + enum mpc_mux_oppid oppid); + +void vpe10_mpc_program_mpcc_blending( + struct mpc *mpc, enum mpc_mpccid mpcc_idx, struct mpcc_blnd_cfg *blnd_cfg); + +void vpe10_mpc_program_mpc_bypass_bg_color(struct mpc *mpc, struct mpcc_blnd_cfg *blnd_cfg); + +void vpe10_mpc_power_on_ogam_lut(struct mpc *mpc, bool power_on); + +void vpe10_mpc_set_output_csc( + struct mpc *mpc, const uint16_t *regval, enum mpc_output_csc_mode ocsc_mode); + +void vpe10_mpc_set_ocsc_default(struct mpc *mpc, enum vpe_surface_pixel_format pixel_format, + enum color_space color_space, enum mpc_output_csc_mode ocsc_mode); + +void vpe10_program_output_csc(struct mpc *mpc, enum vpe_surface_pixel_format pixel_format, + enum color_space colorspace, uint16_t *matrix); + +void vpe10_mpc_set_output_gamma(struct mpc *mpc, const struct pwl_params *params); + +void vpe10_mpc_set_gamut_remap(struct mpc *mpc, struct colorspace_transform *gamut_remap); + +void vpe10_mpc_power_on_1dlut_shaper_3dlut(struct mpc *mpc, bool power_on); + +bool vpe10_mpc_program_shaper(struct mpc *mpc, const struct pwl_params *params); + +// using direct config to program the 3dlut specified in params +void vpe10_mpc_program_3dlut(struct mpc *mpc, const struct tetrahedral_params *params); + +// using indirect config to configure the 3DLut +// note that we still need direct config to switch the mask between lut0 - lut3 +bool vpe10_mpc_program_3dlut_indirect(struct mpc *mpc, + struct vpe_buf *lut0_3_buf, // 3d lut buf which contains the data for lut0-lut3 + bool use_tetrahedral_9, bool use_12bits); + +// Blend-gamma control. +void vpe10_mpc_program_1dlut(struct mpc *mpc, const struct pwl_params *params); + +void vpe10_mpc_program_cm_location(struct mpc *mpc, uint8_t location); + +void vpe10_mpc_set_denorm(struct mpc *mpc, int opp_id, enum color_depth output_depth, + struct mpc_denorm_clamp *denorm_clamp); + +void vpe10_mpc_set_out_float_en(struct mpc *mpc, bool float_enable); + +void vpe10_mpc_program_mpc_out(struct mpc *mpc, enum vpe_surface_pixel_format format); + +void vpe10_mpc_set_output_transfer_func(struct mpc *mpc, struct output_ctx *output_ctx); + +void vpe10_mpc_set_mpc_shaper_3dlut( + struct mpc *mpc, const struct transfer_func *func_shaper, const struct vpe_3dlut *lut3d_func); + +void vpe10_mpc_set_blend_lut(struct mpc *mpc, const struct transfer_func *blend_tf); + +bool vpe10_mpc_program_movable_cm(struct mpc *mpc, const struct transfer_func *func_shaper, + const struct vpe_3dlut *lut3d_func, const struct transfer_func *blend_tf, bool afterblend); + +void vpe10_mpc_program_crc(struct mpc *mpc, bool enable); +#ifdef __cplusplus +} +#endif diff --git a/src/amd/vpelib/src/chip/vpe10/inc/vpe10_opp.h b/src/amd/vpelib/src/chip/vpe10/inc/vpe10_opp.h new file mode 100644 index 00000000000..5637225c3c4 --- /dev/null +++ b/src/amd/vpelib/src/chip/vpe10/inc/vpe10_opp.h @@ -0,0 +1,182 @@ +/* Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ +#pragma once + +#include "opp.h" +#include "reg_helper.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define OPP_REG_LIST_VPE10(id) \ + SRIDFVL(VPFMT_CLAMP_COMPONENT_R, VPFMT, id), SRIDFVL(VPFMT_CLAMP_COMPONENT_G, VPFMT, id), \ + SRIDFVL(VPFMT_CLAMP_COMPONENT_B, VPFMT, id), SRIDFVL(VPFMT_DYNAMIC_EXP_CNTL, VPFMT, id), \ + SRIDFVL(VPFMT_CONTROL, VPFMT, id), SRIDFVL(VPFMT_BIT_DEPTH_CONTROL, VPFMT, id), \ + SRIDFVL(VPFMT_DITHER_RAND_R_SEED, VPFMT, id), \ + SRIDFVL(VPFMT_DITHER_RAND_G_SEED, VPFMT, id), \ + SRIDFVL(VPFMT_DITHER_RAND_B_SEED, VPFMT, id), SRIDFVL(VPFMT_CLAMP_CNTL, VPFMT, id), \ + SRIDFVL(VPOPP_PIPE_CONTROL, VPOPP_PIPE, id), \ + SRIDFVL(VPOPP_TOP_CLK_CONTROL, VPOPP_TOP, id), \ + SRIDFVL(VPOPP_PIPE_CRC_CONTROL, VPOPP_PIPE_CRC, id), + +#define OPP_FIELD_LIST_VPE10(post_fix) \ + SFRB(VPFMT_CLAMP_LOWER_R, VPFMT_CLAMP_COMPONENT_R, post_fix), \ + SFRB(VPFMT_CLAMP_UPPER_R, VPFMT_CLAMP_COMPONENT_R, post_fix), \ + SFRB(VPFMT_CLAMP_LOWER_G, VPFMT_CLAMP_COMPONENT_G, post_fix), \ + SFRB(VPFMT_CLAMP_UPPER_G, VPFMT_CLAMP_COMPONENT_G, post_fix), \ + SFRB(VPFMT_CLAMP_LOWER_B, VPFMT_CLAMP_COMPONENT_B, post_fix), \ + SFRB(VPFMT_CLAMP_UPPER_B, VPFMT_CLAMP_COMPONENT_B, post_fix), \ + SFRB(VPFMT_DYNAMIC_EXP_EN, VPFMT_DYNAMIC_EXP_CNTL, post_fix), \ + SFRB(VPFMT_DYNAMIC_EXP_MODE, VPFMT_DYNAMIC_EXP_CNTL, post_fix), \ + SFRB(VPFMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, VPFMT_CONTROL, post_fix), \ + SFRB(VPFMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, VPFMT_CONTROL, post_fix), \ + SFRB(VPFMT_CBCR_BIT_REDUCTION_BYPASS, VPFMT_CONTROL, post_fix), \ + SFRB(VPFMT_DOUBLE_BUFFER_REG_UPDATE_PENDING, VPFMT_CONTROL, post_fix), \ + SFRB(VPFMT_TRUNCATE_EN, VPFMT_BIT_DEPTH_CONTROL, post_fix), \ + SFRB(VPFMT_TRUNCATE_MODE, VPFMT_BIT_DEPTH_CONTROL, post_fix), \ + SFRB(VPFMT_TRUNCATE_DEPTH, VPFMT_BIT_DEPTH_CONTROL, post_fix), \ + SFRB(VPFMT_SPATIAL_DITHER_EN, VPFMT_BIT_DEPTH_CONTROL, post_fix), \ + SFRB(VPFMT_SPATIAL_DITHER_MODE, VPFMT_BIT_DEPTH_CONTROL, post_fix), \ + SFRB(VPFMT_SPATIAL_DITHER_DEPTH, VPFMT_BIT_DEPTH_CONTROL, post_fix), \ + SFRB(VPFMT_FRAME_RANDOM_ENABLE, VPFMT_BIT_DEPTH_CONTROL, post_fix), \ + SFRB(VPFMT_RGB_RANDOM_ENABLE, VPFMT_BIT_DEPTH_CONTROL, post_fix), \ + SFRB(VPFMT_HIGHPASS_RANDOM_ENABLE, VPFMT_BIT_DEPTH_CONTROL, post_fix), \ + SFRB(VPFMT_RAND_R_SEED, VPFMT_DITHER_RAND_R_SEED, post_fix), \ + SFRB(VPFMT_OFFSET_R_CR, VPFMT_DITHER_RAND_R_SEED, post_fix), \ + SFRB(VPFMT_RAND_G_SEED, VPFMT_DITHER_RAND_G_SEED, post_fix), \ + SFRB(VPFMT_OFFSET_G_Y, VPFMT_DITHER_RAND_G_SEED, post_fix), \ + SFRB(VPFMT_RAND_B_SEED, VPFMT_DITHER_RAND_B_SEED, post_fix), \ + SFRB(VPFMT_OFFSET_B_CB, VPFMT_DITHER_RAND_B_SEED, post_fix), \ + SFRB(VPFMT_CLAMP_DATA_EN, VPFMT_CLAMP_CNTL, post_fix), \ + SFRB(VPFMT_CLAMP_COLOR_FORMAT, VPFMT_CLAMP_CNTL, post_fix), \ + SFRB(VPOPP_PIPE_CLOCK_ON, VPOPP_PIPE_CONTROL, post_fix), \ + SFRB(VPOPP_PIPE_DIGITAL_BYPASS_EN, VPOPP_PIPE_CONTROL, post_fix), \ + SFRB(VPOPP_PIPE_ALPHA, VPOPP_PIPE_CONTROL, post_fix), \ + SFRB(VPOPP_VPECLK_R_GATE_DIS, VPOPP_TOP_CLK_CONTROL, post_fix), \ + SFRB(VPOPP_VPECLK_G_GATE_DIS, VPOPP_TOP_CLK_CONTROL, post_fix), \ + SFRB(VPOPP_PIPE_CRC_EN, VPOPP_PIPE_CRC_CONTROL, post_fix), \ + SFRB(VPOPP_PIPE_CRC_CONT_EN, VPOPP_PIPE_CRC_CONTROL, post_fix), \ + SFRB(VPOPP_PIPE_CRC_PIXEL_SELECT, VPOPP_PIPE_CRC_CONTROL, post_fix) + +#define OPP_REG_VARIABLE_LIST_VPE10 \ + reg_id_val VPFMT_CLAMP_COMPONENT_R; \ + reg_id_val VPFMT_CLAMP_COMPONENT_G; \ + reg_id_val VPFMT_CLAMP_COMPONENT_B; \ + reg_id_val VPFMT_DYNAMIC_EXP_CNTL; \ + reg_id_val VPFMT_CONTROL; \ + reg_id_val VPFMT_BIT_DEPTH_CONTROL; \ + reg_id_val VPFMT_DITHER_RAND_R_SEED; \ + reg_id_val VPFMT_DITHER_RAND_G_SEED; \ + reg_id_val VPFMT_DITHER_RAND_B_SEED; \ + reg_id_val VPFMT_CLAMP_CNTL; \ + reg_id_val VPOPP_PIPE_CONTROL; \ + reg_id_val VPOPP_TOP_CLK_CONTROL; \ + reg_id_val VPOPP_PIPE_CRC_CONTROL; + +#define OPP_FIELD_VARIABLE_LIST_VPE10(type) \ + type VPFMT_CLAMP_LOWER_R; \ + type VPFMT_CLAMP_UPPER_R; \ + type VPFMT_CLAMP_LOWER_G; \ + type VPFMT_CLAMP_UPPER_G; \ + type VPFMT_CLAMP_LOWER_B; \ + type VPFMT_CLAMP_UPPER_B; \ + type VPFMT_DYNAMIC_EXP_EN; \ + type VPFMT_DYNAMIC_EXP_MODE; \ + type VPFMT_SPATIAL_DITHER_FRAME_COUNTER_MAX; \ + type VPFMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP; \ + type VPFMT_CBCR_BIT_REDUCTION_BYPASS; \ + type VPFMT_DOUBLE_BUFFER_REG_UPDATE_PENDING; \ + type VPFMT_TRUNCATE_EN; \ + type VPFMT_TRUNCATE_MODE; \ + type VPFMT_TRUNCATE_DEPTH; \ + type VPFMT_SPATIAL_DITHER_EN; \ + type VPFMT_SPATIAL_DITHER_MODE; \ + type VPFMT_SPATIAL_DITHER_DEPTH; \ + type VPFMT_FRAME_RANDOM_ENABLE; \ + type VPFMT_RGB_RANDOM_ENABLE; \ + type VPFMT_HIGHPASS_RANDOM_ENABLE; \ + type VPFMT_RAND_R_SEED; \ + type VPFMT_OFFSET_R_CR; \ + type VPFMT_RAND_G_SEED; \ + type VPFMT_OFFSET_G_Y; \ + type VPFMT_RAND_B_SEED; \ + type VPFMT_OFFSET_B_CB; \ + type VPFMT_CLAMP_DATA_EN; \ + type VPFMT_CLAMP_COLOR_FORMAT; \ + type VPOPP_PIPE_CLOCK_ON; \ + type VPOPP_PIPE_DIGITAL_BYPASS_EN; \ + type VPOPP_PIPE_ALPHA; \ + type VPOPP_VPECLK_R_GATE_DIS; \ + type VPOPP_VPECLK_G_GATE_DIS; \ + type VPOPP_PIPE_CRC_EN; \ + type VPOPP_PIPE_CRC_CONT_EN; \ + type VPOPP_PIPE_CRC_PIXEL_SELECT; + +struct vpe10_opp_registers { + OPP_REG_VARIABLE_LIST_VPE10 +}; + +struct vpe10_opp_shift { + OPP_FIELD_VARIABLE_LIST_VPE10(uint8_t) +}; + +struct vpe10_opp_mask { + OPP_FIELD_VARIABLE_LIST_VPE10(uint32_t) +}; + +struct vpe10_opp { + struct opp base; + struct vpe10_opp_registers *regs; + const struct vpe10_opp_shift *shift; + const struct vpe10_opp_mask *mask; +}; + +void vpe10_construct_opp(struct vpe_priv *vpe_priv, struct opp *opp); + +enum color_depth vpe10_opp_check_color_depth(enum vpe_surface_pixel_format format); + +void vpe10_opp_set_clamping( + struct opp *opp, const struct clamping_and_pixel_encoding_params *params); + +void vpe10_opp_set_dyn_expansion(struct opp *opp, bool enable, enum color_depth color_dpth); + +void vpe10_opp_set_truncation(struct opp *opp, const struct bit_depth_reduction_params *params); + +void vpe10_opp_set_spatial_dither(struct opp *opp, const struct bit_depth_reduction_params *params); + +void vpe10_opp_program_bit_depth_reduction( + struct opp *opp, const struct bit_depth_reduction_params *fmt_bit_depth); + +void vpe10_opp_program_fmt(struct opp *opp, struct bit_depth_reduction_params *fmt_bit_depth, + struct clamping_and_pixel_encoding_params *clamping); + +void vpe10_opp_program_pipe_alpha(struct opp *opp, uint16_t alpha); + +void vpe10_opp_program_pipe_bypass(struct opp *opp, bool enable); + +void vpe10_opp_program_pipe_crc(struct opp *opp, bool enable); +#ifdef __cplusplus +} +#endif diff --git a/src/amd/vpelib/src/chip/vpe10/inc/vpe10_resource.h b/src/amd/vpelib/src/chip/vpe10/inc/vpe10_resource.h new file mode 100644 index 00000000000..a203e138a44 --- /dev/null +++ b/src/amd/vpelib/src/chip/vpe10/inc/vpe10_resource.h @@ -0,0 +1,80 @@ +/* Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ +#pragma once + +#include "resource.h" + +#ifdef __cplusplus +extern "C" { +#endif + +enum vpe_status vpe10_construct_resource(struct vpe_priv *vpe_priv, struct resource *res); + +void vpe10_destroy_resource(struct vpe_priv *vpe_priv, struct resource *res); + +enum vpe_status vpe10_set_num_segments(struct vpe_priv *vpe_priv, struct stream_ctx *stream_ctx, + struct scaler_data *scl_data, struct vpe_rect *src_rect, struct vpe_rect *dst_rect, + uint32_t *max_seg_width); + +bool vpe10_get_dcc_compression_cap(const struct vpe *vpe, const struct vpe_dcc_surface_param *input, + struct vpe_surface_dcc_cap *output); + +bool vpe10_check_input_color_space(struct vpe_priv *vpe_priv, enum vpe_surface_pixel_format format, + const struct vpe_color_space *vcs); + +bool vpe10_check_output_color_space(struct vpe_priv *vpe_priv, enum vpe_surface_pixel_format format, + const struct vpe_color_space *vcs); + +bool vpe10_check_h_mirror_support(bool *input_mirror, bool *output_mirror); + +enum vpe_status vpe10_calculate_segments( + struct vpe_priv *vpe_priv, const struct vpe_build_param *params); + +int32_t vpe10_program_frontend(struct vpe_priv *vpe_priv, uint32_t pipe_idx, uint32_t cmd_idx, + uint32_t cmd_input_idx, bool seg_only); + +int32_t vpe10_program_backend( + struct vpe_priv *vpe_priv, uint32_t pipe_idx, uint32_t cmd_idx, bool seg_only); + +enum vpe_status vpe10_populate_cmd_info(struct vpe_priv *vpe_priv); + +void vpe10_calculate_dst_viewport_and_active( + struct segment_ctx *segment_ctx, uint32_t max_seg_width); + +void vpe10_create_stream_ops_config(struct vpe_priv *vpe_priv, uint32_t pipe_idx, + struct stream_ctx *stream_ctx, struct vpe_cmd_input *cmd_input, enum vpe_cmd_ops ops); + +void vpe10_get_bufs_req(struct vpe_priv *vpe_priv, struct vpe_bufs_req *req); + +struct opp *vpe10_opp_create(struct vpe_priv *vpe_priv, int inst); + +struct mpc *vpe10_mpc_create(struct vpe_priv *vpe_priv, int inst); + +struct dpp *vpe10_dpp_create(struct vpe_priv *vpe_priv, int inst); + +struct cdc *vpe10_cdc_create(struct vpe_priv *vpe_priv, int inst); + +#ifdef __cplusplus +} +#endif diff --git a/src/amd/vpelib/src/chip/vpe10/inc/vpe10_vpec.h b/src/amd/vpelib/src/chip/vpe10/inc/vpe10_vpec.h new file mode 100644 index 00000000000..4da8ccc140e --- /dev/null +++ b/src/amd/vpelib/src/chip/vpe10/inc/vpe10_vpec.h @@ -0,0 +1,44 @@ +/* Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ +#pragma once + +#include "vpec.h" + +#ifdef __cplusplus +extern "C" { +#endif + +void vpe10_construct_vpec(struct vpe_priv *vpe_priv, struct vpec *vpec); + +/** functions for capability check */ +bool vpe10_vpec_check_swmode_support(struct vpec *vpec, enum vpe_swizzle_mode_values sw_mode); + +bool vpe10_vpec_get_dcc_compression_cap(struct vpec *vpec, + const struct vpe_dcc_surface_param *input, struct vpe_surface_dcc_cap *output); + +/** functions for generating command buffer */ + +#ifdef __cplusplus +} +#endif diff --git a/src/amd/vpelib/src/chip/vpe10/vpe10_background.c b/src/amd/vpelib/src/chip/vpe10/vpe10_background.c new file mode 100644 index 00000000000..2b05be2e751 --- /dev/null +++ b/src/amd/vpelib/src/chip/vpe10/vpe10_background.c @@ -0,0 +1,66 @@ +/* Copyright 2023 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include "vpe10_background.h" +#include "common.h" +#include "vpe_priv.h" + +bool vpe10_split_bg_gap(struct vpe_rect *gaps, const struct vpe_rect *target_rect, + uint32_t max_width, uint16_t max_gaps, uint16_t *num_gaps, uint16_t num_multiple) +{ + uint16_t gap_cnt, gap_idx, num_gaps_t; + uint16_t prev_idx = *num_gaps - 1; + uint32_t gap_width, gap_height; + int32_t gap_x, gap_y; + + // -1 is for removing the previous "going-to-be" splitted segment + num_gaps_t = *num_gaps - 1; + gap_x = gaps[prev_idx].x; + gap_y = gaps[prev_idx].y; + gap_width = gaps[prev_idx].width; + gap_height = gaps[prev_idx].height; + + gap_cnt = (uint16_t)((gap_width + max_width - 1) / max_width); + + if (gap_cnt % num_multiple != 0) { + gap_cnt += (num_multiple - (gap_cnt % num_multiple)); + max_width = (uint16_t)((gap_width + gap_cnt - 1) / gap_cnt); + } + + if (num_gaps_t + gap_cnt > max_gaps) + return false; + + for (gap_idx = prev_idx; gap_idx < num_gaps_t + gap_cnt; gap_idx++) { + gaps[gap_idx].y = gap_y; + gaps[gap_idx].height = gap_height; + gaps[gap_idx].x = gap_x; + gaps[gap_idx].width = gap_width < max_width ? gap_width : max_width; + + gap_x = gap_x + (int32_t)gaps[gap_idx].width; + gap_width = gap_width - gaps[gap_idx].width; + } + + *num_gaps = num_gaps_t + gap_cnt; + return true; +} diff --git a/src/amd/vpelib/src/chip/vpe10/vpe10_cdc.c b/src/amd/vpelib/src/chip/vpe10/vpe10_cdc.c new file mode 100644 index 00000000000..4c79b68a6fa --- /dev/null +++ b/src/amd/vpelib/src/chip/vpe10/vpe10_cdc.c @@ -0,0 +1,317 @@ +/* Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include "common.h" +#include "vpe_priv.h" +#include "vpe10_cdc.h" +#include "reg_helper.h" + +#define CTX_BASE cdc +#define CTX vpe10_cdc + +enum mux_sel { + MUX_SEL_ALPHA = 0, + MUX_SEL_Y_G = 1, + MUX_SEL_CB_B = 2, + MUX_SEL_CR_R = 3 +}; + +static struct cdc_funcs cdc_func = { + .check_input_format = vpe10_cdc_check_input_format, + .check_output_format = vpe10_cdc_check_output_format, + + .program_surface_config = vpe10_cdc_program_surface_config, + .program_crossbar_config = vpe10_cdc_program_crossbar_config, + .program_global_sync = vpe10_cdc_program_global_sync, + .program_p2b_config = vpe10_cdc_program_p2b_config, + .program_viewport = vpe10_cdc_program_viewport, +}; + +void vpe10_construct_cdc(struct vpe_priv *vpe_priv, struct cdc *cdc) +{ + cdc->vpe_priv = vpe_priv; + cdc->funcs = &cdc_func; +} + +bool vpe10_cdc_check_input_format(struct cdc *cdc, enum vpe_surface_pixel_format format) +{ + if (vpe_is_32bit_packed_rgb(format)) + return true; + + if (format == VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr || + format == VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb) + return true; + + if (format == VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr || + format == VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb) + return true; + + return false; +} + +bool vpe10_cdc_check_output_format(struct cdc *cdc, enum vpe_surface_pixel_format format) +{ + if (vpe_is_32bit_packed_rgb(format)) + return true; + if (vpe_is_fp16(format)) + return true; + + return false; +} + +void vpe10_cdc_program_surface_config(struct cdc *cdc, enum vpe_surface_pixel_format format, + enum vpe_rotation_angle rotation, bool horizontal_mirror, enum vpe_swizzle_mode_values swizzle) +{ + uint32_t rotation_angle = 0, surface_linear; + uint32_t surf_format = 8; + + PROGRAM_ENTRY(); + + /* Program rotation angle and horz mirror - no mirror */ + if (rotation == VPE_ROTATION_ANGLE_0) + rotation_angle = 0; + else if (rotation == VPE_ROTATION_ANGLE_90) + rotation_angle = 1; + else if (rotation == VPE_ROTATION_ANGLE_180) + rotation_angle = 2; + else if (rotation == VPE_ROTATION_ANGLE_270) + rotation_angle = 3; + + if (swizzle == VPE_SW_LINEAR) + surface_linear = 1; + else + surface_linear = 0; + + switch (format) { + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: + surf_format = 1; + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGB565: + surf_format = 3; + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_XRGB8888: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_XBGR8888: + surf_format = 8; + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBA8888: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA8888: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBX8888: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRX8888: + surf_format = 9; + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: + surf_format = 10; + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBA1010102: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA1010102: + surf_format = 11; + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: + surf_format = 22; + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: /* use crossbar */ + surf_format = 24; + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBA16161616F: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA16161616F: + surf_format = 25; + break; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: + surf_format = 65; + break; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: + surf_format = 64; + break; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: + surf_format = 67; + break; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: + surf_format = 66; + break; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_AYCbCr8888: // use crossbar + surf_format = 12; + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX: + surf_format = 112; + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX: + surf_format = 113; + break; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010: + surf_format = 114; + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT: + surf_format = 118; + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT: + surf_format = 119; + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBE: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA: + default: + vpe_log("cdc: invalid pixel format %d\n", (int)format); + break; + } + + REG_SET_4(VPCDC_FE0_SURFACE_CONFIG, 0, SURFACE_PIXEL_FORMAT_FE0, surf_format, + ROTATION_ANGLE_FE0, rotation_angle, H_MIRROR_EN_FE0, (unsigned)horizontal_mirror, + PIX_SURFACE_LINEAR_FE0, surface_linear); +} + +void vpe10_cdc_program_crossbar_config(struct cdc *cdc, enum vpe_surface_pixel_format format) +{ + uint32_t alpha_bar = (uint32_t)MUX_SEL_ALPHA; + uint32_t green_bar = (uint32_t)MUX_SEL_Y_G; + uint32_t red_bar = (uint32_t)MUX_SEL_CR_R; + uint32_t blue_bar = (uint32_t)MUX_SEL_CB_B; + + PROGRAM_ENTRY(); + + if (format == VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR8888 || + format == VPE_SURFACE_PIXEL_FORMAT_GRPH_XBGR8888 || + format == VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010 || + format == VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F || + format == VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA8888 || + format == VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRX8888 || + format == VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA1010102 || + format == VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA16161616F || + format == VPE_SURFACE_PIXEL_FORMAT_VIDEO_AYCbCr8888) { + red_bar = MUX_SEL_CB_B; + blue_bar = MUX_SEL_CR_R; + } + + REG_SET_4(VPCDC_FE0_CROSSBAR_CONFIG, 0, CROSSBAR_SRC_ALPHA_FE0, alpha_bar, + CROSSBAR_SRC_CR_R_FE0, red_bar, CROSSBAR_SRC_Y_G_FE0, green_bar, CROSSBAR_SRC_CB_B_FE0, + blue_bar); +} + +void vpe10_cdc_program_global_sync( + struct cdc *cdc, uint32_t vupdate_offset, uint32_t vupdate_width, uint32_t vready_offset) +{ + PROGRAM_ENTRY(); + + REG_SET_3(VPCDC_BE0_GLOBAL_SYNC_CONFIG, 0, BE0_VUPDATE_OFFSET, vupdate_offset, + BE0_VUPDATE_WIDTH, vupdate_width, BE0_VREADY_OFFSET, vready_offset); +} + +void vpe10_cdc_program_p2b_config(struct cdc *cdc, enum vpe_surface_pixel_format format) +{ + uint32_t bar_sel0 = (uint32_t)MUX_SEL_CB_B; + uint32_t bar_sel1 = (uint32_t)MUX_SEL_Y_G; + uint32_t bar_sel2 = (uint32_t)MUX_SEL_CR_R; + uint32_t bar_sel3 = (uint32_t)MUX_SEL_ALPHA; + uint32_t p2b_format_sel = 0; + + PROGRAM_ENTRY(); + + switch (format) { + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBA8888: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA8888: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBX8888: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRX8888: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_XRGB8888: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_XBGR8888: + p2b_format_sel = 0; + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBA1010102: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA1010102: + p2b_format_sel = 1; + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBA16161616F: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA16161616F: + p2b_format_sel = 2; + break; + default: + VPE_ASSERT(0); + break; + } + + switch (format) { + case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBA8888: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBX8888: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBA1010102: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBA16161616F: + bar_sel3 = (uint32_t)MUX_SEL_CR_R; + bar_sel2 = (uint32_t)MUX_SEL_Y_G; + bar_sel1 = (uint32_t)MUX_SEL_CB_B; + bar_sel0 = (uint32_t)MUX_SEL_ALPHA; + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_XBGR8888: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: + bar_sel3 = (uint32_t)MUX_SEL_ALPHA; + bar_sel2 = (uint32_t)MUX_SEL_CB_B; + bar_sel1 = (uint32_t)MUX_SEL_Y_G; + bar_sel0 = (uint32_t)MUX_SEL_CR_R; + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA8888: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRX8888: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA1010102: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA16161616F: + bar_sel3 = (uint32_t)MUX_SEL_CB_B; + bar_sel2 = (uint32_t)MUX_SEL_Y_G; + bar_sel1 = (uint32_t)MUX_SEL_CR_R; + bar_sel0 = (uint32_t)MUX_SEL_ALPHA; + break; + default: + break; + } + + REG_SET_5(VPCDC_BE0_P2B_CONFIG, 0, VPCDC_BE0_P2B_XBAR_SEL0, bar_sel0, VPCDC_BE0_P2B_XBAR_SEL1, + bar_sel1, VPCDC_BE0_P2B_XBAR_SEL2, bar_sel2, VPCDC_BE0_P2B_XBAR_SEL3, bar_sel3, + VPCDC_BE0_P2B_FORMAT_SEL, p2b_format_sel); +} + +/** segment specific */ +void vpe10_cdc_program_viewport( + struct cdc *cdc, const struct vpe_rect *viewport, const struct vpe_rect *viewport_c) +{ + + PROGRAM_ENTRY(); + + REG_SET_2(VPCDC_FE0_VIEWPORT_START_CONFIG, 0, VIEWPORT_X_START_FE0, viewport->x, + VIEWPORT_Y_START_FE0, viewport->y); + + REG_SET_2(VPCDC_FE0_VIEWPORT_DIMENSION_CONFIG, 0, VIEWPORT_WIDTH_FE0, viewport->width, + VIEWPORT_HEIGHT_FE0, viewport->height); + + REG_SET_2(VPCDC_FE0_VIEWPORT_START_C_CONFIG, 0, VIEWPORT_X_START_C_FE0, viewport_c->x, + VIEWPORT_Y_START_C_FE0, viewport_c->y); + + REG_SET_2(VPCDC_FE0_VIEWPORT_DIMENSION_C_CONFIG, 0, VIEWPORT_WIDTH_C_FE0, viewport_c->width, + VIEWPORT_HEIGHT_C_FE0, viewport_c->height); +} + diff --git a/src/amd/vpelib/src/chip/vpe10/vpe10_cm_common.c b/src/amd/vpelib/src/chip/vpe10/vpe10_cm_common.c new file mode 100644 index 00000000000..f892d2152de --- /dev/null +++ b/src/amd/vpelib/src/chip/vpe10/vpe10_cm_common.c @@ -0,0 +1,674 @@ +/* Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ +#include +#include +#include "vpe10_cm_common.h" +#include "custom_float.h" +#include "reg_helper.h" + +#define CTX_BASE dpp +#define CTX vpe10_dpp + +static bool cm_helper_convert_to_custom_float(struct pwl_result_data *rgb_resulted, + struct curve_points3 *corner_points, uint32_t hw_points_num, bool fixpoint) +{ + struct custom_float_format fmt = {0}; + + struct pwl_result_data *rgb = rgb_resulted; + + uint32_t i = 0; + + fmt.exponenta_bits = 6; + fmt.mantissa_bits = 12; + fmt.sign = false; + + /* corner_points[0] - beginning base, slope offset for R,G,B + * corner_points[1] - end base, slope offset for R,G,B + */ + if (!vpe_convert_to_custom_float_format( + corner_points[0].red.x, &fmt, &corner_points[0].red.custom_float_x)) { + VPE_ASSERT(0); + return false; + } + if (!vpe_convert_to_custom_float_format( + corner_points[0].green.x, &fmt, &corner_points[0].green.custom_float_x)) { + VPE_ASSERT(0); + return false; + } + if (!vpe_convert_to_custom_float_format( + corner_points[0].blue.x, &fmt, &corner_points[0].blue.custom_float_x)) { + VPE_ASSERT(0); + return false; + } + + if (!vpe_convert_to_custom_float_format( + corner_points[0].red.offset, &fmt, &corner_points[0].red.custom_float_offset)) { + VPE_ASSERT(0); + return false; + } + if (!vpe_convert_to_custom_float_format( + corner_points[0].green.offset, &fmt, &corner_points[0].green.custom_float_offset)) { + VPE_ASSERT(0); + return false; + } + if (!vpe_convert_to_custom_float_format( + corner_points[0].blue.offset, &fmt, &corner_points[0].blue.custom_float_offset)) { + VPE_ASSERT(0); + return false; + } + + if (!vpe_convert_to_custom_float_format( + corner_points[0].red.slope, &fmt, &corner_points[0].red.custom_float_slope)) { + VPE_ASSERT(0); + return false; + } + if (!vpe_convert_to_custom_float_format( + corner_points[0].green.slope, &fmt, &corner_points[0].green.custom_float_slope)) { + VPE_ASSERT(0); + return false; + } + if (!vpe_convert_to_custom_float_format( + corner_points[0].blue.slope, &fmt, &corner_points[0].blue.custom_float_slope)) { + VPE_ASSERT(0); + return false; + } + + if (fixpoint == true) { + corner_points[1].red.custom_float_y = vpe_fixpt_clamp_u0d14(corner_points[1].red.y); + corner_points[1].green.custom_float_y = vpe_fixpt_clamp_u0d14(corner_points[1].green.y); + corner_points[1].blue.custom_float_y = vpe_fixpt_clamp_u0d14(corner_points[1].blue.y); + } else { + if (!vpe_convert_to_custom_float_format( + corner_points[1].red.y, &fmt, &corner_points[1].red.custom_float_y)) { + VPE_ASSERT(0); + return false; + } + if (!vpe_convert_to_custom_float_format( + corner_points[1].green.y, &fmt, &corner_points[1].green.custom_float_y)) { + VPE_ASSERT(0); + return false; + } + if (!vpe_convert_to_custom_float_format( + corner_points[1].blue.y, &fmt, &corner_points[1].blue.custom_float_y)) { + VPE_ASSERT(0); + return false; + } + } + + fmt.mantissa_bits = 10; + fmt.sign = false; + + if (!vpe_convert_to_custom_float_format( + corner_points[1].red.x, &fmt, &corner_points[1].red.custom_float_x)) { + VPE_ASSERT(0); + return false; + } + if (!vpe_convert_to_custom_float_format( + corner_points[1].green.x, &fmt, &corner_points[1].green.custom_float_x)) { + VPE_ASSERT(0); + return false; + } + if (!vpe_convert_to_custom_float_format( + corner_points[1].blue.x, &fmt, &corner_points[1].blue.custom_float_x)) { + VPE_ASSERT(0); + return false; + } + + if (!vpe_convert_to_custom_float_format( + corner_points[1].red.slope, &fmt, &corner_points[1].red.custom_float_slope)) { + VPE_ASSERT(0); + return false; + } + if (!vpe_convert_to_custom_float_format( + corner_points[1].green.slope, &fmt, &corner_points[1].green.custom_float_slope)) { + VPE_ASSERT(0); + return false; + } + if (!vpe_convert_to_custom_float_format( + corner_points[1].blue.slope, &fmt, &corner_points[1].blue.custom_float_slope)) { + VPE_ASSERT(0); + return false; + } + + if (hw_points_num == 0 || rgb_resulted == NULL || fixpoint == true) + return true; + + fmt.mantissa_bits = 12; + + while (i != hw_points_num) { + if (!vpe_convert_to_custom_float_format(rgb->red, &fmt, &rgb->red_reg)) { + VPE_ASSERT(0); + return false; + } + + if (!vpe_convert_to_custom_float_format(rgb->green, &fmt, &rgb->green_reg)) { + VPE_ASSERT(0); + return false; + } + + if (!vpe_convert_to_custom_float_format(rgb->blue, &fmt, &rgb->blue_reg)) { + VPE_ASSERT(0); + return false; + } + + if (!vpe_convert_to_custom_float_format(rgb->delta_red, &fmt, &rgb->delta_red_reg)) { + VPE_ASSERT(0); + return false; + } + + if (!vpe_convert_to_custom_float_format(rgb->delta_green, &fmt, &rgb->delta_green_reg)) { + VPE_ASSERT(0); + return false; + } + + if (!vpe_convert_to_custom_float_format(rgb->delta_blue, &fmt, &rgb->delta_blue_reg)) { + VPE_ASSERT(0); + return false; + } + + ++rgb; + ++i; + } + + return true; +} + +/* driver uses 32 regions or less, but DCN HW has 34, extra 2 are set to 0 */ +#define MAX_REGIONS_NUMBER 34 +#define MAX_LOW_POINT 25 +#define NUMBER_REGIONS 32 +#define NUMBER_SW_SEGMENTS 16 + +bool vpe10_cm_helper_translate_curve_to_hw_format( + const struct transfer_func *output_tf, struct pwl_params *lut_params, bool fixpoint) +{ + struct curve_points3 *corner_points; + struct pwl_result_data *rgb_resulted; + struct pwl_result_data *rgb; + struct pwl_result_data *rgb_plus_1; + struct pwl_result_data *rgb_minus_1; + + int32_t region_start, region_end; + int32_t i; + uint32_t j, k, seg_distr[MAX_REGIONS_NUMBER], increment, start_index, hw_points; + + if (output_tf == NULL || lut_params == NULL || output_tf->type == TF_TYPE_BYPASS) + return false; + + corner_points = lut_params->corner_points; + rgb_resulted = lut_params->rgb_resulted; + hw_points = 0; + + memset(lut_params, 0, sizeof(struct pwl_params)); + memset(seg_distr, 0, sizeof(seg_distr)); + + if (output_tf->tf == TRANSFER_FUNC_PQ2084) { + + for (i = 0; i < MAX_LOW_POINT; i++) + seg_distr[i] = 3; + + // Extra magic point to account for incorrect programming of the lut + seg_distr[i] = 1; + region_start = -MAX_LOW_POINT; + region_end = 1; + } else if (output_tf->tf == TRANSFER_FUNC_LINEAR_0_125) { + + int num_regions_linear = MAX_LOW_POINT + 3; + + for (i = 0; i < num_regions_linear; i++) + seg_distr[i] = 3; + + region_start = -MAX_LOW_POINT; + region_end = 3; + } else { + seg_distr[0] = 3; + seg_distr[1] = 4; + seg_distr[2] = 4; + seg_distr[3] = 4; + seg_distr[4] = 4; + seg_distr[5] = 4; + seg_distr[6] = 4; + seg_distr[7] = 4; + seg_distr[8] = 4; + seg_distr[9] = 4; + seg_distr[10] = 4; + seg_distr[11] = 4; + seg_distr[12] = 1; + + region_start = -12; + region_end = 1; + } + + for (i = region_end - region_start; i < MAX_REGIONS_NUMBER; i++) + seg_distr[i] = (uint32_t)-1; + + for (k = 0; k < MAX_REGIONS_NUMBER; k++) { + if (seg_distr[k] != (uint32_t)-1) + hw_points += (1 << seg_distr[k]); + } + + j = 0; + for (k = 0; k < (uint32_t)(region_end - region_start); k++) { + increment = NUMBER_SW_SEGMENTS / (1 << seg_distr[k]); + start_index = ((uint32_t)region_start + k + MAX_LOW_POINT) * NUMBER_SW_SEGMENTS; + for (i = (int32_t)start_index; i < (int32_t)start_index + NUMBER_SW_SEGMENTS; + i += increment) { + if (j == hw_points - 1) + break; + rgb_resulted[j].red = output_tf->tf_pts.red[i]; + rgb_resulted[j].green = output_tf->tf_pts.green[i]; + rgb_resulted[j].blue = output_tf->tf_pts.blue[i]; + j++; + } + } + + /* last point */ + start_index = (uint32_t)((region_end + MAX_LOW_POINT) * NUMBER_SW_SEGMENTS); + rgb_resulted[hw_points - 1].red = output_tf->tf_pts.red[start_index]; + rgb_resulted[hw_points - 1].green = output_tf->tf_pts.green[start_index]; + rgb_resulted[hw_points - 1].blue = output_tf->tf_pts.blue[start_index]; + + rgb_resulted[hw_points].red = rgb_resulted[hw_points - 1].red; + rgb_resulted[hw_points].green = rgb_resulted[hw_points - 1].green; + rgb_resulted[hw_points].blue = rgb_resulted[hw_points - 1].blue; + + // All 3 color channels have same x + corner_points[0].red.x = vpe_fixpt_pow(vpe_fixpt_from_int(2), vpe_fixpt_from_int(region_start)); + corner_points[0].green.x = corner_points[0].red.x; + corner_points[0].blue.x = corner_points[0].red.x; + + corner_points[1].red.x = vpe_fixpt_pow(vpe_fixpt_from_int(2), vpe_fixpt_from_int(region_end)); + corner_points[1].green.x = corner_points[1].red.x; + corner_points[1].blue.x = corner_points[1].red.x; + + corner_points[0].red.y = rgb_resulted[0].red; + corner_points[0].green.y = rgb_resulted[0].green; + corner_points[0].blue.y = rgb_resulted[0].blue; + + corner_points[0].red.slope = vpe_fixpt_div(corner_points[0].red.y, corner_points[0].red.x); + corner_points[0].green.slope = + vpe_fixpt_div(corner_points[0].green.y, corner_points[0].green.x); + corner_points[0].blue.slope = vpe_fixpt_div(corner_points[0].blue.y, corner_points[0].blue.x); + + /* see comment above, m_arrPoints[1].y should be the Y value for the + * region end (m_numOfHwPoints), not last HW point(m_numOfHwPoints - 1) + */ + corner_points[1].red.y = rgb_resulted[hw_points - 1].red; + corner_points[1].green.y = rgb_resulted[hw_points - 1].green; + corner_points[1].blue.y = rgb_resulted[hw_points - 1].blue; + corner_points[1].red.slope = vpe_fixpt_zero; + corner_points[1].green.slope = vpe_fixpt_zero; + corner_points[1].blue.slope = vpe_fixpt_zero; + + lut_params->hw_points_num = hw_points; + + k = 0; + for (i = 1; i < MAX_REGIONS_NUMBER; i++) { + if (seg_distr[k] != (uint32_t)-1) { + lut_params->arr_curve_points[k].segments_num = seg_distr[k]; + lut_params->arr_curve_points[i].offset = + lut_params->arr_curve_points[k].offset + (1 << seg_distr[k]); + } + k++; + } + + if (seg_distr[k] != (uint32_t)-1) + lut_params->arr_curve_points[k].segments_num = seg_distr[k]; + + rgb = rgb_resulted; + rgb_plus_1 = rgb_resulted + 1; + rgb_minus_1 = rgb; + + i = 1; + while (i != (int32_t)(hw_points + 1)) { + if (i >= (int32_t)(hw_points - 1)) { + if (vpe_fixpt_lt(rgb_plus_1->red, rgb->red)) + rgb_plus_1->red = vpe_fixpt_add(rgb->red, rgb_minus_1->delta_red); + if (vpe_fixpt_lt(rgb_plus_1->green, rgb->green)) + rgb_plus_1->green = vpe_fixpt_add(rgb->green, rgb_minus_1->delta_green); + if (vpe_fixpt_lt(rgb_plus_1->blue, rgb->blue)) + rgb_plus_1->blue = vpe_fixpt_add(rgb->blue, rgb_minus_1->delta_blue); + } + + rgb->delta_red = vpe_fixpt_sub(rgb_plus_1->red, rgb->red); + rgb->delta_green = vpe_fixpt_sub(rgb_plus_1->green, rgb->green); + rgb->delta_blue = vpe_fixpt_sub(rgb_plus_1->blue, rgb->blue); + + if (fixpoint == true) { + rgb->delta_red_reg = vpe_fixpt_clamp_u0d10(rgb->delta_red); + rgb->delta_green_reg = vpe_fixpt_clamp_u0d10(rgb->delta_green); + rgb->delta_blue_reg = vpe_fixpt_clamp_u0d10(rgb->delta_blue); + rgb->red_reg = vpe_fixpt_clamp_u0d14(rgb->red); + rgb->green_reg = vpe_fixpt_clamp_u0d14(rgb->green); + rgb->blue_reg = vpe_fixpt_clamp_u0d14(rgb->blue); + } + + ++rgb_plus_1; + rgb_minus_1 = rgb; + ++rgb; + ++i; + } + cm_helper_convert_to_custom_float(rgb_resulted, lut_params->corner_points, hw_points, fixpoint); + + return true; +} + +#define NUM_DEGAMMA_REGIONS 9 +#define MAX_REGIONS_NUMBER_DEGAMMA 16 +#define MAX_HW_POINTS_DEGAMMA 257 + +bool vpe10_cm_helper_translate_curve_to_degamma_hw_format( + const struct transfer_func *output_tf, struct pwl_params *lut_params) +{ + struct curve_points3 *corner_points; + struct pwl_result_data *rgb_resulted; + struct pwl_result_data *rgb; + struct pwl_result_data *rgb_plus_1; + + int32_t region_start, region_end; + int32_t i; + uint32_t k, seg_distr[MAX_REGIONS_NUMBER_DEGAMMA], num_segments, hw_points; + + if (output_tf == NULL || lut_params == NULL || output_tf->type == TF_TYPE_BYPASS) + return false; + + corner_points = lut_params->corner_points; + rgb_resulted = lut_params->rgb_resulted; + num_segments = 0; + + memset(lut_params, 0, sizeof(struct pwl_params)); + memset(seg_distr, 0, sizeof(seg_distr)); + + region_start = -NUM_DEGAMMA_REGIONS; + region_end = 0; + + for (i = 0; i < MAX_HW_POINTS_DEGAMMA; i++) { + rgb_resulted[i].red = output_tf->tf_pts.red[i]; + rgb_resulted[i].green = output_tf->tf_pts.green[i]; + rgb_resulted[i].blue = output_tf->tf_pts.blue[i]; + } + + for (k = (uint32_t)(region_end - region_start); k < MAX_REGIONS_NUMBER_DEGAMMA; k++) + seg_distr[k] = (uint32_t)-1; + + /* 9 segments + * segments are from 2^-8 to 0 + */ + seg_distr[0] = 0; /* Since we only have one point in last region */ + num_segments += 1; + + for (k = 1; k < NUM_DEGAMMA_REGIONS; k++) { + seg_distr[k] = k - 1; /* Depends upon the regions' points 2^n; seg_distr = n */ + num_segments += (1 << seg_distr[k]); + } + hw_points = num_segments + 1; + + corner_points[0].red.x = vpe_fixpt_pow(vpe_fixpt_from_int(2), vpe_fixpt_from_int(region_start)); + corner_points[0].green.x = corner_points[0].red.x; + corner_points[0].blue.x = corner_points[0].red.x; + corner_points[0].red.y = rgb_resulted[0].red; + corner_points[0].green.y = rgb_resulted[0].green; + corner_points[0].blue.y = rgb_resulted[0].blue; + corner_points[0].red.slope = vpe_fixpt_div(corner_points[0].red.y, corner_points[0].red.x); + corner_points[0].green.slope = corner_points[0].red.slope; + corner_points[0].blue.slope = corner_points[0].red.slope; + + corner_points[1].red.x = vpe_fixpt_pow(vpe_fixpt_from_int(2), vpe_fixpt_from_int(region_end)); + corner_points[1].green.x = corner_points[1].red.x; + corner_points[1].blue.x = corner_points[1].red.x; + + corner_points[1].red.y = rgb_resulted[num_segments].red; + corner_points[1].green.y = rgb_resulted[num_segments].green; + corner_points[1].blue.y = rgb_resulted[num_segments].blue; + corner_points[1].red.slope = vpe_fixpt_zero; + corner_points[1].green.slope = vpe_fixpt_zero; + corner_points[1].blue.slope = vpe_fixpt_zero; + + // The number of HW points is equal to num_segments+1, however due to bug in lower layer, it + // must be set to num_segments + lut_params->hw_points_num = num_segments; + + lut_params->arr_curve_points[0].segments_num = seg_distr[0]; + for (i = 1; i < NUM_DEGAMMA_REGIONS; i++) { + lut_params->arr_curve_points[i].segments_num = seg_distr[i]; + lut_params->arr_curve_points[i].offset = + lut_params->arr_curve_points[i - 1].offset + (1 << seg_distr[i - 1]); + } + + if (seg_distr[i] != (uint32_t)-1) + lut_params->arr_curve_points[k].segments_num = seg_distr[k]; + + rgb = rgb_resulted; + rgb_plus_1 = rgb_resulted + 1; + + i = 1; + while (i != (int32_t)(hw_points)) { + if (vpe_fixpt_lt(rgb_plus_1->red, rgb->red)) + rgb_plus_1->red = rgb->red; + if (vpe_fixpt_lt(rgb_plus_1->green, rgb->green)) + rgb_plus_1->green = rgb->green; + if (vpe_fixpt_lt(rgb_plus_1->blue, rgb->blue)) + rgb_plus_1->blue = rgb->blue; + + rgb->delta_red = vpe_fixpt_sub(rgb_plus_1->red, rgb->red); + rgb->delta_green = vpe_fixpt_sub(rgb_plus_1->green, rgb->green); + rgb->delta_blue = vpe_fixpt_sub(rgb_plus_1->blue, rgb->blue); + + ++rgb_plus_1; + ++rgb; + ++i; + } + + cm_helper_convert_to_custom_float(rgb_resulted, lut_params->corner_points, hw_points, false); + + return true; +} + +void vpe10_cm_get_tf_pwl_params( + const struct transfer_func *output_tf, struct pwl_params **lut_params, enum cm_type vpe_cm_type) +{ + int table_index = 0; + + switch (output_tf->tf) { + case TRANSFER_FUNC_SRGB: + table_index = 0; + break; + case TRANSFER_FUNC_BT1886: + table_index = 1; + break; + case TRANSFER_FUNC_PQ2084: + table_index = 2; + break; + case TRANSFER_FUNC_BT709: + case TRANSFER_FUNC_LINEAR_0_125: + table_index = 3; + break; + default: + *lut_params = NULL; + return; + } + *lut_params = &tf_pwl_param_table[vpe_cm_type][table_index]; +} + +#define REG_FIELD_VALUE_CM(field, value) \ + ((uint32_t)((value) << reg->shifts.field) & reg->masks.field) +#define REG_FIELD_MASK_CM(field) reg->masks.field + +#define REG_SET_CM(reg_offset, init_val, field, val) \ + do { \ + config_writer_fill( \ + config_writer, VPEC_FIELD_VALUE(VPE_DIR_CFG_PKT_DATA_SIZE, 0) | \ + VPEC_FIELD_VALUE(VPE_DIR_CFG_PKT_REGISTER_OFFSET, reg_offset)); \ + config_writer_fill(config_writer, \ + ((init_val & ~(REG_FIELD_MASK_CM(field))) | REG_FIELD_VALUE_CM(field, val))); \ + } while (0) + +#define REG_SET_2_CM(reg_offset, init_val, f1, v1, f2, v2) \ + do { \ + config_writer_fill( \ + config_writer, VPEC_FIELD_VALUE(VPE_DIR_CFG_PKT_DATA_SIZE, 0) | \ + VPEC_FIELD_VALUE(VPE_DIR_CFG_PKT_REGISTER_OFFSET, reg_offset)); \ + config_writer_fill( \ + config_writer, ((init_val & ~(REG_FIELD_MASK_CM(f1)) & ~(REG_FIELD_MASK_CM(f2))) | \ + REG_FIELD_VALUE_CM(f1, v1) | REG_FIELD_VALUE_CM(f2, v2))); \ + } while (0) + +#define REG_SET_4_CM(reg_offset, init_val, f1, v1, f2, v2, f3, v3, f4, v4) \ + do { \ + config_writer_fill( \ + config_writer, VPEC_FIELD_VALUE(VPE_DIR_CFG_PKT_DATA_SIZE, 0) | \ + VPEC_FIELD_VALUE(VPE_DIR_CFG_PKT_REGISTER_OFFSET, reg_offset)); \ + config_writer_fill( \ + config_writer, ((init_val & ~(REG_FIELD_MASK_CM(f1)) & ~(REG_FIELD_MASK_CM(f2)) & \ + ~(REG_FIELD_MASK_CM(f3)) & ~(REG_FIELD_MASK_CM(f4))) | \ + REG_FIELD_VALUE_CM(f1, v1) | REG_FIELD_VALUE_CM(f2, v2) | \ + REG_FIELD_VALUE_CM(f3, v3) | REG_FIELD_VALUE_CM(f4, v4))); \ + } while (0) + +void vpe10_cm_helper_program_gamcor_xfer_func(struct config_writer *config_writer, + const struct pwl_params *params, const struct vpe10_xfer_func_reg *reg) +{ + // Total: 13 * 4 + (region_end - region_start + 4) = 13*4 + 68 = 120 bytes + uint32_t reg_region_cur; + unsigned int i = 0; + uint16_t packet_data_size = (uint16_t)((reg->region_end - reg->region_start + 1)); + + REG_SET_2_CM(reg->start_cntl_b, 0, exp_region_start, + params->corner_points[0].blue.custom_float_x, exp_region_start_segment, 0); + REG_SET_2_CM(reg->start_cntl_g, 0, exp_region_start, + params->corner_points[0].green.custom_float_x, exp_region_start_segment, 0); + REG_SET_2_CM(reg->start_cntl_r, 0, exp_region_start, + params->corner_points[0].red.custom_float_x, exp_region_start_segment, 0); + + REG_SET_CM(reg->start_slope_cntl_b, 0, // linear slope at start of curve + field_region_linear_slope, params->corner_points[0].blue.custom_float_slope); + REG_SET_CM(reg->start_slope_cntl_g, 0, field_region_linear_slope, + params->corner_points[0].green.custom_float_slope); + REG_SET_CM(reg->start_slope_cntl_r, 0, field_region_linear_slope, + params->corner_points[0].red.custom_float_slope); + + REG_SET_CM(reg->start_end_cntl1_b, 0, field_region_end_base, + params->corner_points[1].blue.custom_float_y); + REG_SET_CM(reg->start_end_cntl1_g, 0, field_region_end_base, + params->corner_points[1].green.custom_float_y); + REG_SET_CM(reg->start_end_cntl1_r, 0, field_region_end_base, + params->corner_points[1].red.custom_float_y); + + REG_SET_2_CM(reg->start_end_cntl2_b, 0, field_region_end_slope, + params->corner_points[1].blue.custom_float_slope, field_region_end, + params->corner_points[1].blue.custom_float_x); + REG_SET_2_CM(reg->start_end_cntl2_g, 0, field_region_end_slope, + params->corner_points[1].green.custom_float_slope, field_region_end, + params->corner_points[1].green.custom_float_x); + REG_SET_2_CM(reg->start_end_cntl2_r, 0, field_region_end_slope, + params->corner_points[1].red.custom_float_slope, field_region_end, + params->corner_points[1].red.custom_float_x); + + // program all the *GAM_RAM?_REGION_start ~ region_end regs in one VPEP_DIRECT_CONFIG packet + // with auto inc + config_writer_fill( + config_writer, VPEC_FIELD_VALUE(VPE_DIR_CFG_PKT_DATA_SIZE, packet_data_size - 1) | + VPEC_FIELD_VALUE(VPE_DIR_CFG_PKT_REGISTER_OFFSET, reg->region_start) | + 0x01); // auto increase on + + for (reg_region_cur = reg->region_start; reg_region_cur <= reg->region_end; reg_region_cur++) { + + const struct gamma_curve *curve0 = &(params->arr_curve_points[2 * i]); + const struct gamma_curve *curve1 = &(params->arr_curve_points[(2 * i) + 1]); + + config_writer_fill( + config_writer, (((curve0->offset << reg->shifts.exp_region0_lut_offset) & + reg->masks.exp_region0_lut_offset) | + ((curve0->segments_num << reg->shifts.exp_region0_num_segments) & + reg->masks.exp_region0_num_segments) | + ((curve1->offset << reg->shifts.exp_region1_lut_offset) & + reg->masks.exp_region1_lut_offset) | + ((curve1->segments_num << reg->shifts.exp_region1_num_segments) & + reg->masks.exp_region1_num_segments))); + + i++; + } +} + +void vpe10_cm_helper_program_pwl(struct config_writer *config_writer, + const struct pwl_result_data *rgb, uint32_t last_base_value, uint32_t num, + uint32_t lut_data_reg_offset, uint8_t lut_data_reg_shift, uint32_t lut_data_reg_mask, + enum cm_rgb_channel channel) +{ + uint32_t i; + uint32_t lut_data = 0; + + // For LUT, we keep write the same address with entire LUT data, so don't set INC bit + config_writer_fill( + config_writer, VPEC_FIELD_VALUE(VPE_DIR_CFG_PKT_DATA_SIZE, num) | + VPEC_FIELD_VALUE(VPE_DIR_CFG_PKT_REGISTER_OFFSET, lut_data_reg_offset)); + + for (i = 0; i < num; i++) { + switch (channel) { + case CM_PWL_R: + lut_data = rgb[i].red_reg; + break; + case CM_PWL_G: + lut_data = rgb[i].green_reg; + break; + case CM_PWL_B: + lut_data = rgb[i].blue_reg; + break; + } + config_writer_fill(config_writer, ((lut_data << lut_data_reg_shift) & lut_data_reg_mask)); + } + + config_writer_fill( + config_writer, ((last_base_value << lut_data_reg_shift) & lut_data_reg_mask)); +} + +void vpe10_cm_helper_program_color_matrices(struct config_writer *config_writer, + const uint16_t *regval, const struct color_matrices_reg *reg) +{ + uint32_t cur_csc_reg; + unsigned int i = 0; + uint16_t packet_data_size = (uint16_t)((reg->csc_c33_c34 - reg->csc_c11_c12 + 1)); + + config_writer_fill( + config_writer, VPEC_FIELD_VALUE(VPE_DIR_CFG_PKT_DATA_SIZE, packet_data_size - 1) | + VPEC_FIELD_VALUE(VPE_DIR_CFG_PKT_REGISTER_OFFSET, reg->csc_c11_c12) | + 0x01); // auto increase on + + for (cur_csc_reg = reg->csc_c11_c12; cur_csc_reg <= reg->csc_c33_c34; cur_csc_reg++) { + + const uint16_t *regval0 = &(regval[2 * i]); + const uint16_t *regval1 = &(regval[(2 * i) + 1]); + + // use C11/C12 mask value for all CSC regs to ease programing + config_writer_fill( + config_writer, ((uint32_t)(*regval0 << reg->shifts.csc_c11) & reg->masks.csc_c11) | + ((uint32_t)(*regval1 << reg->shifts.csc_c12) & reg->masks.csc_c12)); + + // Due to the program nature of CSC regs are switchable to different sets + // Skip record REG_IS_WRITTEN and LAST_WRITTEN_VAL used in REG_SET* macros. + // and those CSC regs will always write at once for all fields + + i++; + } +} diff --git a/src/amd/vpelib/src/chip/vpe10/vpe10_cmd_builder.c b/src/amd/vpelib/src/chip/vpe10/vpe10_cmd_builder.c new file mode 100644 index 00000000000..438c4dff4b0 --- /dev/null +++ b/src/amd/vpelib/src/chip/vpe10/vpe10_cmd_builder.c @@ -0,0 +1,334 @@ +/* Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ +#include "vpe_assert.h" +#include "common.h" +#include "vpe_priv.h" +#include "vpe_command.h" +#include "vpe10_cmd_builder.h" +#include "plane_desc_writer.h" +#include "reg_helper.h" + +/***** Internal helpers *****/ +static void get_np(struct vpe_priv *vpe_priv, struct vpe_cmd_info *cmd_info, int32_t *nps0, + int32_t *nps1, int32_t *npd0, int32_t *npd1); + +static enum VPE_PLANE_CFG_ELEMENT_SIZE vpe_get_element_size( + enum vpe_surface_pixel_format format, int plane_idx); + +void vpe10_construct_cmd_builder(struct vpe_priv *vpe_priv, struct cmd_builder *builder) +{ + builder->build_noops = vpe10_build_noops; + builder->build_vpe_cmd = vpe10_build_vpe_cmd; + builder->build_plane_descriptor = vpe10_build_plane_descriptor; +} + +enum vpe_status vpe10_build_noops(struct vpe_priv *vpe_priv, uint32_t **ppbuf, uint32_t num_dwords) +{ + uint32_t i; + uint32_t *buffer = *ppbuf; + uint32_t noop = VPE_CMD_HEADER(VPE_CMD_OPCODE_NOP, 0); + + for (i = 0; i < num_dwords; i++) + *buffer++ = noop; + + *ppbuf = buffer; + + return VPE_STATUS_OK; +} + +enum vpe_status vpe10_build_vpe_cmd( + struct vpe_priv *vpe_priv, struct vpe_build_bufs *cur_bufs, uint32_t cmd_idx) +{ + struct cmd_builder *builder = &vpe_priv->resource.cmd_builder; + struct vpe_buf *emb_buf = &cur_bufs->emb_buf; + struct vpe_cmd_info *cmd_info = &vpe_priv->vpe_cmd_info[cmd_idx]; + struct output_ctx *output_ctx; + struct pipe_ctx *pipe_ctx = NULL; + uint32_t i, j; + + vpe_desc_writer_init(&vpe_priv->vpe_desc_writer, &cur_bufs->cmd_buf, cmd_info->cd); + + // plane descriptor + builder->build_plane_descriptor(vpe_priv, emb_buf, cmd_idx); + + vpe_desc_writer_add_plane_desc( + &vpe_priv->vpe_desc_writer, vpe_priv->plane_desc_writer.base_gpu_va, emb_buf->tmz); + + // reclaim any pipe if the owner no longer presents + vpe_pipe_reclaim(vpe_priv, cmd_info); + + config_writer_init(&vpe_priv->config_writer, emb_buf); + + // frontend programming + for (i = 0; i < cmd_info->num_inputs; i++) { + bool reuse; + struct stream_ctx *stream_ctx; + enum vpe_cmd_type cmd_type = VPE_CMD_TYPE_COUNT; + + // keep using the same pipe whenever possible + // this would allow reuse of the previous register configs + pipe_ctx = vpe_pipe_find_owner(vpe_priv, cmd_info->inputs[i].stream_idx, &reuse); + VPE_ASSERT(pipe_ctx); + + if (!reuse) { + vpe_priv->resource.program_frontend(vpe_priv, pipe_ctx->pipe_idx, cmd_idx, i, false); + } else { + if (vpe_priv->init.debug.disable_reuse_bit) + reuse = false; + + stream_ctx = &vpe_priv->stream_ctx[cmd_info->inputs[i].stream_idx]; + + // frame specific for same type of command + if (cmd_info->ops == VPE_CMD_OPS_BG) + cmd_type = VPE_CMD_TYPE_BG; + else if (cmd_info->ops == VPE_CMD_OPS_COMPOSITING) + cmd_type = VPE_CMD_TYPE_COMPOSITING; + else if (cmd_info->ops == VPE_CMD_OPS_BG_VSCF_INPUT) + cmd_type = VPE_CMD_TYPE_BG_VSCF_INPUT; + else if (cmd_info->ops == VPE_CMD_OPS_BG_VSCF_OUTPUT) + cmd_type = VPE_CMD_TYPE_BG_VSCF_OUTPUT; + else { + VPE_ASSERT(0); + return VPE_STATUS_ERROR; + } + + // follow the same order of config generation in "non-reuse" case + // stream sharing + VPE_ASSERT(stream_ctx->num_configs); + for (j = 0; j < stream_ctx->num_configs; j++) { + vpe_desc_writer_add_config_desc(&vpe_priv->vpe_desc_writer, + stream_ctx->configs[j].config_base_addr, reuse, emb_buf->tmz); + } + + // stream-op sharing + for (j = 0; j < stream_ctx->num_stream_op_configs[cmd_type]; j++) { + vpe_desc_writer_add_config_desc(&vpe_priv->vpe_desc_writer, + stream_ctx->stream_op_configs[cmd_type][j].config_base_addr, reuse, + emb_buf->tmz); + } + + // command specific + vpe_priv->resource.program_frontend(vpe_priv, pipe_ctx->pipe_idx, cmd_idx, i, true); + } + } + + VPE_ASSERT(pipe_ctx); + + // If config writer has been crashed due to buffer overflow + if (vpe_priv->config_writer.status != VPE_STATUS_OK) { + return vpe_priv->config_writer.status; + } + + // backend programming + output_ctx = &vpe_priv->output_ctx; + if (!output_ctx->num_configs) { + vpe_priv->resource.program_backend(vpe_priv, pipe_ctx->pipe_idx, cmd_idx, false); + } else { + bool reuse = !vpe_priv->init.debug.disable_reuse_bit; + // re-use output register configs + for (j = 0; j < output_ctx->num_configs; j++) { + vpe_desc_writer_add_config_desc(&vpe_priv->vpe_desc_writer, + output_ctx->configs[j].config_base_addr, reuse, emb_buf->tmz); + } + + vpe_priv->resource.program_backend(vpe_priv, pipe_ctx->pipe_idx, cmd_idx, true); + } + + /* If writer crashed due to buffer overflow */ + if (vpe_priv->vpe_desc_writer.status != VPE_STATUS_OK) { + return vpe_priv->vpe_desc_writer.status; + } + vpe_desc_writer_complete(&vpe_priv->vpe_desc_writer); + + return VPE_STATUS_OK; +} + +enum vpe_status vpe10_build_plane_descriptor( + struct vpe_priv *vpe_priv, struct vpe_buf *buf, uint32_t cmd_idx) +{ + struct stream_ctx *stream_ctx; + struct vpe_surface_info *surface_info; + int32_t nps0, nps1, npd0, npd1; + int32_t stream_idx; + struct vpe_cmd_info *cmd_info; + PHYSICAL_ADDRESS_LOC *addrloc; + struct plane_desc_src src; + struct plane_desc_dst dst; + + cmd_info = &vpe_priv->vpe_cmd_info[cmd_idx]; + + VPE_ASSERT(cmd_info->num_inputs == 1); + + // obtains number of planes for each source/destination stream + get_np(vpe_priv, cmd_info, &nps0, &nps1, &npd0, &npd1); + + plane_desc_writer_init( + &vpe_priv->plane_desc_writer, buf, nps0, npd0, nps1, npd1, VPE_PLANE_CFG_SUBOP_1_TO_1); + + stream_idx = cmd_info->inputs[0].stream_idx; + stream_ctx = &vpe_priv->stream_ctx[stream_idx]; + surface_info = &stream_ctx->stream.surface_info; + + src.tmz = surface_info->address.tmz_surface; + src.swizzle = surface_info->swizzle; + src.rotation = stream_ctx->stream.rotation; + + if (surface_info->address.type == VPE_PLN_ADDR_TYPE_VIDEO_PROGRESSIVE) { + addrloc = &surface_info->address.video_progressive.luma_addr; + + src.base_addr_lo = addrloc->u.low_part; + src.base_addr_hi = (uint32_t)addrloc->u.high_part; + src.pitch = (uint16_t)surface_info->plane_size.surface_pitch; + src.viewport_x = (uint16_t)cmd_info->inputs[0].scaler_data.viewport.x; + src.viewport_y = (uint16_t)cmd_info->inputs[0].scaler_data.viewport.y; + src.viewport_w = (uint16_t)cmd_info->inputs[0].scaler_data.viewport.width; + src.viewport_h = (uint16_t)cmd_info->inputs[0].scaler_data.viewport.height; + src.elem_size = (uint8_t)(vpe_get_element_size(surface_info->format, 0)); + + plane_desc_writer_add_source(&vpe_priv->plane_desc_writer, &src, true); + + if (vpe_is_dual_plane_format(surface_info->format)) { + addrloc = &surface_info->address.video_progressive.chroma_addr; + + src.base_addr_lo = addrloc->u.low_part; + src.base_addr_hi = (uint32_t)addrloc->u.high_part; + src.pitch = (uint16_t)surface_info->plane_size.chroma_pitch; + src.viewport_x = (uint16_t)cmd_info->inputs[0].scaler_data.viewport_c.x; + src.viewport_y = (uint16_t)cmd_info->inputs[0].scaler_data.viewport_c.y; + src.viewport_w = (uint16_t)cmd_info->inputs[0].scaler_data.viewport_c.width; + src.viewport_h = (uint16_t)cmd_info->inputs[0].scaler_data.viewport_c.height; + src.elem_size = (uint8_t)(vpe_get_element_size(surface_info->format, 1)); + + plane_desc_writer_add_source(&vpe_priv->plane_desc_writer, &src, false); + } + } else { + addrloc = &surface_info->address.grph.addr; + + src.base_addr_lo = addrloc->u.low_part; + src.base_addr_hi = (uint32_t)addrloc->u.high_part; + src.pitch = (uint16_t)surface_info->plane_size.surface_pitch; + src.viewport_x = (uint16_t)cmd_info->inputs[0].scaler_data.viewport.x; + src.viewport_y = (uint16_t)cmd_info->inputs[0].scaler_data.viewport.y; + src.viewport_w = (uint16_t)cmd_info->inputs[0].scaler_data.viewport.width; + src.viewport_h = (uint16_t)cmd_info->inputs[0].scaler_data.viewport.height; + src.elem_size = (uint8_t)(vpe_get_element_size(surface_info->format, 0)); + + plane_desc_writer_add_source(&vpe_priv->plane_desc_writer, &src, true); + } + + surface_info = &vpe_priv->output_ctx.surface; + + VPE_ASSERT(surface_info->address.type == VPE_PLN_ADDR_TYPE_GRAPHICS); + + addrloc = &surface_info->address.grph.addr; + + dst.tmz = surface_info->address.tmz_surface; + dst.swizzle = surface_info->swizzle; + + if (stream_ctx->flip_horizonal_output) + dst.mirror = VPE_MIRROR_HORIZONTAL; + else + dst.mirror = VPE_MIRROR_NONE; + + dst.base_addr_lo = addrloc->u.low_part; + dst.base_addr_hi = (uint32_t)addrloc->u.high_part; + dst.pitch = (uint16_t)surface_info->plane_size.surface_pitch; + dst.viewport_x = (uint16_t)cmd_info->dst_viewport.x; + dst.viewport_y = (uint16_t)cmd_info->dst_viewport.y; + dst.viewport_w = (uint16_t)cmd_info->dst_viewport.width; + dst.viewport_h = (uint16_t)cmd_info->dst_viewport.height; + dst.elem_size = (uint8_t)(vpe_get_element_size(surface_info->format, 0)); + + plane_desc_writer_add_destination(&vpe_priv->plane_desc_writer, &dst, true); + + return vpe_priv->plane_desc_writer.status; +} + +static void get_np(struct vpe_priv *vpe_priv, struct vpe_cmd_info *cmd_info, int32_t *nps0, + int32_t *nps1, int32_t *npd0, int32_t *npd1) +{ + *npd1 = 0; + + if (cmd_info->num_inputs == 1) { + *nps1 = 0; + if (vpe_is_dual_plane_format( + vpe_priv->stream_ctx[cmd_info->inputs[0].stream_idx].stream.surface_info.format)) + *nps0 = VPE_PLANE_CFG_TWO_PLANES; + else + *nps0 = VPE_PLANE_CFG_ONE_PLANE; + } else if (cmd_info->num_inputs == 2) { + if (vpe_is_dual_plane_format( + vpe_priv->stream_ctx[cmd_info->inputs[0].stream_idx].stream.surface_info.format)) + *nps0 = VPE_PLANE_CFG_TWO_PLANES; + else + *nps0 = VPE_PLANE_CFG_ONE_PLANE; + + if (vpe_is_dual_plane_format( + vpe_priv->stream_ctx[cmd_info->inputs[1].stream_idx].stream.surface_info.format)) + *nps1 = VPE_PLANE_CFG_TWO_PLANES; + else + *nps1 = VPE_PLANE_CFG_ONE_PLANE; + } else { + *nps0 = 0; + *nps1 = 0; + *npd0 = 0; + return; + } + + if (vpe_is_dual_plane_format(vpe_priv->output_ctx.surface.format)) + *npd0 = 1; + else + *npd0 = 0; +} + +static enum VPE_PLANE_CFG_ELEMENT_SIZE vpe_get_element_size( + enum vpe_surface_pixel_format format, int plane_idx) +{ + switch (format) { + // nv12/21 + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: + if (plane_idx == 0) + return VPE_PLANE_CFG_ELEMENT_SIZE_8BPE; + else + return VPE_PLANE_CFG_ELEMENT_SIZE_16BPE; + // P010 + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: + if (plane_idx == 0) + return VPE_PLANE_CFG_ELEMENT_SIZE_16BPE; + else + return VPE_PLANE_CFG_ELEMENT_SIZE_32BPE; + // 64bpp + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBA16161616F: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA16161616F: + return VPE_PLANE_CFG_ELEMENT_SIZE_64BPE; + default: + break; + } + return VPE_PLANE_CFG_ELEMENT_SIZE_32BPE; +} diff --git a/src/amd/vpelib/src/chip/vpe10/vpe10_dpp.c b/src/amd/vpelib/src/chip/vpe10/vpe10_dpp.c new file mode 100644 index 00000000000..043754972d6 --- /dev/null +++ b/src/amd/vpelib/src/chip/vpe10/vpe10_dpp.c @@ -0,0 +1,434 @@ +/* Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include +#include "common.h" +#include "vpe_priv.h" +#include "vpe10_dpp.h" +#include "color.h" +#include "vpe10/inc/vpe10_cm_common.h" +#include "hw_shared.h" +#include "reg_helper.h" + +#define CTX_BASE dpp +#define CTX vpe10_dpp + +static struct dpp_funcs vpe10_dpp_funcs = { + + // cnv + .program_cnv = vpe10_dpp_program_cnv, + .program_pre_dgam = vpe10_dpp_cnv_program_pre_dgam, + .program_cnv_bias_scale = vpe10_dpp_program_cnv_bias_scale, + .program_alpha_keyer = vpe10_dpp_cnv_program_alpha_keyer, + .program_crc = vpe10_dpp_program_crc, + + // cm + .program_input_transfer_func = vpe10_dpp_program_input_transfer_func, + .program_gamut_remap = vpe10_dpp_program_gamut_remap, + .program_post_csc = vpe10_dpp_program_post_csc, + .set_hdr_multiplier = vpe10_dpp_set_hdr_multiplier, + + // scaler + .get_optimal_number_of_taps = vpe10_dpp_get_optimal_number_of_taps, + .dscl_calc_lb_num_partitions = vpe10_dscl_calc_lb_num_partitions, + .set_segment_scaler = vpe10_dpp_set_segment_scaler, + .set_frame_scaler = vpe10_dpp_set_frame_scaler, + .get_line_buffer_size = vpe10_get_line_buffer_size, + .validate_number_of_taps = vpe10_dpp_validate_number_of_taps, +}; + +void vpe10_construct_dpp(struct vpe_priv *vpe_priv, struct dpp *dpp) +{ + dpp->vpe_priv = vpe_priv; + dpp->funcs = &vpe10_dpp_funcs; +} + +bool vpe10_dpp_get_optimal_number_of_taps( + struct dpp *dpp, struct scaler_data *scl_data, const struct vpe_scaling_taps *in_taps) +{ + struct vpe_priv *vpe_priv = dpp->vpe_priv; + uint32_t h_taps_min = 0, v_taps_min = 0; + /* + * Set default taps if none are provided + * From programming guide: taps = min{ ceil(2*H_RATIO,1), 8} for downscaling + * taps = 4 for upscaling + */ + if (in_taps->h_taps > 8 || in_taps->v_taps > 8 || in_taps->h_taps_c > 8 || + in_taps->v_taps_c > 8) + return false; + + if (vpe_fixpt_ceil(scl_data->ratios.horz) > 1) + h_taps_min = (uint32_t)max(4, min(2 * vpe_fixpt_ceil(scl_data->ratios.horz), 8)); + else + h_taps_min = (uint32_t)4; + + if (in_taps->h_taps == 0) { + scl_data->taps.h_taps = h_taps_min; + } else { + if (in_taps->h_taps < h_taps_min) + return false; + + scl_data->taps.h_taps = in_taps->h_taps; + } + + if (vpe_fixpt_ceil(scl_data->ratios.vert) > 1) + v_taps_min = + (uint32_t)max(4, min(vpe_fixpt_ceil(vpe_fixpt_mul_int(scl_data->ratios.vert, 2)), 8)); + else + v_taps_min = (uint32_t)4; + + if (in_taps->v_taps == 0) { + scl_data->taps.v_taps = v_taps_min; + } else { + if (in_taps->v_taps < v_taps_min) + return false; + + scl_data->taps.v_taps = in_taps->v_taps; + } + + if (in_taps->h_taps_c == 0) { + // default to 2 as mmd only uses bilinear for chroma + scl_data->taps.h_taps_c = (uint32_t)2; + } else + scl_data->taps.h_taps_c = in_taps->h_taps_c; + + if (in_taps->v_taps_c == 0) { + // default to 2 as mmd only uses bilinear for chroma + scl_data->taps.v_taps_c = (uint32_t)2; + } else + scl_data->taps.v_taps_c = in_taps->v_taps_c; + + /* taps can be either 1 or an even number */ + if (scl_data->taps.h_taps % 2 && scl_data->taps.h_taps != 1) + scl_data->taps.h_taps++; + + if (scl_data->taps.v_taps % 2 && scl_data->taps.v_taps != 1) + scl_data->taps.v_taps++; + + if (scl_data->taps.h_taps_c % 2 && scl_data->taps.h_taps_c != 1) + scl_data->taps.h_taps_c++; + + if (scl_data->taps.v_taps_c % 2 && scl_data->taps.v_taps_c != 1) + scl_data->taps.v_taps_c++; + + // bypass scaler if all ratios are 1 + if (IDENTITY_RATIO(scl_data->ratios.horz)) + scl_data->taps.h_taps = 1; + if (IDENTITY_RATIO(scl_data->ratios.vert)) + scl_data->taps.v_taps = 1; + + return true; +} + +void vpe10_dscl_calc_lb_num_partitions(const struct scaler_data *scl_data, + enum lb_memory_config lb_config, uint32_t *num_part_y, uint32_t *num_part_c) +{ + uint32_t memory_line_size_y, memory_line_size_c, memory_line_size_a, lb_memory_size, + lb_memory_size_c, lb_memory_size_a, num_partitions_a; + + uint32_t line_size = scl_data->viewport.width < scl_data->recout.width + ? scl_data->viewport.width + : scl_data->recout.width; + uint32_t line_size_c = scl_data->viewport_c.width < scl_data->recout.width + ? scl_data->viewport_c.width + : scl_data->recout.width; + + if (line_size == 0) + line_size = 1; + + if (line_size_c == 0) + line_size_c = 1; + + memory_line_size_y = (line_size + 5) / 6; /* +5 to ceil */ + memory_line_size_c = (line_size_c + 5) / 6; /* +5 to ceil */ + memory_line_size_a = (line_size + 5) / 6; /* +5 to ceil */ + + // only has 1-piece lb config in vpe1 + lb_memory_size = 696; + lb_memory_size_c = 696; + lb_memory_size_a = 696; + + *num_part_y = lb_memory_size / memory_line_size_y; + *num_part_c = lb_memory_size_c / memory_line_size_c; + num_partitions_a = lb_memory_size_a / memory_line_size_a; + + if (scl_data->lb_params.alpha_en && (num_partitions_a < *num_part_y)) + *num_part_y = num_partitions_a; + + if (*num_part_y > 12) + *num_part_y = 12; + if (*num_part_c > 12) + *num_part_c = 12; +} + +/* Not used as we don't enable prealpha dealpha currently + * Can skip for optimize performance and use default val + */ +static void vpe10_dpp_program_prealpha_dealpha(struct dpp *dpp) +{ + uint32_t dealpha_en = 0, dealpha_ablnd_en = 0; + uint32_t realpha_en = 0, realpha_ablnd_en = 0; + uint32_t program_prealpha_dealpha = 0; + PROGRAM_ENTRY(); + + if (program_prealpha_dealpha) { + dealpha_en = 1; + realpha_en = 1; + } + REG_SET_2( + VPCNVC_PRE_DEALPHA, 0, PRE_DEALPHA_EN, dealpha_en, PRE_DEALPHA_ABLND_EN, dealpha_ablnd_en); + REG_SET_2( + VPCNVC_PRE_REALPHA, 0, PRE_REALPHA_EN, realpha_en, PRE_REALPHA_ABLND_EN, realpha_ablnd_en); +} + +/* Not used as we don't have special 2bit LUt currently + * Can skip for optimize performance and use default val + */ +static void vpe10_dpp_program_alpha_2bit_lut( + struct dpp *dpp, struct cnv_alpha_2bit_lut *alpha_2bit_lut) +{ + PROGRAM_ENTRY(); + + if (alpha_2bit_lut != NULL) { + REG_SET_4(VPCNVC_ALPHA_2BIT_LUT, 0, ALPHA_2BIT_LUT0, alpha_2bit_lut->lut0, ALPHA_2BIT_LUT1, + alpha_2bit_lut->lut1, ALPHA_2BIT_LUT2, alpha_2bit_lut->lut2, ALPHA_2BIT_LUT3, + alpha_2bit_lut->lut3); + } else { // restore to default + REG_SET_DEFAULT(VPCNVC_ALPHA_2BIT_LUT); + } +} + +void vpe10_dpp_program_cnv( + struct dpp *dpp, enum vpe_surface_pixel_format format, enum vpe_expansion_mode mode) +{ + uint32_t alpha_en = 1; + uint32_t pixel_format = 0; + uint32_t hw_expansion_mode = 0; + + PROGRAM_ENTRY(); + + switch (mode) { + case VPE_EXPANSION_MODE_DYNAMIC: + hw_expansion_mode = 0; + break; + case VPE_EXPANSION_MODE_ZERO: + hw_expansion_mode = 1; + break; + default: + VPE_ASSERT(0); + break; + } + + switch (format) { + case VPE_SURFACE_PIXEL_FORMAT_GRPH_XRGB8888: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_XBGR8888: + alpha_en = 0; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: + pixel_format = 8; + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBX8888: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRX8888: + alpha_en = 0; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBA8888: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA8888: + pixel_format = 9; + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: + pixel_format = 10; + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBA1010102: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA1010102: + pixel_format = 11; + break; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_AYCbCr8888: + pixel_format = 12; + break; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: + pixel_format = 64; + alpha_en = 0; + break; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: + pixel_format = 65; + alpha_en = 0; + break; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: + pixel_format = 66; + alpha_en = 0; + break; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: + pixel_format = 67; + alpha_en = 0; + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: + pixel_format = 22; + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: + pixel_format = 24; + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBA16161616F: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA16161616F: + pixel_format = 25; + break; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010: + pixel_format = 114; + break; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_CrYCbA1010102: + pixel_format = 115; + break; + default: + break; + } + + REG_SET(VPCNVC_SURFACE_PIXEL_FORMAT, 0, VPCNVC_SURFACE_PIXEL_FORMAT, pixel_format); + + REG_SET_7(VPCNVC_FORMAT_CONTROL, 0, FORMAT_EXPANSION_MODE, hw_expansion_mode, FORMAT_CNV16, 0, + FORMAT_CONTROL__ALPHA_EN, alpha_en, VPCNVC_BYPASS, dpp->vpe_priv->init.debug.vpcnvc_bypass, + VPCNVC_BYPASS_MSB_ALIGN, 0, CLAMP_POSITIVE, 0, CLAMP_POSITIVE_C, 0); +} + +void vpe10_dpp_program_cnv_bias_scale(struct dpp *dpp, struct bias_and_scale *bias_and_scale) +{ + PROGRAM_ENTRY(); + + REG_SET(VPCNVC_FCNV_FP_BIAS_R, 0, FCNV_FP_BIAS_R, bias_and_scale->bias_red); + REG_SET(VPCNVC_FCNV_FP_BIAS_G, 0, FCNV_FP_BIAS_G, bias_and_scale->bias_green); + REG_SET(VPCNVC_FCNV_FP_BIAS_B, 0, FCNV_FP_BIAS_B, bias_and_scale->bias_blue); + + REG_SET(VPCNVC_FCNV_FP_SCALE_R, 0, FCNV_FP_SCALE_R, bias_and_scale->scale_red); + REG_SET(VPCNVC_FCNV_FP_SCALE_G, 0, FCNV_FP_SCALE_G, bias_and_scale->scale_green); + REG_SET(VPCNVC_FCNV_FP_SCALE_B, 0, FCNV_FP_SCALE_B, bias_and_scale->scale_blue); +} + +void vpe10_dpp_cnv_program_pre_dgam(struct dpp *dpp, enum color_transfer_func tr) +{ + int pre_degam_en = 1; + int degamma_lut_selection = 0; + + PROGRAM_ENTRY(); + + switch (tr) { + case TRANSFER_FUNC_LINEAR_0_125: + pre_degam_en = 0; // bypass + break; + case TRANSFER_FUNC_SRGB: + degamma_lut_selection = 0; + break; + case TRANSFER_FUNC_BT709: + degamma_lut_selection = 4; + break; + case TRANSFER_FUNC_PQ2084: + degamma_lut_selection = 5; + break; + default: + pre_degam_en = 0; + break; + } + + REG_SET_2( + VPCNVC_PRE_DEGAM, 0, PRE_DEGAM_MODE, pre_degam_en, PRE_DEGAM_SELECT, degamma_lut_selection); +} + +void vpe10_dpp_cnv_program_alpha_keyer(struct dpp *dpp, struct cnv_color_keyer_params *color_keyer) +{ + PROGRAM_ENTRY(); + + REG_SET_2(VPCNVC_COLOR_KEYER_CONTROL, 0, COLOR_KEYER_EN, color_keyer->color_keyer_en, + COLOR_KEYER_MODE, color_keyer->color_keyer_mode); + + REG_SET_2(VPCNVC_COLOR_KEYER_ALPHA, 0, COLOR_KEYER_ALPHA_LOW, + color_keyer->color_keyer_alpha_low, COLOR_KEYER_ALPHA_HIGH, + color_keyer->color_keyer_alpha_high); + + REG_SET_2(VPCNVC_COLOR_KEYER_RED, 0, COLOR_KEYER_RED_LOW, color_keyer->color_keyer_red_low, + COLOR_KEYER_RED_HIGH, color_keyer->color_keyer_red_high); + + REG_SET_2(VPCNVC_COLOR_KEYER_GREEN, 0, COLOR_KEYER_GREEN_LOW, + color_keyer->color_keyer_green_low, COLOR_KEYER_GREEN_HIGH, + color_keyer->color_keyer_green_high); + + REG_SET_2(VPCNVC_COLOR_KEYER_BLUE, 0, COLOR_KEYER_BLUE_LOW, color_keyer->color_keyer_blue_low, + COLOR_KEYER_BLUE_HIGH, color_keyer->color_keyer_blue_high); +} + +uint32_t vpe10_get_line_buffer_size() +{ + return MAX_LINE_SIZE * MAX_LINE_CNT; +} + +bool vpe10_dpp_validate_number_of_taps(struct dpp *dpp, struct scaler_data *scl_data) +{ + uint32_t num_part_y, num_part_c; + uint32_t max_taps_y, max_taps_c; + uint32_t min_taps_y, min_taps_c; + + /*Ensure we can support the requested number of vtaps*/ + min_taps_y = (uint32_t)vpe_fixpt_ceil(scl_data->ratios.vert); + min_taps_c = (uint32_t)vpe_fixpt_ceil(scl_data->ratios.vert_c); + + dpp->funcs->dscl_calc_lb_num_partitions(scl_data, LB_MEMORY_CONFIG_1, &num_part_y, &num_part_c); + + /* MAX_V_TAPS = MIN (NUM_LINES - MAX(CEILING(V_RATIO,1)-2, 0), 8) */ + if (vpe_fixpt_ceil(scl_data->ratios.vert) > 2) + max_taps_y = num_part_y - ((uint32_t)vpe_fixpt_ceil(scl_data->ratios.vert) - 2); + else + max_taps_y = num_part_y; + + if (vpe_fixpt_ceil(scl_data->ratios.vert_c) > 2) + max_taps_c = num_part_c - ((uint32_t)vpe_fixpt_ceil(scl_data->ratios.vert_c) - 2); + else + max_taps_c = num_part_c; + + if (max_taps_y < min_taps_y) + return false; + else if (max_taps_c < min_taps_c) + return false; + + if (scl_data->taps.v_taps > max_taps_y) + scl_data->taps.v_taps = max_taps_y; + + if (scl_data->taps.v_taps_c > max_taps_c) + scl_data->taps.v_taps_c = max_taps_c; + + if (IDENTITY_RATIO(scl_data->ratios.vert)) + scl_data->taps.v_taps = 1; + + if (scl_data->taps.v_taps % 2 && scl_data->taps.v_taps != 1) + scl_data->taps.v_taps++; + + if (scl_data->taps.v_taps_c % 2 && scl_data->taps.v_taps_c != 1) + scl_data->taps.v_taps_c++; + + return true; +} + +void vpe10_dpp_program_crc(struct dpp *dpp, bool enable) +{ + PROGRAM_ENTRY(); + REG_UPDATE(VPDPP_CRC_CTRL, VPDPP_CRC_EN, enable); +} + diff --git a/src/amd/vpelib/src/chip/vpe10/vpe10_dpp_cm.c b/src/amd/vpelib/src/chip/vpe10/vpe10_dpp_cm.c new file mode 100644 index 00000000000..05b7910e566 --- /dev/null +++ b/src/amd/vpelib/src/chip/vpe10/vpe10_dpp_cm.c @@ -0,0 +1,289 @@ + +#include "vpe_priv.h" +#include "reg_helper.h" +#include "vpe10/inc/vpe10_cm_common.h" +#include "vpe10_dpp.h" +#include "conversion.h" +#include "color_pwl.h" + +#define CTX vpe10_dpp +#define CTX_BASE dpp + +static void vpe10_enable_cm_block(struct dpp *dpp) +{ + unsigned int cm_bypass_mode = 0; + + PROGRAM_ENTRY(); + + // debug option: put CM in bypass mode + if (vpe_priv->init.debug.cm_in_bypass) + cm_bypass_mode = 1; + + REG_SET(VPCM_CONTROL, 0, VPCM_BYPASS, cm_bypass_mode); +} + +static void vpe10_power_on_gamcor_lut(struct dpp *dpp, bool power_on) +{ + PROGRAM_ENTRY(); + + if (vpe_priv->init.debug.enable_mem_low_power.bits.cm) { + if (power_on) { + REG_SET_2(VPCM_MEM_PWR_CTRL, REG_DEFAULT(VPCM_MEM_PWR_CTRL), GAMCOR_MEM_PWR_DIS, 0, + GAMCOR_MEM_PWR_FORCE, 0); + + // two dummy updates (10-15clks each) for wake up delay + REG_SET_2(VPCM_MEM_PWR_CTRL, REG_DEFAULT(VPCM_MEM_PWR_CTRL), GAMCOR_MEM_PWR_DIS, 0, + GAMCOR_MEM_PWR_FORCE, 0); + REG_SET_2(VPCM_MEM_PWR_CTRL, REG_DEFAULT(VPCM_MEM_PWR_CTRL), GAMCOR_MEM_PWR_DIS, 0, + GAMCOR_MEM_PWR_FORCE, 0); + } else { + REG_SET_2(VPCM_MEM_PWR_CTRL, REG_DEFAULT(VPCM_MEM_PWR_CTRL), GAMCOR_MEM_PWR_DIS, 0, + GAMCOR_MEM_PWR_FORCE, 3); + } + } else { + REG_SET_2(VPCM_MEM_PWR_CTRL, REG_DEFAULT(VPCM_MEM_PWR_CTRL), GAMCOR_MEM_PWR_DIS, + power_on == true ? 1 : 0, GAMCOR_MEM_PWR_FORCE, 0); + } +} + +static void vpe10_configure_gamcor_lut(struct dpp *dpp) +{ + PROGRAM_ENTRY(); + + REG_SET(VPCM_GAMCOR_LUT_CONTROL, 0, VPCM_GAMCOR_LUT_WRITE_COLOR_MASK, 7); + REG_SET(VPCM_GAMCOR_LUT_INDEX, 0, VPCM_GAMCOR_LUT_INDEX, 0); +} + +static void vpe10_dpp_gamcor_reg_field(struct dpp *dpp, struct vpe10_xfer_func_reg *reg) +{ + struct vpe10_dpp *vpe10_dpp = (struct vpe10_dpp *)dpp; + + reg->shifts.field_region_start_base = + vpe10_dpp->shift->VPCM_GAMCOR_RAMA_EXP_REGION_START_BASE_B; + reg->masks.field_region_start_base = vpe10_dpp->mask->VPCM_GAMCOR_RAMA_EXP_REGION_START_BASE_B; + reg->shifts.field_offset = vpe10_dpp->shift->VPCM_GAMCOR_RAMA_OFFSET_B; + reg->masks.field_offset = vpe10_dpp->mask->VPCM_GAMCOR_RAMA_OFFSET_B; + + reg->shifts.exp_region0_lut_offset = vpe10_dpp->shift->VPCM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET; + reg->masks.exp_region0_lut_offset = vpe10_dpp->mask->VPCM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET; + reg->shifts.exp_region0_num_segments = + vpe10_dpp->shift->VPCM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS; + reg->masks.exp_region0_num_segments = + vpe10_dpp->mask->VPCM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS; + reg->shifts.exp_region1_lut_offset = vpe10_dpp->shift->VPCM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET; + reg->masks.exp_region1_lut_offset = vpe10_dpp->mask->VPCM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET; + reg->shifts.exp_region1_num_segments = + vpe10_dpp->shift->VPCM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS; + reg->masks.exp_region1_num_segments = + vpe10_dpp->mask->VPCM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS; + + reg->shifts.field_region_end = vpe10_dpp->shift->VPCM_GAMCOR_RAMA_EXP_REGION_END_B; + reg->masks.field_region_end = vpe10_dpp->mask->VPCM_GAMCOR_RAMA_EXP_REGION_END_B; + reg->shifts.field_region_end_slope = vpe10_dpp->shift->VPCM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B; + reg->masks.field_region_end_slope = vpe10_dpp->mask->VPCM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B; + reg->shifts.field_region_end_base = vpe10_dpp->shift->VPCM_GAMCOR_RAMA_EXP_REGION_END_BASE_B; + reg->masks.field_region_end_base = vpe10_dpp->mask->VPCM_GAMCOR_RAMA_EXP_REGION_END_BASE_B; + reg->shifts.field_region_linear_slope = + vpe10_dpp->shift->VPCM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B; + reg->masks.field_region_linear_slope = + vpe10_dpp->mask->VPCM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B; + reg->shifts.exp_region_start = vpe10_dpp->shift->VPCM_GAMCOR_RAMA_EXP_REGION_START_B; + reg->masks.exp_region_start = vpe10_dpp->mask->VPCM_GAMCOR_RAMA_EXP_REGION_START_B; + reg->shifts.exp_region_start_segment = + vpe10_dpp->shift->VPCM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B; + reg->masks.exp_region_start_segment = + vpe10_dpp->mask->VPCM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B; +} + +static void vpe10_dpp_program_gammcor_lut( + struct dpp *dpp, const struct pwl_result_data *rgb, uint32_t num) +{ + uint32_t last_base_value_red = rgb[num].red_reg; + uint32_t last_base_value_green = rgb[num].blue_reg; + uint32_t last_base_value_blue = rgb[num].green_reg; + + PROGRAM_ENTRY(); + + /*fill in the LUT with all base values to be used by pwl module + * HW auto increments the LUT index: back-to-back write + */ + if (vpe_is_rgb_equal(rgb, num)) { + vpe10_cm_helper_program_pwl(config_writer, rgb, last_base_value_red, num, + REG_OFFSET(VPCM_GAMCOR_LUT_DATA), REG_FIELD_SHIFT(VPCM_GAMCOR_LUT_DATA), + REG_FIELD_MASK(VPCM_GAMCOR_LUT_DATA), CM_PWL_R); + } else { + REG_UPDATE(VPCM_GAMCOR_LUT_CONTROL, VPCM_GAMCOR_LUT_WRITE_COLOR_MASK, 4); + + vpe10_cm_helper_program_pwl(config_writer, rgb, last_base_value_red, num, + REG_OFFSET(VPCM_GAMCOR_LUT_DATA), REG_FIELD_SHIFT(VPCM_GAMCOR_LUT_DATA), + REG_FIELD_MASK(VPCM_GAMCOR_LUT_DATA), CM_PWL_R); + + REG_SET(VPCM_GAMCOR_LUT_INDEX, 0, VPCM_GAMCOR_LUT_INDEX, 0); + REG_UPDATE(VPCM_GAMCOR_LUT_CONTROL, VPCM_GAMCOR_LUT_WRITE_COLOR_MASK, 2); + + vpe10_cm_helper_program_pwl(config_writer, rgb, last_base_value_green, num, + REG_OFFSET(VPCM_GAMCOR_LUT_DATA), REG_FIELD_SHIFT(VPCM_GAMCOR_LUT_DATA), + REG_FIELD_MASK(VPCM_GAMCOR_LUT_DATA), CM_PWL_G); + + REG_SET(VPCM_GAMCOR_LUT_INDEX, 0, VPCM_GAMCOR_LUT_INDEX, 0); + REG_UPDATE(VPCM_GAMCOR_LUT_CONTROL, VPCM_GAMCOR_LUT_WRITE_COLOR_MASK, 1); + + vpe10_cm_helper_program_pwl(config_writer, rgb, last_base_value_blue, num, + REG_OFFSET(VPCM_GAMCOR_LUT_DATA), REG_FIELD_SHIFT(VPCM_GAMCOR_LUT_DATA), + REG_FIELD_MASK(VPCM_GAMCOR_LUT_DATA), CM_PWL_B); + } +} + +static void vpe10_dpp_program_gamcor_lut(struct dpp *dpp, const struct pwl_params *params) +{ + struct vpe10_xfer_func_reg gam_regs = {0}; + + PROGRAM_ENTRY(); + + vpe10_enable_cm_block(dpp); + + if (dpp->vpe_priv->init.debug.bypass_gamcor || params == NULL) { + // bypass + REG_SET(VPCM_GAMCOR_CONTROL, 0, VPCM_GAMCOR_MODE, 0); + vpe10_power_on_gamcor_lut(dpp, false); + return; + } + + vpe10_power_on_gamcor_lut(dpp, true); + vpe10_configure_gamcor_lut(dpp); + + REG_SET(VPCM_GAMCOR_CONTROL, 0, VPCM_GAMCOR_MODE, 2); // programmable RAM + + gam_regs.start_cntl_b = REG_OFFSET(VPCM_GAMCOR_RAMA_START_CNTL_B); + gam_regs.start_cntl_g = REG_OFFSET(VPCM_GAMCOR_RAMA_START_CNTL_G); + gam_regs.start_cntl_r = REG_OFFSET(VPCM_GAMCOR_RAMA_START_CNTL_R); + gam_regs.start_slope_cntl_b = REG_OFFSET(VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_B); + gam_regs.start_slope_cntl_g = REG_OFFSET(VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_G); + gam_regs.start_slope_cntl_r = REG_OFFSET(VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_R); + gam_regs.start_end_cntl1_b = REG_OFFSET(VPCM_GAMCOR_RAMA_END_CNTL1_B); + gam_regs.start_end_cntl2_b = REG_OFFSET(VPCM_GAMCOR_RAMA_END_CNTL2_B); + gam_regs.start_end_cntl1_g = REG_OFFSET(VPCM_GAMCOR_RAMA_END_CNTL1_G); + gam_regs.start_end_cntl2_g = REG_OFFSET(VPCM_GAMCOR_RAMA_END_CNTL2_G); + gam_regs.start_end_cntl1_r = REG_OFFSET(VPCM_GAMCOR_RAMA_END_CNTL1_R); + gam_regs.start_end_cntl2_r = REG_OFFSET(VPCM_GAMCOR_RAMA_END_CNTL2_R); + gam_regs.region_start = REG_OFFSET(VPCM_GAMCOR_RAMA_REGION_0_1); + gam_regs.region_end = REG_OFFSET(VPCM_GAMCOR_RAMA_REGION_32_33); + gam_regs.offset_b = REG_OFFSET(VPCM_GAMCOR_RAMA_OFFSET_B); + gam_regs.offset_g = REG_OFFSET(VPCM_GAMCOR_RAMA_OFFSET_G); + gam_regs.offset_r = REG_OFFSET(VPCM_GAMCOR_RAMA_OFFSET_R); + gam_regs.start_base_cntl_b = REG_OFFSET(VPCM_GAMCOR_RAMA_START_BASE_CNTL_B); + gam_regs.start_base_cntl_g = REG_OFFSET(VPCM_GAMCOR_RAMA_START_BASE_CNTL_G); + gam_regs.start_base_cntl_r = REG_OFFSET(VPCM_GAMCOR_RAMA_START_BASE_CNTL_R); + + vpe10_dpp_gamcor_reg_field(dpp, &gam_regs); + + vpe10_cm_helper_program_gamcor_xfer_func(config_writer, params, &gam_regs); + vpe10_dpp_program_gammcor_lut(dpp, params->rgb_resulted, params->hw_points_num); +} + +void vpe10_dpp_program_input_transfer_func(struct dpp *dpp, struct transfer_func *input_tf) +{ + struct pwl_params *params = NULL; + + PROGRAM_ENTRY(); + + // There should always have input_tf + VPE_ASSERT(input_tf); + // Only accept either DISTRIBUTED_POINTS or BYPASS + // No support for PREDEFINED case + VPE_ASSERT(input_tf->type == TF_TYPE_DISTRIBUTED_POINTS || input_tf->type == TF_TYPE_BYPASS); + + // VPE always do NL scaling using gamcor, thus skipping dgam (default bypass) + // dpp->funcs->program_pre_dgam(dpp, tf); + if (input_tf->type == TF_TYPE_DISTRIBUTED_POINTS) { + if (!input_tf->use_pre_calculated_table || dpp->vpe_priv->init.debug.force_tf_calculation) { + vpe10_cm_helper_translate_curve_to_degamma_hw_format(input_tf, &dpp->degamma_params); + params = &dpp->degamma_params; + } else { + vpe10_cm_get_tf_pwl_params(input_tf, ¶ms, CM_DEGAM); + VPE_ASSERT(params != NULL); + if (params == NULL) + return; + } + } + vpe10_dpp_program_gamcor_lut(dpp, params); +} + +void vpe10_dpp_program_gamut_remap(struct dpp *dpp, struct colorspace_transform *gamut_remap) +{ + struct color_matrices_reg gam_regs; + uint16_t arr_reg_val[12]; + + PROGRAM_ENTRY(); + + if (!gamut_remap || !gamut_remap->enable_remap || + dpp->vpe_priv->init.debug.bypass_dpp_gamut_remap) { + REG_SET(VPCM_GAMUT_REMAP_CONTROL, 0, VPCM_GAMUT_REMAP_MODE, 0); + return; + } + + gam_regs.shifts.csc_c11 = REG_FIELD_SHIFT(VPCM_GAMUT_REMAP_C11); + gam_regs.masks.csc_c11 = REG_FIELD_MASK(VPCM_GAMUT_REMAP_C11); + gam_regs.shifts.csc_c12 = REG_FIELD_SHIFT(VPCM_GAMUT_REMAP_C12); + gam_regs.masks.csc_c12 = REG_FIELD_MASK(VPCM_GAMUT_REMAP_C12); + gam_regs.csc_c11_c12 = REG_OFFSET(VPCM_GAMUT_REMAP_C11_C12); + gam_regs.csc_c33_c34 = REG_OFFSET(VPCM_GAMUT_REMAP_C33_C34); + + conv_convert_float_matrix(arr_reg_val, gamut_remap->matrix, 12); + + vpe10_cm_helper_program_color_matrices(config_writer, arr_reg_val, &gam_regs); + + REG_SET(VPCM_GAMUT_REMAP_CONTROL, 0, VPCM_GAMUT_REMAP_MODE, 1); +} + +/*program post scaler scs block in dpp CM*/ +void vpe10_dpp_program_post_csc(struct dpp *dpp, enum color_space color_space, + enum input_csc_select input_select, struct vpe_csc_matrix *input_cs) +{ + PROGRAM_ENTRY(); + int i; + int arr_size = sizeof(vpe_input_csc_matrix_fixed) / sizeof(struct vpe_csc_matrix); + const uint16_t *regval = NULL; + struct color_matrices_reg gam_regs; + + if (input_select == INPUT_CSC_SELECT_BYPASS || dpp->vpe_priv->init.debug.bypass_post_csc) { + REG_SET(VPCM_POST_CSC_CONTROL, 0, VPCM_POST_CSC_MODE, 0); + return; + } + + if (input_cs == NULL) { + for (i = 0; i < arr_size; i++) + if (vpe_input_csc_matrix_fixed[i].cs == color_space) { + regval = vpe_input_csc_matrix_fixed[i].regval; + break; + } + + if (regval == NULL) { + VPE_ASSERT(0); + return; + } + } else { + regval = input_cs->regval; + } + + /* Always use the only one set of CSC matrix + */ + + gam_regs.shifts.csc_c11 = REG_FIELD_SHIFT(VPCM_POST_CSC_C11); + gam_regs.masks.csc_c11 = REG_FIELD_MASK(VPCM_POST_CSC_C11); + gam_regs.shifts.csc_c12 = REG_FIELD_SHIFT(VPCM_POST_CSC_C12); + gam_regs.masks.csc_c12 = REG_FIELD_MASK(VPCM_POST_CSC_C12); + gam_regs.csc_c11_c12 = REG_OFFSET(VPCM_POST_CSC_C11_C12); + gam_regs.csc_c33_c34 = REG_OFFSET(VPCM_POST_CSC_C33_C34); + + vpe10_cm_helper_program_color_matrices(config_writer, regval, &gam_regs); + + REG_SET(VPCM_POST_CSC_CONTROL, 0, VPCM_POST_CSC_MODE, input_select); +} + +void vpe10_dpp_set_hdr_multiplier(struct dpp *dpp, uint32_t multiplier) +{ + PROGRAM_ENTRY(); + + REG_SET(VPCM_HDR_MULT_COEF, REG_DEFAULT(VPCM_HDR_MULT_COEF), VPCM_HDR_MULT_COEF, multiplier); +} diff --git a/src/amd/vpelib/src/chip/vpe10/vpe10_dpp_dscl.c b/src/amd/vpelib/src/chip/vpe10/vpe10_dpp_dscl.c new file mode 100644 index 00000000000..efd575346d5 --- /dev/null +++ b/src/amd/vpelib/src/chip/vpe10/vpe10_dpp_dscl.c @@ -0,0 +1,383 @@ +/* Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include "vpe_priv.h" +#include "vpe10_dpp.h" + +#define CTX vpe10_dpp +#define CTX_BASE dpp + +#define NUM_PHASES 64 +#define HORZ_MAX_TAPS 8 +#define VERT_MAX_TAPS 8 + +#define LB_MAX_PARTITION 12 + +enum vpe10_coef_filter_type_sel { + SCL_COEF_LUMA_VERT_FILTER = 0, + SCL_COEF_LUMA_HORZ_FILTER = 1, + SCL_COEF_CHROMA_VERT_FILTER = 2, + SCL_COEF_CHROMA_HORZ_FILTER = 3, + SCL_COEF_ALPHA_VERT_FILTER = 4, + SCL_COEF_ALPHA_HORZ_FILTER = 5 +}; + +enum dscl_autocal_mode { + AUTOCAL_MODE_OFF = 0, + + /* Autocal calculate the scaling ratio and initial phase and the + * DSCL_MODE_SEL must be set to 1 + */ + AUTOCAL_MODE_AUTOSCALE = 1, + /* Autocal perform auto centering without replication and the + * DSCL_MODE_SEL must be set to 0 + */ + AUTOCAL_MODE_AUTOCENTER = 2, + /* Autocal perform auto centering and auto replication and the + * DSCL_MODE_SEL must be set to 0 + */ + AUTOCAL_MODE_AUTOREPLICATE = 3 +}; + +enum dscl_mode_sel { + DSCL_MODE_SCALING_444_BYPASS = 0, + DSCL_MODE_SCALING_444_RGB_ENABLE = 1, + DSCL_MODE_SCALING_444_YCBCR_ENABLE = 2, + DSCL_MODE_SCALING_420_YCBCR_ENABLE = 3, + DSCL_MODE_SCALING_420_LUMA_BYPASS = 4, + DSCL_MODE_SCALING_420_CHROMA_BYPASS = 5, + DSCL_MODE_DSCL_BYPASS = 6 +}; + +static bool dpp1_dscl_is_ycbcr(const enum vpe_surface_pixel_format format) +{ + return format >= VPE_SURFACE_PIXEL_FORMAT_VIDEO_BEGIN && + format <= VPE_SURFACE_PIXEL_FORMAT_VIDEO_END; +} + +static bool dpp1_dscl_is_video_subsampled(const enum vpe_surface_pixel_format format) +{ + return (format >= VPE_SURFACE_PIXEL_FORMAT_VIDEO_BEGIN && + format <= VPE_SURFACE_PIXEL_FORMAT_SUBSAMPLE_END); +} + +static enum dscl_mode_sel dpp1_dscl_get_dscl_mode(const struct scaler_data *data) +{ + + // TODO Check if bypass bit enabled + const long long one = vpe_fixpt_one.value; + + if (data->ratios.horz.value == one && data->ratios.vert.value == one && + data->ratios.horz_c.value == one && data->ratios.vert_c.value == one) + return DSCL_MODE_DSCL_BYPASS; + + if (!dpp1_dscl_is_ycbcr(data->format)) + return DSCL_MODE_SCALING_444_RGB_ENABLE; + + if (!dpp1_dscl_is_video_subsampled(data->format)) + return DSCL_MODE_SCALING_444_YCBCR_ENABLE; + + if (data->ratios.horz.value == one && data->ratios.vert.value == one) + return DSCL_MODE_SCALING_420_LUMA_BYPASS; + + return DSCL_MODE_SCALING_420_YCBCR_ENABLE; +} + +static void dpp1_dscl_set_dscl_mode(struct dpp *dpp, enum dscl_mode_sel dscl_mode) +{ + + PROGRAM_ENTRY(); + + REG_SET(VPDSCL_MODE, 0, VPDSCL_MODE, dscl_mode); +} + +static void dpp1_dscl_set_recout(struct dpp *dpp, const struct vpe_rect *recout) +{ + + PROGRAM_ENTRY(); + + REG_SET_2(VPDSCL_RECOUT_START, 0, RECOUT_START_X, recout->x, RECOUT_START_Y, recout->y); + + REG_SET_2(VPDSCL_RECOUT_SIZE, 0, RECOUT_WIDTH, recout->width, RECOUT_HEIGHT, recout->height); +} + +static void dpp1_dscl_set_mpc_size(struct dpp *dpp, const struct scaler_data *scl_data) +{ + + PROGRAM_ENTRY(); + + REG_SET_2(VPMPC_SIZE, 0, VPMPC_WIDTH, scl_data->h_active, VPMPC_HEIGHT, scl_data->v_active); +} + +static void dpp1_dscl_set_h_blank(struct dpp *dpp, uint16_t start, uint16_t end) +{ + + PROGRAM_ENTRY(); + REG_SET_2(VPOTG_H_BLANK, 0, OTG_H_BLANK_END, end, OTG_H_BLANK_START, start); +} + +static void dpp1_dscl_set_v_blank(struct dpp *dpp, uint16_t start, uint16_t end) +{ + + PROGRAM_ENTRY(); + REG_SET_2(VPOTG_V_BLANK, 0, OTG_V_BLANK_END, end, OTG_V_BLANK_START, start); +} + +static void dpp1_dscl_set_taps(struct dpp *dpp, const struct scaler_data *scl_data) +{ + + PROGRAM_ENTRY(); + + REG_SET_4(VPDSCL_TAP_CONTROL, 0, SCL_V_NUM_TAPS, scl_data->taps.v_taps - 1, SCL_H_NUM_TAPS, + scl_data->taps.h_taps - 1, SCL_V_NUM_TAPS_C, scl_data->taps.v_taps_c - 1, SCL_H_NUM_TAPS_C, + scl_data->taps.h_taps_c - 1); +} + +static const uint16_t *dpp1_dscl_get_filter_coeffs_64p(int taps, struct fixed31_32 ratio) +{ + if (taps == 8) + return vpe_get_filter_8tap_64p(ratio); + else if (taps == 6) + return vpe_get_filter_6tap_64p(ratio); + else if (taps == 4) + return vpe_get_filter_4tap_64p(ratio); + else if (taps == 2) + return vpe_get_2tap_bilinear_64p(); + else if (taps == 1) + return NULL; + else { + /* should never happen, bug */ + return NULL; + } +} + +static void dpp1_dscl_set_scaler_filter(struct dpp *dpp, uint32_t taps, + enum vpe10_coef_filter_type_sel filter_type, const uint16_t *filter) +{ + const int tap_pairs = (taps + 1) / 2; + int phase; + int pair; + uint16_t odd_coef, even_coef; + + PROGRAM_ENTRY(); + + REG_SET_3(VPDSCL_COEF_RAM_TAP_SELECT, 0, SCL_COEF_RAM_TAP_PAIR_IDX, 0, SCL_COEF_RAM_PHASE, 0, + SCL_COEF_RAM_FILTER_TYPE, filter_type); + + for (phase = 0; phase < (NUM_PHASES / 2 + 1); phase++) { + for (pair = 0; pair < tap_pairs; pair++) { + even_coef = filter[phase * (int)taps + 2 * pair]; + if ((pair * 2 + 1) < (int)taps) + odd_coef = filter[phase * (int)taps + 2 * pair + 1]; + else + odd_coef = 0; + + REG_SET_4(VPDSCL_COEF_RAM_TAP_DATA, 0, + /* Even tap coefficient (bits 1:0 fixed to 0) */ + SCL_COEF_RAM_EVEN_TAP_COEF, even_coef, + /* Write/read control for even coefficient */ + SCL_COEF_RAM_EVEN_TAP_COEF_EN, 1, + /* Odd tap coefficient (bits 1:0 fixed to 0) */ + SCL_COEF_RAM_ODD_TAP_COEF, odd_coef, + /* Write/read control for odd coefficient */ + SCL_COEF_RAM_ODD_TAP_COEF_EN, 1); + } + } +} + +static void dpp1_dscl_set_scl_filter(struct dpp *dpp, const struct scaler_data *scl_data, + enum dscl_mode_sel scl_mode, bool chroma_coef_mode) +{ + + const uint16_t *filter_h = NULL; + const uint16_t *filter_v = NULL; + const uint16_t *filter_h_c = NULL; + const uint16_t *filter_v_c = NULL; + + PROGRAM_ENTRY(); + + if (scl_data->polyphase_filter_coeffs == 0) /*no externally provided set of coeffs and taps*/ + { + filter_h = (uint16_t *)dpp1_dscl_get_filter_coeffs_64p( + (int)scl_data->taps.h_taps, scl_data->ratios.horz); + filter_v = + dpp1_dscl_get_filter_coeffs_64p((int)scl_data->taps.v_taps, scl_data->ratios.vert); + } else { + filter_h = (const uint16_t *)&scl_data->polyphase_filter_coeffs->horiz_polyphase_coeffs; + filter_v = (const uint16_t *)&scl_data->polyphase_filter_coeffs->vert_polyphase_coeffs; + } + if (filter_h != NULL) + dpp1_dscl_set_scaler_filter( + dpp, scl_data->taps.h_taps, SCL_COEF_LUMA_HORZ_FILTER, filter_h); + + if (filter_v != NULL) + dpp1_dscl_set_scaler_filter( + dpp, scl_data->taps.v_taps, SCL_COEF_LUMA_VERT_FILTER, filter_v); + + if (chroma_coef_mode) { + + filter_h_c = + dpp1_dscl_get_filter_coeffs_64p((int)scl_data->taps.h_taps_c, scl_data->ratios.horz_c); + filter_v_c = + dpp1_dscl_get_filter_coeffs_64p((int)scl_data->taps.v_taps_c, scl_data->ratios.vert_c); + + if (filter_h_c != NULL) + dpp1_dscl_set_scaler_filter( + dpp, scl_data->taps.h_taps_c, SCL_COEF_CHROMA_HORZ_FILTER, filter_h_c); + + if (filter_v_c != NULL) + dpp1_dscl_set_scaler_filter( + dpp, scl_data->taps.v_taps_c, SCL_COEF_CHROMA_VERT_FILTER, filter_v_c); + } + + REG_UPDATE(VPDSCL_MODE, SCL_CHROMA_COEF_MODE, chroma_coef_mode); +} + +static void dpp1_dscl_set_lb(struct dpp *dpp, const struct line_buffer_params *lb_params, + enum lb_memory_config mem_size_config) +{ + + PROGRAM_ENTRY(); + + REG_SET(VPLB_DATA_FORMAT, 0, ALPHA_EN, lb_params->alpha_en); /* Alpha enable */ + + REG_SET_2( + VPLB_MEMORY_CTRL, 0, MEMORY_CONFIG, mem_size_config, LB_MAX_PARTITIONS, LB_MAX_PARTITION); +} + +static void dpp1_dscl_set_scale_ratio(struct dpp *dpp, const struct scaler_data *data) +{ + + PROGRAM_ENTRY(); + + REG_SET(VPDSCL_HORZ_FILTER_SCALE_RATIO, 0, SCL_H_SCALE_RATIO, + vpe_fixpt_u3d19(data->ratios.horz) << 5); + + REG_SET(VPDSCL_VERT_FILTER_SCALE_RATIO, 0, SCL_V_SCALE_RATIO, + vpe_fixpt_u3d19(data->ratios.vert) << 5); + + REG_SET(VPDSCL_HORZ_FILTER_SCALE_RATIO_C, 0, SCL_H_SCALE_RATIO_C, + vpe_fixpt_u3d19(data->ratios.horz_c) << 5); + + REG_SET(VPDSCL_VERT_FILTER_SCALE_RATIO_C, 0, SCL_V_SCALE_RATIO_C, + vpe_fixpt_u3d19(data->ratios.vert_c) << 5); +} + +static void dpp1_dscl_set_scaler_position(struct dpp *dpp, const struct scaler_data *data) +{ + uint32_t init_frac = 0; + uint32_t init_int = 0; + + PROGRAM_ENTRY(); + + /* + * 0.24 format for fraction, first five bits zeroed + */ + init_frac = vpe_fixpt_u0d19(data->inits.h) << 5; + init_int = (uint32_t)vpe_fixpt_floor(data->inits.h); + REG_SET_2(VPDSCL_HORZ_FILTER_INIT, 0, SCL_H_INIT_FRAC, init_frac, SCL_H_INIT_INT, init_int); + + init_frac = vpe_fixpt_u0d19(data->inits.h_c) << 5; + init_int = (uint32_t)vpe_fixpt_floor(data->inits.h_c); + REG_SET_2( + VPDSCL_HORZ_FILTER_INIT_C, 0, SCL_H_INIT_FRAC_C, init_frac, SCL_H_INIT_INT_C, init_int); + + init_frac = vpe_fixpt_u0d19(data->inits.v) << 5; + init_int = (uint32_t)vpe_fixpt_floor(data->inits.v); + REG_SET_2(VPDSCL_VERT_FILTER_INIT, 0, SCL_V_INIT_FRAC, init_frac, SCL_V_INIT_INT, init_int); + + init_frac = vpe_fixpt_u0d19(data->inits.v_c) << 5; + init_int = (uint32_t)vpe_fixpt_floor(data->inits.v_c); + REG_SET_2( + VPDSCL_VERT_FILTER_INIT_C, 0, SCL_V_INIT_FRAC_C, init_frac, SCL_V_INIT_INT_C, init_int); +} + +static void dpp1_power_on_dscl(struct dpp *dpp, bool power_on) +{ + PROGRAM_ENTRY(); + + if (dpp->vpe_priv->init.debug.enable_mem_low_power.bits.dscl) { + if (power_on) { + REG_SET_2(VPDSCL_MEM_PWR_CTRL, REG_DEFAULT(VPDSCL_MEM_PWR_CTRL), LUT_MEM_PWR_DIS, 0, + LUT_MEM_PWR_FORCE, 0); + + // introduce a delay by dummy set + REG_SET_2(VPDSCL_MEM_PWR_CTRL, REG_DEFAULT(VPDSCL_MEM_PWR_CTRL), LUT_MEM_PWR_DIS, 0, + LUT_MEM_PWR_FORCE, 0); + + REG_SET_2(VPDSCL_MEM_PWR_CTRL, REG_DEFAULT(VPDSCL_MEM_PWR_CTRL), LUT_MEM_PWR_DIS, 0, + LUT_MEM_PWR_FORCE, 0); + } else { + REG_SET_2(VPDSCL_MEM_PWR_CTRL, REG_DEFAULT(VPDSCL_MEM_PWR_CTRL), LUT_MEM_PWR_DIS, 0, + LUT_MEM_PWR_FORCE, 3); + } + } else { + if (power_on) { + REG_SET_2(VPDSCL_MEM_PWR_CTRL, REG_DEFAULT(VPDSCL_MEM_PWR_CTRL), LUT_MEM_PWR_DIS, 1, + LUT_MEM_PWR_FORCE, 0); + } else { + REG_SET_2(VPDSCL_MEM_PWR_CTRL, REG_DEFAULT(VPDSCL_MEM_PWR_CTRL), LUT_MEM_PWR_DIS, 0, + LUT_MEM_PWR_FORCE, 0); + } + } +} + +void vpe10_dpp_set_segment_scaler(struct dpp *dpp, const struct scaler_data *scl_data) +{ + + enum dscl_mode_sel dscl_mode = dpp1_dscl_get_dscl_mode(scl_data); + + dpp1_dscl_set_recout(dpp, &scl_data->recout); + dpp1_dscl_set_mpc_size(dpp, scl_data); + + if (dscl_mode == DSCL_MODE_DSCL_BYPASS) + return; + + dpp1_dscl_set_scaler_position(dpp, scl_data); +} + +void vpe10_dpp_set_frame_scaler(struct dpp *dpp, const struct scaler_data *scl_data) +{ + + enum dscl_mode_sel dscl_mode = dpp1_dscl_get_dscl_mode(scl_data); + bool ycbcr = dpp1_dscl_is_ycbcr(scl_data->format); + + dpp1_dscl_set_h_blank(dpp, 1, 0); + dpp1_dscl_set_v_blank(dpp, 1, 0); + + if (dscl_mode != DSCL_MODE_DSCL_BYPASS) + dpp1_power_on_dscl(dpp, true); + + dpp1_dscl_set_dscl_mode(dpp, dscl_mode); + + if (dscl_mode == DSCL_MODE_DSCL_BYPASS) { + dpp1_power_on_dscl(dpp, false); + return; + } + + dpp1_dscl_set_lb(dpp, &scl_data->lb_params, LB_MEMORY_CONFIG_0); + dpp1_dscl_set_scale_ratio(dpp, scl_data); + dpp1_dscl_set_taps(dpp, scl_data); + dpp1_dscl_set_scl_filter(dpp, scl_data, dscl_mode, ycbcr); +} diff --git a/src/amd/vpelib/src/chip/vpe10/vpe10_mpc.c b/src/amd/vpelib/src/chip/vpe10/vpe10_mpc.c new file mode 100644 index 00000000000..a103027e06e --- /dev/null +++ b/src/amd/vpelib/src/chip/vpe10/vpe10_mpc.c @@ -0,0 +1,1321 @@ +/* Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ +#include "vpe_assert.h" +#include "common.h" +#include "vpe_priv.h" +#include "vpe10_mpc.h" +#include "reg_helper.h" +#include "vpe10_cm_common.h" +#include "fixed31_32.h" +#include "conversion.h" +#include "color_pwl.h" + +#define CTX_BASE mpc +#define CTX vpe10_mpc + +static struct mpc_funcs mpc_funcs = { + .program_mpcc_mux = vpe10_mpc_program_mpcc_mux, + .program_mpcc_blending = vpe10_mpc_program_mpcc_blending, + .program_mpc_bypass_bg_color = vpe10_mpc_program_mpc_bypass_bg_color, + .power_on_ogam_lut = vpe10_mpc_power_on_ogam_lut, + .set_output_csc = vpe10_mpc_set_output_csc, + .set_ocsc_default = vpe10_mpc_set_ocsc_default, + .program_output_csc = vpe10_program_output_csc, + .set_output_gamma = vpe10_mpc_set_output_gamma, + .set_gamut_remap = vpe10_mpc_set_gamut_remap, + .power_on_1dlut_shaper_3dlut = vpe10_mpc_power_on_1dlut_shaper_3dlut, + .program_shaper = vpe10_mpc_program_shaper, + .program_3dlut = vpe10_mpc_program_3dlut, + .program_3dlut_indirect = vpe10_mpc_program_3dlut_indirect, + .program_1dlut = vpe10_mpc_program_1dlut, + .program_cm_location = vpe10_mpc_program_cm_location, + .set_denorm = vpe10_mpc_set_denorm, + .set_out_float_en = vpe10_mpc_set_out_float_en, + .program_mpc_out = vpe10_mpc_program_mpc_out, + .set_output_transfer_func = vpe10_mpc_set_output_transfer_func, + .set_mpc_shaper_3dlut = vpe10_mpc_set_mpc_shaper_3dlut, + .set_blend_lut = vpe10_mpc_set_blend_lut, + .program_movable_cm = vpe10_mpc_program_movable_cm, + .program_crc = vpe10_mpc_program_crc, +}; + +void vpe10_construct_mpc(struct vpe_priv *vpe_priv, struct mpc *mpc) +{ + mpc->vpe_priv = vpe_priv; + mpc->funcs = &mpc_funcs; +} + +void vpe10_mpc_program_mpcc_mux(struct mpc *mpc, enum mpc_mpccid mpcc_idx, + enum mpc_mux_topsel topsel, enum mpc_mux_botsel botsel, enum mpc_mux_outmux outmux, + enum mpc_mux_oppid oppid) +{ + PROGRAM_ENTRY(); + + VPE_ASSERT(mpcc_idx == MPC_MPCCID_0); + + REG_SET(VPMPCC_TOP_SEL, 0, VPMPCC_TOP_SEL, topsel); + REG_SET(VPMPCC_BOT_SEL, 0, VPMPCC_BOT_SEL, botsel); + REG_SET(VPMPC_OUT0_MUX, 0, VPMPC_OUT_MUX, outmux); + REG_SET(VPMPCC_VPOPP_ID, 0, VPMPCC_VPOPP_ID, oppid); + + /* program mux and MPCC_MODE */ + if (mpc->vpe_priv->init.debug.mpc_bypass) { + REG_UPDATE(VPMPCC_CONTROL, VPMPCC_MODE, MPCC_BLEND_MODE_BYPASS); + } else if (botsel != MPC_MUX_BOTSEL_DISABLE) { + // ERROR: Actually VPE10 only supports 1 MPCC so botsel should always disable + VPE_ASSERT(0); + REG_UPDATE(VPMPCC_CONTROL, VPMPCC_MODE, MPCC_BLEND_MODE_TOP_BOT_BLENDING); + } else { + // single layer, use Top layer bleneded with background color + if (topsel != MPC_MUX_TOPSEL_DISABLE) + REG_UPDATE(VPMPCC_CONTROL, VPMPCC_MODE, MPCC_BLEND_MODE_TOP_LAYER_ONLY); + else // both layer disabled, pure bypass mode + REG_UPDATE(VPMPCC_CONTROL, VPMPCC_MODE, MPCC_BLEND_MODE_BYPASS); + } +} + +void vpe10_mpc_program_mpcc_blending( + struct mpc *mpc, enum mpc_mpccid mpcc_idx, struct mpcc_blnd_cfg *blnd_cfg) +{ + PROGRAM_ENTRY(); + float r_cr, g_y, b_cb; + uint32_t bg_r_cr, bg_g_y, bg_b_cb; + uint32_t factor; + + VPE_ASSERT(mpcc_idx == MPC_MPCCID_0); + + REG_UPDATE_7(VPMPCC_CONTROL, VPMPCC_ALPHA_BLND_MODE, blnd_cfg->alpha_mode, + VPMPCC_ALPHA_MULTIPLIED_MODE, blnd_cfg->pre_multiplied_alpha, + VPMPCC_BLND_ACTIVE_OVERLAP_ONLY, blnd_cfg->overlap_only, VPMPCC_GLOBAL_ALPHA, + blnd_cfg->global_alpha, VPMPCC_GLOBAL_GAIN, blnd_cfg->global_gain, VPMPCC_BG_BPC, + blnd_cfg->background_color_bpc, VPMPCC_BOT_GAIN_MODE, blnd_cfg->bottom_gain_mode); + + REG_SET(VPMPCC_TOP_GAIN, 0, VPMPCC_TOP_GAIN, blnd_cfg->top_gain); + REG_SET(VPMPCC_BOT_GAIN_INSIDE, 0, VPMPCC_BOT_GAIN_INSIDE, blnd_cfg->bottom_inside_gain); + REG_SET(VPMPCC_BOT_GAIN_OUTSIDE, 0, VPMPCC_BOT_GAIN_OUTSIDE, blnd_cfg->bottom_outside_gain); + + if (blnd_cfg->bg_color.is_ycbcr) { + r_cr = blnd_cfg->bg_color.ycbcra.cr; + g_y = blnd_cfg->bg_color.ycbcra.y; + b_cb = blnd_cfg->bg_color.ycbcra.cb; + } else { + r_cr = blnd_cfg->bg_color.rgba.r; + g_y = blnd_cfg->bg_color.rgba.g; + b_cb = blnd_cfg->bg_color.rgba.b; + } + + switch (blnd_cfg->background_color_bpc) { + case 0: // 8bit + factor = 0xff; + break; + case 1: // 9bit + factor = 0x1ff; + break; + case 2: // 10bit + factor = 0x3ff; + break; + case 3: // 11bit + factor = 0x7ff; + break; + case 4: // 12bit + default: + factor = 0xfff; + break; + } + bg_r_cr = (uint32_t)(r_cr * (float)factor); + bg_b_cb = (uint32_t)(b_cb * (float)factor); + bg_g_y = (uint32_t)(g_y * (float)factor); + + // Set background color + REG_SET(VPMPCC_BG_R_CR, 0, VPMPCC_BG_R_CR, bg_r_cr); + REG_SET(VPMPCC_BG_G_Y, 0, VPMPCC_BG_G_Y, bg_g_y); + REG_SET(VPMPCC_BG_B_CB, 0, VPMPCC_BG_B_CB, bg_b_cb); +} + +void vpe10_mpc_program_mpc_bypass_bg_color(struct mpc *mpc, struct mpcc_blnd_cfg *blnd_cfg) +{ + PROGRAM_ENTRY(); + float r_cr, g_y, b_cb, alpha; + uint32_t bg_r_cr, bg_g_y, bg_b_cb, bg_alpha; + + if (blnd_cfg->bg_color.is_ycbcr) { + r_cr = blnd_cfg->bg_color.ycbcra.cr; + g_y = blnd_cfg->bg_color.ycbcra.y; + b_cb = blnd_cfg->bg_color.ycbcra.cb; + alpha = blnd_cfg->bg_color.ycbcra.a; + } else { + r_cr = blnd_cfg->bg_color.rgba.r; + g_y = blnd_cfg->bg_color.rgba.g; + b_cb = blnd_cfg->bg_color.rgba.b; + alpha = blnd_cfg->bg_color.rgba.a; + } + + bg_r_cr = (uint32_t)(r_cr * 0xffff); + bg_g_y = (uint32_t)(g_y * 0xffff); + bg_b_cb = (uint32_t)(b_cb * 0xffff); + bg_alpha = (uint32_t)(alpha * 0xffff); + + // Set background color + REG_SET(VPMPC_BYPASS_BG_AR, 0, VPMPC_BYPASS_BG_ALPHA, bg_alpha); + REG_SET(VPMPC_BYPASS_BG_AR, 0, VPMPC_BYPASS_BG_R_CR, bg_r_cr); + REG_SET(VPMPC_BYPASS_BG_GB, 0, VPMPC_BYPASS_BG_G_Y, bg_g_y); + REG_SET(VPMPC_BYPASS_BG_GB, 0, VPMPC_BYPASS_BG_B_CB, bg_b_cb); +} + +void vpe10_mpc_power_on_ogam_lut(struct mpc *mpc, bool power_on) +{ + PROGRAM_ENTRY(); + + /* + * Powering on: force memory active so the LUT can be updated. + * Powering off: allow entering memory low power mode + * + * Memory low power mode is controlled during MPC OGAM LUT init. + */ + REG_UPDATE(VPMPCC_MEM_PWR_CTRL, VPMPCC_OGAM_MEM_PWR_DIS, power_on ? 1 : 0); + + /* Wait for memory to be powered on - we won't be able to write to it otherwise. */ + if (power_on) { + // dummy write as delay in power up + REG_UPDATE(VPMPCC_MEM_PWR_CTRL, VPMPCC_OGAM_MEM_PWR_DIS, power_on ? 1 : 0); + REG_UPDATE(VPMPCC_MEM_PWR_CTRL, VPMPCC_OGAM_MEM_PWR_DIS, power_on ? 1 : 0); + } +} + +void vpe10_mpc_set_output_csc( + struct mpc *mpc, const uint16_t *regval, enum mpc_output_csc_mode ocsc_mode) +{ + PROGRAM_ENTRY(); + struct color_matrices_reg ocsc_regs; + + REG_SET(VPMPC_OUT_CSC_COEF_FORMAT, 0, VPMPC_OCSC0_COEF_FORMAT, 0); + REG_SET(VPMPC_OUT0_CSC_MODE, 0, VPMPC_OCSC_MODE, ocsc_mode); + + if (ocsc_mode == MPC_OUTPUT_CSC_DISABLE) + return; + + if (regval == NULL) + return; + + ocsc_regs.shifts.csc_c11 = REG_FIELD_SHIFT(VPMPC_OCSC_C11_A); + ocsc_regs.masks.csc_c11 = REG_FIELD_MASK(VPMPC_OCSC_C11_A); + ocsc_regs.shifts.csc_c12 = REG_FIELD_SHIFT(VPMPC_OCSC_C12_A); + ocsc_regs.masks.csc_c12 = REG_FIELD_MASK(VPMPC_OCSC_C12_A); + + if (ocsc_mode == MPC_OUTPUT_CSC_COEF_A) { + ocsc_regs.csc_c11_c12 = REG_OFFSET(VPMPC_OUT0_CSC_C11_C12_A); + ocsc_regs.csc_c33_c34 = REG_OFFSET(VPMPC_OUT0_CSC_C33_C34_A); + } else { + VPE_ASSERT(0); + return; + } + + vpe10_cm_helper_program_color_matrices(config_writer, regval, &ocsc_regs); +} + +void vpe10_mpc_set_ocsc_default(struct mpc *mpc, enum vpe_surface_pixel_format pixel_format, + enum color_space color_space, enum mpc_output_csc_mode ocsc_mode) +{ + PROGRAM_ENTRY(); + struct color_matrices_reg ocsc_regs; + uint32_t arr_size; + const uint16_t *regval = NULL; + + REG_SET(VPMPC_OUT_CSC_COEF_FORMAT, 0, VPMPC_OCSC0_COEF_FORMAT, 0); + REG_SET(VPMPC_OUT0_CSC_MODE, 0, VPMPC_OCSC_MODE, ocsc_mode); + + if (ocsc_mode == MPC_OUTPUT_CSC_DISABLE) + return; + + regval = vpe_find_color_matrix(color_space, pixel_format, &arr_size); + if (regval == NULL) + return; + + ocsc_regs.shifts.csc_c11 = REG_FIELD_SHIFT(VPMPC_OCSC_C11_A); + ocsc_regs.masks.csc_c11 = REG_FIELD_MASK(VPMPC_OCSC_C11_A); + ocsc_regs.shifts.csc_c12 = REG_FIELD_SHIFT(VPMPC_OCSC_C12_A); + ocsc_regs.masks.csc_c12 = REG_FIELD_MASK(VPMPC_OCSC_C12_A); + + if (ocsc_mode == MPC_OUTPUT_CSC_COEF_A) { + ocsc_regs.csc_c11_c12 = REG_OFFSET(VPMPC_OUT0_CSC_C11_C12_A); + ocsc_regs.csc_c33_c34 = REG_OFFSET(VPMPC_OUT0_CSC_C33_C34_A); + } else { + VPE_ASSERT(0); + return; + } + + vpe10_cm_helper_program_color_matrices(config_writer, regval, &ocsc_regs); +} + +void vpe10_program_output_csc(struct mpc *mpc, enum vpe_surface_pixel_format pixel_format, + enum color_space colorspace, uint16_t *matrix) +{ + PROGRAM_ENTRY(); + + enum mpc_output_csc_mode ocsc_mode = MPC_OUTPUT_CSC_COEF_A; + + if (mpc->funcs->power_on_ogam_lut) + mpc->funcs->power_on_ogam_lut(mpc, true); + + if (matrix != NULL) { + if (mpc->funcs->set_output_csc != NULL) + mpc->funcs->set_output_csc(mpc, matrix, ocsc_mode); + } else { + if (mpc->funcs->set_ocsc_default != NULL) + mpc->funcs->set_ocsc_default(mpc, pixel_format, colorspace, ocsc_mode); + } +} + +enum vpmpcc_ogam_mode { + VPMPCC_OGAM_DISABLE, + VPMPCC_OGAM_RESERVED1, + VPMPCC_OGAM_RAMLUT, + VPMPCC_OGAM_RESERVED2 +}; + +enum mpcc_ogam_lut_host_sel { + RAM_LUT_A, + // RAM_LUT_B, +}; + +static void vpe10_mpc_ogam_get_reg_field(struct mpc *mpc, struct vpe10_xfer_func_reg *reg) +{ + struct vpe10_mpc *vpe10_mpc = (struct vpe10_mpc *)mpc; + + reg->shifts.field_region_start_base = + vpe10_mpc->shift->VPMPCC_OGAM_RAMA_EXP_REGION_START_BASE_B; + reg->masks.field_region_start_base = vpe10_mpc->mask->VPMPCC_OGAM_RAMA_EXP_REGION_START_BASE_B; + reg->shifts.field_offset = vpe10_mpc->shift->VPMPCC_OGAM_RAMA_OFFSET_B; + reg->masks.field_offset = vpe10_mpc->mask->VPMPCC_OGAM_RAMA_OFFSET_B; + + reg->shifts.exp_region0_lut_offset = vpe10_mpc->shift->VPMPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET; + reg->masks.exp_region0_lut_offset = vpe10_mpc->mask->VPMPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET; + reg->shifts.exp_region0_num_segments = + vpe10_mpc->shift->VPMPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; + reg->masks.exp_region0_num_segments = + vpe10_mpc->mask->VPMPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; + reg->shifts.exp_region1_lut_offset = vpe10_mpc->shift->VPMPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET; + reg->masks.exp_region1_lut_offset = vpe10_mpc->mask->VPMPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET; + reg->shifts.exp_region1_num_segments = + vpe10_mpc->shift->VPMPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; + reg->masks.exp_region1_num_segments = + vpe10_mpc->mask->VPMPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; + + reg->shifts.field_region_end = vpe10_mpc->shift->VPMPCC_OGAM_RAMA_EXP_REGION_END_B; + reg->masks.field_region_end = vpe10_mpc->mask->VPMPCC_OGAM_RAMA_EXP_REGION_END_B; + reg->shifts.field_region_end_slope = vpe10_mpc->shift->VPMPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B; + reg->masks.field_region_end_slope = vpe10_mpc->mask->VPMPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B; + reg->shifts.field_region_end_base = vpe10_mpc->shift->VPMPCC_OGAM_RAMA_EXP_REGION_END_BASE_B; + reg->masks.field_region_end_base = vpe10_mpc->mask->VPMPCC_OGAM_RAMA_EXP_REGION_END_BASE_B; + reg->shifts.field_region_linear_slope = + vpe10_mpc->shift->VPMPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B; + reg->masks.field_region_linear_slope = + vpe10_mpc->mask->VPMPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B; + reg->shifts.exp_region_start = vpe10_mpc->shift->VPMPCC_OGAM_RAMA_EXP_REGION_START_B; + reg->masks.exp_region_start = vpe10_mpc->mask->VPMPCC_OGAM_RAMA_EXP_REGION_START_B; + reg->shifts.exp_region_start_segment = + vpe10_mpc->shift->VPMPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B; + reg->masks.exp_region_start_segment = + vpe10_mpc->mask->VPMPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B; +} + +static void vpe10_mpc_program_luta(struct mpc *mpc, const struct pwl_params *params) +{ + PROGRAM_ENTRY(); + + struct vpe10_xfer_func_reg gam_regs; + + vpe10_mpc_ogam_get_reg_field(mpc, &gam_regs); + + gam_regs.start_cntl_b = REG_OFFSET(VPMPCC_OGAM_RAMA_START_CNTL_B); + gam_regs.start_cntl_g = REG_OFFSET(VPMPCC_OGAM_RAMA_START_CNTL_G); + gam_regs.start_cntl_r = REG_OFFSET(VPMPCC_OGAM_RAMA_START_CNTL_R); + gam_regs.start_slope_cntl_b = REG_OFFSET(VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_B); + gam_regs.start_slope_cntl_g = REG_OFFSET(VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_G); + gam_regs.start_slope_cntl_r = REG_OFFSET(VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_R); + gam_regs.start_end_cntl1_b = REG_OFFSET(VPMPCC_OGAM_RAMA_END_CNTL1_B); + gam_regs.start_end_cntl2_b = REG_OFFSET(VPMPCC_OGAM_RAMA_END_CNTL2_B); + gam_regs.start_end_cntl1_g = REG_OFFSET(VPMPCC_OGAM_RAMA_END_CNTL1_G); + gam_regs.start_end_cntl2_g = REG_OFFSET(VPMPCC_OGAM_RAMA_END_CNTL2_G); + gam_regs.start_end_cntl1_r = REG_OFFSET(VPMPCC_OGAM_RAMA_END_CNTL1_R); + gam_regs.start_end_cntl2_r = REG_OFFSET(VPMPCC_OGAM_RAMA_END_CNTL2_R); + gam_regs.region_start = REG_OFFSET(VPMPCC_OGAM_RAMA_REGION_0_1); + gam_regs.region_end = REG_OFFSET(VPMPCC_OGAM_RAMA_REGION_32_33); + gam_regs.offset_b = REG_OFFSET(VPMPCC_OGAM_RAMA_OFFSET_B); + gam_regs.offset_g = REG_OFFSET(VPMPCC_OGAM_RAMA_OFFSET_G); + gam_regs.offset_r = REG_OFFSET(VPMPCC_OGAM_RAMA_OFFSET_R); + gam_regs.start_base_cntl_b = REG_OFFSET(VPMPCC_OGAM_RAMA_START_BASE_CNTL_B); + gam_regs.start_base_cntl_g = REG_OFFSET(VPMPCC_OGAM_RAMA_START_BASE_CNTL_G); + gam_regs.start_base_cntl_r = REG_OFFSET(VPMPCC_OGAM_RAMA_START_BASE_CNTL_R); + + vpe10_cm_helper_program_gamcor_xfer_func(config_writer, params, &gam_regs); +} + +static void vpe10_mpc_program_ogam_pwl( + struct mpc *mpc, const struct pwl_result_data *rgb, uint32_t num) +{ + PROGRAM_ENTRY(); + + uint32_t last_base_value_red = rgb[num - 1].red_reg + rgb[num - 1].delta_red_reg; + uint32_t last_base_value_green = rgb[num - 1].green_reg + rgb[num - 1].delta_green_reg; + uint32_t last_base_value_blue = rgb[num - 1].blue_reg + rgb[num - 1].delta_blue_reg; + + if (vpe_is_rgb_equal(rgb, num)) { + vpe10_cm_helper_program_pwl(config_writer, rgb, last_base_value_red, num, + REG_OFFSET(VPMPCC_OGAM_LUT_DATA), REG_FIELD_SHIFT(VPMPCC_OGAM_LUT_DATA), + REG_FIELD_MASK(VPMPCC_OGAM_LUT_DATA), CM_PWL_R); + } else { + REG_UPDATE(VPMPCC_OGAM_LUT_CONTROL, VPMPCC_OGAM_LUT_WRITE_COLOR_MASK, 4); + + vpe10_cm_helper_program_pwl(config_writer, rgb, last_base_value_red, num, + REG_OFFSET(VPMPCC_OGAM_LUT_DATA), REG_FIELD_SHIFT(VPMPCC_OGAM_LUT_DATA), + REG_FIELD_MASK(VPMPCC_OGAM_LUT_DATA), CM_PWL_R); + + REG_SET(VPMPCC_OGAM_LUT_INDEX, 0, VPMPCC_OGAM_LUT_INDEX, 0); + REG_UPDATE(VPMPCC_OGAM_LUT_CONTROL, VPMPCC_OGAM_LUT_WRITE_COLOR_MASK, 2); + + vpe10_cm_helper_program_pwl(config_writer, rgb, last_base_value_green, num, + REG_OFFSET(VPMPCC_OGAM_LUT_DATA), REG_FIELD_SHIFT(VPMPCC_OGAM_LUT_DATA), + REG_FIELD_MASK(VPMPCC_OGAM_LUT_DATA), CM_PWL_G); + + REG_SET(VPMPCC_OGAM_LUT_INDEX, 0, VPMPCC_OGAM_LUT_INDEX, 0); + REG_UPDATE(VPMPCC_OGAM_LUT_CONTROL, VPMPCC_OGAM_LUT_WRITE_COLOR_MASK, 1); + + vpe10_cm_helper_program_pwl(config_writer, rgb, last_base_value_blue, num, + REG_OFFSET(VPMPCC_OGAM_LUT_DATA), REG_FIELD_SHIFT(VPMPCC_OGAM_LUT_DATA), + REG_FIELD_MASK(VPMPCC_OGAM_LUT_DATA), CM_PWL_B); + } +} + +void vpe10_mpc_set_output_gamma(struct mpc *mpc, const struct pwl_params *params) +{ + PROGRAM_ENTRY(); + + if (vpe_priv->init.debug.cm_in_bypass || // debug option: put CM in bypass mode + vpe_priv->init.debug.bypass_ogam || params == NULL) { // disable OGAM + REG_SET(VPMPCC_OGAM_CONTROL, 0, VPMPCC_OGAM_MODE, VPMPCC_OGAM_DISABLE); + return; + } + + // enable OGAM RAM LUT mode/Enable PWL + REG_SET_2(VPMPCC_OGAM_CONTROL, REG_DEFAULT(VPMPCC_OGAM_CONTROL), VPMPCC_OGAM_MODE, + VPMPCC_OGAM_RAMLUT, VPMPCC_OGAM_PWL_DISABLE, 0); + + mpc->funcs->power_on_ogam_lut(mpc, true); + + // configure_ogam_lut as LUT_A and all RGB channels to be written + REG_SET_2(VPMPCC_OGAM_LUT_CONTROL, + 0, // disable READ_DBG, set CONFIG_MODE to diff start/end mode implicitly + VPMPCC_OGAM_LUT_WRITE_COLOR_MASK, 7, VPMPCC_OGAM_LUT_HOST_SEL, RAM_LUT_A); + + REG_SET(VPMPCC_OGAM_LUT_INDEX, 0, VPMPCC_OGAM_LUT_INDEX, 0); + + // Always program LUTA in VPE10 + vpe10_mpc_program_luta(mpc, params); + + vpe10_mpc_program_ogam_pwl(mpc, params->rgb_resulted, params->hw_points_num); + + // Assume we prefer to enable_mem_low_power + if (vpe_priv->init.debug.enable_mem_low_power.bits.mpc) + mpc->funcs->power_on_ogam_lut(mpc, false); +} + +static void vpe10_program_gamut_remap( + struct mpc *mpc, const uint16_t *regval, enum gamut_remap_select select) +{ + uint16_t selection = 0; + struct color_matrices_reg gam_regs; + PROGRAM_ENTRY(); + + if (regval == NULL || select == GAMUT_REMAP_BYPASS) { + REG_SET(VPMPCC_GAMUT_REMAP_MODE, 0, VPMPCC_GAMUT_REMAP_MODE, GAMUT_REMAP_BYPASS); + return; + } + + gam_regs.shifts.csc_c11 = REG_FIELD_SHIFT(VPMPCC_GAMUT_REMAP_C11_A); + gam_regs.masks.csc_c11 = REG_FIELD_MASK(VPMPCC_GAMUT_REMAP_C11_A); + gam_regs.shifts.csc_c12 = REG_FIELD_SHIFT(VPMPCC_GAMUT_REMAP_C12_A); + gam_regs.masks.csc_c12 = REG_FIELD_MASK(VPMPCC_GAMUT_REMAP_C12_A); + + gam_regs.csc_c11_c12 = REG_OFFSET(VPMPC_GAMUT_REMAP_C11_C12_A); + gam_regs.csc_c33_c34 = REG_OFFSET(VPMPC_GAMUT_REMAP_C33_C34_A); + + vpe10_cm_helper_program_color_matrices(config_writer, regval, &gam_regs); + + // select coefficient set to use + REG_SET(VPMPCC_GAMUT_REMAP_MODE, 0, VPMPCC_GAMUT_REMAP_MODE, GAMUT_REMAP_COMA_COEFF); +} + +void vpe10_mpc_set_gamut_remap(struct mpc *mpc, struct colorspace_transform *gamut_remap) +{ + uint16_t arr_reg_val[12]; + PROGRAM_ENTRY(); + int i = 0; + + if (!gamut_remap || !gamut_remap->enable_remap) + vpe10_program_gamut_remap(mpc, NULL, GAMUT_REMAP_BYPASS); + else { + conv_convert_float_matrix(arr_reg_val, gamut_remap->matrix, 12); + + vpe10_program_gamut_remap(mpc, arr_reg_val, GAMUT_REMAP_COMA_COEFF); + } +} + +static void vpe10_mpc_configure_shaper_lut(struct mpc *mpc, bool is_ram_a) +{ + PROGRAM_ENTRY(); + + REG_SET_2(VPMPCC_MCM_SHAPER_LUT_WRITE_EN_MASK, 0, VPMPCC_MCM_SHAPER_LUT_WRITE_EN_MASK, 7, + VPMPCC_MCM_SHAPER_LUT_WRITE_SEL, is_ram_a == true ? 0 : 1); + + REG_SET(VPMPCC_MCM_SHAPER_LUT_INDEX, 0, VPMPCC_MCM_SHAPER_LUT_INDEX, 0); +} + +static void vpe10_mpc_program_shaper_luta_settings(struct mpc *mpc, const struct pwl_params *params) +{ + PROGRAM_ENTRY(); + const struct gamma_curve *curve; + uint16_t packet_data_size; + uint16_t i; + + REG_SET_2(VPMPCC_MCM_SHAPER_RAMA_START_CNTL_B, 0, VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B, + params->corner_points[0].blue.custom_float_x, + VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0); + REG_SET_2(VPMPCC_MCM_SHAPER_RAMA_START_CNTL_G, 0, VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B, + params->corner_points[0].green.custom_float_x, + VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0); + REG_SET_2(VPMPCC_MCM_SHAPER_RAMA_START_CNTL_R, 0, VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B, + params->corner_points[0].red.custom_float_x, + VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0); + + REG_SET_2(VPMPCC_MCM_SHAPER_RAMA_END_CNTL_B, 0, VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B, + params->corner_points[1].blue.custom_float_x, VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B, + params->corner_points[1].blue.custom_float_y); + REG_SET_2(VPMPCC_MCM_SHAPER_RAMA_END_CNTL_G, 0, VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B, + params->corner_points[1].green.custom_float_x, VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B, + params->corner_points[1].green.custom_float_y); + REG_SET_2(VPMPCC_MCM_SHAPER_RAMA_END_CNTL_R, 0, VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B, + params->corner_points[1].red.custom_float_x, VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B, + params->corner_points[1].red.custom_float_y); + + // Optimized by single VPEP config packet with auto inc + + packet_data_size = (uint16_t)(REG_OFFSET(VPMPCC_MCM_SHAPER_RAMA_REGION_32_33) - + REG_OFFSET(VPMPCC_MCM_SHAPER_RAMA_REGION_0_1) + 1); + + VPE_ASSERT(packet_data_size <= MAX_CONFIG_PACKET_DATA_SIZE_DWORD); + packet.bits.INC = 1; // set the auto increase bit + packet.bits.VPEP_CONFIG_DATA_SIZE = + packet_data_size - 1; // number of "continuous" dwords, 1-based + packet.bits.VPEP_CONFIG_REGISTER_OFFSET = REG_OFFSET(VPMPCC_MCM_SHAPER_RAMA_REGION_0_1); + + config_writer_fill_direct_config_packet_header(config_writer, &packet); + + curve = params->arr_curve_points; + + for (i = 0; i < packet_data_size; i++) { + config_writer_fill(config_writer, + REG_FIELD_VALUE(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset) | + REG_FIELD_VALUE( + VPMPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num) | + REG_FIELD_VALUE(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset) | + REG_FIELD_VALUE( + VPMPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num)); + curve += 2; + } +} + +static void vpe10_mpc_program_shaper_lut( + struct mpc *mpc, const struct pwl_result_data *rgb, uint32_t num) +{ + PROGRAM_ENTRY(); + uint32_t i, red, green, blue; + uint32_t red_delta, green_delta, blue_delta; + uint32_t red_value, green_value, blue_value; + uint16_t packet_data_size; + + // Optimized by single VPEP config packet for same address with multiple write + packet_data_size = (uint16_t)num * 3; // num writes for each channel in (R, G, B) + + VPE_ASSERT(packet_data_size <= MAX_CONFIG_PACKET_DATA_SIZE_DWORD); + packet.bits.INC = 0; + packet.bits.VPEP_CONFIG_DATA_SIZE = + packet_data_size - 1; // number of "continuous" dwords, 1-based + packet.bits.VPEP_CONFIG_REGISTER_OFFSET = REG_OFFSET(VPMPCC_MCM_SHAPER_LUT_DATA); + + config_writer_fill_direct_config_packet_header(config_writer, &packet); + + for (i = 0; i < num; i++) { + + red = rgb[i].red_reg; + green = rgb[i].green_reg; + blue = rgb[i].blue_reg; + + red_delta = rgb[i].delta_red_reg; + green_delta = rgb[i].delta_green_reg; + blue_delta = rgb[i].delta_blue_reg; + + red_value = ((red_delta & 0x3ff) << 14) | (red & 0x3fff); + green_value = ((green_delta & 0x3ff) << 14) | (green & 0x3fff); + blue_value = ((blue_delta & 0x3ff) << 14) | (blue & 0x3fff); + + config_writer_fill(config_writer, REG_FIELD_VALUE(VPMPCC_MCM_SHAPER_LUT_DATA, red_value)); + config_writer_fill(config_writer, REG_FIELD_VALUE(VPMPCC_MCM_SHAPER_LUT_DATA, green_value)); + config_writer_fill(config_writer, REG_FIELD_VALUE(VPMPCC_MCM_SHAPER_LUT_DATA, blue_value)); + } +} + +void vpe10_mpc_power_on_1dlut_shaper_3dlut(struct mpc *mpc, bool power_on) +{ + PROGRAM_ENTRY(); + // int max_retries = 10; + + REG_SET_3(VPMPCC_MCM_MEM_PWR_CTRL, REG_DEFAULT(VPMPCC_MCM_MEM_PWR_CTRL), + VPMPCC_MCM_SHAPER_MEM_PWR_DIS, power_on == true ? 1 : 0, VPMPCC_MCM_3DLUT_MEM_PWR_DIS, + power_on == true ? 1 : 0, VPMPCC_MCM_1DLUT_MEM_PWR_DIS, power_on == true ? 1 : 0); + + /* wait for memory to fully power up */ + if (power_on && vpe_priv->init.debug.enable_mem_low_power.bits.mpc) { + // REG_WAIT(VPMPCC_MCM_MEM_PWR_CTRL, VPMPCC_MCM_SHAPER_MEM_PWR_STATE, 0, 1, max_retries); + // Use two REG_SET instead of wait for State + // TODO: Confirm if this delay is enough + REG_SET_3(VPMPCC_MCM_MEM_PWR_CTRL, REG_DEFAULT(VPMPCC_MCM_MEM_PWR_CTRL), + VPMPCC_MCM_SHAPER_MEM_PWR_DIS, power_on == true ? 1 : 0, VPMPCC_MCM_3DLUT_MEM_PWR_DIS, + power_on == true ? 1 : 0, VPMPCC_MCM_1DLUT_MEM_PWR_DIS, power_on == true ? 1 : 0); + REG_SET_3(VPMPCC_MCM_MEM_PWR_CTRL, REG_DEFAULT(VPMPCC_MCM_MEM_PWR_CTRL), + VPMPCC_MCM_SHAPER_MEM_PWR_DIS, power_on == true ? 1 : 0, VPMPCC_MCM_3DLUT_MEM_PWR_DIS, + power_on == true ? 1 : 0, VPMPCC_MCM_1DLUT_MEM_PWR_DIS, power_on == true ? 1 : 0); + + // REG_WAIT(VPMPCC_MCM_MEM_PWR_CTRL, VPMPCC_MCM_3DLUT_MEM_PWR_STATE, 0, 1, max_retries); + } +} + +bool vpe10_mpc_program_shaper(struct mpc *mpc, const struct pwl_params *params) +{ + PROGRAM_ENTRY(); + + if (params == NULL) { + REG_SET(VPMPCC_MCM_SHAPER_CONTROL, 0, VPMPCC_MCM_SHAPER_LUT_MODE, 0); + return false; + } + + // if (vpe_priv->init.debug.enable_mem_low_power.bits.mpc) + // should always turn it on + vpe10_mpc_power_on_1dlut_shaper_3dlut(mpc, true); + + vpe10_mpc_configure_shaper_lut(mpc, true); // Always use LUT_RAM_A + + vpe10_mpc_program_shaper_luta_settings(mpc, params); + + vpe10_mpc_program_shaper_lut(mpc, params->rgb_resulted, params->hw_points_num); + + REG_SET(VPMPCC_MCM_SHAPER_CONTROL, 0, VPMPCC_MCM_SHAPER_LUT_MODE, 1); + + //? Should we check debug option before turn off shaper? -- should be yes + if (vpe_priv->init.debug.enable_mem_low_power.bits.mpc) + vpe10_mpc_power_on_1dlut_shaper_3dlut(mpc, false); + + return true; +} + +static void vpe10_mpc_select_3dlut_ram( + struct mpc *mpc, enum vpe_lut_mode mode, bool is_color_channel_12bits) +{ + PROGRAM_ENTRY(); + + VPE_ASSERT(mode == LUT_RAM_A); + + REG_UPDATE_2(VPMPCC_MCM_3DLUT_READ_WRITE_CONTROL, VPMPCC_MCM_3DLUT_RAM_SEL, + mode == LUT_RAM_A ? 0 : 1, VPMPCC_MCM_3DLUT_30BIT_EN, is_color_channel_12bits ? 0 : 1); +} + +static void vpe10_mpc_select_3dlut_ram_mask(struct mpc *mpc, uint32_t ram_selection_mask) +{ + PROGRAM_ENTRY(); + + REG_UPDATE( + VPMPCC_MCM_3DLUT_READ_WRITE_CONTROL, VPMPCC_MCM_3DLUT_WRITE_EN_MASK, ram_selection_mask); + REG_SET(VPMPCC_MCM_3DLUT_INDEX, 0, VPMPCC_MCM_3DLUT_INDEX, 0); +} + +static void vpe10_mpc_set3dlut_ram12(struct mpc *mpc, const struct vpe_rgb *lut, uint32_t entries) +{ + PROGRAM_ENTRY(); + uint32_t i, red, green, blue, red1, green1, blue1; + uint16_t MaxLutEntriesPerPacket = + (MAX_CONFIG_PACKET_DATA_SIZE_DWORD / 3) * 2; // each two entries consumes 3 DWORDs + uint16_t ActualEntriesInPacket = 0; + uint16_t ActualPacketSize; + + // Optimized by single VPEP config packet for same address with multiple write + + for (i = 0; i < entries; i += 2) { + if (i % MaxLutEntriesPerPacket == 0) { // need generate one another new packet + ActualEntriesInPacket = MaxLutEntriesPerPacket; + + // If single packet is big enough to contain remaining entries + if ((entries - i) < MaxLutEntriesPerPacket) { + ActualEntriesInPacket = (uint16_t)(entries - i); + if ((entries - i) % 2) { + // odd entries, round up to even as we need to program in pair + ActualEntriesInPacket++; + } + } + + ActualPacketSize = ActualEntriesInPacket * 3 / 2; + + VPE_ASSERT(ActualPacketSize <= MAX_CONFIG_PACKET_DATA_SIZE_DWORD); + packet.bits.INC = 0; + packet.bits.VPEP_CONFIG_DATA_SIZE = + ActualPacketSize - 1; // number of "continuous" dwords, 1-based + packet.bits.VPEP_CONFIG_REGISTER_OFFSET = REG_OFFSET(VPMPCC_MCM_3DLUT_DATA); + + config_writer_fill_direct_config_packet_header(config_writer, &packet); + } + + red = lut[i].red << 4; + green = lut[i].green << 4; + blue = lut[i].blue << 4; + if (i + 1 < entries) { + red1 = lut[i + 1].red << 4; + green1 = lut[i + 1].green << 4; + blue1 = lut[i + 1].blue << 4; + } else { + // last odd entry, program 0 for extra one that accompany with it. + red1 = 0; + green1 = 0; + blue1 = 0; + } + + config_writer_fill(config_writer, REG_FIELD_VALUE(VPMPCC_MCM_3DLUT_DATA0, red) | + REG_FIELD_VALUE(VPMPCC_MCM_3DLUT_DATA1, red1)); + config_writer_fill(config_writer, REG_FIELD_VALUE(VPMPCC_MCM_3DLUT_DATA0, green) | + REG_FIELD_VALUE(VPMPCC_MCM_3DLUT_DATA1, green1)); + config_writer_fill(config_writer, REG_FIELD_VALUE(VPMPCC_MCM_3DLUT_DATA0, blue) | + REG_FIELD_VALUE(VPMPCC_MCM_3DLUT_DATA1, blue1)); + } +} + +static void vpe10_mpc_set3dlut_ram12_indirect( + struct mpc *mpc, const uint64_t lut_gpuva, uint32_t entries) +{ + PROGRAM_ENTRY(); + // The layout inside the lut buf must be: (each element is 16bit, but LSB[3:0] are always 0) + // DW0: R1<<16 | R0 + // DW1: G1<<16 | G0 + // DW2: B1<<16 | B0 + // DW3: R3<<16 | R2 + // DW4: G3<<16 | G2 + // DW5: B3<<16 | B2 + //... + + uint32_t data_array_size = (entries / 2 * 3); // DW size of config data array, actual size + + config_writer_set_type(config_writer, CONFIG_TYPE_INDIRECT); + + // Optimized by single VPEP indirect config packet + // Fill the 3dLut array pointer + config_writer_fill_indirect_data_array(config_writer, lut_gpuva, data_array_size); + + // Start from index 0 + config_writer_fill_indirect_destination( + config_writer, REG_OFFSET(VPMPCC_MCM_3DLUT_INDEX), 0, REG_OFFSET(VPMPCC_MCM_3DLUT_DATA)); + + // restore back to direct + config_writer_set_type(config_writer, CONFIG_TYPE_DIRECT); +} + +static void vpe10_mpc_set3dlut_ram10(struct mpc *mpc, const struct vpe_rgb *lut, uint32_t entries) +{ + PROGRAM_ENTRY(); + uint32_t i, red, green, blue, value; + uint16_t MaxLutEntriesPerPacket = + MAX_CONFIG_PACKET_DATA_SIZE_DWORD; // each entries consumes 1 DWORDs + uint16_t ActualPacketSize; + + // Optimize to VPEP direct with multiple data + for (i = 0; i < entries; i++) { + // Need to revisit about the new config writer handling , DO WE STILL NEED IT? + // Yes, this is to ensure how many "packets" we need due to each packet have max data size + // i.e. need to split into diff packets (but might still in one direct config descriptor) + // The new config writer handles the "descriptor" size exceeded issue. + // i.e. need to split into diff direct config descriptors. + if (i % MaxLutEntriesPerPacket == 0) { // need generate one another new packet + if ((entries - i) < + MaxLutEntriesPerPacket) // Single packet is big enough to contain remaining entries + MaxLutEntriesPerPacket = (uint16_t)(entries - i); + + ActualPacketSize = MaxLutEntriesPerPacket; + + VPE_ASSERT(ActualPacketSize <= MAX_CONFIG_PACKET_DATA_SIZE_DWORD); + packet.bits.INC = 0; + packet.bits.VPEP_CONFIG_DATA_SIZE = + ActualPacketSize - 1; // number of "continuous" dwords, 1-based + packet.bits.VPEP_CONFIG_REGISTER_OFFSET = REG_OFFSET(VPMPCC_MCM_3DLUT_DATA_30BIT); + + config_writer_fill_direct_config_packet_header(config_writer, &packet); + } + + red = lut[i].red; + green = lut[i].green; + blue = lut[i].blue; + // should we shift red 22bit and green 12? + // Yes, accroding to spec. + // let's do it instead of just shift 10 bits + value = (red << 22) | (green << 12) | blue << 2; + + config_writer_fill(config_writer, REG_FIELD_VALUE(VPMPCC_MCM_3DLUT_DATA_30BIT, value)); + } +} + +static void vpe10_mpc_set3dlut_ram10_indirect( + struct mpc *mpc, const uint64_t lut_gpuva, uint32_t entries) +{ + PROGRAM_ENTRY(); + + uint32_t data_array_size = entries; // DW size of config data array, actual size + // Optimized by single VPEP indirect config packet + // The layout inside the lut buf must be: (each element is 10bit, but LSB[1:0] are always 0) + // DW0: R0<<22 | G0<<12 | B0 <<2 + // DW0: R1<<22 | G1<<12 | B1 <<2 + //... + + config_writer_set_type(config_writer, CONFIG_TYPE_INDIRECT); + + // Optimized by single VPEP indirect config packet + // Fill the 3dLut array pointer + config_writer_fill_indirect_data_array(config_writer, lut_gpuva, data_array_size); + + // Start from index 0 + config_writer_fill_indirect_destination( + config_writer, REG_OFFSET(VPMPCC_MCM_3DLUT_INDEX), 0, REG_OFFSET(VPMPCC_MCM_3DLUT_DATA)); + + // resume back to direct + config_writer_set_type(config_writer, CONFIG_TYPE_DIRECT); +} + +static void vpe10_mpc_set_3dlut_mode( + struct mpc *mpc, enum vpe_lut_mode mode, bool is_lut_size17x17x17) +{ + PROGRAM_ENTRY(); + uint32_t lut_mode; + + if (mode == LUT_BYPASS) + lut_mode = 0; + else if (mode == LUT_RAM_A) + lut_mode = 1; + else + lut_mode = 2; + + REG_SET_2(VPMPCC_MCM_3DLUT_MODE, 0, VPMPCC_MCM_3DLUT_MODE, lut_mode, VPMPCC_MCM_3DLUT_SIZE, + is_lut_size17x17x17 == true ? 0 : 1); +} + +// using direct config to program the 3dlut specified in params +void vpe10_mpc_program_3dlut(struct mpc *mpc, const struct tetrahedral_params *params) +{ + PROGRAM_ENTRY(); + enum vpe_lut_mode mode; + bool is_17x17x17; + bool is_12bits_color_channel; + const struct vpe_rgb *lut0; + const struct vpe_rgb *lut1; + const struct vpe_rgb *lut2; + const struct vpe_rgb *lut3; + uint32_t lut_size0; + uint32_t lut_size; + + if (params == NULL) { + vpe10_mpc_set_3dlut_mode(mpc, LUT_BYPASS, false); + return; + } + + vpe10_mpc_power_on_1dlut_shaper_3dlut(mpc, true); + + // always use LUT_RAM_A except for bypass mode which is not the case here + mode = LUT_RAM_A; + + is_17x17x17 = !params->use_tetrahedral_9; + is_12bits_color_channel = params->use_12bits; + if (is_17x17x17) { + lut0 = params->tetrahedral_17.lut0; + lut1 = params->tetrahedral_17.lut1; + lut2 = params->tetrahedral_17.lut2; + lut3 = params->tetrahedral_17.lut3; + lut_size0 = sizeof(params->tetrahedral_17.lut0) / sizeof(params->tetrahedral_17.lut0[0]); + lut_size = sizeof(params->tetrahedral_17.lut1) / sizeof(params->tetrahedral_17.lut1[0]); + } else { + lut0 = params->tetrahedral_9.lut0; + lut1 = params->tetrahedral_9.lut1; + lut2 = params->tetrahedral_9.lut2; + lut3 = params->tetrahedral_9.lut3; + lut_size0 = sizeof(params->tetrahedral_9.lut0) / sizeof(params->tetrahedral_9.lut0[0]); + lut_size = sizeof(params->tetrahedral_9.lut1) / sizeof(params->tetrahedral_9.lut1[0]); + } + + vpe10_mpc_select_3dlut_ram(mpc, mode, is_12bits_color_channel); + // set mask to LUT0 + vpe10_mpc_select_3dlut_ram_mask(mpc, 0x1); + if (is_12bits_color_channel) + vpe10_mpc_set3dlut_ram12(mpc, lut0, lut_size0); + else + vpe10_mpc_set3dlut_ram10(mpc, lut0, lut_size0); + + // set mask to LUT1 + vpe10_mpc_select_3dlut_ram_mask(mpc, 0x2); + if (is_12bits_color_channel) + vpe10_mpc_set3dlut_ram12(mpc, lut1, lut_size); + else + vpe10_mpc_set3dlut_ram10(mpc, lut1, lut_size); + + // set mask to LUT2 + vpe10_mpc_select_3dlut_ram_mask(mpc, 0x4); + if (is_12bits_color_channel) + vpe10_mpc_set3dlut_ram12(mpc, lut2, lut_size); + else + vpe10_mpc_set3dlut_ram10(mpc, lut2, lut_size); + + // set mask to LUT3 + vpe10_mpc_select_3dlut_ram_mask(mpc, 0x8); + if (is_12bits_color_channel) + vpe10_mpc_set3dlut_ram12(mpc, lut3, lut_size); + else + vpe10_mpc_set3dlut_ram10(mpc, lut3, lut_size); + + vpe10_mpc_set_3dlut_mode(mpc, mode, is_17x17x17); + + if (vpe_priv->init.debug.enable_mem_low_power.bits.mpc) + vpe10_mpc_power_on_1dlut_shaper_3dlut(mpc, false); + + return; +} + +// using indirect config to configure the 3DLut +// note that we still need direct config to switch the mask between lut0 - lut3 +bool vpe10_mpc_program_3dlut_indirect(struct mpc *mpc, + struct vpe_buf *lut0_3_buf, // 3d lut buf which contains the data for lut0-lut3 + bool use_tetrahedral_9, bool use_12bits) +{ + PROGRAM_ENTRY(); + enum vpe_lut_mode mode; + bool is_17x17x17; + bool is_12bits_color_channel; + uint64_t lut0_gpuva; + uint64_t lut1_gpuva; + uint64_t lut2_gpuva; + uint64_t lut3_gpuva; + uint32_t lut_size0; + uint32_t lut_size; + struct tetrahedral_17x17x17 *tetra17 = NULL; + struct tetrahedral_9x9x9 *tetra9 = NULL; + + // make sure it is in DIRECT type + config_writer_set_type(config_writer, CONFIG_TYPE_DIRECT); + + if (lut0_3_buf == NULL) { + vpe10_mpc_set_3dlut_mode(mpc, LUT_BYPASS, false); + return false; + } + + vpe10_mpc_power_on_1dlut_shaper_3dlut(mpc, true); + + // always use LUT_RAM_A except for bypass mode which is not the case here + mode = LUT_RAM_A; + + is_17x17x17 = !use_tetrahedral_9; + is_12bits_color_channel = use_12bits; + if (is_17x17x17) { + lut0_gpuva = lut0_3_buf->gpu_va; + lut1_gpuva = lut0_3_buf->gpu_va + (uint64_t)(offsetof(struct tetrahedral_17x17x17, lut1)); + lut2_gpuva = lut0_3_buf->gpu_va + (uint64_t)(offsetof(struct tetrahedral_17x17x17, lut2)); + lut3_gpuva = lut0_3_buf->gpu_va + (uint64_t)(offsetof(struct tetrahedral_17x17x17, lut3)); + lut_size0 = sizeof(tetra17->lut0) / sizeof(tetra17->lut0[0]); + lut_size = sizeof(tetra17->lut1) / sizeof(tetra17->lut1[0]); + } else { + lut0_gpuva = lut0_3_buf->gpu_va; + lut1_gpuva = lut0_3_buf->gpu_va + (uint64_t)(offsetof(struct tetrahedral_9x9x9, lut1)); + lut2_gpuva = lut0_3_buf->gpu_va + (uint64_t)(offsetof(struct tetrahedral_9x9x9, lut2)); + lut3_gpuva = lut0_3_buf->gpu_va + (uint64_t)(offsetof(struct tetrahedral_9x9x9, lut3)); + lut_size0 = sizeof(tetra9->lut0) / sizeof(tetra9->lut0[0]); + lut_size = sizeof(tetra9->lut1) / sizeof(tetra9->lut1[0]); + } + + vpe10_mpc_select_3dlut_ram(mpc, mode, is_12bits_color_channel); + + // set mask to LUT0 + vpe10_mpc_select_3dlut_ram_mask(mpc, 0x1); + if (is_12bits_color_channel) + vpe10_mpc_set3dlut_ram12_indirect(mpc, lut0_gpuva, lut_size0); + else + vpe10_mpc_set3dlut_ram10_indirect(mpc, lut0_gpuva, lut_size0); + + // set mask to LUT1 + vpe10_mpc_select_3dlut_ram_mask(mpc, 0x2); + if (is_12bits_color_channel) + vpe10_mpc_set3dlut_ram12_indirect(mpc, lut1_gpuva, lut_size); + else + vpe10_mpc_set3dlut_ram10_indirect(mpc, lut1_gpuva, lut_size); + + // set mask to LUT2 + vpe10_mpc_select_3dlut_ram_mask(mpc, 0x4); + if (is_12bits_color_channel) + vpe10_mpc_set3dlut_ram12_indirect(mpc, lut2_gpuva, lut_size); + else + vpe10_mpc_set3dlut_ram10_indirect(mpc, lut2_gpuva, lut_size); + + // set mask to LUT3 + vpe10_mpc_select_3dlut_ram_mask(mpc, 0x8); + if (is_12bits_color_channel) + vpe10_mpc_set3dlut_ram12_indirect(mpc, lut3_gpuva, lut_size); + else + vpe10_mpc_set3dlut_ram10_indirect(mpc, lut3_gpuva, lut_size); + + vpe10_mpc_set_3dlut_mode(mpc, mode, is_17x17x17); + + if (vpe_priv->init.debug.enable_mem_low_power.bits.mpc) + vpe10_mpc_power_on_1dlut_shaper_3dlut(mpc, false); + + return true; +} + +static void vpe10_mpc_configure_1dlut(struct mpc *mpc, bool is_ram_a) +{ + PROGRAM_ENTRY(); + + REG_SET_2(VPMPCC_MCM_1DLUT_LUT_CONTROL, 0, VPMPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK, 7, + VPMPCC_MCM_1DLUT_LUT_HOST_SEL, is_ram_a == true ? 0 : 1); + + REG_SET(VPMPCC_MCM_1DLUT_LUT_INDEX, 0, VPMPCC_MCM_1DLUT_LUT_INDEX, 0); +} + +static void vpe10_mpc_1dlut_get_reg_field(struct mpc *mpc, struct vpe10_xfer_func_reg *reg) +{ + struct vpe10_mpc *vpe10_mpc = (struct vpe10_mpc *)mpc; + + reg->shifts.field_region_start_base = + vpe10_mpc->shift->VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B; + reg->masks.field_region_start_base = + vpe10_mpc->mask->VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B; + reg->shifts.field_offset = vpe10_mpc->shift->VPMPCC_MCM_1DLUT_RAMA_OFFSET_B; + reg->masks.field_offset = vpe10_mpc->mask->VPMPCC_MCM_1DLUT_RAMA_OFFSET_B; + + reg->shifts.exp_region0_lut_offset = + vpe10_mpc->shift->VPMPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET; + reg->masks.exp_region0_lut_offset = + vpe10_mpc->mask->VPMPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET; + reg->shifts.exp_region0_num_segments = + vpe10_mpc->shift->VPMPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS; + reg->masks.exp_region0_num_segments = + vpe10_mpc->mask->VPMPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS; + reg->shifts.exp_region1_lut_offset = + vpe10_mpc->shift->VPMPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET; + reg->masks.exp_region1_lut_offset = + vpe10_mpc->mask->VPMPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET; + reg->shifts.exp_region1_num_segments = + vpe10_mpc->shift->VPMPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS; + reg->masks.exp_region1_num_segments = + vpe10_mpc->mask->VPMPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS; + + reg->shifts.field_region_end = vpe10_mpc->shift->VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B; + reg->masks.field_region_end = vpe10_mpc->mask->VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B; + reg->shifts.field_region_end_slope = + vpe10_mpc->shift->VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B; + reg->masks.field_region_end_slope = + vpe10_mpc->mask->VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B; + reg->shifts.field_region_end_base = + vpe10_mpc->shift->VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B; + reg->masks.field_region_end_base = vpe10_mpc->mask->VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B; + reg->shifts.field_region_linear_slope = + vpe10_mpc->shift->VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B; + reg->masks.field_region_linear_slope = + vpe10_mpc->mask->VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B; + reg->shifts.exp_region_start = vpe10_mpc->shift->VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B; + reg->masks.exp_region_start = vpe10_mpc->mask->VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B; + reg->shifts.exp_region_start_segment = + vpe10_mpc->shift->VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B; + reg->masks.exp_region_start_segment = + vpe10_mpc->mask->VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B; +} + +/*program blnd lut RAM A*/ +static void vpe10_mpc_program_1dlut_luta_settings(struct mpc *mpc, const struct pwl_params *params) +{ + PROGRAM_ENTRY(); + struct vpe10_xfer_func_reg gam_regs; + + vpe10_mpc_1dlut_get_reg_field(mpc, &gam_regs); + + gam_regs.start_cntl_b = REG_OFFSET(VPMPCC_MCM_1DLUT_RAMA_START_CNTL_B); + gam_regs.start_cntl_g = REG_OFFSET(VPMPCC_MCM_1DLUT_RAMA_START_CNTL_G); + gam_regs.start_cntl_r = REG_OFFSET(VPMPCC_MCM_1DLUT_RAMA_START_CNTL_R); + gam_regs.start_slope_cntl_b = REG_OFFSET(VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B); + gam_regs.start_slope_cntl_g = REG_OFFSET(VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G); + gam_regs.start_slope_cntl_r = REG_OFFSET(VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R); + gam_regs.start_end_cntl1_b = REG_OFFSET(VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_B); + gam_regs.start_end_cntl2_b = REG_OFFSET(VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_B); + gam_regs.start_end_cntl1_g = REG_OFFSET(VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_G); + gam_regs.start_end_cntl2_g = REG_OFFSET(VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_G); + gam_regs.start_end_cntl1_r = REG_OFFSET(VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_R); + gam_regs.start_end_cntl2_r = REG_OFFSET(VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_R); + gam_regs.region_start = REG_OFFSET(VPMPCC_MCM_1DLUT_RAMA_REGION_0_1); + gam_regs.region_end = REG_OFFSET(VPMPCC_MCM_1DLUT_RAMA_REGION_32_33); + gam_regs.offset_b = REG_OFFSET(VPMPCC_MCM_1DLUT_RAMA_OFFSET_B); + gam_regs.offset_g = REG_OFFSET(VPMPCC_MCM_1DLUT_RAMA_OFFSET_G); + gam_regs.offset_r = REG_OFFSET(VPMPCC_MCM_1DLUT_RAMA_OFFSET_R); + gam_regs.start_base_cntl_b = REG_OFFSET(VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B); + gam_regs.start_base_cntl_g = REG_OFFSET(VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G); + gam_regs.start_base_cntl_r = REG_OFFSET(VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R); + + vpe10_cm_helper_program_gamcor_xfer_func(config_writer, params, &gam_regs); +} + +static void vpe10_mpc_program_1dlut_pwl( + struct mpc *mpc, const struct pwl_result_data *rgb, uint32_t num) +{ + PROGRAM_ENTRY(); + + uint32_t last_base_value_red = rgb[num].red_reg; + uint32_t last_base_value_green = rgb[num].blue_reg; + uint32_t last_base_value_blue = rgb[num].green_reg; + + if (vpe_is_rgb_equal(rgb, num)) { + vpe10_cm_helper_program_pwl(config_writer, rgb, last_base_value_red, num, + REG_OFFSET(VPMPCC_MCM_1DLUT_LUT_DATA), REG_FIELD_SHIFT(VPMPCC_MCM_1DLUT_LUT_DATA), + REG_FIELD_MASK(VPMPCC_MCM_1DLUT_LUT_DATA), CM_PWL_R); + } else { + REG_SET(VPMPCC_MCM_1DLUT_LUT_INDEX, 0, VPMPCC_MCM_1DLUT_LUT_INDEX, 0); + REG_UPDATE(VPMPCC_MCM_1DLUT_LUT_CONTROL, VPMPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK, 4); + + vpe10_cm_helper_program_pwl(config_writer, rgb, last_base_value_red, num, + REG_OFFSET(VPMPCC_MCM_1DLUT_LUT_DATA), REG_FIELD_SHIFT(VPMPCC_MCM_1DLUT_LUT_DATA), + REG_FIELD_MASK(VPMPCC_MCM_1DLUT_LUT_DATA), CM_PWL_R); + + REG_SET(VPMPCC_MCM_1DLUT_LUT_INDEX, 0, VPMPCC_MCM_1DLUT_LUT_INDEX, 0); + REG_UPDATE(VPMPCC_MCM_1DLUT_LUT_CONTROL, VPMPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK, 2); + + vpe10_cm_helper_program_pwl(config_writer, rgb, last_base_value_green, num, + REG_OFFSET(VPMPCC_MCM_1DLUT_LUT_DATA), REG_FIELD_SHIFT(VPMPCC_MCM_1DLUT_LUT_DATA), + REG_FIELD_MASK(VPMPCC_MCM_1DLUT_LUT_DATA), CM_PWL_G); + + REG_SET(VPMPCC_MCM_1DLUT_LUT_INDEX, 0, VPMPCC_MCM_1DLUT_LUT_INDEX, 0); + REG_UPDATE(VPMPCC_MCM_1DLUT_LUT_CONTROL, VPMPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK, 1); + + vpe10_cm_helper_program_pwl(config_writer, rgb, last_base_value_blue, num, + REG_OFFSET(VPMPCC_MCM_1DLUT_LUT_DATA), REG_FIELD_SHIFT(VPMPCC_MCM_1DLUT_LUT_DATA), + REG_FIELD_MASK(VPMPCC_MCM_1DLUT_LUT_DATA), CM_PWL_B); + } +} + +// Blend-gamma control. +void vpe10_mpc_program_1dlut(struct mpc *mpc, const struct pwl_params *params) +{ + PROGRAM_ENTRY(); + + if (params == NULL) { + REG_SET(VPMPCC_MCM_1DLUT_CONTROL, REG_DEFAULT(VPMPCC_MCM_1DLUT_CONTROL), + VPMPCC_MCM_1DLUT_MODE, 0); + + if (vpe_priv->init.debug.enable_mem_low_power.bits.mpc) + vpe10_mpc_power_on_1dlut_shaper_3dlut(mpc, false); + return; + } + + vpe10_mpc_power_on_1dlut_shaper_3dlut(mpc, true); + + vpe10_mpc_configure_1dlut(mpc, true); + vpe10_mpc_program_1dlut_luta_settings(mpc, params); + vpe10_mpc_program_1dlut_pwl(mpc, params->rgb_resulted, params->hw_points_num); + + REG_SET( + VPMPCC_MCM_1DLUT_CONTROL, REG_DEFAULT(VPMPCC_MCM_1DLUT_CONTROL), VPMPCC_MCM_1DLUT_MODE, 2); +} + +void vpe10_mpc_program_cm_location(struct mpc *mpc, uint8_t location) +{ + PROGRAM_ENTRY(); + // Location 0 == before blending, + // Location 1 == after blending + REG_SET(VPMPCC_MOVABLE_CM_LOCATION_CONTROL, REG_DEFAULT(VPMPCC_MOVABLE_CM_LOCATION_CONTROL), + VPMPCC_MOVABLE_CM_LOCATION_CNTL, location); +} + +void vpe10_mpc_set_denorm(struct mpc *mpc, int opp_id, enum color_depth output_depth, + struct mpc_denorm_clamp *denorm_clamp) +{ + PROGRAM_ENTRY(); + /* De-normalize Fixed U1.13 color data to different target bit depths. 0 is bypass*/ + int denorm_mode = 0; + + VPE_ASSERT(opp_id == 0); // Only support opp0 in v1 + + switch (output_depth) { + case COLOR_DEPTH_666: + denorm_mode = 1; + break; + case COLOR_DEPTH_888: + denorm_mode = 2; + break; + case COLOR_DEPTH_999: + denorm_mode = 3; + break; + case COLOR_DEPTH_101010: + denorm_mode = 4; + break; + case COLOR_DEPTH_111111: + denorm_mode = 5; + break; + case COLOR_DEPTH_121212: + denorm_mode = 6; + break; + case COLOR_DEPTH_141414: + case COLOR_DEPTH_161616: + default: + /* not valid used case! */ + break; + } + + /*program min and max clamp values for the pixel components*/ + if (denorm_clamp) { + REG_SET_3(VPMPC_OUT0_DENORM_CONTROL, 0, VPMPC_OUT_DENORM_MODE, denorm_mode, + VPMPC_OUT_DENORM_CLAMP_MAX_R_CR, denorm_clamp->clamp_max_r_cr, + VPMPC_OUT_DENORM_CLAMP_MIN_R_CR, denorm_clamp->clamp_min_r_cr); + REG_SET_2(VPMPC_OUT0_DENORM_CLAMP_G_Y, 0, VPMPC_OUT_DENORM_CLAMP_MAX_G_Y, + denorm_clamp->clamp_max_g_y, VPMPC_OUT_DENORM_CLAMP_MIN_G_Y, + denorm_clamp->clamp_min_g_y); + REG_SET_2(VPMPC_OUT0_DENORM_CLAMP_B_CB, 0, VPMPC_OUT_DENORM_CLAMP_MAX_B_CB, + denorm_clamp->clamp_max_b_cb, VPMPC_OUT_DENORM_CLAMP_MIN_B_CB, + denorm_clamp->clamp_min_b_cb); + } else { + REG_SET(VPMPC_OUT0_DENORM_CONTROL, REG_DEFAULT(VPMPC_OUT0_DENORM_CONTROL), + VPMPC_OUT_DENORM_MODE, denorm_mode); + REG_SET_DEFAULT(VPMPC_OUT0_DENORM_CLAMP_G_Y); + REG_SET_DEFAULT(VPMPC_OUT0_DENORM_CLAMP_B_CB); + } +} + +void vpe10_mpc_set_out_float_en(struct mpc *mpc, bool float_enable) +{ + PROGRAM_ENTRY(); + + REG_SET(VPMPC_OUT0_FLOAT_CONTROL, 0, VPMPC_OUT_FLOAT_EN, float_enable); +} + +void vpe10_mpc_program_mpc_out(struct mpc *mpc, enum vpe_surface_pixel_format format) +{ + // check output format/color depth + mpc->funcs->set_out_float_en(mpc, vpe_is_fp16(format)); + mpc->funcs->set_denorm(mpc, 0, vpe_get_color_depth(format), NULL); +} + +void vpe10_mpc_set_mpc_shaper_3dlut( + struct mpc *mpc, const struct transfer_func *func_shaper, const struct vpe_3dlut *lut3d_func) +{ + const struct pwl_params *shaper_lut = NULL; + // get the shaper lut params + if (func_shaper) { + if (func_shaper->type == TF_TYPE_DISTRIBUTED_POINTS) { + vpe10_cm_helper_translate_curve_to_hw_format( + func_shaper, &mpc->shaper_params, true); // should init shaper_params first + shaper_lut = &mpc->shaper_params; // are there shaper prams in dpp instead? + } else if (func_shaper->type == TF_TYPE_HWPWL) { + shaper_lut = &func_shaper->pwl; + } + } + + mpc->funcs->program_shaper(mpc, shaper_lut); + + if (lut3d_func) { + if (lut3d_func->state.bits.initialized) + mpc->funcs->program_3dlut(mpc, &lut3d_func->lut_3d); + else + mpc->funcs->program_3dlut(mpc, NULL); + } + return; +} + +void vpe10_mpc_set_output_transfer_func(struct mpc *mpc, struct output_ctx *output_ctx) +{ + /* program OGAM only for the top pipe*/ + struct pwl_params *params = NULL; + bool ret = false; + + if (ret == false && output_ctx->output_tf) { + // No support HWPWL as it is legacy + if (output_ctx->output_tf->type == TF_TYPE_DISTRIBUTED_POINTS) { + if (!output_ctx->output_tf->use_pre_calculated_table || + mpc->vpe_priv->init.debug.force_tf_calculation) { + vpe10_cm_helper_translate_curve_to_hw_format( // this is cm3.0 version instead 1.0 + // as DCN3.2 + output_ctx->output_tf, &mpc->regamma_params, false); + params = &mpc->regamma_params; + } else { + vpe10_cm_get_tf_pwl_params(output_ctx->output_tf, ¶ms, CM_REGAM); + VPE_ASSERT(params != NULL); + if (params == NULL) + return; + } + } + /* there are no ROM LUTs in OUTGAM */ + if (output_ctx->output_tf->type == TF_TYPE_PREDEFINED) + VPE_ASSERT(0); + } + mpc->funcs->set_output_gamma(mpc, params); +} + +void vpe10_mpc_set_blend_lut(struct mpc *mpc, const struct transfer_func *blend_tf) +{ + struct pwl_params *blend_lut = NULL; + + if (blend_tf) { + if (blend_tf->type == TF_TYPE_DISTRIBUTED_POINTS) { + vpe10_cm_helper_translate_curve_to_degamma_hw_format( + blend_tf, &mpc->blender_params); // TODO should init regamma_params first + blend_lut = &mpc->blender_params; + } + } + mpc->funcs->program_1dlut(mpc, blend_lut); + + return; +} + +bool vpe10_mpc_program_movable_cm(struct mpc *mpc, const struct transfer_func *func_shaper, + const struct vpe_3dlut *lut3d_func, const struct transfer_func *blend_tf, bool afterblend) +{ + struct pwl_params *params = NULL; + bool ret = false; + + /*program shaper and 3dlut and 1dlut in MPC*/ + mpc->funcs->set_mpc_shaper_3dlut(mpc, func_shaper, lut3d_func); + mpc->funcs->set_blend_lut(mpc, blend_tf); + mpc->funcs->program_cm_location(mpc, afterblend); + + return ret; +} + +void vpe10_mpc_program_crc(struct mpc *mpc, bool enable) +{ + PROGRAM_ENTRY(); + REG_UPDATE(VPMPC_CRC_CTRL, VPMPC_CRC_EN, enable); +} + diff --git a/src/amd/vpelib/src/chip/vpe10/vpe10_opp.c b/src/amd/vpelib/src/chip/vpe10/vpe10_opp.c new file mode 100644 index 00000000000..71a68604f53 --- /dev/null +++ b/src/amd/vpelib/src/chip/vpe10/vpe10_opp.c @@ -0,0 +1,220 @@ +/* Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include +#include "common.h" +#include "vpe_priv.h" +#include "vpe10_opp.h" +#include "vpe_command.h" +#include "hw_shared.h" +#include "reg_helper.h" + +#define CTX_BASE opp +#define CTX vpe10_opp + +static struct opp_funcs opp_funcs = { + .program_pipe_alpha = vpe10_opp_program_pipe_alpha, + .program_pipe_bypass = vpe10_opp_program_pipe_bypass, + .program_pipe_crc = vpe10_opp_program_pipe_crc, + .set_clamping = vpe10_opp_set_clamping, + .set_truncation = vpe10_opp_set_truncation, + .set_spatial_dither = vpe10_opp_set_spatial_dither, + .program_bit_depth_reduction = vpe10_opp_program_bit_depth_reduction, + .set_dyn_expansion = vpe10_opp_set_dyn_expansion, + .program_fmt = vpe10_opp_program_fmt, +}; + +void vpe10_construct_opp(struct vpe_priv *vpe_priv, struct opp *opp) +{ + opp->vpe_priv = vpe_priv; + opp->funcs = &opp_funcs; +} + +void vpe10_opp_set_clamping( + struct opp *opp, const struct clamping_and_pixel_encoding_params *params) +{ + PROGRAM_ENTRY(); + + switch (params->clamping_level) { + case CLAMPING_LIMITED_RANGE_8BPC: + case CLAMPING_LIMITED_RANGE_10BPC: + case CLAMPING_LIMITED_RANGE_12BPC: + REG_SET_2(VPFMT_CLAMP_CNTL, 0, VPFMT_CLAMP_DATA_EN, 1, VPFMT_CLAMP_COLOR_FORMAT, + params->clamping_level); + break; + case CLAMPING_LIMITED_RANGE_PROGRAMMABLE: + REG_SET_2(VPFMT_CLAMP_CNTL, 0, VPFMT_CLAMP_DATA_EN, 1, VPFMT_CLAMP_COLOR_FORMAT, 7); + REG_SET_2(VPFMT_CLAMP_COMPONENT_R, 0, VPFMT_CLAMP_LOWER_R, params->r_clamp_component_lower, + VPFMT_CLAMP_UPPER_R, params->r_clamp_component_upper); + REG_SET_2(VPFMT_CLAMP_COMPONENT_G, 0, VPFMT_CLAMP_LOWER_G, params->g_clamp_component_lower, + VPFMT_CLAMP_UPPER_G, params->g_clamp_component_upper); + REG_SET_2(VPFMT_CLAMP_COMPONENT_B, 0, VPFMT_CLAMP_LOWER_B, params->b_clamp_component_lower, + VPFMT_CLAMP_UPPER_B, params->b_clamp_component_upper); + break; + case CLAMPING_FULL_RANGE: + default: + REG_SET_2(VPFMT_CLAMP_CNTL, 0, VPFMT_CLAMP_DATA_EN, 0, VPFMT_CLAMP_COLOR_FORMAT, 0); + break; + } +} + +void vpe10_opp_set_dyn_expansion(struct opp *opp, bool enable, enum color_depth color_dpth) +{ + PROGRAM_ENTRY(); + + if (!enable) { + REG_SET_2(VPFMT_DYNAMIC_EXP_CNTL, 0, VPFMT_DYNAMIC_EXP_EN, 0, VPFMT_DYNAMIC_EXP_MODE, 0); + return; + } + + /*00 - 10-bit -> 12-bit dynamic expansion*/ + /*01 - 8-bit -> 12-bit dynamic expansion*/ + switch (color_dpth) { + case COLOR_DEPTH_888: + REG_SET_2(VPFMT_DYNAMIC_EXP_CNTL, 0, VPFMT_DYNAMIC_EXP_EN, 1, VPFMT_DYNAMIC_EXP_MODE, 1); + break; + case COLOR_DEPTH_101010: + REG_SET_2(VPFMT_DYNAMIC_EXP_CNTL, 0, VPFMT_DYNAMIC_EXP_EN, 1, VPFMT_DYNAMIC_EXP_MODE, 0); + break; + case COLOR_DEPTH_121212: + REG_SET_2(VPFMT_DYNAMIC_EXP_CNTL, 0, VPFMT_DYNAMIC_EXP_EN, + 1, /*otherwise last two bits are zero*/ + VPFMT_DYNAMIC_EXP_MODE, 0); + break; + default: + REG_SET_2(VPFMT_DYNAMIC_EXP_CNTL, 0, VPFMT_DYNAMIC_EXP_EN, 0, VPFMT_DYNAMIC_EXP_MODE, 0); + break; + } +} + +void vpe10_opp_set_truncation(struct opp *opp, const struct bit_depth_reduction_params *params) +{ + PROGRAM_ENTRY(); + + REG_UPDATE_3(VPFMT_BIT_DEPTH_CONTROL, VPFMT_TRUNCATE_EN, params->flags.TRUNCATE_ENABLED, + VPFMT_TRUNCATE_DEPTH, params->flags.TRUNCATE_DEPTH, VPFMT_TRUNCATE_MODE, + params->flags.TRUNCATE_MODE); +} + +void vpe10_opp_set_spatial_dither(struct opp *opp, const struct bit_depth_reduction_params *params) +{ + PROGRAM_ENTRY(); + + /*Disable spatial (random) dithering*/ + REG_UPDATE_6(VPFMT_BIT_DEPTH_CONTROL, VPFMT_SPATIAL_DITHER_EN, 0, VPFMT_SPATIAL_DITHER_MODE, 0, + VPFMT_SPATIAL_DITHER_DEPTH, 0, VPFMT_HIGHPASS_RANDOM_ENABLE, 0, VPFMT_FRAME_RANDOM_ENABLE, + 0, VPFMT_RGB_RANDOM_ENABLE, 0); + + if (params->flags.SPATIAL_DITHER_ENABLED == 0) + return; + + /* only use FRAME_COUNTER_MAX if frameRandom == 1*/ + if (params->flags.FRAME_RANDOM == 1) { + if (params->flags.SPATIAL_DITHER_DEPTH == 0 || params->flags.SPATIAL_DITHER_DEPTH == 1) { + REG_UPDATE_2(VPFMT_CONTROL, VPFMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, 15, + VPFMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, 2); + } else if (params->flags.SPATIAL_DITHER_DEPTH == 2) { + REG_UPDATE_2(VPFMT_CONTROL, VPFMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, 3, + VPFMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, 1); + } else + return; + } else { + REG_UPDATE_2(VPFMT_CONTROL, VPFMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, 0, + VPFMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, 0); + } + + /* Set seed for random values for + * spatial dithering for R,G,B channels + */ + REG_SET(VPFMT_DITHER_RAND_R_SEED, 0, VPFMT_RAND_R_SEED, params->r_seed_value); + + REG_SET(VPFMT_DITHER_RAND_G_SEED, 0, VPFMT_RAND_G_SEED, params->g_seed_value); + + REG_SET(VPFMT_DITHER_RAND_B_SEED, 0, VPFMT_RAND_B_SEED, params->b_seed_value); + + /* FMT_OFFSET_R_Cr 31:16 0x0 Setting the zero + * offset for the R/Cr channel, lower 4LSB + * is forced to zeros. Typically set to 0 + * RGB and 0x80000 YCbCr. + */ + /* FMT_OFFSET_G_Y 31:16 0x0 Setting the zero + * offset for the G/Y channel, lower 4LSB is + * forced to zeros. Typically set to 0 RGB + * and 0x80000 YCbCr. + */ + /* FMT_OFFSET_B_Cb 31:16 0x0 Setting the zero + * offset for the B/Cb channel, lower 4LSB is + * forced to zeros. Typically set to 0 RGB and + * 0x80000 YCbCr. + */ + + REG_UPDATE_6(VPFMT_BIT_DEPTH_CONTROL, + /*Enable spatial dithering*/ + VPFMT_SPATIAL_DITHER_EN, params->flags.SPATIAL_DITHER_ENABLED, + /* Set spatial dithering mode + * (default is Seed patterrn AAAA...) + */ + VPFMT_SPATIAL_DITHER_MODE, params->flags.SPATIAL_DITHER_MODE, + /*Set spatial dithering bit depth*/ + VPFMT_SPATIAL_DITHER_DEPTH, params->flags.SPATIAL_DITHER_DEPTH, + /*Disable High pass filter*/ + VPFMT_HIGHPASS_RANDOM_ENABLE, params->flags.HIGHPASS_RANDOM, + /*Reset only at startup*/ + VPFMT_FRAME_RANDOM_ENABLE, params->flags.FRAME_RANDOM, + /*Set RGB data dithered with x^28+x^3+1*/ + VPFMT_RGB_RANDOM_ENABLE, params->flags.RGB_RANDOM); +} + +void vpe10_opp_program_bit_depth_reduction( + struct opp *opp, const struct bit_depth_reduction_params *fmt_bit_depth) +{ + opp->funcs->set_truncation(opp, fmt_bit_depth); + opp->funcs->set_spatial_dither(opp, fmt_bit_depth); +} + +void vpe10_opp_program_fmt(struct opp *opp, struct bit_depth_reduction_params *fmt_bit_depth, + struct clamping_and_pixel_encoding_params *clamping) +{ + opp->funcs->program_bit_depth_reduction(opp, fmt_bit_depth); + opp->funcs->set_clamping(opp, clamping); +} + +void vpe10_opp_program_pipe_alpha(struct opp *opp, uint16_t alpha) +{ + PROGRAM_ENTRY(); + REG_UPDATE(VPOPP_PIPE_CONTROL, VPOPP_PIPE_ALPHA, alpha); +} + +void vpe10_opp_program_pipe_bypass(struct opp *opp, bool enable) +{ + PROGRAM_ENTRY(); + REG_UPDATE(VPOPP_PIPE_CONTROL, VPOPP_PIPE_DIGITAL_BYPASS_EN, enable); +} + +void vpe10_opp_program_pipe_crc(struct opp *opp, bool enable) +{ + PROGRAM_ENTRY(); + REG_UPDATE(VPOPP_PIPE_CRC_CONTROL, VPOPP_PIPE_CRC_EN, enable); +} + diff --git a/src/amd/vpelib/src/chip/vpe10/vpe10_resource.c b/src/amd/vpelib/src/chip/vpe10/vpe10_resource.c new file mode 100644 index 00000000000..368b41c454a --- /dev/null +++ b/src/amd/vpelib/src/chip/vpe10/vpe10_resource.c @@ -0,0 +1,1085 @@ +/* Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ +#include +#include "vpe_priv.h" +#include "common.h" +#include "vpe10_resource.h" +#include "vpe10_cmd_builder.h" +#include "vpe10_vpec.h" +#include "vpe10_cdc.h" +#include "vpe10_dpp.h" +#include "vpe10_mpc.h" +#include "vpe10_opp.h" +#include "vpe_command.h" +#include "vpe10_cm_common.h" +#include "vpe10_background.h" +#include "vpe10/inc/asic/bringup_vpe_6_1_0_offset.h" +#include "vpe10/inc/asic/bringup_vpe_6_1_0_sh_mask.h" +#include "vpe10/inc/asic/bringup_vpe_6_1_0_default.h" +#include "vpe10/inc/asic/vpe_1_0_offset.h" +#include "custom_fp16.h" +#include "custom_float.h" +#include "background.h" +#include "vpe_visual_confirm.h" + +#define LUT_NUM_ENTRIES (17 * 17 * 17) +#define LUT_ENTRY_SIZE (2) +#define LUT_NUM_COMPONENT (3) +#define LUT_BUFFER_SIZE (LUT_NUM_ENTRIES * LUT_ENTRY_SIZE * LUT_NUM_COMPONENT) +// set field/register/bitfield name +#define SFRB(field_name, reg_name, post_fix) .field_name = reg_name##__##field_name##post_fix + +#define BASE_INNER(seg_id) VPE_BASE__INST0_SEG##seg_id + +#define BASE(seg_id) BASE_INNER(seg_id) + +// set register with block id and default val, init lastWrittenVal as default while isWritten set to +// false +#define SRIDFVL(reg_name, block, id) \ + .reg_name = {BASE(reg##reg_name##_BASE_IDX) + reg##reg_name, reg##reg_name##_##DEFAULT, \ + reg##reg_name##_##DEFAULT, false} + +/***************** CDC registers ****************/ +#define cdc_regs(id) [id] = {CDC_REG_LIST_VPE10(id)} + +static struct vpe10_cdc_registers cdc_regs[] = {cdc_regs(0)}; + +static const struct vpe10_cdc_shift cdc_shift = {CDC_FLIED_LIST_VPE10(__SHIFT)}; + +static const struct vpe10_cdc_mask cdc_mask = {CDC_FLIED_LIST_VPE10(_MASK)}; + +/***************** DPP registers ****************/ +#define dpp_regs(id) [id] = {DPP_REG_LIST_VPE10(id)} + +static struct vpe10_dpp_registers dpp_regs[] = {dpp_regs(0)}; + +static const struct vpe10_dpp_shift dpp_shift = {DPP_FIELD_LIST_VPE10(__SHIFT)}; + +static const struct vpe10_dpp_mask dpp_mask = {DPP_FIELD_LIST_VPE10(_MASK)}; + +/***************** MPC registers ****************/ +#define mpc_regs(id) [id] = {MPC_REG_LIST_VPE10(id)} + +static struct vpe10_mpc_registers mpc_regs[] = {mpc_regs(0)}; + +static const struct vpe10_mpc_shift mpc_shift = {MPC_FIELD_LIST_VPE10(__SHIFT)}; + +static const struct vpe10_mpc_mask mpc_mask = {MPC_FIELD_LIST_VPE10(_MASK)}; + +/***************** OPP registers ****************/ +#define opp_regs(id) [id] = {OPP_REG_LIST_VPE10(id)} + +static struct vpe10_opp_registers opp_regs[] = {opp_regs(0)}; + +static const struct vpe10_opp_shift opp_shift = {OPP_FIELD_LIST_VPE10(__SHIFT)}; + +static const struct vpe10_opp_mask opp_mask = {OPP_FIELD_LIST_VPE10(_MASK)}; + +static struct vpe_caps caps = { + .lut_size = LUT_BUFFER_SIZE, + .rotation_support = 0, + .h_mirror_support = 1, + .v_mirror_support = 0, + .is_apu = 1, + .bg_color_check_support = 0, + .resource_caps = + { + .num_dpp = 1, + .num_opp = 1, + .num_mpc_3dlut = 1, + .num_queue = 8, + }, + .color_caps = {.dpp = + { + .pre_csc = 1, + .luma_key = 0, + .dgam_ram = 0, + .post_csc = 1, + .gamma_corr = 1, + .hw_3dlut = 1, + .ogam_ram = 1, /**< programmable gam in output -> gamma_corr */ + .ocsc = 0, + .dgam_rom_caps = + { + .srgb = 1, + .bt2020 = 1, + .gamma2_2 = 1, + .pq = 1, + .hlg = 1, + }, + }, + .mpc = + { + .gamut_remap = 1, + .ogam_ram = 1, + .ocsc = 1, + .shared_3d_lut = 1, + .global_alpha = 1, + .top_bottom_blending = 0, + }}, + .plane_caps = + { + .per_pixel_alpha = 1, + .input_pixel_format_support = + { + .argb_packed_32b = 1, + .nv12 = 1, + .fp16 = 0, + .p010 = 1, /**< planar 4:2:0 10-bit */ + .p016 = 0, /**< planar 4:2:0 16-bit */ + .ayuv = 0, /**< packed 4:4:4 */ + .yuy2 = 0 /**< packed 4:2:2 */ + }, + .output_pixel_format_support = {.argb_packed_32b = 1, + .nv12 = 0, + .fp16 = 1, + .p010 = 0, + .p016 = 0, + .ayuv = 0, + .yuy2 = 0}, + .max_upscale_factor = 64000, + + // 6:1 downscaling ratio: 1000/6 = 166.666 + .max_downscale_factor = 167, + + .pitch_alignment = 256, + .addr_alignment = 256, + .max_viewport_width = 1024, + }, +}; + +static bool vpe10_init_scaler_data(struct vpe_priv *vpe_priv, struct stream_ctx *stream_ctx, + struct scaler_data *scl_data, struct vpe_rect *src_rect, struct vpe_rect *dst_rect) +{ + struct dpp *dpp = vpe_priv->resource.dpp[0]; + calculate_scaling_ratios(scl_data, src_rect, dst_rect, stream_ctx->stream.surface_info.format); + + if (!dpp->funcs->get_optimal_number_of_taps( + dpp, scl_data, &stream_ctx->stream.scaling_info.taps)) + return false; + + if ((stream_ctx->stream.use_external_scaling_coeffs == + false) || /* don't try to optimize is the scaler is configured externally*/ + (stream_ctx->stream.polyphase_scaling_coeffs.taps.h_taps == 0) || + (stream_ctx->stream.polyphase_scaling_coeffs.taps.v_taps == 0)) { + scl_data->polyphase_filter_coeffs = 0; + } else { + if ((stream_ctx->stream.polyphase_scaling_coeffs.taps.h_taps != + stream_ctx->stream.scaling_info.taps.h_taps) || + (stream_ctx->stream.polyphase_scaling_coeffs.taps.v_taps != + stream_ctx->stream.scaling_info.taps.v_taps)) { + return false; // sanity check to make sure the taps structures are the same + } + scl_data->taps = stream_ctx->stream.polyphase_scaling_coeffs + .taps; /* use the extenally provided tap configuration*/ + scl_data->polyphase_filter_coeffs = &stream_ctx->stream.polyphase_scaling_coeffs; + } + // bypass scaler if all ratios are 1 + if (IDENTITY_RATIO(scl_data->ratios.horz)) + scl_data->taps.h_taps = 1; + if (IDENTITY_RATIO(scl_data->ratios.vert)) + scl_data->taps.v_taps = 1; + + return true; +} + +enum vpe_status vpe10_set_num_segments(struct vpe_priv *vpe_priv, struct stream_ctx *stream_ctx, + struct scaler_data *scl_data, struct vpe_rect *src_rect, struct vpe_rect *dst_rect, + uint32_t *max_seg_width) +{ + + uint16_t num_segs; + struct dpp *dpp = vpe_priv->resource.dpp[0]; + const uint32_t max_lb_size = dpp->funcs->get_line_buffer_size(); + + *max_seg_width = min(*max_seg_width, max_lb_size / scl_data->taps.v_taps); + + num_segs = vpe_get_num_segments(vpe_priv, src_rect, dst_rect, *max_seg_width); + + stream_ctx->segment_ctx = vpe_alloc_segment_ctx(vpe_priv, num_segs); + if (!stream_ctx->segment_ctx) + return VPE_STATUS_NO_MEMORY; + + stream_ctx->num_segments = num_segs; + + return VPE_STATUS_OK; +} + +bool vpe10_get_dcc_compression_cap(const struct vpe *vpe, const struct vpe_dcc_surface_param *input, + struct vpe_surface_dcc_cap *output) +{ + struct vpe_priv *vpe_priv = container_of(vpe, struct vpe_priv, pub); + struct vpec *vpec = &vpe_priv->resource.vpec; + + return vpec->funcs->get_dcc_compression_cap(vpec, input, output); +} + +static struct vpe_cap_funcs cap_funcs = {.get_dcc_compression_cap = vpe10_get_dcc_compression_cap}; + +struct cdc *vpe10_cdc_create(struct vpe_priv *vpe_priv, int inst) +{ + struct vpe10_cdc *vpe10_cdc = vpe_zalloc(sizeof(struct vpe10_cdc)); + + if (!vpe10_cdc) + return NULL; + + vpe10_construct_cdc(vpe_priv, &vpe10_cdc->base); + + vpe10_cdc->regs = &cdc_regs[inst]; + vpe10_cdc->mask = &cdc_mask; + vpe10_cdc->shift = &cdc_shift; + + return &vpe10_cdc->base; +} + +struct dpp *vpe10_dpp_create(struct vpe_priv *vpe_priv, int inst) +{ + struct vpe10_dpp *vpe10_dpp = vpe_zalloc(sizeof(struct vpe10_dpp)); + + if (!vpe10_dpp) + return NULL; + + vpe10_construct_dpp(vpe_priv, &vpe10_dpp->base); + + vpe10_dpp->regs = &dpp_regs[inst]; + vpe10_dpp->mask = &dpp_mask; + vpe10_dpp->shift = &dpp_shift; + + return &vpe10_dpp->base; +} + +struct mpc *vpe10_mpc_create(struct vpe_priv *vpe_priv, int inst) +{ + struct vpe10_mpc *vpe10_mpc = vpe_zalloc(sizeof(struct vpe10_mpc)); + + if (!vpe10_mpc) + return NULL; + + vpe10_construct_mpc(vpe_priv, &vpe10_mpc->base); + + vpe10_mpc->regs = &mpc_regs[inst]; + vpe10_mpc->mask = &mpc_mask; + vpe10_mpc->shift = &mpc_shift; + + return &vpe10_mpc->base; +} + +struct opp *vpe10_opp_create(struct vpe_priv *vpe_priv, int inst) +{ + struct vpe10_opp *vpe10_opp = vpe_zalloc(sizeof(struct vpe10_opp)); + + if (!vpe10_opp) + return NULL; + + vpe10_construct_opp(vpe_priv, &vpe10_opp->base); + + vpe10_opp->regs = &opp_regs[inst]; + vpe10_opp->mask = &opp_mask; + vpe10_opp->shift = &opp_shift; + + return &vpe10_opp->base; +} + +enum vpe_status vpe10_construct_resource(struct vpe_priv *vpe_priv, struct resource *res) +{ + struct vpe *vpe = &vpe_priv->pub; + + vpe->caps = ∩︀ + vpe->cap_funcs = &cap_funcs; + + vpe10_construct_vpec(vpe_priv, &res->vpec); + + res->cdc[0] = vpe10_cdc_create(vpe_priv, 0); + if (!res->cdc[0]) + goto err; + + res->dpp[0] = vpe10_dpp_create(vpe_priv, 0); + if (!res->dpp[0]) + goto err; + + res->mpc[0] = vpe10_mpc_create(vpe_priv, 0); + if (!res->mpc[0]) + goto err; + + res->opp[0] = vpe10_opp_create(vpe_priv, 0); + if (!res->opp[0]) + goto err; + + vpe10_construct_cmd_builder(vpe_priv, &res->cmd_builder); + vpe_priv->num_pipe = 1; + + res->internal_hdr_normalization = 1; + + res->check_input_color_space = vpe10_check_input_color_space; + res->check_output_color_space = vpe10_check_output_color_space; + res->check_h_mirror_support = vpe10_check_h_mirror_support; + res->calculate_segments = vpe10_calculate_segments; + res->set_num_segments = vpe10_set_num_segments; + res->split_bg_gap = vpe10_split_bg_gap; + res->calculate_dst_viewport_and_active = vpe10_calculate_dst_viewport_and_active; + res->find_bg_gaps = vpe_find_bg_gaps; + res->create_bg_segments = vpe_create_bg_segments; + res->populate_cmd_info = vpe10_populate_cmd_info; + res->program_frontend = vpe10_program_frontend; + res->program_backend = vpe10_program_backend; + res->get_bufs_req = vpe10_get_bufs_req; + res->get_tf_pwl_params = vpe10_cm_get_tf_pwl_params; + + return VPE_STATUS_OK; +err: + vpe10_destroy_resource(vpe_priv, res); + return VPE_STATUS_ERROR; +} + +void vpe10_destroy_resource(struct vpe_priv *vpe_priv, struct resource *res) +{ + if (res->cdc[0] != NULL) { + vpe_free(container_of(res->cdc[0], struct vpe10_cdc, base)); + res->cdc[0] = NULL; + } + + if (res->dpp[0] != NULL) { + vpe_free(container_of(res->dpp[0], struct vpe10_dpp, base)); + res->dpp[0] = NULL; + } + + if (res->mpc[0] != NULL) { + vpe_free(container_of(res->mpc[0], struct vpe10_mpc, base)); + res->mpc[0] = NULL; + } + + if (res->opp[0] != NULL) { + vpe_free(container_of(res->opp[0], struct vpe10_opp, base)); + res->opp[0] = NULL; + } +} + +bool vpe10_check_input_color_space(struct vpe_priv *vpe_priv, enum vpe_surface_pixel_format format, + const struct vpe_color_space *vcs) +{ + enum color_space cs; + enum color_transfer_func tf; + + vpe_color_get_color_space_and_tf(vcs, &cs, &tf); + if (cs == COLOR_SPACE_UNKNOWN || tf == TRANSFER_FUNC_UNKNOWN) + return false; + + return true; +} + +bool vpe10_check_output_color_space(struct vpe_priv *vpe_priv, enum vpe_surface_pixel_format format, + const struct vpe_color_space *vcs) +{ + enum color_space cs; + enum color_transfer_func tf; + + // packed 32bit rgb + if (vcs->encoding != VPE_PIXEL_ENCODING_RGB) + return false; + + vpe_color_get_color_space_and_tf(vcs, &cs, &tf); + if (cs == COLOR_SPACE_UNKNOWN || tf == TRANSFER_FUNC_UNKNOWN) + return false; + + return true; +} + +bool vpe10_check_h_mirror_support(bool *input_mirror, bool *output_mirror) +{ + *input_mirror = false; + *output_mirror = true; + return true; +} + +void vpe10_calculate_dst_viewport_and_active( + struct segment_ctx *segment_ctx, uint32_t max_seg_width) +{ + struct scaler_data *data = &segment_ctx->scaler_data; + struct stream_ctx *stream_ctx = segment_ctx->stream_ctx; + struct vpe_priv *vpe_priv = stream_ctx->vpe_priv; + struct vpe_rect *dst_rect = &stream_ctx->stream.scaling_info.dst_rect; + struct vpe_rect *target_rect = &vpe_priv->output_ctx.target_rect; + + uint32_t vpc_div = vpe_is_yuv420(vpe_priv->output_ctx.surface.format) ? 2 : 1; + + data->dst_viewport.x = data->recout.x + dst_rect->x; + data->dst_viewport.width = data->recout.width; + + // 1st stream will cover the background + // extends the v_active to cover the full target_rect's height + if (stream_ctx->stream_idx == 0) { + data->recout.x = 0; + data->recout.y = dst_rect->y - target_rect->y; + data->dst_viewport.y = target_rect->y; + data->dst_viewport.height = target_rect->height; + + if (!stream_ctx->flip_horizonal_output) { + /* first segment : + * if the dst_viewport.width is not 1024, + * and we need background on the left, extend the active to cover as much as it can + */ + if (segment_ctx->segment_idx == 0) { + uint32_t remain_gap = min(max_seg_width - data->dst_viewport.width, + (uint32_t)(data->dst_viewport.x - target_rect->x)); + data->recout.x = (int32_t)remain_gap; + + data->dst_viewport.x -= (int32_t)remain_gap; + data->dst_viewport.width += remain_gap; + } + // last segment + if (segment_ctx->segment_idx == stream_ctx->num_segments - 1) { + uint32_t remain_gap = min(max_seg_width - data->dst_viewport.width, + (uint32_t)((target_rect->x + (int32_t)target_rect->width) - + (data->dst_viewport.x + (int32_t)data->dst_viewport.width))); + + data->dst_viewport.width += remain_gap; + } + } + } else { + data->dst_viewport.y = data->recout.y + dst_rect->y; + data->dst_viewport.height = data->recout.height; + data->recout.y = 0; + data->recout.x = 0; + } + + data->dst_viewport_c.x = data->dst_viewport.x / (int32_t)vpc_div; + data->dst_viewport_c.y = data->dst_viewport.y / (int32_t)vpc_div; + data->dst_viewport_c.width = data->dst_viewport.width / vpc_div; + data->dst_viewport_c.height = data->dst_viewport.height / vpc_div; + + // [h/v]_active + data->h_active = data->dst_viewport.width; + data->v_active = data->dst_viewport.height; +} + +enum vpe_status vpe10_calculate_segments( + struct vpe_priv *vpe_priv, const struct vpe_build_param *params) +{ + enum vpe_status res; + struct vpe_rect *gaps; + uint16_t gaps_cnt, max_gaps; + uint16_t stream_idx, seg_idx; + struct stream_ctx *stream_ctx; + struct segment_ctx *segment_ctx; + uint32_t max_seg_width = vpe_priv->pub.caps->plane_caps.max_viewport_width; + struct scaler_data scl_data; + struct vpe_rect *src_rect; + struct vpe_rect *dst_rect; + uint32_t factor; + const uint32_t max_upscale_factor = vpe_priv->pub.caps->plane_caps.max_upscale_factor; + const uint32_t max_downscale_factor = vpe_priv->pub.caps->plane_caps.max_downscale_factor; + struct dpp *dpp = vpe_priv->resource.dpp[0]; + const uint32_t max_lb_size = dpp->funcs->get_line_buffer_size(); + + for (stream_idx = 0; stream_idx < params->num_streams; stream_idx++) { + stream_ctx = &vpe_priv->stream_ctx[stream_idx]; + src_rect = &stream_ctx->stream.scaling_info.src_rect; + dst_rect = &stream_ctx->stream.scaling_info.dst_rect; + + if (src_rect->width < VPE_MIN_VIEWPORT_SIZE || src_rect->height < VPE_MIN_VIEWPORT_SIZE || + dst_rect->width < VPE_MIN_VIEWPORT_SIZE || dst_rect->height < VPE_MIN_VIEWPORT_SIZE) { + return VPE_STATUS_VIEWPORT_SIZE_NOT_SUPPORTED; + } + + vpe_clip_stream(src_rect, dst_rect, ¶ms->target_rect); + + if (src_rect->width <= 0 || src_rect->height <= 0 || dst_rect->width <= 0 || + dst_rect->height <= 0) { + vpe_log("calculate_segments: after clipping, src or dst rect contains no area. Skip " + "this stream.\n"); + stream_ctx->num_segments = 0; + continue; + } + + /* If the source frame size in either dimension is 1 then the scaling ratio becomes 0 + * in that dimension. If destination frame size in any dimesnion is 1 the scaling ratio + * is NAN. + */ + if (src_rect->width < VPE_MIN_VIEWPORT_SIZE || src_rect->height < VPE_MIN_VIEWPORT_SIZE || + dst_rect->width < VPE_MIN_VIEWPORT_SIZE || dst_rect->height < VPE_MIN_VIEWPORT_SIZE) { + return VPE_STATUS_VIEWPORT_SIZE_NOT_SUPPORTED; + } + factor = (uint32_t)vpe_fixpt_ceil( + vpe_fixpt_from_fraction((1000 * dst_rect->width), src_rect->width)); + if (factor > max_upscale_factor || factor < max_downscale_factor) + return VPE_STATUS_SCALING_RATIO_NOT_SUPPORTED; + + // initialize scaling data + if (!vpe10_init_scaler_data(vpe_priv, stream_ctx, &scl_data, src_rect, dst_rect)) + return VPE_STATUS_SCALING_RATIO_NOT_SUPPORTED; + + res = vpe_priv->resource.set_num_segments( + vpe_priv, stream_ctx, &scl_data, src_rect, dst_rect, &max_seg_width); + if (res != VPE_STATUS_OK) + return res; + + for (seg_idx = 0; seg_idx < stream_ctx->num_segments; seg_idx++) { + segment_ctx = &stream_ctx->segment_ctx[seg_idx]; + segment_ctx->segment_idx = seg_idx; + segment_ctx->stream_ctx = stream_ctx; + + segment_ctx->scaler_data.ratios = scl_data.ratios; + segment_ctx->scaler_data.taps = scl_data.taps; + if (stream_ctx->stream.use_external_scaling_coeffs) { + segment_ctx->scaler_data.polyphase_filter_coeffs = + &stream_ctx->stream.polyphase_scaling_coeffs; + } else { + segment_ctx->scaler_data.polyphase_filter_coeffs = 0; + } + res = vpe_resource_build_scaling_params(segment_ctx); + if (res != VPE_STATUS_OK) + return res; + + vpe_priv->resource.calculate_dst_viewport_and_active(segment_ctx, max_seg_width); + } + } + + /* If the stream width is less than max_seg_width - 1024, and it + * lies inside a max_seg_width window of the background, vpe needs + * an extra bg segment to store that. + 1 2 3 4 5 + |....|....|.**.|....| + |....|....|.**.|....| + |....|....|.**.|....| + + (*: stream + .: background + |: 1k separator) + + */ + max_seg_width = vpe_priv->pub.caps->plane_caps.max_viewport_width; + max_gaps = + (uint16_t)(max((params->target_rect.width + max_seg_width - 1) / max_seg_width, 1) + 1); + gaps = vpe_zalloc(sizeof(struct vpe_rect) * max_gaps); + if (!gaps) + return VPE_STATUS_NO_MEMORY; + + gaps_cnt = vpe_priv->resource.find_bg_gaps(vpe_priv, &(params->target_rect), gaps, max_gaps); + if (gaps_cnt > 0) + vpe_priv->resource.create_bg_segments(vpe_priv, gaps, gaps_cnt, VPE_CMD_OPS_BG); + + if (gaps != NULL) { + vpe_free(gaps); + gaps = NULL; + } + + vpe_handle_output_h_mirror(vpe_priv); + + res = vpe_priv->resource.populate_cmd_info(vpe_priv); + + if (res == VPE_STATUS_OK) + res = vpe_create_visual_confirm_segs(vpe_priv, params, max_seg_width); + + return res; +} + +static void build_clamping_params( + struct opp *opp, struct clamping_and_pixel_encoding_params *clamping) +{ + struct vpe_priv *vpe_priv = opp->vpe_priv; + struct vpe_surface_info *dst_surface = &vpe_priv->output_ctx.surface; + enum vpe_color_range output_range = dst_surface->cs.range; + + memset(clamping, 0, sizeof(*clamping)); + clamping->clamping_level = CLAMPING_FULL_RANGE; + clamping->c_depth = vpe_get_color_depth(dst_surface->format); + if (output_range == VPE_COLOR_RANGE_STUDIO) { + if (!vpe_priv->init.debug.clamping_setting) { + switch (clamping->c_depth) { + case COLOR_DEPTH_888: + clamping->clamping_level = CLAMPING_LIMITED_RANGE_8BPC; + break; + case COLOR_DEPTH_101010: + clamping->clamping_level = CLAMPING_LIMITED_RANGE_10BPC; + break; + case COLOR_DEPTH_121212: + clamping->clamping_level = CLAMPING_LIMITED_RANGE_12BPC; + break; + default: + clamping->clamping_level = + CLAMPING_FULL_RANGE; // for all the others bit depths set the full range + break; + } + } else { + switch (vpe_priv->init.debug.clamping_params.clamping_range) { + case VPE_CLAMPING_LIMITED_RANGE_8BPC: + clamping->clamping_level = CLAMPING_LIMITED_RANGE_8BPC; + break; + case VPE_CLAMPING_LIMITED_RANGE_10BPC: + clamping->clamping_level = CLAMPING_LIMITED_RANGE_10BPC; + break; + case VPE_CLAMPING_LIMITED_RANGE_12BPC: + clamping->clamping_level = CLAMPING_LIMITED_RANGE_12BPC; + break; + default: + clamping->clamping_level = + CLAMPING_LIMITED_RANGE_PROGRAMMABLE; // for all the others set to programmable + // range + clamping->r_clamp_component_lower = + vpe_priv->output_ctx.clamping_params.r_clamp_component_lower; + clamping->g_clamp_component_lower = + vpe_priv->output_ctx.clamping_params.g_clamp_component_lower; + clamping->b_clamp_component_lower = + vpe_priv->output_ctx.clamping_params.b_clamp_component_lower; + clamping->r_clamp_component_upper = + vpe_priv->output_ctx.clamping_params.r_clamp_component_upper; + clamping->g_clamp_component_upper = + vpe_priv->output_ctx.clamping_params.g_clamp_component_upper; + clamping->b_clamp_component_upper = + vpe_priv->output_ctx.clamping_params.b_clamp_component_upper; + break; + } + } + } +} + +static void frontend_config_callback( + void *ctx, uint64_t cfg_base_gpu, uint64_t cfg_base_cpu, int64_t size) +{ + struct config_frontend_cb_ctx *cb_ctx = (struct config_frontend_cb_ctx *)ctx; + struct vpe_priv *vpe_priv = cb_ctx->vpe_priv; + struct stream_ctx *stream_ctx = &vpe_priv->stream_ctx[cb_ctx->stream_idx]; + enum vpe_cmd_type cmd_type; + + if (cb_ctx->stream_sharing) { + VPE_ASSERT(stream_ctx->num_configs < + (int)(sizeof(stream_ctx->configs) / sizeof(struct config_record))); + + stream_ctx->configs[stream_ctx->num_configs].config_base_addr = cfg_base_gpu; + stream_ctx->configs[stream_ctx->num_configs].config_size = size; + stream_ctx->num_configs++; + } else if (cb_ctx->stream_op_sharing) { + cmd_type = cb_ctx->cmd_type; + + VPE_ASSERT( + stream_ctx->num_stream_op_configs[cmd_type] < + (int)(sizeof(stream_ctx->stream_op_configs[cmd_type]) / sizeof(struct config_record))); + + stream_ctx->stream_op_configs[cmd_type][stream_ctx->num_stream_op_configs[cmd_type]] + .config_base_addr = cfg_base_gpu; + stream_ctx->stream_op_configs[cmd_type][stream_ctx->num_stream_op_configs[cmd_type]] + .config_size = size; + stream_ctx->num_stream_op_configs[cmd_type]++; + } + + vpe_desc_writer_add_config_desc( + &vpe_priv->vpe_desc_writer, cfg_base_gpu, false, vpe_priv->config_writer.buf->tmz); +} + +int32_t vpe10_program_frontend(struct vpe_priv *vpe_priv, uint32_t pipe_idx, uint32_t cmd_idx, + uint32_t cmd_input_idx, bool seg_only) +{ + struct vpe_cmd_info *cmd_info = &vpe_priv->vpe_cmd_info[cmd_idx]; + struct vpe_cmd_input *cmd_input = &cmd_info->inputs[cmd_input_idx]; + struct stream_ctx *stream_ctx = &vpe_priv->stream_ctx[cmd_input->stream_idx]; + struct vpe_surface_info *surface_info = &stream_ctx->stream.surface_info; + struct cdc *cdc = vpe_priv->resource.cdc[pipe_idx]; + struct dpp *dpp = vpe_priv->resource.dpp[pipe_idx]; + struct mpc *mpc = vpe_priv->resource.mpc[pipe_idx]; + enum input_csc_select select = INPUT_CSC_SELECT_BYPASS; + uint32_t hw_mult = 0; + struct custom_float_format fmt; + + vpe_priv->fe_cb_ctx.stream_idx = cmd_input->stream_idx; + vpe_priv->fe_cb_ctx.vpe_priv = vpe_priv; + + config_writer_set_callback( + &vpe_priv->config_writer, &vpe_priv->fe_cb_ctx, frontend_config_callback); + + config_writer_set_type(&vpe_priv->config_writer, CONFIG_TYPE_DIRECT); + + if (!seg_only) { + /* start front-end programming that can be shared among segments */ + vpe_priv->fe_cb_ctx.stream_sharing = true; + + cdc->funcs->program_surface_config(cdc, surface_info->format, stream_ctx->stream.rotation, + // set to false as h_mirror is not supported by input, only supported in output + false, surface_info->swizzle); + cdc->funcs->program_crossbar_config(cdc, surface_info->format); + + dpp->funcs->program_cnv(dpp, surface_info->format, vpe_priv->expansion_mode); + if (stream_ctx->bias_scale) + dpp->funcs->program_cnv_bias_scale(dpp, stream_ctx->bias_scale); + + /* If input adjustment exists, program the ICSC with those values. */ + if (stream_ctx->input_cs) { + select = INPUT_CSC_SELECT_ICSC; + dpp->funcs->program_post_csc(dpp, stream_ctx->cs, select, stream_ctx->input_cs); + } else { + dpp->funcs->program_post_csc(dpp, stream_ctx->cs, select, NULL); + } + dpp->funcs->program_input_transfer_func(dpp, stream_ctx->input_tf); + dpp->funcs->program_gamut_remap(dpp, stream_ctx->gamut_remap); + + // for not bypass mode, we always are in single layer coming from DPP and output to OPP + mpc->funcs->program_mpcc_mux(mpc, MPC_MPCCID_0, MPC_MUX_TOPSEL_DPP0, MPC_MUX_BOTSEL_DISABLE, + MPC_MUX_OUTMUX_MPCC0, MPC_MUX_OPPID_OPP0); + + // program shaper, 3dlut and 1dlut in MPC for stream before blend + mpc->funcs->program_movable_cm( + mpc, stream_ctx->in_shaper_func, stream_ctx->lut3d_func, stream_ctx->blend_tf, false); + + // program hdr_mult + fmt.exponenta_bits = 6; + fmt.mantissa_bits = 12; + fmt.sign = true; + if (stream_ctx->stream.tm_params.enable_3dlut) { + vpe_convert_to_custom_float_format( + stream_ctx->lut3d_func->hdr_multiplier, &fmt, &hw_mult); + } else { + vpe_convert_to_custom_float_format(stream_ctx->white_point_gain, &fmt, &hw_mult); + } + dpp->funcs->set_hdr_multiplier(dpp, hw_mult); + + if (vpe_priv->init.debug.dpp_crc_ctrl) + dpp->funcs->program_crc(dpp, true); + + if (vpe_priv->init.debug.mpc_crc_ctrl) + mpc->funcs->program_crc(mpc, true); + + // put other hw programming for stream specific that can be shared here + + config_writer_complete(&vpe_priv->config_writer); + } + + vpe10_create_stream_ops_config(vpe_priv, pipe_idx, stream_ctx, cmd_input, cmd_info->ops); + + /* start segment specific programming */ + vpe_priv->fe_cb_ctx.stream_sharing = false; + vpe_priv->fe_cb_ctx.stream_op_sharing = false; + vpe_priv->fe_cb_ctx.cmd_type = VPE_CMD_TYPE_COMPOSITING; + + cdc->funcs->program_viewport( + cdc, &cmd_input->scaler_data.viewport, &cmd_input->scaler_data.viewport_c); + + dpp->funcs->set_segment_scaler(dpp, &cmd_input->scaler_data); + + config_writer_complete(&vpe_priv->config_writer); + + return 0; +} + +static void backend_config_callback( + void *ctx, uint64_t cfg_base_gpu, uint64_t cfg_base_cpu, int64_t size) +{ + struct config_backend_cb_ctx *cb_ctx = (struct config_backend_cb_ctx *)ctx; + struct vpe_priv *vpe_priv = cb_ctx->vpe_priv; + struct output_ctx *output_ctx = &vpe_priv->output_ctx; + + if (cb_ctx->share) { + VPE_ASSERT( + output_ctx->num_configs < (sizeof(output_ctx->configs) / sizeof(struct config_record))); + + output_ctx->configs[output_ctx->num_configs].config_base_addr = cfg_base_gpu; + output_ctx->configs[output_ctx->num_configs].config_size = size; + output_ctx->num_configs++; + } + + vpe_desc_writer_add_config_desc( + &vpe_priv->vpe_desc_writer, cfg_base_gpu, false, vpe_priv->config_writer.buf->tmz); +} + +int32_t vpe10_program_backend( + struct vpe_priv *vpe_priv, uint32_t pipe_idx, uint32_t cmd_idx, bool seg_only) +{ + struct output_ctx *output_ctx = &vpe_priv->output_ctx; + struct vpe_surface_info *surface_info = &vpe_priv->output_ctx.surface; + + struct cdc *cdc = vpe_priv->resource.cdc[pipe_idx]; + struct opp *opp = vpe_priv->resource.opp[pipe_idx]; + struct mpc *mpc = vpe_priv->resource.mpc[pipe_idx]; + + struct bit_depth_reduction_params fmt_bit_depth; + struct clamping_and_pixel_encoding_params clamp_param; + enum color_depth display_color_depth; + uint16_t alpha_16; + bool opp_dig_bypass = false; + + vpe_priv->be_cb_ctx.vpe_priv = vpe_priv; + config_writer_set_callback( + &vpe_priv->config_writer, &vpe_priv->be_cb_ctx, backend_config_callback); + + config_writer_set_type(&vpe_priv->config_writer, CONFIG_TYPE_DIRECT); + + if (!seg_only) { + /* start back-end programming that can be shared among segments */ + vpe_priv->be_cb_ctx.share = true; + + cdc->funcs->program_p2b_config(cdc, surface_info->format); + cdc->funcs->program_global_sync(cdc, VPE10_CDC_VUPDATE_OFFSET_DEFAULT, + VPE10_CDC_VUPDATE_WIDTH_DEFAULT, VPE10_CDC_VREADY_OFFSET_DEFAULT); + + mpc->funcs->program_output_csc(mpc, surface_info->format, output_ctx->cs, NULL); + mpc->funcs->set_output_transfer_func(mpc, output_ctx); + // program shaper, 3dlut and 1dlut in MPC for after blend + // Note: cannot program both before and after blend CM + // caller should ensure only one is programmed + // mpc->funcs->program_movable_cm(mpc, output_ctx->in_shaper_func, + // output_ctx->lut3d_func, output_ctx->blend_tf, true); + mpc->funcs->program_mpc_out(mpc, surface_info->format); + + // Post blend gamut remap + mpc->funcs->set_gamut_remap(mpc, output_ctx->gamut_remap); + + if (vpe_is_fp16(surface_info->format)) { + if (vpe_priv->output_ctx.alpha_mode == VPE_ALPHA_BGCOLOR) + vpe_convert_from_float_to_fp16( + (double)vpe_priv->output_ctx.bg_color.rgba.a, &alpha_16); + else + vpe_convert_from_float_to_fp16(1.0, &alpha_16); + + opp_dig_bypass = true; + } else { + if (vpe_priv->output_ctx.alpha_mode == VPE_ALPHA_BGCOLOR) + alpha_16 = (uint16_t)(vpe_priv->output_ctx.bg_color.rgba.a * 0xffff); + else + alpha_16 = 0xffff; + } + + opp->funcs->program_pipe_alpha(opp, alpha_16); + opp->funcs->program_pipe_bypass(opp, opp_dig_bypass); + + display_color_depth = vpe_get_color_depth(surface_info->format); + build_clamping_params(opp, &clamp_param); + vpe_resource_build_bit_depth_reduction_params(opp, &fmt_bit_depth); + + // disable dynamic expansion for now as no use case + opp->funcs->set_dyn_expansion(opp, false, display_color_depth); + opp->funcs->program_fmt(opp, &fmt_bit_depth, &clamp_param); + if (vpe_priv->init.debug.opp_pipe_crc_ctrl) + opp->funcs->program_pipe_crc(opp, true); + + config_writer_complete(&vpe_priv->config_writer); + } + + return 0; +} + +enum vpe_status vpe10_populate_cmd_info(struct vpe_priv *vpe_priv) +{ + uint16_t stream_idx; + uint16_t segment_idx; + struct stream_ctx *stream_ctx; + struct vpe_cmd_info *cmd_info; + bool tm_enabled; + + for (stream_idx = 0; stream_idx < vpe_priv->num_streams; stream_idx++) { + stream_ctx = &vpe_priv->stream_ctx[stream_idx]; + + tm_enabled = stream_ctx->stream.tm_params.enable_3dlut; + + for (segment_idx = 0; segment_idx < stream_ctx->num_segments; segment_idx++) { + if (vpe_priv->num_vpe_cmds >= MAX_VPE_CMD) { + return VPE_STATUS_CMD_OVERFLOW_ERROR; + } + + cmd_info = &vpe_priv->vpe_cmd_info[vpe_priv->num_vpe_cmds]; + cmd_info->inputs[0].stream_idx = stream_idx; + cmd_info->cd = (uint8_t)(stream_ctx->num_segments - segment_idx - 1); + memcpy(&(cmd_info->inputs[0].scaler_data), + &(stream_ctx->segment_ctx[segment_idx].scaler_data), sizeof(struct scaler_data)); + cmd_info->dst_viewport = stream_ctx->segment_ctx[segment_idx].scaler_data.dst_viewport; + cmd_info->dst_viewport_c = + stream_ctx->segment_ctx[segment_idx].scaler_data.dst_viewport_c; + cmd_info->num_inputs = 1; + cmd_info->ops = VPE_CMD_OPS_COMPOSITING; + cmd_info->tm_enabled = tm_enabled; + vpe_priv->num_vpe_cmds++; + if (cmd_info->cd == (stream_ctx->num_segments - 1)) { + cmd_info->is_begin = true; + } + + if (cmd_info->cd == 0) { + cmd_info->is_end = true; + } + } + } + + return VPE_STATUS_OK; +} + +void vpe10_create_stream_ops_config(struct vpe_priv *vpe_priv, uint32_t pipe_idx, + struct stream_ctx *stream_ctx, struct vpe_cmd_input *cmd_input, enum vpe_cmd_ops ops) +{ + /* put all hw programming that can be shared according to the cmd type within a stream here */ + struct mpcc_blnd_cfg blndcfg = {0}; + struct dpp *dpp = vpe_priv->resource.dpp[pipe_idx]; + struct mpc *mpc = vpe_priv->resource.mpc[pipe_idx]; + enum vpe_cmd_type cmd_type = VPE_CMD_TYPE_COUNT; + + vpe_priv->fe_cb_ctx.stream_op_sharing = true; + vpe_priv->fe_cb_ctx.stream_sharing = false; + + if (ops == VPE_CMD_OPS_BG) { + cmd_type = VPE_CMD_TYPE_BG; + } else if (ops == VPE_CMD_OPS_COMPOSITING) { + cmd_type = VPE_CMD_TYPE_COMPOSITING; + } else if (ops == VPE_CMD_OPS_BG_VSCF_INPUT) { + cmd_type = VPE_CMD_TYPE_BG_VSCF_INPUT; + } else if (ops == VPE_CMD_OPS_BG_VSCF_OUTPUT) { + cmd_type = VPE_CMD_TYPE_BG_VSCF_OUTPUT; + } else + return; + + // return if already generated + if (stream_ctx->num_stream_op_configs[cmd_type]) + return; + + vpe_priv->fe_cb_ctx.cmd_type = cmd_type; + + dpp->funcs->set_frame_scaler(dpp, &cmd_input->scaler_data); + + if (ops == VPE_CMD_OPS_BG_VSCF_INPUT) { + blndcfg.bg_color = vpe_get_visual_confirm_color(stream_ctx->stream.surface_info.format, + stream_ctx->stream.surface_info.cs, vpe_priv->output_ctx.cs, + vpe_priv->output_ctx.output_tf, stream_ctx->stream.tm_params.enable_3dlut); + } else if (ops == VPE_CMD_OPS_BG_VSCF_OUTPUT) { + blndcfg.bg_color = vpe_get_visual_confirm_color(vpe_priv->output_ctx.surface.format, + vpe_priv->output_ctx.surface.cs, vpe_priv->output_ctx.cs, + vpe_priv->output_ctx.output_tf, + false); // 3DLUT should only affect input visual confirm + } else { + blndcfg.bg_color = vpe_priv->output_ctx.bg_color; + } + blndcfg.global_gain = 0xff; + blndcfg.pre_multiplied_alpha = false; + + if (stream_ctx->stream.blend_info.blending) { + if (stream_ctx->per_pixel_alpha) { + blndcfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN; + + blndcfg.pre_multiplied_alpha = stream_ctx->stream.blend_info.pre_multiplied_alpha; + if (stream_ctx->stream.blend_info.global_alpha) + blndcfg.global_gain = + (uint8_t)(stream_ctx->stream.blend_info.global_alpha_value * 0xff); + } else { + blndcfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA; + if (stream_ctx->stream.blend_info.global_alpha == true) { + VPE_ASSERT(stream_ctx->stream.blend_info.global_alpha_value <= 1.0f); + blndcfg.global_alpha = + (uint8_t)(stream_ctx->stream.blend_info.global_alpha_value * 0xff); + } else { + // Global alpha not enabled, make top layer opaque + blndcfg.global_alpha = 0xff; + } + } + } else { + blndcfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA; + blndcfg.global_alpha = 0xff; + } + + if (cmd_type == VPE_CMD_TYPE_BG || cmd_type == VPE_CMD_TYPE_BG_VSCF_INPUT || + cmd_type == VPE_CMD_TYPE_BG_VSCF_OUTPUT) { + // for bg commands, make top layer transparent + // as global alpha only works when global alpha mode, set global alpha mode as well + blndcfg.global_alpha = 0; + blndcfg.global_gain = 0xff; + blndcfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA; + } + + blndcfg.overlap_only = false; + blndcfg.bottom_gain_mode = 0; + + switch (vpe_priv->init.debug.bg_bit_depth) { + case 8: + blndcfg.background_color_bpc = 0; + break; + case 9: + blndcfg.background_color_bpc = 1; + break; + case 10: + blndcfg.background_color_bpc = 2; + break; + case 11: + blndcfg.background_color_bpc = 3; + break; + case 12: + default: + blndcfg.background_color_bpc = 4; // 12 bit. DAL's choice; + break; + } + + blndcfg.top_gain = 0x1f000; + blndcfg.bottom_inside_gain = 0x1f000; + blndcfg.bottom_outside_gain = 0x1f000; + + mpc->funcs->program_mpcc_blending(mpc, MPC_MPCCID_0, &blndcfg); + + config_writer_complete(&vpe_priv->config_writer); +} + +#define VPE10_GENERAL_VPE_DESC_SIZE 64 // 4 * (4 + (2 * num_configs)) +#define VPE10_GENERAL_EMB_USAGE_FRAME_SHARED 6000 // currently max 4804 is recorded +#define VPE10_GENERAL_EMB_USAGE_3DLUT_FRAME_SHARED 40960 // currently max 35192 is recorded +#define VPE10_GENERAL_EMB_USAGE_BG_SHARED 2400 // currently max 1772 + 92 + 72 = 1936 is recorded +#define VPE10_GENERAL_EMB_USAGE_SEG_NON_SHARED \ + 240 // segment specific config + plane descripor size. currently max 92 + 72 = 164 is recorded. + +void vpe10_get_bufs_req(struct vpe_priv *vpe_priv, struct vpe_bufs_req *req) +{ + uint32_t i; + struct vpe_cmd_info *cmd_info; + uint32_t stream_idx = 0xFFFFFFFF; + uint64_t emb_req = 0; + bool have_visual_confirm_input = false; + bool have_visual_confirm_output = false; + + req->cmd_buf_size = 0; + req->emb_buf_size = 0; + + for (i = 0; i < vpe_priv->num_vpe_cmds; i++) { + cmd_info = &vpe_priv->vpe_cmd_info[i]; + + // each cmd consumes one VPE descriptor + req->cmd_buf_size += VPE10_GENERAL_VPE_DESC_SIZE; + + // if a command represents the first segment of a stream, + // total amount of config sizes is added, but for other segments + // just the segment specific config size is added + if (cmd_info->ops == VPE_CMD_OPS_COMPOSITING) { + if (stream_idx != cmd_info->inputs[0].stream_idx) { + emb_req = cmd_info->tm_enabled ? VPE10_GENERAL_EMB_USAGE_3DLUT_FRAME_SHARED + : VPE10_GENERAL_EMB_USAGE_FRAME_SHARED; + stream_idx = cmd_info->inputs[0].stream_idx; + } else { + emb_req = VPE10_GENERAL_EMB_USAGE_SEG_NON_SHARED; + } + } else if (cmd_info->ops == VPE_CMD_OPS_BG) { + emb_req = + i > 0 ? VPE10_GENERAL_EMB_USAGE_SEG_NON_SHARED : VPE10_GENERAL_EMB_USAGE_BG_SHARED; + } else if (cmd_info->ops == VPE_CMD_OPS_BG_VSCF_INPUT) { + emb_req = have_visual_confirm_input ? VPE10_GENERAL_EMB_USAGE_SEG_NON_SHARED + : VPE10_GENERAL_EMB_USAGE_BG_SHARED; + have_visual_confirm_input = true; + } else if (cmd_info->ops == VPE_CMD_OPS_BG_VSCF_OUTPUT) { + emb_req = have_visual_confirm_output ? VPE10_GENERAL_EMB_USAGE_SEG_NON_SHARED + : VPE10_GENERAL_EMB_USAGE_BG_SHARED; + have_visual_confirm_output = true; + } else { + VPE_ASSERT(0); + } + + req->emb_buf_size += emb_req; + } +} diff --git a/src/amd/vpelib/src/chip/vpe10/vpe10_vpec.c b/src/amd/vpelib/src/chip/vpe10/vpe10_vpec.c new file mode 100644 index 00000000000..d8909d036df --- /dev/null +++ b/src/amd/vpelib/src/chip/vpe10/vpe10_vpec.c @@ -0,0 +1,63 @@ +/* Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include "vpe10_vpec.h" + +static struct vpec_funcs vpec_funcs = { + .check_swmode_support = vpe10_vpec_check_swmode_support, + .get_dcc_compression_cap = vpe10_vpec_get_dcc_compression_cap, +}; + +void vpe10_construct_vpec(struct vpe_priv *vpe_priv, struct vpec *vpec) +{ + vpec->vpe_priv = vpe_priv; + vpec->funcs = &vpec_funcs; +} + +/** functions for capability check */ +bool vpe10_vpec_check_swmode_support(struct vpec *vpec, enum vpe_swizzle_mode_values sw_mode) +{ + switch (sw_mode) { + case VPE_SW_LINEAR: + case VPE_SW_256B_D: + case VPE_SW_4KB_D: + case VPE_SW_64KB_D: + case VPE_SW_64KB_D_T: + case VPE_SW_4KB_D_X: + case VPE_SW_64KB_D_X: + case VPE_SW_64KB_R_X: + case VPE_SW_VAR_D_X: + case VPE_SW_VAR_R_X: + return true; + default: + return false; + } +} + +bool vpe10_vpec_get_dcc_compression_cap(struct vpec *vpec, + const struct vpe_dcc_surface_param *input, struct vpe_surface_dcc_cap *output) +{ + output->capable = false; + return output->capable; +} diff --git a/src/amd/vpelib/src/core/3dlut_builder.c b/src/amd/vpelib/src/core/3dlut_builder.c new file mode 100644 index 00000000000..81b5a212b5f --- /dev/null +++ b/src/amd/vpelib/src/core/3dlut_builder.c @@ -0,0 +1,117 @@ +/* Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include "3dlut_builder.h" + +static void convert_3dlut_to_tetrahedral_params( + struct vpe_rgb *rgb, bool is_17x17x17, bool is_12_bits, struct tetrahedral_params *params) +{ + struct vpe_rgb *lut0; + struct vpe_rgb *lut1; + struct vpe_rgb *lut2; + struct vpe_rgb *lut3; + int i, lut_i; + + int num_values; + + if (is_17x17x17 == false) { + lut0 = params->tetrahedral_9.lut0; + lut1 = params->tetrahedral_9.lut1; + lut2 = params->tetrahedral_9.lut2; + lut3 = params->tetrahedral_9.lut3; + num_values = LUT3D_SIZE_9x9x9; + } else { + lut0 = params->tetrahedral_17.lut0; + lut1 = params->tetrahedral_17.lut1; + lut2 = params->tetrahedral_17.lut2; + lut3 = params->tetrahedral_17.lut3; + num_values = LUT3D_SIZE_17x17x17; + } + + for (lut_i = 0, i = 0; i < num_values - 4; lut_i++, i += 4) { + lut0[lut_i].red = rgb[i].red; + lut0[lut_i].green = rgb[i].green; + lut0[lut_i].blue = rgb[i].blue; + + lut1[lut_i].red = rgb[i + 1].red; + lut1[lut_i].green = rgb[i + 1].green; + lut1[lut_i].blue = rgb[i + 1].blue; + + lut2[lut_i].red = rgb[i + 2].red; + lut2[lut_i].green = rgb[i + 2].green; + lut2[lut_i].blue = rgb[i + 2].blue; + + lut3[lut_i].red = rgb[i + 3].red; + lut3[lut_i].green = rgb[i + 3].green; + lut3[lut_i].blue = rgb[i + 3].blue; + } + lut0[lut_i].red = rgb[i].red; + lut0[lut_i].green = rgb[i].green; + lut0[lut_i].blue = rgb[i].blue; + + params->use_12bits = is_12_bits; + params->use_tetrahedral_9 = !is_17x17x17; +} + +bool convert_to_tetrahedral(struct vpe_priv *vpe_priv, uint16_t rgb_lib[17 * 17 * 17 * 3], + struct vpe_3dlut *params, bool enable_3dlut) +{ + + if (!enable_3dlut) { + params->state.bits.initialized = 0; + return true; + } + + bool ret = false; + struct vpe_rgb *rgb_area = NULL; + int ind = 0; + int ind_lut = 0; + int nir, nig, nib; + + rgb_area = (struct vpe_rgb *)vpe_zalloc(sizeof(struct vpe_rgb) * 17 * 17 * 17); + if (rgb_area == NULL) + goto release; + + memset(rgb_area, 0, 17 * 17 * 17 * sizeof(struct vpe_rgb)); + + for (nib = 0; nib < 17; nib++) { + for (nig = 0; nig < 17; nig++) { + for (nir = 0; nir < 17; nir++) { + ind_lut = 3 * (nib + 17 * nig + 289 * nir); + + rgb_area[ind].red = rgb_lib[ind_lut + 0]; + rgb_area[ind].green = rgb_lib[ind_lut + 1]; + rgb_area[ind].blue = rgb_lib[ind_lut + 2]; + ind++; + } + } + } + convert_3dlut_to_tetrahedral_params(rgb_area, true, true, ¶ms->lut_3d); + params->state.bits.initialized = 1; + + vpe_free(rgb_area); + ret = true; +release: + return ret; +} diff --git a/src/amd/vpelib/src/core/background.c b/src/amd/vpelib/src/core/background.c new file mode 100644 index 00000000000..a9dc1610a79 --- /dev/null +++ b/src/amd/vpelib/src/core/background.c @@ -0,0 +1,214 @@ +/* Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include "background.h" +#include "common.h" +#include "vpe_priv.h" +#include "color_bg.h" + +void vpe_create_bg_segments( + struct vpe_priv *vpe_priv, struct vpe_rect *gaps, uint16_t gaps_cnt, enum vpe_cmd_ops ops) +{ + uint16_t gap_index; + struct scaler_data *scaler_data; + struct stream_ctx *stream_ctx = &(vpe_priv->stream_ctx[0]); + int32_t vp_x = stream_ctx->stream.scaling_info.src_rect.x; + int32_t vp_y = stream_ctx->stream.scaling_info.src_rect.y; + uint16_t src_div = vpe_is_yuv420(stream_ctx->stream.surface_info.format) ? 2 : 1; + uint16_t dst_div = vpe_is_yuv420(vpe_priv->output_ctx.surface.format) ? 2 : 1; + + for (gap_index = 0; gap_index < gaps_cnt; gap_index++) { + + scaler_data = &(vpe_priv->vpe_cmd_info[vpe_priv->num_vpe_cmds].inputs[0].scaler_data); + + /* format */ + scaler_data->format = stream_ctx->stream.surface_info.format; + scaler_data->lb_params.alpha_en = stream_ctx->per_pixel_alpha; + + /* recout */ + + scaler_data->recout.x = 0; + scaler_data->recout.y = 0; + scaler_data->recout.height = VPE_MIN_VIEWPORT_SIZE; + scaler_data->recout.width = VPE_MIN_VIEWPORT_SIZE; + + /* ratios */ + scaler_data->ratios.horz = vpe_fixpt_one; + scaler_data->ratios.vert = vpe_fixpt_one; + + if (vpe_is_yuv420(scaler_data->format)) { + scaler_data->ratios.horz_c = vpe_fixpt_from_fraction(1, 2); + scaler_data->ratios.vert_c = vpe_fixpt_from_fraction(1, 2); + } else { + scaler_data->ratios.horz_c = vpe_fixpt_one; + scaler_data->ratios.vert_c = vpe_fixpt_one; + } + + /* Active region */ + scaler_data->h_active = gaps[gap_index].width; + scaler_data->v_active = gaps[gap_index].height; + + /* viewport */ + + scaler_data->viewport.x = vp_x; + scaler_data->viewport.y = vp_y; + scaler_data->viewport.width = VPE_MIN_VIEWPORT_SIZE; + scaler_data->viewport.height = VPE_MIN_VIEWPORT_SIZE; + + scaler_data->viewport_c.x = scaler_data->viewport.x / src_div; + scaler_data->viewport_c.y = scaler_data->viewport.y / src_div; + scaler_data->viewport_c.width = scaler_data->viewport.width / src_div; + scaler_data->viewport_c.height = scaler_data->viewport.height / src_div; + + /* destination viewport */ + scaler_data->dst_viewport = gaps[gap_index]; + + scaler_data->dst_viewport_c.x = scaler_data->dst_viewport.x / dst_div; + scaler_data->dst_viewport_c.y = scaler_data->dst_viewport.y / dst_div; + scaler_data->dst_viewport_c.width = scaler_data->dst_viewport.width / dst_div; + scaler_data->dst_viewport_c.height = scaler_data->dst_viewport.height / dst_div; + + /* taps and inits */ + scaler_data->taps.h_taps = scaler_data->taps.v_taps = 4; + scaler_data->taps.h_taps_c = scaler_data->taps.v_taps_c = 2; + + scaler_data->inits.h = vpe_fixpt_div_int( + vpe_fixpt_add_int(scaler_data->ratios.horz, (int)(scaler_data->taps.h_taps + 1)), 2); + scaler_data->inits.v = vpe_fixpt_div_int( + vpe_fixpt_add_int(scaler_data->ratios.vert, (int)(scaler_data->taps.v_taps + 1)), 2); + scaler_data->inits.h_c = vpe_fixpt_div_int( + vpe_fixpt_add_int(scaler_data->ratios.horz_c, (int)(scaler_data->taps.h_taps_c + 1)), + 2); + scaler_data->inits.v_c = vpe_fixpt_div_int( + vpe_fixpt_add_int(scaler_data->ratios.vert_c, (int)(scaler_data->taps.v_taps_c + 1)), + 2); + + VPE_ASSERT(gaps_cnt - gap_index - 1 <= (uint16_t)0xF); + + // background takes stream_idx 0 as its input + vpe_priv->vpe_cmd_info[vpe_priv->num_vpe_cmds].inputs[0].stream_idx = 0; + vpe_priv->vpe_cmd_info[vpe_priv->num_vpe_cmds].dst_viewport = scaler_data->dst_viewport; + vpe_priv->vpe_cmd_info[vpe_priv->num_vpe_cmds].dst_viewport_c = scaler_data->dst_viewport_c; + vpe_priv->vpe_cmd_info[vpe_priv->num_vpe_cmds].num_inputs = 1; + vpe_priv->vpe_cmd_info[vpe_priv->num_vpe_cmds].ops = ops; + vpe_priv->vpe_cmd_info[vpe_priv->num_vpe_cmds].cd = (uint8_t)(gaps_cnt - gap_index - 1); + vpe_priv->vpe_cmd_info[vpe_priv->num_vpe_cmds].tm_enabled = + false; // currently only support frontend tm + + if (vpe_priv->vpe_cmd_info[vpe_priv->num_vpe_cmds].cd == (gaps_cnt - 1)) { + vpe_priv->vpe_cmd_info[vpe_priv->num_vpe_cmds].is_begin = true; + } + + if (vpe_priv->vpe_cmd_info[vpe_priv->num_vpe_cmds].cd == 0) { + vpe_priv->vpe_cmd_info[vpe_priv->num_vpe_cmds].is_end = true; + } + + vpe_priv->num_vpe_cmds++; + } +} + +void vpe_full_bg_gaps(struct vpe_rect *gaps, const struct vpe_rect *target_rect, uint16_t max_gaps) +{ + uint16_t gap_index; + int32_t last_covered; + uint32_t gap_width, gap_remainder; + + last_covered = target_rect->x; + gap_width = target_rect->width / max_gaps; + gap_remainder = target_rect->width % max_gaps; + + for (gap_index = 0; gap_index < max_gaps; gap_index++) { + gaps[gap_index].x = last_covered; + gaps[gap_index].y = target_rect->y; + gaps[gap_index].width = gap_width; + if (gap_index >= max_gaps - gap_remainder) { + gaps[gap_index].width += 1; + } + gaps[gap_index].height = target_rect->height; + last_covered = last_covered + (int32_t)gaps[gap_index].width; + } +} + +/* calculates the gaps in target_rect which are not covered by the first stream + and returns the number of gaps */ +uint16_t vpe_find_bg_gaps(struct vpe_priv *vpe_priv, const struct vpe_rect *target_rect, + struct vpe_rect *gaps, uint16_t max_gaps) +{ + uint16_t num_gaps = 0; + uint16_t num_segs; + struct vpe_rect *dst_viewport_rect; + bool full_bg = false; + const uint32_t max_seg_width = vpe_priv->pub.caps->plane_caps.max_viewport_width; + const uint16_t num_multiple = 1; + + num_segs = vpe_priv->stream_ctx[0].num_segments; + dst_viewport_rect = &(vpe_priv->stream_ctx[0].segment_ctx[0].scaler_data.dst_viewport); + + if (target_rect->x < dst_viewport_rect->x) { + + if (target_rect->width <= max_seg_width) { + goto full_bg; + } + gaps[0].x = target_rect->x; + gaps[0].y = target_rect->y; + gaps[0].width = (uint32_t)(dst_viewport_rect->x - target_rect->x); + gaps[0].height = target_rect->height; + num_gaps++; + if (gaps[0].width > max_seg_width) { + if (!vpe_priv->resource.split_bg_gap( + gaps, target_rect, max_seg_width, max_gaps, &num_gaps, num_multiple)) { + goto full_bg; + } + } + } + dst_viewport_rect = + &(vpe_priv->stream_ctx[0].segment_ctx[num_segs - 1].scaler_data.dst_viewport); + + if (target_rect->x + (int32_t)target_rect->width > + dst_viewport_rect->x + (int32_t)dst_viewport_rect->width) { + + if (num_gaps == max_gaps) { + goto full_bg; + } + + gaps[num_gaps].x = dst_viewport_rect->x + (int32_t)dst_viewport_rect->width; + gaps[num_gaps].y = target_rect->y; + gaps[num_gaps].width = + (uint32_t)(target_rect->x + (int32_t)target_rect->width - + (dst_viewport_rect->x + (int32_t)dst_viewport_rect->width)); + gaps[num_gaps].height = target_rect->height; + num_gaps++; + if (gaps[num_gaps - 1].width > max_seg_width) { + if (!vpe_priv->resource.split_bg_gap( + gaps, target_rect, max_seg_width, max_gaps, &num_gaps, num_multiple)) { + goto full_bg; + } + } + } + return num_gaps; + +full_bg: + vpe_full_bg_gaps(gaps, target_rect, max_gaps); + return max_gaps; +} diff --git a/src/amd/vpelib/src/core/color.c b/src/amd/vpelib/src/core/color.c new file mode 100644 index 00000000000..d620c1cba09 --- /dev/null +++ b/src/amd/vpelib/src/core/color.c @@ -0,0 +1,887 @@ +/* Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include "vpe_assert.h" +#include +#include "color.h" +#include "color_gamma.h" +#include "color_cs.h" +#include "vpe_priv.h" +#include "color_gamut.h" +#include "common.h" +#include "custom_float.h" +#include "color_test_values.h" +#include "color_pwl.h" +#include "3dlut_builder.h" +#include "shaper_builder.h" + +static void color_check_input_cm_update(struct vpe_priv *vpe_priv, struct stream_ctx *stream_ctx, + const struct vpe_color_space *vcs, const struct vpe_color_adjust *adjustments, + bool enable_3dlut); + +static void color_check_output_cm_update( + struct vpe_priv *vpe_priv, const struct vpe_color_space *vcs); + +static bool color_check_bypass_cm(struct vpe_priv *vpe_priv, const struct vpe_build_param *param); + +static bool color_update_output_tf(struct vpe_priv *vpe_priv, + enum color_transfer_func output_transfer_function, struct transfer_func *output_tf, + bool can_bypass); + +static bool color_update_input_tf(struct vpe_priv *vpe_priv, + enum color_transfer_func input_transfer_function, struct transfer_func *input_tf, + bool can_bypass, bool force_tf_calculation); + +static bool color_update_input_cs(struct vpe_priv *vpe_priv, enum color_space in_cs, + const struct vpe_color_adjust *adjustments, struct vpe_csc_matrix *input_cs, + struct vpe_color_adjust *stream_clr_adjustments, struct fixed31_32 *matrix_scaling_factor); + +static bool is_ycbcr(enum color_space in_cs); + +static bool is_ycbcr(enum color_space in_cs) +{ + if ((in_cs == COLOR_SPACE_YCBCR601) || (in_cs == COLOR_SPACE_YCBCR601_LIMITED) || + (in_cs == COLOR_SPACE_YCBCR709) || (in_cs == COLOR_SPACE_YCBCR709_LIMITED) || + (in_cs == COLOR_SPACE_2020_YCBCR) || (in_cs == COLOR_SPACE_2020_YCBCR_LIMITED)) { + return true; + } + return false; +} + +static void color_check_output_cm_update( + struct vpe_priv *vpe_priv, const struct vpe_color_space *vcs) +{ + enum color_space cs; + enum color_transfer_func tf; + + vpe_color_get_color_space_and_tf(vcs, &cs, &tf); + + if (cs == COLOR_SPACE_UNKNOWN || tf == TRANSFER_FUNC_UNKNOWN) + VPE_ASSERT(0); + + if (cs != vpe_priv->output_ctx.cs) { + vpe_priv->output_ctx.dirty_bits.color_space = 1; + vpe_priv->output_ctx.cs = cs; + } else { + vpe_priv->output_ctx.dirty_bits.color_space = 0; + } + + if (tf != vpe_priv->output_ctx.tf) { + vpe_priv->output_ctx.dirty_bits.transfer_function = 1; + vpe_priv->output_ctx.tf = tf; + } else { + vpe_priv->output_ctx.dirty_bits.transfer_function = 0; + } +} + +static void color_check_input_cm_update(struct vpe_priv *vpe_priv, struct stream_ctx *stream_ctx, + const struct vpe_color_space *vcs, const struct vpe_color_adjust *adjustments, + bool enable_3dlut) +{ + enum color_space cs; + enum color_transfer_func tf; + + vpe_color_get_color_space_and_tf(vcs, &cs, &tf); + /* + * Bias and Scale already does full->limited range conversion. + * Hence, the ICSC matrix should always be full range + */ + vpe_convert_full_range_color_enum(&cs); + + if (cs == COLOR_SPACE_UNKNOWN && tf == TRANSFER_FUNC_UNKNOWN) + VPE_ASSERT(0); + + if (cs != stream_ctx->cs || enable_3dlut != stream_ctx->enable_3dlut) { + stream_ctx->dirty_bits.color_space = 1; + stream_ctx->cs = cs; + } else { + stream_ctx->dirty_bits.color_space = 0; + if (adjustments) { + if (vpe_color_different_color_adjusts( + adjustments, &stream_ctx->color_adjustments)) // the new stream has different + // color adjustments params + stream_ctx->dirty_bits.color_space = 1; + } + } + // if the new transfer function is different than the old one or the scaling factor is not one + // any new stream will start with a transfer function which is not scaled + if (tf != stream_ctx->tf || enable_3dlut != stream_ctx->enable_3dlut) { + stream_ctx->dirty_bits.transfer_function = 1; + stream_ctx->tf = tf; + } else { + stream_ctx->dirty_bits.transfer_function = 0; + } + + stream_ctx->enable_3dlut = enable_3dlut; +} + +static bool color_update_output_tf(struct vpe_priv *vpe_priv, + enum color_transfer_func output_transfer_function, struct transfer_func *output_tf, + bool can_bypass) +{ + struct pwl_params *params = NULL; + output_tf->sdr_ref_white_level = 80; + + if (can_bypass) { + output_tf->type = TF_TYPE_BYPASS; + return true; + } + + output_tf->type = TF_TYPE_DISTRIBUTED_POINTS; + + switch (output_transfer_function) { + case TRANSFER_FUNC_SRGB: + case TRANSFER_FUNC_BT709: + case TRANSFER_FUNC_BT1886: + case TRANSFER_FUNC_PQ2084: + case TRANSFER_FUNC_LINEAR_0_125: + output_tf->tf = output_transfer_function; + break; + default: + VPE_ASSERT(0); + break; + } + + if (!vpe_priv->init.debug.force_tf_calculation) + vpe_priv->resource.get_tf_pwl_params(output_tf, ¶ms, CM_REGAM); + + if (params) + output_tf->use_pre_calculated_table = true; + else + output_tf->use_pre_calculated_table = false; + + if (!output_tf->use_pre_calculated_table) + vpe_color_calculate_regamma_params(vpe_priv, output_tf, &vpe_priv->cal_buffer); + + return true; +} + +static bool color_update_input_tf(struct vpe_priv *vpe_priv, + const enum color_transfer_func color_input_tf, struct transfer_func *input_tf, bool can_bypass, + bool force_tf_calculation) +{ + bool ret = true; + struct pwl_params *params = NULL; + + if (can_bypass) { + input_tf->type = TF_TYPE_BYPASS; + return true; + } + + input_tf->type = TF_TYPE_DISTRIBUTED_POINTS; + + switch (color_input_tf) { + case TRANSFER_FUNC_SRGB: + case TRANSFER_FUNC_BT709: + case TRANSFER_FUNC_BT1886: + case TRANSFER_FUNC_PQ2084: + case TRANSFER_FUNC_LINEAR_0_125: + case TRANSFER_FUNC_NORMALIZED_PQ: + input_tf->tf = color_input_tf; + break; + default: + VPE_ASSERT(0); + break; + } + + if (!vpe_priv->init.debug.force_tf_calculation) + vpe_priv->resource.get_tf_pwl_params(input_tf, ¶ms, CM_DEGAM); + + if (params) + input_tf->use_pre_calculated_table = true; + else + input_tf->use_pre_calculated_table = false; + + if ((!input_tf->use_pre_calculated_table) || (force_tf_calculation)) { + input_tf->use_pre_calculated_table = false; + vpe_color_calculate_degamma_params(vpe_priv, vpe_priv->stream_ctx->tf_scaling_factor, + vpe_fixpt_from_int(1), + input_tf); + } + + return ret; +} + +// return true if bypass can be done +static bool color_check_bypass_cm(struct vpe_priv *vpe_priv, const struct vpe_build_param *param) +{ + uint32_t i; + struct stream_ctx *stream_ctx; + + // TODO: revisit the TM case + for (i = 0; i < param->num_streams; i++) { + stream_ctx = &vpe_priv->stream_ctx[i]; + if (stream_ctx->cs != vpe_priv->output_ctx.cs || + stream_ctx->tf != vpe_priv->output_ctx.tf) { + return false; + } + } + return true; +} + +static enum color_space color_get_icsc_cs(enum color_space ics) +{ + switch (ics) { + case COLOR_SPACE_SRGB: + case COLOR_SPACE_SRGB_LIMITED: + case COLOR_SPACE_MSREF_SCRGB: + case COLOR_SPACE_2020_RGB_FULLRANGE: + case COLOR_SPACE_2020_RGB_LIMITEDRANGE: + return COLOR_SPACE_SRGB; + case COLOR_SPACE_JFIF: + case COLOR_SPACE_YCBCR601: + case COLOR_SPACE_YCBCR601_LIMITED: + return COLOR_SPACE_YCBCR601; + case COLOR_SPACE_YCBCR709: + case COLOR_SPACE_YCBCR709_LIMITED: + return COLOR_SPACE_YCBCR709; + case COLOR_SPACE_2020_YCBCR: + case COLOR_SPACE_2020_YCBCR_LIMITED: + return COLOR_SPACE_2020_YCBCR; + default: + return COLOR_SPACE_UNKNOWN; + } +} + +// return true is bypass can be done +static bool color_update_input_cs(struct vpe_priv *vpe_priv, enum color_space in_cs, + const struct vpe_color_adjust *adjustments, struct vpe_csc_matrix *input_cs, + struct vpe_color_adjust *stream_clr_adjustments, struct fixed31_32 *matrix_scaling_factor) +{ + int i, j; + bool use_adjustments = false; + int arr_size = sizeof(vpe_input_csc_matrix_fixed) / sizeof(struct vpe_csc_matrix); + + input_cs->cs = COLOR_SPACE_UNKNOWN; + use_adjustments = vpe_use_csc_adjust(adjustments); + in_cs = color_get_icsc_cs(in_cs); + + for (i = 0; i < arr_size; i++) + if (vpe_input_csc_matrix_fixed[i].cs == in_cs) { + input_cs->cs = vpe_input_csc_matrix_fixed[i].cs; + for (j = 0; j < 12; j++) + input_cs->regval[j] = vpe_input_csc_matrix_fixed[i].regval[j]; + break; + } + + if (i == arr_size) { + vpe_log("err: unknown cs not handled!"); + return false; + } + + if (use_adjustments && is_ycbcr(in_cs)) { // shader supports only yuv input for color + // adjustments + vpe_log("Apply color adjustments (contrast, saturation, hue, brightness)"); + if (!vpe_color_calculate_input_cs( + vpe_priv, in_cs, adjustments, input_cs, matrix_scaling_factor)) + return false; + *stream_clr_adjustments = *adjustments; + } + + return true; +} + +bool vpe_use_csc_adjust(const struct vpe_color_adjust *adjustments) +{ + float epsilon = 0.001f; // steps are 1.0f or 0.01f, so should be plenty + + // see vpe_types.h and vpe_color_adjust definition for VpBlt ranges + + // default brightness = 0 + if (adjustments->brightness > epsilon || adjustments->brightness < -epsilon) + return true; + + // default contrast = 1 + if (adjustments->contrast > 1 + epsilon || adjustments->contrast < 1 - epsilon) + return true; + + // default saturation = 1 + if (adjustments->saturation > 1 + epsilon || adjustments->saturation < 1 - epsilon) + return true; + + // default hue = 0 + if (adjustments->hue > epsilon || adjustments->hue < -epsilon) + return true; + + return false; +} + +/* Bias and Scale reference table + Encoding Bpp Format Data Range Expansion Bias Scale + aRGB 32bpp 8888 Full Zero 0 256/255 + 8888 Limited Zero -16/256 256/(235-16) + 2101010 Full Zero 0 1024/1023 + 2101010 Limited Zero -64/1024 1024/(940-64) + 2101010 XR bias Zero -384/1024 1024/510 // not used + 64bpp fixed 10bpc Full Zero 0 1024/1023 // do we have these? + 10 bpc limited zero -64/1024 1024/(940-64) + 12 bpc Full Zero 0 4096/4095 + 12 bpc Limited Zero -256/4096 4096/(3760-256) + aCrYCb 32bpp 8888 Full Zero 0 256/255 + 8888 Limited Zero Y:-16/256 Y:256/(235-16) + C:-128/256 C:256/(240-16) // See notes + below 2101010 Full Zero 0 1024/1023 2101010 Limited Zero + Y:-64/1024 Y:1024/(940-64) C:-512/1024 C:1024(960-64) 64bpp fixed 10bpc Full Zero 0 + 1024/1023 10 bpc Limited Zero Y:-64/1024 Y:1024/(940-64) C:-512/1024 + C:1024(960-64) // See notes below 12 bpc Full Zero 0 4096/4095 12 + bpc Limited Zero Y:-256/4096 Y:4096/(3760-256) C:-2048/4096 C:4096/(3840-256) // + See notes below + + The bias_c we use here in the function are diff with the above table from hw team + because the table is to run with CSC matrix which expect chroma + from -0.5~+0.5. + However the csc matrix we use in ICSC is expecting chroma value + from 0.0~1.0. + Hence we need a bias for chroma to output a range from 0.0~1.0 instead. + So we use the same value as luma (Y) which expects range from 0~1.0 already. + */ +static bool build_scale_and_bias(struct bias_and_scale *bias_and_scale, + const struct vpe_color_space *vcs, enum vpe_surface_pixel_format format) +{ + struct fixed31_32 scale = vpe_fixpt_one; // RGB or Y + struct fixed31_32 scale_c = vpe_fixpt_one; // Cb/Cr + struct fixed31_32 bias = vpe_fixpt_zero; // RGB or Y + struct fixed31_32 bias_c = vpe_fixpt_from_fraction(-1, 2); // Cb/Cr + bool is_chroma_different = false; + + struct custom_float_format fmt; + fmt.exponenta_bits = 6; + fmt.mantissa_bits = 12; + fmt.sign = true; + + if (vpe_is_rgb8(format)) { + if (vcs->range == VPE_COLOR_RANGE_FULL) { + scale = vpe_fixpt_from_fraction(256, 255); + } else if (vcs->range == VPE_COLOR_RANGE_STUDIO) { + scale = vpe_fixpt_from_fraction(256, 235 - 16); + bias = vpe_fixpt_from_fraction(-16, 256); + } // else report error? here just go with default (1.0, 0.0) + } else if (vpe_is_rgb10(format)) { + if (vcs->range == VPE_COLOR_RANGE_FULL) { + scale = vpe_fixpt_from_fraction(1024, 1023); + } else if (vcs->range == VPE_COLOR_RANGE_STUDIO) { + scale = vpe_fixpt_from_fraction(1024, 940 - 64); + bias = vpe_fixpt_from_fraction(-64, 1024); + } // else report error? here just go with default (1.0, 0.0) + } else if (vpe_is_yuv420_8(format) || vpe_is_yuv444_8(format)) { + if (vcs->range == VPE_COLOR_RANGE_FULL) { + scale = vpe_fixpt_from_fraction(256, 255); + } else if (vcs->range == VPE_COLOR_RANGE_STUDIO) { + scale = vpe_fixpt_from_fraction(256, 235 - 16); + bias = vpe_fixpt_from_fraction(-16, 256); + scale_c = vpe_fixpt_from_fraction(256, 240 - 16); + bias_c = vpe_fixpt_from_fraction(-16, 256); // See notes in function comment + is_chroma_different = true; + } // else report error? not sure if default is right + } else if (vpe_is_yuv420_10(format) || vpe_is_yuv444_10(format)) { + if (vcs->range == VPE_COLOR_RANGE_FULL) { + scale = vpe_fixpt_from_fraction(1024, 1023); + } else if (vcs->range == VPE_COLOR_RANGE_STUDIO) { + scale = vpe_fixpt_from_fraction(1024, 940 - 64); + bias = vpe_fixpt_from_fraction(-64, 1024); + scale_c = vpe_fixpt_from_fraction(1024, 960 - 64); + bias_c = vpe_fixpt_from_fraction(-64, 1024); // See notes in function comment + is_chroma_different = true; + } // else report error? not sure if default is right + } + + vpe_convert_to_custom_float_format(scale, &fmt, &bias_and_scale->scale_green); + vpe_convert_to_custom_float_format(bias, &fmt, &bias_and_scale->bias_green); + + // see definition of scale/bias and scale_c/bias_c + // RGB formats only have scale/bias since all color channels are the same + // YCbCr have scale/bias for Y (in HW maps to G) and scale_c/bias_c for CrCb (mapping to R,B) + if (!is_chroma_different) { + bias_and_scale->scale_red = bias_and_scale->scale_green; + bias_and_scale->scale_blue = bias_and_scale->scale_green; + bias_and_scale->bias_red = bias_and_scale->bias_green; + bias_and_scale->bias_blue = bias_and_scale->bias_green; + } else { + vpe_convert_to_custom_float_format(scale_c, &fmt, &bias_and_scale->scale_red); + vpe_convert_to_custom_float_format(bias_c, &fmt, &bias_and_scale->bias_red); + bias_and_scale->scale_blue = bias_and_scale->scale_red; + bias_and_scale->bias_blue = bias_and_scale->bias_red; + } + + return true; +} + +enum vpe_status vpe_color_build_tm_cs(const struct vpe_tonemap_params *tm_params, + struct vpe_surface_info surface_info, struct vpe_color_space *tm_out_cs) +{ + tm_out_cs->tf = tm_params->lut_out_tf; + tm_out_cs->primaries = tm_params->lut_out_gamut; + tm_out_cs->encoding = surface_info.cs.encoding; + tm_out_cs->range = VPE_COLOR_RANGE_FULL; // surface_info.cs.range; + tm_out_cs->cositing = VPE_CHROMA_COSITING_NONE; // surface_info.cs.cositing; + + return VPE_STATUS_OK; +} + +enum vpe_status vpe_color_update_color_space_and_tf( + struct vpe_priv *vpe_priv, const struct vpe_build_param *param) +{ + uint32_t stream_idx; + struct stream_ctx *stream_ctx; + struct output_ctx *output_ctx; + enum vpe_status status = VPE_STATUS_OK; + + color_check_output_cm_update(vpe_priv, ¶m->dst_surface.cs); + + for (stream_idx = 0; stream_idx < param->num_streams; stream_idx++) { + stream_ctx = &vpe_priv->stream_ctx[stream_idx]; + + color_check_input_cm_update(vpe_priv, stream_ctx, + ¶m->streams[stream_idx].surface_info.cs, ¶m->streams[stream_idx].color_adj, + param->streams[stream_idx].tm_params.enable_3dlut); + } + + output_ctx = &vpe_priv->output_ctx; + if (output_ctx->dirty_bits.transfer_function) { + if (!output_ctx->output_tf) { + output_ctx->output_tf = + (struct transfer_func *)vpe_zalloc(sizeof(struct transfer_func)); + if (!output_ctx->output_tf) { + vpe_log("err: out of memory for output tf!"); + return VPE_STATUS_NO_MEMORY; + } + } + + color_update_output_tf(vpe_priv, output_ctx->tf, output_ctx->output_tf, + false); // No bypass, always do regam/degam + } + + for (stream_idx = 0; stream_idx < param->num_streams; stream_idx++) { + stream_ctx = &vpe_priv->stream_ctx[stream_idx]; + struct fixed31_32 new_matrix_scaling_factor = vpe_fixpt_one; + + if (stream_ctx->dirty_bits.color_space) { + if (!stream_ctx->input_cs) { + stream_ctx->input_cs = + (struct vpe_csc_matrix *)vpe_zalloc(sizeof(struct vpe_csc_matrix)); + if (!stream_ctx->input_cs) { + vpe_log("err: out of memory for input cs!"); + return VPE_STATUS_NO_MEMORY; + } + } + + if (!color_update_input_cs(vpe_priv, stream_ctx->cs, + ¶m->streams[stream_idx].color_adj, stream_ctx->input_cs, + &stream_ctx->color_adjustments, &new_matrix_scaling_factor)) { + vpe_log("err: input cs not being programmed!"); + } else { + if ((vpe_priv->scale_yuv_matrix) && // the option to scale the matrix yuv to rgb is + // on + (new_matrix_scaling_factor.value != + vpe_priv->stream_ctx->tf_scaling_factor.value)) { + vpe_priv->stream_ctx->tf_scaling_factor = new_matrix_scaling_factor; + stream_ctx->dirty_bits.transfer_function = 1; // force tf recalculation + } + } + } + + if (stream_ctx->dirty_bits.transfer_function) { + if (!stream_ctx->input_tf) { + stream_ctx->input_tf = + (struct transfer_func *)vpe_zalloc(sizeof(struct transfer_func)); + if (!stream_ctx->input_tf) { + vpe_log("err: out of memory for input tf!"); + return VPE_STATUS_NO_MEMORY; + } + } + + color_update_input_tf(vpe_priv, stream_ctx->tf, stream_ctx->input_tf, + stream_ctx->stream.tm_params.enable_3dlut, // By Pass regamma if 3DLUT is enabled + false); + } + + if (!stream_ctx->bias_scale) { + stream_ctx->bias_scale = + (struct bias_and_scale *)vpe_zalloc(sizeof(struct bias_and_scale)); + if (!stream_ctx->bias_scale) { + vpe_log("err: out of memory for bias and scale!"); + return VPE_STATUS_NO_MEMORY; + } + + build_scale_and_bias(stream_ctx->bias_scale, + ¶m->streams[stream_idx].surface_info.cs, + param->streams[stream_idx].surface_info.format); + } + + if (stream_ctx->dirty_bits.color_space || output_ctx->dirty_bits.color_space) { + if (!stream_ctx->gamut_remap) { + stream_ctx->gamut_remap = vpe_zalloc(sizeof(struct colorspace_transform)); + if (!stream_ctx->gamut_remap) { + vpe_log("err: out of memory for gamut_remap!"); + return VPE_STATUS_NO_MEMORY; + } + } + status = vpe_color_update_gamut(vpe_priv, stream_ctx->cs, output_ctx->cs, + stream_ctx->gamut_remap, stream_ctx->stream.tm_params.enable_3dlut); + } + } + + if (status != VPE_STATUS_OK) { + vpe_log("failed in updating gamut %d\n", (int)status); + return status; + } + + return VPE_STATUS_OK; +} + +enum vpe_status vpe_color_tm_update_hdr_mult(uint16_t shaper_in_exp_max, uint32_t peak_white, + struct fixed31_32 *hdr_multiplier, bool enable3dlut) +{ + if (enable3dlut) { + struct fixed31_32 shaper_in_gain; + struct fixed31_32 pq_norm_gain; + + // HDRMULT = 2^shaper_in_exp_max*(1/PQ(x)) + shaper_in_gain = vpe_fixpt_from_int((long long)1 << shaper_in_exp_max); + vpe_compute_pq(vpe_fixpt_from_fraction((long long)peak_white, 10000), &pq_norm_gain); + + *hdr_multiplier = vpe_fixpt_div(shaper_in_gain, pq_norm_gain); + } else { + *hdr_multiplier = vpe_fixpt_one; + } + + return VPE_STATUS_OK; +} + +enum vpe_status vpe_color_update_shaper( + uint16_t shaper_in_exp_max, struct transfer_func *shaper_func, bool enable_3dlut) + +{ + if (!enable_3dlut) { + shaper_func->type = TF_TYPE_BYPASS; + return VPE_STATUS_OK; + } + struct vpe_shaper_setup_in shaper_in; + + shaper_in.shaper_in_max = 1 << 16; + shaper_in.use_const_hdr_mult = false; // can't be true. Fix is required. + + shaper_func->type = TF_TYPE_HWPWL; + shaper_func->tf = TRANSFER_FUNC_LINEAR_0_125; + return vpe_build_shaper(&shaper_in, &shaper_func->pwl); +} + +enum vpe_status vpe_color_update_blnd_gam(struct vpe_priv *vpe_priv, + const struct vpe_build_param *param, const struct vpe_tonemap_params *tm_params, + struct transfer_func *blnd_tf_func, bool enable_3dlut) +{ + + if (!enable_3dlut) { + blnd_tf_func->type = TF_TYPE_BYPASS; + return VPE_STATUS_OK; + } + + enum vpe_status ret = VPE_STATUS_OK; + struct vpe_color_space tm_out_cs; + enum color_space cs; + enum color_transfer_func tf; + struct fixed31_32 tf_norm_gain; + + vpe_color_build_tm_cs(tm_params, param->dst_surface, &tm_out_cs); + vpe_color_get_color_space_and_tf(&tm_out_cs, &cs, &tf); + + if (tf == TRANSFER_FUNC_NORMALIZED_PQ) { + uint32_t outLuminance = vpe_priv->output_ctx.hdr_metadata.max_mastering; + vpe_compute_pq(vpe_fixpt_from_fraction((long long)outLuminance, 10000), &tf_norm_gain); + } else { + tf_norm_gain = vpe_fixpt_from_int(1); + } + + blnd_tf_func->type = TF_TYPE_DISTRIBUTED_POINTS; + blnd_tf_func->tf = tf; + blnd_tf_func->use_pre_calculated_table = false; + + vpe_color_calculate_degamma_params(vpe_priv, tf_norm_gain, vpe_fixpt_from_int(1), blnd_tf_func); + return VPE_STATUS_OK; +} + +enum vpe_status vpe_color_update_movable_cm( + struct vpe_priv *vpe_priv, const struct vpe_build_param *param) +{ + enum vpe_status ret = VPE_STATUS_OK; + + uint32_t stream_idx; + struct stream_ctx *stream_ctx; + struct output_ctx *output_ctx = &vpe_priv->output_ctx; + + for (stream_idx = 0; stream_idx < param->num_streams; stream_idx++) { + stream_ctx = &vpe_priv->stream_ctx[stream_idx]; + + bool enable_3dlut = stream_ctx->stream.tm_params.enable_3dlut; + bool update_3dlut = stream_ctx->stream.tm_params.update_3dlut; + + if (stream_ctx->update_3dlut) { + + uint32_t pqNormFactor; + struct vpe_color_space tm_out_cs; + enum color_space out_lut_cs; + enum color_transfer_func tf; + + if (!stream_ctx->in_shaper_func) { + stream_ctx->in_shaper_func = vpe_zalloc(sizeof(struct transfer_func)); + if (!stream_ctx->in_shaper_func) { + vpe_log("err: out of memory for shaper tf!"); + ret = VPE_STATUS_NO_MEMORY; + goto exit; + } + } + + if (!stream_ctx->blend_tf) { + stream_ctx->blend_tf = vpe_zalloc(sizeof(struct transfer_func)); + if (!stream_ctx->blend_tf) { + vpe_log("err: out of memory for blend/post1d tf!"); + ret = VPE_STATUS_NO_MEMORY; + goto exit; + } + } + + if (!stream_ctx->lut3d_func) { + stream_ctx->lut3d_func = vpe_zalloc(sizeof(struct vpe_3dlut)); + if (!stream_ctx->lut3d_func) { + vpe_log("err: out of memory for 3d lut!"); + ret = VPE_STATUS_NO_MEMORY; + goto exit; + } + } + + if (!output_ctx->gamut_remap) { + output_ctx->gamut_remap = vpe_zalloc(sizeof(struct colorspace_transform)); + if (!output_ctx->gamut_remap) { + vpe_log("err: out of memory for post blend gamut remap!"); + ret = VPE_STATUS_NO_MEMORY; + goto exit; + } + } + + if (param->streams[stream_idx].tm_params.shaper_tf == VPE_TF_PQ_NORMALIZED) + pqNormFactor = stream_ctx->stream.hdr_metadata.max_mastering; + else + pqNormFactor = HDR_PEAK_WHITE; + + vpe_color_tm_update_hdr_mult(SHAPER_EXP_MAX_IN, pqNormFactor, + &stream_ctx->lut3d_func->hdr_multiplier, enable_3dlut); + + vpe_color_update_shaper(SHAPER_EXP_MAX_IN, stream_ctx->in_shaper_func, enable_3dlut); + + vpe_color_update_blnd_gam( + vpe_priv, param, &stream_ctx->stream.tm_params, stream_ctx->blend_tf, enable_3dlut); + + vpe_color_build_tm_cs(&stream_ctx->stream.tm_params, param->dst_surface, &tm_out_cs); + + vpe_color_get_color_space_and_tf(&tm_out_cs, &out_lut_cs, &tf); + + vpe_color_update_gamut(vpe_priv, out_lut_cs, vpe_priv->output_ctx.cs, + output_ctx->gamut_remap, !enable_3dlut); + + convert_to_tetrahedral(vpe_priv, param->streams[stream_idx].tm_params.lut_data, + stream_ctx->lut3d_func, enable_3dlut); + + stream_ctx->update_3dlut = false; + } + } +exit: + return ret; +} + +void vpe_color_get_color_space_and_tf( + const struct vpe_color_space *vcs, enum color_space *cs, enum color_transfer_func *tf) +{ + enum vpe_color_range colorRange = vcs->range; + + *cs = COLOR_SPACE_UNKNOWN; + *tf = TRANSFER_FUNC_UNKNOWN; + + if (vcs->encoding == VPE_PIXEL_ENCODING_YCbCr) { + switch (vcs->tf) { + case VPE_TF_G22: + *tf = TRANSFER_FUNC_SRGB; + break; + case VPE_TF_G24: + *tf = TRANSFER_FUNC_BT1886; + break; + case VPE_TF_PQ: + *tf = TRANSFER_FUNC_PQ2084; + break; + case VPE_TF_PQ_NORMALIZED: + *tf = TRANSFER_FUNC_NORMALIZED_PQ; + default: + break; + } + + switch (vcs->primaries) { + case VPE_PRIMARIES_BT601: + *cs = colorRange == VPE_COLOR_RANGE_FULL ? COLOR_SPACE_YCBCR601 + : COLOR_SPACE_YCBCR601_LIMITED; + break; + case VPE_PRIMARIES_BT709: + *cs = colorRange == VPE_COLOR_RANGE_FULL ? COLOR_SPACE_YCBCR709 + : COLOR_SPACE_YCBCR709_LIMITED; + break; + case VPE_PRIMARIES_BT2020: + *cs = colorRange == VPE_COLOR_RANGE_FULL ? COLOR_SPACE_2020_YCBCR + : COLOR_SPACE_2020_YCBCR_LIMITED; + break; + case VPE_PRIMARIES_JFIF: + *cs = colorRange == VPE_COLOR_RANGE_FULL ? COLOR_SPACE_JFIF : COLOR_SPACE_UNKNOWN; + break; + default: + break; + } + } else { + switch (vcs->tf) { + case VPE_TF_G22: + *tf = TRANSFER_FUNC_SRGB; + break; + case VPE_TF_G24: + *tf = TRANSFER_FUNC_BT1886; + break; + case VPE_TF_PQ: + *tf = TRANSFER_FUNC_PQ2084; + break; + case VPE_TF_PQ_NORMALIZED: + *tf = TRANSFER_FUNC_NORMALIZED_PQ; + break; + case VPE_TF_G10: + *tf = TRANSFER_FUNC_LINEAR_0_125; + break; + default: + break; + } + + switch (vcs->primaries) { + case VPE_PRIMARIES_BT709: + if (vcs->tf == VPE_TF_G10) { + *cs = COLOR_SPACE_MSREF_SCRGB; + } else { + *cs = colorRange == VPE_COLOR_RANGE_FULL ? COLOR_SPACE_SRGB + : COLOR_SPACE_SRGB_LIMITED; + } + break; + case VPE_PRIMARIES_BT2020: + *cs = colorRange == VPE_COLOR_RANGE_FULL ? COLOR_SPACE_2020_RGB_FULLRANGE + : COLOR_SPACE_2020_RGB_LIMITEDRANGE; + break; + default: + break; + } + } +} + +bool vpe_is_rgb_equal(const struct pwl_result_data *rgb, uint32_t num) +{ + uint32_t i; + bool ret = true; + + for (i = 0; i < num; i++) { + if (rgb[i].red_reg != rgb[i].green_reg || rgb[i].blue_reg != rgb[i].red_reg || + rgb[i].blue_reg != rgb[i].green_reg) { + ret = false; + break; + } + } + return ret; +} + +void vpe_convert_full_range_color_enum(enum color_space *cs) +{ + switch (*cs) { + case COLOR_SPACE_YCBCR601_LIMITED: + *cs = COLOR_SPACE_YCBCR601; + break; + case COLOR_SPACE_YCBCR709_LIMITED: + *cs = COLOR_SPACE_YCBCR709; + break; + case COLOR_SPACE_2020_YCBCR_LIMITED: + *cs = COLOR_SPACE_2020_YCBCR; + break; + case COLOR_SPACE_SRGB_LIMITED: + *cs = COLOR_SPACE_SRGB; + break; + case COLOR_SPACE_2020_RGB_LIMITEDRANGE: + *cs = COLOR_SPACE_2020_RGB_FULLRANGE; + break; + default: + break; + } +} + +bool vpe_is_HDR(enum color_transfer_func tf) +{ + + return (tf == TRANSFER_FUNC_PQ2084 || tf == TRANSFER_FUNC_LINEAR_0_125); +} + +/* + * + * Pixel processing in VPE can be divided int two main paths. Tone maping cases and non tone mapping + * cases. The gain factor supplied by the below function is only applied in the non-tone mapping + * path. + * + * The gain is used to scale the white point in SDR<->HDR conversions. + * + * The policy is as follows: + * HDR -> SDR (None tone mapping case): Map max input pixel value indicated by HDR meta data to + * value of 1. SDR-> HDR : Map nominal value of 1 to display brightness indicated by metadata. + * + * Table outlining handling for full combination can be found in VPE Wolfpack + */ +enum vpe_status vpe_color_update_whitepoint( + const struct vpe_priv *vpe_priv, const struct vpe_build_param *param) +{ + + struct stream_ctx *stream = vpe_priv->stream_ctx; + const struct output_ctx *output_ctx = &vpe_priv->output_ctx; + const struct vpe_color_space *vpe_cs = &stream->stream.surface_info.cs; + bool output_isHDR = vpe_is_HDR(vpe_priv->output_ctx.tf); + bool input_isHDR = false; + bool isYCbCr = false; + bool isG24 = false; + + for (unsigned int stream_index = 0; stream_index < vpe_priv->num_streams; stream_index++) { + + input_isHDR = vpe_is_HDR(stream->tf); + isYCbCr = (vpe_cs->encoding == VPE_PIXEL_ENCODING_YCbCr); + isG24 = (vpe_cs->tf == VPE_TF_G24); + + if (!input_isHDR && output_isHDR) { + int sdrWhiteLevel = (isYCbCr || isG24) ? SDR_VIDEO_WHITE_POINT : SDR_WHITE_POINT; + stream->white_point_gain = vpe_fixpt_from_fraction(sdrWhiteLevel, 10000); + } else if (input_isHDR && !output_isHDR) { + + stream->white_point_gain = stream->stream.hdr_metadata.max_mastering != 0 + ? vpe_fixpt_from_fraction(HDR_PEAK_WHITE, + stream->stream.hdr_metadata.max_mastering) + : vpe_fixpt_one; + } else { + stream->white_point_gain = vpe_fixpt_one; + } + stream++; + } + return VPE_STATUS_OK; +} diff --git a/src/amd/vpelib/src/core/color_bg.c b/src/amd/vpelib/src/core/color_bg.c new file mode 100644 index 00000000000..ce919dd8b5c --- /dev/null +++ b/src/amd/vpelib/src/core/color_bg.c @@ -0,0 +1,363 @@ +#include +#include +#include "color_bg.h" + +struct csc_vector { + float x; + float y; + float z; +}; + +struct csc_table { + struct csc_vector rgb_offset; // RGB offset + struct csc_vector red_coef; // RED coefficient + struct csc_vector green_coef; // GREEN coefficient + struct csc_vector blue_coef; // BLUE coefficient +}; + +static struct csc_table bgcolor_to_rgbfull_table[COLOR_SPACE_MAX] = { + [COLOR_SPACE_YCBCR601] = + { + {0.0f, -0.5f, -0.5f}, + {1.0f, 0.0f, 1.402f}, + {1.0f, -0.344136286f, -0.714136286f}, + {1.0f, 1.772f, 0.0f}, + }, + [COLOR_SPACE_YCBCR709] = + { + {0.0f, -0.5f, -0.5f}, + {1.0f, 0.0f, 1.5748f}, + {1.0f, -0.187324273f, -0.468124273f}, + {1.0f, 1.8556f, 0.0f}, + }, + [COLOR_SPACE_YCBCR601_LIMITED] = + { + {-0.0625f, -0.5f, -0.5f}, + {1.164383562f, 0.0f, 1.596026786f}, + {1.164383562f, -0.39176229f, -0.812967647f}, + {1.164383562f, 2.017232143f, 0.0f}, + }, + [COLOR_SPACE_YCBCR709_LIMITED] = + { + {-0.0625f, -0.5f, -0.5f}, + {1.164383562f, 0.0f, 1.792741071f}, + {1.164383562f, -0.213248614f, -0.532909329f}, + {1.164383562f, 2.112401786f, 0.0f}, + }, + [COLOR_SPACE_2020_YCBCR] = + { + {0.0f, -512.f / 1023.f, -512.f / 1023.f}, + {1.0f, 0.0f, 1.4746f}, + {1.0f, -0.164553127f, -0.571353127f}, + {1.0f, 1.8814f, 0.0f}, + }, + [COLOR_SPACE_2020_YCBCR_LIMITED] = + { + {-0.0625f, -0.5f, -0.5f}, + {1.167808219f, 0.0f, 1.683611384f}, + {1.167808219f, -0.187877063f, -0.652337331f}, + {1.167808219f, 2.148071652f, 0.0f}, + }, + [COLOR_SPACE_SRGB_LIMITED] = + { + {-0.0626221f, -0.0626221f, -0.0626221f}, + {1.167783652f, 0.0f, 0.0f}, + {0.0f, 1.167783652f, 0.0f}, + {0.0f, 0.0, 1.167783652f}, + }, + [COLOR_SPACE_2020_RGB_LIMITEDRANGE] = { + {-0.0626221f, -0.0626221f, -0.0626221f}, + {1.167783652f, 0.0f, 0.0f}, + {0.0f, 1.167783652f, 0.0f}, + {0.0f, 0.0, 1.167783652f}, + }}; + +static double clip_double(double x) +{ + if (x < 0.0) + return 0.0; + else if (x > 1.0) + return 1.0; + else + return x; +} + +static float clip_float(float x) +{ + if (x < 0.0f) + return 0.0f; + else if (x > 1.0f) + return 1.0f; + else + return x; +} + +static bool bg_csc(struct vpe_color *bg_color, enum color_space cs) +{ + struct csc_table *entry = &bgcolor_to_rgbfull_table[cs]; + float csc_final[3] = {0}; + float csc_mm[3][4] = {0}; + bool output_is_clipped = false; + + memcpy(&csc_mm[0][0], &entry->red_coef, sizeof(struct csc_vector)); + memcpy(&csc_mm[1][0], &entry->green_coef, sizeof(struct csc_vector)); + memcpy(&csc_mm[2][0], &entry->blue_coef, sizeof(struct csc_vector)); + + csc_mm[0][3] = entry->rgb_offset.x * csc_mm[0][0] + entry->rgb_offset.y * csc_mm[0][1] + + entry->rgb_offset.z * csc_mm[0][2]; + + csc_mm[1][3] = entry->rgb_offset.x * csc_mm[1][0] + entry->rgb_offset.y * csc_mm[1][1] + + entry->rgb_offset.z * csc_mm[1][2]; + + csc_mm[2][3] = entry->rgb_offset.x * csc_mm[2][0] + entry->rgb_offset.y * csc_mm[2][1] + + entry->rgb_offset.z * csc_mm[2][2]; + + csc_final[0] = csc_mm[0][0] * bg_color->ycbcra.y + csc_mm[0][1] * bg_color->ycbcra.cb + + csc_mm[0][2] * bg_color->ycbcra.cr + csc_mm[0][3]; + + csc_final[1] = csc_mm[1][0] * bg_color->ycbcra.y + csc_mm[1][1] * bg_color->ycbcra.cb + + csc_mm[1][2] * bg_color->ycbcra.cr + csc_mm[1][3]; + + csc_final[2] = csc_mm[2][0] * bg_color->ycbcra.y + csc_mm[2][1] * bg_color->ycbcra.cb + + csc_mm[2][2] * bg_color->ycbcra.cr + csc_mm[2][3]; + + // switch to RGB components + bg_color->rgba.a = bg_color->ycbcra.a; + bg_color->rgba.r = clip_float(csc_final[0]); + bg_color->rgba.g = clip_float(csc_final[1]); + bg_color->rgba.b = clip_float(csc_final[2]); + if ((bg_color->rgba.r != csc_final[0]) || (bg_color->rgba.g != csc_final[1]) || + (bg_color->rgba.b != csc_final[2])) { + output_is_clipped = true; + } + bg_color->is_ycbcr = false; + return output_is_clipped; +} + +struct gamma_coefs { + float a0; + float a1; + float a2; + float a3; + float user_gamma; + float user_contrast; + float user_brightness; +}; + +// srgb, 709, G24 +static const int32_t numerator01[] = {31308, 180000, 0}; +static const int32_t numerator02[] = {12920, 4500, 0}; +static const int32_t numerator03[] = {55, 99, 0}; +static const int32_t numerator04[] = {55, 99, 0}; +static const int32_t numerator05[] = {2400, 2222, 2400}; + +static bool build_coefficients(struct gamma_coefs *coefficients, enum color_transfer_func type) +{ + uint32_t index = 0; + bool ret = true; + + if (type == TRANSFER_FUNC_SRGB) + index = 0; + else if (type == TRANSFER_FUNC_BT709) + index = 1; + else if (type == TRANSFER_FUNC_BT1886) + index = 2; + else { + ret = false; + goto release; + } + + coefficients->a0 = (float)numerator01[index] / 10000000.0f; + coefficients->a1 = (float)numerator02[index] / 1000.0f; + coefficients->a2 = (float)numerator03[index] / 1000.0f; + coefficients->a3 = (float)numerator04[index] / 1000.0f; + coefficients->user_gamma = (float)numerator05[index] / 1000.0f; + +release: + return ret; +} + +static double translate_to_linear_space( + double arg, double a0, double a1, double a2, double a3, double gamma) +{ + double linear; + double base; + + a0 *= a1; + if (arg <= -a0) { + base = (a2 - arg) / (1.0 + a3); + linear = -pow(base, gamma); + } else if ((-a0 <= arg) && (arg <= a0)) + linear = arg / a1; + else { + base = (a2 + arg) / (1.0 + a3); + linear = pow(base, gamma); + } + + return linear; +} + +// for 709 & sRGB +static void compute_degam(enum color_transfer_func tf, double inY, double *outX, bool clip) +{ + double ret; + struct gamma_coefs coefs = {0}; + + build_coefficients(&coefs, tf); + + ret = translate_to_linear_space(inY, (double)coefs.a0, (double)coefs.a1, (double)coefs.a2, + (double)coefs.a3, (double)coefs.user_gamma); + + if (clip) { + ret = clip_double(ret); + } + *outX = ret; +} + +static double get_maximum_fp(double a, double b) +{ + if (a > b) + return a; + return b; +} + +static void compute_depq(double inY, double *outX, bool clip) +{ + double M1 = 0.159301758; + double M2 = 78.84375; + double C1 = 0.8359375; + double C2 = 18.8515625; + double C3 = 18.6875; + + double nPowM2; + double base; + double one = 1.0; + double zero = 0.0; + bool negative = false; + double ret; + + if (inY < zero) { + inY = -inY; + negative = true; + } + nPowM2 = pow(inY, one / M2); + base = get_maximum_fp(nPowM2 - C1, zero) / (C2 - C3 * nPowM2); + ret = pow(base, one / M1); + if (clip) { + ret = clip_double(ret); + } + if (negative) + ret = -ret; + + *outX = ret; +} + +static bool is_rgb_limited(enum color_space cs) +{ + return (cs == COLOR_SPACE_SRGB_LIMITED || cs == COLOR_SPACE_2020_RGB_LIMITEDRANGE); +} + +void vpe_bg_color_convert( + enum color_space output_cs, struct transfer_func *output_tf, struct vpe_color *bg_color) +{ + enum color_space bgcolor_cs; + + if (bg_color->is_ycbcr) { + // Need YUV to RGB csc as internal pipe is using RGB full range + // For range conversion, if output is limited, we assume bg color + // is limited range too + switch (output_cs) { + // output is ycbr cs, follow output's setting + case COLOR_SPACE_YCBCR601: + case COLOR_SPACE_YCBCR709: + case COLOR_SPACE_YCBCR601_LIMITED: + case COLOR_SPACE_YCBCR709_LIMITED: + case COLOR_SPACE_2020_YCBCR: + case COLOR_SPACE_2020_YCBCR_LIMITED: + bgcolor_cs = output_cs; + break; + // output is RGB cs, follow output's range + // but need yuv to rgb csc + case COLOR_SPACE_SRGB_LIMITED: + bgcolor_cs = COLOR_SPACE_YCBCR709_LIMITED; + break; + case COLOR_SPACE_2020_RGB_LIMITEDRANGE: + bgcolor_cs = COLOR_SPACE_2020_YCBCR_LIMITED; + break; + case COLOR_SPACE_SRGB: + case COLOR_SPACE_MSREF_SCRGB: + bgcolor_cs = COLOR_SPACE_YCBCR709; + break; + case COLOR_SPACE_2020_RGB_FULLRANGE: + bgcolor_cs = COLOR_SPACE_2020_YCBCR; + break; + default: + // should revise the newly added CS + // and set corresponding bgcolor_cs accordingly + VPE_ASSERT(0); + bgcolor_cs = COLOR_SPACE_YCBCR709; + break; + } + } else { + // RGB BG color, use output's cs for range check + bgcolor_cs = output_cs; + } + + // input is [0-0xffff] + // convert bg color to RGB full range for use inside pipe + if (bg_color->is_ycbcr || is_rgb_limited(bgcolor_cs)) + bg_csc(bg_color, bgcolor_cs); + + if (output_tf->type == TF_TYPE_DISTRIBUTED_POINTS) { + double degam_r = 0; + double degam_g = 0; + double degam_b = 0; + + // de-gam + switch (output_tf->tf) { + case TRANSFER_FUNC_SRGB: + case TRANSFER_FUNC_BT709: + case TRANSFER_FUNC_BT1886: + compute_degam(output_tf->tf, (double)bg_color->rgba.r, °am_r, true); + compute_degam(output_tf->tf, (double)bg_color->rgba.g, °am_g, true); + compute_degam(output_tf->tf, (double)bg_color->rgba.b, °am_b, true); + bg_color->rgba.r = (float)degam_r; + bg_color->rgba.g = (float)degam_g; + bg_color->rgba.b = (float)degam_b; + break; + case TRANSFER_FUNC_PQ2084: + compute_depq((double)bg_color->rgba.r, °am_r, true); + compute_depq((double)bg_color->rgba.g, °am_g, true); + compute_depq((double)bg_color->rgba.b, °am_b, true); + bg_color->rgba.r = (float)degam_r; + bg_color->rgba.g = (float)degam_g; + bg_color->rgba.b = (float)degam_b; + break; + case TRANSFER_FUNC_LINEAR_0_125: + break; + default: + VPE_ASSERT(0); + break; + } + } + + // for TF_TYPE_BYPASS, bg color should be programmed to mpc as linear +} +enum vpe_status vpe_bg_color_outside_cs_gamut( + const struct vpe_color_space *vcs, struct vpe_color *bg_color) +{ + enum color_space cs; + enum color_transfer_func tf; + struct vpe_color bg_color_copy = *bg_color; + vpe_color_get_color_space_and_tf(vcs, &cs, &tf); + + if (is_rgb_limited(cs) || (bg_color->is_ycbcr)) { + // using the bg_color_copy instead as bg_csc will modify it + // we should not do modification in checking stage + // otherwise validate_cached_param() will fail + if (bg_csc(&bg_color_copy, cs)) { + return VPE_STATUS_BG_COLOR_OUT_OF_RANGE; + } + } + return VPE_STATUS_OK; +} diff --git a/src/amd/vpelib/src/core/color_cs.c b/src/amd/vpelib/src/core/color_cs.c new file mode 100644 index 00000000000..9e8d2a0b088 --- /dev/null +++ b/src/amd/vpelib/src/core/color_cs.c @@ -0,0 +1,744 @@ +/* Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include +#include "common.h" +#include "vpe_priv.h" +#include "color.h" +#include "color_cs.h" +#include "hw_shared.h" +#include "conversion.h" + +#define DIVIDER 10000 +/* S2D13 value in [-3.999...3.999] */ +#define S2D13_MIN (-39990) +#define S2D13_MAX (39990) + +static void translate_blt_to_internal_adjustments( + const struct vpe_color_adjust *blt_adjust, struct vpe_color_adjustments *dal_adjust); + +/* these values are defaults: 0 brightness, 1 contrast, 0 hue, 1 saturation*/ +static struct vpe_color_adjust defaultClrAdjust = {0.0f, 1.0f, 0.0f, 1.0f}; + +void vpe_color_set_adjustments_to_default(struct vpe_color_adjust *crt_vpe_adjusts) +{ + *crt_vpe_adjusts = defaultClrAdjust; +} + +bool vpe_color_different_color_adjusts( + const struct vpe_color_adjust *new_vpe_adjusts, struct vpe_color_adjust *crt_vpe_adjsuts) +{ + if ((crt_vpe_adjsuts->brightness != new_vpe_adjusts->brightness) || + (crt_vpe_adjsuts->saturation != new_vpe_adjusts->saturation) || + (crt_vpe_adjsuts->hue != new_vpe_adjusts->hue) || + (crt_vpe_adjsuts->contrast != new_vpe_adjusts->contrast)) { + return true; + } + return false; +} + +/** + * Adjustment Min Max default step + * + * Input range + * Brightness -100.0f, 100.0f, 0.0f, 0.1f + * Contrast 0.0f, 2.0f, 1.0f, 0.01f + * Hue -180.0f, 180.0f, 0.0f, 1.0f + * Saturation 0.0f, 3.0f, 1.0f, 0.01f + * + * DAL range + * Brightness -100, 100, 0, 1 + * Contrast 0, 200, 100, 1 + * Hue -30, 30, 0, 1 + * Saturation 0, 200, 100, 1 + */ + +static void translate_blt_to_internal_adjustments( + const struct vpe_color_adjust *blt_adjust, struct vpe_color_adjustments *dal_adjust) +{ + dal_adjust->brightness.current = (int)(10 * blt_adjust->brightness); + dal_adjust->brightness.min = -1000; + dal_adjust->brightness.max = 1000; + + dal_adjust->contrast.current = (int)(100 * blt_adjust->contrast); + dal_adjust->contrast.min = 0; + dal_adjust->contrast.max = 200; + + dal_adjust->saturation.current = (int)(100 * blt_adjust->saturation); + dal_adjust->saturation.min = 0; + dal_adjust->saturation.max = 300; // assuming input bigger range + + dal_adjust->hue.current = (int)(blt_adjust->hue); + dal_adjust->hue.min = -180; + dal_adjust->hue.max = 180; // assuming input bigger range +} + +static int get_hw_value_from_sw_value(int swVal, int swMin, int swMax, int hwMin, int hwMax) +{ + int dSW = swMax - swMin; /*software adjustment range size*/ + int dHW = hwMax - hwMin; /*hardware adjustment range size*/ + int hwVal; /*HW adjustment value*/ + + /* error case, I preserve the behavior from the predecessor + *getHwStepFromSwHwMinMaxValue (removed in Feb 2013) + *which was the FP version that only computed SCLF (i.e. dHW/dSW). + *it would return 0 in this case so + *hwVal = hwMin from the formula given in @brief + */ + if (dSW == 0) + return hwMin; + + /*it's quite often that ranges match, + *e.g. for overlay colors currently (Feb 2013) + *only brightness has a different + *HW range, and in this case no multiplication or division is needed, + *and if minimums match, no calculation at all + */ + + if (dSW != dHW) { + hwVal = (swVal - swMin) * dHW / dSW + hwMin; + } else { + hwVal = swVal; + if (swMin != hwMin) + hwVal += (hwMin - swMin); + } + + return hwVal; +} + +static void color_adjustments_to_fixed_point(const struct vpe_color_adjustments *vpe_adjust, + bool icsc, // input csc or output csc + struct fixed31_32 *grph_cont, struct fixed31_32 *grph_sat, struct fixed31_32 *grph_bright, + struct fixed31_32 *sin_grph_hue, struct fixed31_32 *cos_grph_hue) +{ + /* Hue adjustment could be negative. -45 ~ +45 */ + struct fixed31_32 hue; + const int hw_hue_min = -30; + const int hw_hue_max = 30; + const int hw_sat_min = 0; + const int hw_sat_max = 200; + const int hw_contrast_min = 0; + const int hw_contrast_max = 200; + const int hw_bright_min = -1000; + const int hw_bright_max = 1000; + if (icsc) { + hue = vpe_fixpt_mul( + vpe_fixpt_from_fraction( + get_hw_value_from_sw_value(vpe_adjust->hue.current, vpe_adjust->hue.min, + vpe_adjust->hue.max, -hw_hue_min, hw_hue_max), + 180), + vpe_fixpt_pi); + + // In MMD is -100 to +100 in 16-235 range; which when scaled to full + // range is ~-116 to +116. When normalized this is about 0.4566. + *grph_bright = vpe_fixpt_from_fraction( + get_hw_value_from_sw_value(vpe_adjust->brightness.current, vpe_adjust->brightness.min, + vpe_adjust->brightness.max, hw_bright_min, hw_bright_max), + 1000); + + *grph_cont = vpe_fixpt_from_fraction( + get_hw_value_from_sw_value(vpe_adjust->contrast.current, vpe_adjust->contrast.min, + vpe_adjust->contrast.max, hw_contrast_min, hw_contrast_max), + 100); + + *grph_sat = vpe_fixpt_from_fraction( + get_hw_value_from_sw_value(vpe_adjust->saturation.current, vpe_adjust->saturation.min, + vpe_adjust->saturation.max, hw_sat_min, hw_sat_max), + 100); + } else { + hue = vpe_fixpt_mul( + vpe_fixpt_from_fraction( + get_hw_value_from_sw_value(vpe_adjust->hue.current, vpe_adjust->hue.min, + vpe_adjust->hue.max, -hw_hue_min, hw_hue_max), + 180), + vpe_fixpt_pi); + + *grph_bright = vpe_fixpt_from_fraction( + get_hw_value_from_sw_value(vpe_adjust->brightness.current, vpe_adjust->brightness.min, + vpe_adjust->brightness.max, hw_bright_min, hw_bright_max), + 100); + + *grph_cont = vpe_fixpt_from_fraction( + get_hw_value_from_sw_value(vpe_adjust->contrast.current, vpe_adjust->contrast.min, + vpe_adjust->contrast.max, hw_contrast_min, hw_contrast_max), + 100); + + *grph_sat = vpe_fixpt_from_fraction( + get_hw_value_from_sw_value(vpe_adjust->saturation.current, vpe_adjust->saturation.min, + vpe_adjust->saturation.max, hw_sat_min, hw_sat_max), + 100); + } + + *sin_grph_hue = vpe_fixpt_sin(hue); + *cos_grph_hue = vpe_fixpt_cos(hue); +} + +static void calculate_rgb_matrix_legacy( + struct vpe_color_adjustments *vpe_adjust, struct fixed31_32 *rgb_matrix) +{ + const struct fixed31_32 k1 = vpe_fixpt_from_fraction(787400, 1000000); + const struct fixed31_32 k2 = vpe_fixpt_from_fraction(180428, 1000000); + const struct fixed31_32 k3 = vpe_fixpt_from_fraction(-715200, 1000000); + const struct fixed31_32 k4 = vpe_fixpt_from_fraction(606972, 1000000); + const struct fixed31_32 k5 = vpe_fixpt_from_fraction(-72200, 1000000); + const struct fixed31_32 k6 = vpe_fixpt_from_fraction(-787400, 1000000); + const struct fixed31_32 k7 = vpe_fixpt_from_fraction(-212600, 1000000); + const struct fixed31_32 k8 = vpe_fixpt_from_fraction(-147296, 1000000); + const struct fixed31_32 k9 = vpe_fixpt_from_fraction(284800, 1000000); + const struct fixed31_32 k10 = vpe_fixpt_from_fraction(-95354, 1000000); + const struct fixed31_32 k11 = vpe_fixpt_from_fraction(-72200, 1000000); + const struct fixed31_32 k12 = vpe_fixpt_from_fraction(242650, 1000000); + const struct fixed31_32 k13 = vpe_fixpt_from_fraction(-212600, 1000000); + const struct fixed31_32 k14 = vpe_fixpt_from_fraction(927800, 1000000); + const struct fixed31_32 k15 = vpe_fixpt_from_fraction(-715200, 1000000); + const struct fixed31_32 k16 = vpe_fixpt_from_fraction(-842726, 1000000); + const struct fixed31_32 k17 = vpe_fixpt_from_fraction(927800, 1000000); + const struct fixed31_32 k18 = vpe_fixpt_from_fraction(-85074, 1000000); + + const struct fixed31_32 luma_r = vpe_fixpt_from_fraction(2126, 10000); + const struct fixed31_32 luma_g = vpe_fixpt_from_fraction(7152, 10000); + const struct fixed31_32 luma_b = vpe_fixpt_from_fraction(722, 10000); + + struct fixed31_32 grph_cont; + struct fixed31_32 grph_sat; + struct fixed31_32 grph_bright; + struct fixed31_32 sin_grph_hue; + struct fixed31_32 cos_grph_hue; + + color_adjustments_to_fixed_point( + vpe_adjust, true, &grph_cont, &grph_sat, &grph_bright, &sin_grph_hue, &cos_grph_hue); + + /* COEF_1_1 = GrphCont * (LumaR + GrphSat * (Cos(GrphHue) * K1 +*/ + /* Sin(GrphHue) * K2))*/ + /* (Cos(GrphHue) * K1 + Sin(GrphHue) * K2)*/ + rgb_matrix[0] = vpe_fixpt_add(vpe_fixpt_mul(cos_grph_hue, k1), vpe_fixpt_mul(sin_grph_hue, k2)); + /* GrphSat * (Cos(GrphHue) * K1 + Sin(GrphHue) * K2 */ + rgb_matrix[0] = vpe_fixpt_mul(grph_sat, rgb_matrix[0]); + /* (LumaR + GrphSat * (Cos(GrphHue) * K1 + Sin(GrphHue) * K2))*/ + rgb_matrix[0] = vpe_fixpt_add(luma_r, rgb_matrix[0]); + /* GrphCont * (LumaR + GrphSat * (Cos(GrphHue) * K1 + Sin(GrphHue)**/ + /* K2))*/ + rgb_matrix[0] = vpe_fixpt_mul(grph_cont, rgb_matrix[0]); + + /* COEF_1_2 = GrphCont * (LumaG + GrphSat * (Cos(GrphHue) * K3 +*/ + /* Sin(GrphHue) * K4))*/ + /* (Cos(GrphHue) * K3 + Sin(GrphHue) * K4)*/ + rgb_matrix[1] = vpe_fixpt_add(vpe_fixpt_mul(cos_grph_hue, k3), vpe_fixpt_mul(sin_grph_hue, k4)); + /* GrphSat * (Cos(GrphHue) * K3 + Sin(GrphHue) * K4)*/ + rgb_matrix[1] = vpe_fixpt_mul(grph_sat, rgb_matrix[1]); + /* (LumaG + GrphSat * (Cos(GrphHue) * K3 + Sin(GrphHue) * K4))*/ + rgb_matrix[1] = vpe_fixpt_add(luma_g, rgb_matrix[1]); + /* GrphCont * (LumaG + GrphSat * (Cos(GrphHue) * K3 + Sin(GrphHue)**/ + /* K4))*/ + rgb_matrix[1] = vpe_fixpt_mul(grph_cont, rgb_matrix[1]); + + /* COEF_1_3 = GrphCont * (LumaB + GrphSat * (Cos(GrphHue) * K5 +*/ + /* Sin(GrphHue) * K6))*/ + /* (Cos(GrphHue) * K5 + Sin(GrphHue) * K6)*/ + rgb_matrix[2] = vpe_fixpt_add(vpe_fixpt_mul(cos_grph_hue, k5), vpe_fixpt_mul(sin_grph_hue, k6)); + /* GrphSat * (Cos(GrphHue) * K5 + Sin(GrphHue) * K6)*/ + rgb_matrix[2] = vpe_fixpt_mul(grph_sat, rgb_matrix[2]); + /* LumaB + GrphSat * (Cos(GrphHue) * K5 + Sin(GrphHue) * K6)*/ + rgb_matrix[2] = vpe_fixpt_add(luma_b, rgb_matrix[2]); + /* GrphCont * (LumaB + GrphSat * (Cos(GrphHue) * K5 + Sin(GrphHue)**/ + /* K6))*/ + rgb_matrix[2] = vpe_fixpt_mul(grph_cont, rgb_matrix[2]); + + /* COEF_1_4 = GrphBright*/ + rgb_matrix[3] = grph_bright; + + /* COEF_2_1 = GrphCont * (LumaR + GrphSat * (Cos(GrphHue) * K7 +*/ + /* Sin(GrphHue) * K8))*/ + /* (Cos(GrphHue) * K7 + Sin(GrphHue) * K8)*/ + rgb_matrix[4] = vpe_fixpt_add(vpe_fixpt_mul(cos_grph_hue, k7), vpe_fixpt_mul(sin_grph_hue, k8)); + /* GrphSat * (Cos(GrphHue) * K7 + Sin(GrphHue) * K8)*/ + rgb_matrix[4] = vpe_fixpt_mul(grph_sat, rgb_matrix[4]); + /* (LumaR + GrphSat * (Cos(GrphHue) * K7 + Sin(GrphHue) * K8))*/ + rgb_matrix[4] = vpe_fixpt_add(luma_r, rgb_matrix[4]); + /* GrphCont * (LumaR + GrphSat * (Cos(GrphHue) * K7 + Sin(GrphHue)**/ + /* K8))*/ + rgb_matrix[4] = vpe_fixpt_mul(grph_cont, rgb_matrix[4]); + + /* COEF_2_2 = GrphCont * (LumaG + GrphSat * (Cos(GrphHue) * K9 +*/ + /* Sin(GrphHue) * K10))*/ + /* (Cos(GrphHue) * K9 + Sin(GrphHue) * K10))*/ + rgb_matrix[5] = + vpe_fixpt_add(vpe_fixpt_mul(cos_grph_hue, k9), vpe_fixpt_mul(sin_grph_hue, k10)); + /* GrphSat * (Cos(GrphHue) * K9 + Sin(GrphHue) * K10))*/ + rgb_matrix[5] = vpe_fixpt_mul(grph_sat, rgb_matrix[5]); + /* (LumaG + GrphSat * (Cos(GrphHue) * K9 + Sin(GrphHue) * K10))*/ + rgb_matrix[5] = vpe_fixpt_add(luma_g, rgb_matrix[5]); + /* GrphCont * (LumaG + GrphSat * (Cos(GrphHue) * K9 + Sin(GrphHue)**/ + /* K10))*/ + rgb_matrix[5] = vpe_fixpt_mul(grph_cont, rgb_matrix[5]); + + /* COEF_2_3 = GrphCont * (LumaB + GrphSat * (Cos(GrphHue) * K11 +*/ + /* Sin(GrphHue) * K12))*/ + /* (Cos(GrphHue) * K11 + Sin(GrphHue) * K12))*/ + rgb_matrix[6] = + vpe_fixpt_add(vpe_fixpt_mul(cos_grph_hue, k11), vpe_fixpt_mul(sin_grph_hue, k12)); + /* GrphSat * (Cos(GrphHue) * K11 + Sin(GrphHue) * K12))*/ + rgb_matrix[6] = vpe_fixpt_mul(grph_sat, rgb_matrix[6]); + /* (LumaB + GrphSat * (Cos(GrphHue) * K11 + Sin(GrphHue) * K12))*/ + rgb_matrix[6] = vpe_fixpt_add(luma_b, rgb_matrix[6]); + /* GrphCont * (LumaB + GrphSat * (Cos(GrphHue) * K11 + Sin(GrphHue)**/ + /* K12))*/ + rgb_matrix[6] = vpe_fixpt_mul(grph_cont, rgb_matrix[6]); + + /* COEF_2_4 = GrphBright*/ + rgb_matrix[7] = grph_bright; + + /* COEF_3_1 = GrphCont * (LumaR + GrphSat * (Cos(GrphHue) * K13 +*/ + /* Sin(GrphHue) * K14))*/ + /* (Cos(GrphHue) * K13 + Sin(GrphHue) * K14)) */ + rgb_matrix[8] = + vpe_fixpt_add(vpe_fixpt_mul(cos_grph_hue, k13), vpe_fixpt_mul(sin_grph_hue, k14)); + /* GrphSat * (Cos(GrphHue) * K13 + Sin(GrphHue) * K14)) */ + rgb_matrix[8] = vpe_fixpt_mul(grph_sat, rgb_matrix[8]); + /* (LumaR + GrphSat * (Cos(GrphHue) * K13 + Sin(GrphHue) * K14)) */ + rgb_matrix[8] = vpe_fixpt_add(luma_r, rgb_matrix[8]); + /* GrphCont * (LumaR + GrphSat * (Cos(GrphHue) * K13 + Sin(GrphHue)**/ + /* K14)) */ + rgb_matrix[8] = vpe_fixpt_mul(grph_cont, rgb_matrix[8]); + + /* COEF_3_2 = GrphCont * (LumaG + GrphSat * (Cos(GrphHue) * K15 +*/ + /* Sin(GrphHue) * K16)) */ + /* GrphSat * (Cos(GrphHue) * K15 + Sin(GrphHue) * K16) */ + rgb_matrix[9] = + vpe_fixpt_add(vpe_fixpt_mul(cos_grph_hue, k15), vpe_fixpt_mul(sin_grph_hue, k16)); + /* (LumaG + GrphSat * (Cos(GrphHue) * K15 + Sin(GrphHue) * K16)) */ + rgb_matrix[9] = vpe_fixpt_mul(grph_sat, rgb_matrix[9]); + /* (LumaG + GrphSat * (Cos(GrphHue) * K15 + Sin(GrphHue) * K16)) */ + rgb_matrix[9] = vpe_fixpt_add(luma_g, rgb_matrix[9]); + /* GrphCont * (LumaG + GrphSat * (Cos(GrphHue) * K15 + Sin(GrphHue)**/ + /* K16)) */ + rgb_matrix[9] = vpe_fixpt_mul(grph_cont, rgb_matrix[9]); + + /* COEF_3_3 = GrphCont * (LumaB + GrphSat * (Cos(GrphHue) * K17 +*/ + /* Sin(GrphHue) * K18)) */ + /* (Cos(GrphHue) * K17 + Sin(GrphHue) * K18)) */ + rgb_matrix[10] = + vpe_fixpt_add(vpe_fixpt_mul(cos_grph_hue, k17), vpe_fixpt_mul(sin_grph_hue, k18)); + /* GrphSat * (Cos(GrphHue) * K17 + Sin(GrphHue) * K18)) */ + rgb_matrix[10] = vpe_fixpt_mul(grph_sat, rgb_matrix[10]); + /* (LumaB + GrphSat * (Cos(GrphHue) * K17 + Sin(GrphHue) * K18)) */ + rgb_matrix[10] = vpe_fixpt_add(luma_b, rgb_matrix[10]); + /* GrphCont * (LumaB + GrphSat * (Cos(GrphHue) * K17 + Sin(GrphHue)**/ + /* K18)) */ + rgb_matrix[10] = vpe_fixpt_mul(grph_cont, rgb_matrix[10]); + + /* COEF_3_4 = GrphBright */ + rgb_matrix[11] = grph_bright; +} + +static void calculate_rgb_limited_range_matrix_legacy( + struct vpe_color_adjustments *vpe_adjust, struct fixed31_32 *rgb_matrix) +{ + const struct fixed31_32 k1 = vpe_fixpt_from_fraction(701000, 1000000); + const struct fixed31_32 k2 = vpe_fixpt_from_fraction(236568, 1000000); + const struct fixed31_32 k3 = vpe_fixpt_from_fraction(-587000, 1000000); + const struct fixed31_32 k4 = vpe_fixpt_from_fraction(464432, 1000000); + const struct fixed31_32 k5 = vpe_fixpt_from_fraction(-114000, 1000000); + const struct fixed31_32 k6 = vpe_fixpt_from_fraction(-701000, 1000000); + const struct fixed31_32 k7 = vpe_fixpt_from_fraction(-299000, 1000000); + const struct fixed31_32 k8 = vpe_fixpt_from_fraction(-292569, 1000000); + const struct fixed31_32 k9 = vpe_fixpt_from_fraction(413000, 1000000); + const struct fixed31_32 k10 = vpe_fixpt_from_fraction(-92482, 1000000); + const struct fixed31_32 k11 = vpe_fixpt_from_fraction(-114000, 1000000); + const struct fixed31_32 k12 = vpe_fixpt_from_fraction(385051, 1000000); + const struct fixed31_32 k13 = vpe_fixpt_from_fraction(-299000, 1000000); + const struct fixed31_32 k14 = vpe_fixpt_from_fraction(886000, 1000000); + const struct fixed31_32 k15 = vpe_fixpt_from_fraction(-587000, 1000000); + const struct fixed31_32 k16 = vpe_fixpt_from_fraction(-741914, 1000000); + const struct fixed31_32 k17 = vpe_fixpt_from_fraction(886000, 1000000); + const struct fixed31_32 k18 = vpe_fixpt_from_fraction(-144086, 1000000); + + const struct fixed31_32 luma_r = vpe_fixpt_from_fraction(299, 1000); + const struct fixed31_32 luma_g = vpe_fixpt_from_fraction(587, 1000); + const struct fixed31_32 luma_b = vpe_fixpt_from_fraction(114, 1000); + /*onst struct fixed31_32 luma_scale = + vpe_fixpt_from_fraction(875855, 1000000);*/ + + const struct fixed31_32 rgb_scale = vpe_fixpt_from_fraction(85546875, 100000000); + const struct fixed31_32 rgb_bias = vpe_fixpt_from_fraction(625, 10000); + + struct fixed31_32 grph_cont; + struct fixed31_32 grph_sat; + struct fixed31_32 grph_bright; + struct fixed31_32 sin_grph_hue; + struct fixed31_32 cos_grph_hue; + + color_adjustments_to_fixed_point( + vpe_adjust, true, &grph_cont, &grph_sat, &grph_bright, &sin_grph_hue, &cos_grph_hue); + + /* COEF_1_1 = GrphCont * (LumaR + GrphSat * (Cos(GrphHue) * K1 +*/ + /* Sin(GrphHue) * K2))*/ + /* (Cos(GrphHue) * K1 + Sin(GrphHue) * K2)*/ + rgb_matrix[0] = vpe_fixpt_add(vpe_fixpt_mul(cos_grph_hue, k1), vpe_fixpt_mul(sin_grph_hue, k2)); + /* GrphSat * (Cos(GrphHue) * K1 + Sin(GrphHue) * K2 */ + rgb_matrix[0] = vpe_fixpt_mul(grph_sat, rgb_matrix[0]); + /* (LumaR + GrphSat * (Cos(GrphHue) * K1 + Sin(GrphHue) * K2))*/ + rgb_matrix[0] = vpe_fixpt_add(luma_r, rgb_matrix[0]); + /* GrphCont * (LumaR + GrphSat * (Cos(GrphHue) * K1 + Sin(GrphHue)**/ + /* K2))*/ + rgb_matrix[0] = vpe_fixpt_mul(grph_cont, rgb_matrix[0]); + /* LumaScale * GrphCont * (LumaR + GrphSat * (Cos(GrphHue) * K1 + */ + /* Sin(GrphHue) * K2))*/ + rgb_matrix[0] = vpe_fixpt_mul(rgb_scale, rgb_matrix[0]); + + /* COEF_1_2 = GrphCont * (LumaG + GrphSat * (Cos(GrphHue) * K3 +*/ + /* Sin(GrphHue) * K4))*/ + /* (Cos(GrphHue) * K3 + Sin(GrphHue) * K4)*/ + rgb_matrix[1] = vpe_fixpt_add(vpe_fixpt_mul(cos_grph_hue, k3), vpe_fixpt_mul(sin_grph_hue, k4)); + /* GrphSat * (Cos(GrphHue) * K3 + Sin(GrphHue) * K4)*/ + rgb_matrix[1] = vpe_fixpt_mul(grph_sat, rgb_matrix[1]); + /* (LumaG + GrphSat * (Cos(GrphHue) * K3 + Sin(GrphHue) * K4))*/ + rgb_matrix[1] = vpe_fixpt_add(luma_g, rgb_matrix[1]); + /* GrphCont * (LumaG + GrphSat * (Cos(GrphHue) * K3 + Sin(GrphHue)**/ + /* K4))*/ + rgb_matrix[1] = vpe_fixpt_mul(grph_cont, rgb_matrix[1]); + /* LumaScale * GrphCont * (LumaG + GrphSat *(Cos(GrphHue) * K3 + */ + /* Sin(GrphHue) * K4))*/ + rgb_matrix[1] = vpe_fixpt_mul(rgb_scale, rgb_matrix[1]); + + /* COEF_1_3 = GrphCont * (LumaB + GrphSat * (Cos(GrphHue) * K5 +*/ + /* Sin(GrphHue) * K6))*/ + /* (Cos(GrphHue) * K5 + Sin(GrphHue) * K6)*/ + rgb_matrix[2] = vpe_fixpt_add(vpe_fixpt_mul(cos_grph_hue, k5), vpe_fixpt_mul(sin_grph_hue, k6)); + /* GrphSat * (Cos(GrphHue) * K5 + Sin(GrphHue) * K6)*/ + rgb_matrix[2] = vpe_fixpt_mul(grph_sat, rgb_matrix[2]); + /* LumaB + GrphSat * (Cos(GrphHue) * K5 + Sin(GrphHue) * K6)*/ + rgb_matrix[2] = vpe_fixpt_add(luma_b, rgb_matrix[2]); + /* GrphCont * (LumaB + GrphSat * (Cos(GrphHue) * K5 + Sin(GrphHue)**/ + /* K6))*/ + rgb_matrix[2] = vpe_fixpt_mul(grph_cont, rgb_matrix[2]); + /* LumaScale * GrphCont * (LumaB + GrphSat *(Cos(GrphHue) * K5 + */ + /* Sin(GrphHue) * K6))*/ + rgb_matrix[2] = vpe_fixpt_mul(rgb_scale, rgb_matrix[2]); + + /* COEF_1_4 = RGBBias + RGBScale * GrphBright*/ + rgb_matrix[3] = vpe_fixpt_add(rgb_bias, vpe_fixpt_mul(rgb_scale, grph_bright)); + + /* COEF_2_1 = GrphCont * (LumaR + GrphSat * (Cos(GrphHue) * K7 +*/ + /* Sin(GrphHue) * K8))*/ + /* (Cos(GrphHue) * K7 + Sin(GrphHue) * K8)*/ + rgb_matrix[4] = vpe_fixpt_add(vpe_fixpt_mul(cos_grph_hue, k7), vpe_fixpt_mul(sin_grph_hue, k8)); + /* GrphSat * (Cos(GrphHue) * K7 + Sin(GrphHue) * K8)*/ + rgb_matrix[4] = vpe_fixpt_mul(grph_sat, rgb_matrix[4]); + /* (LumaR + GrphSat * (Cos(GrphHue) * K7 + Sin(GrphHue) * K8))*/ + rgb_matrix[4] = vpe_fixpt_add(luma_r, rgb_matrix[4]); + /* GrphCont * (LumaR + GrphSat * (Cos(GrphHue) * K7 + Sin(GrphHue)**/ + /* K8))*/ + rgb_matrix[4] = vpe_fixpt_mul(grph_cont, rgb_matrix[4]); + /* LumaScale * GrphCont * (LumaR + GrphSat * (Cos(GrphHue) * K7 + */ + /* Sin(GrphHue) * K8))*/ + rgb_matrix[4] = vpe_fixpt_mul(rgb_scale, rgb_matrix[4]); + + /* COEF_2_2 = GrphCont * (LumaG + GrphSat * (Cos(GrphHue) * K9 +*/ + /* Sin(GrphHue) * K10))*/ + /* (Cos(GrphHue) * K9 + Sin(GrphHue) * K10))*/ + rgb_matrix[5] = + vpe_fixpt_add(vpe_fixpt_mul(cos_grph_hue, k9), vpe_fixpt_mul(sin_grph_hue, k10)); + /* GrphSat * (Cos(GrphHue) * K9 + Sin(GrphHue) * K10))*/ + rgb_matrix[5] = vpe_fixpt_mul(grph_sat, rgb_matrix[5]); + /* (LumaG + GrphSat * (Cos(GrphHue) * K9 + Sin(GrphHue) * K10))*/ + rgb_matrix[5] = vpe_fixpt_add(luma_g, rgb_matrix[5]); + /* GrphCont * (LumaG + GrphSat * (Cos(GrphHue) * K9 + Sin(GrphHue)**/ + /* K10))*/ + rgb_matrix[5] = vpe_fixpt_mul(grph_cont, rgb_matrix[5]); + /* LumaScale * GrphCont * (LumaG + GrphSat *(Cos(GrphHue) * K9 + */ + /* Sin(GrphHue) * K10))*/ + rgb_matrix[5] = vpe_fixpt_mul(rgb_scale, rgb_matrix[5]); + + /* COEF_2_3 = GrphCont * (LumaB + GrphSat * (Cos(GrphHue) * K11 +*/ + /* Sin(GrphHue) * K12))*/ + /* (Cos(GrphHue) * K11 + Sin(GrphHue) * K12))*/ + rgb_matrix[6] = + vpe_fixpt_add(vpe_fixpt_mul(cos_grph_hue, k11), vpe_fixpt_mul(sin_grph_hue, k12)); + /* GrphSat * (Cos(GrphHue) * K11 + Sin(GrphHue) * K12))*/ + rgb_matrix[6] = vpe_fixpt_mul(grph_sat, rgb_matrix[6]); + /* (LumaB + GrphSat * (Cos(GrphHue) * K11 + Sin(GrphHue) * K12))*/ + rgb_matrix[6] = vpe_fixpt_add(luma_b, rgb_matrix[6]); + /* GrphCont * (LumaB + GrphSat * (Cos(GrphHue) * K11 + Sin(GrphHue)**/ + /* K12))*/ + rgb_matrix[6] = vpe_fixpt_mul(grph_cont, rgb_matrix[6]); + /* LumaScale * GrphCont * (LumaB + GrphSat *(Cos(GrphHue) * K11 +*/ + /* Sin(GrphHue) * K12)) */ + rgb_matrix[6] = vpe_fixpt_mul(rgb_scale, rgb_matrix[6]); + + /* COEF_2_4 = RGBBias + RGBScale * GrphBright*/ + rgb_matrix[7] = vpe_fixpt_add(rgb_bias, vpe_fixpt_mul(rgb_scale, grph_bright)); + + /* COEF_3_1 = GrphCont * (LumaR + GrphSat * (Cos(GrphHue) * K13 +*/ + /* Sin(GrphHue) * K14))*/ + /* (Cos(GrphHue) * K13 + Sin(GrphHue) * K14)) */ + rgb_matrix[8] = + vpe_fixpt_add(vpe_fixpt_mul(cos_grph_hue, k13), vpe_fixpt_mul(sin_grph_hue, k14)); + /* GrphSat * (Cos(GrphHue) * K13 + Sin(GrphHue) * K14)) */ + rgb_matrix[8] = vpe_fixpt_mul(grph_sat, rgb_matrix[8]); + /* (LumaR + GrphSat * (Cos(GrphHue) * K13 + Sin(GrphHue) * K14)) */ + rgb_matrix[8] = vpe_fixpt_add(luma_r, rgb_matrix[8]); + /* GrphCont * (LumaR + GrphSat * (Cos(GrphHue) * K13 + Sin(GrphHue)**/ + /* K14)) */ + rgb_matrix[8] = vpe_fixpt_mul(grph_cont, rgb_matrix[8]); + /* LumaScale * GrphCont * (LumaR + GrphSat * (Cos(GrphHue) * K13 +*/ + /* Sin(GrphHue) * K14))*/ + rgb_matrix[8] = vpe_fixpt_mul(rgb_scale, rgb_matrix[8]); + + /* COEF_3_2 = GrphCont * (LumaG + GrphSat * (Cos(GrphHue) * K15 +*/ + /* Sin(GrphHue) * K16)) */ + /* GrphSat * (Cos(GrphHue) * K15 + Sin(GrphHue) * K16) */ + rgb_matrix[9] = + vpe_fixpt_add(vpe_fixpt_mul(cos_grph_hue, k15), vpe_fixpt_mul(sin_grph_hue, k16)); + /* (LumaG + GrphSat * (Cos(GrphHue) * K15 + Sin(GrphHue) * K16)) */ + rgb_matrix[9] = vpe_fixpt_mul(grph_sat, rgb_matrix[9]); + /* (LumaG + GrphSat * (Cos(GrphHue) * K15 + Sin(GrphHue) * K16)) */ + rgb_matrix[9] = vpe_fixpt_add(luma_g, rgb_matrix[9]); + /* GrphCont * (LumaG + GrphSat * (Cos(GrphHue) * K15 + Sin(GrphHue)**/ + /* K16)) */ + rgb_matrix[9] = vpe_fixpt_mul(grph_cont, rgb_matrix[9]); + /* LumaScale * GrphCont * (LumaG + GrphSat *(Cos(GrphHue) * K15 + */ + /* Sin(GrphHue) * K16))*/ + rgb_matrix[9] = vpe_fixpt_mul(rgb_scale, rgb_matrix[9]); + + /* COEF_3_3 = GrphCont * (LumaB + GrphSat * (Cos(GrphHue) * K17 +*/ + /* Sin(GrphHue) * K18)) */ + /* (Cos(GrphHue) * K17 + Sin(GrphHue) * K18)) */ + rgb_matrix[10] = + vpe_fixpt_add(vpe_fixpt_mul(cos_grph_hue, k17), vpe_fixpt_mul(sin_grph_hue, k18)); + /* GrphSat * (Cos(GrphHue) * K17 + Sin(GrphHue) * K18)) */ + rgb_matrix[10] = vpe_fixpt_mul(grph_sat, rgb_matrix[10]); + /* (LumaB + GrphSat * (Cos(GrphHue) * K17 + Sin(GrphHue) * K18)) */ + rgb_matrix[10] = vpe_fixpt_add(luma_b, rgb_matrix[10]); + /* GrphCont * (LumaB + GrphSat * (Cos(GrphHue) * K17 + Sin(GrphHue)**/ + /* K18)) */ + rgb_matrix[10] = vpe_fixpt_mul(grph_cont, rgb_matrix[10]); + /* LumaScale * GrphCont * (LumaB + GrphSat *(Cos(GrphHue) * */ + /* K17 + Sin(GrphHue) * K18))*/ + rgb_matrix[10] = vpe_fixpt_mul(rgb_scale, rgb_matrix[10]); + + /* COEF_3_4 = RGBBias + RGBScale * GrphBright */ + rgb_matrix[11] = vpe_fixpt_add(rgb_bias, vpe_fixpt_mul(rgb_scale, grph_bright)); +} + +/* this function scales the matrix coefficients to fit a maximum integer bit range*/ +static bool vpe_scale_csc_matrix(struct fixed31_32 *matrix, unsigned int matrixLength, + unsigned int maxIntegerBits, struct fixed31_32 *scalingFactor) +{ + bool ret = false; + unsigned int index = 0; + long long maxIntegerVal = ((long long)1 << maxIntegerBits); + long long maxMatrixVal = 0; + unsigned int crtIntPart = 0; + struct fixed31_32 divisionFactor = vpe_fixpt_one; + long long crtValue = 0; + unsigned int posLargestBit = 0; + (*scalingFactor) = vpe_fixpt_one; // by default this is initialized to one + for (index = 0; index < matrixLength; index++) { + crtValue = matrix[index].value; + if (crtValue < 0) { + crtValue = -crtValue; + } + crtIntPart = (crtValue >> FIXED31_32_BITS_PER_FRACTIONAL_PART); + if (maxMatrixVal < crtIntPart) { + maxMatrixVal = crtIntPart; + } + } + if ((maxMatrixVal >= maxIntegerVal) && (maxIntegerVal > 0)) { + for (index = 0; index < (FIXED31_32_BITS_PER_FRACTIONAL_PART - 1); index++) { + if (maxMatrixVal & ((long long)1 << index)) { // scan all the bits + posLargestBit = index; + } + } + divisionFactor.value = (long long)1 << (posLargestBit - maxIntegerBits + 1); + divisionFactor.value <<= FIXED31_32_BITS_PER_FRACTIONAL_PART; + (*scalingFactor) = divisionFactor; + for (index = 0; index < matrixLength; index++) { + matrix[index] = vpe_fixpt_div(matrix[index], divisionFactor); + } + ret = true; + } + return ret; +} + +static void calculate_yuv_matrix(struct vpe_color_adjustments *vpe_adjust, + enum color_space color_space, struct vpe_csc_matrix *input_cs, struct fixed31_32 *yuv_matrix) +{ + struct fixed31_32 initialMatrix[12]; + uint32_t i = 0; + bool ovl = true; // if we ever have Output CSC case, we can reuse this function with ovl passed + // in as param + struct fixed31_32 grph_cont; + struct fixed31_32 grph_sat; + struct fixed31_32 grph_bright; + struct fixed31_32 sin_grph_hue; + struct fixed31_32 cos_grph_hue; + struct fixed31_32 multiplier; + struct fixed31_32 chromaOffset = vpe_fixpt_sub(vpe_fixpt_half, vpe_fixpt_one); // = -0.5 + struct fixed31_32 lumaOffset = { + 0x10101010LL}; //=16/255.0 This is an offset applied in the shader, not clear why + // to maintain compatibility this offset is still applied in VPE + + /* The input YCbCr to RGB matrix is modified to embed the color adjustments as follows: + A = initial YCbCr to RGB conversion matrix + s = saturation , h = hue, c = contrast, b = brightness + + | c*s*(a11*cos(h)+a13*sin(h)) a12*c c*s(a13*cos(h)-a11*sin(h)) | + |R| | | |Y+b | + |G|= | c*s*(a21*cos(h)+a23*sin(h)) a22*c c*s(a23*cos(h)-a21*sin(h)) | * |Cb-0.5| + |B| | | |Cr-0.5| + | c*s*(a31*cos(h)+a33*sin(h)) a32*c c*s(a33*cos(h)-a31*sin(h)) | + */ + + for (i = 0; i < 12; i++) { + initialMatrix[i] = vpe_convfix31_32(input_cs->regval[i]); // convert from s.2.13 to s.31.32 + } + color_adjustments_to_fixed_point( + vpe_adjust, ovl, &grph_cont, &grph_sat, &grph_bright, &sin_grph_hue, &cos_grph_hue); + grph_bright = vpe_fixpt_sub(grph_bright, lumaOffset); + multiplier = vpe_fixpt_mul(grph_cont, grph_sat); // contSat + + yuv_matrix[0] = + vpe_fixpt_mul(multiplier, vpe_fixpt_add(vpe_fixpt_mul(initialMatrix[0], cos_grph_hue), + vpe_fixpt_mul(initialMatrix[2], sin_grph_hue))); + + yuv_matrix[1] = vpe_fixpt_mul(initialMatrix[1], grph_cont); + + yuv_matrix[2] = + vpe_fixpt_mul(multiplier, vpe_fixpt_sub(vpe_fixpt_mul(initialMatrix[2], cos_grph_hue), + vpe_fixpt_mul(initialMatrix[0], sin_grph_hue))); + + yuv_matrix[3] = initialMatrix[3]; + + yuv_matrix[4] = + vpe_fixpt_mul(multiplier, vpe_fixpt_add(vpe_fixpt_mul(initialMatrix[4], cos_grph_hue), + vpe_fixpt_mul(initialMatrix[6], sin_grph_hue))); + + yuv_matrix[5] = vpe_fixpt_mul(initialMatrix[5], grph_cont); + + yuv_matrix[6] = + vpe_fixpt_mul(multiplier, vpe_fixpt_sub(vpe_fixpt_mul(initialMatrix[6], cos_grph_hue), + vpe_fixpt_mul(initialMatrix[4], sin_grph_hue))); + + yuv_matrix[7] = initialMatrix[7]; + + yuv_matrix[8] = + vpe_fixpt_mul(multiplier, vpe_fixpt_add(vpe_fixpt_mul(initialMatrix[8], cos_grph_hue), + vpe_fixpt_mul(initialMatrix[10], sin_grph_hue))); + + yuv_matrix[9] = vpe_fixpt_mul(initialMatrix[9], grph_cont); + + yuv_matrix[10] = + vpe_fixpt_mul(multiplier, vpe_fixpt_sub(vpe_fixpt_mul(initialMatrix[10], cos_grph_hue), + vpe_fixpt_mul(initialMatrix[8], sin_grph_hue))); + + yuv_matrix[3] = vpe_fixpt_add(vpe_fixpt_mul(grph_bright, yuv_matrix[1]), + vpe_fixpt_add(vpe_fixpt_mul(chromaOffset, yuv_matrix[0]), + vpe_fixpt_mul(chromaOffset, yuv_matrix[2]))); + yuv_matrix[7] = vpe_fixpt_add(vpe_fixpt_mul(grph_bright, yuv_matrix[5]), + vpe_fixpt_add(vpe_fixpt_mul(chromaOffset, yuv_matrix[4]), + vpe_fixpt_mul(chromaOffset, yuv_matrix[6]))); + yuv_matrix[11] = vpe_fixpt_add(vpe_fixpt_mul(grph_bright, yuv_matrix[9]), + vpe_fixpt_add(vpe_fixpt_mul(chromaOffset, yuv_matrix[8]), + vpe_fixpt_mul(chromaOffset, yuv_matrix[10]))); +} + +static void convert_float_matrix(uint16_t *matrix, struct fixed31_32 *flt, uint32_t buffer_size) +{ + const struct fixed31_32 min_2_13 = vpe_fixpt_from_fraction(S2D13_MIN, DIVIDER); + const struct fixed31_32 max_2_13 = vpe_fixpt_from_fraction(S2D13_MAX, DIVIDER); + uint32_t i; + uint16_t temp_matrix[12]; + + for (i = 0; i < 12; i++) + temp_matrix[i] = 0; + + for (i = 0; i < buffer_size; ++i) { + uint32_t reg_value = + conv_fixed_point_to_int_frac(vpe_fixpt_clamp(flt[i], min_2_13, max_2_13), 2, 13); + + temp_matrix[i] = (uint16_t)reg_value; + } + + matrix[4] = temp_matrix[0]; + matrix[5] = temp_matrix[1]; + matrix[6] = temp_matrix[2]; + matrix[7] = temp_matrix[3]; + + matrix[8] = temp_matrix[4]; + matrix[9] = temp_matrix[5]; + matrix[10] = temp_matrix[6]; + matrix[11] = temp_matrix[7]; + + matrix[0] = temp_matrix[8]; + matrix[1] = temp_matrix[9]; + matrix[2] = temp_matrix[10]; + matrix[3] = temp_matrix[11]; +} + +bool vpe_color_calculate_input_cs(struct vpe_priv *vpe_priv, enum color_space in_cs, + const struct vpe_color_adjust *vpe_blt_adjust, struct vpe_csc_matrix *input_cs, + struct fixed31_32 *matrix_scaling_factor) +{ + struct fixed31_32 fixed_csc_matrix[12]; + + struct vpe_color_adjustments vpe_adjust = {0}; + + if (vpe_blt_adjust) { + translate_blt_to_internal_adjustments(vpe_blt_adjust, &vpe_adjust); + } + + switch (in_cs) { + case COLOR_SPACE_SRGB: + case COLOR_SPACE_2020_RGB_FULLRANGE: + case COLOR_SPACE_MSREF_SCRGB: + case COLOR_SPACE_SRGB_LIMITED: + case COLOR_SPACE_2020_RGB_LIMITEDRANGE: + calculate_rgb_matrix_legacy(&vpe_adjust, fixed_csc_matrix); + break; + + case COLOR_SPACE_YCBCR601: + case COLOR_SPACE_YCBCR709: + case COLOR_SPACE_YCBCR601_LIMITED: + case COLOR_SPACE_YCBCR709_LIMITED: + case COLOR_SPACE_2020_YCBCR: + calculate_yuv_matrix(&vpe_adjust, in_cs, input_cs, fixed_csc_matrix); + if (vpe_priv->scale_yuv_matrix) { // in case the coefficitents are too large + // they are scaled down to fit the n integer bits, m + // fractional bits (for now 2.19) + vpe_log("Scale down YUV -> RGB matrix"); + vpe_scale_csc_matrix(fixed_csc_matrix, 12, 2, matrix_scaling_factor); + } else { + vpe_log("No scaling on the yuv -> rgb matrix"); + } + break; + + default: + calculate_rgb_matrix_legacy(&vpe_adjust, fixed_csc_matrix); + break; + } + conv_convert_float_matrix(&input_cs->regval[0], fixed_csc_matrix, 12); + + return true; +} diff --git a/src/amd/vpelib/src/core/color_gamma.c b/src/amd/vpelib/src/core/color_gamma.c new file mode 100644 index 00000000000..399f56cf96f --- /dev/null +++ b/src/amd/vpelib/src/core/color_gamma.c @@ -0,0 +1,623 @@ +/* Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include +#include "common.h" +#include "vpe_priv.h" +#include "color.h" +#include "color_gamma.h" +#include "hw_shared.h" + +#define PRECISE_LUT_REGION_START 224 +#define PRECISE_LUT_REGION_END 239 + +static struct hw_x_point coordinates_x[MAX_HW_POINTS + 2]; +static struct hw_x_point coordinates_x_degamma[MAX_HW_POINTS_DEGAMMA]; + +// these are helpers for calculations to reduce stack usage +// do not depend on these being preserved across calls + +/* Helper to optimize gamma calculation, only use in translate_from_linear, in + * particular the vpe_fixpt_pow function which is very expensive + * The idea is that our regions for X points are exponential and currently they all use + * the same number of points (NUM_PTS_IN_REGION) and in each region every point + * is exactly 2x the one at the same index in the previous region. In other words + * X[i] = 2 * X[i-NUM_PTS_IN_REGION] for i>=16 + * The other fact is that (2x)^gamma = 2^gamma * x^gamma + * So we compute and save x^gamma for the first 16 regions, and for every next region + * just multiply with 2^gamma which can be computed once, and save the result so we + * recursively compute all the values. + */ + +/* + * Regamma coefficients are used for both regamma and degamma. Degamma + * coefficients are calculated in our formula using the regamma coefficients. + */ +/*sRGB 709 2.2 2.4 P3*/ +static const int32_t numerator01[] = {31308, 180000, 0, 0, 0}; +static const int32_t numerator02[] = {12920, 4500, 0, 0, 0}; +static const int32_t numerator03[] = {55, 99, 0, 0, 0}; +static const int32_t numerator04[] = {55, 99, 0, 0, 0}; +static const int32_t numerator05[] = { + 2400, 2222, 2200, 2400, 2600}; // the standard REC 709 states 0.45. Inverse of that is 2.22 + + /* one-time setup of X points */ +void vpe_color_setup_x_points_distribution(void) +{ + struct fixed31_32 region_size = vpe_fixpt_from_int(128); + int32_t segment; + uint32_t seg_offset; + uint32_t index; + struct fixed31_32 increment; + + coordinates_x[MAX_HW_POINTS].x = region_size; + coordinates_x[MAX_HW_POINTS + 1].x = region_size; + + for (segment = 6; segment > (6 - NUM_REGIONS); segment--) { + region_size = vpe_fixpt_div_int(region_size, 2); + increment = vpe_fixpt_div_int(region_size, NUM_PTS_IN_REGION); + seg_offset = (uint32_t)((segment + (NUM_REGIONS - 7)) * NUM_PTS_IN_REGION); + + coordinates_x[seg_offset].x = region_size; + + for (index = seg_offset + 1; index < seg_offset + NUM_PTS_IN_REGION; index++) { + coordinates_x[index].x = vpe_fixpt_add(coordinates_x[index - 1].x, increment); + } + } +} + +/* Setting up x points for DEGAMMA once */ +void vpe_color_setup_x_points_distribution_degamma(void) +{ + struct fixed31_32 region_size = vpe_fixpt_from_int(1); + int32_t segment; + uint32_t index = 0; + uint32_t numptsdegamma = 1; + uint32_t segment_offset; + + /* Since region = -8 only has 1 point setting it up before the loop */ + coordinates_x_degamma[0].x = vpe_fixpt_div(vpe_fixpt_from_int(1), vpe_fixpt_from_int(512)); + + for (segment = -7; segment <= 0; segment++) { + segment_offset = numptsdegamma; + numptsdegamma *= 2; + + for (index = segment_offset; index < numptsdegamma; index++) { + coordinates_x_degamma[index].x = + vpe_fixpt_div(vpe_fixpt_from_int(index), vpe_fixpt_from_int(256)); + } + } + coordinates_x_degamma[MAX_HW_POINTS_DEGAMMA - 1].x = region_size; +} + +void vpe_compute_pq(struct fixed31_32 in_x, struct fixed31_32 *out_y) +{ + /* consts for PQ gamma formula. */ + const struct fixed31_32 m1 = vpe_fixpt_from_fraction(159301758, 1000000000); + const struct fixed31_32 m2 = vpe_fixpt_from_fraction(7884375, 100000); + const struct fixed31_32 c1 = vpe_fixpt_from_fraction(8359375, 10000000); + const struct fixed31_32 c2 = vpe_fixpt_from_fraction(188515625, 10000000); + const struct fixed31_32 c3 = vpe_fixpt_from_fraction(186875, 10000); + + struct fixed31_32 l_pow_m1; + struct fixed31_32 base; + + if (vpe_fixpt_le(vpe_fixpt_one, in_x)) { + *out_y = vpe_fixpt_one; + return; + } + + if (vpe_fixpt_lt(in_x, vpe_fixpt_zero)) + in_x = vpe_fixpt_zero; + + l_pow_m1 = vpe_fixpt_pow(in_x, m1); + base = vpe_fixpt_div(vpe_fixpt_add(c1, (vpe_fixpt_mul(c2, l_pow_m1))), + vpe_fixpt_add(vpe_fixpt_one, (vpe_fixpt_mul(c3, l_pow_m1)))); + *out_y = vpe_fixpt_pow(base, m2); +} + +static void compute_de_pq(struct fixed31_32 in_x, struct fixed31_32 *out_y) +{ + /* consts for dePQ gamma formula. */ + const struct fixed31_32 m1 = vpe_fixpt_from_fraction(159301758, 1000000000); + const struct fixed31_32 m2 = vpe_fixpt_from_fraction(7884375, 100000); + const struct fixed31_32 c1 = vpe_fixpt_from_fraction(8359375, 10000000); + const struct fixed31_32 c2 = vpe_fixpt_from_fraction(188515625, 10000000); + const struct fixed31_32 c3 = vpe_fixpt_from_fraction(186875, 10000); + + struct fixed31_32 l_pow_m1; + struct fixed31_32 base, div; + struct fixed31_32 base2; + + if (vpe_fixpt_lt(in_x, vpe_fixpt_zero)) + in_x = vpe_fixpt_zero; + + if (vpe_fixpt_le(vpe_fixpt_one, in_x)) { + *out_y = vpe_fixpt_one; + return; + } + + l_pow_m1 = vpe_fixpt_pow(in_x, vpe_fixpt_div(vpe_fixpt_one, m2)); + base = vpe_fixpt_sub(l_pow_m1, c1); + + div = vpe_fixpt_sub(c2, vpe_fixpt_mul(c3, l_pow_m1)); + + base2 = vpe_fixpt_div(base, div); + // avoid complex numbers + if (vpe_fixpt_lt(base2, vpe_fixpt_zero)) + base2 = vpe_fixpt_sub(vpe_fixpt_zero, base2); + + *out_y = vpe_fixpt_pow(base2, vpe_fixpt_div(vpe_fixpt_one, m1)); +} + +/* one-time pre-compute PQ values - only for sdr_white_level 80 */ +static void precompute_pq(void) +{ + int i; + struct fixed31_32 x; + const struct hw_x_point *coord_x = coordinates_x + 32; + struct fixed31_32 scaling_factor = vpe_fixpt_from_fraction(80, 10000); + + struct fixed31_32 *pq_table = vpe_color_get_table(type_pq_table); + + /* pow function has problems with arguments too small */ + for (i = 0; i < 32; i++) + pq_table[i] = vpe_fixpt_zero; + + for (i = 32; i <= MAX_HW_POINTS; i++) { + x = vpe_fixpt_mul(coord_x->x, scaling_factor); + vpe_compute_pq(x, &pq_table[i]); + ++coord_x; + } +} + +/* one-time pre-compute dePQ values - only for max pixel value 125 FP16. + yuv2rgbScaling is used when the output yuv->rgb is scaled down + due to limited range of the yuv2rgb matrix +*/ + +static void precompute_de_pq(struct fixed31_32 x_scale, struct fixed31_32 y_scale) +{ + uint32_t i; + struct fixed31_32 y; + struct fixed31_32 *de_pq_table = vpe_color_get_table(type_de_pq_table); + + for (i = 0; i < MAX_HW_POINTS_DEGAMMA; i++) { + compute_de_pq(vpe_fixpt_mul(coordinates_x_degamma[i].x, x_scale), &y); + de_pq_table[i] = vpe_fixpt_mul(y, y_scale); + } +} + +static bool build_coefficients( + struct gamma_coefficients *coefficients, enum color_transfer_func type) +{ + + uint32_t i = 0; + uint32_t index = 0; + bool ret = true; + + if (type == TRANSFER_FUNC_SRGB) + index = 0; + else if (type == TRANSFER_FUNC_BT709) + index = 1; + else if (type == TRANSFER_FUNC_BT1886) + index = 3; + else { + VPE_ASSERT(0); + ret = false; + goto release; + } + + do { + coefficients->a0[i] = vpe_fixpt_from_fraction(numerator01[index], 10000000); + coefficients->a1[i] = vpe_fixpt_from_fraction(numerator02[index], 1000); + coefficients->a2[i] = vpe_fixpt_from_fraction(numerator03[index], 1000); + coefficients->a3[i] = vpe_fixpt_from_fraction(numerator04[index], 1000); + coefficients->user_gamma[i] = vpe_fixpt_from_fraction(numerator05[index], 1000); + + ++i; + } while (i != ARRAY_SIZE(coefficients->a0)); +release: + return ret; +} + +// bt.1886 +static struct fixed31_32 translate_to_linear_space(struct fixed31_32 arg, struct fixed31_32 a0, + struct fixed31_32 a1, struct fixed31_32 a2, struct fixed31_32 a3, struct fixed31_32 gamma) +{ + struct fixed31_32 linear; + + a0 = vpe_fixpt_mul(a0, a1); + if (vpe_fixpt_le(arg, vpe_fixpt_neg(a0))) + + linear = vpe_fixpt_neg(vpe_fixpt_pow( + vpe_fixpt_div(vpe_fixpt_sub(a2, arg), vpe_fixpt_add(vpe_fixpt_one, a3)), gamma)); + + else if (vpe_fixpt_le(vpe_fixpt_neg(a0), arg) && vpe_fixpt_le(arg, a0)) + linear = vpe_fixpt_div(arg, a1); + else + linear = vpe_fixpt_pow( + vpe_fixpt_div(vpe_fixpt_add(a2, arg), vpe_fixpt_add(vpe_fixpt_one, a3)), gamma); + + return linear; +} + +static inline struct fixed31_32 translate_to_linear_space_ex( + struct fixed31_32 arg, struct gamma_coefficients *coeff, uint32_t color_index) +{ + if (vpe_fixpt_le(vpe_fixpt_one, arg)) + return vpe_fixpt_one; + + return translate_to_linear_space(arg, coeff->a0[color_index], coeff->a1[color_index], + coeff->a2[color_index], coeff->a3[color_index], coeff->user_gamma[color_index]); +} + +static struct fixed31_32 translate_from_linear_space(struct translate_from_linear_space_args *args) +{ + const struct fixed31_32 one = vpe_fixpt_from_int(1); + + struct fixed31_32 scratch_1, scratch_2; + struct calculate_buffer *cal_buffer = args->cal_buffer; + + if (vpe_fixpt_le(one, args->arg)) + return one; + + if (vpe_fixpt_le(args->arg, vpe_fixpt_neg(args->a0))) { + scratch_1 = vpe_fixpt_add(one, args->a3); + scratch_2 = vpe_fixpt_pow(vpe_fixpt_neg(args->arg), vpe_fixpt_recip(args->gamma)); + scratch_1 = vpe_fixpt_mul(scratch_1, scratch_2); + scratch_1 = vpe_fixpt_sub(args->a2, scratch_1); + + return scratch_1; + } else if (vpe_fixpt_le(args->a0, args->arg)) { + if (cal_buffer->buffer_index == 0) { + cal_buffer->gamma_of_2 = + vpe_fixpt_pow(vpe_fixpt_from_int(2), vpe_fixpt_recip(args->gamma)); + } + scratch_1 = vpe_fixpt_add(one, args->a3); + // In the first region (first 16 points) and in the + // region delimited by START/END we calculate with + // full precision to avoid error accumulation. + if ((cal_buffer->buffer_index >= PRECISE_LUT_REGION_START && + cal_buffer->buffer_index <= PRECISE_LUT_REGION_END) || + (cal_buffer->buffer_index < 16)) + scratch_2 = vpe_fixpt_pow(args->arg, vpe_fixpt_recip(args->gamma)); + else + scratch_2 = vpe_fixpt_mul( + cal_buffer->gamma_of_2, cal_buffer->buffer[cal_buffer->buffer_index % 16]); + + if (cal_buffer->buffer_index != -1) { + cal_buffer->buffer[cal_buffer->buffer_index % 16] = scratch_2; + cal_buffer->buffer_index++; + } + + scratch_1 = vpe_fixpt_mul(scratch_1, scratch_2); + scratch_1 = vpe_fixpt_sub(scratch_1, args->a2); + + return scratch_1; + } else + return vpe_fixpt_mul(args->arg, args->a1); +} + +static struct fixed31_32 translate_from_linear_space_ex(struct fixed31_32 arg, + struct gamma_coefficients *coeff, uint32_t color_index, struct calculate_buffer *cal_buffer) +{ + struct translate_from_linear_space_args scratch_gamma_args = {0}; + + scratch_gamma_args.arg = arg; + scratch_gamma_args.a0 = coeff->a0[color_index]; + scratch_gamma_args.a1 = coeff->a1[color_index]; + scratch_gamma_args.a2 = coeff->a2[color_index]; + scratch_gamma_args.a3 = coeff->a3[color_index]; + scratch_gamma_args.gamma = coeff->user_gamma[color_index]; + scratch_gamma_args.cal_buffer = cal_buffer; + + return translate_from_linear_space(&scratch_gamma_args); +} + +static void build_pq(struct pwl_float_data_ex *rgb_regamma, uint32_t hw_points_num, + const struct hw_x_point *coordinate_x, uint32_t hdr_normalization) +{ + uint32_t i, start_index; + + struct pwl_float_data_ex *rgb = rgb_regamma; + const struct hw_x_point *coord_x = coordinate_x; + struct fixed31_32 output; + struct fixed31_32 scaling_factor = vpe_fixpt_from_fraction(1, hdr_normalization); + + /* TODO: start index is from segment 2^-24, skipping first segment + * due to x values too small for power calculations + */ + start_index = 32; + rgb += start_index; + coord_x += start_index; + + for (i = start_index; i <= hw_points_num; i++) { + + vpe_compute_pq(vpe_fixpt_mul(coord_x->x, scaling_factor), &output); + + /* should really not happen? */ + if (vpe_fixpt_lt(output, vpe_fixpt_zero)) + output = vpe_fixpt_zero; + else if (vpe_fixpt_lt(vpe_fixpt_one, output)) + output = vpe_fixpt_one; + + rgb->r = output; + rgb->g = output; + rgb->b = output; + + ++coord_x; + ++rgb; + } + coord_x = coordinates_x; + rgb = rgb_regamma; + struct fixed31_32 slope = vpe_fixpt_div(rgb[start_index].r, coord_x[start_index].x); + for (i = 0; i < start_index; i++) { + output = vpe_fixpt_mul(coord_x->x, slope); + rgb->r = output; + rgb->g = output; + rgb->b = output; + + ++coord_x; + ++rgb; + } +} + +static void build_de_pq(struct transfer_func_distributed_points *de_pq, uint32_t hw_points_num, + const struct hw_x_point *coordinate_x_degamma, struct fixed31_32 x_scale, + struct fixed31_32 y_scale) +{ + uint32_t i; + struct fixed31_32 output; + struct fixed31_32 *de_pq_table = vpe_color_get_table(type_de_pq_table); + + precompute_de_pq(x_scale, y_scale); + + for (i = 0; i < hw_points_num; i++) { + output = de_pq_table[i]; + /* should really not happen? */ + if (vpe_fixpt_lt(output, vpe_fixpt_zero)) + output = vpe_fixpt_zero; + + de_pq->red[i] = output; + de_pq->green[i] = output; + de_pq->blue[i] = output; + } +} + +static bool build_degamma(struct transfer_func_distributed_points *curve, uint32_t hw_points_num, + const struct hw_x_point *coordinate_x_degamma, enum color_transfer_func type, + struct fixed31_32 yuv2rgbScaling) +{ + uint32_t i; + struct gamma_coefficients coeff; + struct fixed31_32 scaledX; + struct fixed31_32 scaledY; + bool ret = false; + + if (!build_coefficients(&coeff, type)) + goto release; + + /* De-gamma X is 2^-8 to 2^0 i.e. 9 regions + */ + + i = 0; + while (i != MAX_HW_POINTS_DEGAMMA) { + scaledX = vpe_fixpt_mul(coordinate_x_degamma[i].x, yuv2rgbScaling); + scaledY = translate_to_linear_space_ex(scaledX, &coeff, 0); + curve->red[i] = scaledY; + curve->green[i] = scaledY; + curve->blue[i] = scaledY; + i++; + } + ret = true; +release: + return ret; +} + +static bool build_regamma(struct vpe_priv *vpe_priv, struct pwl_float_data_ex *rgb_regamma, + uint32_t hw_points_num, const struct hw_x_point *coordinate_x, enum color_transfer_func type, + struct calculate_buffer *cal_buffer) +{ + uint32_t i; + bool ret = false; + + struct gamma_coefficients *coeff; + struct pwl_float_data_ex *rgb = rgb_regamma; + const struct hw_x_point *coord_x = coordinate_x; + + coeff = (struct gamma_coefficients *)vpe_zalloc(sizeof(*coeff)); + if (!coeff) + goto release; + + if (!build_coefficients(coeff, type)) + goto release; + + memset(cal_buffer->buffer, 0, NUM_PTS_IN_REGION * sizeof(struct fixed31_32)); + cal_buffer->buffer_index = 0; // see variable definition for more info + + i = 0; + while (i <= hw_points_num) { + /* TODO use y vs r,g,b */ + rgb->r = translate_from_linear_space_ex(coord_x->x, coeff, 0, cal_buffer); + rgb->g = rgb->r; + rgb->b = rgb->r; + ++coord_x; + ++rgb; + ++i; + } + cal_buffer->buffer_index = -1; + ret = true; +release: + vpe_free(coeff); + return ret; +} + +static void build_new_custom_resulted_curve( + uint32_t hw_points_num, struct transfer_func_distributed_points *tf_pts) +{ + uint32_t i = 0; + + while (i != hw_points_num + 1) { + tf_pts->red[i] = vpe_fixpt_clamp(tf_pts->red[i], vpe_fixpt_zero, vpe_fixpt_one); + tf_pts->green[i] = vpe_fixpt_clamp(tf_pts->green[i], vpe_fixpt_zero, vpe_fixpt_one); + tf_pts->blue[i] = vpe_fixpt_clamp(tf_pts->blue[i], vpe_fixpt_zero, vpe_fixpt_one); + + ++i; + } +} + +static bool map_regamma_hw_to_x_user(struct pixel_gamma_point *coeff128, + struct hw_x_point *coords_x, const struct pwl_float_data_ex *rgb_regamma, + uint32_t hw_points_num, struct transfer_func_distributed_points *tf_pts, bool doClamping) +{ + /* setup to spare calculated ideal regamma values */ + + uint32_t i = 0; + struct hw_x_point *coords = coords_x; + const struct pwl_float_data_ex *regamma = rgb_regamma; + + /* just copy current rgb_regamma into tf_pts */ + while (i <= hw_points_num) { + tf_pts->red[i] = regamma->r; + tf_pts->green[i] = regamma->g; + tf_pts->blue[i] = regamma->b; + + ++regamma; + ++i; + } + + if (doClamping) { + /* this should be named differently, all it does is clamp to 0-1 */ + build_new_custom_resulted_curve(hw_points_num, tf_pts); + } + + return true; +} + +static bool calculate_curve(struct vpe_priv *vpe_priv, enum color_transfer_func trans, + struct transfer_func_distributed_points *points, struct pwl_float_data_ex *rgb_regamma, + uint32_t hdr_normalization, struct calculate_buffer *cal_buffer) +{ + bool ret = false; + + if (trans == TRANSFER_FUNC_PQ2084) { + points->end_exponent = 0; + points->x_point_at_y1_red = 1; + points->x_point_at_y1_green = 1; + points->x_point_at_y1_blue = 1; + + build_pq(rgb_regamma, MAX_HW_POINTS, coordinates_x, hdr_normalization); + ret = true; + } else if (trans == TRANSFER_FUNC_LINEAR_0_125) { + for (int i = 0; i < MAX_HW_POINTS; i++) { + rgb_regamma[i].r = + vpe_fixpt_mul(coordinates_x[i].x, vpe_fixpt_from_fraction(125, hdr_normalization)); + rgb_regamma[i].g = rgb_regamma[i].r; + rgb_regamma[i].b = rgb_regamma[i].r; + } + ret = true; + } else { + // trans == TRANSFER_FUNC_SRGB + // trans == TRANSFER_FUNC_BT709 + // trans == TRANSFER_FUNCTION_GAMMA22 + // trans == TRANSFER_FUNCTION_GAMMA24 + // trans == TRANSFER_FUNCTION_GAMMA26 + points->end_exponent = 0; + points->x_point_at_y1_red = 1; + points->x_point_at_y1_green = 1; + points->x_point_at_y1_blue = 1; + + build_regamma(vpe_priv, rgb_regamma, MAX_HW_POINTS, coordinates_x, trans, cal_buffer); + + ret = true; + } + return ret; +} + +#define _EXTRA_POINTS 3 + +bool vpe_color_calculate_degamma_params(struct vpe_priv *vpe_priv, struct fixed31_32 x_scale, + struct fixed31_32 y_scale, struct transfer_func *input_tf) +{ + struct transfer_func_distributed_points *tf_pts = &input_tf->tf_pts; + enum color_transfer_func tf; + uint32_t i; + bool ret = true; + + tf = input_tf->tf; + + if (tf == TRANSFER_FUNC_PQ2084 || tf == TRANSFER_FUNC_NORMALIZED_PQ) + build_de_pq(tf_pts, MAX_HW_POINTS_DEGAMMA, coordinates_x_degamma, x_scale, y_scale); + else if (tf == TRANSFER_FUNC_SRGB || tf == TRANSFER_FUNC_BT709 || tf == TRANSFER_FUNC_BT1886) + build_degamma(tf_pts, MAX_HW_POINTS_DEGAMMA, coordinates_x_degamma, tf, x_scale); + else if (tf == TRANSFER_FUNC_LINEAR_0_125) { + // just copy coordinates_x_degamma into curve + i = 0; + while (i != MAX_HW_POINTS_DEGAMMA) { + tf_pts->red[i] = vpe_fixpt_mul(coordinates_x[i].x, y_scale); + tf_pts->red[i] = tf_pts->red[i]; + tf_pts->red[i] = tf_pts->red[i]; + i++; + } + } else + ret = false; + + return ret; +} + +bool vpe_color_calculate_regamma_params( + struct vpe_priv *vpe_priv, struct transfer_func *output_tf, struct calculate_buffer *cal_buffer) +{ + struct transfer_func_distributed_points *tf_pts = &output_tf->tf_pts; + struct pwl_float_data_ex *rgb_regamma = NULL; + struct pixel_gamma_point *coeff = NULL; + enum color_transfer_func tf; + bool ret = false; + + rgb_regamma = (struct pwl_float_data_ex *)vpe_zalloc( + (MAX_HW_POINTS + _EXTRA_POINTS) * sizeof(*rgb_regamma)); + if (!rgb_regamma) + goto rgb_regamma_alloc_fail; + + coeff = + (struct pixel_gamma_point *)vpe_zalloc((MAX_HW_POINTS + _EXTRA_POINTS) * sizeof(*coeff)); + if (!coeff) + goto coeff_alloc_fail; + + tf = output_tf->tf; + + ret = calculate_curve(vpe_priv, tf, tf_pts, rgb_regamma, + vpe_priv->resource.internal_hdr_normalization, cal_buffer); + + if (ret) { + map_regamma_hw_to_x_user(coeff, coordinates_x, rgb_regamma, MAX_HW_POINTS, tf_pts, false); + } + + vpe_free(coeff); +coeff_alloc_fail: + vpe_free(rgb_regamma); +rgb_regamma_alloc_fail: + return ret; +} diff --git a/src/amd/vpelib/src/core/color_gamut.c b/src/amd/vpelib/src/core/color_gamut.c new file mode 100644 index 00000000000..00dec648b28 --- /dev/null +++ b/src/amd/vpelib/src/core/color_gamut.c @@ -0,0 +1,459 @@ +/* Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ +#include "color_gamut.h" + +#define DIVIDER 10000 + +struct gamut_space_entry { + unsigned int redX; + unsigned int redY; + unsigned int greenX; + unsigned int greenY; + unsigned int blueX; + unsigned int blueY; + + int a0; + int a1; + int a2; + int a3; + int gamma; +}; + +struct white_point_coodinates_entry { + unsigned int temperature; + unsigned int whiteX; + unsigned int whiteY; +}; + +static const struct gamut_space_entry predefined_gamuts[] = { + /* x_red y_red x_gr y_gr x_blue y_blue a0 a1 a2 a3 gamma + */ + [gamut_type_bt709] = {6400, 3300, 3000, 6000, 1500, 600, 180000, 4500, 99, 99, 2222}, + [gamut_type_bt601] = {6300, 3400, 3100, 5950, 1550, 700, 180000, 4500, 99, 99, 2200}, + [gamut_type_adobe_rgb] = {6400, 3300, 2100, 7100, 1500, 600, 180000, 4500, 99, 99, 2200}, + [gamut_type_srgb] = {6400, 3300, 3000, 6000, 1500, 600, 31308, 12920, 55, 55, 2400}, + [gamut_type_bt2020] = {7080, 2920, 1700, 7970, 1310, 460, 180000, 4500, 99, 99, 2200}, + [gamut_type_dcip3] = {6800, 3200, 2650, 6900, 1500, 600, 0, 0, 0, 0, 2600}}; + +static const struct white_point_coodinates_entry predefined_white_points[] = { + [white_point_type_5000k_horizon] = {5000, 3473, 3561}, + [white_point_type_6500k_noon] = {6500, 3127, 3290}, + [white_point_type_7500k_north_sky] = {7500, 3022, 3129}, + [white_point_type_9300k] = {9300, 2866, 2950}}; + +struct gamut_src_dst_matrix { + struct fixed31_32 rgbCoeffDst[9]; + struct fixed31_32 whiteCoeffDst[3]; + struct fixed31_32 rgbCoeffSrc[9]; + struct fixed31_32 whiteCoeffSrc[3]; + struct fixed31_32 xyzMatrix[9]; + struct fixed31_32 xyzOffset[3]; + struct fixed31_32 bradford[9]; +}; + +struct gamut_calculation_matrix { + struct fixed31_32 MTransposed[9]; + struct fixed31_32 XYZtoRGB_Custom[9]; + struct fixed31_32 XYZtoRGB_Ref[9]; + struct fixed31_32 RGBtoXYZ_Final[9]; + + struct fixed31_32 MResult[9]; + struct fixed31_32 fXYZofWhiteRef[9]; + struct fixed31_32 fXYZofRGBRef[9]; + struct fixed31_32 fXYZofRGBRefCopy[9]; + struct fixed31_32 MResultOffset[3]; +}; + +static void color_find_predefined_gamut( + struct color_space_coordinates *out_gamut, enum predefined_gamut_type type) +{ + out_gamut->redX = predefined_gamuts[type].redX; + out_gamut->redY = predefined_gamuts[type].redY; + out_gamut->greenX = predefined_gamuts[type].greenX; + out_gamut->greenY = predefined_gamuts[type].greenY; + out_gamut->blueX = predefined_gamuts[type].blueX; + out_gamut->blueY = predefined_gamuts[type].blueY; +} + +static void color_find_predefined_white_point( + struct color_space_coordinates *out_white_point, enum predefined_white_point_type type) +{ + out_white_point->whiteX = predefined_white_points[type].whiteX; + out_white_point->whiteY = predefined_white_points[type].whiteY; +} + +static void color_transpose_matrix(const struct fixed31_32 *M, unsigned int Rows, unsigned int Cols, + struct fixed31_32 *MTransposed) +{ + unsigned int i, j; + + for (i = 0; i < Rows; i++) { + for (j = 0; j < Cols; j++) + MTransposed[(j * Rows) + i] = M[(i * Cols) + j]; + } +} + +static void color_multiply_matrices(struct fixed31_32 *mResult, const struct fixed31_32 *M1, + const struct fixed31_32 *M2, unsigned int Rows1, unsigned int Cols1, unsigned int Cols2) +{ + unsigned int i, j, k; + + for (i = 0; i < Rows1; i++) { + for (j = 0; j < Cols2; j++) { + mResult[(i * Cols2) + j] = vpe_fixpt_zero; + for (k = 0; k < Cols1; k++) + mResult[(i * Cols2) + j] = vpe_fixpt_add(mResult[(i * Cols2) + j], + vpe_fixpt_mul(M1[(i * Cols1) + k], M2[(k * Cols2) + j])); + } + } +} + +static enum predefined_gamut_type color_space_to_predefined_gamut_types( + enum color_space color_space) +{ + switch (color_space) { + case COLOR_SPACE_JFIF: + case COLOR_SPACE_YCBCR709: + case COLOR_SPACE_YCBCR709_LIMITED: + return gamut_type_bt709; + case COLOR_SPACE_YCBCR601: + case COLOR_SPACE_YCBCR601_LIMITED: + return gamut_type_bt601; + case COLOR_SPACE_SRGB: + case COLOR_SPACE_SRGB_LIMITED: + case COLOR_SPACE_MSREF_SCRGB: + return gamut_type_srgb; + case COLOR_SPACE_2020_RGB_FULLRANGE: + case COLOR_SPACE_2020_RGB_LIMITEDRANGE: + case COLOR_SPACE_2020_YCBCR: + return gamut_type_bt2020; + default: + VPE_ASSERT(0); + return gamut_type_unknown; + } +} + +static enum vpe_status find_predefined_gamut_and_white_point( + struct vpe_priv *vpe_priv, struct color_gamut_data *gamut, enum color_space color_space) +{ + enum predefined_gamut_type gamut_type; + + gamut->color_space = color_space; + + gamut_type = color_space_to_predefined_gamut_types(color_space); + if (gamut_type == gamut_type_unknown) { + vpe_log("err: color space not supported! %d %d\n", (int)color_space, (int)gamut_type); + return VPE_STATUS_COLOR_SPACE_VALUE_NOT_SUPPORTED; + } + + color_find_predefined_gamut(&gamut->gamut, gamut_type); + gamut->white_point = color_white_point_type_6500k_noon; + color_find_predefined_white_point(&gamut->gamut, white_point_type_6500k_noon); + + return VPE_STATUS_OK; +} + +static bool build_gamut_remap_matrix(struct color_space_coordinates gamut_description, + struct fixed31_32 *rgb_matrix, struct fixed31_32 *white_point_matrix) +{ + struct fixed31_32 fixed_blueX = vpe_fixpt_from_fraction(gamut_description.blueX, DIVIDER); + struct fixed31_32 fixed_blueY = vpe_fixpt_from_fraction(gamut_description.blueY, DIVIDER); + struct fixed31_32 fixed_greenX = vpe_fixpt_from_fraction(gamut_description.greenX, DIVIDER); + struct fixed31_32 fixed_greenY = vpe_fixpt_from_fraction(gamut_description.greenY, DIVIDER); + struct fixed31_32 fixed_redX = vpe_fixpt_from_fraction(gamut_description.redX, DIVIDER); + struct fixed31_32 fixed_redY = vpe_fixpt_from_fraction(gamut_description.redY, DIVIDER); + struct fixed31_32 fixed_whiteX = vpe_fixpt_from_fraction(gamut_description.whiteX, DIVIDER); + struct fixed31_32 fixed_whiteY = vpe_fixpt_from_fraction(gamut_description.whiteY, DIVIDER); + + rgb_matrix[0] = vpe_fixpt_div(fixed_redX, fixed_redY); + rgb_matrix[1] = vpe_fixpt_one; + rgb_matrix[2] = vpe_fixpt_div( + vpe_fixpt_sub(vpe_fixpt_sub(vpe_fixpt_one, fixed_redX), fixed_redY), fixed_redY); + + rgb_matrix[3] = vpe_fixpt_div(fixed_greenX, fixed_greenY); + rgb_matrix[4] = vpe_fixpt_one; + rgb_matrix[5] = vpe_fixpt_div( + vpe_fixpt_sub(vpe_fixpt_sub(vpe_fixpt_one, fixed_greenX), fixed_greenY), fixed_greenY); + + rgb_matrix[6] = vpe_fixpt_div(fixed_blueX, fixed_blueY); + rgb_matrix[7] = vpe_fixpt_one; + rgb_matrix[8] = vpe_fixpt_div( + vpe_fixpt_sub(vpe_fixpt_sub(vpe_fixpt_one, fixed_blueX), fixed_blueY), fixed_blueY); + + white_point_matrix[0] = vpe_fixpt_div(fixed_whiteX, fixed_whiteY); + white_point_matrix[1] = vpe_fixpt_one; + white_point_matrix[2] = vpe_fixpt_div( + vpe_fixpt_sub(vpe_fixpt_sub(vpe_fixpt_one, fixed_whiteX), fixed_whiteY), fixed_whiteY); + + return true; +} + +static struct fixed31_32 find_3X3_det(const struct fixed31_32 *m) +{ + struct fixed31_32 det, A1, A2, A3; + + A1 = vpe_fixpt_mul(m[0], vpe_fixpt_sub(vpe_fixpt_mul(m[4], m[8]), vpe_fixpt_mul(m[5], m[7]))); + A2 = vpe_fixpt_mul(m[1], vpe_fixpt_sub(vpe_fixpt_mul(m[3], m[8]), vpe_fixpt_mul(m[5], m[6]))); + A3 = vpe_fixpt_mul(m[2], vpe_fixpt_sub(vpe_fixpt_mul(m[3], m[7]), vpe_fixpt_mul(m[4], m[6]))); + det = vpe_fixpt_add(vpe_fixpt_sub(A1, A2), A3); + return det; +} + +static bool compute_inverse_matrix_3x3(const struct fixed31_32 *m, struct fixed31_32 *im) +{ + struct fixed31_32 determinant = find_3X3_det(m); + + if (vpe_fixpt_eq(determinant, vpe_fixpt_zero) == false) { + im[0] = vpe_fixpt_div( + vpe_fixpt_sub(vpe_fixpt_mul(m[4], m[8]), vpe_fixpt_mul(m[5], m[7])), determinant); + im[1] = vpe_fixpt_neg(vpe_fixpt_div( + vpe_fixpt_sub(vpe_fixpt_mul(m[1], m[8]), vpe_fixpt_mul(m[2], m[7])), determinant)); + im[2] = vpe_fixpt_div( + vpe_fixpt_sub(vpe_fixpt_mul(m[1], m[5]), vpe_fixpt_mul(m[2], m[4])), determinant); + im[3] = vpe_fixpt_neg(vpe_fixpt_div( + vpe_fixpt_sub(vpe_fixpt_mul(m[3], m[8]), vpe_fixpt_mul(m[5], m[6])), determinant)); + im[4] = vpe_fixpt_div( + vpe_fixpt_sub(vpe_fixpt_mul(m[0], m[8]), vpe_fixpt_mul(m[2], m[6])), determinant); + im[5] = vpe_fixpt_neg(vpe_fixpt_div( + vpe_fixpt_sub(vpe_fixpt_mul(m[0], m[5]), vpe_fixpt_mul(m[2], m[3])), determinant)); + im[6] = vpe_fixpt_div( + vpe_fixpt_sub(vpe_fixpt_mul(m[3], m[7]), vpe_fixpt_mul(m[4], m[6])), determinant); + im[7] = vpe_fixpt_neg(vpe_fixpt_div( + vpe_fixpt_sub(vpe_fixpt_mul(m[0], m[7]), vpe_fixpt_mul(m[1], m[6])), determinant)); + im[8] = vpe_fixpt_div( + vpe_fixpt_sub(vpe_fixpt_mul(m[0], m[4]), vpe_fixpt_mul(m[1], m[3])), determinant); + return true; + } + return false; +} + +static bool calculate_XYZ_to_RGB_3x3(const struct fixed31_32 *XYZofRGB, + const struct fixed31_32 *XYZofWhite, struct fixed31_32 *XYZtoRGB) +{ + + struct fixed31_32 MInversed[9]; + struct fixed31_32 SVector[3]; + + /*1. Find Inverse matrix 3x3 of MTransposed*/ + if (!compute_inverse_matrix_3x3(XYZofRGB, MInversed)) + return false; + + /*2. Calculate vector: |Sr Sg Sb| = [MInversed] * |Wx Wy Wz|*/ + color_multiply_matrices(SVector, MInversed, XYZofWhite, 3, 3, 1); + + /*3. Calculate matrix XYZtoRGB 3x3*/ + XYZtoRGB[0] = vpe_fixpt_mul(XYZofRGB[0], SVector[0]); + XYZtoRGB[1] = vpe_fixpt_mul(XYZofRGB[1], SVector[1]); + XYZtoRGB[2] = vpe_fixpt_mul(XYZofRGB[2], SVector[2]); + + XYZtoRGB[3] = vpe_fixpt_mul(XYZofRGB[3], SVector[0]); + XYZtoRGB[4] = vpe_fixpt_mul(XYZofRGB[4], SVector[1]); + XYZtoRGB[5] = vpe_fixpt_mul(XYZofRGB[5], SVector[2]); + + XYZtoRGB[6] = vpe_fixpt_mul(XYZofRGB[6], SVector[0]); + XYZtoRGB[7] = vpe_fixpt_mul(XYZofRGB[7], SVector[1]); + XYZtoRGB[8] = vpe_fixpt_mul(XYZofRGB[8], SVector[2]); + + return true; +} + +static bool gamut_to_color_matrix(struct vpe_priv *vpe_priv, + const struct gamut_src_dst_matrix *matrices, bool invert, struct fixed31_32 *tempMatrix3X3, + struct fixed31_32 *tempOffset) +{ + int i = 0; + struct gamut_calculation_matrix *matrix = vpe_zalloc(sizeof(struct gamut_calculation_matrix)); + + const struct fixed31_32 *pXYZofRGB = matrices->rgbCoeffDst; /*destination gamut*/ + const struct fixed31_32 *pXYZofWhite = matrices->whiteCoeffDst; /*destination of white point*/ + const struct fixed31_32 *pRefXYZofRGB = matrices->rgbCoeffSrc; /*source gamut*/ + const struct fixed31_32 *pRefXYZofWhite = matrices->whiteCoeffSrc; /*source of white point*/ + const struct fixed31_32 *pColorTransformXYZ = matrices->xyzMatrix; /*additional XYZ->XYZ tfm*/ + const struct fixed31_32 *pColorTransformXYZOffset = matrices->xyzOffset; /*XYZ tfm offset*/ + const struct fixed31_32 *pBradford = matrices->bradford; /*Bradford chromatic adaptation*/ + + struct fixed31_32 *pXYZtoRGB_Temp; + struct fixed31_32 *pXYZtoRGB_Final; + + if (!matrix) + return false; + + matrix->fXYZofWhiteRef[0] = pRefXYZofWhite[0]; + matrix->fXYZofWhiteRef[1] = pRefXYZofWhite[1]; + matrix->fXYZofWhiteRef[2] = pRefXYZofWhite[2]; + + matrix->fXYZofRGBRef[0] = pRefXYZofRGB[0]; + matrix->fXYZofRGBRef[1] = pRefXYZofRGB[1]; + matrix->fXYZofRGBRef[2] = pRefXYZofRGB[2]; + + matrix->fXYZofRGBRef[3] = pRefXYZofRGB[3]; + matrix->fXYZofRGBRef[4] = pRefXYZofRGB[4]; + matrix->fXYZofRGBRef[5] = pRefXYZofRGB[5]; + + matrix->fXYZofRGBRef[6] = pRefXYZofRGB[6]; + matrix->fXYZofRGBRef[7] = pRefXYZofRGB[7]; + matrix->fXYZofRGBRef[8] = pRefXYZofRGB[8]; + + /*default values - unity matrix*/ + while (i < 9) { + if (i == 0 || i == 4 || i == 8) + tempMatrix3X3[i] = vpe_fixpt_one; + else + tempMatrix3X3[i] = vpe_fixpt_zero; + i++; + } + + /*1. Decide about the order of calculation. + * bInvert == FALSE --> RGBtoXYZ_Ref * XYZtoRGB_Custom + * bInvert == TRUE --> RGBtoXYZ_Custom * XYZtoRGB_Ref */ + if (invert) { + pXYZtoRGB_Temp = matrix->XYZtoRGB_Custom; + pXYZtoRGB_Final = matrix->XYZtoRGB_Ref; + } else { + pXYZtoRGB_Temp = matrix->XYZtoRGB_Ref; + pXYZtoRGB_Final = matrix->XYZtoRGB_Custom; + } + + /*2. Calculate XYZtoRGB_Ref*/ + color_transpose_matrix(matrix->fXYZofRGBRef, 3, 3, matrix->MTransposed); + + if (!calculate_XYZ_to_RGB_3x3( + matrix->MTransposed, matrix->fXYZofWhiteRef, matrix->XYZtoRGB_Ref)) + goto function_fail; + + /*3. Calculate XYZtoRGB_Custom*/ + color_transpose_matrix(pXYZofRGB, 3, 3, matrix->MTransposed); + + if (!calculate_XYZ_to_RGB_3x3(matrix->MTransposed, pXYZofWhite, matrix->XYZtoRGB_Custom)) + goto function_fail; + + /*4. Calculate RGBtoXYZ - + * inverse matrix 3x3 of XYZtoRGB_Ref or XYZtoRGB_Custom*/ + if (!compute_inverse_matrix_3x3(pXYZtoRGB_Temp, matrix->RGBtoXYZ_Final)) + goto function_fail; + + /* The naming is a bit confusing here (and earlier as well if you're + * trying to follow RP 177-1993...), so in short: + * S - source->XYZ + * D - dest->XYZ + * At this point: + * D^-1 = RGBtoXYZ_Final + * S = XYZtoRGB_Ref == pXYZtoRGB_Final + */ + + /*5. Calculate M(3x3) = RGBtoXYZ * XYZtoRGB*/ + color_multiply_matrices(matrix->MResult, matrix->RGBtoXYZ_Final, pXYZtoRGB_Final, 3, 3, 3); + + /*7. Calculate offsets */ + for (i = 0; i < 9; i++) + tempMatrix3X3[i] = matrix->MResult[i]; + + for (i = 0; i < 3; i++) + tempOffset[i] = vpe_fixpt_zero; + + vpe_free(matrix); + return true; + +function_fail: + vpe_free(matrix); + return false; +} + +static bool color_build_gamut_remap_matrix(struct vpe_priv *vpe_priv, + struct color_gamut_data *source_gamut, struct color_gamut_data *destination_gamut, + struct colorspace_transform *gamut_remap_matrix) +{ + struct gamut_src_dst_matrix *matrix = NULL; + struct fixed31_32 gamut_result[12]; + struct fixed31_32 temp_matrix[9]; + struct fixed31_32 temp_offset[3]; + int j; + + matrix = vpe_zalloc(sizeof(struct gamut_src_dst_matrix)); + if (matrix == NULL) + return false; + + build_gamut_remap_matrix(source_gamut->gamut, matrix->rgbCoeffSrc, matrix->whiteCoeffSrc); + build_gamut_remap_matrix(destination_gamut->gamut, matrix->rgbCoeffDst, matrix->whiteCoeffDst); + + if (!gamut_to_color_matrix(vpe_priv, matrix, true, temp_matrix, temp_offset)) + goto function_fail; + + gamut_result[0] = temp_matrix[0]; + gamut_result[1] = temp_matrix[1]; + gamut_result[2] = temp_matrix[2]; + gamut_result[4] = temp_matrix[3]; + gamut_result[5] = temp_matrix[4]; + gamut_result[6] = temp_matrix[5]; + gamut_result[8] = temp_matrix[6]; + gamut_result[9] = temp_matrix[7]; + gamut_result[10] = temp_matrix[8]; + + gamut_result[3] = temp_offset[0]; + gamut_result[7] = temp_offset[1]; + gamut_result[11] = temp_offset[2]; + + gamut_remap_matrix->enable_remap = true; + + for (j = 0; j < 12; j++) + gamut_remap_matrix->matrix[j] = gamut_result[j]; + + vpe_free(matrix); + return true; + +function_fail: + vpe_free(matrix); + vpe_log("err: build gamut remap fails!\n"); + return false; +} + +enum vpe_status vpe_color_update_gamut(struct vpe_priv *vpe_priv, enum color_space in_color, + enum color_space outColor, struct colorspace_transform *gamut_remap, bool bypass_remap) +{ + struct output_ctx *output_ctx = &vpe_priv->output_ctx; + struct color_gamut_data src_gamut; + struct color_gamut_data dst_gamut; + enum vpe_status status; + + if (bypass_remap || in_color == outColor) { + gamut_remap->enable_remap = false; + return VPE_STATUS_OK; + } + + status = find_predefined_gamut_and_white_point(vpe_priv, &src_gamut, in_color); + if (status != VPE_STATUS_OK) + return status; + + status = find_predefined_gamut_and_white_point(vpe_priv, &dst_gamut, outColor); + if (status != VPE_STATUS_OK) + return status; + + if (!color_build_gamut_remap_matrix(vpe_priv, &src_gamut, &dst_gamut, gamut_remap)) { + vpe_log("err: build gamut remap failure!"); + VPE_ASSERT(0); + return VPE_STATUS_ERROR; + } + + return VPE_STATUS_OK; +} diff --git a/src/amd/vpelib/src/core/color_table.c b/src/amd/vpelib/src/core/color_table.c new file mode 100644 index 00000000000..3c4e3309e56 --- /dev/null +++ b/src/amd/vpelib/src/core/color_table.c @@ -0,0 +1,64 @@ + +/* Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include "color_table.h" +#include "fixed31_32.h" + +static struct fixed31_32 pq_table[MAX_HW_POINTS + 2]; +static struct fixed31_32 de_pq_table[MAX_HW_POINTS + 2]; +static bool pq_initialized = false; +static bool de_pg_initialized = false; + +bool vpe_color_is_table_init(enum table_type type) +{ + bool ret = false; + + if (type == type_pq_table) + ret = pq_initialized; + if (type == type_de_pq_table) + ret = de_pg_initialized; + + return ret; +} + +struct fixed31_32 *vpe_color_get_table(enum table_type type) +{ + struct fixed31_32 *table = NULL; + + if (type == type_pq_table) + table = pq_table; + if (type == type_de_pq_table) + table = de_pq_table; + + return table; +} + +void vpe_color_set_table_init_state(enum table_type type, bool state) +{ + if (type == type_pq_table) + pq_initialized = state; + if (type == type_de_pq_table) + de_pg_initialized = state; +} diff --git a/src/amd/vpelib/src/core/color_test_values.c b/src/amd/vpelib/src/core/color_test_values.c new file mode 100644 index 00000000000..235ca5dc97a --- /dev/null +++ b/src/amd/vpelib/src/core/color_test_values.c @@ -0,0 +1,7092 @@ + +/* Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include "color_test_values.h" + +// facilitate fpga testing with test 3d lut values + +static const struct fixed31_32 hdr_mult_sdr = {281474976710656}; // 2^16 + +bool build_test_shaper_sdr(struct transfer_func *shaper) +{ + if (shaper == NULL) + return false; + + memset(shaper, 0, sizeof(struct transfer_func)); + + shaper->type = TF_TYPE_HWPWL; + shaper->tf = + TRANSFER_FUNC_SRGB; // it's 2.2, but no such type - we use PWL values, so irrelevant + shaper->sdr_ref_white_level = 80; + shaper->pwl.hw_points_num = 256; + + shaper->pwl.arr_curve_points[0].offset = 0; + shaper->pwl.arr_curve_points[0].segments_num = 0; + shaper->pwl.arr_curve_points[1].offset = 1; + shaper->pwl.arr_curve_points[1].segments_num = 0; + shaper->pwl.arr_curve_points[2].offset = 2; + shaper->pwl.arr_curve_points[2].segments_num = 0; + shaper->pwl.arr_curve_points[3].offset = 3; + shaper->pwl.arr_curve_points[3].segments_num = 0; + shaper->pwl.arr_curve_points[4].offset = 4; + shaper->pwl.arr_curve_points[4].segments_num = 0; + shaper->pwl.arr_curve_points[5].offset = 5; + shaper->pwl.arr_curve_points[5].segments_num = 0; + shaper->pwl.arr_curve_points[6].offset = 6; + shaper->pwl.arr_curve_points[6].segments_num = 0; + shaper->pwl.arr_curve_points[7].offset = 7; + shaper->pwl.arr_curve_points[7].segments_num = 0; + shaper->pwl.arr_curve_points[8].offset = 8; + shaper->pwl.arr_curve_points[8].segments_num = 0; + shaper->pwl.arr_curve_points[9].offset = 9; + shaper->pwl.arr_curve_points[9].segments_num = 0; + shaper->pwl.arr_curve_points[10].offset = 10; + shaper->pwl.arr_curve_points[10].segments_num = 0; + shaper->pwl.arr_curve_points[11].offset = 11; + shaper->pwl.arr_curve_points[11].segments_num = 0; + shaper->pwl.arr_curve_points[12].offset = 12; + shaper->pwl.arr_curve_points[12].segments_num = 0; + shaper->pwl.arr_curve_points[13].offset = 13; + shaper->pwl.arr_curve_points[13].segments_num = 0; + shaper->pwl.arr_curve_points[14].offset = 14; + shaper->pwl.arr_curve_points[14].segments_num = 0; + shaper->pwl.arr_curve_points[15].offset = 15; + shaper->pwl.arr_curve_points[15].segments_num = 0; + shaper->pwl.arr_curve_points[16].offset = 16; + shaper->pwl.arr_curve_points[16].segments_num = 0; + shaper->pwl.arr_curve_points[17].offset = 17; + shaper->pwl.arr_curve_points[17].segments_num = 0; + shaper->pwl.arr_curve_points[18].offset = 18; + shaper->pwl.arr_curve_points[18].segments_num = 1; + shaper->pwl.arr_curve_points[19].offset = 20; + shaper->pwl.arr_curve_points[19].segments_num = 1; + shaper->pwl.arr_curve_points[20].offset = 22; + shaper->pwl.arr_curve_points[20].segments_num = 1; + shaper->pwl.arr_curve_points[21].offset = 24; + shaper->pwl.arr_curve_points[21].segments_num = 2; + shaper->pwl.arr_curve_points[22].offset = 28; + shaper->pwl.arr_curve_points[22].segments_num = 2; + shaper->pwl.arr_curve_points[23].offset = 32; + shaper->pwl.arr_curve_points[23].segments_num = 3; + shaper->pwl.arr_curve_points[24].offset = 40; + shaper->pwl.arr_curve_points[24].segments_num = 3; + shaper->pwl.arr_curve_points[25].offset = 48; + shaper->pwl.arr_curve_points[25].segments_num = 4; + shaper->pwl.arr_curve_points[26].offset = 64; + shaper->pwl.arr_curve_points[26].segments_num = 4; + shaper->pwl.arr_curve_points[27].offset = 80; + shaper->pwl.arr_curve_points[27].segments_num = 4; + shaper->pwl.arr_curve_points[28].offset = 96; + shaper->pwl.arr_curve_points[28].segments_num = 4; + shaper->pwl.arr_curve_points[29].offset = 112; + shaper->pwl.arr_curve_points[29].segments_num = 4; + shaper->pwl.arr_curve_points[30].offset = 128; + shaper->pwl.arr_curve_points[30].segments_num = 5; + shaper->pwl.arr_curve_points[31].offset = 160; + shaper->pwl.arr_curve_points[31].segments_num = 5; + shaper->pwl.arr_curve_points[32].offset = 192; + shaper->pwl.arr_curve_points[32].segments_num = 5; + shaper->pwl.arr_curve_points[33].offset = 224; + shaper->pwl.arr_curve_points[33].segments_num = 5; + + shaper->pwl.arr_points[0].x.value = 0; + shaper->pwl.arr_points[0].y.value = 0; + shaper->pwl.arr_points[0].offset.value = 0; + shaper->pwl.arr_points[0].slope.value = 0; + shaper->pwl.arr_points[0].custom_float_x = 57344; + shaper->pwl.arr_points[0].custom_float_y = 0; + shaper->pwl.arr_points[0].custom_float_offset = 0; + shaper->pwl.arr_points[0].custom_float_slope = 0; + shaper->pwl.arr_points[1].x.value = 0; + shaper->pwl.arr_points[1].y.value = 0; + shaper->pwl.arr_points[1].offset.value = 0; + shaper->pwl.arr_points[1].slope.value = 0; + shaper->pwl.arr_points[1].custom_float_x = 57344; + shaper->pwl.arr_points[1].custom_float_y = 0; + shaper->pwl.arr_points[1].custom_float_offset = 0; + shaper->pwl.arr_points[1].custom_float_slope = 0; + + shaper->pwl.corner_points[0].red.custom_float_x = 57344; + shaper->pwl.corner_points[0].green.custom_float_x = 57344; + shaper->pwl.corner_points[0].blue.custom_float_x = 57344; + shaper->pwl.corner_points[0].red.custom_float_y = 0; + shaper->pwl.corner_points[0].green.custom_float_y = 0; + shaper->pwl.corner_points[0].blue.custom_float_y = 0; + shaper->pwl.corner_points[1].red.custom_float_x = 48128; + shaper->pwl.corner_points[1].green.custom_float_x = 48128; + shaper->pwl.corner_points[1].blue.custom_float_x = 48128; + shaper->pwl.corner_points[1].red.custom_float_y = 16383; + shaper->pwl.corner_points[1].green.custom_float_y = 16383; + shaper->pwl.corner_points[1].blue.custom_float_y = 16383; + + shaper->pwl.rgb_resulted[0].red_reg = 0; + shaper->pwl.rgb_resulted[0].green_reg = 0; + shaper->pwl.rgb_resulted[0].blue_reg = 0; + shaper->pwl.rgb_resulted[0].delta_red_reg = 1; + shaper->pwl.rgb_resulted[0].delta_green_reg = 1; + shaper->pwl.rgb_resulted[0].delta_blue_reg = 1; + shaper->pwl.rgb_resulted[1].red_reg = 1; + shaper->pwl.rgb_resulted[1].green_reg = 1; + shaper->pwl.rgb_resulted[1].blue_reg = 1; + shaper->pwl.rgb_resulted[1].delta_red_reg = 0; + shaper->pwl.rgb_resulted[1].delta_green_reg = 0; + shaper->pwl.rgb_resulted[1].delta_blue_reg = 0; + shaper->pwl.rgb_resulted[2].red_reg = 1; + shaper->pwl.rgb_resulted[2].green_reg = 1; + shaper->pwl.rgb_resulted[2].blue_reg = 1; + shaper->pwl.rgb_resulted[2].delta_red_reg = 0; + shaper->pwl.rgb_resulted[2].delta_green_reg = 0; + shaper->pwl.rgb_resulted[2].delta_blue_reg = 0; + shaper->pwl.rgb_resulted[3].red_reg = 1; + shaper->pwl.rgb_resulted[3].green_reg = 1; + shaper->pwl.rgb_resulted[3].blue_reg = 1; + shaper->pwl.rgb_resulted[3].delta_red_reg = 1; + shaper->pwl.rgb_resulted[3].delta_green_reg = 1; + shaper->pwl.rgb_resulted[3].delta_blue_reg = 1; + shaper->pwl.rgb_resulted[4].red_reg = 2; + shaper->pwl.rgb_resulted[4].green_reg = 2; + shaper->pwl.rgb_resulted[4].blue_reg = 2; + shaper->pwl.rgb_resulted[4].delta_red_reg = 0; + shaper->pwl.rgb_resulted[4].delta_green_reg = 0; + shaper->pwl.rgb_resulted[4].delta_blue_reg = 0; + shaper->pwl.rgb_resulted[5].red_reg = 2; + shaper->pwl.rgb_resulted[5].green_reg = 2; + shaper->pwl.rgb_resulted[5].blue_reg = 2; + shaper->pwl.rgb_resulted[5].delta_red_reg = 1; + shaper->pwl.rgb_resulted[5].delta_green_reg = 1; + shaper->pwl.rgb_resulted[5].delta_blue_reg = 1; + shaper->pwl.rgb_resulted[6].red_reg = 3; + shaper->pwl.rgb_resulted[6].green_reg = 3; + shaper->pwl.rgb_resulted[6].blue_reg = 3; + shaper->pwl.rgb_resulted[6].delta_red_reg = 2; + shaper->pwl.rgb_resulted[6].delta_green_reg = 2; + shaper->pwl.rgb_resulted[6].delta_blue_reg = 2; + shaper->pwl.rgb_resulted[7].red_reg = 5; + shaper->pwl.rgb_resulted[7].green_reg = 5; + shaper->pwl.rgb_resulted[7].blue_reg = 5; + shaper->pwl.rgb_resulted[7].delta_red_reg = 1; + shaper->pwl.rgb_resulted[7].delta_green_reg = 1; + shaper->pwl.rgb_resulted[7].delta_blue_reg = 1; + shaper->pwl.rgb_resulted[8].red_reg = 6; + shaper->pwl.rgb_resulted[8].green_reg = 6; + shaper->pwl.rgb_resulted[8].blue_reg = 6; + shaper->pwl.rgb_resulted[8].delta_red_reg = 3; + shaper->pwl.rgb_resulted[8].delta_green_reg = 3; + shaper->pwl.rgb_resulted[8].delta_blue_reg = 3; + shaper->pwl.rgb_resulted[9].red_reg = 9; + shaper->pwl.rgb_resulted[9].green_reg = 9; + shaper->pwl.rgb_resulted[9].blue_reg = 9; + shaper->pwl.rgb_resulted[9].delta_red_reg = 3; + shaper->pwl.rgb_resulted[9].delta_green_reg = 3; + shaper->pwl.rgb_resulted[9].delta_blue_reg = 3; + shaper->pwl.rgb_resulted[10].red_reg = 12; + shaper->pwl.rgb_resulted[10].green_reg = 12; + shaper->pwl.rgb_resulted[10].blue_reg = 12; + shaper->pwl.rgb_resulted[10].delta_red_reg = 4; + shaper->pwl.rgb_resulted[10].delta_green_reg = 4; + shaper->pwl.rgb_resulted[10].delta_blue_reg = 4; + shaper->pwl.rgb_resulted[11].red_reg = 16; + shaper->pwl.rgb_resulted[11].green_reg = 16; + shaper->pwl.rgb_resulted[11].blue_reg = 16; + shaper->pwl.rgb_resulted[11].delta_red_reg = 6; + shaper->pwl.rgb_resulted[11].delta_green_reg = 6; + shaper->pwl.rgb_resulted[11].delta_blue_reg = 6; + shaper->pwl.rgb_resulted[12].red_reg = 22; + shaper->pwl.rgb_resulted[12].green_reg = 22; + shaper->pwl.rgb_resulted[12].blue_reg = 22; + shaper->pwl.rgb_resulted[12].delta_red_reg = 8; + shaper->pwl.rgb_resulted[12].delta_green_reg = 8; + shaper->pwl.rgb_resulted[12].delta_blue_reg = 8; + shaper->pwl.rgb_resulted[13].red_reg = 30; + shaper->pwl.rgb_resulted[13].green_reg = 30; + shaper->pwl.rgb_resulted[13].blue_reg = 30; + shaper->pwl.rgb_resulted[13].delta_red_reg = 11; + shaper->pwl.rgb_resulted[13].delta_green_reg = 11; + shaper->pwl.rgb_resulted[13].delta_blue_reg = 11; + shaper->pwl.rgb_resulted[14].red_reg = 41; + shaper->pwl.rgb_resulted[14].green_reg = 41; + shaper->pwl.rgb_resulted[14].blue_reg = 41; + shaper->pwl.rgb_resulted[14].delta_red_reg = 15; + shaper->pwl.rgb_resulted[14].delta_green_reg = 15; + shaper->pwl.rgb_resulted[14].delta_blue_reg = 15; + shaper->pwl.rgb_resulted[15].red_reg = 56; + shaper->pwl.rgb_resulted[15].green_reg = 56; + shaper->pwl.rgb_resulted[15].blue_reg = 56; + shaper->pwl.rgb_resulted[15].delta_red_reg = 21; + shaper->pwl.rgb_resulted[15].delta_green_reg = 21; + shaper->pwl.rgb_resulted[15].delta_blue_reg = 21; + shaper->pwl.rgb_resulted[16].red_reg = 77; + shaper->pwl.rgb_resulted[16].green_reg = 77; + shaper->pwl.rgb_resulted[16].blue_reg = 77; + shaper->pwl.rgb_resulted[16].delta_red_reg = 29; + shaper->pwl.rgb_resulted[16].delta_green_reg = 29; + shaper->pwl.rgb_resulted[16].delta_blue_reg = 29; + shaper->pwl.rgb_resulted[17].red_reg = 106; + shaper->pwl.rgb_resulted[17].green_reg = 106; + shaper->pwl.rgb_resulted[17].blue_reg = 106; + shaper->pwl.rgb_resulted[17].delta_red_reg = 39; + shaper->pwl.rgb_resulted[17].delta_green_reg = 39; + shaper->pwl.rgb_resulted[17].delta_blue_reg = 39; + shaper->pwl.rgb_resulted[18].red_reg = 145; + shaper->pwl.rgb_resulted[18].green_reg = 145; + shaper->pwl.rgb_resulted[18].blue_reg = 145; + shaper->pwl.rgb_resulted[18].delta_red_reg = 30; + shaper->pwl.rgb_resulted[18].delta_green_reg = 30; + shaper->pwl.rgb_resulted[18].delta_blue_reg = 30; + shaper->pwl.rgb_resulted[19].red_reg = 175; + shaper->pwl.rgb_resulted[19].green_reg = 175; + shaper->pwl.rgb_resulted[19].blue_reg = 175; + shaper->pwl.rgb_resulted[19].delta_red_reg = 24; + shaper->pwl.rgb_resulted[19].delta_green_reg = 24; + shaper->pwl.rgb_resulted[19].delta_blue_reg = 24; + shaper->pwl.rgb_resulted[20].red_reg = 199; + shaper->pwl.rgb_resulted[20].green_reg = 199; + shaper->pwl.rgb_resulted[20].blue_reg = 199; + shaper->pwl.rgb_resulted[20].delta_red_reg = 40; + shaper->pwl.rgb_resulted[20].delta_green_reg = 40; + shaper->pwl.rgb_resulted[20].delta_blue_reg = 40; + shaper->pwl.rgb_resulted[21].red_reg = 239; + shaper->pwl.rgb_resulted[21].green_reg = 239; + shaper->pwl.rgb_resulted[21].blue_reg = 239; + shaper->pwl.rgb_resulted[21].delta_red_reg = 34; + shaper->pwl.rgb_resulted[21].delta_green_reg = 34; + shaper->pwl.rgb_resulted[21].delta_blue_reg = 34; + shaper->pwl.rgb_resulted[22].red_reg = 273; + shaper->pwl.rgb_resulted[22].green_reg = 273; + shaper->pwl.rgb_resulted[22].blue_reg = 273; + shaper->pwl.rgb_resulted[22].delta_red_reg = 55; + shaper->pwl.rgb_resulted[22].delta_green_reg = 55; + shaper->pwl.rgb_resulted[22].delta_blue_reg = 55; + shaper->pwl.rgb_resulted[23].red_reg = 328; + shaper->pwl.rgb_resulted[23].green_reg = 328; + shaper->pwl.rgb_resulted[23].blue_reg = 328; + shaper->pwl.rgb_resulted[23].delta_red_reg = 46; + shaper->pwl.rgb_resulted[23].delta_green_reg = 46; + shaper->pwl.rgb_resulted[23].delta_blue_reg = 46; + shaper->pwl.rgb_resulted[24].red_reg = 374; + shaper->pwl.rgb_resulted[24].green_reg = 374; + shaper->pwl.rgb_resulted[24].blue_reg = 374; + shaper->pwl.rgb_resulted[24].delta_red_reg = 39; + shaper->pwl.rgb_resulted[24].delta_green_reg = 39; + shaper->pwl.rgb_resulted[24].delta_blue_reg = 39; + shaper->pwl.rgb_resulted[25].red_reg = 413; + shaper->pwl.rgb_resulted[25].green_reg = 413; + shaper->pwl.rgb_resulted[25].blue_reg = 413; + shaper->pwl.rgb_resulted[25].delta_red_reg = 36; + shaper->pwl.rgb_resulted[25].delta_green_reg = 36; + shaper->pwl.rgb_resulted[25].delta_blue_reg = 36; + shaper->pwl.rgb_resulted[26].red_reg = 449; + shaper->pwl.rgb_resulted[26].green_reg = 449; + shaper->pwl.rgb_resulted[26].blue_reg = 449; + shaper->pwl.rgb_resulted[26].delta_red_reg = 33; + shaper->pwl.rgb_resulted[26].delta_green_reg = 33; + shaper->pwl.rgb_resulted[26].delta_blue_reg = 33; + shaper->pwl.rgb_resulted[27].red_reg = 482; + shaper->pwl.rgb_resulted[27].green_reg = 482; + shaper->pwl.rgb_resulted[27].blue_reg = 482; + shaper->pwl.rgb_resulted[27].delta_red_reg = 30; + shaper->pwl.rgb_resulted[27].delta_green_reg = 30; + shaper->pwl.rgb_resulted[27].delta_blue_reg = 30; + shaper->pwl.rgb_resulted[28].red_reg = 512; + shaper->pwl.rgb_resulted[28].green_reg = 512; + shaper->pwl.rgb_resulted[28].blue_reg = 512; + shaper->pwl.rgb_resulted[28].delta_red_reg = 55; + shaper->pwl.rgb_resulted[28].delta_green_reg = 55; + shaper->pwl.rgb_resulted[28].delta_blue_reg = 55; + shaper->pwl.rgb_resulted[29].red_reg = 567; + shaper->pwl.rgb_resulted[29].green_reg = 567; + shaper->pwl.rgb_resulted[29].blue_reg = 567; + shaper->pwl.rgb_resulted[29].delta_red_reg = 49; + shaper->pwl.rgb_resulted[29].delta_green_reg = 49; + shaper->pwl.rgb_resulted[29].delta_blue_reg = 49; + shaper->pwl.rgb_resulted[30].red_reg = 616; + shaper->pwl.rgb_resulted[30].green_reg = 616; + shaper->pwl.rgb_resulted[30].blue_reg = 616; + shaper->pwl.rgb_resulted[30].delta_red_reg = 44; + shaper->pwl.rgb_resulted[30].delta_green_reg = 44; + shaper->pwl.rgb_resulted[30].delta_blue_reg = 44; + shaper->pwl.rgb_resulted[31].red_reg = 660; + shaper->pwl.rgb_resulted[31].green_reg = 660; + shaper->pwl.rgb_resulted[31].blue_reg = 660; + shaper->pwl.rgb_resulted[31].delta_red_reg = 42; + shaper->pwl.rgb_resulted[31].delta_green_reg = 42; + shaper->pwl.rgb_resulted[31].delta_blue_reg = 42; + shaper->pwl.rgb_resulted[32].red_reg = 702; + shaper->pwl.rgb_resulted[32].green_reg = 702; + shaper->pwl.rgb_resulted[32].blue_reg = 702; + shaper->pwl.rgb_resulted[32].delta_red_reg = 38; + shaper->pwl.rgb_resulted[32].delta_green_reg = 38; + shaper->pwl.rgb_resulted[32].delta_blue_reg = 38; + shaper->pwl.rgb_resulted[33].red_reg = 740; + shaper->pwl.rgb_resulted[33].green_reg = 740; + shaper->pwl.rgb_resulted[33].blue_reg = 740; + shaper->pwl.rgb_resulted[33].delta_red_reg = 36; + shaper->pwl.rgb_resulted[33].delta_green_reg = 36; + shaper->pwl.rgb_resulted[33].delta_blue_reg = 36; + shaper->pwl.rgb_resulted[34].red_reg = 776; + shaper->pwl.rgb_resulted[34].green_reg = 776; + shaper->pwl.rgb_resulted[34].blue_reg = 776; + shaper->pwl.rgb_resulted[34].delta_red_reg = 35; + shaper->pwl.rgb_resulted[34].delta_green_reg = 35; + shaper->pwl.rgb_resulted[34].delta_blue_reg = 35; + shaper->pwl.rgb_resulted[35].red_reg = 811; + shaper->pwl.rgb_resulted[35].green_reg = 811; + shaper->pwl.rgb_resulted[35].blue_reg = 811; + shaper->pwl.rgb_resulted[35].delta_red_reg = 33; + shaper->pwl.rgb_resulted[35].delta_green_reg = 33; + shaper->pwl.rgb_resulted[35].delta_blue_reg = 33; + shaper->pwl.rgb_resulted[36].red_reg = 844; + shaper->pwl.rgb_resulted[36].green_reg = 844; + shaper->pwl.rgb_resulted[36].blue_reg = 844; + shaper->pwl.rgb_resulted[36].delta_red_reg = 31; + shaper->pwl.rgb_resulted[36].delta_green_reg = 31; + shaper->pwl.rgb_resulted[36].delta_blue_reg = 31; + shaper->pwl.rgb_resulted[37].red_reg = 875; + shaper->pwl.rgb_resulted[37].green_reg = 875; + shaper->pwl.rgb_resulted[37].blue_reg = 875; + shaper->pwl.rgb_resulted[37].delta_red_reg = 30; + shaper->pwl.rgb_resulted[37].delta_green_reg = 30; + shaper->pwl.rgb_resulted[37].delta_blue_reg = 30; + shaper->pwl.rgb_resulted[38].red_reg = 905; + shaper->pwl.rgb_resulted[38].green_reg = 905; + shaper->pwl.rgb_resulted[38].blue_reg = 905; + shaper->pwl.rgb_resulted[38].delta_red_reg = 29; + shaper->pwl.rgb_resulted[38].delta_green_reg = 29; + shaper->pwl.rgb_resulted[38].delta_blue_reg = 29; + shaper->pwl.rgb_resulted[39].red_reg = 934; + shaper->pwl.rgb_resulted[39].green_reg = 934; + shaper->pwl.rgb_resulted[39].blue_reg = 934; + shaper->pwl.rgb_resulted[39].delta_red_reg = 27; + shaper->pwl.rgb_resulted[39].delta_green_reg = 27; + shaper->pwl.rgb_resulted[39].delta_blue_reg = 27; + shaper->pwl.rgb_resulted[40].red_reg = 961; + shaper->pwl.rgb_resulted[40].green_reg = 961; + shaper->pwl.rgb_resulted[40].blue_reg = 961; + shaper->pwl.rgb_resulted[40].delta_red_reg = 53; + shaper->pwl.rgb_resulted[40].delta_green_reg = 53; + shaper->pwl.rgb_resulted[40].delta_blue_reg = 53; + shaper->pwl.rgb_resulted[41].red_reg = 1014; + shaper->pwl.rgb_resulted[41].green_reg = 1014; + shaper->pwl.rgb_resulted[41].blue_reg = 1014; + shaper->pwl.rgb_resulted[41].delta_red_reg = 50; + shaper->pwl.rgb_resulted[41].delta_green_reg = 50; + shaper->pwl.rgb_resulted[41].delta_blue_reg = 50; + shaper->pwl.rgb_resulted[42].red_reg = 1064; + shaper->pwl.rgb_resulted[42].green_reg = 1064; + shaper->pwl.rgb_resulted[42].blue_reg = 1064; + shaper->pwl.rgb_resulted[42].delta_red_reg = 47; + shaper->pwl.rgb_resulted[42].delta_green_reg = 47; + shaper->pwl.rgb_resulted[42].delta_blue_reg = 47; + shaper->pwl.rgb_resulted[43].red_reg = 1111; + shaper->pwl.rgb_resulted[43].green_reg = 1111; + shaper->pwl.rgb_resulted[43].blue_reg = 1111; + shaper->pwl.rgb_resulted[43].delta_red_reg = 45; + shaper->pwl.rgb_resulted[43].delta_green_reg = 45; + shaper->pwl.rgb_resulted[43].delta_blue_reg = 45; + shaper->pwl.rgb_resulted[44].red_reg = 1156; + shaper->pwl.rgb_resulted[44].green_reg = 1156; + shaper->pwl.rgb_resulted[44].blue_reg = 1156; + shaper->pwl.rgb_resulted[44].delta_red_reg = 43; + shaper->pwl.rgb_resulted[44].delta_green_reg = 43; + shaper->pwl.rgb_resulted[44].delta_blue_reg = 43; + shaper->pwl.rgb_resulted[45].red_reg = 1199; + shaper->pwl.rgb_resulted[45].green_reg = 1199; + shaper->pwl.rgb_resulted[45].blue_reg = 1199; + shaper->pwl.rgb_resulted[45].delta_red_reg = 41; + shaper->pwl.rgb_resulted[45].delta_green_reg = 41; + shaper->pwl.rgb_resulted[45].delta_blue_reg = 41; + shaper->pwl.rgb_resulted[46].red_reg = 1240; + shaper->pwl.rgb_resulted[46].green_reg = 1240; + shaper->pwl.rgb_resulted[46].blue_reg = 1240; + shaper->pwl.rgb_resulted[46].delta_red_reg = 39; + shaper->pwl.rgb_resulted[46].delta_green_reg = 39; + shaper->pwl.rgb_resulted[46].delta_blue_reg = 39; + shaper->pwl.rgb_resulted[47].red_reg = 1279; + shaper->pwl.rgb_resulted[47].green_reg = 1279; + shaper->pwl.rgb_resulted[47].blue_reg = 1279; + shaper->pwl.rgb_resulted[47].delta_red_reg = 38; + shaper->pwl.rgb_resulted[47].delta_green_reg = 38; + shaper->pwl.rgb_resulted[47].delta_blue_reg = 38; + shaper->pwl.rgb_resulted[48].red_reg = 1317; + shaper->pwl.rgb_resulted[48].green_reg = 1317; + shaper->pwl.rgb_resulted[48].blue_reg = 1317; + shaper->pwl.rgb_resulted[48].delta_red_reg = 37; + shaper->pwl.rgb_resulted[48].delta_green_reg = 37; + shaper->pwl.rgb_resulted[48].delta_blue_reg = 37; + shaper->pwl.rgb_resulted[49].red_reg = 1354; + shaper->pwl.rgb_resulted[49].green_reg = 1354; + shaper->pwl.rgb_resulted[49].blue_reg = 1354; + shaper->pwl.rgb_resulted[49].delta_red_reg = 36; + shaper->pwl.rgb_resulted[49].delta_green_reg = 36; + shaper->pwl.rgb_resulted[49].delta_blue_reg = 36; + shaper->pwl.rgb_resulted[50].red_reg = 1390; + shaper->pwl.rgb_resulted[50].green_reg = 1390; + shaper->pwl.rgb_resulted[50].blue_reg = 1390; + shaper->pwl.rgb_resulted[50].delta_red_reg = 35; + shaper->pwl.rgb_resulted[50].delta_green_reg = 35; + shaper->pwl.rgb_resulted[50].delta_blue_reg = 35; + shaper->pwl.rgb_resulted[51].red_reg = 1425; + shaper->pwl.rgb_resulted[51].green_reg = 1425; + shaper->pwl.rgb_resulted[51].blue_reg = 1425; + shaper->pwl.rgb_resulted[51].delta_red_reg = 33; + shaper->pwl.rgb_resulted[51].delta_green_reg = 33; + shaper->pwl.rgb_resulted[51].delta_blue_reg = 33; + shaper->pwl.rgb_resulted[52].red_reg = 1458; + shaper->pwl.rgb_resulted[52].green_reg = 1458; + shaper->pwl.rgb_resulted[52].blue_reg = 1458; + shaper->pwl.rgb_resulted[52].delta_red_reg = 33; + shaper->pwl.rgb_resulted[52].delta_green_reg = 33; + shaper->pwl.rgb_resulted[52].delta_blue_reg = 33; + shaper->pwl.rgb_resulted[53].red_reg = 1491; + shaper->pwl.rgb_resulted[53].green_reg = 1491; + shaper->pwl.rgb_resulted[53].blue_reg = 1491; + shaper->pwl.rgb_resulted[53].delta_red_reg = 32; + shaper->pwl.rgb_resulted[53].delta_green_reg = 32; + shaper->pwl.rgb_resulted[53].delta_blue_reg = 32; + shaper->pwl.rgb_resulted[54].red_reg = 1523; + shaper->pwl.rgb_resulted[54].green_reg = 1523; + shaper->pwl.rgb_resulted[54].blue_reg = 1523; + shaper->pwl.rgb_resulted[54].delta_red_reg = 31; + shaper->pwl.rgb_resulted[54].delta_green_reg = 31; + shaper->pwl.rgb_resulted[54].delta_blue_reg = 31; + shaper->pwl.rgb_resulted[55].red_reg = 1554; + shaper->pwl.rgb_resulted[55].green_reg = 1554; + shaper->pwl.rgb_resulted[55].blue_reg = 1554; + shaper->pwl.rgb_resulted[55].delta_red_reg = 30; + shaper->pwl.rgb_resulted[55].delta_green_reg = 30; + shaper->pwl.rgb_resulted[55].delta_blue_reg = 30; + shaper->pwl.rgb_resulted[56].red_reg = 1584; + shaper->pwl.rgb_resulted[56].green_reg = 1584; + shaper->pwl.rgb_resulted[56].blue_reg = 1584; + shaper->pwl.rgb_resulted[56].delta_red_reg = 30; + shaper->pwl.rgb_resulted[56].delta_green_reg = 30; + shaper->pwl.rgb_resulted[56].delta_blue_reg = 30; + shaper->pwl.rgb_resulted[57].red_reg = 1614; + shaper->pwl.rgb_resulted[57].green_reg = 1614; + shaper->pwl.rgb_resulted[57].blue_reg = 1614; + shaper->pwl.rgb_resulted[57].delta_red_reg = 29; + shaper->pwl.rgb_resulted[57].delta_green_reg = 29; + shaper->pwl.rgb_resulted[57].delta_blue_reg = 29; + shaper->pwl.rgb_resulted[58].red_reg = 1643; + shaper->pwl.rgb_resulted[58].green_reg = 1643; + shaper->pwl.rgb_resulted[58].blue_reg = 1643; + shaper->pwl.rgb_resulted[58].delta_red_reg = 28; + shaper->pwl.rgb_resulted[58].delta_green_reg = 28; + shaper->pwl.rgb_resulted[58].delta_blue_reg = 28; + shaper->pwl.rgb_resulted[59].red_reg = 1671; + shaper->pwl.rgb_resulted[59].green_reg = 1671; + shaper->pwl.rgb_resulted[59].blue_reg = 1671; + shaper->pwl.rgb_resulted[59].delta_red_reg = 28; + shaper->pwl.rgb_resulted[59].delta_green_reg = 28; + shaper->pwl.rgb_resulted[59].delta_blue_reg = 28; + shaper->pwl.rgb_resulted[60].red_reg = 1699; + shaper->pwl.rgb_resulted[60].green_reg = 1699; + shaper->pwl.rgb_resulted[60].blue_reg = 1699; + shaper->pwl.rgb_resulted[60].delta_red_reg = 27; + shaper->pwl.rgb_resulted[60].delta_green_reg = 27; + shaper->pwl.rgb_resulted[60].delta_blue_reg = 27; + shaper->pwl.rgb_resulted[61].red_reg = 1726; + shaper->pwl.rgb_resulted[61].green_reg = 1726; + shaper->pwl.rgb_resulted[61].blue_reg = 1726; + shaper->pwl.rgb_resulted[61].delta_red_reg = 27; + shaper->pwl.rgb_resulted[61].delta_green_reg = 27; + shaper->pwl.rgb_resulted[61].delta_blue_reg = 27; + shaper->pwl.rgb_resulted[62].red_reg = 1753; + shaper->pwl.rgb_resulted[62].green_reg = 1753; + shaper->pwl.rgb_resulted[62].blue_reg = 1753; + shaper->pwl.rgb_resulted[62].delta_red_reg = 27; + shaper->pwl.rgb_resulted[62].delta_green_reg = 27; + shaper->pwl.rgb_resulted[62].delta_blue_reg = 27; + shaper->pwl.rgb_resulted[63].red_reg = 1780; + shaper->pwl.rgb_resulted[63].green_reg = 1780; + shaper->pwl.rgb_resulted[63].blue_reg = 1780; + shaper->pwl.rgb_resulted[63].delta_red_reg = 25; + shaper->pwl.rgb_resulted[63].delta_green_reg = 25; + shaper->pwl.rgb_resulted[63].delta_blue_reg = 25; + shaper->pwl.rgb_resulted[64].red_reg = 1805; + shaper->pwl.rgb_resulted[64].green_reg = 1805; + shaper->pwl.rgb_resulted[64].blue_reg = 1805; + shaper->pwl.rgb_resulted[64].delta_red_reg = 51; + shaper->pwl.rgb_resulted[64].delta_green_reg = 51; + shaper->pwl.rgb_resulted[64].delta_blue_reg = 51; + shaper->pwl.rgb_resulted[65].red_reg = 1856; + shaper->pwl.rgb_resulted[65].green_reg = 1856; + shaper->pwl.rgb_resulted[65].blue_reg = 1856; + shaper->pwl.rgb_resulted[65].delta_red_reg = 49; + shaper->pwl.rgb_resulted[65].delta_green_reg = 49; + shaper->pwl.rgb_resulted[65].delta_blue_reg = 49; + shaper->pwl.rgb_resulted[66].red_reg = 1905; + shaper->pwl.rgb_resulted[66].green_reg = 1905; + shaper->pwl.rgb_resulted[66].blue_reg = 1905; + shaper->pwl.rgb_resulted[66].delta_red_reg = 47; + shaper->pwl.rgb_resulted[66].delta_green_reg = 47; + shaper->pwl.rgb_resulted[66].delta_blue_reg = 47; + shaper->pwl.rgb_resulted[67].red_reg = 1952; + shaper->pwl.rgb_resulted[67].green_reg = 1952; + shaper->pwl.rgb_resulted[67].blue_reg = 1952; + shaper->pwl.rgb_resulted[67].delta_red_reg = 46; + shaper->pwl.rgb_resulted[67].delta_green_reg = 46; + shaper->pwl.rgb_resulted[67].delta_blue_reg = 46; + shaper->pwl.rgb_resulted[68].red_reg = 1998; + shaper->pwl.rgb_resulted[68].green_reg = 1998; + shaper->pwl.rgb_resulted[68].blue_reg = 1998; + shaper->pwl.rgb_resulted[68].delta_red_reg = 45; + shaper->pwl.rgb_resulted[68].delta_green_reg = 45; + shaper->pwl.rgb_resulted[68].delta_blue_reg = 45; + shaper->pwl.rgb_resulted[69].red_reg = 2043; + shaper->pwl.rgb_resulted[69].green_reg = 2043; + shaper->pwl.rgb_resulted[69].blue_reg = 2043; + shaper->pwl.rgb_resulted[69].delta_red_reg = 44; + shaper->pwl.rgb_resulted[69].delta_green_reg = 44; + shaper->pwl.rgb_resulted[69].delta_blue_reg = 44; + shaper->pwl.rgb_resulted[70].red_reg = 2087; + shaper->pwl.rgb_resulted[70].green_reg = 2087; + shaper->pwl.rgb_resulted[70].blue_reg = 2087; + shaper->pwl.rgb_resulted[70].delta_red_reg = 42; + shaper->pwl.rgb_resulted[70].delta_green_reg = 42; + shaper->pwl.rgb_resulted[70].delta_blue_reg = 42; + shaper->pwl.rgb_resulted[71].red_reg = 2129; + shaper->pwl.rgb_resulted[71].green_reg = 2129; + shaper->pwl.rgb_resulted[71].blue_reg = 2129; + shaper->pwl.rgb_resulted[71].delta_red_reg = 42; + shaper->pwl.rgb_resulted[71].delta_green_reg = 42; + shaper->pwl.rgb_resulted[71].delta_blue_reg = 42; + shaper->pwl.rgb_resulted[72].red_reg = 2171; + shaper->pwl.rgb_resulted[72].green_reg = 2171; + shaper->pwl.rgb_resulted[72].blue_reg = 2171; + shaper->pwl.rgb_resulted[72].delta_red_reg = 40; + shaper->pwl.rgb_resulted[72].delta_green_reg = 40; + shaper->pwl.rgb_resulted[72].delta_blue_reg = 40; + shaper->pwl.rgb_resulted[73].red_reg = 2211; + shaper->pwl.rgb_resulted[73].green_reg = 2211; + shaper->pwl.rgb_resulted[73].blue_reg = 2211; + shaper->pwl.rgb_resulted[73].delta_red_reg = 40; + shaper->pwl.rgb_resulted[73].delta_green_reg = 40; + shaper->pwl.rgb_resulted[73].delta_blue_reg = 40; + shaper->pwl.rgb_resulted[74].red_reg = 2251; + shaper->pwl.rgb_resulted[74].green_reg = 2251; + shaper->pwl.rgb_resulted[74].blue_reg = 2251; + shaper->pwl.rgb_resulted[74].delta_red_reg = 39; + shaper->pwl.rgb_resulted[74].delta_green_reg = 39; + shaper->pwl.rgb_resulted[74].delta_blue_reg = 39; + shaper->pwl.rgb_resulted[75].red_reg = 2290; + shaper->pwl.rgb_resulted[75].green_reg = 2290; + shaper->pwl.rgb_resulted[75].blue_reg = 2290; + shaper->pwl.rgb_resulted[75].delta_red_reg = 38; + shaper->pwl.rgb_resulted[75].delta_green_reg = 38; + shaper->pwl.rgb_resulted[75].delta_blue_reg = 38; + shaper->pwl.rgb_resulted[76].red_reg = 2328; + shaper->pwl.rgb_resulted[76].green_reg = 2328; + shaper->pwl.rgb_resulted[76].blue_reg = 2328; + shaper->pwl.rgb_resulted[76].delta_red_reg = 38; + shaper->pwl.rgb_resulted[76].delta_green_reg = 38; + shaper->pwl.rgb_resulted[76].delta_blue_reg = 38; + shaper->pwl.rgb_resulted[77].red_reg = 2366; + shaper->pwl.rgb_resulted[77].green_reg = 2366; + shaper->pwl.rgb_resulted[77].blue_reg = 2366; + shaper->pwl.rgb_resulted[77].delta_red_reg = 36; + shaper->pwl.rgb_resulted[77].delta_green_reg = 36; + shaper->pwl.rgb_resulted[77].delta_blue_reg = 36; + shaper->pwl.rgb_resulted[78].red_reg = 2402; + shaper->pwl.rgb_resulted[78].green_reg = 2402; + shaper->pwl.rgb_resulted[78].blue_reg = 2402; + shaper->pwl.rgb_resulted[78].delta_red_reg = 37; + shaper->pwl.rgb_resulted[78].delta_green_reg = 37; + shaper->pwl.rgb_resulted[78].delta_blue_reg = 37; + shaper->pwl.rgb_resulted[79].red_reg = 2439; + shaper->pwl.rgb_resulted[79].green_reg = 2439; + shaper->pwl.rgb_resulted[79].blue_reg = 2439; + shaper->pwl.rgb_resulted[79].delta_red_reg = 35; + shaper->pwl.rgb_resulted[79].delta_green_reg = 35; + shaper->pwl.rgb_resulted[79].delta_blue_reg = 35; + shaper->pwl.rgb_resulted[80].red_reg = 2474; + shaper->pwl.rgb_resulted[80].green_reg = 2474; + shaper->pwl.rgb_resulted[80].blue_reg = 2474; + shaper->pwl.rgb_resulted[80].delta_red_reg = 69; + shaper->pwl.rgb_resulted[80].delta_green_reg = 69; + shaper->pwl.rgb_resulted[80].delta_blue_reg = 69; + shaper->pwl.rgb_resulted[81].red_reg = 2543; + shaper->pwl.rgb_resulted[81].green_reg = 2543; + shaper->pwl.rgb_resulted[81].blue_reg = 2543; + shaper->pwl.rgb_resulted[81].delta_red_reg = 67; + shaper->pwl.rgb_resulted[81].delta_green_reg = 67; + shaper->pwl.rgb_resulted[81].delta_blue_reg = 67; + shaper->pwl.rgb_resulted[82].red_reg = 2610; + shaper->pwl.rgb_resulted[82].green_reg = 2610; + shaper->pwl.rgb_resulted[82].blue_reg = 2610; + shaper->pwl.rgb_resulted[82].delta_red_reg = 65; + shaper->pwl.rgb_resulted[82].delta_green_reg = 65; + shaper->pwl.rgb_resulted[82].delta_blue_reg = 65; + shaper->pwl.rgb_resulted[83].red_reg = 2675; + shaper->pwl.rgb_resulted[83].green_reg = 2675; + shaper->pwl.rgb_resulted[83].blue_reg = 2675; + shaper->pwl.rgb_resulted[83].delta_red_reg = 63; + shaper->pwl.rgb_resulted[83].delta_green_reg = 63; + shaper->pwl.rgb_resulted[83].delta_blue_reg = 63; + shaper->pwl.rgb_resulted[84].red_reg = 2738; + shaper->pwl.rgb_resulted[84].green_reg = 2738; + shaper->pwl.rgb_resulted[84].blue_reg = 2738; + shaper->pwl.rgb_resulted[84].delta_red_reg = 62; + shaper->pwl.rgb_resulted[84].delta_green_reg = 62; + shaper->pwl.rgb_resulted[84].delta_blue_reg = 62; + shaper->pwl.rgb_resulted[85].red_reg = 2800; + shaper->pwl.rgb_resulted[85].green_reg = 2800; + shaper->pwl.rgb_resulted[85].blue_reg = 2800; + shaper->pwl.rgb_resulted[85].delta_red_reg = 59; + shaper->pwl.rgb_resulted[85].delta_green_reg = 59; + shaper->pwl.rgb_resulted[85].delta_blue_reg = 59; + shaper->pwl.rgb_resulted[86].red_reg = 2859; + shaper->pwl.rgb_resulted[86].green_reg = 2859; + shaper->pwl.rgb_resulted[86].blue_reg = 2859; + shaper->pwl.rgb_resulted[86].delta_red_reg = 59; + shaper->pwl.rgb_resulted[86].delta_green_reg = 59; + shaper->pwl.rgb_resulted[86].delta_blue_reg = 59; + shaper->pwl.rgb_resulted[87].red_reg = 2918; + shaper->pwl.rgb_resulted[87].green_reg = 2918; + shaper->pwl.rgb_resulted[87].blue_reg = 2918; + shaper->pwl.rgb_resulted[87].delta_red_reg = 57; + shaper->pwl.rgb_resulted[87].delta_green_reg = 57; + shaper->pwl.rgb_resulted[87].delta_blue_reg = 57; + shaper->pwl.rgb_resulted[88].red_reg = 2975; + shaper->pwl.rgb_resulted[88].green_reg = 2975; + shaper->pwl.rgb_resulted[88].blue_reg = 2975; + shaper->pwl.rgb_resulted[88].delta_red_reg = 55; + shaper->pwl.rgb_resulted[88].delta_green_reg = 55; + shaper->pwl.rgb_resulted[88].delta_blue_reg = 55; + shaper->pwl.rgb_resulted[89].red_reg = 3030; + shaper->pwl.rgb_resulted[89].green_reg = 3030; + shaper->pwl.rgb_resulted[89].blue_reg = 3030; + shaper->pwl.rgb_resulted[89].delta_red_reg = 55; + shaper->pwl.rgb_resulted[89].delta_green_reg = 55; + shaper->pwl.rgb_resulted[89].delta_blue_reg = 55; + shaper->pwl.rgb_resulted[90].red_reg = 3085; + shaper->pwl.rgb_resulted[90].green_reg = 3085; + shaper->pwl.rgb_resulted[90].blue_reg = 3085; + shaper->pwl.rgb_resulted[90].delta_red_reg = 53; + shaper->pwl.rgb_resulted[90].delta_green_reg = 53; + shaper->pwl.rgb_resulted[90].delta_blue_reg = 53; + shaper->pwl.rgb_resulted[91].red_reg = 3138; + shaper->pwl.rgb_resulted[91].green_reg = 3138; + shaper->pwl.rgb_resulted[91].blue_reg = 3138; + shaper->pwl.rgb_resulted[91].delta_red_reg = 53; + shaper->pwl.rgb_resulted[91].delta_green_reg = 53; + shaper->pwl.rgb_resulted[91].delta_blue_reg = 53; + shaper->pwl.rgb_resulted[92].red_reg = 3191; + shaper->pwl.rgb_resulted[92].green_reg = 3191; + shaper->pwl.rgb_resulted[92].blue_reg = 3191; + shaper->pwl.rgb_resulted[92].delta_red_reg = 51; + shaper->pwl.rgb_resulted[92].delta_green_reg = 51; + shaper->pwl.rgb_resulted[92].delta_blue_reg = 51; + shaper->pwl.rgb_resulted[93].red_reg = 3242; + shaper->pwl.rgb_resulted[93].green_reg = 3242; + shaper->pwl.rgb_resulted[93].blue_reg = 3242; + shaper->pwl.rgb_resulted[93].delta_red_reg = 50; + shaper->pwl.rgb_resulted[93].delta_green_reg = 50; + shaper->pwl.rgb_resulted[93].delta_blue_reg = 50; + shaper->pwl.rgb_resulted[94].red_reg = 3292; + shaper->pwl.rgb_resulted[94].green_reg = 3292; + shaper->pwl.rgb_resulted[94].blue_reg = 3292; + shaper->pwl.rgb_resulted[94].delta_red_reg = 50; + shaper->pwl.rgb_resulted[94].delta_green_reg = 50; + shaper->pwl.rgb_resulted[94].delta_blue_reg = 50; + shaper->pwl.rgb_resulted[95].red_reg = 3342; + shaper->pwl.rgb_resulted[95].green_reg = 3342; + shaper->pwl.rgb_resulted[95].blue_reg = 3342; + shaper->pwl.rgb_resulted[95].delta_red_reg = 48; + shaper->pwl.rgb_resulted[95].delta_green_reg = 48; + shaper->pwl.rgb_resulted[95].delta_blue_reg = 48; + shaper->pwl.rgb_resulted[96].red_reg = 3390; + shaper->pwl.rgb_resulted[96].green_reg = 3390; + shaper->pwl.rgb_resulted[96].blue_reg = 3390; + shaper->pwl.rgb_resulted[96].delta_red_reg = 95; + shaper->pwl.rgb_resulted[96].delta_green_reg = 95; + shaper->pwl.rgb_resulted[96].delta_blue_reg = 95; + shaper->pwl.rgb_resulted[97].red_reg = 3485; + shaper->pwl.rgb_resulted[97].green_reg = 3485; + shaper->pwl.rgb_resulted[97].blue_reg = 3485; + shaper->pwl.rgb_resulted[97].delta_red_reg = 92; + shaper->pwl.rgb_resulted[97].delta_green_reg = 92; + shaper->pwl.rgb_resulted[97].delta_blue_reg = 92; + shaper->pwl.rgb_resulted[98].red_reg = 3577; + shaper->pwl.rgb_resulted[98].green_reg = 3577; + shaper->pwl.rgb_resulted[98].blue_reg = 3577; + shaper->pwl.rgb_resulted[98].delta_red_reg = 89; + shaper->pwl.rgb_resulted[98].delta_green_reg = 89; + shaper->pwl.rgb_resulted[98].delta_blue_reg = 89; + shaper->pwl.rgb_resulted[99].red_reg = 3666; + shaper->pwl.rgb_resulted[99].green_reg = 3666; + shaper->pwl.rgb_resulted[99].blue_reg = 3666; + shaper->pwl.rgb_resulted[99].delta_red_reg = 86; + shaper->pwl.rgb_resulted[99].delta_green_reg = 86; + shaper->pwl.rgb_resulted[99].delta_blue_reg = 86; + shaper->pwl.rgb_resulted[100].red_reg = 3752; + shaper->pwl.rgb_resulted[100].green_reg = 3752; + shaper->pwl.rgb_resulted[100].blue_reg = 3752; + shaper->pwl.rgb_resulted[100].delta_red_reg = 84; + shaper->pwl.rgb_resulted[100].delta_green_reg = 84; + shaper->pwl.rgb_resulted[100].delta_blue_reg = 84; + shaper->pwl.rgb_resulted[101].red_reg = 3836; + shaper->pwl.rgb_resulted[101].green_reg = 3836; + shaper->pwl.rgb_resulted[101].blue_reg = 3836; + shaper->pwl.rgb_resulted[101].delta_red_reg = 82; + shaper->pwl.rgb_resulted[101].delta_green_reg = 82; + shaper->pwl.rgb_resulted[101].delta_blue_reg = 82; + shaper->pwl.rgb_resulted[102].red_reg = 3918; + shaper->pwl.rgb_resulted[102].green_reg = 3918; + shaper->pwl.rgb_resulted[102].blue_reg = 3918; + shaper->pwl.rgb_resulted[102].delta_red_reg = 80; + shaper->pwl.rgb_resulted[102].delta_green_reg = 80; + shaper->pwl.rgb_resulted[102].delta_blue_reg = 80; + shaper->pwl.rgb_resulted[103].red_reg = 3998; + shaper->pwl.rgb_resulted[103].green_reg = 3998; + shaper->pwl.rgb_resulted[103].blue_reg = 3998; + shaper->pwl.rgb_resulted[103].delta_red_reg = 78; + shaper->pwl.rgb_resulted[103].delta_green_reg = 78; + shaper->pwl.rgb_resulted[103].delta_blue_reg = 78; + shaper->pwl.rgb_resulted[104].red_reg = 4076; + shaper->pwl.rgb_resulted[104].green_reg = 4076; + shaper->pwl.rgb_resulted[104].blue_reg = 4076; + shaper->pwl.rgb_resulted[104].delta_red_reg = 77; + shaper->pwl.rgb_resulted[104].delta_green_reg = 77; + shaper->pwl.rgb_resulted[104].delta_blue_reg = 77; + shaper->pwl.rgb_resulted[105].red_reg = 4153; + shaper->pwl.rgb_resulted[105].green_reg = 4153; + shaper->pwl.rgb_resulted[105].blue_reg = 4153; + shaper->pwl.rgb_resulted[105].delta_red_reg = 74; + shaper->pwl.rgb_resulted[105].delta_green_reg = 74; + shaper->pwl.rgb_resulted[105].delta_blue_reg = 74; + shaper->pwl.rgb_resulted[106].red_reg = 4227; + shaper->pwl.rgb_resulted[106].green_reg = 4227; + shaper->pwl.rgb_resulted[106].blue_reg = 4227; + shaper->pwl.rgb_resulted[106].delta_red_reg = 74; + shaper->pwl.rgb_resulted[106].delta_green_reg = 74; + shaper->pwl.rgb_resulted[106].delta_blue_reg = 74; + shaper->pwl.rgb_resulted[107].red_reg = 4301; + shaper->pwl.rgb_resulted[107].green_reg = 4301; + shaper->pwl.rgb_resulted[107].blue_reg = 4301; + shaper->pwl.rgb_resulted[107].delta_red_reg = 71; + shaper->pwl.rgb_resulted[107].delta_green_reg = 71; + shaper->pwl.rgb_resulted[107].delta_blue_reg = 71; + shaper->pwl.rgb_resulted[108].red_reg = 4372; + shaper->pwl.rgb_resulted[108].green_reg = 4372; + shaper->pwl.rgb_resulted[108].blue_reg = 4372; + shaper->pwl.rgb_resulted[108].delta_red_reg = 71; + shaper->pwl.rgb_resulted[108].delta_green_reg = 71; + shaper->pwl.rgb_resulted[108].delta_blue_reg = 71; + shaper->pwl.rgb_resulted[109].red_reg = 4443; + shaper->pwl.rgb_resulted[109].green_reg = 4443; + shaper->pwl.rgb_resulted[109].blue_reg = 4443; + shaper->pwl.rgb_resulted[109].delta_red_reg = 69; + shaper->pwl.rgb_resulted[109].delta_green_reg = 69; + shaper->pwl.rgb_resulted[109].delta_blue_reg = 69; + shaper->pwl.rgb_resulted[110].red_reg = 4512; + shaper->pwl.rgb_resulted[110].green_reg = 4512; + shaper->pwl.rgb_resulted[110].blue_reg = 4512; + shaper->pwl.rgb_resulted[110].delta_red_reg = 67; + shaper->pwl.rgb_resulted[110].delta_green_reg = 67; + shaper->pwl.rgb_resulted[110].delta_blue_reg = 67; + shaper->pwl.rgb_resulted[111].red_reg = 4579; + shaper->pwl.rgb_resulted[111].green_reg = 4579; + shaper->pwl.rgb_resulted[111].blue_reg = 4579; + shaper->pwl.rgb_resulted[111].delta_red_reg = 67; + shaper->pwl.rgb_resulted[111].delta_green_reg = 67; + shaper->pwl.rgb_resulted[111].delta_blue_reg = 67; + shaper->pwl.rgb_resulted[112].red_reg = 4646; + shaper->pwl.rgb_resulted[112].green_reg = 4646; + shaper->pwl.rgb_resulted[112].blue_reg = 4646; + shaper->pwl.rgb_resulted[112].delta_red_reg = 130; + shaper->pwl.rgb_resulted[112].delta_green_reg = 130; + shaper->pwl.rgb_resulted[112].delta_blue_reg = 130; + shaper->pwl.rgb_resulted[113].red_reg = 4776; + shaper->pwl.rgb_resulted[113].green_reg = 4776; + shaper->pwl.rgb_resulted[113].blue_reg = 4776; + shaper->pwl.rgb_resulted[113].delta_red_reg = 125; + shaper->pwl.rgb_resulted[113].delta_green_reg = 125; + shaper->pwl.rgb_resulted[113].delta_blue_reg = 125; + shaper->pwl.rgb_resulted[114].red_reg = 4901; + shaper->pwl.rgb_resulted[114].green_reg = 4901; + shaper->pwl.rgb_resulted[114].blue_reg = 4901; + shaper->pwl.rgb_resulted[114].delta_red_reg = 122; + shaper->pwl.rgb_resulted[114].delta_green_reg = 122; + shaper->pwl.rgb_resulted[114].delta_blue_reg = 122; + shaper->pwl.rgb_resulted[115].red_reg = 5023; + shaper->pwl.rgb_resulted[115].green_reg = 5023; + shaper->pwl.rgb_resulted[115].blue_reg = 5023; + shaper->pwl.rgb_resulted[115].delta_red_reg = 119; + shaper->pwl.rgb_resulted[115].delta_green_reg = 119; + shaper->pwl.rgb_resulted[115].delta_blue_reg = 119; + shaper->pwl.rgb_resulted[116].red_reg = 5142; + shaper->pwl.rgb_resulted[116].green_reg = 5142; + shaper->pwl.rgb_resulted[116].blue_reg = 5142; + shaper->pwl.rgb_resulted[116].delta_red_reg = 115; + shaper->pwl.rgb_resulted[116].delta_green_reg = 115; + shaper->pwl.rgb_resulted[116].delta_blue_reg = 115; + shaper->pwl.rgb_resulted[117].red_reg = 5257; + shaper->pwl.rgb_resulted[117].green_reg = 5257; + shaper->pwl.rgb_resulted[117].blue_reg = 5257; + shaper->pwl.rgb_resulted[117].delta_red_reg = 112; + shaper->pwl.rgb_resulted[117].delta_green_reg = 112; + shaper->pwl.rgb_resulted[117].delta_blue_reg = 112; + shaper->pwl.rgb_resulted[118].red_reg = 5369; + shaper->pwl.rgb_resulted[118].green_reg = 5369; + shaper->pwl.rgb_resulted[118].blue_reg = 5369; + shaper->pwl.rgb_resulted[118].delta_red_reg = 110; + shaper->pwl.rgb_resulted[118].delta_green_reg = 110; + shaper->pwl.rgb_resulted[118].delta_blue_reg = 110; + shaper->pwl.rgb_resulted[119].red_reg = 5479; + shaper->pwl.rgb_resulted[119].green_reg = 5479; + shaper->pwl.rgb_resulted[119].blue_reg = 5479; + shaper->pwl.rgb_resulted[119].delta_red_reg = 107; + shaper->pwl.rgb_resulted[119].delta_green_reg = 107; + shaper->pwl.rgb_resulted[119].delta_blue_reg = 107; + shaper->pwl.rgb_resulted[120].red_reg = 5586; + shaper->pwl.rgb_resulted[120].green_reg = 5586; + shaper->pwl.rgb_resulted[120].blue_reg = 5586; + shaper->pwl.rgb_resulted[120].delta_red_reg = 105; + shaper->pwl.rgb_resulted[120].delta_green_reg = 105; + shaper->pwl.rgb_resulted[120].delta_blue_reg = 105; + shaper->pwl.rgb_resulted[121].red_reg = 5691; + shaper->pwl.rgb_resulted[121].green_reg = 5691; + shaper->pwl.rgb_resulted[121].blue_reg = 5691; + shaper->pwl.rgb_resulted[121].delta_red_reg = 102; + shaper->pwl.rgb_resulted[121].delta_green_reg = 102; + shaper->pwl.rgb_resulted[121].delta_blue_reg = 102; + shaper->pwl.rgb_resulted[122].red_reg = 5793; + shaper->pwl.rgb_resulted[122].green_reg = 5793; + shaper->pwl.rgb_resulted[122].blue_reg = 5793; + shaper->pwl.rgb_resulted[122].delta_red_reg = 100; + shaper->pwl.rgb_resulted[122].delta_green_reg = 100; + shaper->pwl.rgb_resulted[122].delta_blue_reg = 100; + shaper->pwl.rgb_resulted[123].red_reg = 5893; + shaper->pwl.rgb_resulted[123].green_reg = 5893; + shaper->pwl.rgb_resulted[123].blue_reg = 5893; + shaper->pwl.rgb_resulted[123].delta_red_reg = 99; + shaper->pwl.rgb_resulted[123].delta_green_reg = 99; + shaper->pwl.rgb_resulted[123].delta_blue_reg = 99; + shaper->pwl.rgb_resulted[124].red_reg = 5992; + shaper->pwl.rgb_resulted[124].green_reg = 5992; + shaper->pwl.rgb_resulted[124].blue_reg = 5992; + shaper->pwl.rgb_resulted[124].delta_red_reg = 96; + shaper->pwl.rgb_resulted[124].delta_green_reg = 96; + shaper->pwl.rgb_resulted[124].delta_blue_reg = 96; + shaper->pwl.rgb_resulted[125].red_reg = 6088; + shaper->pwl.rgb_resulted[125].green_reg = 6088; + shaper->pwl.rgb_resulted[125].blue_reg = 6088; + shaper->pwl.rgb_resulted[125].delta_red_reg = 94; + shaper->pwl.rgb_resulted[125].delta_green_reg = 94; + shaper->pwl.rgb_resulted[125].delta_blue_reg = 94; + shaper->pwl.rgb_resulted[126].red_reg = 6182; + shaper->pwl.rgb_resulted[126].green_reg = 6182; + shaper->pwl.rgb_resulted[126].blue_reg = 6182; + shaper->pwl.rgb_resulted[126].delta_red_reg = 93; + shaper->pwl.rgb_resulted[126].delta_green_reg = 93; + shaper->pwl.rgb_resulted[126].delta_blue_reg = 93; + shaper->pwl.rgb_resulted[127].red_reg = 6275; + shaper->pwl.rgb_resulted[127].green_reg = 6275; + shaper->pwl.rgb_resulted[127].blue_reg = 6275; + shaper->pwl.rgb_resulted[127].delta_red_reg = 91; + shaper->pwl.rgb_resulted[127].delta_green_reg = 91; + shaper->pwl.rgb_resulted[127].delta_blue_reg = 91; + shaper->pwl.rgb_resulted[128].red_reg = 6366; + shaper->pwl.rgb_resulted[128].green_reg = 6366; + shaper->pwl.rgb_resulted[128].blue_reg = 6366; + shaper->pwl.rgb_resulted[128].delta_red_reg = 90; + shaper->pwl.rgb_resulted[128].delta_green_reg = 90; + shaper->pwl.rgb_resulted[128].delta_blue_reg = 90; + shaper->pwl.rgb_resulted[129].red_reg = 6456; + shaper->pwl.rgb_resulted[129].green_reg = 6456; + shaper->pwl.rgb_resulted[129].blue_reg = 6456; + shaper->pwl.rgb_resulted[129].delta_red_reg = 88; + shaper->pwl.rgb_resulted[129].delta_green_reg = 88; + shaper->pwl.rgb_resulted[129].delta_blue_reg = 88; + shaper->pwl.rgb_resulted[130].red_reg = 6544; + shaper->pwl.rgb_resulted[130].green_reg = 6544; + shaper->pwl.rgb_resulted[130].blue_reg = 6544; + shaper->pwl.rgb_resulted[130].delta_red_reg = 87; + shaper->pwl.rgb_resulted[130].delta_green_reg = 87; + shaper->pwl.rgb_resulted[130].delta_blue_reg = 87; + shaper->pwl.rgb_resulted[131].red_reg = 6631; + shaper->pwl.rgb_resulted[131].green_reg = 6631; + shaper->pwl.rgb_resulted[131].blue_reg = 6631; + shaper->pwl.rgb_resulted[131].delta_red_reg = 86; + shaper->pwl.rgb_resulted[131].delta_green_reg = 86; + shaper->pwl.rgb_resulted[131].delta_blue_reg = 86; + shaper->pwl.rgb_resulted[132].red_reg = 6717; + shaper->pwl.rgb_resulted[132].green_reg = 6717; + shaper->pwl.rgb_resulted[132].blue_reg = 6717; + shaper->pwl.rgb_resulted[132].delta_red_reg = 84; + shaper->pwl.rgb_resulted[132].delta_green_reg = 84; + shaper->pwl.rgb_resulted[132].delta_blue_reg = 84; + shaper->pwl.rgb_resulted[133].red_reg = 6801; + shaper->pwl.rgb_resulted[133].green_reg = 6801; + shaper->pwl.rgb_resulted[133].blue_reg = 6801; + shaper->pwl.rgb_resulted[133].delta_red_reg = 83; + shaper->pwl.rgb_resulted[133].delta_green_reg = 83; + shaper->pwl.rgb_resulted[133].delta_blue_reg = 83; + shaper->pwl.rgb_resulted[134].red_reg = 6884; + shaper->pwl.rgb_resulted[134].green_reg = 6884; + shaper->pwl.rgb_resulted[134].blue_reg = 6884; + shaper->pwl.rgb_resulted[134].delta_red_reg = 81; + shaper->pwl.rgb_resulted[134].delta_green_reg = 81; + shaper->pwl.rgb_resulted[134].delta_blue_reg = 81; + shaper->pwl.rgb_resulted[135].red_reg = 6965; + shaper->pwl.rgb_resulted[135].green_reg = 6965; + shaper->pwl.rgb_resulted[135].blue_reg = 6965; + shaper->pwl.rgb_resulted[135].delta_red_reg = 81; + shaper->pwl.rgb_resulted[135].delta_green_reg = 81; + shaper->pwl.rgb_resulted[135].delta_blue_reg = 81; + shaper->pwl.rgb_resulted[136].red_reg = 7046; + shaper->pwl.rgb_resulted[136].green_reg = 7046; + shaper->pwl.rgb_resulted[136].blue_reg = 7046; + shaper->pwl.rgb_resulted[136].delta_red_reg = 80; + shaper->pwl.rgb_resulted[136].delta_green_reg = 80; + shaper->pwl.rgb_resulted[136].delta_blue_reg = 80; + shaper->pwl.rgb_resulted[137].red_reg = 7126; + shaper->pwl.rgb_resulted[137].green_reg = 7126; + shaper->pwl.rgb_resulted[137].blue_reg = 7126; + shaper->pwl.rgb_resulted[137].delta_red_reg = 78; + shaper->pwl.rgb_resulted[137].delta_green_reg = 78; + shaper->pwl.rgb_resulted[137].delta_blue_reg = 78; + shaper->pwl.rgb_resulted[138].red_reg = 7204; + shaper->pwl.rgb_resulted[138].green_reg = 7204; + shaper->pwl.rgb_resulted[138].blue_reg = 7204; + shaper->pwl.rgb_resulted[138].delta_red_reg = 78; + shaper->pwl.rgb_resulted[138].delta_green_reg = 78; + shaper->pwl.rgb_resulted[138].delta_blue_reg = 78; + shaper->pwl.rgb_resulted[139].red_reg = 7282; + shaper->pwl.rgb_resulted[139].green_reg = 7282; + shaper->pwl.rgb_resulted[139].blue_reg = 7282; + shaper->pwl.rgb_resulted[139].delta_red_reg = 76; + shaper->pwl.rgb_resulted[139].delta_green_reg = 76; + shaper->pwl.rgb_resulted[139].delta_blue_reg = 76; + shaper->pwl.rgb_resulted[140].red_reg = 7358; + shaper->pwl.rgb_resulted[140].green_reg = 7358; + shaper->pwl.rgb_resulted[140].blue_reg = 7358; + shaper->pwl.rgb_resulted[140].delta_red_reg = 76; + shaper->pwl.rgb_resulted[140].delta_green_reg = 76; + shaper->pwl.rgb_resulted[140].delta_blue_reg = 76; + shaper->pwl.rgb_resulted[141].red_reg = 7434; + shaper->pwl.rgb_resulted[141].green_reg = 7434; + shaper->pwl.rgb_resulted[141].blue_reg = 7434; + shaper->pwl.rgb_resulted[141].delta_red_reg = 74; + shaper->pwl.rgb_resulted[141].delta_green_reg = 74; + shaper->pwl.rgb_resulted[141].delta_blue_reg = 74; + shaper->pwl.rgb_resulted[142].red_reg = 7508; + shaper->pwl.rgb_resulted[142].green_reg = 7508; + shaper->pwl.rgb_resulted[142].blue_reg = 7508; + shaper->pwl.rgb_resulted[142].delta_red_reg = 74; + shaper->pwl.rgb_resulted[142].delta_green_reg = 74; + shaper->pwl.rgb_resulted[142].delta_blue_reg = 74; + shaper->pwl.rgb_resulted[143].red_reg = 7582; + shaper->pwl.rgb_resulted[143].green_reg = 7582; + shaper->pwl.rgb_resulted[143].blue_reg = 7582; + shaper->pwl.rgb_resulted[143].delta_red_reg = 73; + shaper->pwl.rgb_resulted[143].delta_green_reg = 73; + shaper->pwl.rgb_resulted[143].delta_blue_reg = 73; + shaper->pwl.rgb_resulted[144].red_reg = 7655; + shaper->pwl.rgb_resulted[144].green_reg = 7655; + shaper->pwl.rgb_resulted[144].blue_reg = 7655; + shaper->pwl.rgb_resulted[144].delta_red_reg = 72; + shaper->pwl.rgb_resulted[144].delta_green_reg = 72; + shaper->pwl.rgb_resulted[144].delta_blue_reg = 72; + shaper->pwl.rgb_resulted[145].red_reg = 7727; + shaper->pwl.rgb_resulted[145].green_reg = 7727; + shaper->pwl.rgb_resulted[145].blue_reg = 7727; + shaper->pwl.rgb_resulted[145].delta_red_reg = 71; + shaper->pwl.rgb_resulted[145].delta_green_reg = 71; + shaper->pwl.rgb_resulted[145].delta_blue_reg = 71; + shaper->pwl.rgb_resulted[146].red_reg = 7798; + shaper->pwl.rgb_resulted[146].green_reg = 7798; + shaper->pwl.rgb_resulted[146].blue_reg = 7798; + shaper->pwl.rgb_resulted[146].delta_red_reg = 71; + shaper->pwl.rgb_resulted[146].delta_green_reg = 71; + shaper->pwl.rgb_resulted[146].delta_blue_reg = 71; + shaper->pwl.rgb_resulted[147].red_reg = 7869; + shaper->pwl.rgb_resulted[147].green_reg = 7869; + shaper->pwl.rgb_resulted[147].blue_reg = 7869; + shaper->pwl.rgb_resulted[147].delta_red_reg = 70; + shaper->pwl.rgb_resulted[147].delta_green_reg = 70; + shaper->pwl.rgb_resulted[147].delta_blue_reg = 70; + shaper->pwl.rgb_resulted[148].red_reg = 7939; + shaper->pwl.rgb_resulted[148].green_reg = 7939; + shaper->pwl.rgb_resulted[148].blue_reg = 7939; + shaper->pwl.rgb_resulted[148].delta_red_reg = 69; + shaper->pwl.rgb_resulted[148].delta_green_reg = 69; + shaper->pwl.rgb_resulted[148].delta_blue_reg = 69; + shaper->pwl.rgb_resulted[149].red_reg = 8008; + shaper->pwl.rgb_resulted[149].green_reg = 8008; + shaper->pwl.rgb_resulted[149].blue_reg = 8008; + shaper->pwl.rgb_resulted[149].delta_red_reg = 68; + shaper->pwl.rgb_resulted[149].delta_green_reg = 68; + shaper->pwl.rgb_resulted[149].delta_blue_reg = 68; + shaper->pwl.rgb_resulted[150].red_reg = 8076; + shaper->pwl.rgb_resulted[150].green_reg = 8076; + shaper->pwl.rgb_resulted[150].blue_reg = 8076; + shaper->pwl.rgb_resulted[150].delta_red_reg = 68; + shaper->pwl.rgb_resulted[150].delta_green_reg = 68; + shaper->pwl.rgb_resulted[150].delta_blue_reg = 68; + shaper->pwl.rgb_resulted[151].red_reg = 8144; + shaper->pwl.rgb_resulted[151].green_reg = 8144; + shaper->pwl.rgb_resulted[151].blue_reg = 8144; + shaper->pwl.rgb_resulted[151].delta_red_reg = 67; + shaper->pwl.rgb_resulted[151].delta_green_reg = 67; + shaper->pwl.rgb_resulted[151].delta_blue_reg = 67; + shaper->pwl.rgb_resulted[152].red_reg = 8211; + shaper->pwl.rgb_resulted[152].green_reg = 8211; + shaper->pwl.rgb_resulted[152].blue_reg = 8211; + shaper->pwl.rgb_resulted[152].delta_red_reg = 66; + shaper->pwl.rgb_resulted[152].delta_green_reg = 66; + shaper->pwl.rgb_resulted[152].delta_blue_reg = 66; + shaper->pwl.rgb_resulted[153].red_reg = 8277; + shaper->pwl.rgb_resulted[153].green_reg = 8277; + shaper->pwl.rgb_resulted[153].blue_reg = 8277; + shaper->pwl.rgb_resulted[153].delta_red_reg = 66; + shaper->pwl.rgb_resulted[153].delta_green_reg = 66; + shaper->pwl.rgb_resulted[153].delta_blue_reg = 66; + shaper->pwl.rgb_resulted[154].red_reg = 8343; + shaper->pwl.rgb_resulted[154].green_reg = 8343; + shaper->pwl.rgb_resulted[154].blue_reg = 8343; + shaper->pwl.rgb_resulted[154].delta_red_reg = 65; + shaper->pwl.rgb_resulted[154].delta_green_reg = 65; + shaper->pwl.rgb_resulted[154].delta_blue_reg = 65; + shaper->pwl.rgb_resulted[155].red_reg = 8408; + shaper->pwl.rgb_resulted[155].green_reg = 8408; + shaper->pwl.rgb_resulted[155].blue_reg = 8408; + shaper->pwl.rgb_resulted[155].delta_red_reg = 64; + shaper->pwl.rgb_resulted[155].delta_green_reg = 64; + shaper->pwl.rgb_resulted[155].delta_blue_reg = 64; + shaper->pwl.rgb_resulted[156].red_reg = 8472; + shaper->pwl.rgb_resulted[156].green_reg = 8472; + shaper->pwl.rgb_resulted[156].blue_reg = 8472; + shaper->pwl.rgb_resulted[156].delta_red_reg = 64; + shaper->pwl.rgb_resulted[156].delta_green_reg = 64; + shaper->pwl.rgb_resulted[156].delta_blue_reg = 64; + shaper->pwl.rgb_resulted[157].red_reg = 8536; + shaper->pwl.rgb_resulted[157].green_reg = 8536; + shaper->pwl.rgb_resulted[157].blue_reg = 8536; + shaper->pwl.rgb_resulted[157].delta_red_reg = 63; + shaper->pwl.rgb_resulted[157].delta_green_reg = 63; + shaper->pwl.rgb_resulted[157].delta_blue_reg = 63; + shaper->pwl.rgb_resulted[158].red_reg = 8599; + shaper->pwl.rgb_resulted[158].green_reg = 8599; + shaper->pwl.rgb_resulted[158].blue_reg = 8599; + shaper->pwl.rgb_resulted[158].delta_red_reg = 63; + shaper->pwl.rgb_resulted[158].delta_green_reg = 63; + shaper->pwl.rgb_resulted[158].delta_blue_reg = 63; + shaper->pwl.rgb_resulted[159].red_reg = 8662; + shaper->pwl.rgb_resulted[159].green_reg = 8662; + shaper->pwl.rgb_resulted[159].blue_reg = 8662; + shaper->pwl.rgb_resulted[159].delta_red_reg = 62; + shaper->pwl.rgb_resulted[159].delta_green_reg = 62; + shaper->pwl.rgb_resulted[159].delta_blue_reg = 62; + shaper->pwl.rgb_resulted[160].red_reg = 8724; + shaper->pwl.rgb_resulted[160].green_reg = 8724; + shaper->pwl.rgb_resulted[160].blue_reg = 8724; + shaper->pwl.rgb_resulted[160].delta_red_reg = 123; + shaper->pwl.rgb_resulted[160].delta_green_reg = 123; + shaper->pwl.rgb_resulted[160].delta_blue_reg = 123; + shaper->pwl.rgb_resulted[161].red_reg = 8847; + shaper->pwl.rgb_resulted[161].green_reg = 8847; + shaper->pwl.rgb_resulted[161].blue_reg = 8847; + shaper->pwl.rgb_resulted[161].delta_red_reg = 121; + shaper->pwl.rgb_resulted[161].delta_green_reg = 121; + shaper->pwl.rgb_resulted[161].delta_blue_reg = 121; + shaper->pwl.rgb_resulted[162].red_reg = 8968; + shaper->pwl.rgb_resulted[162].green_reg = 8968; + shaper->pwl.rgb_resulted[162].blue_reg = 8968; + shaper->pwl.rgb_resulted[162].delta_red_reg = 119; + shaper->pwl.rgb_resulted[162].delta_green_reg = 119; + shaper->pwl.rgb_resulted[162].delta_blue_reg = 119; + shaper->pwl.rgb_resulted[163].red_reg = 9087; + shaper->pwl.rgb_resulted[163].green_reg = 9087; + shaper->pwl.rgb_resulted[163].blue_reg = 9087; + shaper->pwl.rgb_resulted[163].delta_red_reg = 117; + shaper->pwl.rgb_resulted[163].delta_green_reg = 117; + shaper->pwl.rgb_resulted[163].delta_blue_reg = 117; + shaper->pwl.rgb_resulted[164].red_reg = 9204; + shaper->pwl.rgb_resulted[164].green_reg = 9204; + shaper->pwl.rgb_resulted[164].blue_reg = 9204; + shaper->pwl.rgb_resulted[164].delta_red_reg = 115; + shaper->pwl.rgb_resulted[164].delta_green_reg = 115; + shaper->pwl.rgb_resulted[164].delta_blue_reg = 115; + shaper->pwl.rgb_resulted[165].red_reg = 9319; + shaper->pwl.rgb_resulted[165].green_reg = 9319; + shaper->pwl.rgb_resulted[165].blue_reg = 9319; + shaper->pwl.rgb_resulted[165].delta_red_reg = 114; + shaper->pwl.rgb_resulted[165].delta_green_reg = 114; + shaper->pwl.rgb_resulted[165].delta_blue_reg = 114; + shaper->pwl.rgb_resulted[166].red_reg = 9433; + shaper->pwl.rgb_resulted[166].green_reg = 9433; + shaper->pwl.rgb_resulted[166].blue_reg = 9433; + shaper->pwl.rgb_resulted[166].delta_red_reg = 112; + shaper->pwl.rgb_resulted[166].delta_green_reg = 112; + shaper->pwl.rgb_resulted[166].delta_blue_reg = 112; + shaper->pwl.rgb_resulted[167].red_reg = 9545; + shaper->pwl.rgb_resulted[167].green_reg = 9545; + shaper->pwl.rgb_resulted[167].blue_reg = 9545; + shaper->pwl.rgb_resulted[167].delta_red_reg = 111; + shaper->pwl.rgb_resulted[167].delta_green_reg = 111; + shaper->pwl.rgb_resulted[167].delta_blue_reg = 111; + shaper->pwl.rgb_resulted[168].red_reg = 9656; + shaper->pwl.rgb_resulted[168].green_reg = 9656; + shaper->pwl.rgb_resulted[168].blue_reg = 9656; + shaper->pwl.rgb_resulted[168].delta_red_reg = 109; + shaper->pwl.rgb_resulted[168].delta_green_reg = 109; + shaper->pwl.rgb_resulted[168].delta_blue_reg = 109; + shaper->pwl.rgb_resulted[169].red_reg = 9765; + shaper->pwl.rgb_resulted[169].green_reg = 9765; + shaper->pwl.rgb_resulted[169].blue_reg = 9765; + shaper->pwl.rgb_resulted[169].delta_red_reg = 107; + shaper->pwl.rgb_resulted[169].delta_green_reg = 107; + shaper->pwl.rgb_resulted[169].delta_blue_reg = 107; + shaper->pwl.rgb_resulted[170].red_reg = 9872; + shaper->pwl.rgb_resulted[170].green_reg = 9872; + shaper->pwl.rgb_resulted[170].blue_reg = 9872; + shaper->pwl.rgb_resulted[170].delta_red_reg = 106; + shaper->pwl.rgb_resulted[170].delta_green_reg = 106; + shaper->pwl.rgb_resulted[170].delta_blue_reg = 106; + shaper->pwl.rgb_resulted[171].red_reg = 9978; + shaper->pwl.rgb_resulted[171].green_reg = 9978; + shaper->pwl.rgb_resulted[171].blue_reg = 9978; + shaper->pwl.rgb_resulted[171].delta_red_reg = 105; + shaper->pwl.rgb_resulted[171].delta_green_reg = 105; + shaper->pwl.rgb_resulted[171].delta_blue_reg = 105; + shaper->pwl.rgb_resulted[172].red_reg = 10083; + shaper->pwl.rgb_resulted[172].green_reg = 10083; + shaper->pwl.rgb_resulted[172].blue_reg = 10083; + shaper->pwl.rgb_resulted[172].delta_red_reg = 104; + shaper->pwl.rgb_resulted[172].delta_green_reg = 104; + shaper->pwl.rgb_resulted[172].delta_blue_reg = 104; + shaper->pwl.rgb_resulted[173].red_reg = 10187; + shaper->pwl.rgb_resulted[173].green_reg = 10187; + shaper->pwl.rgb_resulted[173].blue_reg = 10187; + shaper->pwl.rgb_resulted[173].delta_red_reg = 102; + shaper->pwl.rgb_resulted[173].delta_green_reg = 102; + shaper->pwl.rgb_resulted[173].delta_blue_reg = 102; + shaper->pwl.rgb_resulted[174].red_reg = 10289; + shaper->pwl.rgb_resulted[174].green_reg = 10289; + shaper->pwl.rgb_resulted[174].blue_reg = 10289; + shaper->pwl.rgb_resulted[174].delta_red_reg = 101; + shaper->pwl.rgb_resulted[174].delta_green_reg = 101; + shaper->pwl.rgb_resulted[174].delta_blue_reg = 101; + shaper->pwl.rgb_resulted[175].red_reg = 10390; + shaper->pwl.rgb_resulted[175].green_reg = 10390; + shaper->pwl.rgb_resulted[175].blue_reg = 10390; + shaper->pwl.rgb_resulted[175].delta_red_reg = 100; + shaper->pwl.rgb_resulted[175].delta_green_reg = 100; + shaper->pwl.rgb_resulted[175].delta_blue_reg = 100; + shaper->pwl.rgb_resulted[176].red_reg = 10490; + shaper->pwl.rgb_resulted[176].green_reg = 10490; + shaper->pwl.rgb_resulted[176].blue_reg = 10490; + shaper->pwl.rgb_resulted[176].delta_red_reg = 99; + shaper->pwl.rgb_resulted[176].delta_green_reg = 99; + shaper->pwl.rgb_resulted[176].delta_blue_reg = 99; + shaper->pwl.rgb_resulted[177].red_reg = 10589; + shaper->pwl.rgb_resulted[177].green_reg = 10589; + shaper->pwl.rgb_resulted[177].blue_reg = 10589; + shaper->pwl.rgb_resulted[177].delta_red_reg = 97; + shaper->pwl.rgb_resulted[177].delta_green_reg = 97; + shaper->pwl.rgb_resulted[177].delta_blue_reg = 97; + shaper->pwl.rgb_resulted[178].red_reg = 10686; + shaper->pwl.rgb_resulted[178].green_reg = 10686; + shaper->pwl.rgb_resulted[178].blue_reg = 10686; + shaper->pwl.rgb_resulted[178].delta_red_reg = 97; + shaper->pwl.rgb_resulted[178].delta_green_reg = 97; + shaper->pwl.rgb_resulted[178].delta_blue_reg = 97; + shaper->pwl.rgb_resulted[179].red_reg = 10783; + shaper->pwl.rgb_resulted[179].green_reg = 10783; + shaper->pwl.rgb_resulted[179].blue_reg = 10783; + shaper->pwl.rgb_resulted[179].delta_red_reg = 96; + shaper->pwl.rgb_resulted[179].delta_green_reg = 96; + shaper->pwl.rgb_resulted[179].delta_blue_reg = 96; + shaper->pwl.rgb_resulted[180].red_reg = 10879; + shaper->pwl.rgb_resulted[180].green_reg = 10879; + shaper->pwl.rgb_resulted[180].blue_reg = 10879; + shaper->pwl.rgb_resulted[180].delta_red_reg = 94; + shaper->pwl.rgb_resulted[180].delta_green_reg = 94; + shaper->pwl.rgb_resulted[180].delta_blue_reg = 94; + shaper->pwl.rgb_resulted[181].red_reg = 10973; + shaper->pwl.rgb_resulted[181].green_reg = 10973; + shaper->pwl.rgb_resulted[181].blue_reg = 10973; + shaper->pwl.rgb_resulted[181].delta_red_reg = 94; + shaper->pwl.rgb_resulted[181].delta_green_reg = 94; + shaper->pwl.rgb_resulted[181].delta_blue_reg = 94; + shaper->pwl.rgb_resulted[182].red_reg = 11067; + shaper->pwl.rgb_resulted[182].green_reg = 11067; + shaper->pwl.rgb_resulted[182].blue_reg = 11067; + shaper->pwl.rgb_resulted[182].delta_red_reg = 92; + shaper->pwl.rgb_resulted[182].delta_green_reg = 92; + shaper->pwl.rgb_resulted[182].delta_blue_reg = 92; + shaper->pwl.rgb_resulted[183].red_reg = 11159; + shaper->pwl.rgb_resulted[183].green_reg = 11159; + shaper->pwl.rgb_resulted[183].blue_reg = 11159; + shaper->pwl.rgb_resulted[183].delta_red_reg = 92; + shaper->pwl.rgb_resulted[183].delta_green_reg = 92; + shaper->pwl.rgb_resulted[183].delta_blue_reg = 92; + shaper->pwl.rgb_resulted[184].red_reg = 11251; + shaper->pwl.rgb_resulted[184].green_reg = 11251; + shaper->pwl.rgb_resulted[184].blue_reg = 11251; + shaper->pwl.rgb_resulted[184].delta_red_reg = 91; + shaper->pwl.rgb_resulted[184].delta_green_reg = 91; + shaper->pwl.rgb_resulted[184].delta_blue_reg = 91; + shaper->pwl.rgb_resulted[185].red_reg = 11342; + shaper->pwl.rgb_resulted[185].green_reg = 11342; + shaper->pwl.rgb_resulted[185].blue_reg = 11342; + shaper->pwl.rgb_resulted[185].delta_red_reg = 90; + shaper->pwl.rgb_resulted[185].delta_green_reg = 90; + shaper->pwl.rgb_resulted[185].delta_blue_reg = 90; + shaper->pwl.rgb_resulted[186].red_reg = 11432; + shaper->pwl.rgb_resulted[186].green_reg = 11432; + shaper->pwl.rgb_resulted[186].blue_reg = 11432; + shaper->pwl.rgb_resulted[186].delta_red_reg = 89; + shaper->pwl.rgb_resulted[186].delta_green_reg = 89; + shaper->pwl.rgb_resulted[186].delta_blue_reg = 89; + shaper->pwl.rgb_resulted[187].red_reg = 11521; + shaper->pwl.rgb_resulted[187].green_reg = 11521; + shaper->pwl.rgb_resulted[187].blue_reg = 11521; + shaper->pwl.rgb_resulted[187].delta_red_reg = 89; + shaper->pwl.rgb_resulted[187].delta_green_reg = 89; + shaper->pwl.rgb_resulted[187].delta_blue_reg = 89; + shaper->pwl.rgb_resulted[188].red_reg = 11610; + shaper->pwl.rgb_resulted[188].green_reg = 11610; + shaper->pwl.rgb_resulted[188].blue_reg = 11610; + shaper->pwl.rgb_resulted[188].delta_red_reg = 87; + shaper->pwl.rgb_resulted[188].delta_green_reg = 87; + shaper->pwl.rgb_resulted[188].delta_blue_reg = 87; + shaper->pwl.rgb_resulted[189].red_reg = 11697; + shaper->pwl.rgb_resulted[189].green_reg = 11697; + shaper->pwl.rgb_resulted[189].blue_reg = 11697; + shaper->pwl.rgb_resulted[189].delta_red_reg = 87; + shaper->pwl.rgb_resulted[189].delta_green_reg = 87; + shaper->pwl.rgb_resulted[189].delta_blue_reg = 87; + shaper->pwl.rgb_resulted[190].red_reg = 11784; + shaper->pwl.rgb_resulted[190].green_reg = 11784; + shaper->pwl.rgb_resulted[190].blue_reg = 11784; + shaper->pwl.rgb_resulted[190].delta_red_reg = 86; + shaper->pwl.rgb_resulted[190].delta_green_reg = 86; + shaper->pwl.rgb_resulted[190].delta_blue_reg = 86; + shaper->pwl.rgb_resulted[191].red_reg = 11870; + shaper->pwl.rgb_resulted[191].green_reg = 11870; + shaper->pwl.rgb_resulted[191].blue_reg = 11870; + shaper->pwl.rgb_resulted[191].delta_red_reg = 85; + shaper->pwl.rgb_resulted[191].delta_green_reg = 85; + shaper->pwl.rgb_resulted[191].delta_blue_reg = 85; + shaper->pwl.rgb_resulted[192].red_reg = 11955; + shaper->pwl.rgb_resulted[192].green_reg = 11955; + shaper->pwl.rgb_resulted[192].blue_reg = 11955; + shaper->pwl.rgb_resulted[192].delta_red_reg = 169; + shaper->pwl.rgb_resulted[192].delta_green_reg = 169; + shaper->pwl.rgb_resulted[192].delta_blue_reg = 169; + shaper->pwl.rgb_resulted[193].red_reg = 12124; + shaper->pwl.rgb_resulted[193].green_reg = 12124; + shaper->pwl.rgb_resulted[193].blue_reg = 12124; + shaper->pwl.rgb_resulted[193].delta_red_reg = 165; + shaper->pwl.rgb_resulted[193].delta_green_reg = 165; + shaper->pwl.rgb_resulted[193].delta_blue_reg = 165; + shaper->pwl.rgb_resulted[194].red_reg = 12289; + shaper->pwl.rgb_resulted[194].green_reg = 12289; + shaper->pwl.rgb_resulted[194].blue_reg = 12289; + shaper->pwl.rgb_resulted[194].delta_red_reg = 163; + shaper->pwl.rgb_resulted[194].delta_green_reg = 163; + shaper->pwl.rgb_resulted[194].delta_blue_reg = 163; + shaper->pwl.rgb_resulted[195].red_reg = 12452; + shaper->pwl.rgb_resulted[195].green_reg = 12452; + shaper->pwl.rgb_resulted[195].blue_reg = 12452; + shaper->pwl.rgb_resulted[195].delta_red_reg = 161; + shaper->pwl.rgb_resulted[195].delta_green_reg = 161; + shaper->pwl.rgb_resulted[195].delta_blue_reg = 161; + shaper->pwl.rgb_resulted[196].red_reg = 12613; + shaper->pwl.rgb_resulted[196].green_reg = 12613; + shaper->pwl.rgb_resulted[196].blue_reg = 12613; + shaper->pwl.rgb_resulted[196].delta_red_reg = 158; + shaper->pwl.rgb_resulted[196].delta_green_reg = 158; + shaper->pwl.rgb_resulted[196].delta_blue_reg = 158; + shaper->pwl.rgb_resulted[197].red_reg = 12771; + shaper->pwl.rgb_resulted[197].green_reg = 12771; + shaper->pwl.rgb_resulted[197].blue_reg = 12771; + shaper->pwl.rgb_resulted[197].delta_red_reg = 156; + shaper->pwl.rgb_resulted[197].delta_green_reg = 156; + shaper->pwl.rgb_resulted[197].delta_blue_reg = 156; + shaper->pwl.rgb_resulted[198].red_reg = 12927; + shaper->pwl.rgb_resulted[198].green_reg = 12927; + shaper->pwl.rgb_resulted[198].blue_reg = 12927; + shaper->pwl.rgb_resulted[198].delta_red_reg = 153; + shaper->pwl.rgb_resulted[198].delta_green_reg = 153; + shaper->pwl.rgb_resulted[198].delta_blue_reg = 153; + shaper->pwl.rgb_resulted[199].red_reg = 13080; + shaper->pwl.rgb_resulted[199].green_reg = 13080; + shaper->pwl.rgb_resulted[199].blue_reg = 13080; + shaper->pwl.rgb_resulted[199].delta_red_reg = 152; + shaper->pwl.rgb_resulted[199].delta_green_reg = 152; + shaper->pwl.rgb_resulted[199].delta_blue_reg = 152; + shaper->pwl.rgb_resulted[200].red_reg = 13232; + shaper->pwl.rgb_resulted[200].green_reg = 13232; + shaper->pwl.rgb_resulted[200].blue_reg = 13232; + shaper->pwl.rgb_resulted[200].delta_red_reg = 149; + shaper->pwl.rgb_resulted[200].delta_green_reg = 149; + shaper->pwl.rgb_resulted[200].delta_blue_reg = 149; + shaper->pwl.rgb_resulted[201].red_reg = 13381; + shaper->pwl.rgb_resulted[201].green_reg = 13381; + shaper->pwl.rgb_resulted[201].blue_reg = 13381; + shaper->pwl.rgb_resulted[201].delta_red_reg = 147; + shaper->pwl.rgb_resulted[201].delta_green_reg = 147; + shaper->pwl.rgb_resulted[201].delta_blue_reg = 147; + shaper->pwl.rgb_resulted[202].red_reg = 13528; + shaper->pwl.rgb_resulted[202].green_reg = 13528; + shaper->pwl.rgb_resulted[202].blue_reg = 13528; + shaper->pwl.rgb_resulted[202].delta_red_reg = 146; + shaper->pwl.rgb_resulted[202].delta_green_reg = 146; + shaper->pwl.rgb_resulted[202].delta_blue_reg = 146; + shaper->pwl.rgb_resulted[203].red_reg = 13674; + shaper->pwl.rgb_resulted[203].green_reg = 13674; + shaper->pwl.rgb_resulted[203].blue_reg = 13674; + shaper->pwl.rgb_resulted[203].delta_red_reg = 143; + shaper->pwl.rgb_resulted[203].delta_green_reg = 143; + shaper->pwl.rgb_resulted[203].delta_blue_reg = 143; + shaper->pwl.rgb_resulted[204].red_reg = 13817; + shaper->pwl.rgb_resulted[204].green_reg = 13817; + shaper->pwl.rgb_resulted[204].blue_reg = 13817; + shaper->pwl.rgb_resulted[204].delta_red_reg = 142; + shaper->pwl.rgb_resulted[204].delta_green_reg = 142; + shaper->pwl.rgb_resulted[204].delta_blue_reg = 142; + shaper->pwl.rgb_resulted[205].red_reg = 13959; + shaper->pwl.rgb_resulted[205].green_reg = 13959; + shaper->pwl.rgb_resulted[205].blue_reg = 13959; + shaper->pwl.rgb_resulted[205].delta_red_reg = 140; + shaper->pwl.rgb_resulted[205].delta_green_reg = 140; + shaper->pwl.rgb_resulted[205].delta_blue_reg = 140; + shaper->pwl.rgb_resulted[206].red_reg = 14099; + shaper->pwl.rgb_resulted[206].green_reg = 14099; + shaper->pwl.rgb_resulted[206].blue_reg = 14099; + shaper->pwl.rgb_resulted[206].delta_red_reg = 139; + shaper->pwl.rgb_resulted[206].delta_green_reg = 139; + shaper->pwl.rgb_resulted[206].delta_blue_reg = 139; + shaper->pwl.rgb_resulted[207].red_reg = 14238; + shaper->pwl.rgb_resulted[207].green_reg = 14238; + shaper->pwl.rgb_resulted[207].blue_reg = 14238; + shaper->pwl.rgb_resulted[207].delta_red_reg = 137; + shaper->pwl.rgb_resulted[207].delta_green_reg = 137; + shaper->pwl.rgb_resulted[207].delta_blue_reg = 137; + shaper->pwl.rgb_resulted[208].red_reg = 14375; + shaper->pwl.rgb_resulted[208].green_reg = 14375; + shaper->pwl.rgb_resulted[208].blue_reg = 14375; + shaper->pwl.rgb_resulted[208].delta_red_reg = 135; + shaper->pwl.rgb_resulted[208].delta_green_reg = 135; + shaper->pwl.rgb_resulted[208].delta_blue_reg = 135; + shaper->pwl.rgb_resulted[209].red_reg = 14510; + shaper->pwl.rgb_resulted[209].green_reg = 14510; + shaper->pwl.rgb_resulted[209].blue_reg = 14510; + shaper->pwl.rgb_resulted[209].delta_red_reg = 134; + shaper->pwl.rgb_resulted[209].delta_green_reg = 134; + shaper->pwl.rgb_resulted[209].delta_blue_reg = 134; + shaper->pwl.rgb_resulted[210].red_reg = 14644; + shaper->pwl.rgb_resulted[210].green_reg = 14644; + shaper->pwl.rgb_resulted[210].blue_reg = 14644; + shaper->pwl.rgb_resulted[210].delta_red_reg = 132; + shaper->pwl.rgb_resulted[210].delta_green_reg = 132; + shaper->pwl.rgb_resulted[210].delta_blue_reg = 132; + shaper->pwl.rgb_resulted[211].red_reg = 14776; + shaper->pwl.rgb_resulted[211].green_reg = 14776; + shaper->pwl.rgb_resulted[211].blue_reg = 14776; + shaper->pwl.rgb_resulted[211].delta_red_reg = 131; + shaper->pwl.rgb_resulted[211].delta_green_reg = 131; + shaper->pwl.rgb_resulted[211].delta_blue_reg = 131; + shaper->pwl.rgb_resulted[212].red_reg = 14907; + shaper->pwl.rgb_resulted[212].green_reg = 14907; + shaper->pwl.rgb_resulted[212].blue_reg = 14907; + shaper->pwl.rgb_resulted[212].delta_red_reg = 130; + shaper->pwl.rgb_resulted[212].delta_green_reg = 130; + shaper->pwl.rgb_resulted[212].delta_blue_reg = 130; + shaper->pwl.rgb_resulted[213].red_reg = 15037; + shaper->pwl.rgb_resulted[213].green_reg = 15037; + shaper->pwl.rgb_resulted[213].blue_reg = 15037; + shaper->pwl.rgb_resulted[213].delta_red_reg = 128; + shaper->pwl.rgb_resulted[213].delta_green_reg = 128; + shaper->pwl.rgb_resulted[213].delta_blue_reg = 128; + shaper->pwl.rgb_resulted[214].red_reg = 15165; + shaper->pwl.rgb_resulted[214].green_reg = 15165; + shaper->pwl.rgb_resulted[214].blue_reg = 15165; + shaper->pwl.rgb_resulted[214].delta_red_reg = 127; + shaper->pwl.rgb_resulted[214].delta_green_reg = 127; + shaper->pwl.rgb_resulted[214].delta_blue_reg = 127; + shaper->pwl.rgb_resulted[215].red_reg = 15292; + shaper->pwl.rgb_resulted[215].green_reg = 15292; + shaper->pwl.rgb_resulted[215].blue_reg = 15292; + shaper->pwl.rgb_resulted[215].delta_red_reg = 126; + shaper->pwl.rgb_resulted[215].delta_green_reg = 126; + shaper->pwl.rgb_resulted[215].delta_blue_reg = 126; + shaper->pwl.rgb_resulted[216].red_reg = 15418; + shaper->pwl.rgb_resulted[216].green_reg = 15418; + shaper->pwl.rgb_resulted[216].blue_reg = 15418; + shaper->pwl.rgb_resulted[216].delta_red_reg = 125; + shaper->pwl.rgb_resulted[216].delta_green_reg = 125; + shaper->pwl.rgb_resulted[216].delta_blue_reg = 125; + shaper->pwl.rgb_resulted[217].red_reg = 15543; + shaper->pwl.rgb_resulted[217].green_reg = 15543; + shaper->pwl.rgb_resulted[217].blue_reg = 15543; + shaper->pwl.rgb_resulted[217].delta_red_reg = 123; + shaper->pwl.rgb_resulted[217].delta_green_reg = 123; + shaper->pwl.rgb_resulted[217].delta_blue_reg = 123; + shaper->pwl.rgb_resulted[218].red_reg = 15666; + shaper->pwl.rgb_resulted[218].green_reg = 15666; + shaper->pwl.rgb_resulted[218].blue_reg = 15666; + shaper->pwl.rgb_resulted[218].delta_red_reg = 122; + shaper->pwl.rgb_resulted[218].delta_green_reg = 122; + shaper->pwl.rgb_resulted[218].delta_blue_reg = 122; + shaper->pwl.rgb_resulted[219].red_reg = 15788; + shaper->pwl.rgb_resulted[219].green_reg = 15788; + shaper->pwl.rgb_resulted[219].blue_reg = 15788; + shaper->pwl.rgb_resulted[219].delta_red_reg = 121; + shaper->pwl.rgb_resulted[219].delta_green_reg = 121; + shaper->pwl.rgb_resulted[219].delta_blue_reg = 121; + shaper->pwl.rgb_resulted[220].red_reg = 15909; + shaper->pwl.rgb_resulted[220].green_reg = 15909; + shaper->pwl.rgb_resulted[220].blue_reg = 15909; + shaper->pwl.rgb_resulted[220].delta_red_reg = 120; + shaper->pwl.rgb_resulted[220].delta_green_reg = 120; + shaper->pwl.rgb_resulted[220].delta_blue_reg = 120; + shaper->pwl.rgb_resulted[221].red_reg = 16029; + shaper->pwl.rgb_resulted[221].green_reg = 16029; + shaper->pwl.rgb_resulted[221].blue_reg = 16029; + shaper->pwl.rgb_resulted[221].delta_red_reg = 119; + shaper->pwl.rgb_resulted[221].delta_green_reg = 119; + shaper->pwl.rgb_resulted[221].delta_blue_reg = 119; + shaper->pwl.rgb_resulted[222].red_reg = 16148; + shaper->pwl.rgb_resulted[222].green_reg = 16148; + shaper->pwl.rgb_resulted[222].blue_reg = 16148; + shaper->pwl.rgb_resulted[222].delta_red_reg = 118; + shaper->pwl.rgb_resulted[222].delta_green_reg = 118; + shaper->pwl.rgb_resulted[222].delta_blue_reg = 118; + shaper->pwl.rgb_resulted[223].red_reg = 16266; + shaper->pwl.rgb_resulted[223].green_reg = 16266; + shaper->pwl.rgb_resulted[223].blue_reg = 16266; + shaper->pwl.rgb_resulted[223].delta_red_reg = 117; + shaper->pwl.rgb_resulted[223].delta_green_reg = 117; + shaper->pwl.rgb_resulted[223].delta_blue_reg = 117; + shaper->pwl.rgb_resulted[224].red_reg = 16383; + shaper->pwl.rgb_resulted[224].green_reg = 16383; + shaper->pwl.rgb_resulted[224].blue_reg = 16383; + shaper->pwl.rgb_resulted[224].delta_red_reg = 4294951143; + shaper->pwl.rgb_resulted[224].delta_green_reg = 4294951143; + shaper->pwl.rgb_resulted[224].delta_blue_reg = 4294951143; + shaper->pwl.rgb_resulted[225].red_reg = 230; + shaper->pwl.rgb_resulted[225].green_reg = 230; + shaper->pwl.rgb_resulted[225].blue_reg = 230; + shaper->pwl.rgb_resulted[225].delta_red_reg = 227; + shaper->pwl.rgb_resulted[225].delta_green_reg = 227; + shaper->pwl.rgb_resulted[225].delta_blue_reg = 227; + shaper->pwl.rgb_resulted[226].red_reg = 457; + shaper->pwl.rgb_resulted[226].green_reg = 457; + shaper->pwl.rgb_resulted[226].blue_reg = 457; + shaper->pwl.rgb_resulted[226].delta_red_reg = 223; + shaper->pwl.rgb_resulted[226].delta_green_reg = 223; + shaper->pwl.rgb_resulted[226].delta_blue_reg = 223; + shaper->pwl.rgb_resulted[227].red_reg = 680; + shaper->pwl.rgb_resulted[227].green_reg = 680; + shaper->pwl.rgb_resulted[227].blue_reg = 680; + shaper->pwl.rgb_resulted[227].delta_red_reg = 220; + shaper->pwl.rgb_resulted[227].delta_green_reg = 220; + shaper->pwl.rgb_resulted[227].delta_blue_reg = 220; + shaper->pwl.rgb_resulted[228].red_reg = 900; + shaper->pwl.rgb_resulted[228].green_reg = 900; + shaper->pwl.rgb_resulted[228].blue_reg = 900; + shaper->pwl.rgb_resulted[228].delta_red_reg = 217; + shaper->pwl.rgb_resulted[228].delta_green_reg = 217; + shaper->pwl.rgb_resulted[228].delta_blue_reg = 217; + shaper->pwl.rgb_resulted[229].red_reg = 1117; + shaper->pwl.rgb_resulted[229].green_reg = 1117; + shaper->pwl.rgb_resulted[229].blue_reg = 1117; + shaper->pwl.rgb_resulted[229].delta_red_reg = 213; + shaper->pwl.rgb_resulted[229].delta_green_reg = 213; + shaper->pwl.rgb_resulted[229].delta_blue_reg = 213; + shaper->pwl.rgb_resulted[230].red_reg = 1330; + shaper->pwl.rgb_resulted[230].green_reg = 1330; + shaper->pwl.rgb_resulted[230].blue_reg = 1330; + shaper->pwl.rgb_resulted[230].delta_red_reg = 210; + shaper->pwl.rgb_resulted[230].delta_green_reg = 210; + shaper->pwl.rgb_resulted[230].delta_blue_reg = 210; + shaper->pwl.rgb_resulted[231].red_reg = 1540; + shaper->pwl.rgb_resulted[231].green_reg = 1540; + shaper->pwl.rgb_resulted[231].blue_reg = 1540; + shaper->pwl.rgb_resulted[231].delta_red_reg = 208; + shaper->pwl.rgb_resulted[231].delta_green_reg = 208; + shaper->pwl.rgb_resulted[231].delta_blue_reg = 208; + shaper->pwl.rgb_resulted[232].red_reg = 1748; + shaper->pwl.rgb_resulted[232].green_reg = 1748; + shaper->pwl.rgb_resulted[232].blue_reg = 1748; + shaper->pwl.rgb_resulted[232].delta_red_reg = 205; + shaper->pwl.rgb_resulted[232].delta_green_reg = 205; + shaper->pwl.rgb_resulted[232].delta_blue_reg = 205; + shaper->pwl.rgb_resulted[233].red_reg = 1953; + shaper->pwl.rgb_resulted[233].green_reg = 1953; + shaper->pwl.rgb_resulted[233].blue_reg = 1953; + shaper->pwl.rgb_resulted[233].delta_red_reg = 202; + shaper->pwl.rgb_resulted[233].delta_green_reg = 202; + shaper->pwl.rgb_resulted[233].delta_blue_reg = 202; + shaper->pwl.rgb_resulted[234].red_reg = 2155; + shaper->pwl.rgb_resulted[234].green_reg = 2155; + shaper->pwl.rgb_resulted[234].blue_reg = 2155; + shaper->pwl.rgb_resulted[234].delta_red_reg = 199; + shaper->pwl.rgb_resulted[234].delta_green_reg = 199; + shaper->pwl.rgb_resulted[234].delta_blue_reg = 199; + shaper->pwl.rgb_resulted[235].red_reg = 2354; + shaper->pwl.rgb_resulted[235].green_reg = 2354; + shaper->pwl.rgb_resulted[235].blue_reg = 2354; + shaper->pwl.rgb_resulted[235].delta_red_reg = 197; + shaper->pwl.rgb_resulted[235].delta_green_reg = 197; + shaper->pwl.rgb_resulted[235].delta_blue_reg = 197; + shaper->pwl.rgb_resulted[236].red_reg = 2551; + shaper->pwl.rgb_resulted[236].green_reg = 2551; + shaper->pwl.rgb_resulted[236].blue_reg = 2551; + shaper->pwl.rgb_resulted[236].delta_red_reg = 194; + shaper->pwl.rgb_resulted[236].delta_green_reg = 194; + shaper->pwl.rgb_resulted[236].delta_blue_reg = 194; + shaper->pwl.rgb_resulted[237].red_reg = 2745; + shaper->pwl.rgb_resulted[237].green_reg = 2745; + shaper->pwl.rgb_resulted[237].blue_reg = 2745; + shaper->pwl.rgb_resulted[237].delta_red_reg = 192; + shaper->pwl.rgb_resulted[237].delta_green_reg = 192; + shaper->pwl.rgb_resulted[237].delta_blue_reg = 192; + shaper->pwl.rgb_resulted[238].red_reg = 2937; + shaper->pwl.rgb_resulted[238].green_reg = 2937; + shaper->pwl.rgb_resulted[238].blue_reg = 2937; + shaper->pwl.rgb_resulted[238].delta_red_reg = 190; + shaper->pwl.rgb_resulted[238].delta_green_reg = 190; + shaper->pwl.rgb_resulted[238].delta_blue_reg = 190; + shaper->pwl.rgb_resulted[239].red_reg = 3127; + shaper->pwl.rgb_resulted[239].green_reg = 3127; + shaper->pwl.rgb_resulted[239].blue_reg = 3127; + shaper->pwl.rgb_resulted[239].delta_red_reg = 188; + shaper->pwl.rgb_resulted[239].delta_green_reg = 188; + shaper->pwl.rgb_resulted[239].delta_blue_reg = 188; + shaper->pwl.rgb_resulted[240].red_reg = 3315; + shaper->pwl.rgb_resulted[240].green_reg = 3315; + shaper->pwl.rgb_resulted[240].blue_reg = 3315; + shaper->pwl.rgb_resulted[240].delta_red_reg = 185; + shaper->pwl.rgb_resulted[240].delta_green_reg = 185; + shaper->pwl.rgb_resulted[240].delta_blue_reg = 185; + shaper->pwl.rgb_resulted[241].red_reg = 3500; + shaper->pwl.rgb_resulted[241].green_reg = 3500; + shaper->pwl.rgb_resulted[241].blue_reg = 3500; + shaper->pwl.rgb_resulted[241].delta_red_reg = 184; + shaper->pwl.rgb_resulted[241].delta_green_reg = 184; + shaper->pwl.rgb_resulted[241].delta_blue_reg = 184; + shaper->pwl.rgb_resulted[242].red_reg = 3684; + shaper->pwl.rgb_resulted[242].green_reg = 3684; + shaper->pwl.rgb_resulted[242].blue_reg = 3684; + shaper->pwl.rgb_resulted[242].delta_red_reg = 181; + shaper->pwl.rgb_resulted[242].delta_green_reg = 181; + shaper->pwl.rgb_resulted[242].delta_blue_reg = 181; + shaper->pwl.rgb_resulted[243].red_reg = 3865; + shaper->pwl.rgb_resulted[243].green_reg = 3865; + shaper->pwl.rgb_resulted[243].blue_reg = 3865; + shaper->pwl.rgb_resulted[243].delta_red_reg = 179; + shaper->pwl.rgb_resulted[243].delta_green_reg = 179; + shaper->pwl.rgb_resulted[243].delta_blue_reg = 179; + shaper->pwl.rgb_resulted[244].red_reg = 4044; + shaper->pwl.rgb_resulted[244].green_reg = 4044; + shaper->pwl.rgb_resulted[244].blue_reg = 4044; + shaper->pwl.rgb_resulted[244].delta_red_reg = 178; + shaper->pwl.rgb_resulted[244].delta_green_reg = 178; + shaper->pwl.rgb_resulted[244].delta_blue_reg = 178; + shaper->pwl.rgb_resulted[245].red_reg = 4222; + shaper->pwl.rgb_resulted[245].green_reg = 4222; + shaper->pwl.rgb_resulted[245].blue_reg = 4222; + shaper->pwl.rgb_resulted[245].delta_red_reg = 176; + shaper->pwl.rgb_resulted[245].delta_green_reg = 176; + shaper->pwl.rgb_resulted[245].delta_blue_reg = 176; + shaper->pwl.rgb_resulted[246].red_reg = 4398; + shaper->pwl.rgb_resulted[246].green_reg = 4398; + shaper->pwl.rgb_resulted[246].blue_reg = 4398; + shaper->pwl.rgb_resulted[246].delta_red_reg = 174; + shaper->pwl.rgb_resulted[246].delta_green_reg = 174; + shaper->pwl.rgb_resulted[246].delta_blue_reg = 174; + shaper->pwl.rgb_resulted[247].red_reg = 4572; + shaper->pwl.rgb_resulted[247].green_reg = 4572; + shaper->pwl.rgb_resulted[247].blue_reg = 4572; + shaper->pwl.rgb_resulted[247].delta_red_reg = 172; + shaper->pwl.rgb_resulted[247].delta_green_reg = 172; + shaper->pwl.rgb_resulted[247].delta_blue_reg = 172; + shaper->pwl.rgb_resulted[248].red_reg = 4744; + shaper->pwl.rgb_resulted[248].green_reg = 4744; + shaper->pwl.rgb_resulted[248].blue_reg = 4744; + shaper->pwl.rgb_resulted[248].delta_red_reg = 171; + shaper->pwl.rgb_resulted[248].delta_green_reg = 171; + shaper->pwl.rgb_resulted[248].delta_blue_reg = 171; + shaper->pwl.rgb_resulted[249].red_reg = 4915; + shaper->pwl.rgb_resulted[249].green_reg = 4915; + shaper->pwl.rgb_resulted[249].blue_reg = 4915; + shaper->pwl.rgb_resulted[249].delta_red_reg = 169; + shaper->pwl.rgb_resulted[249].delta_green_reg = 169; + shaper->pwl.rgb_resulted[249].delta_blue_reg = 169; + shaper->pwl.rgb_resulted[250].red_reg = 5084; + shaper->pwl.rgb_resulted[250].green_reg = 5084; + shaper->pwl.rgb_resulted[250].blue_reg = 5084; + shaper->pwl.rgb_resulted[250].delta_red_reg = 168; + shaper->pwl.rgb_resulted[250].delta_green_reg = 168; + shaper->pwl.rgb_resulted[250].delta_blue_reg = 168; + shaper->pwl.rgb_resulted[251].red_reg = 5252; + shaper->pwl.rgb_resulted[251].green_reg = 5252; + shaper->pwl.rgb_resulted[251].blue_reg = 5252; + shaper->pwl.rgb_resulted[251].delta_red_reg = 165; + shaper->pwl.rgb_resulted[251].delta_green_reg = 165; + shaper->pwl.rgb_resulted[251].delta_blue_reg = 165; + shaper->pwl.rgb_resulted[252].red_reg = 5417; + shaper->pwl.rgb_resulted[252].green_reg = 5417; + shaper->pwl.rgb_resulted[252].blue_reg = 5417; + shaper->pwl.rgb_resulted[252].delta_red_reg = 165; + shaper->pwl.rgb_resulted[252].delta_green_reg = 165; + shaper->pwl.rgb_resulted[252].delta_blue_reg = 165; + shaper->pwl.rgb_resulted[253].red_reg = 5582; + shaper->pwl.rgb_resulted[253].green_reg = 5582; + shaper->pwl.rgb_resulted[253].blue_reg = 5582; + shaper->pwl.rgb_resulted[253].delta_red_reg = 163; + shaper->pwl.rgb_resulted[253].delta_green_reg = 163; + shaper->pwl.rgb_resulted[253].delta_blue_reg = 163; + shaper->pwl.rgb_resulted[254].red_reg = 5745; + shaper->pwl.rgb_resulted[254].green_reg = 5745; + shaper->pwl.rgb_resulted[254].blue_reg = 5745; + shaper->pwl.rgb_resulted[254].delta_red_reg = 161; + shaper->pwl.rgb_resulted[254].delta_green_reg = 161; + shaper->pwl.rgb_resulted[254].delta_blue_reg = 161; + shaper->pwl.rgb_resulted[255].red_reg = 5906; + shaper->pwl.rgb_resulted[255].green_reg = 5906; + shaper->pwl.rgb_resulted[255].blue_reg = 5906; + shaper->pwl.rgb_resulted[255].delta_red_reg = 0; + shaper->pwl.rgb_resulted[255].delta_green_reg = 0; + shaper->pwl.rgb_resulted[255].delta_blue_reg = 0; + shaper->pwl.rgb_resulted[256].red_reg = 0; + shaper->pwl.rgb_resulted[256].green_reg = 0; + shaper->pwl.rgb_resulted[256].blue_reg = 0; + shaper->pwl.rgb_resulted[256].delta_red_reg = 0; + shaper->pwl.rgb_resulted[256].delta_green_reg = 0; + shaper->pwl.rgb_resulted[256].delta_blue_reg = 0; + shaper->pwl.rgb_resulted[257].red_reg = 0; + shaper->pwl.rgb_resulted[257].green_reg = 0; + shaper->pwl.rgb_resulted[257].blue_reg = 0; + shaper->pwl.rgb_resulted[257].delta_red_reg = 0; + shaper->pwl.rgb_resulted[257].delta_green_reg = 0; + shaper->pwl.rgb_resulted[257].delta_blue_reg = 0; + shaper->pwl.rgb_resulted[258].red_reg = 0; + shaper->pwl.rgb_resulted[258].green_reg = 0; + shaper->pwl.rgb_resulted[258].blue_reg = 0; + shaper->pwl.rgb_resulted[258].delta_red_reg = 0; + shaper->pwl.rgb_resulted[258].delta_green_reg = 0; + shaper->pwl.rgb_resulted[258].delta_blue_reg = 0; + + return true; +} + +bool build_test_post1dlut_sdr(struct transfer_func *post1D) +{ + if (post1D == NULL) + return false; + + memset(post1D, 0, sizeof(struct transfer_func)); + + post1D->type = TF_TYPE_DISTRIBUTED_POINTS; + post1D->tf = TRANSFER_FUNC_SRGB; // see comment for shaper - actually 2.2, but irrelevant when + // distributed points used + post1D->sdr_ref_white_level = 80; + + post1D->tf_pts.red[0].value = 0; + post1D->tf_pts.green[0].value = 0; + post1D->tf_pts.blue[0].value = 0; + post1D->tf_pts.red[1].value = 0; + post1D->tf_pts.green[1].value = 0; + post1D->tf_pts.blue[1].value = 0; + post1D->tf_pts.red[2].value = 0; + post1D->tf_pts.green[2].value = 0; + post1D->tf_pts.blue[2].value = 0; + post1D->tf_pts.red[3].value = 0; + post1D->tf_pts.green[3].value = 0; + post1D->tf_pts.blue[3].value = 0; + post1D->tf_pts.red[4].value = 0; + post1D->tf_pts.green[4].value = 0; + post1D->tf_pts.blue[4].value = 0; + post1D->tf_pts.red[5].value = 0; + post1D->tf_pts.green[5].value = 0; + post1D->tf_pts.blue[5].value = 0; + post1D->tf_pts.red[6].value = 0; + post1D->tf_pts.green[6].value = 0; + post1D->tf_pts.blue[6].value = 0; + post1D->tf_pts.red[7].value = 0; + post1D->tf_pts.green[7].value = 0; + post1D->tf_pts.blue[7].value = 0; + post1D->tf_pts.red[8].value = 0; + post1D->tf_pts.green[8].value = 0; + post1D->tf_pts.blue[8].value = 0; + post1D->tf_pts.red[9].value = 0; + post1D->tf_pts.green[9].value = 0; + post1D->tf_pts.blue[9].value = 0; + post1D->tf_pts.red[10].value = 0; + post1D->tf_pts.green[10].value = 0; + post1D->tf_pts.blue[10].value = 0; + post1D->tf_pts.red[11].value = 0; + post1D->tf_pts.green[11].value = 0; + post1D->tf_pts.blue[11].value = 0; + post1D->tf_pts.red[12].value = 0; + post1D->tf_pts.green[12].value = 0; + post1D->tf_pts.blue[12].value = 0; + post1D->tf_pts.red[13].value = 0; + post1D->tf_pts.green[13].value = 0; + post1D->tf_pts.blue[13].value = 0; + post1D->tf_pts.red[14].value = 0; + post1D->tf_pts.green[14].value = 0; + post1D->tf_pts.blue[14].value = 0; + post1D->tf_pts.red[15].value = 0; + post1D->tf_pts.green[15].value = 0; + post1D->tf_pts.blue[15].value = 0; + post1D->tf_pts.red[16].value = 0; + post1D->tf_pts.green[16].value = 0; + post1D->tf_pts.blue[16].value = 0; + post1D->tf_pts.red[17].value = 0; + post1D->tf_pts.green[17].value = 0; + post1D->tf_pts.blue[17].value = 0; + post1D->tf_pts.red[18].value = 0; + post1D->tf_pts.green[18].value = 0; + post1D->tf_pts.blue[18].value = 0; + post1D->tf_pts.red[19].value = 0; + post1D->tf_pts.green[19].value = 0; + post1D->tf_pts.blue[19].value = 0; + post1D->tf_pts.red[20].value = 0; + post1D->tf_pts.green[20].value = 0; + post1D->tf_pts.blue[20].value = 0; + post1D->tf_pts.red[21].value = 0; + post1D->tf_pts.green[21].value = 0; + post1D->tf_pts.blue[21].value = 0; + post1D->tf_pts.red[22].value = 0; + post1D->tf_pts.green[22].value = 0; + post1D->tf_pts.blue[22].value = 0; + post1D->tf_pts.red[23].value = 0; + post1D->tf_pts.green[23].value = 0; + post1D->tf_pts.blue[23].value = 0; + post1D->tf_pts.red[24].value = 0; + post1D->tf_pts.green[24].value = 0; + post1D->tf_pts.blue[24].value = 0; + post1D->tf_pts.red[25].value = 0; + post1D->tf_pts.green[25].value = 0; + post1D->tf_pts.blue[25].value = 0; + post1D->tf_pts.red[26].value = 0; + post1D->tf_pts.green[26].value = 0; + post1D->tf_pts.blue[26].value = 0; + post1D->tf_pts.red[27].value = 0; + post1D->tf_pts.green[27].value = 0; + post1D->tf_pts.blue[27].value = 0; + post1D->tf_pts.red[28].value = 0; + post1D->tf_pts.green[28].value = 0; + post1D->tf_pts.blue[28].value = 0; + post1D->tf_pts.red[29].value = 0; + post1D->tf_pts.green[29].value = 0; + post1D->tf_pts.blue[29].value = 0; + post1D->tf_pts.red[30].value = 0; + post1D->tf_pts.green[30].value = 0; + post1D->tf_pts.blue[30].value = 0; + post1D->tf_pts.red[31].value = 0; + post1D->tf_pts.green[31].value = 0; + post1D->tf_pts.blue[31].value = 0; + post1D->tf_pts.red[32].value = 0; + post1D->tf_pts.green[32].value = 0; + post1D->tf_pts.blue[32].value = 0; + post1D->tf_pts.red[33].value = 0; + post1D->tf_pts.green[33].value = 0; + post1D->tf_pts.blue[33].value = 0; + post1D->tf_pts.red[34].value = 0; + post1D->tf_pts.green[34].value = 0; + post1D->tf_pts.blue[34].value = 0; + post1D->tf_pts.red[35].value = 0; + post1D->tf_pts.green[35].value = 0; + post1D->tf_pts.blue[35].value = 0; + post1D->tf_pts.red[36].value = 0; + post1D->tf_pts.green[36].value = 0; + post1D->tf_pts.blue[36].value = 0; + post1D->tf_pts.red[37].value = 0; + post1D->tf_pts.green[37].value = 0; + post1D->tf_pts.blue[37].value = 0; + post1D->tf_pts.red[38].value = 0; + post1D->tf_pts.green[38].value = 0; + post1D->tf_pts.blue[38].value = 0; + post1D->tf_pts.red[39].value = 0; + post1D->tf_pts.green[39].value = 0; + post1D->tf_pts.blue[39].value = 0; + post1D->tf_pts.red[40].value = 0; + post1D->tf_pts.green[40].value = 0; + post1D->tf_pts.blue[40].value = 0; + post1D->tf_pts.red[41].value = 0; + post1D->tf_pts.green[41].value = 0; + post1D->tf_pts.blue[41].value = 0; + post1D->tf_pts.red[42].value = 0; + post1D->tf_pts.green[42].value = 0; + post1D->tf_pts.blue[42].value = 0; + post1D->tf_pts.red[43].value = 0; + post1D->tf_pts.green[43].value = 0; + post1D->tf_pts.blue[43].value = 0; + post1D->tf_pts.red[44].value = 0; + post1D->tf_pts.green[44].value = 0; + post1D->tf_pts.blue[44].value = 0; + post1D->tf_pts.red[45].value = 0; + post1D->tf_pts.green[45].value = 0; + post1D->tf_pts.blue[45].value = 0; + post1D->tf_pts.red[46].value = 0; + post1D->tf_pts.green[46].value = 0; + post1D->tf_pts.blue[46].value = 0; + post1D->tf_pts.red[47].value = 0; + post1D->tf_pts.green[47].value = 0; + post1D->tf_pts.blue[47].value = 0; + post1D->tf_pts.red[48].value = 0; + post1D->tf_pts.green[48].value = 0; + post1D->tf_pts.blue[48].value = 0; + post1D->tf_pts.red[49].value = 0; + post1D->tf_pts.green[49].value = 0; + post1D->tf_pts.blue[49].value = 0; + post1D->tf_pts.red[50].value = 0; + post1D->tf_pts.green[50].value = 0; + post1D->tf_pts.blue[50].value = 0; + post1D->tf_pts.red[51].value = 0; + post1D->tf_pts.green[51].value = 0; + post1D->tf_pts.blue[51].value = 0; + post1D->tf_pts.red[52].value = 0; + post1D->tf_pts.green[52].value = 0; + post1D->tf_pts.blue[52].value = 0; + post1D->tf_pts.red[53].value = 0; + post1D->tf_pts.green[53].value = 0; + post1D->tf_pts.blue[53].value = 0; + post1D->tf_pts.red[54].value = 0; + post1D->tf_pts.green[54].value = 0; + post1D->tf_pts.blue[54].value = 0; + post1D->tf_pts.red[55].value = 0; + post1D->tf_pts.green[55].value = 0; + post1D->tf_pts.blue[55].value = 0; + post1D->tf_pts.red[56].value = 0; + post1D->tf_pts.green[56].value = 0; + post1D->tf_pts.blue[56].value = 0; + post1D->tf_pts.red[57].value = 0; + post1D->tf_pts.green[57].value = 0; + post1D->tf_pts.blue[57].value = 0; + post1D->tf_pts.red[58].value = 0; + post1D->tf_pts.green[58].value = 0; + post1D->tf_pts.blue[58].value = 0; + post1D->tf_pts.red[59].value = 0; + post1D->tf_pts.green[59].value = 0; + post1D->tf_pts.blue[59].value = 0; + post1D->tf_pts.red[60].value = 0; + post1D->tf_pts.green[60].value = 0; + post1D->tf_pts.blue[60].value = 0; + post1D->tf_pts.red[61].value = 0; + post1D->tf_pts.green[61].value = 0; + post1D->tf_pts.blue[61].value = 0; + post1D->tf_pts.red[62].value = 0; + post1D->tf_pts.green[62].value = 0; + post1D->tf_pts.blue[62].value = 0; + post1D->tf_pts.red[63].value = 0; + post1D->tf_pts.green[63].value = 0; + post1D->tf_pts.blue[63].value = 0; + post1D->tf_pts.red[64].value = 0; + post1D->tf_pts.green[64].value = 0; + post1D->tf_pts.blue[64].value = 0; + post1D->tf_pts.red[65].value = 0; + post1D->tf_pts.green[65].value = 0; + post1D->tf_pts.blue[65].value = 0; + post1D->tf_pts.red[66].value = 0; + post1D->tf_pts.green[66].value = 0; + post1D->tf_pts.blue[66].value = 0; + post1D->tf_pts.red[67].value = 0; + post1D->tf_pts.green[67].value = 0; + post1D->tf_pts.blue[67].value = 0; + post1D->tf_pts.red[68].value = 0; + post1D->tf_pts.green[68].value = 0; + post1D->tf_pts.blue[68].value = 0; + post1D->tf_pts.red[69].value = 0; + post1D->tf_pts.green[69].value = 0; + post1D->tf_pts.blue[69].value = 0; + post1D->tf_pts.red[70].value = 0; + post1D->tf_pts.green[70].value = 0; + post1D->tf_pts.blue[70].value = 0; + post1D->tf_pts.red[71].value = 0; + post1D->tf_pts.green[71].value = 0; + post1D->tf_pts.blue[71].value = 0; + post1D->tf_pts.red[72].value = 0; + post1D->tf_pts.green[72].value = 0; + post1D->tf_pts.blue[72].value = 0; + post1D->tf_pts.red[73].value = 0; + post1D->tf_pts.green[73].value = 0; + post1D->tf_pts.blue[73].value = 0; + post1D->tf_pts.red[74].value = 0; + post1D->tf_pts.green[74].value = 0; + post1D->tf_pts.blue[74].value = 0; + post1D->tf_pts.red[75].value = 0; + post1D->tf_pts.green[75].value = 0; + post1D->tf_pts.blue[75].value = 0; + post1D->tf_pts.red[76].value = 0; + post1D->tf_pts.green[76].value = 0; + post1D->tf_pts.blue[76].value = 0; + post1D->tf_pts.red[77].value = 0; + post1D->tf_pts.green[77].value = 0; + post1D->tf_pts.blue[77].value = 0; + post1D->tf_pts.red[78].value = 0; + post1D->tf_pts.green[78].value = 0; + post1D->tf_pts.blue[78].value = 0; + post1D->tf_pts.red[79].value = 0; + post1D->tf_pts.green[79].value = 0; + post1D->tf_pts.blue[79].value = 0; + post1D->tf_pts.red[80].value = 0; + post1D->tf_pts.green[80].value = 0; + post1D->tf_pts.blue[80].value = 0; + post1D->tf_pts.red[81].value = 0; + post1D->tf_pts.green[81].value = 0; + post1D->tf_pts.blue[81].value = 0; + post1D->tf_pts.red[82].value = 0; + post1D->tf_pts.green[82].value = 0; + post1D->tf_pts.blue[82].value = 0; + post1D->tf_pts.red[83].value = 0; + post1D->tf_pts.green[83].value = 0; + post1D->tf_pts.blue[83].value = 0; + post1D->tf_pts.red[84].value = 0; + post1D->tf_pts.green[84].value = 0; + post1D->tf_pts.blue[84].value = 0; + post1D->tf_pts.red[85].value = 0; + post1D->tf_pts.green[85].value = 0; + post1D->tf_pts.blue[85].value = 0; + post1D->tf_pts.red[86].value = 0; + post1D->tf_pts.green[86].value = 0; + post1D->tf_pts.blue[86].value = 0; + post1D->tf_pts.red[87].value = 0; + post1D->tf_pts.green[87].value = 0; + post1D->tf_pts.blue[87].value = 0; + post1D->tf_pts.red[88].value = 0; + post1D->tf_pts.green[88].value = 0; + post1D->tf_pts.blue[88].value = 0; + post1D->tf_pts.red[89].value = 0; + post1D->tf_pts.green[89].value = 0; + post1D->tf_pts.blue[89].value = 0; + post1D->tf_pts.red[90].value = 0; + post1D->tf_pts.green[90].value = 0; + post1D->tf_pts.blue[90].value = 0; + post1D->tf_pts.red[91].value = 0; + post1D->tf_pts.green[91].value = 0; + post1D->tf_pts.blue[91].value = 0; + post1D->tf_pts.red[92].value = 0; + post1D->tf_pts.green[92].value = 0; + post1D->tf_pts.blue[92].value = 0; + post1D->tf_pts.red[93].value = 0; + post1D->tf_pts.green[93].value = 0; + post1D->tf_pts.blue[93].value = 0; + post1D->tf_pts.red[94].value = 0; + post1D->tf_pts.green[94].value = 0; + post1D->tf_pts.blue[94].value = 0; + post1D->tf_pts.red[95].value = 0; + post1D->tf_pts.green[95].value = 0; + post1D->tf_pts.blue[95].value = 0; + post1D->tf_pts.red[96].value = 0; + post1D->tf_pts.green[96].value = 0; + post1D->tf_pts.blue[96].value = 0; + post1D->tf_pts.red[97].value = 0; + post1D->tf_pts.green[97].value = 0; + post1D->tf_pts.blue[97].value = 0; + post1D->tf_pts.red[98].value = 0; + post1D->tf_pts.green[98].value = 0; + post1D->tf_pts.blue[98].value = 0; + post1D->tf_pts.red[99].value = 0; + post1D->tf_pts.green[99].value = 0; + post1D->tf_pts.blue[99].value = 0; + post1D->tf_pts.red[100].value = 0; + post1D->tf_pts.green[100].value = 0; + post1D->tf_pts.blue[100].value = 0; + post1D->tf_pts.red[101].value = 0; + post1D->tf_pts.green[101].value = 0; + post1D->tf_pts.blue[101].value = 0; + post1D->tf_pts.red[102].value = 0; + post1D->tf_pts.green[102].value = 0; + post1D->tf_pts.blue[102].value = 0; + post1D->tf_pts.red[103].value = 0; + post1D->tf_pts.green[103].value = 0; + post1D->tf_pts.blue[103].value = 0; + post1D->tf_pts.red[104].value = 0; + post1D->tf_pts.green[104].value = 0; + post1D->tf_pts.blue[104].value = 0; + post1D->tf_pts.red[105].value = 0; + post1D->tf_pts.green[105].value = 0; + post1D->tf_pts.blue[105].value = 0; + post1D->tf_pts.red[106].value = 0; + post1D->tf_pts.green[106].value = 0; + post1D->tf_pts.blue[106].value = 0; + post1D->tf_pts.red[107].value = 0; + post1D->tf_pts.green[107].value = 0; + post1D->tf_pts.blue[107].value = 0; + post1D->tf_pts.red[108].value = 0; + post1D->tf_pts.green[108].value = 0; + post1D->tf_pts.blue[108].value = 0; + post1D->tf_pts.red[109].value = 0; + post1D->tf_pts.green[109].value = 0; + post1D->tf_pts.blue[109].value = 0; + post1D->tf_pts.red[110].value = 0; + post1D->tf_pts.green[110].value = 0; + post1D->tf_pts.blue[110].value = 0; + post1D->tf_pts.red[111].value = 0; + post1D->tf_pts.green[111].value = 0; + post1D->tf_pts.blue[111].value = 0; + post1D->tf_pts.red[112].value = 0; + post1D->tf_pts.green[112].value = 0; + post1D->tf_pts.blue[112].value = 0; + post1D->tf_pts.red[113].value = 0; + post1D->tf_pts.green[113].value = 0; + post1D->tf_pts.blue[113].value = 0; + post1D->tf_pts.red[114].value = 0; + post1D->tf_pts.green[114].value = 0; + post1D->tf_pts.blue[114].value = 0; + post1D->tf_pts.red[115].value = 0; + post1D->tf_pts.green[115].value = 0; + post1D->tf_pts.blue[115].value = 0; + post1D->tf_pts.red[116].value = 0; + post1D->tf_pts.green[116].value = 0; + post1D->tf_pts.blue[116].value = 0; + post1D->tf_pts.red[117].value = 0; + post1D->tf_pts.green[117].value = 0; + post1D->tf_pts.blue[117].value = 0; + post1D->tf_pts.red[118].value = 0; + post1D->tf_pts.green[118].value = 0; + post1D->tf_pts.blue[118].value = 0; + post1D->tf_pts.red[119].value = 0; + post1D->tf_pts.green[119].value = 0; + post1D->tf_pts.blue[119].value = 0; + post1D->tf_pts.red[120].value = 0; + post1D->tf_pts.green[120].value = 0; + post1D->tf_pts.blue[120].value = 0; + post1D->tf_pts.red[121].value = 0; + post1D->tf_pts.green[121].value = 0; + post1D->tf_pts.blue[121].value = 0; + post1D->tf_pts.red[122].value = 0; + post1D->tf_pts.green[122].value = 0; + post1D->tf_pts.blue[122].value = 0; + post1D->tf_pts.red[123].value = 0; + post1D->tf_pts.green[123].value = 0; + post1D->tf_pts.blue[123].value = 0; + post1D->tf_pts.red[124].value = 0; + post1D->tf_pts.green[124].value = 0; + post1D->tf_pts.blue[124].value = 0; + post1D->tf_pts.red[125].value = 0; + post1D->tf_pts.green[125].value = 0; + post1D->tf_pts.blue[125].value = 0; + post1D->tf_pts.red[126].value = 0; + post1D->tf_pts.green[126].value = 0; + post1D->tf_pts.blue[126].value = 0; + post1D->tf_pts.red[127].value = 0; + post1D->tf_pts.green[127].value = 0; + post1D->tf_pts.blue[127].value = 0; + post1D->tf_pts.red[128].value = 0; + post1D->tf_pts.green[128].value = 0; + post1D->tf_pts.blue[128].value = 0; + post1D->tf_pts.red[129].value = 0; + post1D->tf_pts.green[129].value = 0; + post1D->tf_pts.blue[129].value = 0; + post1D->tf_pts.red[130].value = 0; + post1D->tf_pts.green[130].value = 0; + post1D->tf_pts.blue[130].value = 0; + post1D->tf_pts.red[131].value = 0; + post1D->tf_pts.green[131].value = 0; + post1D->tf_pts.blue[131].value = 0; + post1D->tf_pts.red[132].value = 0; + post1D->tf_pts.green[132].value = 0; + post1D->tf_pts.blue[132].value = 0; + post1D->tf_pts.red[133].value = 0; + post1D->tf_pts.green[133].value = 0; + post1D->tf_pts.blue[133].value = 0; + post1D->tf_pts.red[134].value = 0; + post1D->tf_pts.green[134].value = 0; + post1D->tf_pts.blue[134].value = 0; + post1D->tf_pts.red[135].value = 0; + post1D->tf_pts.green[135].value = 0; + post1D->tf_pts.blue[135].value = 0; + post1D->tf_pts.red[136].value = 0; + post1D->tf_pts.green[136].value = 0; + post1D->tf_pts.blue[136].value = 0; + post1D->tf_pts.red[137].value = 0; + post1D->tf_pts.green[137].value = 0; + post1D->tf_pts.blue[137].value = 0; + post1D->tf_pts.red[138].value = 0; + post1D->tf_pts.green[138].value = 0; + post1D->tf_pts.blue[138].value = 0; + post1D->tf_pts.red[139].value = 0; + post1D->tf_pts.green[139].value = 0; + post1D->tf_pts.blue[139].value = 0; + post1D->tf_pts.red[140].value = 0; + post1D->tf_pts.green[140].value = 0; + post1D->tf_pts.blue[140].value = 0; + post1D->tf_pts.red[141].value = 0; + post1D->tf_pts.green[141].value = 0; + post1D->tf_pts.blue[141].value = 0; + post1D->tf_pts.red[142].value = 0; + post1D->tf_pts.green[142].value = 0; + post1D->tf_pts.blue[142].value = 0; + post1D->tf_pts.red[143].value = 0; + post1D->tf_pts.green[143].value = 0; + post1D->tf_pts.blue[143].value = 0; + post1D->tf_pts.red[144].value = 0; + post1D->tf_pts.green[144].value = 0; + post1D->tf_pts.blue[144].value = 0; + post1D->tf_pts.red[145].value = 0; + post1D->tf_pts.green[145].value = 0; + post1D->tf_pts.blue[145].value = 0; + post1D->tf_pts.red[146].value = 0; + post1D->tf_pts.green[146].value = 0; + post1D->tf_pts.blue[146].value = 0; + post1D->tf_pts.red[147].value = 0; + post1D->tf_pts.green[147].value = 0; + post1D->tf_pts.blue[147].value = 0; + post1D->tf_pts.red[148].value = 0; + post1D->tf_pts.green[148].value = 0; + post1D->tf_pts.blue[148].value = 0; + post1D->tf_pts.red[149].value = 0; + post1D->tf_pts.green[149].value = 0; + post1D->tf_pts.blue[149].value = 0; + post1D->tf_pts.red[150].value = 0; + post1D->tf_pts.green[150].value = 0; + post1D->tf_pts.blue[150].value = 0; + post1D->tf_pts.red[151].value = 0; + post1D->tf_pts.green[151].value = 0; + post1D->tf_pts.blue[151].value = 0; + post1D->tf_pts.red[152].value = 0; + post1D->tf_pts.green[152].value = 0; + post1D->tf_pts.blue[152].value = 0; + post1D->tf_pts.red[153].value = 0; + post1D->tf_pts.green[153].value = 0; + post1D->tf_pts.blue[153].value = 0; + post1D->tf_pts.red[154].value = 0; + post1D->tf_pts.green[154].value = 0; + post1D->tf_pts.blue[154].value = 0; + post1D->tf_pts.red[155].value = 0; + post1D->tf_pts.green[155].value = 0; + post1D->tf_pts.blue[155].value = 0; + post1D->tf_pts.red[156].value = 0; + post1D->tf_pts.green[156].value = 0; + post1D->tf_pts.blue[156].value = 0; + post1D->tf_pts.red[157].value = 0; + post1D->tf_pts.green[157].value = 0; + post1D->tf_pts.blue[157].value = 0; + post1D->tf_pts.red[158].value = 0; + post1D->tf_pts.green[158].value = 0; + post1D->tf_pts.blue[158].value = 0; + post1D->tf_pts.red[159].value = 0; + post1D->tf_pts.green[159].value = 0; + post1D->tf_pts.blue[159].value = 0; + post1D->tf_pts.red[160].value = 0; + post1D->tf_pts.green[160].value = 0; + post1D->tf_pts.blue[160].value = 0; + post1D->tf_pts.red[161].value = 0; + post1D->tf_pts.green[161].value = 0; + post1D->tf_pts.blue[161].value = 0; + post1D->tf_pts.red[162].value = 0; + post1D->tf_pts.green[162].value = 0; + post1D->tf_pts.blue[162].value = 0; + post1D->tf_pts.red[163].value = 0; + post1D->tf_pts.green[163].value = 0; + post1D->tf_pts.blue[163].value = 0; + post1D->tf_pts.red[164].value = 0; + post1D->tf_pts.green[164].value = 0; + post1D->tf_pts.blue[164].value = 0; + post1D->tf_pts.red[165].value = 0; + post1D->tf_pts.green[165].value = 0; + post1D->tf_pts.blue[165].value = 0; + post1D->tf_pts.red[166].value = 0; + post1D->tf_pts.green[166].value = 0; + post1D->tf_pts.blue[166].value = 0; + post1D->tf_pts.red[167].value = 0; + post1D->tf_pts.green[167].value = 0; + post1D->tf_pts.blue[167].value = 0; + post1D->tf_pts.red[168].value = 0; + post1D->tf_pts.green[168].value = 0; + post1D->tf_pts.blue[168].value = 0; + post1D->tf_pts.red[169].value = 0; + post1D->tf_pts.green[169].value = 0; + post1D->tf_pts.blue[169].value = 0; + post1D->tf_pts.red[170].value = 0; + post1D->tf_pts.green[170].value = 0; + post1D->tf_pts.blue[170].value = 0; + post1D->tf_pts.red[171].value = 0; + post1D->tf_pts.green[171].value = 0; + post1D->tf_pts.blue[171].value = 0; + post1D->tf_pts.red[172].value = 0; + post1D->tf_pts.green[172].value = 0; + post1D->tf_pts.blue[172].value = 0; + post1D->tf_pts.red[173].value = 0; + post1D->tf_pts.green[173].value = 0; + post1D->tf_pts.blue[173].value = 0; + post1D->tf_pts.red[174].value = 0; + post1D->tf_pts.green[174].value = 0; + post1D->tf_pts.blue[174].value = 0; + post1D->tf_pts.red[175].value = 0; + post1D->tf_pts.green[175].value = 0; + post1D->tf_pts.blue[175].value = 0; + post1D->tf_pts.red[176].value = 0; + post1D->tf_pts.green[176].value = 0; + post1D->tf_pts.blue[176].value = 0; + post1D->tf_pts.red[177].value = 0; + post1D->tf_pts.green[177].value = 0; + post1D->tf_pts.blue[177].value = 0; + post1D->tf_pts.red[178].value = 0; + post1D->tf_pts.green[178].value = 0; + post1D->tf_pts.blue[178].value = 0; + post1D->tf_pts.red[179].value = 0; + post1D->tf_pts.green[179].value = 0; + post1D->tf_pts.blue[179].value = 0; + post1D->tf_pts.red[180].value = 0; + post1D->tf_pts.green[180].value = 0; + post1D->tf_pts.blue[180].value = 0; + post1D->tf_pts.red[181].value = 0; + post1D->tf_pts.green[181].value = 0; + post1D->tf_pts.blue[181].value = 0; + post1D->tf_pts.red[182].value = 0; + post1D->tf_pts.green[182].value = 0; + post1D->tf_pts.blue[182].value = 0; + post1D->tf_pts.red[183].value = 0; + post1D->tf_pts.green[183].value = 0; + post1D->tf_pts.blue[183].value = 0; + post1D->tf_pts.red[184].value = 0; + post1D->tf_pts.green[184].value = 0; + post1D->tf_pts.blue[184].value = 0; + post1D->tf_pts.red[185].value = 0; + post1D->tf_pts.green[185].value = 0; + post1D->tf_pts.blue[185].value = 0; + post1D->tf_pts.red[186].value = 0; + post1D->tf_pts.green[186].value = 0; + post1D->tf_pts.blue[186].value = 0; + post1D->tf_pts.red[187].value = 0; + post1D->tf_pts.green[187].value = 0; + post1D->tf_pts.blue[187].value = 0; + post1D->tf_pts.red[188].value = 0; + post1D->tf_pts.green[188].value = 0; + post1D->tf_pts.blue[188].value = 0; + post1D->tf_pts.red[189].value = 0; + post1D->tf_pts.green[189].value = 0; + post1D->tf_pts.blue[189].value = 0; + post1D->tf_pts.red[190].value = 0; + post1D->tf_pts.green[190].value = 0; + post1D->tf_pts.blue[190].value = 0; + post1D->tf_pts.red[191].value = 0; + post1D->tf_pts.green[191].value = 0; + post1D->tf_pts.blue[191].value = 0; + post1D->tf_pts.red[192].value = 0; + post1D->tf_pts.green[192].value = 0; + post1D->tf_pts.blue[192].value = 0; + post1D->tf_pts.red[193].value = 0; + post1D->tf_pts.green[193].value = 0; + post1D->tf_pts.blue[193].value = 0; + post1D->tf_pts.red[194].value = 0; + post1D->tf_pts.green[194].value = 0; + post1D->tf_pts.blue[194].value = 0; + post1D->tf_pts.red[195].value = 0; + post1D->tf_pts.green[195].value = 0; + post1D->tf_pts.blue[195].value = 0; + post1D->tf_pts.red[196].value = 0; + post1D->tf_pts.green[196].value = 0; + post1D->tf_pts.blue[196].value = 0; + post1D->tf_pts.red[197].value = 0; + post1D->tf_pts.green[197].value = 0; + post1D->tf_pts.blue[197].value = 0; + post1D->tf_pts.red[198].value = 0; + post1D->tf_pts.green[198].value = 0; + post1D->tf_pts.blue[198].value = 0; + post1D->tf_pts.red[199].value = 0; + post1D->tf_pts.green[199].value = 0; + post1D->tf_pts.blue[199].value = 0; + post1D->tf_pts.red[200].value = 0; + post1D->tf_pts.green[200].value = 0; + post1D->tf_pts.blue[200].value = 0; + post1D->tf_pts.red[201].value = 0; + post1D->tf_pts.green[201].value = 0; + post1D->tf_pts.blue[201].value = 0; + post1D->tf_pts.red[202].value = 0; + post1D->tf_pts.green[202].value = 0; + post1D->tf_pts.blue[202].value = 0; + post1D->tf_pts.red[203].value = 0; + post1D->tf_pts.green[203].value = 0; + post1D->tf_pts.blue[203].value = 0; + post1D->tf_pts.red[204].value = 0; + post1D->tf_pts.green[204].value = 0; + post1D->tf_pts.blue[204].value = 0; + post1D->tf_pts.red[205].value = 0; + post1D->tf_pts.green[205].value = 0; + post1D->tf_pts.blue[205].value = 0; + post1D->tf_pts.red[206].value = 0; + post1D->tf_pts.green[206].value = 0; + post1D->tf_pts.blue[206].value = 0; + post1D->tf_pts.red[207].value = 0; + post1D->tf_pts.green[207].value = 0; + post1D->tf_pts.blue[207].value = 0; + post1D->tf_pts.red[208].value = 49; + post1D->tf_pts.green[208].value = 49; + post1D->tf_pts.blue[208].value = 49; + post1D->tf_pts.red[209].value = 55; + post1D->tf_pts.green[209].value = 55; + post1D->tf_pts.blue[209].value = 55; + post1D->tf_pts.red[210].value = 63; + post1D->tf_pts.green[210].value = 63; + post1D->tf_pts.blue[210].value = 63; + post1D->tf_pts.red[211].value = 71; + post1D->tf_pts.green[211].value = 71; + post1D->tf_pts.blue[211].value = 71; + post1D->tf_pts.red[212].value = 79; + post1D->tf_pts.green[212].value = 79; + post1D->tf_pts.blue[212].value = 79; + post1D->tf_pts.red[213].value = 88; + post1D->tf_pts.green[213].value = 88; + post1D->tf_pts.blue[213].value = 88; + post1D->tf_pts.red[214].value = 98; + post1D->tf_pts.green[214].value = 98; + post1D->tf_pts.blue[214].value = 98; + post1D->tf_pts.red[215].value = 108; + post1D->tf_pts.green[215].value = 108; + post1D->tf_pts.blue[215].value = 108; + post1D->tf_pts.red[216].value = 118; + post1D->tf_pts.green[216].value = 118; + post1D->tf_pts.blue[216].value = 118; + post1D->tf_pts.red[217].value = 129; + post1D->tf_pts.green[217].value = 129; + post1D->tf_pts.blue[217].value = 129; + post1D->tf_pts.red[218].value = 141; + post1D->tf_pts.green[218].value = 141; + post1D->tf_pts.blue[218].value = 141; + post1D->tf_pts.red[219].value = 153; + post1D->tf_pts.green[219].value = 153; + post1D->tf_pts.blue[219].value = 153; + post1D->tf_pts.red[220].value = 166; + post1D->tf_pts.green[220].value = 166; + post1D->tf_pts.blue[220].value = 166; + post1D->tf_pts.red[221].value = 179; + post1D->tf_pts.green[221].value = 179; + post1D->tf_pts.blue[221].value = 179; + post1D->tf_pts.red[222].value = 193; + post1D->tf_pts.green[222].value = 193; + post1D->tf_pts.blue[222].value = 193; + post1D->tf_pts.red[223].value = 208; + post1D->tf_pts.green[223].value = 208; + post1D->tf_pts.blue[223].value = 208; + post1D->tf_pts.red[224].value = 223; + post1D->tf_pts.green[224].value = 223; + post1D->tf_pts.blue[224].value = 223; + post1D->tf_pts.red[225].value = 255; + post1D->tf_pts.green[225].value = 255; + post1D->tf_pts.blue[225].value = 255; + post1D->tf_pts.red[226].value = 289; + post1D->tf_pts.green[226].value = 289; + post1D->tf_pts.blue[226].value = 289; + post1D->tf_pts.red[227].value = 325; + post1D->tf_pts.green[227].value = 325; + post1D->tf_pts.blue[227].value = 325; + post1D->tf_pts.red[228].value = 364; + post1D->tf_pts.green[228].value = 364; + post1D->tf_pts.blue[228].value = 364; + post1D->tf_pts.red[229].value = 405; + post1D->tf_pts.green[229].value = 405; + post1D->tf_pts.blue[229].value = 405; + post1D->tf_pts.red[230].value = 449; + post1D->tf_pts.green[230].value = 449; + post1D->tf_pts.blue[230].value = 449; + post1D->tf_pts.red[231].value = 495; + post1D->tf_pts.green[231].value = 495; + post1D->tf_pts.blue[231].value = 495; + post1D->tf_pts.red[232].value = 544; + post1D->tf_pts.green[232].value = 544; + post1D->tf_pts.blue[232].value = 544; + post1D->tf_pts.red[233].value = 595; + post1D->tf_pts.green[233].value = 595; + post1D->tf_pts.blue[233].value = 595; + post1D->tf_pts.red[234].value = 649; + post1D->tf_pts.green[234].value = 649; + post1D->tf_pts.blue[234].value = 649; + post1D->tf_pts.red[235].value = 705; + post1D->tf_pts.green[235].value = 705; + post1D->tf_pts.blue[235].value = 705; + post1D->tf_pts.red[236].value = 763; + post1D->tf_pts.green[236].value = 763; + post1D->tf_pts.blue[236].value = 763; + post1D->tf_pts.red[237].value = 825; + post1D->tf_pts.green[237].value = 825; + post1D->tf_pts.blue[237].value = 825; + post1D->tf_pts.red[238].value = 888; + post1D->tf_pts.green[238].value = 888; + post1D->tf_pts.blue[238].value = 888; + post1D->tf_pts.red[239].value = 955; + post1D->tf_pts.green[239].value = 955; + post1D->tf_pts.blue[239].value = 955; + post1D->tf_pts.red[240].value = 1024; + post1D->tf_pts.green[240].value = 1024; + post1D->tf_pts.blue[240].value = 1024; + post1D->tf_pts.red[241].value = 1170; + post1D->tf_pts.green[241].value = 1170; + post1D->tf_pts.blue[241].value = 1170; + post1D->tf_pts.red[242].value = 1327; + post1D->tf_pts.green[242].value = 1327; + post1D->tf_pts.blue[242].value = 1327; + post1D->tf_pts.red[243].value = 1494; + post1D->tf_pts.green[243].value = 1494; + post1D->tf_pts.blue[243].value = 1494; + post1D->tf_pts.red[244].value = 1673; + post1D->tf_pts.green[244].value = 1673; + post1D->tf_pts.blue[244].value = 1673; + post1D->tf_pts.red[245].value = 1863; + post1D->tf_pts.green[245].value = 1863; + post1D->tf_pts.blue[245].value = 1863; + post1D->tf_pts.red[246].value = 2063; + post1D->tf_pts.green[246].value = 2063; + post1D->tf_pts.blue[246].value = 2063; + post1D->tf_pts.red[247].value = 2275; + post1D->tf_pts.green[247].value = 2275; + post1D->tf_pts.blue[247].value = 2275; + post1D->tf_pts.red[248].value = 2499; + post1D->tf_pts.green[248].value = 2499; + post1D->tf_pts.blue[248].value = 2499; + post1D->tf_pts.red[249].value = 2733; + post1D->tf_pts.green[249].value = 2733; + post1D->tf_pts.blue[249].value = 2733; + post1D->tf_pts.red[250].value = 2980; + post1D->tf_pts.green[250].value = 2980; + post1D->tf_pts.blue[250].value = 2980; + post1D->tf_pts.red[251].value = 3238; + post1D->tf_pts.green[251].value = 3238; + post1D->tf_pts.blue[251].value = 3238; + post1D->tf_pts.red[252].value = 3507; + post1D->tf_pts.green[252].value = 3507; + post1D->tf_pts.blue[252].value = 3507; + post1D->tf_pts.red[253].value = 3789; + post1D->tf_pts.green[253].value = 3789; + post1D->tf_pts.blue[253].value = 3789; + post1D->tf_pts.red[254].value = 4082; + post1D->tf_pts.green[254].value = 4082; + post1D->tf_pts.blue[254].value = 4082; + post1D->tf_pts.red[255].value = 4388; + post1D->tf_pts.green[255].value = 4388; + post1D->tf_pts.blue[255].value = 4388; + post1D->tf_pts.red[256].value = 4705; + post1D->tf_pts.green[256].value = 4705; + post1D->tf_pts.blue[256].value = 4705; + post1D->tf_pts.red[257].value = 5376; + post1D->tf_pts.green[257].value = 5376; + post1D->tf_pts.blue[257].value = 5376; + post1D->tf_pts.red[258].value = 6097; + post1D->tf_pts.green[258].value = 6097; + post1D->tf_pts.blue[258].value = 6097; + post1D->tf_pts.red[259].value = 6867; + post1D->tf_pts.green[259].value = 6867; + post1D->tf_pts.blue[259].value = 6867; + post1D->tf_pts.red[260].value = 7687; + post1D->tf_pts.green[260].value = 7687; + post1D->tf_pts.blue[260].value = 7687; + post1D->tf_pts.red[261].value = 8558; + post1D->tf_pts.green[261].value = 8558; + post1D->tf_pts.blue[261].value = 8558; + post1D->tf_pts.red[262].value = 9481; + post1D->tf_pts.green[262].value = 9481; + post1D->tf_pts.blue[262].value = 9481; + post1D->tf_pts.red[263].value = 10454; + post1D->tf_pts.green[263].value = 10454; + post1D->tf_pts.blue[263].value = 10454; + post1D->tf_pts.red[264].value = 11481; + post1D->tf_pts.green[264].value = 11481; + post1D->tf_pts.blue[264].value = 11481; + post1D->tf_pts.red[265].value = 12559; + post1D->tf_pts.green[265].value = 12559; + post1D->tf_pts.blue[265].value = 12559; + post1D->tf_pts.red[266].value = 13691; + post1D->tf_pts.green[266].value = 13691; + post1D->tf_pts.blue[266].value = 13691; + post1D->tf_pts.red[267].value = 14877; + post1D->tf_pts.green[267].value = 14877; + post1D->tf_pts.blue[267].value = 14877; + post1D->tf_pts.red[268].value = 16116; + post1D->tf_pts.green[268].value = 16116; + post1D->tf_pts.blue[268].value = 16116; + post1D->tf_pts.red[269].value = 17409; + post1D->tf_pts.green[269].value = 17409; + post1D->tf_pts.blue[269].value = 17409; + post1D->tf_pts.red[270].value = 18757; + post1D->tf_pts.green[270].value = 18757; + post1D->tf_pts.blue[270].value = 18757; + post1D->tf_pts.red[271].value = 20160; + post1D->tf_pts.green[271].value = 20160; + post1D->tf_pts.blue[271].value = 20160; + post1D->tf_pts.red[272].value = 21619; + post1D->tf_pts.green[272].value = 21619; + post1D->tf_pts.blue[272].value = 21619; + post1D->tf_pts.red[273].value = 24703; + post1D->tf_pts.green[273].value = 24703; + post1D->tf_pts.blue[273].value = 24703; + post1D->tf_pts.red[274].value = 28014; + post1D->tf_pts.green[274].value = 28014; + post1D->tf_pts.blue[274].value = 28014; + post1D->tf_pts.red[275].value = 31552; + post1D->tf_pts.green[275].value = 31552; + post1D->tf_pts.blue[275].value = 31552; + post1D->tf_pts.red[276].value = 35321; + post1D->tf_pts.green[276].value = 35321; + post1D->tf_pts.blue[276].value = 35321; + post1D->tf_pts.red[277].value = 39323; + post1D->tf_pts.green[277].value = 39323; + post1D->tf_pts.blue[277].value = 39323; + post1D->tf_pts.red[278].value = 43561; + post1D->tf_pts.green[278].value = 43561; + post1D->tf_pts.blue[278].value = 43561; + post1D->tf_pts.red[279].value = 48036; + post1D->tf_pts.green[279].value = 48036; + post1D->tf_pts.blue[279].value = 48036; + post1D->tf_pts.red[280].value = 52751; + post1D->tf_pts.green[280].value = 52751; + post1D->tf_pts.blue[280].value = 52751; + post1D->tf_pts.red[281].value = 57708; + post1D->tf_pts.green[281].value = 57708; + post1D->tf_pts.blue[281].value = 57708; + post1D->tf_pts.red[282].value = 62909; + post1D->tf_pts.green[282].value = 62909; + post1D->tf_pts.blue[282].value = 62909; + post1D->tf_pts.red[283].value = 68355; + post1D->tf_pts.green[283].value = 68355; + post1D->tf_pts.blue[283].value = 68355; + post1D->tf_pts.red[284].value = 74048; + post1D->tf_pts.green[284].value = 74048; + post1D->tf_pts.blue[284].value = 74048; + post1D->tf_pts.red[285].value = 79991; + post1D->tf_pts.green[285].value = 79991; + post1D->tf_pts.blue[285].value = 79991; + post1D->tf_pts.red[286].value = 86186; + post1D->tf_pts.green[286].value = 86186; + post1D->tf_pts.blue[286].value = 86186; + post1D->tf_pts.red[287].value = 92633; + post1D->tf_pts.green[287].value = 92633; + post1D->tf_pts.blue[287].value = 92633; + post1D->tf_pts.red[288].value = 99334; + post1D->tf_pts.green[288].value = 99334; + post1D->tf_pts.blue[288].value = 99334; + post1D->tf_pts.red[289].value = 113507; + post1D->tf_pts.green[289].value = 113507; + post1D->tf_pts.blue[289].value = 113507; + post1D->tf_pts.red[290].value = 128716; + post1D->tf_pts.green[290].value = 128716; + post1D->tf_pts.blue[290].value = 128716; + post1D->tf_pts.red[291].value = 144975; + post1D->tf_pts.green[291].value = 144975; + post1D->tf_pts.blue[291].value = 144975; + post1D->tf_pts.red[292].value = 162293; + post1D->tf_pts.green[292].value = 162293; + post1D->tf_pts.blue[292].value = 162293; + post1D->tf_pts.red[293].value = 180683; + post1D->tf_pts.green[293].value = 180683; + post1D->tf_pts.blue[293].value = 180683; + post1D->tf_pts.red[294].value = 200154; + post1D->tf_pts.green[294].value = 200154; + post1D->tf_pts.blue[294].value = 200154; + post1D->tf_pts.red[295].value = 220717; + post1D->tf_pts.green[295].value = 220717; + post1D->tf_pts.blue[295].value = 220717; + post1D->tf_pts.red[296].value = 242381; + post1D->tf_pts.green[296].value = 242381; + post1D->tf_pts.blue[296].value = 242381; + post1D->tf_pts.red[297].value = 265156; + post1D->tf_pts.green[297].value = 265156; + post1D->tf_pts.blue[297].value = 265156; + post1D->tf_pts.red[298].value = 289052; + post1D->tf_pts.green[298].value = 289052; + post1D->tf_pts.blue[298].value = 289052; + post1D->tf_pts.red[299].value = 314076; + post1D->tf_pts.green[299].value = 314076; + post1D->tf_pts.blue[299].value = 314076; + post1D->tf_pts.red[300].value = 340237; + post1D->tf_pts.green[300].value = 340237; + post1D->tf_pts.blue[300].value = 340237; + post1D->tf_pts.red[301].value = 367544; + post1D->tf_pts.green[301].value = 367544; + post1D->tf_pts.blue[301].value = 367544; + post1D->tf_pts.red[302].value = 396005; + post1D->tf_pts.green[302].value = 396005; + post1D->tf_pts.blue[302].value = 396005; + post1D->tf_pts.red[303].value = 425628; + post1D->tf_pts.green[303].value = 425628; + post1D->tf_pts.blue[303].value = 425628; + post1D->tf_pts.red[304].value = 456419; + post1D->tf_pts.green[304].value = 456419; + post1D->tf_pts.blue[304].value = 456419; + post1D->tf_pts.red[305].value = 521540; + post1D->tf_pts.green[305].value = 521540; + post1D->tf_pts.blue[305].value = 521540; + post1D->tf_pts.red[306].value = 591425; + post1D->tf_pts.green[306].value = 591425; + post1D->tf_pts.blue[306].value = 591425; + post1D->tf_pts.red[307].value = 666128; + post1D->tf_pts.green[307].value = 666128; + post1D->tf_pts.blue[307].value = 666128; + post1D->tf_pts.red[308].value = 745703; + post1D->tf_pts.green[308].value = 745703; + post1D->tf_pts.blue[308].value = 745703; + post1D->tf_pts.red[309].value = 830199; + post1D->tf_pts.green[309].value = 830199; + post1D->tf_pts.blue[309].value = 830199; + post1D->tf_pts.red[310].value = 919665; + post1D->tf_pts.green[310].value = 919665; + post1D->tf_pts.blue[310].value = 919665; + post1D->tf_pts.red[311].value = 1014148; + post1D->tf_pts.green[311].value = 1014148; + post1D->tf_pts.blue[311].value = 1014148; + post1D->tf_pts.red[312].value = 1113691; + post1D->tf_pts.green[312].value = 1113691; + post1D->tf_pts.blue[312].value = 1113691; + post1D->tf_pts.red[313].value = 1218339; + post1D->tf_pts.green[313].value = 1218339; + post1D->tf_pts.blue[313].value = 1218339; + post1D->tf_pts.red[314].value = 1328132; + post1D->tf_pts.green[314].value = 1328132; + post1D->tf_pts.blue[314].value = 1328132; + post1D->tf_pts.red[315].value = 1443113; + post1D->tf_pts.green[315].value = 1443113; + post1D->tf_pts.blue[315].value = 1443113; + post1D->tf_pts.red[316].value = 1563319; + post1D->tf_pts.green[316].value = 1563319; + post1D->tf_pts.blue[316].value = 1563319; + post1D->tf_pts.red[317].value = 1688790; + post1D->tf_pts.green[317].value = 1688790; + post1D->tf_pts.blue[317].value = 1688790; + post1D->tf_pts.red[318].value = 1819561; + post1D->tf_pts.green[318].value = 1819561; + post1D->tf_pts.blue[318].value = 1819561; + post1D->tf_pts.red[319].value = 1955670; + post1D->tf_pts.green[319].value = 1955670; + post1D->tf_pts.blue[319].value = 1955670; + post1D->tf_pts.red[320].value = 2097152; + post1D->tf_pts.green[320].value = 2097152; + post1D->tf_pts.blue[320].value = 2097152; + post1D->tf_pts.red[321].value = 2396368; + post1D->tf_pts.green[321].value = 2396368; + post1D->tf_pts.blue[321].value = 2396368; + post1D->tf_pts.red[322].value = 2717474; + post1D->tf_pts.green[322].value = 2717474; + post1D->tf_pts.blue[322].value = 2717474; + post1D->tf_pts.red[323].value = 3060722; + post1D->tf_pts.green[323].value = 3060722; + post1D->tf_pts.blue[323].value = 3060722; + post1D->tf_pts.red[324].value = 3426352; + post1D->tf_pts.green[324].value = 3426352; + post1D->tf_pts.blue[324].value = 3426352; + post1D->tf_pts.red[325].value = 3814595; + post1D->tf_pts.green[325].value = 3814595; + post1D->tf_pts.blue[325].value = 3814595; + post1D->tf_pts.red[326].value = 4225673; + post1D->tf_pts.green[326].value = 4225673; + post1D->tf_pts.blue[326].value = 4225673; + post1D->tf_pts.red[327].value = 4659799; + post1D->tf_pts.green[327].value = 4659799; + post1D->tf_pts.blue[327].value = 4659799; + post1D->tf_pts.red[328].value = 5117180; + post1D->tf_pts.green[328].value = 5117180; + post1D->tf_pts.blue[328].value = 5117180; + post1D->tf_pts.red[329].value = 5598014; + post1D->tf_pts.green[329].value = 5598014; + post1D->tf_pts.blue[329].value = 5598014; + post1D->tf_pts.red[330].value = 6102493; + post1D->tf_pts.green[330].value = 6102493; + post1D->tf_pts.blue[330].value = 6102493; + post1D->tf_pts.red[331].value = 6630805; + post1D->tf_pts.green[331].value = 6630805; + post1D->tf_pts.blue[331].value = 6630805; + post1D->tf_pts.red[332].value = 7183128; + post1D->tf_pts.green[332].value = 7183128; + post1D->tf_pts.blue[332].value = 7183128; + post1D->tf_pts.red[333].value = 7759639; + post1D->tf_pts.green[333].value = 7759639; + post1D->tf_pts.blue[333].value = 7759639; + post1D->tf_pts.red[334].value = 8360509; + post1D->tf_pts.green[334].value = 8360509; + post1D->tf_pts.blue[334].value = 8360509; + post1D->tf_pts.red[335].value = 8985902; + post1D->tf_pts.green[335].value = 8985902; + post1D->tf_pts.blue[335].value = 8985902; + post1D->tf_pts.red[336].value = 9635980; + post1D->tf_pts.green[336].value = 9635980; + post1D->tf_pts.blue[336].value = 9635980; + post1D->tf_pts.red[337].value = 11010818; + post1D->tf_pts.green[337].value = 11010818; + post1D->tf_pts.blue[337].value = 11010818; + post1D->tf_pts.red[338].value = 12486233; + post1D->tf_pts.green[338].value = 12486233; + post1D->tf_pts.blue[338].value = 12486233; + post1D->tf_pts.red[339].value = 14063385; + post1D->tf_pts.green[339].value = 14063385; + post1D->tf_pts.blue[339].value = 14063385; + post1D->tf_pts.red[340].value = 15743378; + post1D->tf_pts.green[340].value = 15743378; + post1D->tf_pts.blue[340].value = 15743378; + post1D->tf_pts.red[341].value = 17527274; + post1D->tf_pts.green[341].value = 17527274; + post1D->tf_pts.blue[341].value = 17527274; + post1D->tf_pts.red[342].value = 19416093; + post1D->tf_pts.green[342].value = 19416093; + post1D->tf_pts.blue[342].value = 19416093; + post1D->tf_pts.red[343].value = 21410814; + post1D->tf_pts.green[343].value = 21410814; + post1D->tf_pts.blue[343].value = 21410814; + post1D->tf_pts.red[344].value = 23512384; + post1D->tf_pts.green[344].value = 23512384; + post1D->tf_pts.blue[344].value = 23512384; + post1D->tf_pts.red[345].value = 25721717; + post1D->tf_pts.green[345].value = 25721717; + post1D->tf_pts.blue[345].value = 25721717; + post1D->tf_pts.red[346].value = 28039696; + post1D->tf_pts.green[346].value = 28039696; + post1D->tf_pts.blue[346].value = 28039696; + post1D->tf_pts.red[347].value = 30467177; + post1D->tf_pts.green[347].value = 30467177; + post1D->tf_pts.blue[347].value = 30467177; + post1D->tf_pts.red[348].value = 33004990; + post1D->tf_pts.green[348].value = 33004990; + post1D->tf_pts.blue[348].value = 33004990; + post1D->tf_pts.red[349].value = 35653940; + post1D->tf_pts.green[349].value = 35653940; + post1D->tf_pts.blue[349].value = 35653940; + post1D->tf_pts.red[350].value = 38414811; + post1D->tf_pts.green[350].value = 38414811; + post1D->tf_pts.blue[350].value = 38414811; + post1D->tf_pts.red[351].value = 41288363; + post1D->tf_pts.green[351].value = 41288363; + post1D->tf_pts.blue[351].value = 41288363; + post1D->tf_pts.red[352].value = 44275338; + post1D->tf_pts.green[352].value = 44275338; + post1D->tf_pts.blue[352].value = 44275338; + post1D->tf_pts.red[353].value = 50592432; + post1D->tf_pts.green[353].value = 50592432; + post1D->tf_pts.blue[353].value = 50592432; + post1D->tf_pts.red[354].value = 57371663; + post1D->tf_pts.green[354].value = 57371663; + post1D->tf_pts.blue[354].value = 57371663; + post1D->tf_pts.red[355].value = 64618348; + post1D->tf_pts.green[355].value = 64618348; + post1D->tf_pts.blue[355].value = 64618348; + post1D->tf_pts.red[356].value = 72337570; + post1D->tf_pts.green[356].value = 72337570; + post1D->tf_pts.blue[356].value = 72337570; + post1D->tf_pts.red[357].value = 80534205; + post1D->tf_pts.green[357].value = 80534205; + post1D->tf_pts.blue[357].value = 80534205; + post1D->tf_pts.red[358].value = 89212935; + post1D->tf_pts.green[358].value = 89212935; + post1D->tf_pts.blue[358].value = 89212935; + post1D->tf_pts.red[359].value = 98378267; + post1D->tf_pts.green[359].value = 98378267; + post1D->tf_pts.blue[359].value = 98378267; + post1D->tf_pts.red[360].value = 108034548; + post1D->tf_pts.green[360].value = 108034548; + post1D->tf_pts.blue[360].value = 108034548; + post1D->tf_pts.red[361].value = 118185976; + post1D->tf_pts.green[361].value = 118185976; + post1D->tf_pts.blue[361].value = 118185976; + post1D->tf_pts.red[362].value = 128836611; + post1D->tf_pts.green[362].value = 128836611; + post1D->tf_pts.blue[362].value = 128836611; + post1D->tf_pts.red[363].value = 139990385; + post1D->tf_pts.green[363].value = 139990385; + post1D->tf_pts.blue[363].value = 139990385; + post1D->tf_pts.red[364].value = 151651111; + post1D->tf_pts.green[364].value = 151651111; + post1D->tf_pts.blue[364].value = 151651111; + post1D->tf_pts.red[365].value = 163822490; + post1D->tf_pts.green[365].value = 163822490; + post1D->tf_pts.blue[365].value = 163822490; + post1D->tf_pts.red[366].value = 176508120; + post1D->tf_pts.green[366].value = 176508120; + post1D->tf_pts.blue[366].value = 176508120; + post1D->tf_pts.red[367].value = 189711499; + post1D->tf_pts.green[367].value = 189711499; + post1D->tf_pts.blue[367].value = 189711499; + post1D->tf_pts.red[368].value = 203436034; + post1D->tf_pts.green[368].value = 203436034; + post1D->tf_pts.blue[368].value = 203436034; + post1D->tf_pts.red[369].value = 232461773; + post1D->tf_pts.green[369].value = 232461773; + post1D->tf_pts.blue[369].value = 232461773; + post1D->tf_pts.red[370].value = 263610940; + post1D->tf_pts.green[370].value = 263610940; + post1D->tf_pts.blue[370].value = 263610940; + post1D->tf_pts.red[371].value = 296907960; + post1D->tf_pts.green[371].value = 296907960; + post1D->tf_pts.blue[371].value = 296907960; + post1D->tf_pts.red[372].value = 332376193; + post1D->tf_pts.green[372].value = 332376193; + post1D->tf_pts.blue[372].value = 332376193; + post1D->tf_pts.red[373].value = 370038035; + post1D->tf_pts.green[373].value = 370038035; + post1D->tf_pts.blue[373].value = 370038035; + post1D->tf_pts.red[374].value = 409915005; + post1D->tf_pts.green[374].value = 409915005; + post1D->tf_pts.blue[374].value = 409915005; + post1D->tf_pts.red[375].value = 452027813; + post1D->tf_pts.green[375].value = 452027813; + post1D->tf_pts.blue[375].value = 452027813; + post1D->tf_pts.red[376].value = 496396431; + post1D->tf_pts.green[376].value = 496396431; + post1D->tf_pts.blue[376].value = 496396431; + post1D->tf_pts.red[377].value = 543040146; + post1D->tf_pts.green[377].value = 543040146; + post1D->tf_pts.blue[377].value = 543040146; + post1D->tf_pts.red[378].value = 591977614; + post1D->tf_pts.green[378].value = 591977614; + post1D->tf_pts.blue[378].value = 591977614; + post1D->tf_pts.red[379].value = 643226902; + post1D->tf_pts.green[379].value = 643226902; + post1D->tf_pts.blue[379].value = 643226902; + post1D->tf_pts.red[380].value = 696805528; + post1D->tf_pts.green[380].value = 696805528; + post1D->tf_pts.blue[380].value = 696805528; + post1D->tf_pts.red[381].value = 752730501; + post1D->tf_pts.green[381].value = 752730501; + post1D->tf_pts.blue[381].value = 752730501; + post1D->tf_pts.red[382].value = 811018347; + post1D->tf_pts.green[382].value = 811018347; + post1D->tf_pts.blue[382].value = 811018347; + post1D->tf_pts.red[383].value = 871685145; + post1D->tf_pts.green[383].value = 871685145; + post1D->tf_pts.blue[383].value = 871685145; + post1D->tf_pts.red[384].value = 934746550; + post1D->tf_pts.green[384].value = 934746550; + post1D->tf_pts.blue[384].value = 934746550; + post1D->tf_pts.red[385].value = 1068113823; + post1D->tf_pts.green[385].value = 1068113823; + post1D->tf_pts.blue[385].value = 1068113823; + post1D->tf_pts.red[386].value = 1211237812; + post1D->tf_pts.green[386].value = 1211237812; + post1D->tf_pts.blue[386].value = 1211237812; + post1D->tf_pts.red[387].value = 1364230740; + post1D->tf_pts.green[387].value = 1364230740; + post1D->tf_pts.blue[387].value = 1364230740; + post1D->tf_pts.red[388].value = 1527199943; + post1D->tf_pts.green[388].value = 1527199943; + post1D->tf_pts.blue[388].value = 1527199943; + post1D->tf_pts.red[389].value = 1700248331; + post1D->tf_pts.green[389].value = 1700248331; + post1D->tf_pts.blue[389].value = 1700248331; + post1D->tf_pts.red[390].value = 1883474769; + post1D->tf_pts.green[390].value = 1883474769; + post1D->tf_pts.blue[390].value = 1883474769; + post1D->tf_pts.red[391].value = 2076974422; + post1D->tf_pts.green[391].value = 2076974422; + post1D->tf_pts.blue[391].value = 2076974422; + post1D->tf_pts.red[392].value = 2280839055; + post1D->tf_pts.green[392].value = 2280839055; + post1D->tf_pts.blue[392].value = 2280839055; + post1D->tf_pts.red[393].value = 2495157291; + post1D->tf_pts.green[393].value = 2495157291; + post1D->tf_pts.blue[393].value = 2495157291; + post1D->tf_pts.red[394].value = 2720014848; + post1D->tf_pts.green[394].value = 2720014848; + post1D->tf_pts.blue[394].value = 2720014848; + post1D->tf_pts.red[395].value = 2955494736; + post1D->tf_pts.green[395].value = 2955494736; + post1D->tf_pts.blue[395].value = 2955494736; + post1D->tf_pts.red[396].value = 3201677455; + post1D->tf_pts.green[396].value = 3201677455; + post1D->tf_pts.blue[396].value = 3201677455; + post1D->tf_pts.red[397].value = 3458641150; + post1D->tf_pts.green[397].value = 3458641150; + post1D->tf_pts.blue[397].value = 3458641150; + post1D->tf_pts.red[398].value = 3726461762; + post1D->tf_pts.green[398].value = 3726461762; + post1D->tf_pts.blue[398].value = 3726461762; + post1D->tf_pts.red[399].value = 4005213167; + post1D->tf_pts.green[399].value = 4005213167; + post1D->tf_pts.blue[399].value = 4005213167; + post1D->tf_pts.red[400].value = 4294967296; + post1D->tf_pts.green[400].value = 4294967296; + post1D->tf_pts.blue[400].value = 4294967296; + post1D->tf_pts.red[401].value = 4294967296; + post1D->tf_pts.green[401].value = 4294967296; + post1D->tf_pts.blue[401].value = 4294967296; + post1D->tf_pts.red[402].value = 4294967296; + post1D->tf_pts.green[402].value = 4294967296; + post1D->tf_pts.blue[402].value = 4294967296; + post1D->tf_pts.red[403].value = 4294967296; + post1D->tf_pts.green[403].value = 4294967296; + post1D->tf_pts.blue[403].value = 4294967296; + post1D->tf_pts.red[404].value = 4294967296; + post1D->tf_pts.green[404].value = 4294967296; + post1D->tf_pts.blue[404].value = 4294967296; + post1D->tf_pts.red[405].value = 4294967296; + post1D->tf_pts.green[405].value = 4294967296; + post1D->tf_pts.blue[405].value = 4294967296; + post1D->tf_pts.red[406].value = 4294967296; + post1D->tf_pts.green[406].value = 4294967296; + post1D->tf_pts.blue[406].value = 4294967296; + post1D->tf_pts.red[407].value = 4294967296; + post1D->tf_pts.green[407].value = 4294967296; + post1D->tf_pts.blue[407].value = 4294967296; + post1D->tf_pts.red[408].value = 4294967296; + post1D->tf_pts.green[408].value = 4294967296; + post1D->tf_pts.blue[408].value = 4294967296; + post1D->tf_pts.red[409].value = 4294967296; + post1D->tf_pts.green[409].value = 4294967296; + post1D->tf_pts.blue[409].value = 4294967296; + post1D->tf_pts.red[410].value = 4294967296; + post1D->tf_pts.green[410].value = 4294967296; + post1D->tf_pts.blue[410].value = 4294967296; + post1D->tf_pts.red[411].value = 4294967296; + post1D->tf_pts.green[411].value = 4294967296; + post1D->tf_pts.blue[411].value = 4294967296; + post1D->tf_pts.red[412].value = 4294967296; + post1D->tf_pts.green[412].value = 4294967296; + post1D->tf_pts.blue[412].value = 4294967296; + post1D->tf_pts.red[413].value = 4294967296; + post1D->tf_pts.green[413].value = 4294967296; + post1D->tf_pts.blue[413].value = 4294967296; + post1D->tf_pts.red[414].value = 4294967296; + post1D->tf_pts.green[414].value = 4294967296; + post1D->tf_pts.blue[414].value = 4294967296; + post1D->tf_pts.red[415].value = 4294967296; + post1D->tf_pts.green[415].value = 4294967296; + post1D->tf_pts.blue[415].value = 4294967296; + post1D->tf_pts.red[416].value = 4294967296; + post1D->tf_pts.green[416].value = 4294967296; + post1D->tf_pts.blue[416].value = 4294967296; + post1D->tf_pts.red[417].value = 4294967296; + post1D->tf_pts.green[417].value = 4294967296; + post1D->tf_pts.blue[417].value = 4294967296; + post1D->tf_pts.red[418].value = 4294967296; + post1D->tf_pts.green[418].value = 4294967296; + post1D->tf_pts.blue[418].value = 4294967296; + post1D->tf_pts.red[419].value = 4294967296; + post1D->tf_pts.green[419].value = 4294967296; + post1D->tf_pts.blue[419].value = 4294967296; + post1D->tf_pts.red[420].value = 4294967296; + post1D->tf_pts.green[420].value = 4294967296; + post1D->tf_pts.blue[420].value = 4294967296; + post1D->tf_pts.red[421].value = 4294967296; + post1D->tf_pts.green[421].value = 4294967296; + post1D->tf_pts.blue[421].value = 4294967296; + post1D->tf_pts.red[422].value = 4294967296; + post1D->tf_pts.green[422].value = 4294967296; + post1D->tf_pts.blue[422].value = 4294967296; + post1D->tf_pts.red[423].value = 4294967296; + post1D->tf_pts.green[423].value = 4294967296; + post1D->tf_pts.blue[423].value = 4294967296; + post1D->tf_pts.red[424].value = 4294967296; + post1D->tf_pts.green[424].value = 4294967296; + post1D->tf_pts.blue[424].value = 4294967296; + post1D->tf_pts.red[425].value = 4294967296; + post1D->tf_pts.green[425].value = 4294967296; + post1D->tf_pts.blue[425].value = 4294967296; + post1D->tf_pts.red[426].value = 4294967296; + post1D->tf_pts.green[426].value = 4294967296; + post1D->tf_pts.blue[426].value = 4294967296; + post1D->tf_pts.red[427].value = 4294967296; + post1D->tf_pts.green[427].value = 4294967296; + post1D->tf_pts.blue[427].value = 4294967296; + post1D->tf_pts.red[428].value = 4294967296; + post1D->tf_pts.green[428].value = 4294967296; + post1D->tf_pts.blue[428].value = 4294967296; + post1D->tf_pts.red[429].value = 4294967296; + post1D->tf_pts.green[429].value = 4294967296; + post1D->tf_pts.blue[429].value = 4294967296; + post1D->tf_pts.red[430].value = 4294967296; + post1D->tf_pts.green[430].value = 4294967296; + post1D->tf_pts.blue[430].value = 4294967296; + post1D->tf_pts.red[431].value = 4294967296; + post1D->tf_pts.green[431].value = 4294967296; + post1D->tf_pts.blue[431].value = 4294967296; + post1D->tf_pts.red[432].value = 4294967296; + post1D->tf_pts.green[432].value = 4294967296; + post1D->tf_pts.blue[432].value = 4294967296; + post1D->tf_pts.red[433].value = 4294967296; + post1D->tf_pts.green[433].value = 4294967296; + post1D->tf_pts.blue[433].value = 4294967296; + post1D->tf_pts.red[434].value = 4294967296; + post1D->tf_pts.green[434].value = 4294967296; + post1D->tf_pts.blue[434].value = 4294967296; + post1D->tf_pts.red[435].value = 4294967296; + post1D->tf_pts.green[435].value = 4294967296; + post1D->tf_pts.blue[435].value = 4294967296; + post1D->tf_pts.red[436].value = 4294967296; + post1D->tf_pts.green[436].value = 4294967296; + post1D->tf_pts.blue[436].value = 4294967296; + post1D->tf_pts.red[437].value = 4294967296; + post1D->tf_pts.green[437].value = 4294967296; + post1D->tf_pts.blue[437].value = 4294967296; + post1D->tf_pts.red[438].value = 4294967296; + post1D->tf_pts.green[438].value = 4294967296; + post1D->tf_pts.blue[438].value = 4294967296; + post1D->tf_pts.red[439].value = 4294967296; + post1D->tf_pts.green[439].value = 4294967296; + post1D->tf_pts.blue[439].value = 4294967296; + post1D->tf_pts.red[440].value = 4294967296; + post1D->tf_pts.green[440].value = 4294967296; + post1D->tf_pts.blue[440].value = 4294967296; + post1D->tf_pts.red[441].value = 4294967296; + post1D->tf_pts.green[441].value = 4294967296; + post1D->tf_pts.blue[441].value = 4294967296; + post1D->tf_pts.red[442].value = 4294967296; + post1D->tf_pts.green[442].value = 4294967296; + post1D->tf_pts.blue[442].value = 4294967296; + post1D->tf_pts.red[443].value = 4294967296; + post1D->tf_pts.green[443].value = 4294967296; + post1D->tf_pts.blue[443].value = 4294967296; + post1D->tf_pts.red[444].value = 4294967296; + post1D->tf_pts.green[444].value = 4294967296; + post1D->tf_pts.blue[444].value = 4294967296; + post1D->tf_pts.red[445].value = 4294967296; + post1D->tf_pts.green[445].value = 4294967296; + post1D->tf_pts.blue[445].value = 4294967296; + post1D->tf_pts.red[446].value = 4294967296; + post1D->tf_pts.green[446].value = 4294967296; + post1D->tf_pts.blue[446].value = 4294967296; + post1D->tf_pts.red[447].value = 4294967296; + post1D->tf_pts.green[447].value = 4294967296; + post1D->tf_pts.blue[447].value = 4294967296; + post1D->tf_pts.red[448].value = 4294967296; + post1D->tf_pts.green[448].value = 4294967296; + post1D->tf_pts.blue[448].value = 4294967296; + post1D->tf_pts.red[449].value = 4294967296; + post1D->tf_pts.green[449].value = 4294967296; + post1D->tf_pts.blue[449].value = 4294967296; + post1D->tf_pts.red[450].value = 4294967296; + post1D->tf_pts.green[450].value = 4294967296; + post1D->tf_pts.blue[450].value = 4294967296; + post1D->tf_pts.red[451].value = 4294967296; + post1D->tf_pts.green[451].value = 4294967296; + post1D->tf_pts.blue[451].value = 4294967296; + post1D->tf_pts.red[452].value = 4294967296; + post1D->tf_pts.green[452].value = 4294967296; + post1D->tf_pts.blue[452].value = 4294967296; + post1D->tf_pts.red[453].value = 4294967296; + post1D->tf_pts.green[453].value = 4294967296; + post1D->tf_pts.blue[453].value = 4294967296; + post1D->tf_pts.red[454].value = 4294967296; + post1D->tf_pts.green[454].value = 4294967296; + post1D->tf_pts.blue[454].value = 4294967296; + post1D->tf_pts.red[455].value = 4294967296; + post1D->tf_pts.green[455].value = 4294967296; + post1D->tf_pts.blue[455].value = 4294967296; + post1D->tf_pts.red[456].value = 4294967296; + post1D->tf_pts.green[456].value = 4294967296; + post1D->tf_pts.blue[456].value = 4294967296; + post1D->tf_pts.red[457].value = 4294967296; + post1D->tf_pts.green[457].value = 4294967296; + post1D->tf_pts.blue[457].value = 4294967296; + post1D->tf_pts.red[458].value = 4294967296; + post1D->tf_pts.green[458].value = 4294967296; + post1D->tf_pts.blue[458].value = 4294967296; + post1D->tf_pts.red[459].value = 4294967296; + post1D->tf_pts.green[459].value = 4294967296; + post1D->tf_pts.blue[459].value = 4294967296; + post1D->tf_pts.red[460].value = 4294967296; + post1D->tf_pts.green[460].value = 4294967296; + post1D->tf_pts.blue[460].value = 4294967296; + post1D->tf_pts.red[461].value = 4294967296; + post1D->tf_pts.green[461].value = 4294967296; + post1D->tf_pts.blue[461].value = 4294967296; + post1D->tf_pts.red[462].value = 4294967296; + post1D->tf_pts.green[462].value = 4294967296; + post1D->tf_pts.blue[462].value = 4294967296; + post1D->tf_pts.red[463].value = 4294967296; + post1D->tf_pts.green[463].value = 4294967296; + post1D->tf_pts.blue[463].value = 4294967296; + post1D->tf_pts.red[464].value = 4294967296; + post1D->tf_pts.green[464].value = 4294967296; + post1D->tf_pts.blue[464].value = 4294967296; + post1D->tf_pts.red[465].value = 4294967296; + post1D->tf_pts.green[465].value = 4294967296; + post1D->tf_pts.blue[465].value = 4294967296; + post1D->tf_pts.red[466].value = 4294967296; + post1D->tf_pts.green[466].value = 4294967296; + post1D->tf_pts.blue[466].value = 4294967296; + post1D->tf_pts.red[467].value = 4294967296; + post1D->tf_pts.green[467].value = 4294967296; + post1D->tf_pts.blue[467].value = 4294967296; + post1D->tf_pts.red[468].value = 4294967296; + post1D->tf_pts.green[468].value = 4294967296; + post1D->tf_pts.blue[468].value = 4294967296; + post1D->tf_pts.red[469].value = 4294967296; + post1D->tf_pts.green[469].value = 4294967296; + post1D->tf_pts.blue[469].value = 4294967296; + post1D->tf_pts.red[470].value = 4294967296; + post1D->tf_pts.green[470].value = 4294967296; + post1D->tf_pts.blue[470].value = 4294967296; + post1D->tf_pts.red[471].value = 4294967296; + post1D->tf_pts.green[471].value = 4294967296; + post1D->tf_pts.blue[471].value = 4294967296; + post1D->tf_pts.red[472].value = 4294967296; + post1D->tf_pts.green[472].value = 4294967296; + post1D->tf_pts.blue[472].value = 4294967296; + post1D->tf_pts.red[473].value = 4294967296; + post1D->tf_pts.green[473].value = 4294967296; + post1D->tf_pts.blue[473].value = 4294967296; + post1D->tf_pts.red[474].value = 4294967296; + post1D->tf_pts.green[474].value = 4294967296; + post1D->tf_pts.blue[474].value = 4294967296; + post1D->tf_pts.red[475].value = 4294967296; + post1D->tf_pts.green[475].value = 4294967296; + post1D->tf_pts.blue[475].value = 4294967296; + post1D->tf_pts.red[476].value = 4294967296; + post1D->tf_pts.green[476].value = 4294967296; + post1D->tf_pts.blue[476].value = 4294967296; + post1D->tf_pts.red[477].value = 4294967296; + post1D->tf_pts.green[477].value = 4294967296; + post1D->tf_pts.blue[477].value = 4294967296; + post1D->tf_pts.red[478].value = 4294967296; + post1D->tf_pts.green[478].value = 4294967296; + post1D->tf_pts.blue[478].value = 4294967296; + post1D->tf_pts.red[479].value = 4294967296; + post1D->tf_pts.green[479].value = 4294967296; + post1D->tf_pts.blue[479].value = 4294967296; + post1D->tf_pts.red[480].value = 4294967296; + post1D->tf_pts.green[480].value = 4294967296; + post1D->tf_pts.blue[480].value = 4294967296; + post1D->tf_pts.red[481].value = 4294967296; + post1D->tf_pts.green[481].value = 4294967296; + post1D->tf_pts.blue[481].value = 4294967296; + post1D->tf_pts.red[482].value = 4294967296; + post1D->tf_pts.green[482].value = 4294967296; + post1D->tf_pts.blue[482].value = 4294967296; + post1D->tf_pts.red[483].value = 4294967296; + post1D->tf_pts.green[483].value = 4294967296; + post1D->tf_pts.blue[483].value = 4294967296; + post1D->tf_pts.red[484].value = 4294967296; + post1D->tf_pts.green[484].value = 4294967296; + post1D->tf_pts.blue[484].value = 4294967296; + post1D->tf_pts.red[485].value = 4294967296; + post1D->tf_pts.green[485].value = 4294967296; + post1D->tf_pts.blue[485].value = 4294967296; + post1D->tf_pts.red[486].value = 4294967296; + post1D->tf_pts.green[486].value = 4294967296; + post1D->tf_pts.blue[486].value = 4294967296; + post1D->tf_pts.red[487].value = 4294967296; + post1D->tf_pts.green[487].value = 4294967296; + post1D->tf_pts.blue[487].value = 4294967296; + post1D->tf_pts.red[488].value = 4294967296; + post1D->tf_pts.green[488].value = 4294967296; + post1D->tf_pts.blue[488].value = 4294967296; + post1D->tf_pts.red[489].value = 4294967296; + post1D->tf_pts.green[489].value = 4294967296; + post1D->tf_pts.blue[489].value = 4294967296; + post1D->tf_pts.red[490].value = 4294967296; + post1D->tf_pts.green[490].value = 4294967296; + post1D->tf_pts.blue[490].value = 4294967296; + post1D->tf_pts.red[491].value = 4294967296; + post1D->tf_pts.green[491].value = 4294967296; + post1D->tf_pts.blue[491].value = 4294967296; + post1D->tf_pts.red[492].value = 4294967296; + post1D->tf_pts.green[492].value = 4294967296; + post1D->tf_pts.blue[492].value = 4294967296; + post1D->tf_pts.red[493].value = 4294967296; + post1D->tf_pts.green[493].value = 4294967296; + post1D->tf_pts.blue[493].value = 4294967296; + post1D->tf_pts.red[494].value = 4294967296; + post1D->tf_pts.green[494].value = 4294967296; + post1D->tf_pts.blue[494].value = 4294967296; + post1D->tf_pts.red[495].value = 4294967296; + post1D->tf_pts.green[495].value = 4294967296; + post1D->tf_pts.blue[495].value = 4294967296; + post1D->tf_pts.red[496].value = 4294967296; + post1D->tf_pts.green[496].value = 4294967296; + post1D->tf_pts.blue[496].value = 4294967296; + post1D->tf_pts.red[497].value = 4294967296; + post1D->tf_pts.green[497].value = 4294967296; + post1D->tf_pts.blue[497].value = 4294967296; + post1D->tf_pts.red[498].value = 4294967296; + post1D->tf_pts.green[498].value = 4294967296; + post1D->tf_pts.blue[498].value = 4294967296; + post1D->tf_pts.red[499].value = 4294967296; + post1D->tf_pts.green[499].value = 4294967296; + post1D->tf_pts.blue[499].value = 4294967296; + post1D->tf_pts.red[500].value = 4294967296; + post1D->tf_pts.green[500].value = 4294967296; + post1D->tf_pts.blue[500].value = 4294967296; + post1D->tf_pts.red[501].value = 4294967296; + post1D->tf_pts.green[501].value = 4294967296; + post1D->tf_pts.blue[501].value = 4294967296; + post1D->tf_pts.red[502].value = 4294967296; + post1D->tf_pts.green[502].value = 4294967296; + post1D->tf_pts.blue[502].value = 4294967296; + post1D->tf_pts.red[503].value = 4294967296; + post1D->tf_pts.green[503].value = 4294967296; + post1D->tf_pts.blue[503].value = 4294967296; + post1D->tf_pts.red[504].value = 4294967296; + post1D->tf_pts.green[504].value = 4294967296; + post1D->tf_pts.blue[504].value = 4294967296; + post1D->tf_pts.red[505].value = 4294967296; + post1D->tf_pts.green[505].value = 4294967296; + post1D->tf_pts.blue[505].value = 4294967296; + post1D->tf_pts.red[506].value = 4294967296; + post1D->tf_pts.green[506].value = 4294967296; + post1D->tf_pts.blue[506].value = 4294967296; + post1D->tf_pts.red[507].value = 4294967296; + post1D->tf_pts.green[507].value = 4294967296; + post1D->tf_pts.blue[507].value = 4294967296; + post1D->tf_pts.red[508].value = 4294967296; + post1D->tf_pts.green[508].value = 4294967296; + post1D->tf_pts.blue[508].value = 4294967296; + post1D->tf_pts.red[509].value = 4294967296; + post1D->tf_pts.green[509].value = 4294967296; + post1D->tf_pts.blue[509].value = 4294967296; + post1D->tf_pts.red[510].value = 4294967296; + post1D->tf_pts.green[510].value = 4294967296; + post1D->tf_pts.blue[510].value = 4294967296; + post1D->tf_pts.red[511].value = 4294967296; + post1D->tf_pts.green[511].value = 4294967296; + post1D->tf_pts.blue[511].value = 4294967296; + post1D->tf_pts.red[512].value = 4294967296; + post1D->tf_pts.green[512].value = 4294967296; + post1D->tf_pts.blue[512].value = 4294967296; + post1D->tf_pts.red[513].value = 0; + post1D->tf_pts.green[513].value = 0; + post1D->tf_pts.blue[513].value = 0; + post1D->tf_pts.red[514].value = 0; + post1D->tf_pts.green[514].value = 0; + post1D->tf_pts.blue[514].value = 0; + post1D->tf_pts.red[515].value = 0; + post1D->tf_pts.green[515].value = 0; + post1D->tf_pts.blue[515].value = 0; + post1D->tf_pts.red[516].value = 0; + post1D->tf_pts.green[516].value = 0; + post1D->tf_pts.blue[516].value = 0; + post1D->tf_pts.red[517].value = 0; + post1D->tf_pts.green[517].value = 0; + post1D->tf_pts.blue[517].value = 0; + post1D->tf_pts.red[518].value = 0; + post1D->tf_pts.green[518].value = 0; + post1D->tf_pts.blue[518].value = 0; + post1D->tf_pts.red[519].value = 0; + post1D->tf_pts.green[519].value = 0; + post1D->tf_pts.blue[519].value = 0; + post1D->tf_pts.red[520].value = 0; + post1D->tf_pts.green[520].value = 0; + post1D->tf_pts.blue[520].value = 0; + post1D->tf_pts.red[521].value = 0; + post1D->tf_pts.green[521].value = 0; + post1D->tf_pts.blue[521].value = 0; + post1D->tf_pts.red[522].value = 0; + post1D->tf_pts.green[522].value = 0; + post1D->tf_pts.blue[522].value = 0; + post1D->tf_pts.red[523].value = 0; + post1D->tf_pts.green[523].value = 0; + post1D->tf_pts.blue[523].value = 0; + post1D->tf_pts.red[524].value = 0; + post1D->tf_pts.green[524].value = 0; + post1D->tf_pts.blue[524].value = 0; + post1D->tf_pts.red[525].value = 0; + post1D->tf_pts.green[525].value = 0; + post1D->tf_pts.blue[525].value = 0; + post1D->tf_pts.red[526].value = 0; + post1D->tf_pts.green[526].value = 0; + post1D->tf_pts.blue[526].value = 0; + post1D->tf_pts.red[527].value = 0; + post1D->tf_pts.green[527].value = 0; + post1D->tf_pts.blue[527].value = 0; + post1D->tf_pts.red[528].value = 0; + post1D->tf_pts.green[528].value = 0; + post1D->tf_pts.blue[528].value = 0; + post1D->tf_pts.red[529].value = 0; + post1D->tf_pts.green[529].value = 0; + post1D->tf_pts.blue[529].value = 0; + post1D->tf_pts.red[530].value = 0; + post1D->tf_pts.green[530].value = 0; + post1D->tf_pts.blue[530].value = 0; + post1D->tf_pts.red[531].value = 0; + post1D->tf_pts.green[531].value = 0; + post1D->tf_pts.blue[531].value = 0; + post1D->tf_pts.red[532].value = 0; + post1D->tf_pts.green[532].value = 0; + post1D->tf_pts.blue[532].value = 0; + post1D->tf_pts.red[533].value = 0; + post1D->tf_pts.green[533].value = 0; + post1D->tf_pts.blue[533].value = 0; + post1D->tf_pts.red[534].value = 0; + post1D->tf_pts.green[534].value = 0; + post1D->tf_pts.blue[534].value = 0; + post1D->tf_pts.red[535].value = 0; + post1D->tf_pts.green[535].value = 0; + post1D->tf_pts.blue[535].value = 0; + post1D->tf_pts.red[536].value = 0; + post1D->tf_pts.green[536].value = 0; + post1D->tf_pts.blue[536].value = 0; + post1D->tf_pts.red[537].value = 0; + post1D->tf_pts.green[537].value = 0; + post1D->tf_pts.blue[537].value = 0; + post1D->tf_pts.red[538].value = 0; + post1D->tf_pts.green[538].value = 0; + post1D->tf_pts.blue[538].value = 0; + post1D->tf_pts.red[539].value = 0; + post1D->tf_pts.green[539].value = 0; + post1D->tf_pts.blue[539].value = 0; + post1D->tf_pts.red[540].value = 0; + post1D->tf_pts.green[540].value = 0; + post1D->tf_pts.blue[540].value = 0; + post1D->tf_pts.red[541].value = 0; + post1D->tf_pts.green[541].value = 0; + post1D->tf_pts.blue[541].value = 0; + post1D->tf_pts.red[542].value = 0; + post1D->tf_pts.green[542].value = 0; + post1D->tf_pts.blue[542].value = 0; + post1D->tf_pts.red[543].value = 0; + post1D->tf_pts.green[543].value = 0; + post1D->tf_pts.blue[543].value = 0; + post1D->tf_pts.red[544].value = 0; + post1D->tf_pts.green[544].value = 0; + post1D->tf_pts.blue[544].value = 0; + post1D->tf_pts.red[545].value = 0; + post1D->tf_pts.green[545].value = 0; + post1D->tf_pts.blue[545].value = 0; + post1D->tf_pts.red[546].value = 0; + post1D->tf_pts.green[546].value = 0; + post1D->tf_pts.blue[546].value = 0; + post1D->tf_pts.red[547].value = 0; + post1D->tf_pts.green[547].value = 0; + post1D->tf_pts.blue[547].value = 0; + post1D->tf_pts.red[548].value = 0; + post1D->tf_pts.green[548].value = 0; + post1D->tf_pts.blue[548].value = 0; + post1D->tf_pts.red[549].value = 0; + post1D->tf_pts.green[549].value = 0; + post1D->tf_pts.blue[549].value = 0; + post1D->tf_pts.red[550].value = 0; + post1D->tf_pts.green[550].value = 0; + post1D->tf_pts.blue[550].value = 0; + post1D->tf_pts.red[551].value = 0; + post1D->tf_pts.green[551].value = 0; + post1D->tf_pts.blue[551].value = 0; + post1D->tf_pts.red[552].value = 0; + post1D->tf_pts.green[552].value = 0; + post1D->tf_pts.blue[552].value = 0; + post1D->tf_pts.red[553].value = 0; + post1D->tf_pts.green[553].value = 0; + post1D->tf_pts.blue[553].value = 0; + post1D->tf_pts.red[554].value = 0; + post1D->tf_pts.green[554].value = 0; + post1D->tf_pts.blue[554].value = 0; + post1D->tf_pts.red[555].value = 0; + post1D->tf_pts.green[555].value = 0; + post1D->tf_pts.blue[555].value = 0; + post1D->tf_pts.red[556].value = 0; + post1D->tf_pts.green[556].value = 0; + post1D->tf_pts.blue[556].value = 0; + post1D->tf_pts.red[557].value = 0; + post1D->tf_pts.green[557].value = 0; + post1D->tf_pts.blue[557].value = 0; + post1D->tf_pts.red[558].value = 0; + post1D->tf_pts.green[558].value = 0; + post1D->tf_pts.blue[558].value = 0; + post1D->tf_pts.red[559].value = 0; + post1D->tf_pts.green[559].value = 0; + post1D->tf_pts.blue[559].value = 0; + post1D->tf_pts.red[560].value = 0; + post1D->tf_pts.green[560].value = 0; + post1D->tf_pts.blue[560].value = 0; + post1D->tf_pts.red[561].value = 0; + post1D->tf_pts.green[561].value = 0; + post1D->tf_pts.blue[561].value = 0; + post1D->tf_pts.red[562].value = 0; + post1D->tf_pts.green[562].value = 0; + post1D->tf_pts.blue[562].value = 0; + post1D->tf_pts.red[563].value = 0; + post1D->tf_pts.green[563].value = 0; + post1D->tf_pts.blue[563].value = 0; + post1D->tf_pts.red[564].value = 0; + post1D->tf_pts.green[564].value = 0; + post1D->tf_pts.blue[564].value = 0; + post1D->tf_pts.red[565].value = 0; + post1D->tf_pts.green[565].value = 0; + post1D->tf_pts.blue[565].value = 0; + post1D->tf_pts.red[566].value = 0; + post1D->tf_pts.green[566].value = 0; + post1D->tf_pts.blue[566].value = 0; + post1D->tf_pts.red[567].value = 0; + post1D->tf_pts.green[567].value = 0; + post1D->tf_pts.blue[567].value = 0; + post1D->tf_pts.red[568].value = 0; + post1D->tf_pts.green[568].value = 0; + post1D->tf_pts.blue[568].value = 0; + post1D->tf_pts.red[569].value = 0; + post1D->tf_pts.green[569].value = 0; + post1D->tf_pts.blue[569].value = 0; + post1D->tf_pts.red[570].value = 0; + post1D->tf_pts.green[570].value = 0; + post1D->tf_pts.blue[570].value = 0; + post1D->tf_pts.red[571].value = 0; + post1D->tf_pts.green[571].value = 0; + post1D->tf_pts.blue[571].value = 0; + post1D->tf_pts.red[572].value = 0; + post1D->tf_pts.green[572].value = 0; + post1D->tf_pts.blue[572].value = 0; + post1D->tf_pts.red[573].value = 0; + post1D->tf_pts.green[573].value = 0; + post1D->tf_pts.blue[573].value = 0; + post1D->tf_pts.red[574].value = 0; + post1D->tf_pts.green[574].value = 0; + post1D->tf_pts.blue[574].value = 0; + post1D->tf_pts.red[575].value = 0; + post1D->tf_pts.green[575].value = 0; + post1D->tf_pts.blue[575].value = 0; + post1D->tf_pts.red[576].value = 0; + post1D->tf_pts.green[576].value = 0; + post1D->tf_pts.blue[576].value = 0; + post1D->tf_pts.red[577].value = 0; + post1D->tf_pts.green[577].value = 0; + post1D->tf_pts.blue[577].value = 0; + post1D->tf_pts.red[578].value = 0; + post1D->tf_pts.green[578].value = 0; + post1D->tf_pts.blue[578].value = 0; + post1D->tf_pts.red[579].value = 0; + post1D->tf_pts.green[579].value = 0; + post1D->tf_pts.blue[579].value = 0; + post1D->tf_pts.red[580].value = 0; + post1D->tf_pts.green[580].value = 0; + post1D->tf_pts.blue[580].value = 0; + post1D->tf_pts.red[581].value = 0; + post1D->tf_pts.green[581].value = 0; + post1D->tf_pts.blue[581].value = 0; + post1D->tf_pts.red[582].value = 0; + post1D->tf_pts.green[582].value = 0; + post1D->tf_pts.blue[582].value = 0; + post1D->tf_pts.red[583].value = 0; + post1D->tf_pts.green[583].value = 0; + post1D->tf_pts.blue[583].value = 0; + post1D->tf_pts.red[584].value = 0; + post1D->tf_pts.green[584].value = 0; + post1D->tf_pts.blue[584].value = 0; + post1D->tf_pts.red[585].value = 0; + post1D->tf_pts.green[585].value = 0; + post1D->tf_pts.blue[585].value = 0; + post1D->tf_pts.red[586].value = 0; + post1D->tf_pts.green[586].value = 0; + post1D->tf_pts.blue[586].value = 0; + post1D->tf_pts.red[587].value = 0; + post1D->tf_pts.green[587].value = 0; + post1D->tf_pts.blue[587].value = 0; + post1D->tf_pts.red[588].value = 0; + post1D->tf_pts.green[588].value = 0; + post1D->tf_pts.blue[588].value = 0; + post1D->tf_pts.red[589].value = 0; + post1D->tf_pts.green[589].value = 0; + post1D->tf_pts.blue[589].value = 0; + post1D->tf_pts.red[590].value = 0; + post1D->tf_pts.green[590].value = 0; + post1D->tf_pts.blue[590].value = 0; + post1D->tf_pts.red[591].value = 0; + post1D->tf_pts.green[591].value = 0; + post1D->tf_pts.blue[591].value = 0; + post1D->tf_pts.red[592].value = 0; + post1D->tf_pts.green[592].value = 0; + post1D->tf_pts.blue[592].value = 0; + post1D->tf_pts.red[593].value = 0; + post1D->tf_pts.green[593].value = 0; + post1D->tf_pts.blue[593].value = 0; + post1D->tf_pts.red[594].value = 0; + post1D->tf_pts.green[594].value = 0; + post1D->tf_pts.blue[594].value = 0; + post1D->tf_pts.red[595].value = 0; + post1D->tf_pts.green[595].value = 0; + post1D->tf_pts.blue[595].value = 0; + post1D->tf_pts.red[596].value = 0; + post1D->tf_pts.green[596].value = 0; + post1D->tf_pts.blue[596].value = 0; + post1D->tf_pts.red[597].value = 0; + post1D->tf_pts.green[597].value = 0; + post1D->tf_pts.blue[597].value = 0; + post1D->tf_pts.red[598].value = 0; + post1D->tf_pts.green[598].value = 0; + post1D->tf_pts.blue[598].value = 0; + post1D->tf_pts.red[599].value = 0; + post1D->tf_pts.green[599].value = 0; + post1D->tf_pts.blue[599].value = 0; + post1D->tf_pts.red[600].value = 0; + post1D->tf_pts.green[600].value = 0; + post1D->tf_pts.blue[600].value = 0; + post1D->tf_pts.red[601].value = 0; + post1D->tf_pts.green[601].value = 0; + post1D->tf_pts.blue[601].value = 0; + post1D->tf_pts.red[602].value = 0; + post1D->tf_pts.green[602].value = 0; + post1D->tf_pts.blue[602].value = 0; + post1D->tf_pts.red[603].value = 0; + post1D->tf_pts.green[603].value = 0; + post1D->tf_pts.blue[603].value = 0; + post1D->tf_pts.red[604].value = 0; + post1D->tf_pts.green[604].value = 0; + post1D->tf_pts.blue[604].value = 0; + post1D->tf_pts.red[605].value = 0; + post1D->tf_pts.green[605].value = 0; + post1D->tf_pts.blue[605].value = 0; + post1D->tf_pts.red[606].value = 0; + post1D->tf_pts.green[606].value = 0; + post1D->tf_pts.blue[606].value = 0; + post1D->tf_pts.red[607].value = 0; + post1D->tf_pts.green[607].value = 0; + post1D->tf_pts.blue[607].value = 0; + post1D->tf_pts.red[608].value = 0; + post1D->tf_pts.green[608].value = 0; + post1D->tf_pts.blue[608].value = 0; + post1D->tf_pts.red[609].value = 0; + post1D->tf_pts.green[609].value = 0; + post1D->tf_pts.blue[609].value = 0; + post1D->tf_pts.red[610].value = 0; + post1D->tf_pts.green[610].value = 0; + post1D->tf_pts.blue[610].value = 0; + post1D->tf_pts.red[611].value = 0; + post1D->tf_pts.green[611].value = 0; + post1D->tf_pts.blue[611].value = 0; + post1D->tf_pts.red[612].value = 0; + post1D->tf_pts.green[612].value = 0; + post1D->tf_pts.blue[612].value = 0; + post1D->tf_pts.red[613].value = 0; + post1D->tf_pts.green[613].value = 0; + post1D->tf_pts.blue[613].value = 0; + post1D->tf_pts.red[614].value = 0; + post1D->tf_pts.green[614].value = 0; + post1D->tf_pts.blue[614].value = 0; + post1D->tf_pts.red[615].value = 0; + post1D->tf_pts.green[615].value = 0; + post1D->tf_pts.blue[615].value = 0; + post1D->tf_pts.red[616].value = 0; + post1D->tf_pts.green[616].value = 0; + post1D->tf_pts.blue[616].value = 0; + post1D->tf_pts.red[617].value = 0; + post1D->tf_pts.green[617].value = 0; + post1D->tf_pts.blue[617].value = 0; + post1D->tf_pts.red[618].value = 0; + post1D->tf_pts.green[618].value = 0; + post1D->tf_pts.blue[618].value = 0; + post1D->tf_pts.red[619].value = 0; + post1D->tf_pts.green[619].value = 0; + post1D->tf_pts.blue[619].value = 0; + post1D->tf_pts.red[620].value = 0; + post1D->tf_pts.green[620].value = 0; + post1D->tf_pts.blue[620].value = 0; + post1D->tf_pts.red[621].value = 0; + post1D->tf_pts.green[621].value = 0; + post1D->tf_pts.blue[621].value = 0; + post1D->tf_pts.red[622].value = 0; + post1D->tf_pts.green[622].value = 0; + post1D->tf_pts.blue[622].value = 0; + post1D->tf_pts.red[623].value = 0; + post1D->tf_pts.green[623].value = 0; + post1D->tf_pts.blue[623].value = 0; + post1D->tf_pts.red[624].value = 0; + post1D->tf_pts.green[624].value = 0; + post1D->tf_pts.blue[624].value = 0; + post1D->tf_pts.red[625].value = 0; + post1D->tf_pts.green[625].value = 0; + post1D->tf_pts.blue[625].value = 0; + post1D->tf_pts.red[626].value = 0; + post1D->tf_pts.green[626].value = 0; + post1D->tf_pts.blue[626].value = 0; + post1D->tf_pts.red[627].value = 0; + post1D->tf_pts.green[627].value = 0; + post1D->tf_pts.blue[627].value = 0; + post1D->tf_pts.red[628].value = 0; + post1D->tf_pts.green[628].value = 0; + post1D->tf_pts.blue[628].value = 0; + post1D->tf_pts.red[629].value = 0; + post1D->tf_pts.green[629].value = 0; + post1D->tf_pts.blue[629].value = 0; + post1D->tf_pts.red[630].value = 0; + post1D->tf_pts.green[630].value = 0; + post1D->tf_pts.blue[630].value = 0; + post1D->tf_pts.red[631].value = 0; + post1D->tf_pts.green[631].value = 0; + post1D->tf_pts.blue[631].value = 0; + post1D->tf_pts.red[632].value = 0; + post1D->tf_pts.green[632].value = 0; + post1D->tf_pts.blue[632].value = 0; + post1D->tf_pts.red[633].value = 0; + post1D->tf_pts.green[633].value = 0; + post1D->tf_pts.blue[633].value = 0; + post1D->tf_pts.red[634].value = 0; + post1D->tf_pts.green[634].value = 0; + post1D->tf_pts.blue[634].value = 0; + post1D->tf_pts.red[635].value = 0; + post1D->tf_pts.green[635].value = 0; + post1D->tf_pts.blue[635].value = 0; + post1D->tf_pts.red[636].value = 0; + post1D->tf_pts.green[636].value = 0; + post1D->tf_pts.blue[636].value = 0; + post1D->tf_pts.red[637].value = 0; + post1D->tf_pts.green[637].value = 0; + post1D->tf_pts.blue[637].value = 0; + post1D->tf_pts.red[638].value = 0; + post1D->tf_pts.green[638].value = 0; + post1D->tf_pts.blue[638].value = 0; + post1D->tf_pts.red[639].value = 0; + post1D->tf_pts.green[639].value = 0; + post1D->tf_pts.blue[639].value = 0; + post1D->tf_pts.red[640].value = 0; + post1D->tf_pts.green[640].value = 0; + post1D->tf_pts.blue[640].value = 0; + post1D->tf_pts.red[641].value = 0; + post1D->tf_pts.green[641].value = 0; + post1D->tf_pts.blue[641].value = 0; + post1D->tf_pts.red[642].value = 0; + post1D->tf_pts.green[642].value = 0; + post1D->tf_pts.blue[642].value = 0; + post1D->tf_pts.red[643].value = 0; + post1D->tf_pts.green[643].value = 0; + post1D->tf_pts.blue[643].value = 0; + post1D->tf_pts.red[644].value = 0; + post1D->tf_pts.green[644].value = 0; + post1D->tf_pts.blue[644].value = 0; + post1D->tf_pts.red[645].value = 0; + post1D->tf_pts.green[645].value = 0; + post1D->tf_pts.blue[645].value = 0; + post1D->tf_pts.red[646].value = 0; + post1D->tf_pts.green[646].value = 0; + post1D->tf_pts.blue[646].value = 0; + post1D->tf_pts.red[647].value = 0; + post1D->tf_pts.green[647].value = 0; + post1D->tf_pts.blue[647].value = 0; + post1D->tf_pts.red[648].value = 0; + post1D->tf_pts.green[648].value = 0; + post1D->tf_pts.blue[648].value = 0; + post1D->tf_pts.red[649].value = 0; + post1D->tf_pts.green[649].value = 0; + post1D->tf_pts.blue[649].value = 0; + post1D->tf_pts.red[650].value = 0; + post1D->tf_pts.green[650].value = 0; + post1D->tf_pts.blue[650].value = 0; + post1D->tf_pts.red[651].value = 0; + post1D->tf_pts.green[651].value = 0; + post1D->tf_pts.blue[651].value = 0; + post1D->tf_pts.red[652].value = 0; + post1D->tf_pts.green[652].value = 0; + post1D->tf_pts.blue[652].value = 0; + post1D->tf_pts.red[653].value = 0; + post1D->tf_pts.green[653].value = 0; + post1D->tf_pts.blue[653].value = 0; + post1D->tf_pts.red[654].value = 0; + post1D->tf_pts.green[654].value = 0; + post1D->tf_pts.blue[654].value = 0; + post1D->tf_pts.red[655].value = 0; + post1D->tf_pts.green[655].value = 0; + post1D->tf_pts.blue[655].value = 0; + post1D->tf_pts.red[656].value = 0; + post1D->tf_pts.green[656].value = 0; + post1D->tf_pts.blue[656].value = 0; + post1D->tf_pts.red[657].value = 0; + post1D->tf_pts.green[657].value = 0; + post1D->tf_pts.blue[657].value = 0; + post1D->tf_pts.red[658].value = 0; + post1D->tf_pts.green[658].value = 0; + post1D->tf_pts.blue[658].value = 0; + post1D->tf_pts.red[659].value = 0; + post1D->tf_pts.green[659].value = 0; + post1D->tf_pts.blue[659].value = 0; + post1D->tf_pts.red[660].value = 0; + post1D->tf_pts.green[660].value = 0; + post1D->tf_pts.blue[660].value = 0; + post1D->tf_pts.red[661].value = 0; + post1D->tf_pts.green[661].value = 0; + post1D->tf_pts.blue[661].value = 0; + post1D->tf_pts.red[662].value = 0; + post1D->tf_pts.green[662].value = 0; + post1D->tf_pts.blue[662].value = 0; + post1D->tf_pts.red[663].value = 0; + post1D->tf_pts.green[663].value = 0; + post1D->tf_pts.blue[663].value = 0; + post1D->tf_pts.red[664].value = 0; + post1D->tf_pts.green[664].value = 0; + post1D->tf_pts.blue[664].value = 0; + post1D->tf_pts.red[665].value = 0; + post1D->tf_pts.green[665].value = 0; + post1D->tf_pts.blue[665].value = 0; + post1D->tf_pts.red[666].value = 0; + post1D->tf_pts.green[666].value = 0; + post1D->tf_pts.blue[666].value = 0; + post1D->tf_pts.red[667].value = 0; + post1D->tf_pts.green[667].value = 0; + post1D->tf_pts.blue[667].value = 0; + post1D->tf_pts.red[668].value = 0; + post1D->tf_pts.green[668].value = 0; + post1D->tf_pts.blue[668].value = 0; + post1D->tf_pts.red[669].value = 0; + post1D->tf_pts.green[669].value = 0; + post1D->tf_pts.blue[669].value = 0; + post1D->tf_pts.red[670].value = 0; + post1D->tf_pts.green[670].value = 0; + post1D->tf_pts.blue[670].value = 0; + post1D->tf_pts.red[671].value = 0; + post1D->tf_pts.green[671].value = 0; + post1D->tf_pts.blue[671].value = 0; + post1D->tf_pts.red[672].value = 0; + post1D->tf_pts.green[672].value = 0; + post1D->tf_pts.blue[672].value = 0; + post1D->tf_pts.red[673].value = 0; + post1D->tf_pts.green[673].value = 0; + post1D->tf_pts.blue[673].value = 0; + post1D->tf_pts.red[674].value = 0; + post1D->tf_pts.green[674].value = 0; + post1D->tf_pts.blue[674].value = 0; + post1D->tf_pts.red[675].value = 0; + post1D->tf_pts.green[675].value = 0; + post1D->tf_pts.blue[675].value = 0; + post1D->tf_pts.red[676].value = 0; + post1D->tf_pts.green[676].value = 0; + post1D->tf_pts.blue[676].value = 0; + post1D->tf_pts.red[677].value = 0; + post1D->tf_pts.green[677].value = 0; + post1D->tf_pts.blue[677].value = 0; + post1D->tf_pts.red[678].value = 0; + post1D->tf_pts.green[678].value = 0; + post1D->tf_pts.blue[678].value = 0; + post1D->tf_pts.red[679].value = 0; + post1D->tf_pts.green[679].value = 0; + post1D->tf_pts.blue[679].value = 0; + post1D->tf_pts.red[680].value = 0; + post1D->tf_pts.green[680].value = 0; + post1D->tf_pts.blue[680].value = 0; + post1D->tf_pts.red[681].value = 0; + post1D->tf_pts.green[681].value = 0; + post1D->tf_pts.blue[681].value = 0; + post1D->tf_pts.red[682].value = 0; + post1D->tf_pts.green[682].value = 0; + post1D->tf_pts.blue[682].value = 0; + post1D->tf_pts.red[683].value = 0; + post1D->tf_pts.green[683].value = 0; + post1D->tf_pts.blue[683].value = 0; + post1D->tf_pts.red[684].value = 0; + post1D->tf_pts.green[684].value = 0; + post1D->tf_pts.blue[684].value = 0; + post1D->tf_pts.red[685].value = 0; + post1D->tf_pts.green[685].value = 0; + post1D->tf_pts.blue[685].value = 0; + post1D->tf_pts.red[686].value = 0; + post1D->tf_pts.green[686].value = 0; + post1D->tf_pts.blue[686].value = 0; + post1D->tf_pts.red[687].value = 0; + post1D->tf_pts.green[687].value = 0; + post1D->tf_pts.blue[687].value = 0; + post1D->tf_pts.red[688].value = 0; + post1D->tf_pts.green[688].value = 0; + post1D->tf_pts.blue[688].value = 0; + post1D->tf_pts.red[689].value = 0; + post1D->tf_pts.green[689].value = 0; + post1D->tf_pts.blue[689].value = 0; + post1D->tf_pts.red[690].value = 0; + post1D->tf_pts.green[690].value = 0; + post1D->tf_pts.blue[690].value = 0; + post1D->tf_pts.red[691].value = 0; + post1D->tf_pts.green[691].value = 0; + post1D->tf_pts.blue[691].value = 0; + post1D->tf_pts.red[692].value = 0; + post1D->tf_pts.green[692].value = 0; + post1D->tf_pts.blue[692].value = 0; + post1D->tf_pts.red[693].value = 0; + post1D->tf_pts.green[693].value = 0; + post1D->tf_pts.blue[693].value = 0; + post1D->tf_pts.red[694].value = 0; + post1D->tf_pts.green[694].value = 0; + post1D->tf_pts.blue[694].value = 0; + post1D->tf_pts.red[695].value = 0; + post1D->tf_pts.green[695].value = 0; + post1D->tf_pts.blue[695].value = 0; + post1D->tf_pts.red[696].value = 0; + post1D->tf_pts.green[696].value = 0; + post1D->tf_pts.blue[696].value = 0; + post1D->tf_pts.red[697].value = 0; + post1D->tf_pts.green[697].value = 0; + post1D->tf_pts.blue[697].value = 0; + post1D->tf_pts.red[698].value = 0; + post1D->tf_pts.green[698].value = 0; + post1D->tf_pts.blue[698].value = 0; + post1D->tf_pts.red[699].value = 0; + post1D->tf_pts.green[699].value = 0; + post1D->tf_pts.blue[699].value = 0; + post1D->tf_pts.red[700].value = 0; + post1D->tf_pts.green[700].value = 0; + post1D->tf_pts.blue[700].value = 0; + post1D->tf_pts.red[701].value = 0; + post1D->tf_pts.green[701].value = 0; + post1D->tf_pts.blue[701].value = 0; + post1D->tf_pts.red[702].value = 0; + post1D->tf_pts.green[702].value = 0; + post1D->tf_pts.blue[702].value = 0; + post1D->tf_pts.red[703].value = 0; + post1D->tf_pts.green[703].value = 0; + post1D->tf_pts.blue[703].value = 0; + post1D->tf_pts.red[704].value = 0; + post1D->tf_pts.green[704].value = 0; + post1D->tf_pts.blue[704].value = 0; + post1D->tf_pts.red[705].value = 0; + post1D->tf_pts.green[705].value = 0; + post1D->tf_pts.blue[705].value = 0; + post1D->tf_pts.red[706].value = 0; + post1D->tf_pts.green[706].value = 0; + post1D->tf_pts.blue[706].value = 0; + post1D->tf_pts.red[707].value = 0; + post1D->tf_pts.green[707].value = 0; + post1D->tf_pts.blue[707].value = 0; + post1D->tf_pts.red[708].value = 0; + post1D->tf_pts.green[708].value = 0; + post1D->tf_pts.blue[708].value = 0; + post1D->tf_pts.red[709].value = 0; + post1D->tf_pts.green[709].value = 0; + post1D->tf_pts.blue[709].value = 0; + post1D->tf_pts.red[710].value = 0; + post1D->tf_pts.green[710].value = 0; + post1D->tf_pts.blue[710].value = 0; + post1D->tf_pts.red[711].value = 0; + post1D->tf_pts.green[711].value = 0; + post1D->tf_pts.blue[711].value = 0; + post1D->tf_pts.red[712].value = 0; + post1D->tf_pts.green[712].value = 0; + post1D->tf_pts.blue[712].value = 0; + post1D->tf_pts.red[713].value = 0; + post1D->tf_pts.green[713].value = 0; + post1D->tf_pts.blue[713].value = 0; + post1D->tf_pts.red[714].value = 0; + post1D->tf_pts.green[714].value = 0; + post1D->tf_pts.blue[714].value = 0; + post1D->tf_pts.red[715].value = 0; + post1D->tf_pts.green[715].value = 0; + post1D->tf_pts.blue[715].value = 0; + post1D->tf_pts.red[716].value = 0; + post1D->tf_pts.green[716].value = 0; + post1D->tf_pts.blue[716].value = 0; + post1D->tf_pts.red[717].value = 0; + post1D->tf_pts.green[717].value = 0; + post1D->tf_pts.blue[717].value = 0; + post1D->tf_pts.red[718].value = 0; + post1D->tf_pts.green[718].value = 0; + post1D->tf_pts.blue[718].value = 0; + post1D->tf_pts.red[719].value = 0; + post1D->tf_pts.green[719].value = 0; + post1D->tf_pts.blue[719].value = 0; + post1D->tf_pts.red[720].value = 0; + post1D->tf_pts.green[720].value = 0; + post1D->tf_pts.blue[720].value = 0; + post1D->tf_pts.red[721].value = 0; + post1D->tf_pts.green[721].value = 0; + post1D->tf_pts.blue[721].value = 0; + post1D->tf_pts.red[722].value = 0; + post1D->tf_pts.green[722].value = 0; + post1D->tf_pts.blue[722].value = 0; + post1D->tf_pts.red[723].value = 0; + post1D->tf_pts.green[723].value = 0; + post1D->tf_pts.blue[723].value = 0; + post1D->tf_pts.red[724].value = 0; + post1D->tf_pts.green[724].value = 0; + post1D->tf_pts.blue[724].value = 0; + post1D->tf_pts.red[725].value = 0; + post1D->tf_pts.green[725].value = 0; + post1D->tf_pts.blue[725].value = 0; + post1D->tf_pts.red[726].value = 0; + post1D->tf_pts.green[726].value = 0; + post1D->tf_pts.blue[726].value = 0; + post1D->tf_pts.red[727].value = 0; + post1D->tf_pts.green[727].value = 0; + post1D->tf_pts.blue[727].value = 0; + post1D->tf_pts.red[728].value = 0; + post1D->tf_pts.green[728].value = 0; + post1D->tf_pts.blue[728].value = 0; + post1D->tf_pts.red[729].value = 0; + post1D->tf_pts.green[729].value = 0; + post1D->tf_pts.blue[729].value = 0; + post1D->tf_pts.red[730].value = 0; + post1D->tf_pts.green[730].value = 0; + post1D->tf_pts.blue[730].value = 0; + post1D->tf_pts.red[731].value = 0; + post1D->tf_pts.green[731].value = 0; + post1D->tf_pts.blue[731].value = 0; + post1D->tf_pts.red[732].value = 0; + post1D->tf_pts.green[732].value = 0; + post1D->tf_pts.blue[732].value = 0; + post1D->tf_pts.red[733].value = 0; + post1D->tf_pts.green[733].value = 0; + post1D->tf_pts.blue[733].value = 0; + post1D->tf_pts.red[734].value = 0; + post1D->tf_pts.green[734].value = 0; + post1D->tf_pts.blue[734].value = 0; + post1D->tf_pts.red[735].value = 0; + post1D->tf_pts.green[735].value = 0; + post1D->tf_pts.blue[735].value = 0; + post1D->tf_pts.red[736].value = 0; + post1D->tf_pts.green[736].value = 0; + post1D->tf_pts.blue[736].value = 0; + post1D->tf_pts.red[737].value = 0; + post1D->tf_pts.green[737].value = 0; + post1D->tf_pts.blue[737].value = 0; + post1D->tf_pts.red[738].value = 0; + post1D->tf_pts.green[738].value = 0; + post1D->tf_pts.blue[738].value = 0; + post1D->tf_pts.red[739].value = 0; + post1D->tf_pts.green[739].value = 0; + post1D->tf_pts.blue[739].value = 0; + post1D->tf_pts.red[740].value = 0; + post1D->tf_pts.green[740].value = 0; + post1D->tf_pts.blue[740].value = 0; + post1D->tf_pts.red[741].value = 0; + post1D->tf_pts.green[741].value = 0; + post1D->tf_pts.blue[741].value = 0; + post1D->tf_pts.red[742].value = 0; + post1D->tf_pts.green[742].value = 0; + post1D->tf_pts.blue[742].value = 0; + post1D->tf_pts.red[743].value = 0; + post1D->tf_pts.green[743].value = 0; + post1D->tf_pts.blue[743].value = 0; + post1D->tf_pts.red[744].value = 0; + post1D->tf_pts.green[744].value = 0; + post1D->tf_pts.blue[744].value = 0; + post1D->tf_pts.red[745].value = 0; + post1D->tf_pts.green[745].value = 0; + post1D->tf_pts.blue[745].value = 0; + post1D->tf_pts.red[746].value = 0; + post1D->tf_pts.green[746].value = 0; + post1D->tf_pts.blue[746].value = 0; + post1D->tf_pts.red[747].value = 0; + post1D->tf_pts.green[747].value = 0; + post1D->tf_pts.blue[747].value = 0; + post1D->tf_pts.red[748].value = 0; + post1D->tf_pts.green[748].value = 0; + post1D->tf_pts.blue[748].value = 0; + post1D->tf_pts.red[749].value = 0; + post1D->tf_pts.green[749].value = 0; + post1D->tf_pts.blue[749].value = 0; + post1D->tf_pts.red[750].value = 0; + post1D->tf_pts.green[750].value = 0; + post1D->tf_pts.blue[750].value = 0; + post1D->tf_pts.red[751].value = 0; + post1D->tf_pts.green[751].value = 0; + post1D->tf_pts.blue[751].value = 0; + post1D->tf_pts.red[752].value = 0; + post1D->tf_pts.green[752].value = 0; + post1D->tf_pts.blue[752].value = 0; + post1D->tf_pts.red[753].value = 0; + post1D->tf_pts.green[753].value = 0; + post1D->tf_pts.blue[753].value = 0; + post1D->tf_pts.red[754].value = 0; + post1D->tf_pts.green[754].value = 0; + post1D->tf_pts.blue[754].value = 0; + post1D->tf_pts.red[755].value = 0; + post1D->tf_pts.green[755].value = 0; + post1D->tf_pts.blue[755].value = 0; + post1D->tf_pts.red[756].value = 0; + post1D->tf_pts.green[756].value = 0; + post1D->tf_pts.blue[756].value = 0; + post1D->tf_pts.red[757].value = 0; + post1D->tf_pts.green[757].value = 0; + post1D->tf_pts.blue[757].value = 0; + post1D->tf_pts.red[758].value = 0; + post1D->tf_pts.green[758].value = 0; + post1D->tf_pts.blue[758].value = 0; + post1D->tf_pts.red[759].value = 0; + post1D->tf_pts.green[759].value = 0; + post1D->tf_pts.blue[759].value = 0; + post1D->tf_pts.red[760].value = 0; + post1D->tf_pts.green[760].value = 0; + post1D->tf_pts.blue[760].value = 0; + post1D->tf_pts.red[761].value = 0; + post1D->tf_pts.green[761].value = 0; + post1D->tf_pts.blue[761].value = 0; + post1D->tf_pts.red[762].value = 0; + post1D->tf_pts.green[762].value = 0; + post1D->tf_pts.blue[762].value = 0; + post1D->tf_pts.red[763].value = 0; + post1D->tf_pts.green[763].value = 0; + post1D->tf_pts.blue[763].value = 0; + post1D->tf_pts.red[764].value = 0; + post1D->tf_pts.green[764].value = 0; + post1D->tf_pts.blue[764].value = 0; + post1D->tf_pts.red[765].value = 0; + post1D->tf_pts.green[765].value = 0; + post1D->tf_pts.blue[765].value = 0; + post1D->tf_pts.red[766].value = 0; + post1D->tf_pts.green[766].value = 0; + post1D->tf_pts.blue[766].value = 0; + post1D->tf_pts.red[767].value = 0; + post1D->tf_pts.green[767].value = 0; + post1D->tf_pts.blue[767].value = 0; + post1D->tf_pts.red[768].value = 0; + post1D->tf_pts.green[768].value = 0; + post1D->tf_pts.blue[768].value = 0; + post1D->tf_pts.red[769].value = 0; + post1D->tf_pts.green[769].value = 0; + post1D->tf_pts.blue[769].value = 0; + post1D->tf_pts.red[770].value = 0; + post1D->tf_pts.green[770].value = 0; + post1D->tf_pts.blue[770].value = 0; + post1D->tf_pts.red[771].value = 0; + post1D->tf_pts.green[771].value = 0; + post1D->tf_pts.blue[771].value = 0; + post1D->tf_pts.red[772].value = 0; + post1D->tf_pts.green[772].value = 0; + post1D->tf_pts.blue[772].value = 0; + post1D->tf_pts.red[773].value = 0; + post1D->tf_pts.green[773].value = 0; + post1D->tf_pts.blue[773].value = 0; + post1D->tf_pts.red[774].value = 0; + post1D->tf_pts.green[774].value = 0; + post1D->tf_pts.blue[774].value = 0; + post1D->tf_pts.red[775].value = 0; + post1D->tf_pts.green[775].value = 0; + post1D->tf_pts.blue[775].value = 0; + post1D->tf_pts.red[776].value = 0; + post1D->tf_pts.green[776].value = 0; + post1D->tf_pts.blue[776].value = 0; + post1D->tf_pts.red[777].value = 0; + post1D->tf_pts.green[777].value = 0; + post1D->tf_pts.blue[777].value = 0; + post1D->tf_pts.red[778].value = 0; + post1D->tf_pts.green[778].value = 0; + post1D->tf_pts.blue[778].value = 0; + post1D->tf_pts.red[779].value = 0; + post1D->tf_pts.green[779].value = 0; + post1D->tf_pts.blue[779].value = 0; + post1D->tf_pts.red[780].value = 0; + post1D->tf_pts.green[780].value = 0; + post1D->tf_pts.blue[780].value = 0; + post1D->tf_pts.red[781].value = 0; + post1D->tf_pts.green[781].value = 0; + post1D->tf_pts.blue[781].value = 0; + post1D->tf_pts.red[782].value = 0; + post1D->tf_pts.green[782].value = 0; + post1D->tf_pts.blue[782].value = 0; + post1D->tf_pts.red[783].value = 0; + post1D->tf_pts.green[783].value = 0; + post1D->tf_pts.blue[783].value = 0; + post1D->tf_pts.red[784].value = 0; + post1D->tf_pts.green[784].value = 0; + post1D->tf_pts.blue[784].value = 0; + post1D->tf_pts.red[785].value = 0; + post1D->tf_pts.green[785].value = 0; + post1D->tf_pts.blue[785].value = 0; + post1D->tf_pts.red[786].value = 0; + post1D->tf_pts.green[786].value = 0; + post1D->tf_pts.blue[786].value = 0; + post1D->tf_pts.red[787].value = 0; + post1D->tf_pts.green[787].value = 0; + post1D->tf_pts.blue[787].value = 0; + post1D->tf_pts.red[788].value = 0; + post1D->tf_pts.green[788].value = 0; + post1D->tf_pts.blue[788].value = 0; + post1D->tf_pts.red[789].value = 0; + post1D->tf_pts.green[789].value = 0; + post1D->tf_pts.blue[789].value = 0; + post1D->tf_pts.red[790].value = 0; + post1D->tf_pts.green[790].value = 0; + post1D->tf_pts.blue[790].value = 0; + post1D->tf_pts.red[791].value = 0; + post1D->tf_pts.green[791].value = 0; + post1D->tf_pts.blue[791].value = 0; + post1D->tf_pts.red[792].value = 0; + post1D->tf_pts.green[792].value = 0; + post1D->tf_pts.blue[792].value = 0; + post1D->tf_pts.red[793].value = 0; + post1D->tf_pts.green[793].value = 0; + post1D->tf_pts.blue[793].value = 0; + post1D->tf_pts.red[794].value = 0; + post1D->tf_pts.green[794].value = 0; + post1D->tf_pts.blue[794].value = 0; + post1D->tf_pts.red[795].value = 0; + post1D->tf_pts.green[795].value = 0; + post1D->tf_pts.blue[795].value = 0; + post1D->tf_pts.red[796].value = 0; + post1D->tf_pts.green[796].value = 0; + post1D->tf_pts.blue[796].value = 0; + post1D->tf_pts.red[797].value = 0; + post1D->tf_pts.green[797].value = 0; + post1D->tf_pts.blue[797].value = 0; + post1D->tf_pts.red[798].value = 0; + post1D->tf_pts.green[798].value = 0; + post1D->tf_pts.blue[798].value = 0; + post1D->tf_pts.red[799].value = 0; + post1D->tf_pts.green[799].value = 0; + post1D->tf_pts.blue[799].value = 0; + post1D->tf_pts.red[800].value = 0; + post1D->tf_pts.green[800].value = 0; + post1D->tf_pts.blue[800].value = 0; + post1D->tf_pts.red[801].value = 0; + post1D->tf_pts.green[801].value = 0; + post1D->tf_pts.blue[801].value = 0; + post1D->tf_pts.red[802].value = 0; + post1D->tf_pts.green[802].value = 0; + post1D->tf_pts.blue[802].value = 0; + post1D->tf_pts.red[803].value = 0; + post1D->tf_pts.green[803].value = 0; + post1D->tf_pts.blue[803].value = 0; + post1D->tf_pts.red[804].value = 0; + post1D->tf_pts.green[804].value = 0; + post1D->tf_pts.blue[804].value = 0; + post1D->tf_pts.red[805].value = 0; + post1D->tf_pts.green[805].value = 0; + post1D->tf_pts.blue[805].value = 0; + post1D->tf_pts.red[806].value = 0; + post1D->tf_pts.green[806].value = 0; + post1D->tf_pts.blue[806].value = 0; + post1D->tf_pts.red[807].value = 0; + post1D->tf_pts.green[807].value = 0; + post1D->tf_pts.blue[807].value = 0; + post1D->tf_pts.red[808].value = 0; + post1D->tf_pts.green[808].value = 0; + post1D->tf_pts.blue[808].value = 0; + post1D->tf_pts.red[809].value = 0; + post1D->tf_pts.green[809].value = 0; + post1D->tf_pts.blue[809].value = 0; + post1D->tf_pts.red[810].value = 0; + post1D->tf_pts.green[810].value = 0; + post1D->tf_pts.blue[810].value = 0; + post1D->tf_pts.red[811].value = 0; + post1D->tf_pts.green[811].value = 0; + post1D->tf_pts.blue[811].value = 0; + post1D->tf_pts.red[812].value = 0; + post1D->tf_pts.green[812].value = 0; + post1D->tf_pts.blue[812].value = 0; + post1D->tf_pts.red[813].value = 0; + post1D->tf_pts.green[813].value = 0; + post1D->tf_pts.blue[813].value = 0; + post1D->tf_pts.red[814].value = 0; + post1D->tf_pts.green[814].value = 0; + post1D->tf_pts.blue[814].value = 0; + post1D->tf_pts.red[815].value = 0; + post1D->tf_pts.green[815].value = 0; + post1D->tf_pts.blue[815].value = 0; + post1D->tf_pts.red[816].value = 0; + post1D->tf_pts.green[816].value = 0; + post1D->tf_pts.blue[816].value = 0; + post1D->tf_pts.red[817].value = 0; + post1D->tf_pts.green[817].value = 0; + post1D->tf_pts.blue[817].value = 0; + post1D->tf_pts.red[818].value = 0; + post1D->tf_pts.green[818].value = 0; + post1D->tf_pts.blue[818].value = 0; + post1D->tf_pts.red[819].value = 0; + post1D->tf_pts.green[819].value = 0; + post1D->tf_pts.blue[819].value = 0; + post1D->tf_pts.red[820].value = 0; + post1D->tf_pts.green[820].value = 0; + post1D->tf_pts.blue[820].value = 0; + post1D->tf_pts.red[821].value = 0; + post1D->tf_pts.green[821].value = 0; + post1D->tf_pts.blue[821].value = 0; + post1D->tf_pts.red[822].value = 0; + post1D->tf_pts.green[822].value = 0; + post1D->tf_pts.blue[822].value = 0; + post1D->tf_pts.red[823].value = 0; + post1D->tf_pts.green[823].value = 0; + post1D->tf_pts.blue[823].value = 0; + post1D->tf_pts.red[824].value = 0; + post1D->tf_pts.green[824].value = 0; + post1D->tf_pts.blue[824].value = 0; + post1D->tf_pts.red[825].value = 0; + post1D->tf_pts.green[825].value = 0; + post1D->tf_pts.blue[825].value = 0; + post1D->tf_pts.red[826].value = 0; + post1D->tf_pts.green[826].value = 0; + post1D->tf_pts.blue[826].value = 0; + post1D->tf_pts.red[827].value = 0; + post1D->tf_pts.green[827].value = 0; + post1D->tf_pts.blue[827].value = 0; + post1D->tf_pts.red[828].value = 0; + post1D->tf_pts.green[828].value = 0; + post1D->tf_pts.blue[828].value = 0; + post1D->tf_pts.red[829].value = 0; + post1D->tf_pts.green[829].value = 0; + post1D->tf_pts.blue[829].value = 0; + post1D->tf_pts.red[830].value = 0; + post1D->tf_pts.green[830].value = 0; + post1D->tf_pts.blue[830].value = 0; + post1D->tf_pts.red[831].value = 0; + post1D->tf_pts.green[831].value = 0; + post1D->tf_pts.blue[831].value = 0; + post1D->tf_pts.red[832].value = 0; + post1D->tf_pts.green[832].value = 0; + post1D->tf_pts.blue[832].value = 0; + post1D->tf_pts.red[833].value = 0; + post1D->tf_pts.green[833].value = 0; + post1D->tf_pts.blue[833].value = 0; + post1D->tf_pts.red[834].value = 0; + post1D->tf_pts.green[834].value = 0; + post1D->tf_pts.blue[834].value = 0; + post1D->tf_pts.red[835].value = 0; + post1D->tf_pts.green[835].value = 0; + post1D->tf_pts.blue[835].value = 0; + post1D->tf_pts.red[836].value = 0; + post1D->tf_pts.green[836].value = 0; + post1D->tf_pts.blue[836].value = 0; + post1D->tf_pts.red[837].value = 0; + post1D->tf_pts.green[837].value = 0; + post1D->tf_pts.blue[837].value = 0; + post1D->tf_pts.red[838].value = 0; + post1D->tf_pts.green[838].value = 0; + post1D->tf_pts.blue[838].value = 0; + post1D->tf_pts.red[839].value = 0; + post1D->tf_pts.green[839].value = 0; + post1D->tf_pts.blue[839].value = 0; + post1D->tf_pts.red[840].value = 0; + post1D->tf_pts.green[840].value = 0; + post1D->tf_pts.blue[840].value = 0; + post1D->tf_pts.red[841].value = 0; + post1D->tf_pts.green[841].value = 0; + post1D->tf_pts.blue[841].value = 0; + post1D->tf_pts.red[842].value = 0; + post1D->tf_pts.green[842].value = 0; + post1D->tf_pts.blue[842].value = 0; + post1D->tf_pts.red[843].value = 0; + post1D->tf_pts.green[843].value = 0; + post1D->tf_pts.blue[843].value = 0; + post1D->tf_pts.red[844].value = 0; + post1D->tf_pts.green[844].value = 0; + post1D->tf_pts.blue[844].value = 0; + post1D->tf_pts.red[845].value = 0; + post1D->tf_pts.green[845].value = 0; + post1D->tf_pts.blue[845].value = 0; + post1D->tf_pts.red[846].value = 0; + post1D->tf_pts.green[846].value = 0; + post1D->tf_pts.blue[846].value = 0; + post1D->tf_pts.red[847].value = 0; + post1D->tf_pts.green[847].value = 0; + post1D->tf_pts.blue[847].value = 0; + post1D->tf_pts.red[848].value = 0; + post1D->tf_pts.green[848].value = 0; + post1D->tf_pts.blue[848].value = 0; + post1D->tf_pts.red[849].value = 0; + post1D->tf_pts.green[849].value = 0; + post1D->tf_pts.blue[849].value = 0; + post1D->tf_pts.red[850].value = 0; + post1D->tf_pts.green[850].value = 0; + post1D->tf_pts.blue[850].value = 0; + post1D->tf_pts.red[851].value = 0; + post1D->tf_pts.green[851].value = 0; + post1D->tf_pts.blue[851].value = 0; + post1D->tf_pts.red[852].value = 0; + post1D->tf_pts.green[852].value = 0; + post1D->tf_pts.blue[852].value = 0; + post1D->tf_pts.red[853].value = 0; + post1D->tf_pts.green[853].value = 0; + post1D->tf_pts.blue[853].value = 0; + post1D->tf_pts.red[854].value = 0; + post1D->tf_pts.green[854].value = 0; + post1D->tf_pts.blue[854].value = 0; + post1D->tf_pts.red[855].value = 0; + post1D->tf_pts.green[855].value = 0; + post1D->tf_pts.blue[855].value = 0; + post1D->tf_pts.red[856].value = 0; + post1D->tf_pts.green[856].value = 0; + post1D->tf_pts.blue[856].value = 0; + post1D->tf_pts.red[857].value = 0; + post1D->tf_pts.green[857].value = 0; + post1D->tf_pts.blue[857].value = 0; + post1D->tf_pts.red[858].value = 0; + post1D->tf_pts.green[858].value = 0; + post1D->tf_pts.blue[858].value = 0; + post1D->tf_pts.red[859].value = 0; + post1D->tf_pts.green[859].value = 0; + post1D->tf_pts.blue[859].value = 0; + post1D->tf_pts.red[860].value = 0; + post1D->tf_pts.green[860].value = 0; + post1D->tf_pts.blue[860].value = 0; + post1D->tf_pts.red[861].value = 0; + post1D->tf_pts.green[861].value = 0; + post1D->tf_pts.blue[861].value = 0; + post1D->tf_pts.red[862].value = 0; + post1D->tf_pts.green[862].value = 0; + post1D->tf_pts.blue[862].value = 0; + post1D->tf_pts.red[863].value = 0; + post1D->tf_pts.green[863].value = 0; + post1D->tf_pts.blue[863].value = 0; + post1D->tf_pts.red[864].value = 0; + post1D->tf_pts.green[864].value = 0; + post1D->tf_pts.blue[864].value = 0; + post1D->tf_pts.red[865].value = 0; + post1D->tf_pts.green[865].value = 0; + post1D->tf_pts.blue[865].value = 0; + post1D->tf_pts.red[866].value = 0; + post1D->tf_pts.green[866].value = 0; + post1D->tf_pts.blue[866].value = 0; + post1D->tf_pts.red[867].value = 0; + post1D->tf_pts.green[867].value = 0; + post1D->tf_pts.blue[867].value = 0; + post1D->tf_pts.red[868].value = 0; + post1D->tf_pts.green[868].value = 0; + post1D->tf_pts.blue[868].value = 0; + post1D->tf_pts.red[869].value = 0; + post1D->tf_pts.green[869].value = 0; + post1D->tf_pts.blue[869].value = 0; + post1D->tf_pts.red[870].value = 0; + post1D->tf_pts.green[870].value = 0; + post1D->tf_pts.blue[870].value = 0; + post1D->tf_pts.red[871].value = 0; + post1D->tf_pts.green[871].value = 0; + post1D->tf_pts.blue[871].value = 0; + post1D->tf_pts.red[872].value = 0; + post1D->tf_pts.green[872].value = 0; + post1D->tf_pts.blue[872].value = 0; + post1D->tf_pts.red[873].value = 0; + post1D->tf_pts.green[873].value = 0; + post1D->tf_pts.blue[873].value = 0; + post1D->tf_pts.red[874].value = 0; + post1D->tf_pts.green[874].value = 0; + post1D->tf_pts.blue[874].value = 0; + post1D->tf_pts.red[875].value = 0; + post1D->tf_pts.green[875].value = 0; + post1D->tf_pts.blue[875].value = 0; + post1D->tf_pts.red[876].value = 0; + post1D->tf_pts.green[876].value = 0; + post1D->tf_pts.blue[876].value = 0; + post1D->tf_pts.red[877].value = 0; + post1D->tf_pts.green[877].value = 0; + post1D->tf_pts.blue[877].value = 0; + post1D->tf_pts.red[878].value = 0; + post1D->tf_pts.green[878].value = 0; + post1D->tf_pts.blue[878].value = 0; + post1D->tf_pts.red[879].value = 0; + post1D->tf_pts.green[879].value = 0; + post1D->tf_pts.blue[879].value = 0; + post1D->tf_pts.red[880].value = 0; + post1D->tf_pts.green[880].value = 0; + post1D->tf_pts.blue[880].value = 0; + post1D->tf_pts.red[881].value = 0; + post1D->tf_pts.green[881].value = 0; + post1D->tf_pts.blue[881].value = 0; + post1D->tf_pts.red[882].value = 0; + post1D->tf_pts.green[882].value = 0; + post1D->tf_pts.blue[882].value = 0; + post1D->tf_pts.red[883].value = 0; + post1D->tf_pts.green[883].value = 0; + post1D->tf_pts.blue[883].value = 0; + post1D->tf_pts.red[884].value = 0; + post1D->tf_pts.green[884].value = 0; + post1D->tf_pts.blue[884].value = 0; + post1D->tf_pts.red[885].value = 0; + post1D->tf_pts.green[885].value = 0; + post1D->tf_pts.blue[885].value = 0; + post1D->tf_pts.red[886].value = 0; + post1D->tf_pts.green[886].value = 0; + post1D->tf_pts.blue[886].value = 0; + post1D->tf_pts.red[887].value = 0; + post1D->tf_pts.green[887].value = 0; + post1D->tf_pts.blue[887].value = 0; + post1D->tf_pts.red[888].value = 0; + post1D->tf_pts.green[888].value = 0; + post1D->tf_pts.blue[888].value = 0; + post1D->tf_pts.red[889].value = 0; + post1D->tf_pts.green[889].value = 0; + post1D->tf_pts.blue[889].value = 0; + post1D->tf_pts.red[890].value = 0; + post1D->tf_pts.green[890].value = 0; + post1D->tf_pts.blue[890].value = 0; + post1D->tf_pts.red[891].value = 0; + post1D->tf_pts.green[891].value = 0; + post1D->tf_pts.blue[891].value = 0; + post1D->tf_pts.red[892].value = 0; + post1D->tf_pts.green[892].value = 0; + post1D->tf_pts.blue[892].value = 0; + post1D->tf_pts.red[893].value = 0; + post1D->tf_pts.green[893].value = 0; + post1D->tf_pts.blue[893].value = 0; + post1D->tf_pts.red[894].value = 0; + post1D->tf_pts.green[894].value = 0; + post1D->tf_pts.blue[894].value = 0; + post1D->tf_pts.red[895].value = 0; + post1D->tf_pts.green[895].value = 0; + post1D->tf_pts.blue[895].value = 0; + post1D->tf_pts.red[896].value = 0; + post1D->tf_pts.green[896].value = 0; + post1D->tf_pts.blue[896].value = 0; + post1D->tf_pts.red[897].value = 0; + post1D->tf_pts.green[897].value = 0; + post1D->tf_pts.blue[897].value = 0; + post1D->tf_pts.red[898].value = 0; + post1D->tf_pts.green[898].value = 0; + post1D->tf_pts.blue[898].value = 0; + post1D->tf_pts.red[899].value = 0; + post1D->tf_pts.green[899].value = 0; + post1D->tf_pts.blue[899].value = 0; + post1D->tf_pts.red[900].value = 0; + post1D->tf_pts.green[900].value = 0; + post1D->tf_pts.blue[900].value = 0; + post1D->tf_pts.red[901].value = 0; + post1D->tf_pts.green[901].value = 0; + post1D->tf_pts.blue[901].value = 0; + post1D->tf_pts.red[902].value = 0; + post1D->tf_pts.green[902].value = 0; + post1D->tf_pts.blue[902].value = 0; + post1D->tf_pts.red[903].value = 0; + post1D->tf_pts.green[903].value = 0; + post1D->tf_pts.blue[903].value = 0; + post1D->tf_pts.red[904].value = 0; + post1D->tf_pts.green[904].value = 0; + post1D->tf_pts.blue[904].value = 0; + post1D->tf_pts.red[905].value = 0; + post1D->tf_pts.green[905].value = 0; + post1D->tf_pts.blue[905].value = 0; + post1D->tf_pts.red[906].value = 0; + post1D->tf_pts.green[906].value = 0; + post1D->tf_pts.blue[906].value = 0; + post1D->tf_pts.red[907].value = 0; + post1D->tf_pts.green[907].value = 0; + post1D->tf_pts.blue[907].value = 0; + post1D->tf_pts.red[908].value = 0; + post1D->tf_pts.green[908].value = 0; + post1D->tf_pts.blue[908].value = 0; + post1D->tf_pts.red[909].value = 0; + post1D->tf_pts.green[909].value = 0; + post1D->tf_pts.blue[909].value = 0; + post1D->tf_pts.red[910].value = 0; + post1D->tf_pts.green[910].value = 0; + post1D->tf_pts.blue[910].value = 0; + post1D->tf_pts.red[911].value = 0; + post1D->tf_pts.green[911].value = 0; + post1D->tf_pts.blue[911].value = 0; + post1D->tf_pts.red[912].value = 0; + post1D->tf_pts.green[912].value = 0; + post1D->tf_pts.blue[912].value = 0; + post1D->tf_pts.red[913].value = 0; + post1D->tf_pts.green[913].value = 0; + post1D->tf_pts.blue[913].value = 0; + post1D->tf_pts.red[914].value = 0; + post1D->tf_pts.green[914].value = 0; + post1D->tf_pts.blue[914].value = 0; + post1D->tf_pts.red[915].value = 0; + post1D->tf_pts.green[915].value = 0; + post1D->tf_pts.blue[915].value = 0; + post1D->tf_pts.red[916].value = 0; + post1D->tf_pts.green[916].value = 0; + post1D->tf_pts.blue[916].value = 0; + post1D->tf_pts.red[917].value = 0; + post1D->tf_pts.green[917].value = 0; + post1D->tf_pts.blue[917].value = 0; + post1D->tf_pts.red[918].value = 0; + post1D->tf_pts.green[918].value = 0; + post1D->tf_pts.blue[918].value = 0; + post1D->tf_pts.red[919].value = 0; + post1D->tf_pts.green[919].value = 0; + post1D->tf_pts.blue[919].value = 0; + post1D->tf_pts.red[920].value = 0; + post1D->tf_pts.green[920].value = 0; + post1D->tf_pts.blue[920].value = 0; + post1D->tf_pts.red[921].value = 0; + post1D->tf_pts.green[921].value = 0; + post1D->tf_pts.blue[921].value = 0; + post1D->tf_pts.red[922].value = 0; + post1D->tf_pts.green[922].value = 0; + post1D->tf_pts.blue[922].value = 0; + post1D->tf_pts.red[923].value = 0; + post1D->tf_pts.green[923].value = 0; + post1D->tf_pts.blue[923].value = 0; + post1D->tf_pts.red[924].value = 0; + post1D->tf_pts.green[924].value = 0; + post1D->tf_pts.blue[924].value = 0; + post1D->tf_pts.red[925].value = 0; + post1D->tf_pts.green[925].value = 0; + post1D->tf_pts.blue[925].value = 0; + post1D->tf_pts.red[926].value = 0; + post1D->tf_pts.green[926].value = 0; + post1D->tf_pts.blue[926].value = 0; + post1D->tf_pts.red[927].value = 0; + post1D->tf_pts.green[927].value = 0; + post1D->tf_pts.blue[927].value = 0; + post1D->tf_pts.red[928].value = 0; + post1D->tf_pts.green[928].value = 0; + post1D->tf_pts.blue[928].value = 0; + post1D->tf_pts.red[929].value = 0; + post1D->tf_pts.green[929].value = 0; + post1D->tf_pts.blue[929].value = 0; + post1D->tf_pts.red[930].value = 0; + post1D->tf_pts.green[930].value = 0; + post1D->tf_pts.blue[930].value = 0; + post1D->tf_pts.red[931].value = 0; + post1D->tf_pts.green[931].value = 0; + post1D->tf_pts.blue[931].value = 0; + post1D->tf_pts.red[932].value = 0; + post1D->tf_pts.green[932].value = 0; + post1D->tf_pts.blue[932].value = 0; + post1D->tf_pts.red[933].value = 0; + post1D->tf_pts.green[933].value = 0; + post1D->tf_pts.blue[933].value = 0; + post1D->tf_pts.red[934].value = 0; + post1D->tf_pts.green[934].value = 0; + post1D->tf_pts.blue[934].value = 0; + post1D->tf_pts.red[935].value = 0; + post1D->tf_pts.green[935].value = 0; + post1D->tf_pts.blue[935].value = 0; + post1D->tf_pts.red[936].value = 0; + post1D->tf_pts.green[936].value = 0; + post1D->tf_pts.blue[936].value = 0; + post1D->tf_pts.red[937].value = 0; + post1D->tf_pts.green[937].value = 0; + post1D->tf_pts.blue[937].value = 0; + post1D->tf_pts.red[938].value = 0; + post1D->tf_pts.green[938].value = 0; + post1D->tf_pts.blue[938].value = 0; + post1D->tf_pts.red[939].value = 0; + post1D->tf_pts.green[939].value = 0; + post1D->tf_pts.blue[939].value = 0; + post1D->tf_pts.red[940].value = 0; + post1D->tf_pts.green[940].value = 0; + post1D->tf_pts.blue[940].value = 0; + post1D->tf_pts.red[941].value = 0; + post1D->tf_pts.green[941].value = 0; + post1D->tf_pts.blue[941].value = 0; + post1D->tf_pts.red[942].value = 0; + post1D->tf_pts.green[942].value = 0; + post1D->tf_pts.blue[942].value = 0; + post1D->tf_pts.red[943].value = 0; + post1D->tf_pts.green[943].value = 0; + post1D->tf_pts.blue[943].value = 0; + post1D->tf_pts.red[944].value = 0; + post1D->tf_pts.green[944].value = 0; + post1D->tf_pts.blue[944].value = 0; + post1D->tf_pts.red[945].value = 0; + post1D->tf_pts.green[945].value = 0; + post1D->tf_pts.blue[945].value = 0; + post1D->tf_pts.red[946].value = 0; + post1D->tf_pts.green[946].value = 0; + post1D->tf_pts.blue[946].value = 0; + post1D->tf_pts.red[947].value = 0; + post1D->tf_pts.green[947].value = 0; + post1D->tf_pts.blue[947].value = 0; + post1D->tf_pts.red[948].value = 0; + post1D->tf_pts.green[948].value = 0; + post1D->tf_pts.blue[948].value = 0; + post1D->tf_pts.red[949].value = 0; + post1D->tf_pts.green[949].value = 0; + post1D->tf_pts.blue[949].value = 0; + post1D->tf_pts.red[950].value = 0; + post1D->tf_pts.green[950].value = 0; + post1D->tf_pts.blue[950].value = 0; + post1D->tf_pts.red[951].value = 0; + post1D->tf_pts.green[951].value = 0; + post1D->tf_pts.blue[951].value = 0; + post1D->tf_pts.red[952].value = 0; + post1D->tf_pts.green[952].value = 0; + post1D->tf_pts.blue[952].value = 0; + post1D->tf_pts.red[953].value = 0; + post1D->tf_pts.green[953].value = 0; + post1D->tf_pts.blue[953].value = 0; + post1D->tf_pts.red[954].value = 0; + post1D->tf_pts.green[954].value = 0; + post1D->tf_pts.blue[954].value = 0; + post1D->tf_pts.red[955].value = 0; + post1D->tf_pts.green[955].value = 0; + post1D->tf_pts.blue[955].value = 0; + post1D->tf_pts.red[956].value = 0; + post1D->tf_pts.green[956].value = 0; + post1D->tf_pts.blue[956].value = 0; + post1D->tf_pts.red[957].value = 0; + post1D->tf_pts.green[957].value = 0; + post1D->tf_pts.blue[957].value = 0; + post1D->tf_pts.red[958].value = 0; + post1D->tf_pts.green[958].value = 0; + post1D->tf_pts.blue[958].value = 0; + post1D->tf_pts.red[959].value = 0; + post1D->tf_pts.green[959].value = 0; + post1D->tf_pts.blue[959].value = 0; + post1D->tf_pts.red[960].value = 0; + post1D->tf_pts.green[960].value = 0; + post1D->tf_pts.blue[960].value = 0; + post1D->tf_pts.red[961].value = 0; + post1D->tf_pts.green[961].value = 0; + post1D->tf_pts.blue[961].value = 0; + post1D->tf_pts.red[962].value = 0; + post1D->tf_pts.green[962].value = 0; + post1D->tf_pts.blue[962].value = 0; + post1D->tf_pts.red[963].value = 0; + post1D->tf_pts.green[963].value = 0; + post1D->tf_pts.blue[963].value = 0; + post1D->tf_pts.red[964].value = 0; + post1D->tf_pts.green[964].value = 0; + post1D->tf_pts.blue[964].value = 0; + post1D->tf_pts.red[965].value = 0; + post1D->tf_pts.green[965].value = 0; + post1D->tf_pts.blue[965].value = 0; + post1D->tf_pts.red[966].value = 0; + post1D->tf_pts.green[966].value = 0; + post1D->tf_pts.blue[966].value = 0; + post1D->tf_pts.red[967].value = 0; + post1D->tf_pts.green[967].value = 0; + post1D->tf_pts.blue[967].value = 0; + post1D->tf_pts.red[968].value = 0; + post1D->tf_pts.green[968].value = 0; + post1D->tf_pts.blue[968].value = 0; + post1D->tf_pts.red[969].value = 0; + post1D->tf_pts.green[969].value = 0; + post1D->tf_pts.blue[969].value = 0; + post1D->tf_pts.red[970].value = 0; + post1D->tf_pts.green[970].value = 0; + post1D->tf_pts.blue[970].value = 0; + post1D->tf_pts.red[971].value = 0; + post1D->tf_pts.green[971].value = 0; + post1D->tf_pts.blue[971].value = 0; + post1D->tf_pts.red[972].value = 0; + post1D->tf_pts.green[972].value = 0; + post1D->tf_pts.blue[972].value = 0; + post1D->tf_pts.red[973].value = 0; + post1D->tf_pts.green[973].value = 0; + post1D->tf_pts.blue[973].value = 0; + post1D->tf_pts.red[974].value = 0; + post1D->tf_pts.green[974].value = 0; + post1D->tf_pts.blue[974].value = 0; + post1D->tf_pts.red[975].value = 0; + post1D->tf_pts.green[975].value = 0; + post1D->tf_pts.blue[975].value = 0; + post1D->tf_pts.red[976].value = 0; + post1D->tf_pts.green[976].value = 0; + post1D->tf_pts.blue[976].value = 0; + post1D->tf_pts.red[977].value = 0; + post1D->tf_pts.green[977].value = 0; + post1D->tf_pts.blue[977].value = 0; + post1D->tf_pts.red[978].value = 0; + post1D->tf_pts.green[978].value = 0; + post1D->tf_pts.blue[978].value = 0; + post1D->tf_pts.red[979].value = 0; + post1D->tf_pts.green[979].value = 0; + post1D->tf_pts.blue[979].value = 0; + post1D->tf_pts.red[980].value = 0; + post1D->tf_pts.green[980].value = 0; + post1D->tf_pts.blue[980].value = 0; + post1D->tf_pts.red[981].value = 0; + post1D->tf_pts.green[981].value = 0; + post1D->tf_pts.blue[981].value = 0; + post1D->tf_pts.red[982].value = 0; + post1D->tf_pts.green[982].value = 0; + post1D->tf_pts.blue[982].value = 0; + post1D->tf_pts.red[983].value = 0; + post1D->tf_pts.green[983].value = 0; + post1D->tf_pts.blue[983].value = 0; + post1D->tf_pts.red[984].value = 0; + post1D->tf_pts.green[984].value = 0; + post1D->tf_pts.blue[984].value = 0; + post1D->tf_pts.red[985].value = 0; + post1D->tf_pts.green[985].value = 0; + post1D->tf_pts.blue[985].value = 0; + post1D->tf_pts.red[986].value = 0; + post1D->tf_pts.green[986].value = 0; + post1D->tf_pts.blue[986].value = 0; + post1D->tf_pts.red[987].value = 0; + post1D->tf_pts.green[987].value = 0; + post1D->tf_pts.blue[987].value = 0; + post1D->tf_pts.red[988].value = 0; + post1D->tf_pts.green[988].value = 0; + post1D->tf_pts.blue[988].value = 0; + post1D->tf_pts.red[989].value = 0; + post1D->tf_pts.green[989].value = 0; + post1D->tf_pts.blue[989].value = 0; + post1D->tf_pts.red[990].value = 0; + post1D->tf_pts.green[990].value = 0; + post1D->tf_pts.blue[990].value = 0; + post1D->tf_pts.red[991].value = 0; + post1D->tf_pts.green[991].value = 0; + post1D->tf_pts.blue[991].value = 0; + post1D->tf_pts.red[992].value = 0; + post1D->tf_pts.green[992].value = 0; + post1D->tf_pts.blue[992].value = 0; + post1D->tf_pts.red[993].value = 0; + post1D->tf_pts.green[993].value = 0; + post1D->tf_pts.blue[993].value = 0; + post1D->tf_pts.red[994].value = 0; + post1D->tf_pts.green[994].value = 0; + post1D->tf_pts.blue[994].value = 0; + post1D->tf_pts.red[995].value = 0; + post1D->tf_pts.green[995].value = 0; + post1D->tf_pts.blue[995].value = 0; + post1D->tf_pts.red[996].value = 0; + post1D->tf_pts.green[996].value = 0; + post1D->tf_pts.blue[996].value = 0; + post1D->tf_pts.red[997].value = 0; + post1D->tf_pts.green[997].value = 0; + post1D->tf_pts.blue[997].value = 0; + post1D->tf_pts.red[998].value = 0; + post1D->tf_pts.green[998].value = 0; + post1D->tf_pts.blue[998].value = 0; + post1D->tf_pts.red[999].value = 0; + post1D->tf_pts.green[999].value = 0; + post1D->tf_pts.blue[999].value = 0; + post1D->tf_pts.red[1000].value = 0; + post1D->tf_pts.green[1000].value = 0; + post1D->tf_pts.blue[1000].value = 0; + post1D->tf_pts.red[1001].value = 0; + post1D->tf_pts.green[1001].value = 0; + post1D->tf_pts.blue[1001].value = 0; + post1D->tf_pts.red[1002].value = 0; + post1D->tf_pts.green[1002].value = 0; + post1D->tf_pts.blue[1002].value = 0; + post1D->tf_pts.red[1003].value = 0; + post1D->tf_pts.green[1003].value = 0; + post1D->tf_pts.blue[1003].value = 0; + post1D->tf_pts.red[1004].value = 0; + post1D->tf_pts.green[1004].value = 0; + post1D->tf_pts.blue[1004].value = 0; + post1D->tf_pts.red[1005].value = 0; + post1D->tf_pts.green[1005].value = 0; + post1D->tf_pts.blue[1005].value = 0; + post1D->tf_pts.red[1006].value = 0; + post1D->tf_pts.green[1006].value = 0; + post1D->tf_pts.blue[1006].value = 0; + post1D->tf_pts.red[1007].value = 0; + post1D->tf_pts.green[1007].value = 0; + post1D->tf_pts.blue[1007].value = 0; + post1D->tf_pts.red[1008].value = 0; + post1D->tf_pts.green[1008].value = 0; + post1D->tf_pts.blue[1008].value = 0; + post1D->tf_pts.red[1009].value = 0; + post1D->tf_pts.green[1009].value = 0; + post1D->tf_pts.blue[1009].value = 0; + post1D->tf_pts.red[1010].value = 0; + post1D->tf_pts.green[1010].value = 0; + post1D->tf_pts.blue[1010].value = 0; + post1D->tf_pts.red[1011].value = 0; + post1D->tf_pts.green[1011].value = 0; + post1D->tf_pts.blue[1011].value = 0; + post1D->tf_pts.red[1012].value = 0; + post1D->tf_pts.green[1012].value = 0; + post1D->tf_pts.blue[1012].value = 0; + post1D->tf_pts.red[1013].value = 0; + post1D->tf_pts.green[1013].value = 0; + post1D->tf_pts.blue[1013].value = 0; + post1D->tf_pts.red[1014].value = 0; + post1D->tf_pts.green[1014].value = 0; + post1D->tf_pts.blue[1014].value = 0; + post1D->tf_pts.red[1015].value = 0; + post1D->tf_pts.green[1015].value = 0; + post1D->tf_pts.blue[1015].value = 0; + post1D->tf_pts.red[1016].value = 0; + post1D->tf_pts.green[1016].value = 0; + post1D->tf_pts.blue[1016].value = 0; + post1D->tf_pts.red[1017].value = 0; + post1D->tf_pts.green[1017].value = 0; + post1D->tf_pts.blue[1017].value = 0; + post1D->tf_pts.red[1018].value = 0; + post1D->tf_pts.green[1018].value = 0; + post1D->tf_pts.blue[1018].value = 0; + post1D->tf_pts.red[1019].value = 0; + post1D->tf_pts.green[1019].value = 0; + post1D->tf_pts.blue[1019].value = 0; + post1D->tf_pts.red[1020].value = 0; + post1D->tf_pts.green[1020].value = 0; + post1D->tf_pts.blue[1020].value = 0; + post1D->tf_pts.red[1021].value = 0; + post1D->tf_pts.green[1021].value = 0; + post1D->tf_pts.blue[1021].value = 0; + post1D->tf_pts.red[1022].value = 0; + post1D->tf_pts.green[1022].value = 0; + post1D->tf_pts.blue[1022].value = 0; + post1D->tf_pts.red[1023].value = 0; + post1D->tf_pts.green[1023].value = 0; + post1D->tf_pts.blue[1023].value = 0; + post1D->tf_pts.red[1024].value = 0; + post1D->tf_pts.green[1024].value = 0; + post1D->tf_pts.blue[1024].value = 0; + + post1D->tf_pts.end_exponent = 0; + post1D->tf_pts.x_point_at_y1_red = 1; + post1D->tf_pts.x_point_at_y1_green = 1; + post1D->tf_pts.x_point_at_y1_blue = 1; + + return true; +} + +static const struct tetrahedral_17x17x17 tetra_ident_3dlut = { + {{0, 0, 0}, {1023, 0, 0}, {2047, 0, 0}, {3071, 0, 0}, {4095, 0, 0}, {767, 255, 0}, + {1791, 255, 0}, {2815, 255, 0}, {3839, 255, 0}, {511, 511, 0}, {1535, 511, 0}, + {2559, 511, 0}, {3583, 511, 0}, {255, 767, 0}, {1279, 767, 0}, {2303, 767, 0}, + {3327, 767, 0}, {0, 1023, 0}, {1023, 1023, 0}, {2047, 1023, 0}, {3071, 1023, 0}, + {4095, 1023, 0}, {767, 1279, 0}, {1791, 1279, 0}, {2815, 1279, 0}, {3839, 1279, 0}, + {511, 1535, 0}, {1535, 1535, 0}, {2559, 1535, 0}, {3583, 1535, 0}, {255, 1791, 0}, + {1279, 1791, 0}, {2303, 1791, 0}, {3327, 1791, 0}, {0, 2047, 0}, {1023, 2047, 0}, + {2047, 2047, 0}, {3071, 2047, 0}, {4095, 2047, 0}, {767, 2303, 0}, {1791, 2303, 0}, + {2815, 2303, 0}, {3839, 2303, 0}, {511, 2559, 0}, {1535, 2559, 0}, {2559, 2559, 0}, + {3583, 2559, 0}, {255, 2815, 0}, {1279, 2815, 0}, {2303, 2815, 0}, {3327, 2815, 0}, + {0, 3071, 0}, {1023, 3071, 0}, {2047, 3071, 0}, {3071, 3071, 0}, {4095, 3071, 0}, + {767, 3327, 0}, {1791, 3327, 0}, {2815, 3327, 0}, {3839, 3327, 0}, {511, 3583, 0}, + {1535, 3583, 0}, {2559, 3583, 0}, {3583, 3583, 0}, {255, 3839, 0}, {1279, 3839, 0}, + {2303, 3839, 0}, {3327, 3839, 0}, {0, 4095, 0}, {1023, 4095, 0}, {2047, 4095, 0}, + {3071, 4095, 0}, {4095, 4095, 0}, {767, 0, 255}, {1791, 0, 255}, {2815, 0, 255}, + {3839, 0, 255}, {511, 255, 255}, {1535, 255, 255}, {2559, 255, 255}, {3583, 255, 255}, + {255, 511, 255}, {1279, 511, 255}, {2303, 511, 255}, {3327, 511, 255}, {0, 767, 255}, + {1023, 767, 255}, {2047, 767, 255}, {3071, 767, 255}, {4095, 767, 255}, {767, 1023, 255}, + {1791, 1023, 255}, {2815, 1023, 255}, {3839, 1023, 255}, {511, 1279, 255}, + {1535, 1279, 255}, {2559, 1279, 255}, {3583, 1279, 255}, {255, 1535, 255}, + {1279, 1535, 255}, {2303, 1535, 255}, {3327, 1535, 255}, {0, 1791, 255}, {1023, 1791, 255}, + {2047, 1791, 255}, {3071, 1791, 255}, {4095, 1791, 255}, {767, 2047, 255}, + {1791, 2047, 255}, {2815, 2047, 255}, {3839, 2047, 255}, {511, 2303, 255}, + {1535, 2303, 255}, {2559, 2303, 255}, {3583, 2303, 255}, {255, 2559, 255}, + {1279, 2559, 255}, {2303, 2559, 255}, {3327, 2559, 255}, {0, 2815, 255}, {1023, 2815, 255}, + {2047, 2815, 255}, {3071, 2815, 255}, {4095, 2815, 255}, {767, 3071, 255}, + {1791, 3071, 255}, {2815, 3071, 255}, {3839, 3071, 255}, {511, 3327, 255}, + {1535, 3327, 255}, {2559, 3327, 255}, {3583, 3327, 255}, {255, 3583, 255}, + {1279, 3583, 255}, {2303, 3583, 255}, {3327, 3583, 255}, {0, 3839, 255}, {1023, 3839, 255}, + {2047, 3839, 255}, {3071, 3839, 255}, {4095, 3839, 255}, {767, 4095, 255}, + {1791, 4095, 255}, {2815, 4095, 255}, {3839, 4095, 255}, {511, 0, 511}, {1535, 0, 511}, + {2559, 0, 511}, {3583, 0, 511}, {255, 255, 511}, {1279, 255, 511}, {2303, 255, 511}, + {3327, 255, 511}, {0, 511, 511}, {1023, 511, 511}, {2047, 511, 511}, {3071, 511, 511}, + {4095, 511, 511}, {767, 767, 511}, {1791, 767, 511}, {2815, 767, 511}, {3839, 767, 511}, + {511, 1023, 511}, {1535, 1023, 511}, {2559, 1023, 511}, {3583, 1023, 511}, {255, 1279, 511}, + {1279, 1279, 511}, {2303, 1279, 511}, {3327, 1279, 511}, {0, 1535, 511}, {1023, 1535, 511}, + {2047, 1535, 511}, {3071, 1535, 511}, {4095, 1535, 511}, {767, 1791, 511}, + {1791, 1791, 511}, {2815, 1791, 511}, {3839, 1791, 511}, {511, 2047, 511}, + {1535, 2047, 511}, {2559, 2047, 511}, {3583, 2047, 511}, {255, 2303, 511}, + {1279, 2303, 511}, {2303, 2303, 511}, {3327, 2303, 511}, {0, 2559, 511}, {1023, 2559, 511}, + {2047, 2559, 511}, {3071, 2559, 511}, {4095, 2559, 511}, {767, 2815, 511}, + {1791, 2815, 511}, {2815, 2815, 511}, {3839, 2815, 511}, {511, 3071, 511}, + {1535, 3071, 511}, {2559, 3071, 511}, {3583, 3071, 511}, {255, 3327, 511}, + {1279, 3327, 511}, {2303, 3327, 511}, {3327, 3327, 511}, {0, 3583, 511}, {1023, 3583, 511}, + {2047, 3583, 511}, {3071, 3583, 511}, {4095, 3583, 511}, {767, 3839, 511}, + {1791, 3839, 511}, {2815, 3839, 511}, {3839, 3839, 511}, {511, 4095, 511}, + {1535, 4095, 511}, {2559, 4095, 511}, {3583, 4095, 511}, {255, 0, 767}, {1279, 0, 767}, + {2303, 0, 767}, {3327, 0, 767}, {0, 255, 767}, {1023, 255, 767}, {2047, 255, 767}, + {3071, 255, 767}, {4095, 255, 767}, {767, 511, 767}, {1791, 511, 767}, {2815, 511, 767}, + {3839, 511, 767}, {511, 767, 767}, {1535, 767, 767}, {2559, 767, 767}, {3583, 767, 767}, + {255, 1023, 767}, {1279, 1023, 767}, {2303, 1023, 767}, {3327, 1023, 767}, {0, 1279, 767}, + {1023, 1279, 767}, {2047, 1279, 767}, {3071, 1279, 767}, {4095, 1279, 767}, + {767, 1535, 767}, {1791, 1535, 767}, {2815, 1535, 767}, {3839, 1535, 767}, {511, 1791, 767}, + {1535, 1791, 767}, {2559, 1791, 767}, {3583, 1791, 767}, {255, 2047, 767}, + {1279, 2047, 767}, {2303, 2047, 767}, {3327, 2047, 767}, {0, 2303, 767}, {1023, 2303, 767}, + {2047, 2303, 767}, {3071, 2303, 767}, {4095, 2303, 767}, {767, 2559, 767}, + {1791, 2559, 767}, {2815, 2559, 767}, {3839, 2559, 767}, {511, 2815, 767}, + {1535, 2815, 767}, {2559, 2815, 767}, {3583, 2815, 767}, {255, 3071, 767}, + {1279, 3071, 767}, {2303, 3071, 767}, {3327, 3071, 767}, {0, 3327, 767}, {1023, 3327, 767}, + {2047, 3327, 767}, {3071, 3327, 767}, {4095, 3327, 767}, {767, 3583, 767}, + {1791, 3583, 767}, {2815, 3583, 767}, {3839, 3583, 767}, {511, 3839, 767}, + {1535, 3839, 767}, {2559, 3839, 767}, {3583, 3839, 767}, {255, 4095, 767}, + {1279, 4095, 767}, {2303, 4095, 767}, {3327, 4095, 767}, {0, 0, 1023}, {1023, 0, 1023}, + {2047, 0, 1023}, {3071, 0, 1023}, {4095, 0, 1023}, {767, 255, 1023}, {1791, 255, 1023}, + {2815, 255, 1023}, {3839, 255, 1023}, {511, 511, 1023}, {1535, 511, 1023}, + {2559, 511, 1023}, {3583, 511, 1023}, {255, 767, 1023}, {1279, 767, 1023}, + {2303, 767, 1023}, {3327, 767, 1023}, {0, 1023, 1023}, {1023, 1023, 1023}, + {2047, 1023, 1023}, {3071, 1023, 1023}, {4095, 1023, 1023}, {767, 1279, 1023}, + {1791, 1279, 1023}, {2815, 1279, 1023}, {3839, 1279, 1023}, {511, 1535, 1023}, + {1535, 1535, 1023}, {2559, 1535, 1023}, {3583, 1535, 1023}, {255, 1791, 1023}, + {1279, 1791, 1023}, {2303, 1791, 1023}, {3327, 1791, 1023}, {0, 2047, 1023}, + {1023, 2047, 1023}, {2047, 2047, 1023}, {3071, 2047, 1023}, {4095, 2047, 1023}, + {767, 2303, 1023}, {1791, 2303, 1023}, {2815, 2303, 1023}, {3839, 2303, 1023}, + {511, 2559, 1023}, {1535, 2559, 1023}, {2559, 2559, 1023}, {3583, 2559, 1023}, + {255, 2815, 1023}, {1279, 2815, 1023}, {2303, 2815, 1023}, {3327, 2815, 1023}, + {0, 3071, 1023}, {1023, 3071, 1023}, {2047, 3071, 1023}, {3071, 3071, 1023}, + {4095, 3071, 1023}, {767, 3327, 1023}, {1791, 3327, 1023}, {2815, 3327, 1023}, + {3839, 3327, 1023}, {511, 3583, 1023}, {1535, 3583, 1023}, {2559, 3583, 1023}, + {3583, 3583, 1023}, {255, 3839, 1023}, {1279, 3839, 1023}, {2303, 3839, 1023}, + {3327, 3839, 1023}, {0, 4095, 1023}, {1023, 4095, 1023}, {2047, 4095, 1023}, + {3071, 4095, 1023}, {4095, 4095, 1023}, {767, 0, 1279}, {1791, 0, 1279}, {2815, 0, 1279}, + {3839, 0, 1279}, {511, 255, 1279}, {1535, 255, 1279}, {2559, 255, 1279}, {3583, 255, 1279}, + {255, 511, 1279}, {1279, 511, 1279}, {2303, 511, 1279}, {3327, 511, 1279}, {0, 767, 1279}, + {1023, 767, 1279}, {2047, 767, 1279}, {3071, 767, 1279}, {4095, 767, 1279}, + {767, 1023, 1279}, {1791, 1023, 1279}, {2815, 1023, 1279}, {3839, 1023, 1279}, + {511, 1279, 1279}, {1535, 1279, 1279}, {2559, 1279, 1279}, {3583, 1279, 1279}, + {255, 1535, 1279}, {1279, 1535, 1279}, {2303, 1535, 1279}, {3327, 1535, 1279}, + {0, 1791, 1279}, {1023, 1791, 1279}, {2047, 1791, 1279}, {3071, 1791, 1279}, + {4095, 1791, 1279}, {767, 2047, 1279}, {1791, 2047, 1279}, {2815, 2047, 1279}, + {3839, 2047, 1279}, {511, 2303, 1279}, {1535, 2303, 1279}, {2559, 2303, 1279}, + {3583, 2303, 1279}, {255, 2559, 1279}, {1279, 2559, 1279}, {2303, 2559, 1279}, + {3327, 2559, 1279}, {0, 2815, 1279}, {1023, 2815, 1279}, {2047, 2815, 1279}, + {3071, 2815, 1279}, {4095, 2815, 1279}, {767, 3071, 1279}, {1791, 3071, 1279}, + {2815, 3071, 1279}, {3839, 3071, 1279}, {511, 3327, 1279}, {1535, 3327, 1279}, + {2559, 3327, 1279}, {3583, 3327, 1279}, {255, 3583, 1279}, {1279, 3583, 1279}, + {2303, 3583, 1279}, {3327, 3583, 1279}, {0, 3839, 1279}, {1023, 3839, 1279}, + {2047, 3839, 1279}, {3071, 3839, 1279}, {4095, 3839, 1279}, {767, 4095, 1279}, + {1791, 4095, 1279}, {2815, 4095, 1279}, {3839, 4095, 1279}, {511, 0, 1535}, {1535, 0, 1535}, + {2559, 0, 1535}, {3583, 0, 1535}, {255, 255, 1535}, {1279, 255, 1535}, {2303, 255, 1535}, + {3327, 255, 1535}, {0, 511, 1535}, {1023, 511, 1535}, {2047, 511, 1535}, {3071, 511, 1535}, + {4095, 511, 1535}, {767, 767, 1535}, {1791, 767, 1535}, {2815, 767, 1535}, + {3839, 767, 1535}, {511, 1023, 1535}, {1535, 1023, 1535}, {2559, 1023, 1535}, + {3583, 1023, 1535}, {255, 1279, 1535}, {1279, 1279, 1535}, {2303, 1279, 1535}, + {3327, 1279, 1535}, {0, 1535, 1535}, {1023, 1535, 1535}, {2047, 1535, 1535}, + {3071, 1535, 1535}, {4095, 1535, 1535}, {767, 1791, 1535}, {1791, 1791, 1535}, + {2815, 1791, 1535}, {3839, 1791, 1535}, {511, 2047, 1535}, {1535, 2047, 1535}, + {2559, 2047, 1535}, {3583, 2047, 1535}, {255, 2303, 1535}, {1279, 2303, 1535}, + {2303, 2303, 1535}, {3327, 2303, 1535}, {0, 2559, 1535}, {1023, 2559, 1535}, + {2047, 2559, 1535}, {3071, 2559, 1535}, {4095, 2559, 1535}, {767, 2815, 1535}, + {1791, 2815, 1535}, {2815, 2815, 1535}, {3839, 2815, 1535}, {511, 3071, 1535}, + {1535, 3071, 1535}, {2559, 3071, 1535}, {3583, 3071, 1535}, {255, 3327, 1535}, + {1279, 3327, 1535}, {2303, 3327, 1535}, {3327, 3327, 1535}, {0, 3583, 1535}, + {1023, 3583, 1535}, {2047, 3583, 1535}, {3071, 3583, 1535}, {4095, 3583, 1535}, + {767, 3839, 1535}, {1791, 3839, 1535}, {2815, 3839, 1535}, {3839, 3839, 1535}, + {511, 4095, 1535}, {1535, 4095, 1535}, {2559, 4095, 1535}, {3583, 4095, 1535}, + {255, 0, 1791}, {1279, 0, 1791}, {2303, 0, 1791}, {3327, 0, 1791}, {0, 255, 1791}, + {1023, 255, 1791}, {2047, 255, 1791}, {3071, 255, 1791}, {4095, 255, 1791}, + {767, 511, 1791}, {1791, 511, 1791}, {2815, 511, 1791}, {3839, 511, 1791}, {511, 767, 1791}, + {1535, 767, 1791}, {2559, 767, 1791}, {3583, 767, 1791}, {255, 1023, 1791}, + {1279, 1023, 1791}, {2303, 1023, 1791}, {3327, 1023, 1791}, {0, 1279, 1791}, + {1023, 1279, 1791}, {2047, 1279, 1791}, {3071, 1279, 1791}, {4095, 1279, 1791}, + {767, 1535, 1791}, {1791, 1535, 1791}, {2815, 1535, 1791}, {3839, 1535, 1791}, + {511, 1791, 1791}, {1535, 1791, 1791}, {2559, 1791, 1791}, {3583, 1791, 1791}, + {255, 2047, 1791}, {1279, 2047, 1791}, {2303, 2047, 1791}, {3327, 2047, 1791}, + {0, 2303, 1791}, {1023, 2303, 1791}, {2047, 2303, 1791}, {3071, 2303, 1791}, + {4095, 2303, 1791}, {767, 2559, 1791}, {1791, 2559, 1791}, {2815, 2559, 1791}, + {3839, 2559, 1791}, {511, 2815, 1791}, {1535, 2815, 1791}, {2559, 2815, 1791}, + {3583, 2815, 1791}, {255, 3071, 1791}, {1279, 3071, 1791}, {2303, 3071, 1791}, + {3327, 3071, 1791}, {0, 3327, 1791}, {1023, 3327, 1791}, {2047, 3327, 1791}, + {3071, 3327, 1791}, {4095, 3327, 1791}, {767, 3583, 1791}, {1791, 3583, 1791}, + {2815, 3583, 1791}, {3839, 3583, 1791}, {511, 3839, 1791}, {1535, 3839, 1791}, + {2559, 3839, 1791}, {3583, 3839, 1791}, {255, 4095, 1791}, {1279, 4095, 1791}, + {2303, 4095, 1791}, {3327, 4095, 1791}, {0, 0, 2047}, {1023, 0, 2047}, {2047, 0, 2047}, + {3071, 0, 2047}, {4095, 0, 2047}, {767, 255, 2047}, {1791, 255, 2047}, {2815, 255, 2047}, + {3839, 255, 2047}, {511, 511, 2047}, {1535, 511, 2047}, {2559, 511, 2047}, + {3583, 511, 2047}, {255, 767, 2047}, {1279, 767, 2047}, {2303, 767, 2047}, + {3327, 767, 2047}, {0, 1023, 2047}, {1023, 1023, 2047}, {2047, 1023, 2047}, + {3071, 1023, 2047}, {4095, 1023, 2047}, {767, 1279, 2047}, {1791, 1279, 2047}, + {2815, 1279, 2047}, {3839, 1279, 2047}, {511, 1535, 2047}, {1535, 1535, 2047}, + {2559, 1535, 2047}, {3583, 1535, 2047}, {255, 1791, 2047}, {1279, 1791, 2047}, + {2303, 1791, 2047}, {3327, 1791, 2047}, {0, 2047, 2047}, {1023, 2047, 2047}, + {2047, 2047, 2047}, {3071, 2047, 2047}, {4095, 2047, 2047}, {767, 2303, 2047}, + {1791, 2303, 2047}, {2815, 2303, 2047}, {3839, 2303, 2047}, {511, 2559, 2047}, + {1535, 2559, 2047}, {2559, 2559, 2047}, {3583, 2559, 2047}, {255, 2815, 2047}, + {1279, 2815, 2047}, {2303, 2815, 2047}, {3327, 2815, 2047}, {0, 3071, 2047}, + {1023, 3071, 2047}, {2047, 3071, 2047}, {3071, 3071, 2047}, {4095, 3071, 2047}, + {767, 3327, 2047}, {1791, 3327, 2047}, {2815, 3327, 2047}, {3839, 3327, 2047}, + {511, 3583, 2047}, {1535, 3583, 2047}, {2559, 3583, 2047}, {3583, 3583, 2047}, + {255, 3839, 2047}, {1279, 3839, 2047}, {2303, 3839, 2047}, {3327, 3839, 2047}, + {0, 4095, 2047}, {1023, 4095, 2047}, {2047, 4095, 2047}, {3071, 4095, 2047}, + {4095, 4095, 2047}, {767, 0, 2303}, {1791, 0, 2303}, {2815, 0, 2303}, {3839, 0, 2303}, + {511, 255, 2303}, {1535, 255, 2303}, {2559, 255, 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2815, 2047}, {1023, 2815, 2047}, + {2047, 2815, 2047}, {3071, 2815, 2047}, {4095, 2815, 2047}, {767, 3071, 2047}, + {1791, 3071, 2047}, {2815, 3071, 2047}, {3839, 3071, 2047}, {511, 3327, 2047}, + {1535, 3327, 2047}, {2559, 3327, 2047}, {3583, 3327, 2047}, {255, 3583, 2047}, + {1279, 3583, 2047}, {2303, 3583, 2047}, {3327, 3583, 2047}, {0, 3839, 2047}, + {1023, 3839, 2047}, {2047, 3839, 2047}, {3071, 3839, 2047}, {4095, 3839, 2047}, + {767, 4095, 2047}, {1791, 4095, 2047}, {2815, 4095, 2047}, {3839, 4095, 2047}, + {511, 0, 2303}, {1535, 0, 2303}, {2559, 0, 2303}, {3583, 0, 2303}, {255, 255, 2303}, + {1279, 255, 2303}, {2303, 255, 2303}, {3327, 255, 2303}, {0, 511, 2303}, {1023, 511, 2303}, + {2047, 511, 2303}, {3071, 511, 2303}, {4095, 511, 2303}, {767, 767, 2303}, + {1791, 767, 2303}, {2815, 767, 2303}, {3839, 767, 2303}, {511, 1023, 2303}, + {1535, 1023, 2303}, {2559, 1023, 2303}, {3583, 1023, 2303}, {255, 1279, 2303}, + {1279, 1279, 2303}, {2303, 1279, 2303}, {3327, 1279, 2303}, {0, 1535, 2303}, + {1023, 1535, 2303}, {2047, 1535, 2303}, {3071, 1535, 2303}, {4095, 1535, 2303}, + {767, 1791, 2303}, {1791, 1791, 2303}, {2815, 1791, 2303}, {3839, 1791, 2303}, + {511, 2047, 2303}, {1535, 2047, 2303}, {2559, 2047, 2303}, {3583, 2047, 2303}, + {255, 2303, 2303}, {1279, 2303, 2303}, {2303, 2303, 2303}, {3327, 2303, 2303}, + {0, 2559, 2303}, {1023, 2559, 2303}, {2047, 2559, 2303}, {3071, 2559, 2303}, + {4095, 2559, 2303}, {767, 2815, 2303}, {1791, 2815, 2303}, {2815, 2815, 2303}, + {3839, 2815, 2303}, {511, 3071, 2303}, {1535, 3071, 2303}, {2559, 3071, 2303}, + {3583, 3071, 2303}, {255, 3327, 2303}, {1279, 3327, 2303}, {2303, 3327, 2303}, + {3327, 3327, 2303}, {0, 3583, 2303}, {1023, 3583, 2303}, {2047, 3583, 2303}, + {3071, 3583, 2303}, {4095, 3583, 2303}, {767, 3839, 2303}, {1791, 3839, 2303}, + {2815, 3839, 2303}, {3839, 3839, 2303}, {511, 4095, 2303}, {1535, 4095, 2303}, + {2559, 4095, 2303}, {3583, 4095, 2303}, {255, 0, 2559}, {1279, 0, 2559}, {2303, 0, 2559}, + {3327, 0, 2559}, {0, 255, 2559}, {1023, 255, 2559}, {2047, 255, 2559}, {3071, 255, 2559}, + {4095, 255, 2559}, {767, 511, 2559}, {1791, 511, 2559}, {2815, 511, 2559}, + {3839, 511, 2559}, {511, 767, 2559}, {1535, 767, 2559}, {2559, 767, 2559}, + {3583, 767, 2559}, {255, 1023, 2559}, {1279, 1023, 2559}, {2303, 1023, 2559}, + {3327, 1023, 2559}, {0, 1279, 2559}, {1023, 1279, 2559}, {2047, 1279, 2559}, + {3071, 1279, 2559}, {4095, 1279, 2559}, {767, 1535, 2559}, {1791, 1535, 2559}, + {2815, 1535, 2559}, {3839, 1535, 2559}, {511, 1791, 2559}, {1535, 1791, 2559}, + {2559, 1791, 2559}, {3583, 1791, 2559}, {255, 2047, 2559}, {1279, 2047, 2559}, + {2303, 2047, 2559}, {3327, 2047, 2559}, {0, 2303, 2559}, {1023, 2303, 2559}, + {2047, 2303, 2559}, {3071, 2303, 2559}, {4095, 2303, 2559}, {767, 2559, 2559}, + {1791, 2559, 2559}, {2815, 2559, 2559}, {3839, 2559, 2559}, {511, 2815, 2559}, + {1535, 2815, 2559}, {2559, 2815, 2559}, {3583, 2815, 2559}, {255, 3071, 2559}, + {1279, 3071, 2559}, {2303, 3071, 2559}, {3327, 3071, 2559}, {0, 3327, 2559}, + {1023, 3327, 2559}, {2047, 3327, 2559}, {3071, 3327, 2559}, {4095, 3327, 2559}, + {767, 3583, 2559}, {1791, 3583, 2559}, {2815, 3583, 2559}, {3839, 3583, 2559}, + {511, 3839, 2559}, {1535, 3839, 2559}, {2559, 3839, 2559}, {3583, 3839, 2559}, + {255, 4095, 2559}, {1279, 4095, 2559}, {2303, 4095, 2559}, {3327, 4095, 2559}, {0, 0, 2815}, + {1023, 0, 2815}, {2047, 0, 2815}, {3071, 0, 2815}, {4095, 0, 2815}, {767, 255, 2815}, + {1791, 255, 2815}, {2815, 255, 2815}, {3839, 255, 2815}, {511, 511, 2815}, + {1535, 511, 2815}, {2559, 511, 2815}, {3583, 511, 2815}, {255, 767, 2815}, + {1279, 767, 2815}, {2303, 767, 2815}, {3327, 767, 2815}, {0, 1023, 2815}, + {1023, 1023, 2815}, {2047, 1023, 2815}, {3071, 1023, 2815}, {4095, 1023, 2815}, + {767, 1279, 2815}, {1791, 1279, 2815}, {2815, 1279, 2815}, {3839, 1279, 2815}, + {511, 1535, 2815}, {1535, 1535, 2815}, {2559, 1535, 2815}, {3583, 1535, 2815}, + {255, 1791, 2815}, {1279, 1791, 2815}, {2303, 1791, 2815}, {3327, 1791, 2815}, + {0, 2047, 2815}, {1023, 2047, 2815}, {2047, 2047, 2815}, {3071, 2047, 2815}, + {4095, 2047, 2815}, {767, 2303, 2815}, {1791, 2303, 2815}, {2815, 2303, 2815}, + {3839, 2303, 2815}, {511, 2559, 2815}, {1535, 2559, 2815}, {2559, 2559, 2815}, + {3583, 2559, 2815}, {255, 2815, 2815}, {1279, 2815, 2815}, {2303, 2815, 2815}, + {3327, 2815, 2815}, {0, 3071, 2815}, {1023, 3071, 2815}, {2047, 3071, 2815}, + {3071, 3071, 2815}, {4095, 3071, 2815}, {767, 3327, 2815}, {1791, 3327, 2815}, + {2815, 3327, 2815}, {3839, 3327, 2815}, {511, 3583, 2815}, {1535, 3583, 2815}, + {2559, 3583, 2815}, {3583, 3583, 2815}, {255, 3839, 2815}, {1279, 3839, 2815}, + {2303, 3839, 2815}, {3327, 3839, 2815}, {0, 4095, 2815}, {1023, 4095, 2815}, + {2047, 4095, 2815}, {3071, 4095, 2815}, {4095, 4095, 2815}, {767, 0, 3071}, {1791, 0, 3071}, + {2815, 0, 3071}, {3839, 0, 3071}, {511, 255, 3071}, {1535, 255, 3071}, {2559, 255, 3071}, + {3583, 255, 3071}, {255, 511, 3071}, {1279, 511, 3071}, {2303, 511, 3071}, + {3327, 511, 3071}, {0, 767, 3071}, {1023, 767, 3071}, {2047, 767, 3071}, {3071, 767, 3071}, + {4095, 767, 3071}, {767, 1023, 3071}, {1791, 1023, 3071}, {2815, 1023, 3071}, + {3839, 1023, 3071}, {511, 1279, 3071}, {1535, 1279, 3071}, {2559, 1279, 3071}, + {3583, 1279, 3071}, {255, 1535, 3071}, {1279, 1535, 3071}, {2303, 1535, 3071}, + {3327, 1535, 3071}, {0, 1791, 3071}, {1023, 1791, 3071}, {2047, 1791, 3071}, + {3071, 1791, 3071}, {4095, 1791, 3071}, {767, 2047, 3071}, {1791, 2047, 3071}, + {2815, 2047, 3071}, {3839, 2047, 3071}, {511, 2303, 3071}, {1535, 2303, 3071}, + {2559, 2303, 3071}, {3583, 2303, 3071}, {255, 2559, 3071}, {1279, 2559, 3071}, + {2303, 2559, 3071}, {3327, 2559, 3071}, {0, 2815, 3071}, {1023, 2815, 3071}, + {2047, 2815, 3071}, {3071, 2815, 3071}, {4095, 2815, 3071}, {767, 3071, 3071}, + {1791, 3071, 3071}, {2815, 3071, 3071}, {3839, 3071, 3071}, {511, 3327, 3071}, + {1535, 3327, 3071}, {2559, 3327, 3071}, {3583, 3327, 3071}, {255, 3583, 3071}, + {1279, 3583, 3071}, {2303, 3583, 3071}, {3327, 3583, 3071}, {0, 3839, 3071}, + {1023, 3839, 3071}, {2047, 3839, 3071}, {3071, 3839, 3071}, {4095, 3839, 3071}, + {767, 4095, 3071}, {1791, 4095, 3071}, {2815, 4095, 3071}, {3839, 4095, 3071}, + {511, 0, 3327}, {1535, 0, 3327}, {2559, 0, 3327}, {3583, 0, 3327}, {255, 255, 3327}, + {1279, 255, 3327}, {2303, 255, 3327}, {3327, 255, 3327}, {0, 511, 3327}, {1023, 511, 3327}, + {2047, 511, 3327}, {3071, 511, 3327}, {4095, 511, 3327}, {767, 767, 3327}, + {1791, 767, 3327}, {2815, 767, 3327}, {3839, 767, 3327}, {511, 1023, 3327}, + {1535, 1023, 3327}, {2559, 1023, 3327}, {3583, 1023, 3327}, {255, 1279, 3327}, + {1279, 1279, 3327}, {2303, 1279, 3327}, {3327, 1279, 3327}, {0, 1535, 3327}, + {1023, 1535, 3327}, {2047, 1535, 3327}, {3071, 1535, 3327}, {4095, 1535, 3327}, + {767, 1791, 3327}, {1791, 1791, 3327}, {2815, 1791, 3327}, {3839, 1791, 3327}, + {511, 2047, 3327}, {1535, 2047, 3327}, {2559, 2047, 3327}, {3583, 2047, 3327}, + {255, 2303, 3327}, {1279, 2303, 3327}, {2303, 2303, 3327}, {3327, 2303, 3327}, + {0, 2559, 3327}, {1023, 2559, 3327}, {2047, 2559, 3327}, {3071, 2559, 3327}, + {4095, 2559, 3327}, {767, 2815, 3327}, {1791, 2815, 3327}, {2815, 2815, 3327}, + {3839, 2815, 3327}, {511, 3071, 3327}, {1535, 3071, 3327}, {2559, 3071, 3327}, + {3583, 3071, 3327}, {255, 3327, 3327}, {1279, 3327, 3327}, {2303, 3327, 3327}, + {3327, 3327, 3327}, {0, 3583, 3327}, {1023, 3583, 3327}, {2047, 3583, 3327}, + {3071, 3583, 3327}, {4095, 3583, 3327}, {767, 3839, 3327}, {1791, 3839, 3327}, + {2815, 3839, 3327}, {3839, 3839, 3327}, {511, 4095, 3327}, {1535, 4095, 3327}, + {2559, 4095, 3327}, {3583, 4095, 3327}, {255, 0, 3583}, {1279, 0, 3583}, {2303, 0, 3583}, + {3327, 0, 3583}, {0, 255, 3583}, {1023, 255, 3583}, {2047, 255, 3583}, {3071, 255, 3583}, + {4095, 255, 3583}, {767, 511, 3583}, {1791, 511, 3583}, {2815, 511, 3583}, + {3839, 511, 3583}, {511, 767, 3583}, {1535, 767, 3583}, {2559, 767, 3583}, + {3583, 767, 3583}, {255, 1023, 3583}, {1279, 1023, 3583}, {2303, 1023, 3583}, + {3327, 1023, 3583}, {0, 1279, 3583}, {1023, 1279, 3583}, {2047, 1279, 3583}, + {3071, 1279, 3583}, {4095, 1279, 3583}, {767, 1535, 3583}, {1791, 1535, 3583}, + {2815, 1535, 3583}, {3839, 1535, 3583}, {511, 1791, 3583}, {1535, 1791, 3583}, + {2559, 1791, 3583}, {3583, 1791, 3583}, {255, 2047, 3583}, {1279, 2047, 3583}, + {2303, 2047, 3583}, {3327, 2047, 3583}, {0, 2303, 3583}, {1023, 2303, 3583}, + {2047, 2303, 3583}, {3071, 2303, 3583}, {4095, 2303, 3583}, {767, 2559, 3583}, + {1791, 2559, 3583}, {2815, 2559, 3583}, {3839, 2559, 3583}, {511, 2815, 3583}, + {1535, 2815, 3583}, {2559, 2815, 3583}, {3583, 2815, 3583}, {255, 3071, 3583}, + {1279, 3071, 3583}, {2303, 3071, 3583}, {3327, 3071, 3583}, {0, 3327, 3583}, + {1023, 3327, 3583}, {2047, 3327, 3583}, {3071, 3327, 3583}, {4095, 3327, 3583}, + {767, 3583, 3583}, {1791, 3583, 3583}, {2815, 3583, 3583}, {3839, 3583, 3583}, + {511, 3839, 3583}, {1535, 3839, 3583}, {2559, 3839, 3583}, {3583, 3839, 3583}, + {255, 4095, 3583}, {1279, 4095, 3583}, {2303, 4095, 3583}, {3327, 4095, 3583}, {0, 0, 3839}, + {1023, 0, 3839}, {2047, 0, 3839}, {3071, 0, 3839}, {4095, 0, 3839}, {767, 255, 3839}, + {1791, 255, 3839}, {2815, 255, 3839}, {3839, 255, 3839}, {511, 511, 3839}, + {1535, 511, 3839}, {2559, 511, 3839}, {3583, 511, 3839}, {255, 767, 3839}, + {1279, 767, 3839}, {2303, 767, 3839}, {3327, 767, 3839}, {0, 1023, 3839}, + {1023, 1023, 3839}, {2047, 1023, 3839}, {3071, 1023, 3839}, {4095, 1023, 3839}, + {767, 1279, 3839}, {1791, 1279, 3839}, {2815, 1279, 3839}, {3839, 1279, 3839}, + {511, 1535, 3839}, {1535, 1535, 3839}, {2559, 1535, 3839}, {3583, 1535, 3839}, + {255, 1791, 3839}, {1279, 1791, 3839}, {2303, 1791, 3839}, {3327, 1791, 3839}, + {0, 2047, 3839}, {1023, 2047, 3839}, {2047, 2047, 3839}, {3071, 2047, 3839}, + {4095, 2047, 3839}, {767, 2303, 3839}, {1791, 2303, 3839}, {2815, 2303, 3839}, + {3839, 2303, 3839}, {511, 2559, 3839}, {1535, 2559, 3839}, {2559, 2559, 3839}, + {3583, 2559, 3839}, {255, 2815, 3839}, {1279, 2815, 3839}, {2303, 2815, 3839}, + {3327, 2815, 3839}, {0, 3071, 3839}, {1023, 3071, 3839}, {2047, 3071, 3839}, + {3071, 3071, 3839}, {4095, 3071, 3839}, {767, 3327, 3839}, {1791, 3327, 3839}, + {2815, 3327, 3839}, {3839, 3327, 3839}, {511, 3583, 3839}, {1535, 3583, 3839}, + {2559, 3583, 3839}, {3583, 3583, 3839}, {255, 3839, 3839}, {1279, 3839, 3839}, + {2303, 3839, 3839}, {3327, 3839, 3839}, {0, 4095, 3839}, {1023, 4095, 3839}, + {2047, 4095, 3839}, {3071, 4095, 3839}, {4095, 4095, 3839}, {767, 0, 4095}, {1791, 0, 4095}, + {2815, 0, 4095}, {3839, 0, 4095}, {511, 255, 4095}, {1535, 255, 4095}, {2559, 255, 4095}, + {3583, 255, 4095}, {255, 511, 4095}, {1279, 511, 4095}, {2303, 511, 4095}, + {3327, 511, 4095}, {0, 767, 4095}, {1023, 767, 4095}, {2047, 767, 4095}, {3071, 767, 4095}, + {4095, 767, 4095}, {767, 1023, 4095}, {1791, 1023, 4095}, {2815, 1023, 4095}, + {3839, 1023, 4095}, {511, 1279, 4095}, {1535, 1279, 4095}, {2559, 1279, 4095}, + {3583, 1279, 4095}, {255, 1535, 4095}, {1279, 1535, 4095}, {2303, 1535, 4095}, + {3327, 1535, 4095}, {0, 1791, 4095}, {1023, 1791, 4095}, {2047, 1791, 4095}, + {3071, 1791, 4095}, {4095, 1791, 4095}, {767, 2047, 4095}, {1791, 2047, 4095}, + {2815, 2047, 4095}, {3839, 2047, 4095}, {511, 2303, 4095}, {1535, 2303, 4095}, + {2559, 2303, 4095}, {3583, 2303, 4095}, {255, 2559, 4095}, {1279, 2559, 4095}, + {2303, 2559, 4095}, {3327, 2559, 4095}, {0, 2815, 4095}, {1023, 2815, 4095}, + {2047, 2815, 4095}, {3071, 2815, 4095}, {4095, 2815, 4095}, {767, 3071, 4095}, + {1791, 3071, 4095}, {2815, 3071, 4095}, {3839, 3071, 4095}, {511, 3327, 4095}, + {1535, 3327, 4095}, {2559, 3327, 4095}, {3583, 3327, 4095}, {255, 3583, 4095}, + {1279, 3583, 4095}, {2303, 3583, 4095}, {3327, 3583, 4095}, {0, 3839, 4095}, + {1023, 3839, 4095}, {2047, 3839, 4095}, {3071, 3839, 4095}, {4095, 3839, 4095}, + {767, 4095, 4095}, {1791, 4095, 4095}, {2815, 4095, 4095}, {3839, 4095, 4095}}}; + +static const struct tetrahedral_17x17x17 tetra_sce_3dlut = { + // lut 0 + {{0, 0, 0}, {1135, 0, 37}, {2163, 0, 70}, {3422, 0, 0}, {4095, 0, 0}, {900, 244, 0}, + {1848, 0, 0}, {3108, 0, 0}, {4095, 0, 0}, {552, 543, 0}, {1571, 331, 0}, {2804, 0, 0}, + {4065, 0, 0}, {0, 748, 0}, {1309, 684, 0}, {2515, 581, 0}, {3765, 0, 0}, {0, 1005, 0}, + {1018, 996, 0}, {2238, 951, 0}, {3472, 822, 0}, {4095, 461, 0}, {562, 1319, 0}, + {1954, 1279, 0}, {3185, 1206, 0}, {4095, 1044, 0}, {0, 1670, 0}, {1636, 1603, 0}, + {2894, 1547, 0}, {4095, 1441, 0}, {0, 2018, 0}, {1242, 1958, 0}, {2585, 1876, 0}, + {3819, 1792, 0}, {0, 2357, 0}, {443, 2319, 0}, {2245, 2200, 0}, {3512, 2127, 0}, + {4095, 2013, 0}, {0, 2670, 0}, {1867, 2561, 0}, {3184, 2452, 0}, {4095, 2352, 0}, + {0, 3006, 0}, {1302, 2920, 0}, {2828, 2771, 0}, {4084, 2678, 0}, {0, 3322, 0}, {0, 3263, 0}, + {2452, 3124, 0}, {3742, 2995, 0}, {0, 3622, 0}, {0, 3587, 0}, {1944, 3468, 0}, + {3374, 3303, 0}, {4095, 3188, 0}, {0, 3890, 0}, {1175, 3794, 0}, {2992, 3636, 0}, + {4095, 3491, 0}, {0, 4095, 0}, {0, 4095, 0}, {2508, 3955, 0}, {3866, 3783, 0}, {0, 4095, 0}, + {0, 4095, 0}, {1870, 4095, 0}, {3472, 4084, 0}, {0, 4095, 0}, {0, 4095, 0}, {761, 4095, 0}, + {2994, 4095, 0}, {4095, 4095, 0}, {949, 0, 321}, {1851, 0, 60}, {3115, 0, 101}, + {4095, 0, 0}, {682, 342, 351}, {1562, 0, 51}, {2799, 0, 91}, {4052, 0, 0}, {113, 558, 167}, + {1293, 392, 0}, {2485, 0, 0}, {3748, 0, 0}, {153, 753, 58}, {1018, 700, 0}, {2202, 626, 0}, + {3450, 350, 0}, {4095, 0, 0}, {670, 999, 0}, {1931, 969, 0}, {3160, 871, 0}, {4095, 605, 0}, + {0, 1330, 0}, {1642, 1291, 0}, {2875, 1233, 0}, {4095, 1100, 0}, {0, 1675, 0}, + {1304, 1625, 0}, {2583, 1566, 0}, {3811, 1476, 0}, {0, 2018, 0}, {755, 1984, 0}, + {2267, 1892, 0}, {3514, 1819, 0}, {4095, 1696, 0}, {0, 2341, 0}, {1922, 2233, 0}, + {3202, 2149, 0}, {4095, 2047, 0}, {0, 2687, 0}, {1455, 2597, 0}, {2865, 2472, 0}, + {4095, 2381, 0}, {0, 3010, 0}, {564, 2952, 0}, {2512, 2810, 0}, {3779, 2705, 0}, + {0, 3322, 0}, {0, 3289, 0}, {2072, 3165, 0}, {3427, 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0, 4095}, + {591, 0, 4095}, {1611, 0, 4095}, {2639, 0, 4095}, {3632, 0, 4095}, {350, 0, 4095}, + {1347, 0, 4095}, {2386, 0, 4095}, {3389, 274, 4095}, {116, 0, 4095}, {1076, 195, 4095}, + {2130, 474, 4095}, {3144, 622, 4095}, {4095, 722, 4095}, {792, 767, 4095}, + {1870, 840, 4095}, {2899, 914, 4095}, {3882, 973, 4095}, {463, 1129, 4095}, + {1602, 1158, 4095}, {2651, 1196, 4095}, {3645, 1230, 4095}, {207, 1459, 4095}, + {1320, 1463, 4095}, {2398, 1478, 4095}, {3406, 1492, 4095}, {280, 1765, 4095}, + {1011, 1763, 4095}, {2136, 1763, 4095}, {3166, 1760, 4095}, {4095, 1765, 4095}, + {661, 2058, 4095}, {1859, 2051, 4095}, {2921, 2034, 4095}, {3903, 2023, 4095}, + {404, 2341, 4095}, {1559, 2343, 4095}, {2667, 2315, 4095}, {3670, 2287, 4095}, + {462, 2614, 4095}, {1248, 2618, 4095}, {2397, 2603, 4095}, {3433, 2560, 4095}, + {518, 2877, 4095}, {934, 2881, 4095}, {2102, 2890, 4095}, {3188, 2841, 4095}, + {4095, 2796, 4095}, {620, 3133, 4095}, {1807, 3143, 4095}, {2926, 3132, 4095}, + {3954, 3085, 4095}, {628, 3377, 4095}, {1535, 3384, 4095}, {2632, 3400, 4095}, + {3756, 3401, 4095}, {683, 3611, 4095}, {1308, 3620, 4095}, {2380, 3663, 4095}, + {3519, 3725, 4095}, {744, 3866, 4095}, {1163, 3877, 4095}, {2166, 3919, 4095}, + {3245, 3976, 4095}, {4095, 3921, 4095}, {1099, 4068, 4095}, {1978, 4067, 4095}, + {2994, 4066, 4095}, {3958, 4065, 4095}}}; + +bool build_test_3dlut(enum test3d_type type, struct vpe_3dlut *lut3d) +{ + if (!lut3d) + return false; + + if (type == lut3d_identity) { + memcpy(&(lut3d->lut_3d), &tetra_ident_3dlut, sizeof(struct tetrahedral_17x17x17)); + } else if (type == lut3d_sce) { + memcpy(&(lut3d->lut_3d), &tetra_sce_3dlut, sizeof(struct tetrahedral_17x17x17)); + } else + return false; + + lut3d->lut_3d.use_12bits = 1; + lut3d->hdr_multiplier = hdr_mult_sdr; + + lut3d->state.bits.initialized = 1; + + return true; +} diff --git a/src/amd/vpelib/src/core/common.c b/src/amd/vpelib/src/core/common.c new file mode 100644 index 00000000000..60ef31f589b --- /dev/null +++ b/src/amd/vpelib/src/core/common.c @@ -0,0 +1,591 @@ +/* Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include +#include "vpe_types.h" +#include "vpe_priv.h" +#include "common.h" + +bool vpe_find_color_space_from_table( + const struct vpe_color_space *table, int table_size, const struct vpe_color_space *cs) +{ + int i; + for (i = 0; i < table_size; i++) { + if (!memcmp(table, cs, sizeof(struct vpe_color_space))) + return true; + } + return false; +} + +bool vpe_is_dual_plane_format(enum vpe_surface_pixel_format format) +{ + switch (format) { + // nv12/21 + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: + // p010 + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: + return true; + default: + return false; + } +} + +bool vpe_is_32bit_packed_rgb(enum vpe_surface_pixel_format format) +{ + switch (format) { + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBA8888: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA8888: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBX8888: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRX8888: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_XRGB8888: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_XBGR8888: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBA1010102: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA1010102: + return true; + default: + return false; + } +} + +bool vpe_is_rgb8(enum vpe_surface_pixel_format format) +{ + switch (format) { + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBA8888: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA8888: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBX8888: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRX8888: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_XRGB8888: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_XBGR8888: + return true; + default: + return false; + } +} + +bool vpe_is_rgb10(enum vpe_surface_pixel_format format) +{ + switch (format) { + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBA1010102: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA1010102: + return true; + default: + return false; + } +} + +bool vpe_is_fp16(enum vpe_surface_pixel_format format) +{ + switch (format) { + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBA16161616F: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA16161616F: + return true; + default: + return false; + } +} + +bool vpe_is_yuv420_8(enum vpe_surface_pixel_format format) +{ + switch (format) { + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: + return true; + default: + return false; + } +} + +bool vpe_is_yuv420_10(enum vpe_surface_pixel_format format) +{ + switch (format) { + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: + return true; + default: + return false; + } +} + +bool vpe_is_yuv420(enum vpe_surface_pixel_format format) +{ + return (vpe_is_yuv420_8(format) || vpe_is_yuv420_10(format)); +} + +bool vpe_is_yuv444_8(enum vpe_surface_pixel_format format) +{ + switch (format) { + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_AYCbCr8888: + return true; + default: + return false; + } +} + +bool vpe_is_yuv444_10(enum vpe_surface_pixel_format format) +{ + switch (format) { + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_CrYCbA1010102: + return true; + default: + return false; + } +} + +static uint8_t vpe_get_element_size_in_bytes(enum vpe_surface_pixel_format format, int plane_idx) +{ + switch (format) { + // nv12/21 + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: + if (plane_idx == 0) + return 1; + else + return 2; + // P010 + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: + if (plane_idx == 0) + return 2; + else + return 4; + // 64bpp + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBA16161616F: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA16161616F: + return 8; + default: + break; + } + // default 32bpp packed format + return 4; +} + +enum color_depth vpe_get_color_depth(enum vpe_surface_pixel_format format) +{ + enum color_depth c_depth; + switch (format) { + case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGB565: + c_depth = COLOR_DEPTH_666; + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBA8888: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA8888: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBX8888: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRX8888: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_XRGB8888: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_XBGR8888: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_AYCbCr8888: + c_depth = COLOR_DEPTH_888; + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBA1010102: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA1010102: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_CrYCbA1010102: + c_depth = COLOR_DEPTH_101010; + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBA16161616F: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA16161616F: + c_depth = COLOR_DEPTH_161616; + break; + default: + c_depth = COLOR_DEPTH_888; + } + + return c_depth; +} + +bool vpe_has_per_pixel_alpha(enum vpe_surface_pixel_format format) +{ + bool alpha = true; + + switch (format) { + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBA8888: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA8888: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBA1010102: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA1010102: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBA16161616F: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA16161616F: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_CrYCbA1010102: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_AYCbCr8888: + alpha = true; + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGB565: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBE: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBX8888: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRX8888: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_XRGB8888: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_XBGR8888: + default: + alpha = false; + break; + } + + return alpha; +} + +// Note there is another function vpe_is_hdr that performs the same function but with the translated +// internal VPE enums, not the api enums as done below. C does not support function overloading so +// another function is needed here. +static bool is_HDR(enum vpe_transfer_function tf) +{ + return (tf == VPE_TF_PQ || tf == VPE_TF_G10); +} + +enum vpe_status vpe_check_output_support(struct vpe *vpe, const struct vpe_build_param *param) +{ + struct vpe_priv *vpe_priv = container_of(vpe, struct vpe_priv, pub); + struct vpec *vpec; + struct dpp *dpp; + struct cdc *cdc; + const struct vpe_surface_info *surface_info = ¶m->dst_surface; + struct vpe_dcc_surface_param input; + struct vpe_surface_dcc_cap output; + bool support; + + vpec = &vpe_priv->resource.vpec; + dpp = vpe_priv->resource.dpp[0]; + cdc = vpe_priv->resource.cdc[0]; + + // swizzle mode + support = vpec->funcs->check_swmode_support(vpec, surface_info->swizzle); + if (!support) { + vpe_log("output swizzle mode not supported %d\n", surface_info->swizzle); + return VPE_STATUS_SWIZZLE_NOT_SUPPORTED; + } + + // pitch + if ((surface_info->plane_size.surface_pitch * + vpe_get_element_size_in_bytes(surface_info->format, 0) % + vpe->caps->plane_caps.pitch_alignment) || + ((uint32_t)(surface_info->plane_size.surface_size.x + + (int32_t)surface_info->plane_size.surface_size.width) > + surface_info->plane_size.surface_pitch)) { + vpe_log("pitch alignment not supported %lu. %lu\n", surface_info->plane_size.surface_pitch, + vpe->caps->plane_caps.pitch_alignment); + return VPE_STATUS_PITCH_ALIGNMENT_NOT_SUPPORTED; + } + + // target rect shouldn't exceed width/height + if ((param->target_rect.x < surface_info->plane_size.surface_size.x || + param->target_rect.x + (int32_t)param->target_rect.width > + surface_info->plane_size.surface_size.x + + (int32_t)surface_info->plane_size.surface_size.width)) { + vpe_log("target rect exceed surface boundary, target x= %d, width = %u, surface x = %d, " + "width = %u\n", + param->target_rect.x, param->target_rect.width, surface_info->plane_size.surface_size.x, + surface_info->plane_size.surface_size.width); + return VPE_STATUS_PARAM_CHECK_ERROR; + } + + if ((param->target_rect.y < surface_info->plane_size.surface_size.y || + param->target_rect.y + (int32_t)param->target_rect.height > + surface_info->plane_size.surface_size.y + + (int32_t)surface_info->plane_size.surface_size.height)) { + vpe_log( + "target rect exceed surface boundary, y= %d, height = %u, surface x = %d, width = %u\n", + param->target_rect.y, param->target_rect.height, + surface_info->plane_size.surface_size.y, surface_info->plane_size.surface_size.height); + return VPE_STATUS_PARAM_CHECK_ERROR; + } + + if (surface_info->address.type == VPE_PLN_ADDR_TYPE_VIDEO_PROGRESSIVE) { + if (((uint32_t)surface_info->plane_size.chroma_pitch * + vpe_get_element_size_in_bytes(surface_info->format, 1) % + vpe->caps->plane_caps.pitch_alignment) || + ((uint32_t)(surface_info->plane_size.chroma_size.x + + (int32_t)surface_info->plane_size.chroma_size.width) > + surface_info->plane_size.chroma_pitch)) { + vpe_log("chroma pitch alignment not supported %u. %u\n", + surface_info->plane_size.chroma_pitch, vpe->caps->plane_caps.pitch_alignment); + return VPE_STATUS_PITCH_ALIGNMENT_NOT_SUPPORTED; + } + } + + // dcc + if (surface_info->dcc.enable) { + input.surface_size.width = surface_info->plane_size.surface_size.width; + input.surface_size.height = surface_info->plane_size.surface_size.height; + input.format = surface_info->format; + input.swizzle_mode = surface_info->swizzle; + input.scan = VPE_SCAN_DIRECTION_HORIZONTAL; + + support = vpec->funcs->get_dcc_compression_cap(vpec, &input, &output); + if (!support) { + vpe_log("output dcc not supported\n"); + return VPE_STATUS_DCC_NOT_SUPPORTED; + } + } + + // pixel format + support = cdc->funcs->check_output_format(cdc, surface_info->format); + if (!support) { + vpe_log("output pixel format not supported %d\n", (int)surface_info->format); + return VPE_STATUS_PIXEL_FORMAT_NOT_SUPPORTED; + } + + // color space value + support = vpe_priv->resource.check_output_color_space( + vpe_priv, surface_info->format, &surface_info->cs); + if (!support) { + vpe_log("output color space not supported fmt: %d, " + "encoding: %d, cositing: %d, gamma: %d, range: %d, primaries: %d\n", + (int)surface_info->format, (int)surface_info->cs.encoding, + (int)surface_info->cs.cositing, (int)surface_info->cs.tf, (int)surface_info->cs.range, + (int)surface_info->cs.primaries); + return VPE_STATUS_COLOR_SPACE_VALUE_NOT_SUPPORTED; + } + + return VPE_STATUS_OK; +} + +enum vpe_status vpe_check_input_support(struct vpe *vpe, const struct vpe_stream *stream) +{ + struct vpe_priv *vpe_priv = container_of(vpe, struct vpe_priv, pub); + struct vpec *vpec; + struct dpp *dpp; + struct cdc *cdc; + const struct vpe_surface_info *surface_info = &stream->surface_info; + struct vpe_dcc_surface_param input; + struct vpe_surface_dcc_cap output; + bool support; + const PHYSICAL_ADDRESS_LOC *addrloc; + bool use_adj = vpe_use_csc_adjust(&stream->color_adj); + + vpec = &vpe_priv->resource.vpec; + dpp = vpe_priv->resource.dpp[0]; + cdc = vpe_priv->resource.cdc[0]; + + // swizzle mode + support = vpec->funcs->check_swmode_support(vpec, surface_info->swizzle); + if (!support) { + vpe_log("input swizzle mode not supported %d\n", surface_info->swizzle); + return VPE_STATUS_SWIZZLE_NOT_SUPPORTED; + } + + // pitch & address + if ((surface_info->plane_size.surface_pitch * + vpe_get_element_size_in_bytes(surface_info->format, 0) % + vpe->caps->plane_caps.pitch_alignment) || + ((uint32_t)(surface_info->plane_size.surface_size.x + + (int32_t)surface_info->plane_size.surface_size.width) > + surface_info->plane_size.surface_pitch)) { + + vpe_log("pitch alignment not supported %d. %d\n", surface_info->plane_size.surface_pitch, + vpe->caps->plane_caps.pitch_alignment); + return VPE_STATUS_PITCH_ALIGNMENT_NOT_SUPPORTED; + } + + if (surface_info->address.type == VPE_PLN_ADDR_TYPE_VIDEO_PROGRESSIVE) { + + addrloc = &surface_info->address.video_progressive.luma_addr; + if (addrloc->u.low_part % vpe->caps->plane_caps.addr_alignment) { + vpe_log("failed. addr not aligned to 256 bytes\n"); + return VPE_STATUS_PLANE_ADDR_NOT_SUPPORTED; + } + + if (vpe_is_dual_plane_format(surface_info->format)) { + if ((surface_info->plane_size.chroma_pitch * + vpe_get_element_size_in_bytes(surface_info->format, 1) % + vpe->caps->plane_caps.pitch_alignment) || + ((uint32_t)(surface_info->plane_size.chroma_size.x + + (int32_t)surface_info->plane_size.chroma_size.width) > + surface_info->plane_size.chroma_pitch)) { + vpe_log("chroma pitch alignment not supported %d. %d\n", + surface_info->plane_size.chroma_pitch, vpe->caps->plane_caps.pitch_alignment); + return VPE_STATUS_PITCH_ALIGNMENT_NOT_SUPPORTED; + } + + addrloc = &surface_info->address.video_progressive.chroma_addr; + if (addrloc->u.low_part % vpe->caps->plane_caps.addr_alignment) { + vpe_log("failed. addr not aligned to 256 bytes\n"); + return VPE_STATUS_PLANE_ADDR_NOT_SUPPORTED; + } + } + } else { + addrloc = &surface_info->address.grph.addr; + if (addrloc->u.low_part % vpe->caps->plane_caps.addr_alignment) { + vpe_log("failed. addr not aligned to 256 bytes\n"); + return VPE_STATUS_PLANE_ADDR_NOT_SUPPORTED; + } + } + + // dcc + if (surface_info->dcc.enable) { + + input.surface_size.width = surface_info->plane_size.surface_size.width; + input.surface_size.height = surface_info->plane_size.surface_size.height; + input.format = surface_info->format; + input.swizzle_mode = surface_info->swizzle; + + if (stream->rotation == VPE_ROTATION_ANGLE_0 || stream->rotation == VPE_ROTATION_ANGLE_180) + input.scan = VPE_SCAN_DIRECTION_HORIZONTAL; + else if (stream->rotation == VPE_ROTATION_ANGLE_90 || + stream->rotation == VPE_ROTATION_ANGLE_270) + input.scan = VPE_SCAN_DIRECTION_VERTICAL; + else + input.scan = VPE_SCAN_DIRECTION_UNKNOWN; + + support = vpec->funcs->get_dcc_compression_cap(vpec, &input, &output); + if (!support) { + vpe_log("input dcc not supported\n"); + return VPE_STATUS_DCC_NOT_SUPPORTED; + } + } + + // pixel format + support = cdc->funcs->check_input_format(cdc, surface_info->format); + if (!support) { + vpe_log("input pixel format not supported %d\n", (int)surface_info->format); + return VPE_STATUS_PIXEL_FORMAT_NOT_SUPPORTED; + } + + // color space value + support = vpe_priv->resource.check_input_color_space( + vpe_priv, surface_info->format, &surface_info->cs); + if (!support) { + vpe_log("input color space not supported fmt: %d, " + "encoding: %d, cositing: %d, gamma: %d, range: %d, primaries: %d\n", + (int)surface_info->format, (int)surface_info->cs.encoding, + (int)surface_info->cs.cositing, (int)surface_info->cs.tf, (int)surface_info->cs.range, + (int)surface_info->cs.primaries); + return VPE_STATUS_COLOR_SPACE_VALUE_NOT_SUPPORTED; + } + + // TODO: Add support + // adjustments + if (surface_info->cs.primaries == VPE_PRIMARIES_BT2020 && + surface_info->cs.encoding == VPE_PIXEL_ENCODING_RGB && use_adj) { + // for BT2020 + RGB input with adjustments, it is expected not working. + vpe_log("for BT2020 + RGB input with adjustments, it is expected not working\n"); + return VPE_STATUS_ADJUSTMENT_NOT_SUPPORTED; + } + + // rotation + if ((stream->rotation != VPE_ROTATION_ANGLE_0) && !vpe->caps->rotation_support) { + vpe_log("output rotation not supported\n"); + return VPE_STATUS_ROTATION_NOT_SUPPORTED; + } + + // luma keying + if (stream->enable_luma_key && !vpe->caps->color_caps.dpp.luma_key) { + vpe_log("luma keying not supported\n"); + return VPE_STATUS_LUMA_KEYING_NOT_SUPPORTED; + } + + if (stream->horizontal_mirror && !vpe->caps->h_mirror_support) { + vpe_log("output horizontal mirroring not supported h:%d\n", (int)stream->horizontal_mirror); + return VPE_STATUS_MIRROR_NOT_SUPPORTED; + } + + if (stream->vertical_mirror && !vpe->caps->v_mirror_support) { + vpe_log("output vertical mirroring not supported v:%d\n", (int)stream->vertical_mirror); + return VPE_STATUS_MIRROR_NOT_SUPPORTED; + } + + return VPE_STATUS_OK; +} + +enum vpe_status vpe_cache_tone_map_params( + struct stream_ctx *stream_ctx, const struct vpe_build_param *param) +{ + + stream_ctx->update_3dlut = stream_ctx->update_3dlut || param->streams->tm_params.update_3dlut; + + return VPE_STATUS_OK; +} + +enum vpe_status vpe_check_tone_map_support( + struct vpe *vpe, const struct vpe_stream *stream, const struct vpe_build_param *param) +{ + enum vpe_status status = VPE_STATUS_OK; + + // If tone map enabled but bad luminance reject. + if (stream->tm_params.enable_3dlut && + stream->hdr_metadata.max_mastering <= param->hdr_metadata.max_mastering) { + status = VPE_STATUS_BAD_TONE_MAP_PARAMS; + goto exit; + } + + // If tone map enabled but input is not HDR, reject. + if (stream->tm_params.enable_3dlut && !is_HDR(stream->surface_info.cs.tf)) { + status = VPE_STATUS_BAD_TONE_MAP_PARAMS; + goto exit; + } + + // If tone map case but enable tm flag is not set or 3dlut pointer is null reject. + if (stream->hdr_metadata.max_mastering > param->hdr_metadata.max_mastering && + is_HDR(stream->surface_info.cs.tf) && + (!stream->tm_params.enable_3dlut || stream->tm_params.lut_data == NULL)) { + status = VPE_STATUS_BAD_HDR_METADATA; + } + +exit: + return status; +} diff --git a/src/amd/vpelib/src/core/config_writer.c b/src/amd/vpelib/src/core/config_writer.c new file mode 100644 index 00000000000..aa56a1810bd --- /dev/null +++ b/src/amd/vpelib/src/core/config_writer.c @@ -0,0 +1,256 @@ +/* Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include "vpe_assert.h" +#include "vpe_command.h" +#include "config_writer.h" +#include "reg_helper.h" +#include "common.h" + +// in bytes +#define MAX_DIRECT_CONFIG_SIZE (4 * 0x10000) +#define MAX_INDIRECT_CONFIG_SIZE ((4 + 16 * 3) * sizeof(uint32_t)) + +void config_writer_init(struct config_writer *writer, struct vpe_buf *buf) +{ + writer->base_cpu_va = buf->cpu_va; + writer->base_gpu_va = buf->gpu_va; + writer->buf = buf; + writer->type = CONFIG_TYPE_UNKNOWN; + writer->callback_ctx = NULL; + writer->callback = NULL; + writer->completed = false; + writer->status = VPE_STATUS_OK; +} + +void config_writer_set_callback( + struct config_writer *writer, void *callback_ctx, config_callback_t callback) +{ + writer->callback_ctx = callback_ctx; + writer->callback = callback; +} + +static inline void config_writer_new(struct config_writer *writer) +{ + if (writer->status != VPE_STATUS_OK) + return; + + /* Buffer does not have enough space to write */ + if (writer->buf->size < (int64_t)sizeof(uint32_t)) { + writer->status = VPE_STATUS_BUFFER_OVERFLOW; + return; + } + // new base + writer->base_cpu_va = writer->buf->cpu_va; + writer->base_gpu_va = writer->buf->gpu_va; + + // new header. don't need to fill it yet until completion + writer->buf->cpu_va += sizeof(uint32_t); + writer->buf->gpu_va += sizeof(uint32_t); + writer->buf->size -= sizeof(uint32_t); + writer->completed = false; +} + +void config_writer_set_type(struct config_writer *writer, enum config_type type) +{ + VPE_ASSERT(type != CONFIG_TYPE_UNKNOWN); + + if (writer->status != VPE_STATUS_OK) + return; + + if (writer->type != type) { + if (writer->type == CONFIG_TYPE_UNKNOWN) { + // new header. don't need to fill it yet until completion + config_writer_new(writer); + } else { + // a new config type, close the previous one + config_writer_complete(writer); + + config_writer_new(writer); + } + writer->type = type; + } +} + +void config_writer_fill(struct config_writer *writer, uint32_t value) +{ + uint32_t *cmd_space; + uint64_t size = writer->buf->cpu_va - writer->base_cpu_va; + + VPE_ASSERT(writer->type != CONFIG_TYPE_UNKNOWN); + + if (writer->status != VPE_STATUS_OK) + return; + + // check overflow, open a new one if it is + if (writer->type == CONFIG_TYPE_DIRECT) { + if (size >= MAX_DIRECT_CONFIG_SIZE) { + config_writer_complete(writer); + config_writer_new(writer); + } else if (writer->completed) { + config_writer_new(writer); + } + } else { + if (size >= MAX_INDIRECT_CONFIG_SIZE) { + config_writer_complete(writer); + config_writer_new(writer); + } else if (writer->completed) { + config_writer_new(writer); + } + } + + /* Buffer does not have enough space to write */ + if (writer->buf->size < (int64_t)sizeof(uint32_t)) { + writer->status = VPE_STATUS_BUFFER_OVERFLOW; + return; + } + + cmd_space = (uint32_t *)(uintptr_t)writer->buf->cpu_va; + *cmd_space++ = value; + writer->buf->cpu_va += sizeof(uint32_t); + writer->buf->gpu_va += sizeof(uint32_t); + writer->buf->size -= sizeof(uint32_t); +} + +void config_writer_fill_direct_config_packet_header( + struct config_writer *writer, struct vpep_direct_config_packet *packet) +{ + uint32_t *cmd_space; + uint64_t size = writer->buf->cpu_va - writer->base_cpu_va; + + VPE_ASSERT(writer->type == CONFIG_TYPE_DIRECT); + + if (writer->status != VPE_STATUS_OK) + return; + + // first + 1 for header, DATA_SIZE + 1 for real data size + // for estimate overflow, this function only write packet header + if (size + (1 + packet->bits.VPEP_CONFIG_DATA_SIZE + 1) * sizeof(uint32_t) >= + MAX_DIRECT_CONFIG_SIZE) { + config_writer_complete(writer); + config_writer_new(writer); + } else if (writer->completed) { + config_writer_new(writer); + } + + /* Buffer does not have enough space to write */ + if (writer->buf->size < (int64_t)sizeof(uint32_t)) { + writer->status = VPE_STATUS_BUFFER_OVERFLOW; + return; + } + + cmd_space = (uint32_t *)(uintptr_t)writer->buf->cpu_va; + *cmd_space++ = packet->u32all; + writer->buf->cpu_va += sizeof(uint32_t); + writer->buf->gpu_va += sizeof(uint32_t); + writer->buf->size -= sizeof(uint32_t); +} + +void config_writer_fill_direct_config_packet( + struct config_writer *writer, struct vpep_direct_config_packet *packet) +{ + uint32_t *cmd_space; + uint64_t size = writer->buf->cpu_va - writer->base_cpu_va; + + VPE_ASSERT(writer->type == CONFIG_TYPE_DIRECT); + VPE_ASSERT(packet->bits.VPEP_CONFIG_DATA_SIZE == 0); + if (writer->status != VPE_STATUS_OK) + return; + + // first + 1 for header, DATA_SIZE + 1 for real data size + // this function writes both header and the data + if (size + 1 + (packet->bits.VPEP_CONFIG_DATA_SIZE + 1) * sizeof(uint32_t) >= + MAX_DIRECT_CONFIG_SIZE) { + config_writer_complete(writer); + config_writer_new(writer); + } else if (writer->completed) { + config_writer_new(writer); + } + + if (writer->buf->size < (int64_t)(2 * sizeof(uint32_t))) { + writer->status = VPE_STATUS_BUFFER_OVERFLOW; + return; + } + + cmd_space = (uint32_t *)(uintptr_t)writer->buf->cpu_va; + *cmd_space++ = packet->u32all; // Write header + writer->buf->cpu_va += sizeof(uint32_t); + writer->buf->gpu_va += sizeof(uint32_t); + writer->buf->size -= sizeof(uint32_t); + *cmd_space++ = packet->data[0]; // Write data + writer->buf->cpu_va += sizeof(uint32_t); + writer->buf->gpu_va += sizeof(uint32_t); + writer->buf->size -= sizeof(uint32_t); +} + +void config_writer_fill_indirect_data_array( + struct config_writer *writer, const uint64_t data_gpuva, uint32_t size) +{ + VPE_ASSERT(writer->type == CONFIG_TYPE_INDIRECT); + VPE_ASSERT(size > 0); + + // the DATA_ARRAY_SIZE is 1-based, hence -1 from actual size + config_writer_fill(writer, VPEC_FIELD_VALUE(VPE_IND_CFG_DATA_ARRAY_SIZE, size - 1)); + config_writer_fill(writer, ADDR_LO(data_gpuva)); + config_writer_fill(writer, ADDR_HI(data_gpuva)); +} + +void config_writer_fill_indirect_destination(struct config_writer *writer, + const uint32_t offset_index, const uint32_t start_index, const uint32_t offset_data) +{ + VPE_ASSERT(writer->type == CONFIG_TYPE_INDIRECT); + config_writer_fill(writer, VPEC_FIELD_VALUE(VPE_IND_CFG_PKT_REGISTER_OFFSET, offset_index)); + config_writer_fill(writer, start_index); + config_writer_fill(writer, VPEC_FIELD_VALUE(VPE_IND_CFG_PKT_REGISTER_OFFSET, offset_data)); +} + +void config_writer_complete(struct config_writer *writer) +{ + uint32_t *cmd_space = (uint32_t *)(uintptr_t)writer->base_cpu_va; + uint32_t size = (uint32_t)(writer->buf->cpu_va - writer->base_cpu_va); + + if (writer->status != VPE_STATUS_OK) + return; + + VPE_ASSERT(writer->type != CONFIG_TYPE_UNKNOWN); + VPE_ASSERT(writer->buf->cpu_va != writer->base_cpu_va); + + if (writer->type == CONFIG_TYPE_DIRECT) { + // -4 for exclude header + // VPEP_DIRECT_CONFIG_ARRAY_SIZE is 1-based, hence need -1 + *cmd_space = VPE_DIR_CFG_CMD_HEADER(((size - 4) / sizeof(uint32_t) - 1)); + } else { + // -4 DW for header, data array size, data array lo and data array hi + // /3 DW for each destination reg + // NUM_DST is 1-based, hence need -1 + uint32_t num_dst = (uint32_t)((size - (4 * sizeof(uint32_t))) / (3 * sizeof(uint32_t)) - 1); + *cmd_space = VPE_IND_CFG_CMD_HEADER(num_dst); + } + + writer->completed = true; + + if (writer->callback) { + writer->callback(writer->callback_ctx, writer->base_gpu_va, writer->base_cpu_va, size); + } +} diff --git a/src/amd/vpelib/src/core/inc/3dlut_builder.h b/src/amd/vpelib/src/core/inc/3dlut_builder.h new file mode 100644 index 00000000000..07cb626ffe7 --- /dev/null +++ b/src/amd/vpelib/src/core/inc/3dlut_builder.h @@ -0,0 +1,34 @@ +/* Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#pragma once +#include "hw_shared.h" +#include "vpe_priv.h" +#include "common.h" + +#define LUT3D_SIZE_17x17x17 4913 +#define LUT3D_SIZE_9x9x9 729 + +bool convert_to_tetrahedral(struct vpe_priv *vpe_priv, uint16_t rgb[17 * 17 * 17 * 3], + struct vpe_3dlut *params, bool enable_3dlut); diff --git a/src/amd/vpelib/src/core/inc/background.h b/src/amd/vpelib/src/core/inc/background.h new file mode 100644 index 00000000000..cf314b31798 --- /dev/null +++ b/src/amd/vpelib/src/core/inc/background.h @@ -0,0 +1,42 @@ +/* Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include "resource.h" +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +void vpe_create_bg_segments( + struct vpe_priv *vpe_priv, struct vpe_rect *gaps, uint16_t gaps_cnt, enum vpe_cmd_ops ops); + +uint16_t vpe_find_bg_gaps(struct vpe_priv *vpe_priv, const struct vpe_rect *target_rect, + struct vpe_rect *gaps, uint16_t max_gaps); + +void vpe_full_bg_gaps(struct vpe_rect *gaps, const struct vpe_rect *target_rect, uint16_t max_gaps); + +#ifdef __cplusplus +} +#endif diff --git a/src/amd/vpelib/src/core/inc/cdc.h b/src/amd/vpelib/src/core/inc/cdc.h new file mode 100644 index 00000000000..e5cd19fbc74 --- /dev/null +++ b/src/amd/vpelib/src/core/inc/cdc.h @@ -0,0 +1,67 @@ +/* Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#pragma once + +#include "vpe_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct cdc; +struct vpe_priv; + +/** note: all program_* functions shall return number of config packet created */ + +struct cdc_funcs { + bool (*check_input_format)(struct cdc *cdc, enum vpe_surface_pixel_format format); + + bool (*check_output_format)(struct cdc *cdc, enum vpe_surface_pixel_format format); + + /** non segment specific */ + void (*program_surface_config)(struct cdc *cdc, enum vpe_surface_pixel_format format, + enum vpe_rotation_angle rotation, bool horizontal_mirror, + enum vpe_swizzle_mode_values swizzle); + + void (*program_crossbar_config)(struct cdc *cdc, enum vpe_surface_pixel_format format); + + void (*program_global_sync)( + struct cdc *cdc, uint32_t vupdate_offset, uint32_t vupdate_width, uint32_t vready_offset); + + void (*program_p2b_config)(struct cdc *cdc, enum vpe_surface_pixel_format format); + + /** segment specific */ + void (*program_viewport)( + struct cdc *cdc, const struct vpe_rect *viewport, const struct vpe_rect *viewport_c); +}; + +struct cdc { + struct vpe_priv *vpe_priv; + struct cdc_funcs *funcs; +}; + +#ifdef __cplusplus +} +#endif diff --git a/src/amd/vpelib/src/core/inc/cmd_builder.h b/src/amd/vpelib/src/core/inc/cmd_builder.h new file mode 100644 index 00000000000..3d78b489b14 --- /dev/null +++ b/src/amd/vpelib/src/core/inc/cmd_builder.h @@ -0,0 +1,50 @@ +/* Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#pragma once + +#include "vpe_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct vpe_priv; + +struct cmd_builder { + enum vpe_status (*build_noops)( + struct vpe_priv *vpe_priv, uint32_t **ppbuf, uint32_t num_dwords); + + // prelimenary APIs + enum vpe_status (*build_vpe_cmd)( + struct vpe_priv *vpe_priv, struct vpe_build_bufs *cur_bufs, uint32_t cmd_idx); + + enum vpe_status (*build_plane_descriptor)( + struct vpe_priv *vpe_priv, struct vpe_buf *buf, uint32_t cmd_idx); + +}; + +#ifdef __cplusplus +} +#endif diff --git a/src/amd/vpelib/src/core/inc/color.h b/src/amd/vpelib/src/core/inc/color.h new file mode 100644 index 00000000000..231ef6a737c --- /dev/null +++ b/src/amd/vpelib/src/core/inc/color.h @@ -0,0 +1,247 @@ +/* Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#pragma once + +#include "vpe_types.h" +#include "fixed31_32.h" +#include "hw_shared.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define SDR_VIDEO_WHITE_POINT 100 // nits +#define SDR_WHITE_POINT 80 // nits +#define HDR_PEAK_WHITE 10000 + +struct vpe_priv; +struct stream_ctx; + +enum color_depth { + COLOR_DEPTH_UNDEFINED, + COLOR_DEPTH_666, + COLOR_DEPTH_888, + COLOR_DEPTH_101010, + COLOR_DEPTH_121212, + COLOR_DEPTH_141414, + COLOR_DEPTH_161616, + COLOR_DEPTH_999, + COLOR_DEPTH_111111, + COLOR_DEPTH_COUNT +}; + +enum color_transfer_func { + TRANSFER_FUNC_UNKNOWN, + TRANSFER_FUNC_SRGB, + TRANSFER_FUNC_BT709, + TRANSFER_FUNC_BT1886, + TRANSFER_FUNC_PQ2084, + TRANSFER_FUNC_LINEAR_0_125, + TRANSFER_FUNC_NORMALIZED_PQ +}; + +enum dither_option { + DITHER_OPTION_DEFAULT, + DITHER_OPTION_DISABLE, + DITHER_OPTION_FM6, + DITHER_OPTION_FM8, + DITHER_OPTION_FM10, + DITHER_OPTION_SPATIAL6_FRAME_RANDOM, + DITHER_OPTION_SPATIAL8_FRAME_RANDOM, + DITHER_OPTION_SPATIAL10_FRAME_RANDOM, + DITHER_OPTION_SPATIAL6, + DITHER_OPTION_SPATIAL8, + DITHER_OPTION_SPATIAL10, + DITHER_OPTION_TRUN6, + DITHER_OPTION_TRUN8, + DITHER_OPTION_TRUN10, + DITHER_OPTION_TRUN10_SPATIAL8, + DITHER_OPTION_TRUN10_SPATIAL6, + DITHER_OPTION_TRUN10_FM8, + DITHER_OPTION_TRUN10_FM6, + DITHER_OPTION_TRUN10_SPATIAL8_FM6, + DITHER_OPTION_SPATIAL10_FM8, + DITHER_OPTION_SPATIAL10_FM6, + DITHER_OPTION_TRUN8_SPATIAL6, + DITHER_OPTION_TRUN8_FM6, + DITHER_OPTION_SPATIAL8_FM6, + DITHER_OPTION_MAX = DITHER_OPTION_SPATIAL8_FM6, + DITHER_OPTION_INVALID +}; + +enum color_space { + COLOR_SPACE_UNKNOWN, + COLOR_SPACE_SRGB, + COLOR_SPACE_SRGB_LIMITED, + COLOR_SPACE_MSREF_SCRGB, + COLOR_SPACE_YCBCR601, + COLOR_SPACE_YCBCR709, + COLOR_SPACE_JFIF, + COLOR_SPACE_YCBCR601_LIMITED, + COLOR_SPACE_YCBCR709_LIMITED, + COLOR_SPACE_2020_RGB_FULLRANGE, + COLOR_SPACE_2020_RGB_LIMITEDRANGE, + COLOR_SPACE_2020_YCBCR, + COLOR_SPACE_2020_YCBCR_LIMITED, + COLOR_SPACE_MAX, +}; + +enum transfer_func_type { + TF_TYPE_PREDEFINED, + TF_TYPE_DISTRIBUTED_POINTS, + TF_TYPE_BYPASS, + TF_TYPE_HWPWL +}; + +enum { + TRANSFER_FUNC_POINTS = 1025 +}; + +typedef struct fixed31_32 white_point_gain; + +struct transfer_func_distributed_points { + struct fixed31_32 red[TRANSFER_FUNC_POINTS]; + struct fixed31_32 green[TRANSFER_FUNC_POINTS]; + struct fixed31_32 blue[TRANSFER_FUNC_POINTS]; + + uint16_t end_exponent; + uint16_t x_point_at_y1_red; + uint16_t x_point_at_y1_green; + uint16_t x_point_at_y1_blue; +}; + +struct transfer_func { + enum transfer_func_type type; + enum color_transfer_func tf; + + /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/ + uint32_t sdr_ref_white_level; + union { + struct pwl_params pwl; + struct transfer_func_distributed_points tf_pts; + }; + bool use_pre_calculated_table; +}; + +enum color_white_point_type { + color_white_point_type_unknown, + color_white_point_type_5000k_horizon, + color_white_point_type_6500k_noon, + color_white_point_type_7500k_north_sky, + color_white_point_type_9300k, + color_white_point_type_custom_coordinates +}; + +struct color_space_coordinates { + unsigned int redX; + unsigned int redY; + unsigned int greenX; + unsigned int greenY; + unsigned int blueX; + unsigned int blueY; + unsigned int whiteX; + unsigned int whiteY; +}; + +enum predefined_gamut_type { + gamut_type_bt709, + gamut_type_bt601, + gamut_type_adobe_rgb, + gamut_type_srgb, + gamut_type_bt2020, + gamut_type_dcip3, + gamut_type_unknown, +}; + +enum predefined_white_point_type { + white_point_type_5000k_horizon, + white_point_type_6500k_noon, + white_point_type_7500k_north_sky, + white_point_type_9300k, + white_point_type_unknown, +}; + +struct colorspace_transform { + struct fixed31_32 matrix[12]; + bool enable_remap; +}; + +struct color_gamut_data { + enum color_space color_space; + enum color_white_point_type white_point; + struct color_space_coordinates gamut; +}; + +union vpe_3dlut_state { + struct { + uint32_t initialized : 1; /*if 3dlut is went through color module for initialization */ + uint32_t reserved : 15; + } bits; + uint32_t raw; +}; + +struct vpe_3dlut { + // struct kref refcount; + struct tetrahedral_params lut_3d; + struct fixed31_32 hdr_multiplier; + union vpe_3dlut_state state; +}; + +enum vpe_status vpe_color_update_color_space_and_tf( + struct vpe_priv *vpe_priv, const struct vpe_build_param *param); + +enum vpe_status vpe_color_update_movable_cm( + struct vpe_priv *vpe_priv, const struct vpe_build_param *param); + +void vpe_color_get_color_space_and_tf( + const struct vpe_color_space *vcs, enum color_space *cs, enum color_transfer_func *tf); + +bool vpe_use_csc_adjust(const struct vpe_color_adjust *adjustments); + +bool vpe_is_rgb_equal(const struct pwl_result_data *rgb, uint32_t num); + +bool vpe_is_HDR(enum color_transfer_func tf); + +void vpe_convert_full_range_color_enum(enum color_space *cs); + +enum vpe_status vpe_color_update_whitepoint( + const struct vpe_priv *vpe_priv, const struct vpe_build_param *param); + +enum vpe_status vpe_color_tm_update_hdr_mult(uint16_t shaper_in_exp_max, uint32_t peak_white, + struct fixed31_32 *hdr_multiplier, bool enable_3dlut); + +enum vpe_status vpe_color_update_shaper( + uint16_t shaper_in_exp_max, struct transfer_func *shaper_func, bool enable_3dlut); + +enum vpe_status vpe_color_update_blnd_gam(struct vpe_priv *vpe_priv, + const struct vpe_build_param *param, const struct vpe_tonemap_params *tm_params, + struct transfer_func *blnd_tf_func, bool enable_3dlut); + +enum vpe_status vpe_color_build_tm_cs(const struct vpe_tonemap_params *tm_params, + struct vpe_surface_info surface_info, struct vpe_color_space *vcs); + +#ifdef __cplusplus +} +#endif diff --git a/src/amd/vpelib/src/core/inc/color_bg.h b/src/amd/vpelib/src/core/inc/color_bg.h new file mode 100644 index 00000000000..8821e9e6948 --- /dev/null +++ b/src/amd/vpelib/src/core/inc/color_bg.h @@ -0,0 +1,33 @@ +/* Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#pragma once + +#include "color.h" + +void vpe_bg_color_convert( + enum color_space cs, struct transfer_func *output_tf, struct vpe_color *bg_color); + +enum vpe_status vpe_bg_color_outside_cs_gamut( + const struct vpe_color_space *vcs, struct vpe_color *bg_color); diff --git a/src/amd/vpelib/src/core/inc/color_cs.h b/src/amd/vpelib/src/core/inc/color_cs.h new file mode 100644 index 00000000000..6ccbed1a86e --- /dev/null +++ b/src/amd/vpelib/src/core/inc/color_cs.h @@ -0,0 +1,58 @@ +/* Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#pragma once + +#include "fixed31_32.h" +#include "color_table.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct color_range { + int current; + int min; + int max; +}; + +struct vpe_color_adjustments { + struct color_range contrast; + struct color_range saturation; + struct color_range brightness; + struct color_range hue; +}; + +bool vpe_color_calculate_input_cs(struct vpe_priv *vpe_priv, enum color_space in_cs, + const struct vpe_color_adjust *vpe_adjust, struct vpe_csc_matrix *input_cs, + struct fixed31_32 *matrix_scaling_factor); + +bool vpe_color_different_color_adjusts( + const struct vpe_color_adjust *new_vpe_adjusts, struct vpe_color_adjust *crt_vpe_adjusts); + +void vpe_color_set_adjustments_to_default(struct vpe_color_adjust *crt_vpe_adjusts); + +#ifdef __cplusplus +} +#endif diff --git a/src/amd/vpelib/src/core/inc/color_gamma.h b/src/amd/vpelib/src/core/inc/color_gamma.h new file mode 100644 index 00000000000..a870697947f --- /dev/null +++ b/src/amd/vpelib/src/core/inc/color_gamma.h @@ -0,0 +1,64 @@ +/* Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#pragma once + +#include "fixed31_32.h" +#include "color_table.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct calculate_buffer { + int buffer_index; + struct fixed31_32 buffer[NUM_PTS_IN_REGION]; + struct fixed31_32 gamma_of_2; +}; + +struct translate_from_linear_space_args { + struct fixed31_32 arg; + struct fixed31_32 a0; + struct fixed31_32 a1; + struct fixed31_32 a2; + struct fixed31_32 a3; + struct fixed31_32 gamma; + struct calculate_buffer *cal_buffer; +}; + +void vpe_color_setup_x_points_distribution(void); + +void vpe_color_setup_x_points_distribution_degamma(void); + +bool vpe_color_calculate_regamma_params(struct vpe_priv *vpe_priv, struct transfer_func *output_tf, + struct calculate_buffer *cal_buffer); + +bool vpe_color_calculate_degamma_params(struct vpe_priv *vpe_priv, struct fixed31_32 x_scale, + struct fixed31_32 y_scale, struct transfer_func *input_tf); + +void vpe_compute_pq(struct fixed31_32 in_x, struct fixed31_32 *out_y); + +#ifdef __cplusplus +} +#endif diff --git a/src/amd/vpelib/src/core/inc/color_gamut.h b/src/amd/vpelib/src/core/inc/color_gamut.h new file mode 100644 index 00000000000..e2f4ea5d1f1 --- /dev/null +++ b/src/amd/vpelib/src/core/inc/color_gamut.h @@ -0,0 +1,40 @@ +/* Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#pragma once + +#include "vpe_types.h" +#include "fixed31_32.h" +#include "vpe_priv.h" + +#ifdef __cplusplus +extern "C" { +#endif + +enum vpe_status vpe_color_update_gamut(struct vpe_priv *vpe_priv, enum color_space in_color, + enum color_space outColor, struct colorspace_transform *gamut_remap, bool bypass_remap); + +#ifdef __cplusplus +} +#endif diff --git a/src/amd/vpelib/src/core/inc/color_pwl.h b/src/amd/vpelib/src/core/inc/color_pwl.h new file mode 100644 index 00000000000..8166e7ed19c --- /dev/null +++ b/src/amd/vpelib/src/core/inc/color_pwl.h @@ -0,0 +1,2330 @@ +/* Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ +#include "custom_float.h" +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#define NUM_OF_LUT_DATA_DEGAM 256 +#define NUM_OF_LUT_DATA_REGAM_PQ 202 +#define NUM_OF_LUT_DATA_REGAM_LINEAR 224 +#define NUM_OF_LUT_DATA_REGAM_SDR 186 +#define NUM_OF_TRANSFER_FUNCTION 4 + +/* +Table Layout: + + Degam Regam +[0][0] SRGB [1][0] SRGB +[0][1] G24 [1][1] G24 +[0][2] PQ [1][2] PQ +[0][3] BT.709 [1][3] G10 + +*/ + +static struct pwl_params tf_pwl_param_table[2][NUM_OF_TRANSFER_FUNCTION] = { + { + // Degam + {.hw_points_num = NUM_OF_LUT_DATA_DEGAM, + .arr_curve_points = {{0x0, 0x0}, {0x1, 0x0}, {0x2, 0x1}, {0x4, 0x2}, {0x8, 0x3}, + {0x10, 0x4}, {0x20, 0x5}, {0x40, 0x6}, {0x80, 0x7}, {0x0, 0x0}, {0x0, 0x0}, + {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, + {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, + {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, + {0x0, 0x0}, {0x0, 0x0}}, + .corner_points = {{.red.custom_float_x = 0x16000, + .red.custom_float_y = 0x0, + .red.custom_float_slope = 0x1b3d0, + .green.custom_float_x = 0x16000, + .green.custom_float_y = 0x0, + .green.custom_float_slope = 0x1b3d0, + .blue.custom_float_x = 0x16000, + .blue.custom_float_y = 0x0, + .blue.custom_float_slope = 0x1b3d0}, + {.red.custom_float_x = 0x7c00, + .red.custom_float_y = 0x1f000, + .red.custom_float_slope = 0x0, + .green.custom_float_x = 0x7c00, + .green.custom_float_y = 0x1f000, + .green.custom_float_slope = 0x0, + .blue.custom_float_x = 0x7c00, + .blue.custom_float_y = 0x1f000, + .blue.custom_float_slope = 0x0}}, + .rgb_resulted = {{.red_reg = 0x123d0, .green_reg = 0x123d0, .blue_reg = 0x123d0}, + {.red_reg = 0x133d0, .green_reg = 0x133d0, .blue_reg = 0x133d0}, + {.red_reg = 0x143d0, .green_reg = 0x143d0, .blue_reg = 0x143d0}, + {.red_reg = 0x14db8, .green_reg = 0x14db8, .blue_reg = 0x14db8}, + {.red_reg = 0x153d0, .green_reg = 0x153d0, .blue_reg = 0x153d0}, + {.red_reg = 0x158c4, .green_reg = 0x158c4, .blue_reg = 0x158c4}, + {.red_reg = 0x15db8, .green_reg = 0x15db8, .blue_reg = 0x15db8}, + {.red_reg = 0x16156, .green_reg = 0x16156, .blue_reg = 0x16156}, + {.red_reg = 0x163d0, .green_reg = 0x163d0, .blue_reg = 0x163d0}, + {.red_reg = 0x1664a, .green_reg = 0x1664a, .blue_reg = 0x1664a}, + {.red_reg = 0x168c4, .green_reg = 0x168c4, .blue_reg = 0x168c4}, + {.red_reg = 0x16b4d, .green_reg = 0x16b4d, .blue_reg = 0x16b4d}, + {.red_reg = 0x16dfc, .green_reg = 0x16dfc, .blue_reg = 0x16dfc}, + {.red_reg = 0x17069, .green_reg = 0x17069, .blue_reg = 0x17069}, + {.red_reg = 0x171e7, .green_reg = 0x171e7, .blue_reg = 0x171e7}, + {.red_reg = 0x17378, .green_reg = 0x17378, .blue_reg = 0x17378}, + {.red_reg = 0x1751e, .green_reg = 0x1751e, .blue_reg = 0x1751e}, + {.red_reg = 0x176d7, .green_reg = 0x176d7, .blue_reg = 0x176d7}, + {.red_reg = 0x178a5, .green_reg = 0x178a5, .blue_reg = 0x178a5}, + {.red_reg = 0x17a87, .green_reg = 0x17a87, .blue_reg = 0x17a87}, + {.red_reg = 0x17c7e, .green_reg = 0x17c7e, .blue_reg = 0x17c7e}, + {.red_reg = 0x17e8b, .green_reg = 0x17e8b, .blue_reg = 0x17e8b}, + {.red_reg = 0x18056, .green_reg = 0x18056, .blue_reg = 0x18056}, + {.red_reg = 0x18172, .green_reg = 0x18172, .blue_reg = 0x18172}, + {.red_reg = 0x18298, .green_reg = 0x18298, .blue_reg = 0x18298}, + {.red_reg = 0x183ca, .green_reg = 0x183ca, .blue_reg = 0x183ca}, + {.red_reg = 0x18506, .green_reg = 0x18506, .blue_reg = 0x18506}, + {.red_reg = 0x1864e, .green_reg = 0x1864e, .blue_reg = 0x1864e}, + {.red_reg = 0x187a2, .green_reg = 0x187a2, .blue_reg = 0x187a2}, + {.red_reg = 0x18901, .green_reg = 0x18901, .blue_reg = 0x18901}, + {.red_reg = 0x18a6b, .green_reg = 0x18a6b, .blue_reg = 0x18a6b}, + {.red_reg = 0x18be1, .green_reg = 0x18be1, .blue_reg = 0x18be1}, + {.red_reg = 0x18d63, .green_reg = 0x18d63, .blue_reg = 0x18d63}, + {.red_reg = 0x18ef1, .green_reg = 0x18ef1, .blue_reg = 0x18ef1}, + {.red_reg = 0x19045, .green_reg = 0x19045, .blue_reg = 0x19045}, + {.red_reg = 0x19118, .green_reg = 0x19118, .blue_reg = 0x19118}, + {.red_reg = 0x191f1, .green_reg = 0x191f1, .blue_reg = 0x191f1}, + {.red_reg = 0x192d0, .green_reg = 0x192d0, .blue_reg = 0x192d0}, + {.red_reg = 0x193b6, .green_reg = 0x193b6, .blue_reg = 0x193b6}, + {.red_reg = 0x194a1, .green_reg = 0x194a1, .blue_reg = 0x194a1}, + {.red_reg = 0x19593, .green_reg = 0x19593, .blue_reg = 0x19593}, + {.red_reg = 0x1968c, .green_reg = 0x1968c, .blue_reg = 0x1968c}, + {.red_reg = 0x1978a, .green_reg = 0x1978a, .blue_reg = 0x1978a}, + {.red_reg = 0x19890, .green_reg = 0x19890, .blue_reg = 0x19890}, + {.red_reg = 0x1999b, .green_reg = 0x1999b, .blue_reg = 0x1999b}, + {.red_reg = 0x19aad, .green_reg = 0x19aad, .blue_reg = 0x19aad}, + {.red_reg = 0x19bc6, .green_reg = 0x19bc6, .blue_reg = 0x19bc6}, + {.red_reg = 0x19ce6, .green_reg = 0x19ce6, .blue_reg = 0x19ce6}, + {.red_reg = 0x19e0c, .green_reg = 0x19e0c, .blue_reg = 0x19e0c}, + {.red_reg = 0x19f38, .green_reg = 0x19f38, .blue_reg = 0x19f38}, + {.red_reg = 0x1a036, .green_reg = 0x1a036, .blue_reg = 0x1a036}, + {.red_reg = 0x1a0d3, .green_reg = 0x1a0d3, .blue_reg = 0x1a0d3}, + {.red_reg = 0x1a173, .green_reg = 0x1a173, .blue_reg = 0x1a173}, + {.red_reg = 0x1a217, .green_reg = 0x1a217, .blue_reg = 0x1a217}, + {.red_reg = 0x1a2bf, .green_reg = 0x1a2bf, .blue_reg = 0x1a2bf}, + {.red_reg = 0x1a36a, .green_reg = 0x1a36a, .blue_reg = 0x1a36a}, + {.red_reg = 0x1a418, .green_reg = 0x1a418, .blue_reg = 0x1a418}, + {.red_reg = 0x1a4ca, .green_reg = 0x1a4ca, .blue_reg = 0x1a4ca}, + {.red_reg = 0x1a580, .green_reg = 0x1a580, .blue_reg = 0x1a580}, + {.red_reg = 0x1a639, .green_reg = 0x1a639, .blue_reg = 0x1a639}, + {.red_reg = 0x1a6f5, .green_reg = 0x1a6f5, .blue_reg = 0x1a6f5}, + {.red_reg = 0x1a7b5, .green_reg = 0x1a7b5, .blue_reg = 0x1a7b5}, + {.red_reg = 0x1a879, .green_reg = 0x1a879, .blue_reg = 0x1a879}, + {.red_reg = 0x1a941, .green_reg = 0x1a941, .blue_reg = 0x1a941}, + {.red_reg = 0x1aa0c, .green_reg = 0x1aa0c, .blue_reg = 0x1aa0c}, + {.red_reg = 0x1aadb, .green_reg = 0x1aadb, .blue_reg = 0x1aadb}, + {.red_reg = 0x1abad, .green_reg = 0x1abad, .blue_reg = 0x1abad}, + {.red_reg = 0x1ac83, .green_reg = 0x1ac83, .blue_reg = 0x1ac83}, + {.red_reg = 0x1ad5d, .green_reg = 0x1ad5d, .blue_reg = 0x1ad5d}, + {.red_reg = 0x1ae3b, .green_reg = 0x1ae3b, .blue_reg = 0x1ae3b}, + {.red_reg = 0x1af1d, .green_reg = 0x1af1d, .blue_reg = 0x1af1d}, + {.red_reg = 0x1b001, .green_reg = 0x1b001, .blue_reg = 0x1b001}, + {.red_reg = 0x1b075, .green_reg = 0x1b075, .blue_reg = 0x1b075}, + {.red_reg = 0x1b0ec, .green_reg = 0x1b0ec, .blue_reg = 0x1b0ec}, + {.red_reg = 0x1b164, .green_reg = 0x1b164, .blue_reg = 0x1b164}, + {.red_reg = 0x1b1de, .green_reg = 0x1b1de, .blue_reg = 0x1b1de}, + {.red_reg = 0x1b25b, .green_reg = 0x1b25b, .blue_reg = 0x1b25b}, + {.red_reg = 0x1b2d9, .green_reg = 0x1b2d9, .blue_reg = 0x1b2d9}, + {.red_reg = 0x1b359, .green_reg = 0x1b359, .blue_reg = 0x1b359}, + {.red_reg = 0x1b3db, .green_reg = 0x1b3db, .blue_reg = 0x1b3db}, + {.red_reg = 0x1b45f, .green_reg = 0x1b45f, .blue_reg = 0x1b45f}, + {.red_reg = 0x1b4e5, .green_reg = 0x1b4e5, .blue_reg = 0x1b4e5}, + {.red_reg = 0x1b56d, .green_reg = 0x1b56d, .blue_reg = 0x1b56d}, + {.red_reg = 0x1b5f7, .green_reg = 0x1b5f7, .blue_reg = 0x1b5f7}, + {.red_reg = 0x1b683, .green_reg = 0x1b683, .blue_reg = 0x1b683}, + {.red_reg = 0x1b711, .green_reg = 0x1b711, .blue_reg = 0x1b711}, + {.red_reg = 0x1b7a1, .green_reg = 0x1b7a1, .blue_reg = 0x1b7a1}, + {.red_reg = 0x1b833, .green_reg = 0x1b833, .blue_reg = 0x1b833}, + {.red_reg = 0x1b8c7, .green_reg = 0x1b8c7, .blue_reg = 0x1b8c7}, + {.red_reg = 0x1b95e, .green_reg = 0x1b95e, .blue_reg = 0x1b95e}, + {.red_reg = 0x1b9f6, .green_reg = 0x1b9f6, .blue_reg = 0x1b9f6}, + {.red_reg = 0x1ba90, .green_reg = 0x1ba90, .blue_reg = 0x1ba90}, + {.red_reg = 0x1bb2c, .green_reg = 0x1bb2c, .blue_reg = 0x1bb2c}, + {.red_reg = 0x1bbcb, .green_reg = 0x1bbcb, .blue_reg = 0x1bbcb}, + {.red_reg = 0x1bc6b, .green_reg = 0x1bc6b, .blue_reg = 0x1bc6b}, + {.red_reg = 0x1bd0e, .green_reg = 0x1bd0e, .blue_reg = 0x1bd0e}, + {.red_reg = 0x1bdb3, .green_reg = 0x1bdb3, .blue_reg = 0x1bdb3}, + {.red_reg = 0x1be5a, .green_reg = 0x1be5a, .blue_reg = 0x1be5a}, + {.red_reg = 0x1bf02, .green_reg = 0x1bf02, .blue_reg = 0x1bf02}, + {.red_reg = 0x1bfae, .green_reg = 0x1bfae, .blue_reg = 0x1bfae}, + {.red_reg = 0x1c02d, .green_reg = 0x1c02d, .blue_reg = 0x1c02d}, + {.red_reg = 0x1c085, .green_reg = 0x1c085, .blue_reg = 0x1c085}, + {.red_reg = 0x1c0de, .green_reg = 0x1c0de, .blue_reg = 0x1c0de}, + {.red_reg = 0x1c137, .green_reg = 0x1c137, .blue_reg = 0x1c137}, + {.red_reg = 0x1c192, .green_reg = 0x1c192, .blue_reg = 0x1c192}, + {.red_reg = 0x1c1ee, .green_reg = 0x1c1ee, .blue_reg = 0x1c1ee}, + {.red_reg = 0x1c24b, .green_reg = 0x1c24b, .blue_reg = 0x1c24b}, + {.red_reg = 0x1c2a9, .green_reg = 0x1c2a9, .blue_reg = 0x1c2a9}, + {.red_reg = 0x1c309, .green_reg = 0x1c309, .blue_reg = 0x1c309}, + {.red_reg = 0x1c369, .green_reg = 0x1c369, .blue_reg = 0x1c369}, + {.red_reg = 0x1c3cb, .green_reg = 0x1c3cb, .blue_reg = 0x1c3cb}, + {.red_reg = 0x1c42d, .green_reg = 0x1c42d, .blue_reg = 0x1c42d}, + {.red_reg = 0x1c491, .green_reg = 0x1c491, .blue_reg = 0x1c491}, + {.red_reg = 0x1c4f6, .green_reg = 0x1c4f6, .blue_reg = 0x1c4f6}, + {.red_reg = 0x1c55b, .green_reg = 0x1c55b, .blue_reg = 0x1c55b}, + {.red_reg = 0x1c5c2, .green_reg = 0x1c5c2, .blue_reg = 0x1c5c2}, + {.red_reg = 0x1c62b, .green_reg = 0x1c62b, .blue_reg = 0x1c62b}, + {.red_reg = 0x1c694, .green_reg = 0x1c694, .blue_reg = 0x1c694}, + {.red_reg = 0x1c6fe, .green_reg = 0x1c6fe, .blue_reg = 0x1c6fe}, + {.red_reg = 0x1c76a, .green_reg = 0x1c76a, .blue_reg = 0x1c76a}, + {.red_reg = 0x1c7d6, .green_reg = 0x1c7d6, .blue_reg = 0x1c7d6}, + {.red_reg = 0x1c844, .green_reg = 0x1c844, .blue_reg = 0x1c844}, + {.red_reg = 0x1c8b3, .green_reg = 0x1c8b3, .blue_reg = 0x1c8b3}, + {.red_reg = 0x1c923, .green_reg = 0x1c923, .blue_reg = 0x1c923}, + {.red_reg = 0x1c995, .green_reg = 0x1c995, .blue_reg = 0x1c995}, + {.red_reg = 0x1ca07, .green_reg = 0x1ca07, .blue_reg = 0x1ca07}, + {.red_reg = 0x1ca7b, .green_reg = 0x1ca7b, .blue_reg = 0x1ca7b}, + {.red_reg = 0x1caef, .green_reg = 0x1caef, .blue_reg = 0x1caef}, + {.red_reg = 0x1cb65, .green_reg = 0x1cb65, .blue_reg = 0x1cb65}, + {.red_reg = 0x1cbdc, .green_reg = 0x1cbdc, .blue_reg = 0x1cbdc}, + {.red_reg = 0x1cc54, .green_reg = 0x1cc54, .blue_reg = 0x1cc54}, + {.red_reg = 0x1ccce, .green_reg = 0x1ccce, .blue_reg = 0x1ccce}, + {.red_reg = 0x1cd48, .green_reg = 0x1cd48, .blue_reg = 0x1cd48}, + {.red_reg = 0x1cdc4, .green_reg = 0x1cdc4, .blue_reg = 0x1cdc4}, + {.red_reg = 0x1ce41, .green_reg = 0x1ce41, .blue_reg = 0x1ce41}, + {.red_reg = 0x1cebf, .green_reg = 0x1cebf, .blue_reg = 0x1cebf}, + {.red_reg = 0x1cf3f, .green_reg = 0x1cf3f, .blue_reg = 0x1cf3f}, + {.red_reg = 0x1cfbf, .green_reg = 0x1cfbf, .blue_reg = 0x1cfbf}, + {.red_reg = 0x1d020, .green_reg = 0x1d020, .blue_reg = 0x1d020}, + {.red_reg = 0x1d062, .green_reg = 0x1d062, .blue_reg = 0x1d062}, + {.red_reg = 0x1d0a4, .green_reg = 0x1d0a4, .blue_reg = 0x1d0a4}, + {.red_reg = 0x1d0e6, .green_reg = 0x1d0e6, .blue_reg = 0x1d0e6}, + {.red_reg = 0x1d12a, .green_reg = 0x1d12a, .blue_reg = 0x1d12a}, + {.red_reg = 0x1d16d, .green_reg = 0x1d16d, .blue_reg = 0x1d16d}, + {.red_reg = 0x1d1b2, .green_reg = 0x1d1b2, .blue_reg = 0x1d1b2}, + {.red_reg = 0x1d1f7, .green_reg = 0x1d1f7, .blue_reg = 0x1d1f7}, + {.red_reg = 0x1d23d, .green_reg = 0x1d23d, .blue_reg = 0x1d23d}, + {.red_reg = 0x1d283, .green_reg = 0x1d283, .blue_reg = 0x1d283}, + {.red_reg = 0x1d2ca, .green_reg = 0x1d2ca, .blue_reg = 0x1d2ca}, + {.red_reg = 0x1d312, .green_reg = 0x1d312, .blue_reg = 0x1d312}, + {.red_reg = 0x1d35a, .green_reg = 0x1d35a, .blue_reg = 0x1d35a}, + {.red_reg = 0x1d3a2, .green_reg = 0x1d3a2, .blue_reg = 0x1d3a2}, + {.red_reg = 0x1d3ec, .green_reg = 0x1d3ec, .blue_reg = 0x1d3ec}, + {.red_reg = 0x1d436, .green_reg = 0x1d436, .blue_reg = 0x1d436}, + {.red_reg = 0x1d481, .green_reg = 0x1d481, .blue_reg = 0x1d481}, + {.red_reg = 0x1d4cc, .green_reg = 0x1d4cc, .blue_reg = 0x1d4cc}, + {.red_reg = 0x1d518, .green_reg = 0x1d518, .blue_reg = 0x1d518}, + {.red_reg = 0x1d564, .green_reg = 0x1d564, .blue_reg = 0x1d564}, + {.red_reg = 0x1d5b1, .green_reg = 0x1d5b1, .blue_reg = 0x1d5b1}, + {.red_reg = 0x1d5ff, .green_reg = 0x1d5ff, .blue_reg = 0x1d5ff}, + {.red_reg = 0x1d64d, .green_reg = 0x1d64d, .blue_reg = 0x1d64d}, + {.red_reg = 0x1d69d, .green_reg = 0x1d69d, .blue_reg = 0x1d69d}, + {.red_reg = 0x1d6ec, .green_reg = 0x1d6ec, .blue_reg = 0x1d6ec}, + {.red_reg = 0x1d73d, .green_reg = 0x1d73d, .blue_reg = 0x1d73d}, + {.red_reg = 0x1d78d, .green_reg = 0x1d78d, .blue_reg = 0x1d78d}, + {.red_reg = 0x1d7df, .green_reg = 0x1d7df, .blue_reg = 0x1d7df}, + {.red_reg = 0x1d831, .green_reg = 0x1d831, .blue_reg = 0x1d831}, + {.red_reg = 0x1d884, .green_reg = 0x1d884, .blue_reg = 0x1d884}, + {.red_reg = 0x1d8d8, .green_reg = 0x1d8d8, .blue_reg = 0x1d8d8}, + {.red_reg = 0x1d92c, .green_reg = 0x1d92c, .blue_reg = 0x1d92c}, + {.red_reg = 0x1d981, .green_reg = 0x1d981, .blue_reg = 0x1d981}, + {.red_reg = 0x1d9d6, .green_reg = 0x1d9d6, .blue_reg = 0x1d9d6}, + {.red_reg = 0x1da2c, .green_reg = 0x1da2c, .blue_reg = 0x1da2c}, + {.red_reg = 0x1da83, .green_reg = 0x1da83, .blue_reg = 0x1da83}, + {.red_reg = 0x1dada, .green_reg = 0x1dada, .blue_reg = 0x1dada}, + {.red_reg = 0x1db32, .green_reg = 0x1db32, .blue_reg = 0x1db32}, + {.red_reg = 0x1db8b, .green_reg = 0x1db8b, .blue_reg = 0x1db8b}, + {.red_reg = 0x1dbe4, .green_reg = 0x1dbe4, .blue_reg = 0x1dbe4}, + {.red_reg = 0x1dc3e, .green_reg = 0x1dc3e, .blue_reg = 0x1dc3e}, + {.red_reg = 0x1dc99, .green_reg = 0x1dc99, .blue_reg = 0x1dc99}, + {.red_reg = 0x1dcf4, .green_reg = 0x1dcf4, .blue_reg = 0x1dcf4}, + {.red_reg = 0x1dd50, .green_reg = 0x1dd50, .blue_reg = 0x1dd50}, + {.red_reg = 0x1ddad, .green_reg = 0x1ddad, .blue_reg = 0x1ddad}, + {.red_reg = 0x1de0a, .green_reg = 0x1de0a, .blue_reg = 0x1de0a}, + {.red_reg = 0x1de68, .green_reg = 0x1de68, .blue_reg = 0x1de68}, + {.red_reg = 0x1dec7, .green_reg = 0x1dec7, .blue_reg = 0x1dec7}, + {.red_reg = 0x1df26, .green_reg = 0x1df26, .blue_reg = 0x1df26}, + {.red_reg = 0x1df86, .green_reg = 0x1df86, .blue_reg = 0x1df86}, + {.red_reg = 0x1dfe7, .green_reg = 0x1dfe7, .blue_reg = 0x1dfe7}, + {.red_reg = 0x1e024, .green_reg = 0x1e024, .blue_reg = 0x1e024}, + {.red_reg = 0x1e055, .green_reg = 0x1e055, .blue_reg = 0x1e055}, + {.red_reg = 0x1e086, .green_reg = 0x1e086, .blue_reg = 0x1e086}, + {.red_reg = 0x1e0b8, .green_reg = 0x1e0b8, .blue_reg = 0x1e0b8}, + {.red_reg = 0x1e0ea, .green_reg = 0x1e0ea, .blue_reg = 0x1e0ea}, + {.red_reg = 0x1e11c, .green_reg = 0x1e11c, .blue_reg = 0x1e11c}, + {.red_reg = 0x1e14f, .green_reg = 0x1e14f, .blue_reg = 0x1e14f}, + {.red_reg = 0x1e182, .green_reg = 0x1e182, .blue_reg = 0x1e182}, + {.red_reg = 0x1e1b5, .green_reg = 0x1e1b5, .blue_reg = 0x1e1b5}, + {.red_reg = 0x1e1e9, .green_reg = 0x1e1e9, .blue_reg = 0x1e1e9}, + {.red_reg = 0x1e21d, .green_reg = 0x1e21d, .blue_reg = 0x1e21d}, + {.red_reg = 0x1e252, .green_reg = 0x1e252, .blue_reg = 0x1e252}, + {.red_reg = 0x1e286, .green_reg = 0x1e286, .blue_reg = 0x1e286}, + {.red_reg = 0x1e2bc, .green_reg = 0x1e2bc, .blue_reg = 0x1e2bc}, + {.red_reg = 0x1e2f1, .green_reg = 0x1e2f1, .blue_reg = 0x1e2f1}, + {.red_reg = 0x1e327, .green_reg = 0x1e327, .blue_reg = 0x1e327}, + {.red_reg = 0x1e35d, .green_reg = 0x1e35d, .blue_reg = 0x1e35d}, + {.red_reg = 0x1e393, .green_reg = 0x1e393, .blue_reg = 0x1e393}, + {.red_reg = 0x1e3ca, .green_reg = 0x1e3ca, .blue_reg = 0x1e3ca}, + {.red_reg = 0x1e401, .green_reg = 0x1e401, .blue_reg = 0x1e401}, + {.red_reg = 0x1e439, .green_reg = 0x1e439, .blue_reg = 0x1e439}, + {.red_reg = 0x1e471, .green_reg = 0x1e471, .blue_reg = 0x1e471}, + {.red_reg = 0x1e4a9, .green_reg = 0x1e4a9, .blue_reg = 0x1e4a9}, + {.red_reg = 0x1e4e2, .green_reg = 0x1e4e2, .blue_reg = 0x1e4e2}, + {.red_reg = 0x1e51b, .green_reg = 0x1e51b, .blue_reg = 0x1e51b}, + {.red_reg = 0x1e554, .green_reg = 0x1e554, .blue_reg = 0x1e554}, + {.red_reg = 0x1e58d, .green_reg = 0x1e58d, .blue_reg = 0x1e58d}, + {.red_reg = 0x1e5c7, .green_reg = 0x1e5c7, .blue_reg = 0x1e5c7}, + {.red_reg = 0x1e602, .green_reg = 0x1e602, .blue_reg = 0x1e602}, + {.red_reg = 0x1e63c, .green_reg = 0x1e63c, .blue_reg = 0x1e63c}, + {.red_reg = 0x1e678, .green_reg = 0x1e678, .blue_reg = 0x1e678}, + {.red_reg = 0x1e6b3, .green_reg = 0x1e6b3, .blue_reg = 0x1e6b3}, + {.red_reg = 0x1e6ef, .green_reg = 0x1e6ef, .blue_reg = 0x1e6ef}, + {.red_reg = 0x1e72b, .green_reg = 0x1e72b, .blue_reg = 0x1e72b}, + {.red_reg = 0x1e767, .green_reg = 0x1e767, .blue_reg = 0x1e767}, + {.red_reg = 0x1e7a4, .green_reg = 0x1e7a4, .blue_reg = 0x1e7a4}, + {.red_reg = 0x1e7e1, .green_reg = 0x1e7e1, .blue_reg = 0x1e7e1}, + {.red_reg = 0x1e81f, .green_reg = 0x1e81f, .blue_reg = 0x1e81f}, + {.red_reg = 0x1e85d, .green_reg = 0x1e85d, .blue_reg = 0x1e85d}, + {.red_reg = 0x1e89b, .green_reg = 0x1e89b, .blue_reg = 0x1e89b}, + {.red_reg = 0x1e8da, .green_reg = 0x1e8da, .blue_reg = 0x1e8da}, + {.red_reg = 0x1e919, .green_reg = 0x1e919, .blue_reg = 0x1e919}, + {.red_reg = 0x1e958, .green_reg = 0x1e958, .blue_reg = 0x1e958}, + {.red_reg = 0x1e998, .green_reg = 0x1e998, .blue_reg = 0x1e998}, + {.red_reg = 0x1e9d8, .green_reg = 0x1e9d8, .blue_reg = 0x1e9d8}, + {.red_reg = 0x1ea18, .green_reg = 0x1ea18, .blue_reg = 0x1ea18}, + {.red_reg = 0x1ea59, .green_reg = 0x1ea59, .blue_reg = 0x1ea59}, + {.red_reg = 0x1ea9a, .green_reg = 0x1ea9a, .blue_reg = 0x1ea9a}, + {.red_reg = 0x1eadc, .green_reg = 0x1eadc, .blue_reg = 0x1eadc}, + {.red_reg = 0x1eb1e, .green_reg = 0x1eb1e, .blue_reg = 0x1eb1e}, + {.red_reg = 0x1eb60, .green_reg = 0x1eb60, .blue_reg = 0x1eb60}, + {.red_reg = 0x1eba3, .green_reg = 0x1eba3, .blue_reg = 0x1eba3}, + {.red_reg = 0x1ebe6, .green_reg = 0x1ebe6, .blue_reg = 0x1ebe6}, + {.red_reg = 0x1ec29, .green_reg = 0x1ec29, .blue_reg = 0x1ec29}, + {.red_reg = 0x1ec6d, .green_reg = 0x1ec6d, .blue_reg = 0x1ec6d}, + {.red_reg = 0x1ecb1, .green_reg = 0x1ecb1, .blue_reg = 0x1ecb1}, + {.red_reg = 0x1ecf5, .green_reg = 0x1ecf5, .blue_reg = 0x1ecf5}, + {.red_reg = 0x1ed3a, .green_reg = 0x1ed3a, .blue_reg = 0x1ed3a}, + {.red_reg = 0x1ed80, .green_reg = 0x1ed80, .blue_reg = 0x1ed80}, + {.red_reg = 0x1edc5, .green_reg = 0x1edc5, .blue_reg = 0x1edc5}, + {.red_reg = 0x1ee0b, .green_reg = 0x1ee0b, .blue_reg = 0x1ee0b}, + {.red_reg = 0x1ee51, .green_reg = 0x1ee51, .blue_reg = 0x1ee51}, + {.red_reg = 0x1ee98, .green_reg = 0x1ee98, .blue_reg = 0x1ee98}, + {.red_reg = 0x1eedf, .green_reg = 0x1eedf, .blue_reg = 0x1eedf}, + {.red_reg = 0x1ef27, .green_reg = 0x1ef27, .blue_reg = 0x1ef27}, + {.red_reg = 0x1ef6f, .green_reg = 0x1ef6f, .blue_reg = 0x1ef6f}, + {.red_reg = 0x1efb7, .green_reg = 0x1efb7, .blue_reg = 0x1efb7}, + {.red_reg = 0x1f000, .green_reg = 0x1f000, .blue_reg = 0x1f000}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}}}, + {.hw_points_num = NUM_OF_LUT_DATA_DEGAM, + .arr_curve_points = {{0x0, 0x0}, {0x1, 0x0}, {0x2, 0x1}, {0x4, 0x2}, {0x8, 0x3}, + {0x10, 0x4}, {0x20, 0x5}, {0x40, 0x6}, {0x80, 0x7}, {0x0, 0x0}, {0x0, 0x0}, + {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, + {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, + {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, + {0x0, 0x0}, {0x0, 0x0}}, + .corner_points = {{.red.custom_float_x = 0x16000, + .red.custom_float_y = 0x0, + .red.custom_float_slope = 0x1251c, + .green.custom_float_x = 0x16000, + .green.custom_float_y = 0x0, + .green.custom_float_slope = 0x1251c, + .blue.custom_float_x = 0x16000, + .blue.custom_float_y = 0x0, + .blue.custom_float_slope = 0x1251c}, + {.red.custom_float_x = 0x7c00, + .red.custom_float_y = 0x1f000, + .red.custom_float_slope = 0x0, + .green.custom_float_x = 0x7c00, + .green.custom_float_y = 0x1f000, + .green.custom_float_slope = 0x0, + .blue.custom_float_x = 0x7c00, + .blue.custom_float_y = 0x1f000, + .blue.custom_float_slope = 0x0}}, + .rgb_resulted = {{.red_reg = 0x951c, .green_reg = 0x951c, .blue_reg = 0x951c}, + {.red_reg = 0xbbdc, .green_reg = 0xbbdc, .blue_reg = 0xbbdc}, + {.red_reg = 0xe261, .green_reg = 0xe261, .blue_reg = 0xe261}, + {.red_reg = 0xf851, .green_reg = 0xf851, .blue_reg = 0xf851}, + {.red_reg = 0x10840, .green_reg = 0x10840, .blue_reg = 0x10840}, + {.red_reg = 0x114b7, .green_reg = 0x114b7, .blue_reg = 0x114b7}, + {.red_reg = 0x1200b, .green_reg = 0x1200b, .blue_reg = 0x1200b}, + {.red_reg = 0x12739, .green_reg = 0x12739, .blue_reg = 0x12739}, + {.red_reg = 0x13000, .green_reg = 0x13000, .blue_reg = 0x13000}, + {.red_reg = 0x1353a, .green_reg = 0x1353a, .blue_reg = 0x1353a}, + {.red_reg = 0x13b55, .green_reg = 0x13b55, .blue_reg = 0x13b55}, + {.red_reg = 0x1412e, .green_reg = 0x1412e, .blue_reg = 0x1412e}, + {.red_reg = 0x1452b, .green_reg = 0x1452b, .blue_reg = 0x1452b}, + {.red_reg = 0x149a7, .green_reg = 0x149a7, .blue_reg = 0x149a7}, + {.red_reg = 0x14ea5, .green_reg = 0x14ea5, .blue_reg = 0x14ea5}, + {.red_reg = 0x15215, .green_reg = 0x15215, .blue_reg = 0x15215}, + {.red_reg = 0x1551c, .green_reg = 0x1551c, .blue_reg = 0x1551c}, + {.red_reg = 0x1586b, .green_reg = 0x1586b, .blue_reg = 0x1586b}, + {.red_reg = 0x15c02, .green_reg = 0x15c02, .blue_reg = 0x15c02}, + {.red_reg = 0x15fe3, .green_reg = 0x15fe3, .blue_reg = 0x15fe3}, + {.red_reg = 0x16208, .green_reg = 0x16208, .blue_reg = 0x16208}, + {.red_reg = 0x16446, .green_reg = 0x16446, .blue_reg = 0x16446}, + {.red_reg = 0x166ab, .green_reg = 0x166ab, .blue_reg = 0x166ab}, + {.red_reg = 0x16938, .green_reg = 0x16938, .blue_reg = 0x16938}, + {.red_reg = 0x16bee, .green_reg = 0x16bee, .blue_reg = 0x16bee}, + {.red_reg = 0x16ece, .green_reg = 0x16ece, .blue_reg = 0x16ece}, + {.red_reg = 0x170ec, .green_reg = 0x170ec, .blue_reg = 0x170ec}, + {.red_reg = 0x17287, .green_reg = 0x17287, .blue_reg = 0x17287}, + {.red_reg = 0x17438, .green_reg = 0x17438, .blue_reg = 0x17438}, + {.red_reg = 0x175fe, .green_reg = 0x175fe, .blue_reg = 0x175fe}, + {.red_reg = 0x177dc, .green_reg = 0x177dc, .blue_reg = 0x177dc}, + {.red_reg = 0x179d0, .green_reg = 0x179d0, .blue_reg = 0x179d0}, + {.red_reg = 0x17bdb, .green_reg = 0x17bdb, .blue_reg = 0x17bdb}, + {.red_reg = 0x17dfe, .green_reg = 0x17dfe, .blue_reg = 0x17dfe}, + {.red_reg = 0x1801c, .green_reg = 0x1801c, .blue_reg = 0x1801c}, + {.red_reg = 0x18145, .green_reg = 0x18145, .blue_reg = 0x18145}, + {.red_reg = 0x1827a, .green_reg = 0x1827a, .blue_reg = 0x1827a}, + {.red_reg = 0x183bc, .green_reg = 0x183bc, .blue_reg = 0x183bc}, + {.red_reg = 0x1850a, .green_reg = 0x1850a, .blue_reg = 0x1850a}, + {.red_reg = 0x18664, .green_reg = 0x18664, .blue_reg = 0x18664}, + {.red_reg = 0x187cb, .green_reg = 0x187cb, .blue_reg = 0x187cb}, + {.red_reg = 0x1893f, .green_reg = 0x1893f, .blue_reg = 0x1893f}, + {.red_reg = 0x18ac0, .green_reg = 0x18ac0, .blue_reg = 0x18ac0}, + {.red_reg = 0x18c4e, .green_reg = 0x18c4e, .blue_reg = 0x18c4e}, + {.red_reg = 0x18de9, .green_reg = 0x18de9, .blue_reg = 0x18de9}, + {.red_reg = 0x18f91, .green_reg = 0x18f91, .blue_reg = 0x18f91}, + {.red_reg = 0x190a3, .green_reg = 0x190a3, .blue_reg = 0x190a3}, + {.red_reg = 0x19185, .green_reg = 0x19185, .blue_reg = 0x19185}, + {.red_reg = 0x1926d, .green_reg = 0x1926d, .blue_reg = 0x1926d}, + {.red_reg = 0x1935d, .green_reg = 0x1935d, .blue_reg = 0x1935d}, + {.red_reg = 0x19453, .green_reg = 0x19453, .blue_reg = 0x19453}, + {.red_reg = 0x19550, .green_reg = 0x19550, .blue_reg = 0x19550}, + {.red_reg = 0x19655, .green_reg = 0x19655, .blue_reg = 0x19655}, + {.red_reg = 0x19760, .green_reg = 0x19760, .blue_reg = 0x19760}, + {.red_reg = 0x19873, .green_reg = 0x19873, .blue_reg = 0x19873}, + {.red_reg = 0x1998c, .green_reg = 0x1998c, .blue_reg = 0x1998c}, + {.red_reg = 0x19aad, .green_reg = 0x19aad, .blue_reg = 0x19aad}, + {.red_reg = 0x19bd6, .green_reg = 0x19bd6, .blue_reg = 0x19bd6}, + {.red_reg = 0x19d06, .green_reg = 0x19d06, .blue_reg = 0x19d06}, + {.red_reg = 0x19e3d, .green_reg = 0x19e3d, .blue_reg = 0x19e3d}, + {.red_reg = 0x19f7b, .green_reg = 0x19f7b, .blue_reg = 0x19f7b}, + {.red_reg = 0x1a061, .green_reg = 0x1a061, .blue_reg = 0x1a061}, + {.red_reg = 0x1a107, .green_reg = 0x1a107, .blue_reg = 0x1a107}, + {.red_reg = 0x1a1b2, .green_reg = 0x1a1b2, .blue_reg = 0x1a1b2}, + {.red_reg = 0x1a261, .green_reg = 0x1a261, .blue_reg = 0x1a261}, + {.red_reg = 0x1a313, .green_reg = 0x1a313, .blue_reg = 0x1a313}, + {.red_reg = 0x1a3c9, .green_reg = 0x1a3c9, .blue_reg = 0x1a3c9}, + {.red_reg = 0x1a483, .green_reg = 0x1a483, .blue_reg = 0x1a483}, + {.red_reg = 0x1a541, .green_reg = 0x1a541, .blue_reg = 0x1a541}, + {.red_reg = 0x1a604, .green_reg = 0x1a604, .blue_reg = 0x1a604}, + {.red_reg = 0x1a6ca, .green_reg = 0x1a6ca, .blue_reg = 0x1a6ca}, + {.red_reg = 0x1a794, .green_reg = 0x1a794, .blue_reg = 0x1a794}, + {.red_reg = 0x1a862, .green_reg = 0x1a862, .blue_reg = 0x1a862}, + {.red_reg = 0x1a934, .green_reg = 0x1a934, .blue_reg = 0x1a934}, + {.red_reg = 0x1aa0a, .green_reg = 0x1aa0a, .blue_reg = 0x1aa0a}, + {.red_reg = 0x1aae4, .green_reg = 0x1aae4, .blue_reg = 0x1aae4}, + {.red_reg = 0x1abc3, .green_reg = 0x1abc3, .blue_reg = 0x1abc3}, + {.red_reg = 0x1aca5, .green_reg = 0x1aca5, .blue_reg = 0x1aca5}, + {.red_reg = 0x1ad8c, .green_reg = 0x1ad8c, .blue_reg = 0x1ad8c}, + {.red_reg = 0x1ae77, .green_reg = 0x1ae77, .blue_reg = 0x1ae77}, + {.red_reg = 0x1af66, .green_reg = 0x1af66, .blue_reg = 0x1af66}, + {.red_reg = 0x1b02c, .green_reg = 0x1b02c, .blue_reg = 0x1b02c}, + {.red_reg = 0x1b0a8, .green_reg = 0x1b0a8, .blue_reg = 0x1b0a8}, + {.red_reg = 0x1b126, .green_reg = 0x1b126, .blue_reg = 0x1b126}, + {.red_reg = 0x1b1a6, .green_reg = 0x1b1a6, .blue_reg = 0x1b1a6}, + {.red_reg = 0x1b228, .green_reg = 0x1b228, .blue_reg = 0x1b228}, + {.red_reg = 0x1b2ac, .green_reg = 0x1b2ac, .blue_reg = 0x1b2ac}, + {.red_reg = 0x1b333, .green_reg = 0x1b333, .blue_reg = 0x1b333}, + {.red_reg = 0x1b3bb, .green_reg = 0x1b3bb, .blue_reg = 0x1b3bb}, + {.red_reg = 0x1b446, .green_reg = 0x1b446, .blue_reg = 0x1b446}, + {.red_reg = 0x1b4d3, .green_reg = 0x1b4d3, .blue_reg = 0x1b4d3}, + {.red_reg = 0x1b563, .green_reg = 0x1b563, .blue_reg = 0x1b563}, + {.red_reg = 0x1b5f4, .green_reg = 0x1b5f4, .blue_reg = 0x1b5f4}, + {.red_reg = 0x1b688, .green_reg = 0x1b688, .blue_reg = 0x1b688}, + {.red_reg = 0x1b71e, .green_reg = 0x1b71e, .blue_reg = 0x1b71e}, + {.red_reg = 0x1b7b6, .green_reg = 0x1b7b6, .blue_reg = 0x1b7b6}, + {.red_reg = 0x1b851, .green_reg = 0x1b851, .blue_reg = 0x1b851}, + {.red_reg = 0x1b8ed, .green_reg = 0x1b8ed, .blue_reg = 0x1b8ed}, + {.red_reg = 0x1b98d, .green_reg = 0x1b98d, .blue_reg = 0x1b98d}, + {.red_reg = 0x1ba2e, .green_reg = 0x1ba2e, .blue_reg = 0x1ba2e}, + {.red_reg = 0x1bad2, .green_reg = 0x1bad2, .blue_reg = 0x1bad2}, + {.red_reg = 0x1bb77, .green_reg = 0x1bb77, .blue_reg = 0x1bb77}, + {.red_reg = 0x1bc20, .green_reg = 0x1bc20, .blue_reg = 0x1bc20}, + {.red_reg = 0x1bcca, .green_reg = 0x1bcca, .blue_reg = 0x1bcca}, + {.red_reg = 0x1bd77, .green_reg = 0x1bd77, .blue_reg = 0x1bd77}, + {.red_reg = 0x1be26, .green_reg = 0x1be26, .blue_reg = 0x1be26}, + {.red_reg = 0x1bed8, .green_reg = 0x1bed8, .blue_reg = 0x1bed8}, + {.red_reg = 0x1bf8c, .green_reg = 0x1bf8c, .blue_reg = 0x1bf8c}, + {.red_reg = 0x1c021, .green_reg = 0x1c021, .blue_reg = 0x1c021}, + {.red_reg = 0x1c07d, .green_reg = 0x1c07d, .blue_reg = 0x1c07d}, + {.red_reg = 0x1c0db, .green_reg = 0x1c0db, .blue_reg = 0x1c0db}, + {.red_reg = 0x1c13a, .green_reg = 0x1c13a, .blue_reg = 0x1c13a}, + {.red_reg = 0x1c19a, .green_reg = 0x1c19a, .blue_reg = 0x1c19a}, + {.red_reg = 0x1c1fb, .green_reg = 0x1c1fb, .blue_reg = 0x1c1fb}, + {.red_reg = 0x1c25d, .green_reg = 0x1c25d, .blue_reg = 0x1c25d}, + {.red_reg = 0x1c2c1, .green_reg = 0x1c2c1, .blue_reg = 0x1c2c1}, + {.red_reg = 0x1c325, .green_reg = 0x1c325, .blue_reg = 0x1c325}, + {.red_reg = 0x1c38c, .green_reg = 0x1c38c, .blue_reg = 0x1c38c}, + {.red_reg = 0x1c3f3, .green_reg = 0x1c3f3, .blue_reg = 0x1c3f3}, + {.red_reg = 0x1c45b, .green_reg = 0x1c45b, .blue_reg = 0x1c45b}, + {.red_reg = 0x1c4c5, .green_reg = 0x1c4c5, .blue_reg = 0x1c4c5}, + {.red_reg = 0x1c530, .green_reg = 0x1c530, .blue_reg = 0x1c530}, + {.red_reg = 0x1c59c, .green_reg = 0x1c59c, .blue_reg = 0x1c59c}, + {.red_reg = 0x1c60a, .green_reg = 0x1c60a, .blue_reg = 0x1c60a}, + {.red_reg = 0x1c678, .green_reg = 0x1c678, .blue_reg = 0x1c678}, + {.red_reg = 0x1c6e8, .green_reg = 0x1c6e8, .blue_reg = 0x1c6e8}, + {.red_reg = 0x1c75a, .green_reg = 0x1c75a, .blue_reg = 0x1c75a}, + {.red_reg = 0x1c7cc, .green_reg = 0x1c7cc, .blue_reg = 0x1c7cc}, + {.red_reg = 0x1c840, .green_reg = 0x1c840, .blue_reg = 0x1c840}, + {.red_reg = 0x1c8b5, .green_reg = 0x1c8b5, .blue_reg = 0x1c8b5}, + {.red_reg = 0x1c92b, .green_reg = 0x1c92b, .blue_reg = 0x1c92b}, + {.red_reg = 0x1c9a3, .green_reg = 0x1c9a3, .blue_reg = 0x1c9a3}, + {.red_reg = 0x1ca1c, .green_reg = 0x1ca1c, .blue_reg = 0x1ca1c}, + {.red_reg = 0x1ca96, .green_reg = 0x1ca96, .blue_reg = 0x1ca96}, + {.red_reg = 0x1cb11, .green_reg = 0x1cb11, .blue_reg = 0x1cb11}, + {.red_reg = 0x1cb8e, .green_reg = 0x1cb8e, .blue_reg = 0x1cb8e}, + {.red_reg = 0x1cc0c, .green_reg = 0x1cc0c, .blue_reg = 0x1cc0c}, + {.red_reg = 0x1cc8c, .green_reg = 0x1cc8c, .blue_reg = 0x1cc8c}, + {.red_reg = 0x1cd0c, .green_reg = 0x1cd0c, .blue_reg = 0x1cd0c}, + {.red_reg = 0x1cd8e, .green_reg = 0x1cd8e, .blue_reg = 0x1cd8e}, + {.red_reg = 0x1ce12, .green_reg = 0x1ce12, .blue_reg = 0x1ce12}, + {.red_reg = 0x1ce96, .green_reg = 0x1ce96, .blue_reg = 0x1ce96}, + {.red_reg = 0x1cf1c, .green_reg = 0x1cf1c, .blue_reg = 0x1cf1c}, + {.red_reg = 0x1cfa3, .green_reg = 0x1cfa3, .blue_reg = 0x1cfa3}, + {.red_reg = 0x1d016, .green_reg = 0x1d016, .blue_reg = 0x1d016}, + {.red_reg = 0x1d05b, .green_reg = 0x1d05b, .blue_reg = 0x1d05b}, + {.red_reg = 0x1d0a0, .green_reg = 0x1d0a0, .blue_reg = 0x1d0a0}, + {.red_reg = 0x1d0e7, .green_reg = 0x1d0e7, .blue_reg = 0x1d0e7}, + {.red_reg = 0x1d12e, .green_reg = 0x1d12e, .blue_reg = 0x1d12e}, + {.red_reg = 0x1d175, .green_reg = 0x1d175, .blue_reg = 0x1d175}, + {.red_reg = 0x1d1be, .green_reg = 0x1d1be, .blue_reg = 0x1d1be}, + {.red_reg = 0x1d207, .green_reg = 0x1d207, .blue_reg = 0x1d207}, + {.red_reg = 0x1d250, .green_reg = 0x1d250, .blue_reg = 0x1d250}, + {.red_reg = 0x1d29b, .green_reg = 0x1d29b, .blue_reg = 0x1d29b}, + {.red_reg = 0x1d2e6, .green_reg = 0x1d2e6, .blue_reg = 0x1d2e6}, + {.red_reg = 0x1d332, .green_reg = 0x1d332, .blue_reg = 0x1d332}, + {.red_reg = 0x1d37e, .green_reg = 0x1d37e, .blue_reg = 0x1d37e}, + {.red_reg = 0x1d3cb, .green_reg = 0x1d3cb, .blue_reg = 0x1d3cb}, + {.red_reg = 0x1d419, .green_reg = 0x1d419, .blue_reg = 0x1d419}, + {.red_reg = 0x1d467, .green_reg = 0x1d467, .blue_reg = 0x1d467}, + {.red_reg = 0x1d4b7, .green_reg = 0x1d4b7, .blue_reg = 0x1d4b7}, + {.red_reg = 0x1d507, .green_reg = 0x1d507, .blue_reg = 0x1d507}, + {.red_reg = 0x1d557, .green_reg = 0x1d557, .blue_reg = 0x1d557}, + {.red_reg = 0x1d5a8, .green_reg = 0x1d5a8, .blue_reg = 0x1d5a8}, + {.red_reg = 0x1d5fa, .green_reg = 0x1d5fa, .blue_reg = 0x1d5fa}, + {.red_reg = 0x1d64d, .green_reg = 0x1d64d, .blue_reg = 0x1d64d}, + {.red_reg = 0x1d6a0, .green_reg = 0x1d6a0, .blue_reg = 0x1d6a0}, + {.red_reg = 0x1d6f5, .green_reg = 0x1d6f5, .blue_reg = 0x1d6f5}, + {.red_reg = 0x1d749, .green_reg = 0x1d749, .blue_reg = 0x1d749}, + {.red_reg = 0x1d79f, .green_reg = 0x1d79f, .blue_reg = 0x1d79f}, + {.red_reg = 0x1d7f5, .green_reg = 0x1d7f5, .blue_reg = 0x1d7f5}, + {.red_reg = 0x1d84c, .green_reg = 0x1d84c, .blue_reg = 0x1d84c}, + {.red_reg = 0x1d8a4, .green_reg = 0x1d8a4, .blue_reg = 0x1d8a4}, + {.red_reg = 0x1d8fc, .green_reg = 0x1d8fc, .blue_reg = 0x1d8fc}, + {.red_reg = 0x1d955, .green_reg = 0x1d955, .blue_reg = 0x1d955}, + {.red_reg = 0x1d9af, .green_reg = 0x1d9af, .blue_reg = 0x1d9af}, + {.red_reg = 0x1da0a, .green_reg = 0x1da0a, .blue_reg = 0x1da0a}, + {.red_reg = 0x1da65, .green_reg = 0x1da65, .blue_reg = 0x1da65}, + {.red_reg = 0x1dac1, .green_reg = 0x1dac1, .blue_reg = 0x1dac1}, + {.red_reg = 0x1db1e, .green_reg = 0x1db1e, .blue_reg = 0x1db1e}, + {.red_reg = 0x1db7b, .green_reg = 0x1db7b, .blue_reg = 0x1db7b}, + {.red_reg = 0x1dbd9, .green_reg = 0x1dbd9, .blue_reg = 0x1dbd9}, + {.red_reg = 0x1dc38, .green_reg = 0x1dc38, .blue_reg = 0x1dc38}, + {.red_reg = 0x1dc98, .green_reg = 0x1dc98, .blue_reg = 0x1dc98}, + {.red_reg = 0x1dcf8, .green_reg = 0x1dcf8, .blue_reg = 0x1dcf8}, + {.red_reg = 0x1dd59, .green_reg = 0x1dd59, .blue_reg = 0x1dd59}, + {.red_reg = 0x1ddbb, .green_reg = 0x1ddbb, .blue_reg = 0x1ddbb}, + {.red_reg = 0x1de1e, .green_reg = 0x1de1e, .blue_reg = 0x1de1e}, + {.red_reg = 0x1de81, .green_reg = 0x1de81, .blue_reg = 0x1de81}, + {.red_reg = 0x1dee5, .green_reg = 0x1dee5, .blue_reg = 0x1dee5}, + {.red_reg = 0x1df4a, .green_reg = 0x1df4a, .blue_reg = 0x1df4a}, + {.red_reg = 0x1dfaf, .green_reg = 0x1dfaf, .blue_reg = 0x1dfaf}, + {.red_reg = 0x1e00b, .green_reg = 0x1e00b, .blue_reg = 0x1e00b}, + {.red_reg = 0x1e03e, .green_reg = 0x1e03e, .blue_reg = 0x1e03e}, + {.red_reg = 0x1e072, .green_reg = 0x1e072, .blue_reg = 0x1e072}, + {.red_reg = 0x1e0a6, .green_reg = 0x1e0a6, .blue_reg = 0x1e0a6}, + {.red_reg = 0x1e0db, .green_reg = 0x1e0db, .blue_reg = 0x1e0db}, + {.red_reg = 0x1e110, .green_reg = 0x1e110, .blue_reg = 0x1e110}, + {.red_reg = 0x1e145, .green_reg = 0x1e145, .blue_reg = 0x1e145}, + {.red_reg = 0x1e17b, .green_reg = 0x1e17b, .blue_reg = 0x1e17b}, + {.red_reg = 0x1e1b1, .green_reg = 0x1e1b1, .blue_reg = 0x1e1b1}, + {.red_reg = 0x1e1e8, .green_reg = 0x1e1e8, .blue_reg = 0x1e1e8}, + {.red_reg = 0x1e21f, .green_reg = 0x1e21f, .blue_reg = 0x1e21f}, + {.red_reg = 0x1e256, .green_reg = 0x1e256, .blue_reg = 0x1e256}, + {.red_reg = 0x1e28e, .green_reg = 0x1e28e, .blue_reg = 0x1e28e}, + {.red_reg = 0x1e2c6, .green_reg = 0x1e2c6, .blue_reg = 0x1e2c6}, + {.red_reg = 0x1e2fe, .green_reg = 0x1e2fe, .blue_reg = 0x1e2fe}, + {.red_reg = 0x1e337, .green_reg = 0x1e337, .blue_reg = 0x1e337}, + {.red_reg = 0x1e370, .green_reg = 0x1e370, .blue_reg = 0x1e370}, + {.red_reg = 0x1e3aa, .green_reg = 0x1e3aa, .blue_reg = 0x1e3aa}, + {.red_reg = 0x1e3e4, .green_reg = 0x1e3e4, .blue_reg = 0x1e3e4}, + {.red_reg = 0x1e41f, .green_reg = 0x1e41f, .blue_reg = 0x1e41f}, + {.red_reg = 0x1e459, .green_reg = 0x1e459, .blue_reg = 0x1e459}, + {.red_reg = 0x1e494, .green_reg = 0x1e494, .blue_reg = 0x1e494}, + {.red_reg = 0x1e4d0, .green_reg = 0x1e4d0, .blue_reg = 0x1e4d0}, + {.red_reg = 0x1e50c, .green_reg = 0x1e50c, .blue_reg = 0x1e50c}, + {.red_reg = 0x1e548, .green_reg = 0x1e548, .blue_reg = 0x1e548}, + {.red_reg = 0x1e585, .green_reg = 0x1e585, .blue_reg = 0x1e585}, + {.red_reg = 0x1e5c2, .green_reg = 0x1e5c2, .blue_reg = 0x1e5c2}, + {.red_reg = 0x1e600, .green_reg = 0x1e600, .blue_reg = 0x1e600}, + {.red_reg = 0x1e63e, .green_reg = 0x1e63e, .blue_reg = 0x1e63e}, + {.red_reg = 0x1e67c, .green_reg = 0x1e67c, .blue_reg = 0x1e67c}, + {.red_reg = 0x1e6bb, .green_reg = 0x1e6bb, .blue_reg = 0x1e6bb}, + {.red_reg = 0x1e6fa, .green_reg = 0x1e6fa, .blue_reg = 0x1e6fa}, + {.red_reg = 0x1e739, .green_reg = 0x1e739, .blue_reg = 0x1e739}, + {.red_reg = 0x1e779, .green_reg = 0x1e779, .blue_reg = 0x1e779}, + {.red_reg = 0x1e7b9, .green_reg = 0x1e7b9, .blue_reg = 0x1e7b9}, + {.red_reg = 0x1e7fa, .green_reg = 0x1e7fa, .blue_reg = 0x1e7fa}, + {.red_reg = 0x1e83b, .green_reg = 0x1e83b, .blue_reg = 0x1e83b}, + {.red_reg = 0x1e87d, .green_reg = 0x1e87d, .blue_reg = 0x1e87d}, + {.red_reg = 0x1e8bf, .green_reg = 0x1e8bf, .blue_reg = 0x1e8bf}, + {.red_reg = 0x1e901, .green_reg = 0x1e901, .blue_reg = 0x1e901}, + {.red_reg = 0x1e944, .green_reg = 0x1e944, .blue_reg = 0x1e944}, + {.red_reg = 0x1e987, .green_reg = 0x1e987, .blue_reg = 0x1e987}, + {.red_reg = 0x1e9ca, .green_reg = 0x1e9ca, .blue_reg = 0x1e9ca}, + {.red_reg = 0x1ea0e, .green_reg = 0x1ea0e, .blue_reg = 0x1ea0e}, + {.red_reg = 0x1ea53, .green_reg = 0x1ea53, .blue_reg = 0x1ea53}, + {.red_reg = 0x1ea97, .green_reg = 0x1ea97, .blue_reg = 0x1ea97}, + {.red_reg = 0x1eadc, .green_reg = 0x1eadc, .blue_reg = 0x1eadc}, + {.red_reg = 0x1eb22, .green_reg = 0x1eb22, .blue_reg = 0x1eb22}, + {.red_reg = 0x1eb68, .green_reg = 0x1eb68, .blue_reg = 0x1eb68}, + {.red_reg = 0x1ebae, .green_reg = 0x1ebae, .blue_reg = 0x1ebae}, + {.red_reg = 0x1ebf5, .green_reg = 0x1ebf5, .blue_reg = 0x1ebf5}, + {.red_reg = 0x1ec3c, .green_reg = 0x1ec3c, .blue_reg = 0x1ec3c}, + {.red_reg = 0x1ec84, .green_reg = 0x1ec84, .blue_reg = 0x1ec84}, + {.red_reg = 0x1eccc, .green_reg = 0x1eccc, .blue_reg = 0x1eccc}, + {.red_reg = 0x1ed14, .green_reg = 0x1ed14, .blue_reg = 0x1ed14}, + {.red_reg = 0x1ed5d, .green_reg = 0x1ed5d, .blue_reg = 0x1ed5d}, + {.red_reg = 0x1eda6, .green_reg = 0x1eda6, .blue_reg = 0x1eda6}, + {.red_reg = 0x1edf0, .green_reg = 0x1edf0, .blue_reg = 0x1edf0}, + {.red_reg = 0x1ee3a, .green_reg = 0x1ee3a, .blue_reg = 0x1ee3a}, + {.red_reg = 0x1ee85, .green_reg = 0x1ee85, .blue_reg = 0x1ee85}, + {.red_reg = 0x1eed0, .green_reg = 0x1eed0, .blue_reg = 0x1eed0}, + {.red_reg = 0x1ef1b, .green_reg = 0x1ef1b, .blue_reg = 0x1ef1b}, + {.red_reg = 0x1ef67, .green_reg = 0x1ef67, .blue_reg = 0x1ef67}, + {.red_reg = 0x1efb3, .green_reg = 0x1efb3, .blue_reg = 0x1efb3}, + {.red_reg = 0x1f000, .green_reg = 0x1f000, .blue_reg = 0x1f000}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}}}, + {.hw_points_num = NUM_OF_LUT_DATA_DEGAM, + .arr_curve_points = {{0x0, 0x0}, {0x1, 0x0}, {0x2, 0x1}, {0x4, 0x2}, {0x8, 0x3}, + {0x10, 0x4}, {0x20, 0x5}, {0x40, 0x6}, {0x80, 0x7}, {0x0, 0x0}, {0x0, 0x0}, + {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, + {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, + {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, + {0x0, 0x0}, {0x0, 0x0}}, + .corner_points = {{.red.custom_float_x = 0x16000, + .red.custom_float_y = 0x0, + .red.custom_float_slope = 0xdc00, + .green.custom_float_x = 0x16000, + .green.custom_float_y = 0x0, + .green.custom_float_slope = 0xdc00, + .blue.custom_float_x = 0x16000, + .blue.custom_float_y = 0x0, + .blue.custom_float_slope = 0xdc00}, + {.red.custom_float_x = 0x7c00, + .red.custom_float_y = 0x1f000, + .red.custom_float_slope = 0x0, + .green.custom_float_x = 0x7c00, + .green.custom_float_y = 0x1f000, + .green.custom_float_slope = 0x0, + .blue.custom_float_x = 0x7c00, + .blue.custom_float_y = 0x1f000, + .blue.custom_float_slope = 0x0}}, + .rgb_resulted = {{.red_reg = 0x4c00, .green_reg = 0x4c00, .blue_reg = 0x4c00}, + {.red_reg = 0x6720, .green_reg = 0x6720, .blue_reg = 0x6720}, + {.red_reg = 0x83c0, .green_reg = 0x83c0, .blue_reg = 0x83c0}, + {.red_reg = 0x94d0, .green_reg = 0x94d0, .blue_reg = 0x94d0}, + {.red_reg = 0xa1f8, .green_reg = 0xa1f8, .blue_reg = 0xa1f8}, + {.red_reg = 0xabc4, .green_reg = 0xabc4, .blue_reg = 0xabc4}, + {.red_reg = 0xb3fa, .green_reg = 0xb3fa, .blue_reg = 0xb3fa}, + {.red_reg = 0xbb5c, .green_reg = 0xbb5c, .blue_reg = 0xbb5c}, + {.red_reg = 0xc20f, .green_reg = 0xc20f, .blue_reg = 0xc20f}, + {.red_reg = 0xc72e, .green_reg = 0xc72e, .blue_reg = 0xc72e}, + {.red_reg = 0xcd18, .green_reg = 0xcd18, .blue_reg = 0xcd18}, + {.red_reg = 0xd1ed, .green_reg = 0xd1ed, .blue_reg = 0xd1ed}, + {.red_reg = 0xd5c1, .green_reg = 0xd5c1, .blue_reg = 0xd5c1}, + {.red_reg = 0xda11, .green_reg = 0xda11, .blue_reg = 0xda11}, + {.red_reg = 0xdee4, .green_reg = 0xdee4, .blue_reg = 0xdee4}, + {.red_reg = 0xe221, .green_reg = 0xe221, .blue_reg = 0xe221}, + {.red_reg = 0xe51a, .green_reg = 0xe51a, .blue_reg = 0xe51a}, + {.red_reg = 0xe861, .green_reg = 0xe861, .blue_reg = 0xe861}, + {.red_reg = 0xebfb, .green_reg = 0xebfb, .blue_reg = 0xebfb}, + {.red_reg = 0xefed, .green_reg = 0xefed, .blue_reg = 0xefed}, + {.red_reg = 0xf21e, .green_reg = 0xf21e, .blue_reg = 0xf21e}, + {.red_reg = 0xf476, .green_reg = 0xf476, .blue_reg = 0xf476}, + {.red_reg = 0xf702, .green_reg = 0xf702, .blue_reg = 0xf702}, + {.red_reg = 0xf9c5, .green_reg = 0xf9c5, .blue_reg = 0xf9c5}, + {.red_reg = 0xfcc2, .green_reg = 0xfcc2, .blue_reg = 0xfcc2}, + {.red_reg = 0xfffb, .green_reg = 0xfffb, .blue_reg = 0xfffb}, + {.red_reg = 0x101b9, .green_reg = 0x101b9, .blue_reg = 0x101b9}, + {.red_reg = 0x10397, .green_reg = 0x10397, .blue_reg = 0x10397}, + {.red_reg = 0x10599, .green_reg = 0x10599, .blue_reg = 0x10599}, + {.red_reg = 0x107bf, .green_reg = 0x107bf, .blue_reg = 0x107bf}, + {.red_reg = 0x10a0c, .green_reg = 0x10a0c, .blue_reg = 0x10a0c}, + {.red_reg = 0x10c82, .green_reg = 0x10c82, .blue_reg = 0x10c82}, + {.red_reg = 0x10f23, .green_reg = 0x10f23, .blue_reg = 0x10f23}, + {.red_reg = 0x110f8, .green_reg = 0x110f8, .blue_reg = 0x110f8}, + {.red_reg = 0x11276, .green_reg = 0x11276, .blue_reg = 0x11276}, + {.red_reg = 0x1140d, .green_reg = 0x1140d, .blue_reg = 0x1140d}, + {.red_reg = 0x115be, .green_reg = 0x115be, .blue_reg = 0x115be}, + {.red_reg = 0x1178a, .green_reg = 0x1178a, .blue_reg = 0x1178a}, + {.red_reg = 0x11972, .green_reg = 0x11972, .blue_reg = 0x11972}, + {.red_reg = 0x11b78, .green_reg = 0x11b78, .blue_reg = 0x11b78}, + {.red_reg = 0x11d9c, .green_reg = 0x11d9c, .blue_reg = 0x11d9c}, + {.red_reg = 0x11fe1, .green_reg = 0x11fe1, .blue_reg = 0x11fe1}, + {.red_reg = 0x12124, .green_reg = 0x12124, .blue_reg = 0x12124}, + {.red_reg = 0x12269, .green_reg = 0x12269, .blue_reg = 0x12269}, + {.red_reg = 0x123c0, .green_reg = 0x123c0, .blue_reg = 0x123c0}, + {.red_reg = 0x1252b, .green_reg = 0x1252b, .blue_reg = 0x1252b}, + {.red_reg = 0x126aa, .green_reg = 0x126aa, .blue_reg = 0x126aa}, + {.red_reg = 0x1283d, .green_reg = 0x1283d, .blue_reg = 0x1283d}, + {.red_reg = 0x129e7, .green_reg = 0x129e7, .blue_reg = 0x129e7}, + {.red_reg = 0x12ba7, .green_reg = 0x12ba7, .blue_reg = 0x12ba7}, + {.red_reg = 0x12d7f, .green_reg = 0x12d7f, .blue_reg = 0x12d7f}, + {.red_reg = 0x12f70, .green_reg = 0x12f70, .blue_reg = 0x12f70}, + {.red_reg = 0x130bd, .green_reg = 0x130bd, .blue_reg = 0x130bd}, + {.red_reg = 0x131d0, .green_reg = 0x131d0, .blue_reg = 0x131d0}, + {.red_reg = 0x132f1, .green_reg = 0x132f1, .blue_reg = 0x132f1}, + {.red_reg = 0x13420, .green_reg = 0x13420, .blue_reg = 0x13420}, + {.red_reg = 0x1355f, .green_reg = 0x1355f, .blue_reg = 0x1355f}, + {.red_reg = 0x136ad, .green_reg = 0x136ad, .blue_reg = 0x136ad}, + {.red_reg = 0x1380c, .green_reg = 0x1380c, .blue_reg = 0x1380c}, + {.red_reg = 0x1397c, .green_reg = 0x1397c, .blue_reg = 0x1397c}, + {.red_reg = 0x13afe, .green_reg = 0x13afe, .blue_reg = 0x13afe}, + {.red_reg = 0x13c93, .green_reg = 0x13c93, .blue_reg = 0x13c93}, + {.red_reg = 0x13e3a, .green_reg = 0x13e3a, .blue_reg = 0x13e3a}, + {.red_reg = 0x13ff6, .green_reg = 0x13ff6, .blue_reg = 0x13ff6}, + {.red_reg = 0x140e3, .green_reg = 0x140e3, .blue_reg = 0x140e3}, + {.red_reg = 0x141d6, .green_reg = 0x141d6, .blue_reg = 0x141d6}, + {.red_reg = 0x142d5, .green_reg = 0x142d5, .blue_reg = 0x142d5}, + {.red_reg = 0x143df, .green_reg = 0x143df, .blue_reg = 0x143df}, + {.red_reg = 0x144f5, .green_reg = 0x144f5, .blue_reg = 0x144f5}, + {.red_reg = 0x14618, .green_reg = 0x14618, .blue_reg = 0x14618}, + {.red_reg = 0x14749, .green_reg = 0x14749, .blue_reg = 0x14749}, + {.red_reg = 0x14887, .green_reg = 0x14887, .blue_reg = 0x14887}, + {.red_reg = 0x149d3, .green_reg = 0x149d3, .blue_reg = 0x149d3}, + {.red_reg = 0x14b2d, .green_reg = 0x14b2d, .blue_reg = 0x14b2d}, + {.red_reg = 0x14c98, .green_reg = 0x14c98, .blue_reg = 0x14c98}, + {.red_reg = 0x14e12, .green_reg = 0x14e12, .blue_reg = 0x14e12}, + {.red_reg = 0x14f9c, .green_reg = 0x14f9c, .blue_reg = 0x14f9c}, + {.red_reg = 0x1509c, .green_reg = 0x1509c, .blue_reg = 0x1509c}, + {.red_reg = 0x15172, .green_reg = 0x15172, .blue_reg = 0x15172}, + {.red_reg = 0x15252, .green_reg = 0x15252, .blue_reg = 0x15252}, + {.red_reg = 0x1533c, .green_reg = 0x1533c, .blue_reg = 0x1533c}, + {.red_reg = 0x15430, .green_reg = 0x15430, .blue_reg = 0x15430}, + {.red_reg = 0x1552d, .green_reg = 0x1552d, .blue_reg = 0x1552d}, + {.red_reg = 0x15636, .green_reg = 0x15636, .blue_reg = 0x15636}, + {.red_reg = 0x1574a, .green_reg = 0x1574a, .blue_reg = 0x1574a}, + {.red_reg = 0x15869, .green_reg = 0x15869, .blue_reg = 0x15869}, + {.red_reg = 0x15994, .green_reg = 0x15994, .blue_reg = 0x15994}, + {.red_reg = 0x15acc, .green_reg = 0x15acc, .blue_reg = 0x15acc}, + {.red_reg = 0x15c10, .green_reg = 0x15c10, .blue_reg = 0x15c10}, + {.red_reg = 0x15d62, .green_reg = 0x15d62, .blue_reg = 0x15d62}, + {.red_reg = 0x15ec1, .green_reg = 0x15ec1, .blue_reg = 0x15ec1}, + {.red_reg = 0x16017, .green_reg = 0x16017, .blue_reg = 0x16017}, + {.red_reg = 0x160d6, .green_reg = 0x160d6, .blue_reg = 0x160d6}, + {.red_reg = 0x1619c, .green_reg = 0x1619c, .blue_reg = 0x1619c}, + {.red_reg = 0x1626a, .green_reg = 0x1626a, .blue_reg = 0x1626a}, + {.red_reg = 0x16341, .green_reg = 0x16341, .blue_reg = 0x16341}, + {.red_reg = 0x16420, .green_reg = 0x16420, .blue_reg = 0x16420}, + {.red_reg = 0x16508, .green_reg = 0x16508, .blue_reg = 0x16508}, + {.red_reg = 0x165f9, .green_reg = 0x165f9, .blue_reg = 0x165f9}, + {.red_reg = 0x166f3, .green_reg = 0x166f3, .blue_reg = 0x166f3}, + {.red_reg = 0x167f8, .green_reg = 0x167f8, .blue_reg = 0x167f8}, + {.red_reg = 0x16907, .green_reg = 0x16907, .blue_reg = 0x16907}, + {.red_reg = 0x16a21, .green_reg = 0x16a21, .blue_reg = 0x16a21}, + {.red_reg = 0x16b45, .green_reg = 0x16b45, .blue_reg = 0x16b45}, + {.red_reg = 0x16c75, .green_reg = 0x16c75, .blue_reg = 0x16c75}, + {.red_reg = 0x16db1, .green_reg = 0x16db1, .blue_reg = 0x16db1}, + {.red_reg = 0x16ef9, .green_reg = 0x16ef9, .blue_reg = 0x16ef9}, + {.red_reg = 0x17027, .green_reg = 0x17027, .blue_reg = 0x17027}, + {.red_reg = 0x170d8, .green_reg = 0x170d8, .blue_reg = 0x170d8}, + {.red_reg = 0x17190, .green_reg = 0x17190, .blue_reg = 0x17190}, + {.red_reg = 0x1724f, .green_reg = 0x1724f, .blue_reg = 0x1724f}, + {.red_reg = 0x17315, .green_reg = 0x17315, .blue_reg = 0x17315}, + {.red_reg = 0x173e3, .green_reg = 0x173e3, .blue_reg = 0x173e3}, + {.red_reg = 0x174b9, .green_reg = 0x174b9, .blue_reg = 0x174b9}, + {.red_reg = 0x17597, .green_reg = 0x17597, .blue_reg = 0x17597}, + {.red_reg = 0x1767d, .green_reg = 0x1767d, .blue_reg = 0x1767d}, + {.red_reg = 0x1776c, .green_reg = 0x1776c, .blue_reg = 0x1776c}, + {.red_reg = 0x17864, .green_reg = 0x17864, .blue_reg = 0x17864}, + {.red_reg = 0x17966, .green_reg = 0x17966, .blue_reg = 0x17966}, + {.red_reg = 0x17a71, .green_reg = 0x17a71, .blue_reg = 0x17a71}, + {.red_reg = 0x17b86, .green_reg = 0x17b86, .blue_reg = 0x17b86}, + {.red_reg = 0x17ca6, .green_reg = 0x17ca6, .blue_reg = 0x17ca6}, + {.red_reg = 0x17dd0, .green_reg = 0x17dd0, .blue_reg = 0x17dd0}, + {.red_reg = 0x17f06, .green_reg = 0x17f06, .blue_reg = 0x17f06}, + {.red_reg = 0x18023, .green_reg = 0x18023, .blue_reg = 0x18023}, + {.red_reg = 0x180ca, .green_reg = 0x180ca, .blue_reg = 0x180ca}, + {.red_reg = 0x18177, .green_reg = 0x18177, .blue_reg = 0x18177}, + {.red_reg = 0x1822a, .green_reg = 0x1822a, .blue_reg = 0x1822a}, + {.red_reg = 0x182e4, .green_reg = 0x182e4, .blue_reg = 0x182e4}, + {.red_reg = 0x183a5, .green_reg = 0x183a5, .blue_reg = 0x183a5}, + {.red_reg = 0x1846d, .green_reg = 0x1846d, .blue_reg = 0x1846d}, + {.red_reg = 0x1853c, .green_reg = 0x1853c, .blue_reg = 0x1853c}, + {.red_reg = 0x18613, .green_reg = 0x18613, .blue_reg = 0x18613}, + {.red_reg = 0x186f2, .green_reg = 0x186f2, .blue_reg = 0x186f2}, + {.red_reg = 0x187d9, .green_reg = 0x187d9, .blue_reg = 0x187d9}, + {.red_reg = 0x188c8, .green_reg = 0x188c8, .blue_reg = 0x188c8}, + {.red_reg = 0x189c1, .green_reg = 0x189c1, .blue_reg = 0x189c1}, + {.red_reg = 0x18ac2, .green_reg = 0x18ac2, .blue_reg = 0x18ac2}, + {.red_reg = 0x18bcd, .green_reg = 0x18bcd, .blue_reg = 0x18bcd}, + {.red_reg = 0x18ce2, .green_reg = 0x18ce2, .blue_reg = 0x18ce2}, + {.red_reg = 0x18e00, .green_reg = 0x18e00, .blue_reg = 0x18e00}, + {.red_reg = 0x18f2a, .green_reg = 0x18f2a, .blue_reg = 0x18f2a}, + {.red_reg = 0x1902f, .green_reg = 0x1902f, .blue_reg = 0x1902f}, + {.red_reg = 0x190ce, .green_reg = 0x190ce, .blue_reg = 0x190ce}, + {.red_reg = 0x19174, .green_reg = 0x19174, .blue_reg = 0x19174}, + {.red_reg = 0x1921f, .green_reg = 0x1921f, .blue_reg = 0x1921f}, + {.red_reg = 0x192d1, .green_reg = 0x192d1, .blue_reg = 0x192d1}, + {.red_reg = 0x19389, .green_reg = 0x19389, .blue_reg = 0x19389}, + {.red_reg = 0x19448, .green_reg = 0x19448, .blue_reg = 0x19448}, + {.red_reg = 0x1950e, .green_reg = 0x1950e, .blue_reg = 0x1950e}, + {.red_reg = 0x195db, .green_reg = 0x195db, .blue_reg = 0x195db}, + {.red_reg = 0x196af, .green_reg = 0x196af, .blue_reg = 0x196af}, + {.red_reg = 0x1978b, .green_reg = 0x1978b, .blue_reg = 0x1978b}, + {.red_reg = 0x1986f, .green_reg = 0x1986f, .blue_reg = 0x1986f}, + {.red_reg = 0x1995b, .green_reg = 0x1995b, .blue_reg = 0x1995b}, + {.red_reg = 0x19a50, .green_reg = 0x19a50, .blue_reg = 0x19a50}, + {.red_reg = 0x19b4e, .green_reg = 0x19b4e, .blue_reg = 0x19b4e}, + {.red_reg = 0x19c55, .green_reg = 0x19c55, .blue_reg = 0x19c55}, + {.red_reg = 0x19d65, .green_reg = 0x19d65, .blue_reg = 0x19d65}, + {.red_reg = 0x19e7f, .green_reg = 0x19e7f, .blue_reg = 0x19e7f}, + {.red_reg = 0x19fa3, .green_reg = 0x19fa3, .blue_reg = 0x19fa3}, + {.red_reg = 0x1a069, .green_reg = 0x1a069, .blue_reg = 0x1a069}, + {.red_reg = 0x1a106, .green_reg = 0x1a106, .blue_reg = 0x1a106}, + {.red_reg = 0x1a1a8, .green_reg = 0x1a1a8, .blue_reg = 0x1a1a8}, + {.red_reg = 0x1a251, .green_reg = 0x1a251, .blue_reg = 0x1a251}, + {.red_reg = 0x1a2ff, .green_reg = 0x1a2ff, .blue_reg = 0x1a2ff}, + {.red_reg = 0x1a3b4, .green_reg = 0x1a3b4, .blue_reg = 0x1a3b4}, + {.red_reg = 0x1a46f, .green_reg = 0x1a46f, .blue_reg = 0x1a46f}, + {.red_reg = 0x1a531, .green_reg = 0x1a531, .blue_reg = 0x1a531}, + {.red_reg = 0x1a5fa, .green_reg = 0x1a5fa, .blue_reg = 0x1a5fa}, + {.red_reg = 0x1a6ca, .green_reg = 0x1a6ca, .blue_reg = 0x1a6ca}, + {.red_reg = 0x1a7a2, .green_reg = 0x1a7a2, .blue_reg = 0x1a7a2}, + {.red_reg = 0x1a881, .green_reg = 0x1a881, .blue_reg = 0x1a881}, + {.red_reg = 0x1a968, .green_reg = 0x1a968, .blue_reg = 0x1a968}, + {.red_reg = 0x1aa58, .green_reg = 0x1aa58, .blue_reg = 0x1aa58}, + {.red_reg = 0x1ab51, .green_reg = 0x1ab51, .blue_reg = 0x1ab51}, + {.red_reg = 0x1ac52, .green_reg = 0x1ac52, .blue_reg = 0x1ac52}, + {.red_reg = 0x1ad5d, .green_reg = 0x1ad5d, .blue_reg = 0x1ad5d}, + {.red_reg = 0x1ae71, .green_reg = 0x1ae71, .blue_reg = 0x1ae71}, + {.red_reg = 0x1af8f, .green_reg = 0x1af8f, .blue_reg = 0x1af8f}, + {.red_reg = 0x1b05c, .green_reg = 0x1b05c, .blue_reg = 0x1b05c}, + {.red_reg = 0x1b0f5, .green_reg = 0x1b0f5, .blue_reg = 0x1b0f5}, + {.red_reg = 0x1b194, .green_reg = 0x1b194, .blue_reg = 0x1b194}, + {.red_reg = 0x1b239, .green_reg = 0x1b239, .blue_reg = 0x1b239}, + {.red_reg = 0x1b2e4, .green_reg = 0x1b2e4, .blue_reg = 0x1b2e4}, + {.red_reg = 0x1b395, .green_reg = 0x1b395, .blue_reg = 0x1b395}, + {.red_reg = 0x1b44c, .green_reg = 0x1b44c, .blue_reg = 0x1b44c}, + {.red_reg = 0x1b50a, .green_reg = 0x1b50a, .blue_reg = 0x1b50a}, + {.red_reg = 0x1b5cf, .green_reg = 0x1b5cf, .blue_reg = 0x1b5cf}, + {.red_reg = 0x1b69b, .green_reg = 0x1b69b, .blue_reg = 0x1b69b}, + {.red_reg = 0x1b76e, .green_reg = 0x1b76e, .blue_reg = 0x1b76e}, + {.red_reg = 0x1b849, .green_reg = 0x1b849, .blue_reg = 0x1b849}, + {.red_reg = 0x1b92c, .green_reg = 0x1b92c, .blue_reg = 0x1b92c}, + {.red_reg = 0x1ba17, .green_reg = 0x1ba17, .blue_reg = 0x1ba17}, + {.red_reg = 0x1bb0b, .green_reg = 0x1bb0b, .blue_reg = 0x1bb0b}, + {.red_reg = 0x1bc07, .green_reg = 0x1bc07, .blue_reg = 0x1bc07}, + {.red_reg = 0x1bd0d, .green_reg = 0x1bd0d, .blue_reg = 0x1bd0d}, + {.red_reg = 0x1be1c, .green_reg = 0x1be1c, .blue_reg = 0x1be1c}, + {.red_reg = 0x1bf35, .green_reg = 0x1bf35, .blue_reg = 0x1bf35}, + {.red_reg = 0x1c02c, .green_reg = 0x1c02c, .blue_reg = 0x1c02c}, + {.red_reg = 0x1c0c3, .green_reg = 0x1c0c3, .blue_reg = 0x1c0c3}, + {.red_reg = 0x1c15f, .green_reg = 0x1c15f, .blue_reg = 0x1c15f}, + {.red_reg = 0x1c201, .green_reg = 0x1c201, .blue_reg = 0x1c201}, + {.red_reg = 0x1c2a9, .green_reg = 0x1c2a9, .blue_reg = 0x1c2a9}, + {.red_reg = 0x1c358, .green_reg = 0x1c358, .blue_reg = 0x1c358}, + {.red_reg = 0x1c40c, .green_reg = 0x1c40c, .blue_reg = 0x1c40c}, + {.red_reg = 0x1c4c7, .green_reg = 0x1c4c7, .blue_reg = 0x1c4c7}, + {.red_reg = 0x1c589, .green_reg = 0x1c589, .blue_reg = 0x1c589}, + {.red_reg = 0x1c652, .green_reg = 0x1c652, .blue_reg = 0x1c652}, + {.red_reg = 0x1c723, .green_reg = 0x1c723, .blue_reg = 0x1c723}, + {.red_reg = 0x1c7fb, .green_reg = 0x1c7fb, .blue_reg = 0x1c7fb}, + {.red_reg = 0x1c8db, .green_reg = 0x1c8db, .blue_reg = 0x1c8db}, + {.red_reg = 0x1c9c3, .green_reg = 0x1c9c3, .blue_reg = 0x1c9c3}, + {.red_reg = 0x1cab4, .green_reg = 0x1cab4, .blue_reg = 0x1cab4}, + {.red_reg = 0x1cbae, .green_reg = 0x1cbae, .blue_reg = 0x1cbae}, + {.red_reg = 0x1ccb1, .green_reg = 0x1ccb1, .blue_reg = 0x1ccb1}, + {.red_reg = 0x1cdbe, .green_reg = 0x1cdbe, .blue_reg = 0x1cdbe}, + {.red_reg = 0x1ced4, .green_reg = 0x1ced4, .blue_reg = 0x1ced4}, + {.red_reg = 0x1cff5, .green_reg = 0x1cff5, .blue_reg = 0x1cff5}, + {.red_reg = 0x1d090, .green_reg = 0x1d090, .blue_reg = 0x1d090}, + {.red_reg = 0x1d12b, .green_reg = 0x1d12b, .blue_reg = 0x1d12b}, + {.red_reg = 0x1d1cc, .green_reg = 0x1d1cc, .blue_reg = 0x1d1cc}, + {.red_reg = 0x1d274, .green_reg = 0x1d274, .blue_reg = 0x1d274}, + {.red_reg = 0x1d321, .green_reg = 0x1d321, .blue_reg = 0x1d321}, + {.red_reg = 0x1d3d5, .green_reg = 0x1d3d5, .blue_reg = 0x1d3d5}, + {.red_reg = 0x1d48f, .green_reg = 0x1d48f, .blue_reg = 0x1d48f}, + {.red_reg = 0x1d551, .green_reg = 0x1d551, .blue_reg = 0x1d551}, + {.red_reg = 0x1d61a, .green_reg = 0x1d61a, .blue_reg = 0x1d61a}, + {.red_reg = 0x1d6ea, .green_reg = 0x1d6ea, .blue_reg = 0x1d6ea}, + {.red_reg = 0x1d7c2, .green_reg = 0x1d7c2, .blue_reg = 0x1d7c2}, + {.red_reg = 0x1d8a2, .green_reg = 0x1d8a2, .blue_reg = 0x1d8a2}, + {.red_reg = 0x1d98b, .green_reg = 0x1d98b, .blue_reg = 0x1d98b}, + {.red_reg = 0x1da7d, .green_reg = 0x1da7d, .blue_reg = 0x1da7d}, + {.red_reg = 0x1db77, .green_reg = 0x1db77, .blue_reg = 0x1db77}, + {.red_reg = 0x1dc7c, .green_reg = 0x1dc7c, .blue_reg = 0x1dc7c}, + {.red_reg = 0x1dd8a, .green_reg = 0x1dd8a, .blue_reg = 0x1dd8a}, + {.red_reg = 0x1dea2, .green_reg = 0x1dea2, .blue_reg = 0x1dea2}, + {.red_reg = 0x1dfc5, .green_reg = 0x1dfc5, .blue_reg = 0x1dfc5}, + {.red_reg = 0x1e079, .green_reg = 0x1e079, .blue_reg = 0x1e079}, + {.red_reg = 0x1e116, .green_reg = 0x1e116, .blue_reg = 0x1e116}, + {.red_reg = 0x1e1b9, .green_reg = 0x1e1b9, .blue_reg = 0x1e1b9}, + {.red_reg = 0x1e262, .green_reg = 0x1e262, .blue_reg = 0x1e262}, + {.red_reg = 0x1e312, .green_reg = 0x1e312, .blue_reg = 0x1e312}, + {.red_reg = 0x1e3c8, .green_reg = 0x1e3c8, .blue_reg = 0x1e3c8}, + {.red_reg = 0x1e486, .green_reg = 0x1e486, .blue_reg = 0x1e486}, + {.red_reg = 0x1e54a, .green_reg = 0x1e54a, .blue_reg = 0x1e54a}, + {.red_reg = 0x1e617, .green_reg = 0x1e617, .blue_reg = 0x1e617}, + {.red_reg = 0x1e6eb, .green_reg = 0x1e6eb, .blue_reg = 0x1e6eb}, + {.red_reg = 0x1e7c7, .green_reg = 0x1e7c7, .blue_reg = 0x1e7c7}, + {.red_reg = 0x1e8ac, .green_reg = 0x1e8ac, .blue_reg = 0x1e8ac}, + {.red_reg = 0x1e99a, .green_reg = 0x1e99a, .blue_reg = 0x1e99a}, + {.red_reg = 0x1ea92, .green_reg = 0x1ea92, .blue_reg = 0x1ea92}, + {.red_reg = 0x1eb93, .green_reg = 0x1eb93, .blue_reg = 0x1eb93}, + {.red_reg = 0x1ec9e, .green_reg = 0x1ec9e, .blue_reg = 0x1ec9e}, + {.red_reg = 0x1edb3, .green_reg = 0x1edb3, .blue_reg = 0x1edb3}, + {.red_reg = 0x1eed4, .green_reg = 0x1eed4, .blue_reg = 0x1eed4}, + {.red_reg = 0x1f000, .green_reg = 0x1f000, .blue_reg = 0x1f000}, + {.red_reg = 0, .green_reg = 0, .blue_reg = 0}, + {.red_reg = 0, .green_reg = 0, .blue_reg = 0}}}, + {.hw_points_num = NUM_OF_LUT_DATA_DEGAM, + .arr_curve_points = {{0x0, 0x0}, {0x1, 0x0}, {0x2, 0x1}, {0x4, 0x2}, {0x8, 0x3}, + {0x10, 0x4}, {0x20, 0x5}, {0x40, 0x6}, {0x80, 0x7}, {0x0, 0x0}, {0x0, 0x0}, + {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, + {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, + {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, + {0x0, 0x0}, {0x0, 0x0}}, + .corner_points = {{.red.custom_float_x = 0x16000, + .red.custom_float_y = 0x0, + .red.custom_float_slope = 0x1cc71, + .green.custom_float_x = 0x16000, + .green.custom_float_y = 0x0, + .green.custom_float_slope = 0x1cc71, + .blue.custom_float_x = 0x16000, + .blue.custom_float_y = 0x0, + .blue.custom_float_slope = 0x1cc71}, + {.red.custom_float_x = 0x7c00, + .red.custom_float_y = 0x1f000, + .red.custom_float_slope = 0x0, + .green.custom_float_x = 0x7c00, + .green.custom_float_y = 0x1f000, + .green.custom_float_slope = 0x0, + .blue.custom_float_x = 0x7c00, + .blue.custom_float_y = 0x1f000, + .blue.custom_float_slope = 0x0}}, + .rgb_resulted = {{.red_reg = 0x13c71, .green_reg = 0x13c71, .blue_reg = 0x13c71}, + {.red_reg = 0x14c71, .green_reg = 0x14c71, .blue_reg = 0x14c71}, + {.red_reg = 0x15c71, .green_reg = 0x15c71, .blue_reg = 0x15c71}, + {.red_reg = 0x16555, .green_reg = 0x16555, .blue_reg = 0x16555}, + {.red_reg = 0x16c71, .green_reg = 0x16c71, .blue_reg = 0x16c71}, + {.red_reg = 0x171c7, .green_reg = 0x171c7, .blue_reg = 0x171c7}, + {.red_reg = 0x17555, .green_reg = 0x17555, .blue_reg = 0x17555}, + {.red_reg = 0x178e3, .green_reg = 0x178e3, .blue_reg = 0x178e3}, + {.red_reg = 0x17c71, .green_reg = 0x17c71, .blue_reg = 0x17c71}, + {.red_reg = 0x18000, .green_reg = 0x18000, .blue_reg = 0x18000}, + {.red_reg = 0x181c7, .green_reg = 0x181c7, .blue_reg = 0x181c7}, + {.red_reg = 0x1838e, .green_reg = 0x1838e, .blue_reg = 0x1838e}, + {.red_reg = 0x18555, .green_reg = 0x18555, .blue_reg = 0x18555}, + {.red_reg = 0x1871c, .green_reg = 0x1871c, .blue_reg = 0x1871c}, + {.red_reg = 0x188e3, .green_reg = 0x188e3, .blue_reg = 0x188e3}, + {.red_reg = 0x18aaa, .green_reg = 0x18aaa, .blue_reg = 0x18aaa}, + {.red_reg = 0x18c71, .green_reg = 0x18c71, .blue_reg = 0x18c71}, + {.red_reg = 0x18e38, .green_reg = 0x18e38, .blue_reg = 0x18e38}, + {.red_reg = 0x19000, .green_reg = 0x19000, .blue_reg = 0x19000}, + {.red_reg = 0x190e3, .green_reg = 0x190e3, .blue_reg = 0x190e3}, + {.red_reg = 0x191c7, .green_reg = 0x191c7, .blue_reg = 0x191c7}, + {.red_reg = 0x1929e, .green_reg = 0x1929e, .blue_reg = 0x1929e}, + {.red_reg = 0x19385, .green_reg = 0x19385, .blue_reg = 0x19385}, + {.red_reg = 0x19473, .green_reg = 0x19473, .blue_reg = 0x19473}, + {.red_reg = 0x19566, .green_reg = 0x19566, .blue_reg = 0x19566}, + {.red_reg = 0x19660, .green_reg = 0x19660, .blue_reg = 0x19660}, + {.red_reg = 0x19760, .green_reg = 0x19760, .blue_reg = 0x19760}, + {.red_reg = 0x19866, .green_reg = 0x19866, .blue_reg = 0x19866}, + {.red_reg = 0x19973, .green_reg = 0x19973, .blue_reg = 0x19973}, + {.red_reg = 0x19a85, .green_reg = 0x19a85, .blue_reg = 0x19a85}, + {.red_reg = 0x19b9e, .green_reg = 0x19b9e, .blue_reg = 0x19b9e}, + {.red_reg = 0x19cbd, .green_reg = 0x19cbd, .blue_reg = 0x19cbd}, + {.red_reg = 0x19de2, .green_reg = 0x19de2, .blue_reg = 0x19de2}, + {.red_reg = 0x19f0e, .green_reg = 0x19f0e, .blue_reg = 0x19f0e}, + {.red_reg = 0x1a020, .green_reg = 0x1a020, .blue_reg = 0x1a020}, + {.red_reg = 0x1a0bc, .green_reg = 0x1a0bc, .blue_reg = 0x1a0bc}, + {.red_reg = 0x1a15b, .green_reg = 0x1a15b, .blue_reg = 0x1a15b}, + {.red_reg = 0x1a1fe, .green_reg = 0x1a1fe, .blue_reg = 0x1a1fe}, + {.red_reg = 0x1a2a3, .green_reg = 0x1a2a3, .blue_reg = 0x1a2a3}, + {.red_reg = 0x1a34c, .green_reg = 0x1a34c, .blue_reg = 0x1a34c}, + {.red_reg = 0x1a3f9, .green_reg = 0x1a3f9, .blue_reg = 0x1a3f9}, + {.red_reg = 0x1a4a8, .green_reg = 0x1a4a8, .blue_reg = 0x1a4a8}, + {.red_reg = 0x1a55b, .green_reg = 0x1a55b, .blue_reg = 0x1a55b}, + {.red_reg = 0x1a611, .green_reg = 0x1a611, .blue_reg = 0x1a611}, + {.red_reg = 0x1a6ca, .green_reg = 0x1a6ca, .blue_reg = 0x1a6ca}, + {.red_reg = 0x1a787, .green_reg = 0x1a787, .blue_reg = 0x1a787}, + {.red_reg = 0x1a847, .green_reg = 0x1a847, .blue_reg = 0x1a847}, + {.red_reg = 0x1a90a, .green_reg = 0x1a90a, .blue_reg = 0x1a90a}, + {.red_reg = 0x1a9d1, .green_reg = 0x1a9d1, .blue_reg = 0x1a9d1}, + {.red_reg = 0x1aa9b, .green_reg = 0x1aa9b, .blue_reg = 0x1aa9b}, + {.red_reg = 0x1ab68, .green_reg = 0x1ab68, .blue_reg = 0x1ab68}, + {.red_reg = 0x1ac38, .green_reg = 0x1ac38, .blue_reg = 0x1ac38}, + {.red_reg = 0x1ad0c, .green_reg = 0x1ad0c, .blue_reg = 0x1ad0c}, + {.red_reg = 0x1ade4, .green_reg = 0x1ade4, .blue_reg = 0x1ade4}, + {.red_reg = 0x1aebe, .green_reg = 0x1aebe, .blue_reg = 0x1aebe}, + {.red_reg = 0x1af9d, .green_reg = 0x1af9d, .blue_reg = 0x1af9d}, + {.red_reg = 0x1b03f, .green_reg = 0x1b03f, .blue_reg = 0x1b03f}, + {.red_reg = 0x1b0b1, .green_reg = 0x1b0b1, .blue_reg = 0x1b0b1}, + {.red_reg = 0x1b125, .green_reg = 0x1b125, .blue_reg = 0x1b125}, + {.red_reg = 0x1b19b, .green_reg = 0x1b19b, .blue_reg = 0x1b19b}, + {.red_reg = 0x1b213, .green_reg = 0x1b213, .blue_reg = 0x1b213}, + {.red_reg = 0x1b28c, .green_reg = 0x1b28c, .blue_reg = 0x1b28c}, + {.red_reg = 0x1b307, .green_reg = 0x1b307, .blue_reg = 0x1b307}, + {.red_reg = 0x1b384, .green_reg = 0x1b384, .blue_reg = 0x1b384}, + {.red_reg = 0x1b403, .green_reg = 0x1b403, .blue_reg = 0x1b403}, + {.red_reg = 0x1b483, .green_reg = 0x1b483, .blue_reg = 0x1b483}, + {.red_reg = 0x1b505, .green_reg = 0x1b505, .blue_reg = 0x1b505}, + {.red_reg = 0x1b589, .green_reg = 0x1b589, .blue_reg = 0x1b589}, + {.red_reg = 0x1b60e, .green_reg = 0x1b60e, .blue_reg = 0x1b60e}, + {.red_reg = 0x1b696, .green_reg = 0x1b696, .blue_reg = 0x1b696}, + {.red_reg = 0x1b71f, .green_reg = 0x1b71f, .blue_reg = 0x1b71f}, + {.red_reg = 0x1b7aa, .green_reg = 0x1b7aa, .blue_reg = 0x1b7aa}, + {.red_reg = 0x1b836, .green_reg = 0x1b836, .blue_reg = 0x1b836}, + {.red_reg = 0x1b8c5, .green_reg = 0x1b8c5, .blue_reg = 0x1b8c5}, + {.red_reg = 0x1b955, .green_reg = 0x1b955, .blue_reg = 0x1b955}, + {.red_reg = 0x1b9e7, .green_reg = 0x1b9e7, .blue_reg = 0x1b9e7}, + {.red_reg = 0x1ba7a, .green_reg = 0x1ba7a, .blue_reg = 0x1ba7a}, + {.red_reg = 0x1bb10, .green_reg = 0x1bb10, .blue_reg = 0x1bb10}, + {.red_reg = 0x1bba7, .green_reg = 0x1bba7, .blue_reg = 0x1bba7}, + {.red_reg = 0x1bc40, .green_reg = 0x1bc40, .blue_reg = 0x1bc40}, + {.red_reg = 0x1bcdb, .green_reg = 0x1bcdb, .blue_reg = 0x1bcdb}, + {.red_reg = 0x1bd78, .green_reg = 0x1bd78, .blue_reg = 0x1bd78}, + {.red_reg = 0x1be17, .green_reg = 0x1be17, .blue_reg = 0x1be17}, + {.red_reg = 0x1beb7, .green_reg = 0x1beb7, .blue_reg = 0x1beb7}, + {.red_reg = 0x1bf59, .green_reg = 0x1bf59, .blue_reg = 0x1bf59}, + {.red_reg = 0x1bffd, .green_reg = 0x1bffd, .blue_reg = 0x1bffd}, + {.red_reg = 0x1c051, .green_reg = 0x1c051, .blue_reg = 0x1c051}, + {.red_reg = 0x1c0a5, .green_reg = 0x1c0a5, .blue_reg = 0x1c0a5}, + {.red_reg = 0x1c0fa, .green_reg = 0x1c0fa, .blue_reg = 0x1c0fa}, + {.red_reg = 0x1c14f, .green_reg = 0x1c14f, .blue_reg = 0x1c14f}, + {.red_reg = 0x1c1a6, .green_reg = 0x1c1a6, .blue_reg = 0x1c1a6}, + {.red_reg = 0x1c1fe, .green_reg = 0x1c1fe, .blue_reg = 0x1c1fe}, + {.red_reg = 0x1c256, .green_reg = 0x1c256, .blue_reg = 0x1c256}, + {.red_reg = 0x1c2af, .green_reg = 0x1c2af, .blue_reg = 0x1c2af}, + {.red_reg = 0x1c30a, .green_reg = 0x1c30a, .blue_reg = 0x1c30a}, + {.red_reg = 0x1c365, .green_reg = 0x1c365, .blue_reg = 0x1c365}, + {.red_reg = 0x1c3c1, .green_reg = 0x1c3c1, .blue_reg = 0x1c3c1}, + {.red_reg = 0x1c41e, .green_reg = 0x1c41e, .blue_reg = 0x1c41e}, + {.red_reg = 0x1c47c, .green_reg = 0x1c47c, .blue_reg = 0x1c47c}, + {.red_reg = 0x1c4db, .green_reg = 0x1c4db, .blue_reg = 0x1c4db}, + {.red_reg = 0x1c53b, .green_reg = 0x1c53b, .blue_reg = 0x1c53b}, + {.red_reg = 0x1c59c, .green_reg = 0x1c59c, .blue_reg = 0x1c59c}, + {.red_reg = 0x1c5fd, .green_reg = 0x1c5fd, .blue_reg = 0x1c5fd}, + {.red_reg = 0x1c660, .green_reg = 0x1c660, .blue_reg = 0x1c660}, + {.red_reg = 0x1c6c4, .green_reg = 0x1c6c4, .blue_reg = 0x1c6c4}, + {.red_reg = 0x1c728, .green_reg = 0x1c728, .blue_reg = 0x1c728}, + {.red_reg = 0x1c78e, .green_reg = 0x1c78e, .blue_reg = 0x1c78e}, + {.red_reg = 0x1c7f4, .green_reg = 0x1c7f4, .blue_reg = 0x1c7f4}, + {.red_reg = 0x1c85c, .green_reg = 0x1c85c, .blue_reg = 0x1c85c}, + {.red_reg = 0x1c8c4, .green_reg = 0x1c8c4, .blue_reg = 0x1c8c4}, + {.red_reg = 0x1c92e, .green_reg = 0x1c92e, .blue_reg = 0x1c92e}, + {.red_reg = 0x1c998, .green_reg = 0x1c998, .blue_reg = 0x1c998}, + {.red_reg = 0x1ca03, .green_reg = 0x1ca03, .blue_reg = 0x1ca03}, + {.red_reg = 0x1ca6f, .green_reg = 0x1ca6f, .blue_reg = 0x1ca6f}, + {.red_reg = 0x1cadd, .green_reg = 0x1cadd, .blue_reg = 0x1cadd}, + {.red_reg = 0x1cb4b, .green_reg = 0x1cb4b, .blue_reg = 0x1cb4b}, + {.red_reg = 0x1cbba, .green_reg = 0x1cbba, .blue_reg = 0x1cbba}, + {.red_reg = 0x1cc2a, .green_reg = 0x1cc2a, .blue_reg = 0x1cc2a}, + {.red_reg = 0x1cc9b, .green_reg = 0x1cc9b, .blue_reg = 0x1cc9b}, + {.red_reg = 0x1cd0d, .green_reg = 0x1cd0d, .blue_reg = 0x1cd0d}, + {.red_reg = 0x1cd80, .green_reg = 0x1cd80, .blue_reg = 0x1cd80}, + {.red_reg = 0x1cdf4, .green_reg = 0x1cdf4, .blue_reg = 0x1cdf4}, + {.red_reg = 0x1ce69, .green_reg = 0x1ce69, .blue_reg = 0x1ce69}, + {.red_reg = 0x1cedf, .green_reg = 0x1cedf, .blue_reg = 0x1cedf}, + {.red_reg = 0x1cf56, .green_reg = 0x1cf56, .blue_reg = 0x1cf56}, + {.red_reg = 0x1cfcd, .green_reg = 0x1cfcd, .blue_reg = 0x1cfcd}, + {.red_reg = 0x1d023, .green_reg = 0x1d023, .blue_reg = 0x1d023}, + {.red_reg = 0x1d060, .green_reg = 0x1d060, .blue_reg = 0x1d060}, + {.red_reg = 0x1d09d, .green_reg = 0x1d09d, .blue_reg = 0x1d09d}, + {.red_reg = 0x1d0db, .green_reg = 0x1d0db, .blue_reg = 0x1d0db}, + {.red_reg = 0x1d119, .green_reg = 0x1d119, .blue_reg = 0x1d119}, + {.red_reg = 0x1d158, .green_reg = 0x1d158, .blue_reg = 0x1d158}, + {.red_reg = 0x1d198, .green_reg = 0x1d198, .blue_reg = 0x1d198}, + {.red_reg = 0x1d1d8, .green_reg = 0x1d1d8, .blue_reg = 0x1d1d8}, + {.red_reg = 0x1d218, .green_reg = 0x1d218, .blue_reg = 0x1d218}, + {.red_reg = 0x1d259, .green_reg = 0x1d259, .blue_reg = 0x1d259}, + {.red_reg = 0x1d29a, .green_reg = 0x1d29a, .blue_reg = 0x1d29a}, + {.red_reg = 0x1d2dc, .green_reg = 0x1d2dc, .blue_reg = 0x1d2dc}, + {.red_reg = 0x1d31e, .green_reg = 0x1d31e, .blue_reg = 0x1d31e}, + {.red_reg = 0x1d361, .green_reg = 0x1d361, .blue_reg = 0x1d361}, + {.red_reg = 0x1d3a4, .green_reg = 0x1d3a4, .blue_reg = 0x1d3a4}, + {.red_reg = 0x1d3e8, .green_reg = 0x1d3e8, .blue_reg = 0x1d3e8}, + {.red_reg = 0x1d42d, .green_reg = 0x1d42d, .blue_reg = 0x1d42d}, + {.red_reg = 0x1d471, .green_reg = 0x1d471, .blue_reg = 0x1d471}, + {.red_reg = 0x1d4b7, .green_reg = 0x1d4b7, .blue_reg = 0x1d4b7}, + {.red_reg = 0x1d4fd, .green_reg = 0x1d4fd, .blue_reg = 0x1d4fd}, + {.red_reg = 0x1d543, .green_reg = 0x1d543, .blue_reg = 0x1d543}, + {.red_reg = 0x1d58a, .green_reg = 0x1d58a, .blue_reg = 0x1d58a}, + {.red_reg = 0x1d5d1, .green_reg = 0x1d5d1, .blue_reg = 0x1d5d1}, + {.red_reg = 0x1d619, .green_reg = 0x1d619, .blue_reg = 0x1d619}, + {.red_reg = 0x1d661, .green_reg = 0x1d661, .blue_reg = 0x1d661}, + {.red_reg = 0x1d6aa, .green_reg = 0x1d6aa, .blue_reg = 0x1d6aa}, + {.red_reg = 0x1d6f4, .green_reg = 0x1d6f4, .blue_reg = 0x1d6f4}, + {.red_reg = 0x1d73d, .green_reg = 0x1d73d, .blue_reg = 0x1d73d}, + {.red_reg = 0x1d788, .green_reg = 0x1d788, .blue_reg = 0x1d788}, + {.red_reg = 0x1d7d3, .green_reg = 0x1d7d3, .blue_reg = 0x1d7d3}, + {.red_reg = 0x1d81e, .green_reg = 0x1d81e, .blue_reg = 0x1d81e}, + {.red_reg = 0x1d86a, .green_reg = 0x1d86a, .blue_reg = 0x1d86a}, + {.red_reg = 0x1d8b6, .green_reg = 0x1d8b6, .blue_reg = 0x1d8b6}, + {.red_reg = 0x1d903, .green_reg = 0x1d903, .blue_reg = 0x1d903}, + {.red_reg = 0x1d951, .green_reg = 0x1d951, .blue_reg = 0x1d951}, + {.red_reg = 0x1d99f, .green_reg = 0x1d99f, .blue_reg = 0x1d99f}, + {.red_reg = 0x1d9ed, .green_reg = 0x1d9ed, .blue_reg = 0x1d9ed}, + {.red_reg = 0x1da3c, .green_reg = 0x1da3c, .blue_reg = 0x1da3c}, + {.red_reg = 0x1da8c, .green_reg = 0x1da8c, .blue_reg = 0x1da8c}, + {.red_reg = 0x1dadc, .green_reg = 0x1dadc, .blue_reg = 0x1dadc}, + {.red_reg = 0x1db2c, .green_reg = 0x1db2c, .blue_reg = 0x1db2c}, + {.red_reg = 0x1db7d, .green_reg = 0x1db7d, .blue_reg = 0x1db7d}, + {.red_reg = 0x1dbcf, .green_reg = 0x1dbcf, .blue_reg = 0x1dbcf}, + {.red_reg = 0x1dc21, .green_reg = 0x1dc21, .blue_reg = 0x1dc21}, + {.red_reg = 0x1dc74, .green_reg = 0x1dc74, .blue_reg = 0x1dc74}, + {.red_reg = 0x1dcc7, .green_reg = 0x1dcc7, .blue_reg = 0x1dcc7}, + {.red_reg = 0x1dd1a, .green_reg = 0x1dd1a, .blue_reg = 0x1dd1a}, + {.red_reg = 0x1dd6e, .green_reg = 0x1dd6e, .blue_reg = 0x1dd6e}, + {.red_reg = 0x1ddc3, .green_reg = 0x1ddc3, .blue_reg = 0x1ddc3}, + {.red_reg = 0x1de18, .green_reg = 0x1de18, .blue_reg = 0x1de18}, + {.red_reg = 0x1de6e, .green_reg = 0x1de6e, .blue_reg = 0x1de6e}, + {.red_reg = 0x1dec4, .green_reg = 0x1dec4, .blue_reg = 0x1dec4}, + {.red_reg = 0x1df1b, .green_reg = 0x1df1b, .blue_reg = 0x1df1b}, + {.red_reg = 0x1df72, .green_reg = 0x1df72, .blue_reg = 0x1df72}, + {.red_reg = 0x1dfca, .green_reg = 0x1dfca, .blue_reg = 0x1dfca}, + {.red_reg = 0x1e011, .green_reg = 0x1e011, .blue_reg = 0x1e011}, + {.red_reg = 0x1e03d, .green_reg = 0x1e03d, .blue_reg = 0x1e03d}, + {.red_reg = 0x1e06a, .green_reg = 0x1e06a, .blue_reg = 0x1e06a}, + {.red_reg = 0x1e097, .green_reg = 0x1e097, .blue_reg = 0x1e097}, + {.red_reg = 0x1e0c4, .green_reg = 0x1e0c4, .blue_reg = 0x1e0c4}, + {.red_reg = 0x1e0f2, .green_reg = 0x1e0f2, .blue_reg = 0x1e0f2}, + {.red_reg = 0x1e11f, .green_reg = 0x1e11f, .blue_reg = 0x1e11f}, + {.red_reg = 0x1e14d, .green_reg = 0x1e14d, .blue_reg = 0x1e14d}, + {.red_reg = 0x1e17c, .green_reg = 0x1e17c, .blue_reg = 0x1e17c}, + {.red_reg = 0x1e1aa, .green_reg = 0x1e1aa, .blue_reg = 0x1e1aa}, + {.red_reg = 0x1e1d9, .green_reg = 0x1e1d9, .blue_reg = 0x1e1d9}, + {.red_reg = 0x1e208, .green_reg = 0x1e208, .blue_reg = 0x1e208}, + {.red_reg = 0x1e237, .green_reg = 0x1e237, .blue_reg = 0x1e237}, + {.red_reg = 0x1e267, .green_reg = 0x1e267, .blue_reg = 0x1e267}, + {.red_reg = 0x1e297, .green_reg = 0x1e297, .blue_reg = 0x1e297}, + {.red_reg = 0x1e2c7, .green_reg = 0x1e2c7, .blue_reg = 0x1e2c7}, + {.red_reg = 0x1e2f7, .green_reg = 0x1e2f7, .blue_reg = 0x1e2f7}, + {.red_reg = 0x1e328, .green_reg = 0x1e328, .blue_reg = 0x1e328}, + {.red_reg = 0x1e359, .green_reg = 0x1e359, .blue_reg = 0x1e359}, + {.red_reg = 0x1e38a, .green_reg = 0x1e38a, .blue_reg = 0x1e38a}, + {.red_reg = 0x1e3bc, .green_reg = 0x1e3bc, .blue_reg = 0x1e3bc}, + {.red_reg = 0x1e3ed, .green_reg = 0x1e3ed, .blue_reg = 0x1e3ed}, + {.red_reg = 0x1e41f, .green_reg = 0x1e41f, .blue_reg = 0x1e41f}, + {.red_reg = 0x1e452, .green_reg = 0x1e452, .blue_reg = 0x1e452}, + {.red_reg = 0x1e484, .green_reg = 0x1e484, .blue_reg = 0x1e484}, + {.red_reg = 0x1e4b7, .green_reg = 0x1e4b7, .blue_reg = 0x1e4b7}, + {.red_reg = 0x1e4ea, .green_reg = 0x1e4ea, .blue_reg = 0x1e4ea}, + {.red_reg = 0x1e51d, .green_reg = 0x1e51d, .blue_reg = 0x1e51d}, + {.red_reg = 0x1e551, .green_reg = 0x1e551, .blue_reg = 0x1e551}, + {.red_reg = 0x1e585, .green_reg = 0x1e585, .blue_reg = 0x1e585}, + {.red_reg = 0x1e5b9, .green_reg = 0x1e5b9, .blue_reg = 0x1e5b9}, + {.red_reg = 0x1e5ee, .green_reg = 0x1e5ee, .blue_reg = 0x1e5ee}, + {.red_reg = 0x1e622, .green_reg = 0x1e622, .blue_reg = 0x1e622}, + {.red_reg = 0x1e657, .green_reg = 0x1e657, .blue_reg = 0x1e657}, + {.red_reg = 0x1e68c, .green_reg = 0x1e68c, .blue_reg = 0x1e68c}, + {.red_reg = 0x1e6c2, .green_reg = 0x1e6c2, .blue_reg = 0x1e6c2}, + {.red_reg = 0x1e6f8, .green_reg = 0x1e6f8, .blue_reg = 0x1e6f8}, + {.red_reg = 0x1e72e, .green_reg = 0x1e72e, .blue_reg = 0x1e72e}, + {.red_reg = 0x1e764, .green_reg = 0x1e764, .blue_reg = 0x1e764}, + {.red_reg = 0x1e79b, .green_reg = 0x1e79b, .blue_reg = 0x1e79b}, + {.red_reg = 0x1e7d2, .green_reg = 0x1e7d2, .blue_reg = 0x1e7d2}, + {.red_reg = 0x1e809, .green_reg = 0x1e809, .blue_reg = 0x1e809}, + {.red_reg = 0x1e840, .green_reg = 0x1e840, .blue_reg = 0x1e840}, + {.red_reg = 0x1e878, .green_reg = 0x1e878, .blue_reg = 0x1e878}, + {.red_reg = 0x1e8b0, .green_reg = 0x1e8b0, .blue_reg = 0x1e8b0}, + {.red_reg = 0x1e8e8, .green_reg = 0x1e8e8, .blue_reg = 0x1e8e8}, + {.red_reg = 0x1e920, .green_reg = 0x1e920, .blue_reg = 0x1e920}, + {.red_reg = 0x1e959, .green_reg = 0x1e959, .blue_reg = 0x1e959}, + {.red_reg = 0x1e992, .green_reg = 0x1e992, .blue_reg = 0x1e992}, + {.red_reg = 0x1e9cc, .green_reg = 0x1e9cc, .blue_reg = 0x1e9cc}, + {.red_reg = 0x1ea05, .green_reg = 0x1ea05, .blue_reg = 0x1ea05}, + {.red_reg = 0x1ea3f, .green_reg = 0x1ea3f, .blue_reg = 0x1ea3f}, + {.red_reg = 0x1ea79, .green_reg = 0x1ea79, .blue_reg = 0x1ea79}, + {.red_reg = 0x1eab4, .green_reg = 0x1eab4, .blue_reg = 0x1eab4}, + {.red_reg = 0x1eaee, .green_reg = 0x1eaee, .blue_reg = 0x1eaee}, + {.red_reg = 0x1eb29, .green_reg = 0x1eb29, .blue_reg = 0x1eb29}, + {.red_reg = 0x1eb65, .green_reg = 0x1eb65, .blue_reg = 0x1eb65}, + {.red_reg = 0x1eba0, .green_reg = 0x1eba0, .blue_reg = 0x1eba0}, + {.red_reg = 0x1ebdc, .green_reg = 0x1ebdc, .blue_reg = 0x1ebdc}, + {.red_reg = 0x1ec18, .green_reg = 0x1ec18, .blue_reg = 0x1ec18}, + {.red_reg = 0x1ec55, .green_reg = 0x1ec55, .blue_reg = 0x1ec55}, + {.red_reg = 0x1ec91, .green_reg = 0x1ec91, .blue_reg = 0x1ec91}, + {.red_reg = 0x1ecce, .green_reg = 0x1ecce, .blue_reg = 0x1ecce}, + {.red_reg = 0x1ed0b, .green_reg = 0x1ed0b, .blue_reg = 0x1ed0b}, + {.red_reg = 0x1ed49, .green_reg = 0x1ed49, .blue_reg = 0x1ed49}, + {.red_reg = 0x1ed87, .green_reg = 0x1ed87, .blue_reg = 0x1ed87}, + {.red_reg = 0x1edc5, .green_reg = 0x1edc5, .blue_reg = 0x1edc5}, + {.red_reg = 0x1ee03, .green_reg = 0x1ee03, .blue_reg = 0x1ee03}, + {.red_reg = 0x1ee41, .green_reg = 0x1ee41, .blue_reg = 0x1ee41}, + {.red_reg = 0x1ee80, .green_reg = 0x1ee80, .blue_reg = 0x1ee80}, + {.red_reg = 0x1eec0, .green_reg = 0x1eec0, .blue_reg = 0x1eec0}, + {.red_reg = 0x1eeff, .green_reg = 0x1eeff, .blue_reg = 0x1eeff}, + {.red_reg = 0x1ef3f, .green_reg = 0x1ef3f, .blue_reg = 0x1ef3f}, + {.red_reg = 0x1ef7f, .green_reg = 0x1ef7f, .blue_reg = 0x1ef7f}, + {.red_reg = 0x1efbf, .green_reg = 0x1efbf, .blue_reg = 0x1efbf}, + {.red_reg = 0x1f000, .green_reg = 0x1f000, .blue_reg = 0x1f000}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}}}, + }, + { + // Regam + {.hw_points_num = NUM_OF_LUT_DATA_REGAM_SDR, + .arr_curve_points = {{0x0, 0x3}, {0x8, 0x4}, {0x18, 0x4}, {0x28, 0x4}, {0x38, 0x4}, + {0x48, 0x4}, {0x58, 0x4}, {0x68, 0x4}, {0x78, 0x4}, {0x88, 0x4}, {0x98, 0x4}, + {0xa8, 0x4}, {0xb8, 0x1}, {0xba, 0x0}, {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, + {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, + {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, + {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}}, + .corner_points = {{.red.custom_float_x = 0x13000, + .red.custom_float_y = 0x0, + .red.custom_float_slope = 0x229d7, + .green.custom_float_x = 0x13000, + .green.custom_float_y = 0x0, + .green.custom_float_slope = 0x229d7, + .blue.custom_float_x = 0x13000, + .blue.custom_float_y = 0x0, + .blue.custom_float_slope = 0x229d7}, + {.red.custom_float_x = 0x8000, + .red.custom_float_y = 0x1f000, + .red.custom_float_slope = 0x0, + .green.custom_float_x = 0x8000, + .green.custom_float_y = 0x1f000, + .green.custom_float_slope = 0x0, + .blue.custom_float_x = 0x8000, + .blue.custom_float_y = 0x1f000, + .blue.custom_float_slope = 0x0}}, + .rgb_resulted = {{.red_reg = 0x169d7, .green_reg = 0x169d7, .blue_reg = 0x169d7}, + {.red_reg = 0x16d11, .green_reg = 0x16d11, .blue_reg = 0x16d11}, + {.red_reg = 0x17026, .green_reg = 0x17026, .blue_reg = 0x17026}, + {.red_reg = 0x171c3, .green_reg = 0x171c3, .blue_reg = 0x171c3}, + {.red_reg = 0x17361, .green_reg = 0x17361, .blue_reg = 0x17361}, + {.red_reg = 0x174fe, .green_reg = 0x174fe, .blue_reg = 0x174fe}, + {.red_reg = 0x1769c, .green_reg = 0x1769c, .blue_reg = 0x1769c}, + {.red_reg = 0x17839, .green_reg = 0x17839, .blue_reg = 0x17839}, + {.red_reg = 0x179d7, .green_reg = 0x179d7, .blue_reg = 0x179d7}, + {.red_reg = 0x17b74, .green_reg = 0x17b74, .blue_reg = 0x17b74}, + {.red_reg = 0x17d11, .green_reg = 0x17d11, .blue_reg = 0x17d11}, + {.red_reg = 0x17eaf, .green_reg = 0x17eaf, .blue_reg = 0x17eaf}, + {.red_reg = 0x18026, .green_reg = 0x18026, .blue_reg = 0x18026}, + {.red_reg = 0x180f5, .green_reg = 0x180f5, .blue_reg = 0x180f5}, + {.red_reg = 0x181c3, .green_reg = 0x181c3, .blue_reg = 0x181c3}, + {.red_reg = 0x18292, .green_reg = 0x18292, .blue_reg = 0x18292}, + {.red_reg = 0x18361, .green_reg = 0x18361, .blue_reg = 0x18361}, + {.red_reg = 0x18430, .green_reg = 0x18430, .blue_reg = 0x18430}, + {.red_reg = 0x184fe, .green_reg = 0x184fe, .blue_reg = 0x184fe}, + {.red_reg = 0x185cd, .green_reg = 0x185cd, .blue_reg = 0x185cd}, + {.red_reg = 0x1869c, .green_reg = 0x1869c, .blue_reg = 0x1869c}, + {.red_reg = 0x1876a, .green_reg = 0x1876a, .blue_reg = 0x1876a}, + {.red_reg = 0x18839, .green_reg = 0x18839, .blue_reg = 0x18839}, + {.red_reg = 0x18908, .green_reg = 0x18908, .blue_reg = 0x18908}, + {.red_reg = 0x189d7, .green_reg = 0x189d7, .blue_reg = 0x189d7}, + {.red_reg = 0x18b74, .green_reg = 0x18b74, .blue_reg = 0x18b74}, + {.red_reg = 0x18d11, .green_reg = 0x18d11, .blue_reg = 0x18d11}, + {.red_reg = 0x18eaf, .green_reg = 0x18eaf, .blue_reg = 0x18eaf}, + {.red_reg = 0x19026, .green_reg = 0x19026, .blue_reg = 0x19026}, + {.red_reg = 0x190f5, .green_reg = 0x190f5, .blue_reg = 0x190f5}, + {.red_reg = 0x191c3, .green_reg = 0x191c3, .blue_reg = 0x191c3}, + {.red_reg = 0x19292, .green_reg = 0x19292, .blue_reg = 0x19292}, + {.red_reg = 0x19361, .green_reg = 0x19361, .blue_reg = 0x19361}, + {.red_reg = 0x19430, .green_reg = 0x19430, .blue_reg = 0x19430}, + {.red_reg = 0x194fe, .green_reg = 0x194fe, .blue_reg = 0x194fe}, + {.red_reg = 0x195cd, .green_reg = 0x195cd, .blue_reg = 0x195cd}, + {.red_reg = 0x1969c, .green_reg = 0x1969c, .blue_reg = 0x1969c}, + {.red_reg = 0x1976a, .green_reg = 0x1976a, .blue_reg = 0x1976a}, + {.red_reg = 0x19839, .green_reg = 0x19839, .blue_reg = 0x19839}, + {.red_reg = 0x19908, .green_reg = 0x19908, .blue_reg = 0x19908}, + {.red_reg = 0x199d7, .green_reg = 0x199d7, .blue_reg = 0x199d7}, + {.red_reg = 0x19b74, .green_reg = 0x19b74, .blue_reg = 0x19b74}, + {.red_reg = 0x19d11, .green_reg = 0x19d11, .blue_reg = 0x19d11}, + {.red_reg = 0x19eaf, .green_reg = 0x19eaf, .blue_reg = 0x19eaf}, + {.red_reg = 0x1a026, .green_reg = 0x1a026, .blue_reg = 0x1a026}, + {.red_reg = 0x1a0f5, .green_reg = 0x1a0f5, .blue_reg = 0x1a0f5}, + {.red_reg = 0x1a1c3, .green_reg = 0x1a1c3, .blue_reg = 0x1a1c3}, + {.red_reg = 0x1a292, .green_reg = 0x1a292, .blue_reg = 0x1a292}, + {.red_reg = 0x1a361, .green_reg = 0x1a361, .blue_reg = 0x1a361}, + {.red_reg = 0x1a430, .green_reg = 0x1a430, .blue_reg = 0x1a430}, + {.red_reg = 0x1a4fd, .green_reg = 0x1a4fd, .blue_reg = 0x1a4fd}, + {.red_reg = 0x1a5c4, .green_reg = 0x1a5c4, .blue_reg = 0x1a5c4}, + {.red_reg = 0x1a687, .green_reg = 0x1a687, .blue_reg = 0x1a687}, + {.red_reg = 0x1a746, .green_reg = 0x1a746, .blue_reg = 0x1a746}, + {.red_reg = 0x1a802, .green_reg = 0x1a802, .blue_reg = 0x1a802}, + {.red_reg = 0x1a8b9, .green_reg = 0x1a8b9, .blue_reg = 0x1a8b9}, + {.red_reg = 0x1a96e, .green_reg = 0x1a96e, .blue_reg = 0x1a96e}, + {.red_reg = 0x1aacd, .green_reg = 0x1aacd, .blue_reg = 0x1aacd}, + {.red_reg = 0x1ac20, .green_reg = 0x1ac20, .blue_reg = 0x1ac20}, + {.red_reg = 0x1ad68, .green_reg = 0x1ad68, .blue_reg = 0x1ad68}, + {.red_reg = 0x1aea6, .green_reg = 0x1aea6, .blue_reg = 0x1aea6}, + {.red_reg = 0x1afdc, .green_reg = 0x1afdc, .blue_reg = 0x1afdc}, + {.red_reg = 0x1b084, .green_reg = 0x1b084, .blue_reg = 0x1b084}, + {.red_reg = 0x1b116, .green_reg = 0x1b116, .blue_reg = 0x1b116}, + {.red_reg = 0x1b1a5, .green_reg = 0x1b1a5, .blue_reg = 0x1b1a5}, + {.red_reg = 0x1b230, .green_reg = 0x1b230, .blue_reg = 0x1b230}, + {.red_reg = 0x1b2b9, .green_reg = 0x1b2b9, .blue_reg = 0x1b2b9}, + {.red_reg = 0x1b33e, .green_reg = 0x1b33e, .blue_reg = 0x1b33e}, + {.red_reg = 0x1b3c0, .green_reg = 0x1b3c0, .blue_reg = 0x1b3c0}, + {.red_reg = 0x1b440, .green_reg = 0x1b440, .blue_reg = 0x1b440}, + {.red_reg = 0x1b4bd, .green_reg = 0x1b4bd, .blue_reg = 0x1b4bd}, + {.red_reg = 0x1b537, .green_reg = 0x1b537, .blue_reg = 0x1b537}, + {.red_reg = 0x1b5af, .green_reg = 0x1b5af, .blue_reg = 0x1b5af}, + {.red_reg = 0x1b69a, .green_reg = 0x1b69a, .blue_reg = 0x1b69a}, + {.red_reg = 0x1b77c, .green_reg = 0x1b77c, .blue_reg = 0x1b77c}, + {.red_reg = 0x1b857, .green_reg = 0x1b857, .blue_reg = 0x1b857}, + {.red_reg = 0x1b92c, .green_reg = 0x1b92c, .blue_reg = 0x1b92c}, + {.red_reg = 0x1b9fa, .green_reg = 0x1b9fa, .blue_reg = 0x1b9fa}, + {.red_reg = 0x1bac3, .green_reg = 0x1bac3, .blue_reg = 0x1bac3}, + {.red_reg = 0x1bb86, .green_reg = 0x1bb86, .blue_reg = 0x1bb86}, + {.red_reg = 0x1bc45, .green_reg = 0x1bc45, .blue_reg = 0x1bc45}, + {.red_reg = 0x1bcff, .green_reg = 0x1bcff, .blue_reg = 0x1bcff}, + {.red_reg = 0x1bdb4, .green_reg = 0x1bdb4, .blue_reg = 0x1bdb4}, + {.red_reg = 0x1be66, .green_reg = 0x1be66, .blue_reg = 0x1be66}, + {.red_reg = 0x1bf14, .green_reg = 0x1bf14, .blue_reg = 0x1bf14}, + {.red_reg = 0x1bfbe, .green_reg = 0x1bfbe, .blue_reg = 0x1bfbe}, + {.red_reg = 0x1c032, .green_reg = 0x1c032, .blue_reg = 0x1c032}, + {.red_reg = 0x1c084, .green_reg = 0x1c084, .blue_reg = 0x1c084}, + {.red_reg = 0x1c0d4, .green_reg = 0x1c0d4, .blue_reg = 0x1c0d4}, + {.red_reg = 0x1c171, .green_reg = 0x1c171, .blue_reg = 0x1c171}, + {.red_reg = 0x1c208, .green_reg = 0x1c208, .blue_reg = 0x1c208}, + {.red_reg = 0x1c29a, .green_reg = 0x1c29a, .blue_reg = 0x1c29a}, + {.red_reg = 0x1c328, .green_reg = 0x1c328, .blue_reg = 0x1c328}, + {.red_reg = 0x1c3b2, .green_reg = 0x1c3b2, .blue_reg = 0x1c3b2}, + {.red_reg = 0x1c438, .green_reg = 0x1c438, .blue_reg = 0x1c438}, + {.red_reg = 0x1c4ba, .green_reg = 0x1c4ba, .blue_reg = 0x1c4ba}, + {.red_reg = 0x1c539, .green_reg = 0x1c539, .blue_reg = 0x1c539}, + {.red_reg = 0x1c5b5, .green_reg = 0x1c5b5, .blue_reg = 0x1c5b5}, + {.red_reg = 0x1c62f, .green_reg = 0x1c62f, .blue_reg = 0x1c62f}, + {.red_reg = 0x1c6a5, .green_reg = 0x1c6a5, .blue_reg = 0x1c6a5}, + {.red_reg = 0x1c719, .green_reg = 0x1c719, .blue_reg = 0x1c719}, + {.red_reg = 0x1c78b, .green_reg = 0x1c78b, .blue_reg = 0x1c78b}, + {.red_reg = 0x1c7fa, .green_reg = 0x1c7fa, .blue_reg = 0x1c7fa}, + {.red_reg = 0x1c868, .green_reg = 0x1c868, .blue_reg = 0x1c868}, + {.red_reg = 0x1c8d3, .green_reg = 0x1c8d3, .blue_reg = 0x1c8d3}, + {.red_reg = 0x1c9a3, .green_reg = 0x1c9a3, .blue_reg = 0x1c9a3}, + {.red_reg = 0x1ca6d, .green_reg = 0x1ca6d, .blue_reg = 0x1ca6d}, + {.red_reg = 0x1cb30, .green_reg = 0x1cb30, .blue_reg = 0x1cb30}, + {.red_reg = 0x1cbee, .green_reg = 0x1cbee, .blue_reg = 0x1cbee}, + {.red_reg = 0x1cca5, .green_reg = 0x1cca5, .blue_reg = 0x1cca5}, + {.red_reg = 0x1cd58, .green_reg = 0x1cd58, .blue_reg = 0x1cd58}, + {.red_reg = 0x1ce06, .green_reg = 0x1ce06, .blue_reg = 0x1ce06}, + {.red_reg = 0x1ceb0, .green_reg = 0x1ceb0, .blue_reg = 0x1ceb0}, + {.red_reg = 0x1cf56, .green_reg = 0x1cf56, .blue_reg = 0x1cf56}, + {.red_reg = 0x1cff8, .green_reg = 0x1cff8, .blue_reg = 0x1cff8}, + {.red_reg = 0x1d04b, .green_reg = 0x1d04b, .blue_reg = 0x1d04b}, + {.red_reg = 0x1d098, .green_reg = 0x1d098, .blue_reg = 0x1d098}, + {.red_reg = 0x1d0e4, .green_reg = 0x1d0e4, .blue_reg = 0x1d0e4}, + {.red_reg = 0x1d12e, .green_reg = 0x1d12e, .blue_reg = 0x1d12e}, + {.red_reg = 0x1d177, .green_reg = 0x1d177, .blue_reg = 0x1d177}, + {.red_reg = 0x1d1bf, .green_reg = 0x1d1bf, .blue_reg = 0x1d1bf}, + {.red_reg = 0x1d24a, .green_reg = 0x1d24a, .blue_reg = 0x1d24a}, + {.red_reg = 0x1d2d1, .green_reg = 0x1d2d1, .blue_reg = 0x1d2d1}, + {.red_reg = 0x1d353, .green_reg = 0x1d353, .blue_reg = 0x1d353}, + {.red_reg = 0x1d3d1, .green_reg = 0x1d3d1, .blue_reg = 0x1d3d1}, + {.red_reg = 0x1d44c, .green_reg = 0x1d44c, .blue_reg = 0x1d44c}, + {.red_reg = 0x1d4c3, .green_reg = 0x1d4c3, .blue_reg = 0x1d4c3}, + {.red_reg = 0x1d538, .green_reg = 0x1d538, .blue_reg = 0x1d538}, + {.red_reg = 0x1d5a9, .green_reg = 0x1d5a9, .blue_reg = 0x1d5a9}, + {.red_reg = 0x1d618, .green_reg = 0x1d618, .blue_reg = 0x1d618}, + {.red_reg = 0x1d684, .green_reg = 0x1d684, .blue_reg = 0x1d684}, + {.red_reg = 0x1d6ed, .green_reg = 0x1d6ed, .blue_reg = 0x1d6ed}, + {.red_reg = 0x1d755, .green_reg = 0x1d755, .blue_reg = 0x1d755}, + {.red_reg = 0x1d7ba, .green_reg = 0x1d7ba, .blue_reg = 0x1d7ba}, + {.red_reg = 0x1d81d, .green_reg = 0x1d81d, .blue_reg = 0x1d81d}, + {.red_reg = 0x1d87e, .green_reg = 0x1d87e, .blue_reg = 0x1d87e}, + {.red_reg = 0x1d8de, .green_reg = 0x1d8de, .blue_reg = 0x1d8de}, + {.red_reg = 0x1d998, .green_reg = 0x1d998, .blue_reg = 0x1d998}, + {.red_reg = 0x1da4b, .green_reg = 0x1da4b, .blue_reg = 0x1da4b}, + {.red_reg = 0x1daf9, .green_reg = 0x1daf9, .blue_reg = 0x1daf9}, + {.red_reg = 0x1dba2, .green_reg = 0x1dba2, .blue_reg = 0x1dba2}, + {.red_reg = 0x1dc46, .green_reg = 0x1dc46, .blue_reg = 0x1dc46}, + {.red_reg = 0x1dce5, .green_reg = 0x1dce5, .blue_reg = 0x1dce5}, + {.red_reg = 0x1dd80, .green_reg = 0x1dd80, .blue_reg = 0x1dd80}, + {.red_reg = 0x1de17, .green_reg = 0x1de17, .blue_reg = 0x1de17}, + {.red_reg = 0x1deab, .green_reg = 0x1deab, .blue_reg = 0x1deab}, + {.red_reg = 0x1df3b, .green_reg = 0x1df3b, .blue_reg = 0x1df3b}, + {.red_reg = 0x1dfc8, .green_reg = 0x1dfc8, .blue_reg = 0x1dfc8}, + {.red_reg = 0x1e029, .green_reg = 0x1e029, .blue_reg = 0x1e029}, + {.red_reg = 0x1e06c, .green_reg = 0x1e06c, .blue_reg = 0x1e06c}, + {.red_reg = 0x1e0af, .green_reg = 0x1e0af, .blue_reg = 0x1e0af}, + {.red_reg = 0x1e0f0, .green_reg = 0x1e0f0, .blue_reg = 0x1e0f0}, + {.red_reg = 0x1e12f, .green_reg = 0x1e12f, .blue_reg = 0x1e12f}, + {.red_reg = 0x1e1ab, .green_reg = 0x1e1ab, .blue_reg = 0x1e1ab}, + {.red_reg = 0x1e223, .green_reg = 0x1e223, .blue_reg = 0x1e223}, + {.red_reg = 0x1e297, .green_reg = 0x1e297, .blue_reg = 0x1e297}, + {.red_reg = 0x1e308, .green_reg = 0x1e308, .blue_reg = 0x1e308}, + {.red_reg = 0x1e375, .green_reg = 0x1e375, .blue_reg = 0x1e375}, + {.red_reg = 0x1e3e0, .green_reg = 0x1e3e0, .blue_reg = 0x1e3e0}, + {.red_reg = 0x1e447, .green_reg = 0x1e447, .blue_reg = 0x1e447}, + {.red_reg = 0x1e4ac, .green_reg = 0x1e4ac, .blue_reg = 0x1e4ac}, + {.red_reg = 0x1e50f, .green_reg = 0x1e50f, .blue_reg = 0x1e50f}, + {.red_reg = 0x1e56f, .green_reg = 0x1e56f, .blue_reg = 0x1e56f}, + {.red_reg = 0x1e5cd, .green_reg = 0x1e5cd, .blue_reg = 0x1e5cd}, + {.red_reg = 0x1e629, .green_reg = 0x1e629, .blue_reg = 0x1e629}, + {.red_reg = 0x1e683, .green_reg = 0x1e683, .blue_reg = 0x1e683}, + {.red_reg = 0x1e6dc, .green_reg = 0x1e6dc, .blue_reg = 0x1e6dc}, + {.red_reg = 0x1e732, .green_reg = 0x1e732, .blue_reg = 0x1e732}, + {.red_reg = 0x1e788, .green_reg = 0x1e788, .blue_reg = 0x1e788}, + {.red_reg = 0x1e82d, .green_reg = 0x1e82d, .blue_reg = 0x1e82d}, + {.red_reg = 0x1e8cd, .green_reg = 0x1e8cd, .blue_reg = 0x1e8cd}, + {.red_reg = 0x1e968, .green_reg = 0x1e968, .blue_reg = 0x1e968}, + {.red_reg = 0x1e9fe, .green_reg = 0x1e9fe, .blue_reg = 0x1e9fe}, + {.red_reg = 0x1ea90, .green_reg = 0x1ea90, .blue_reg = 0x1ea90}, + {.red_reg = 0x1eb1e, .green_reg = 0x1eb1e, .blue_reg = 0x1eb1e}, + {.red_reg = 0x1eba8, .green_reg = 0x1eba8, .blue_reg = 0x1eba8}, + {.red_reg = 0x1ec2f, .green_reg = 0x1ec2f, .blue_reg = 0x1ec2f}, + {.red_reg = 0x1ecb3, .green_reg = 0x1ecb3, .blue_reg = 0x1ecb3}, + {.red_reg = 0x1ed33, .green_reg = 0x1ed33, .blue_reg = 0x1ed33}, + {.red_reg = 0x1edb1, .green_reg = 0x1edb1, .blue_reg = 0x1edb1}, + {.red_reg = 0x1ee2c, .green_reg = 0x1ee2c, .blue_reg = 0x1ee2c}, + {.red_reg = 0x1eea4, .green_reg = 0x1eea4, .blue_reg = 0x1eea4}, + {.red_reg = 0x1ef1a, .green_reg = 0x1ef1a, .blue_reg = 0x1ef1a}, + {.red_reg = 0x1ef8e, .green_reg = 0x1ef8e, .blue_reg = 0x1ef8e}, + {.red_reg = 0x1f000, .green_reg = 0x1f000, .blue_reg = 0x1f000}, + {.red_reg = 0x1f000, .green_reg = 0x1f000, .blue_reg = 0x1f000}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}}}, + {.hw_points_num = NUM_OF_LUT_DATA_REGAM_SDR, + .arr_curve_points = {{0x0, 0x3}, {0x8, 0x4}, {0x18, 0x4}, {0x28, 0x4}, {0x38, 0x4}, + {0x48, 0x4}, {0x58, 0x4}, {0x68, 0x4}, {0x78, 0x4}, {0x88, 0x4}, {0x98, 0x4}, + {0xa8, 0x4}, {0xb8, 0x1}, {0xba, 0x0}, {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, + {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, + {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, + {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}}, + .corner_points = {{.red.custom_float_x = 0x13000, + .red.custom_float_y = 0x0, + .red.custom_float_slope = 0x25ff6, + .green.custom_float_x = 0x13000, + .green.custom_float_y = 0x0, + .green.custom_float_slope = 0x25ff6, + .blue.custom_float_x = 0x13000, + .blue.custom_float_y = 0x0, + .blue.custom_float_slope = 0x25ff6}, + {.red.custom_float_x = 0x8000, + .red.custom_float_y = 0x1f000, + .red.custom_float_slope = 0x0, + .green.custom_float_x = 0x8000, + .green.custom_float_y = 0x1f000, + .green.custom_float_slope = 0x0, + .blue.custom_float_x = 0x8000, + .blue.custom_float_y = 0x1f000, + .blue.custom_float_slope = 0x0}}, + .rgb_resulted = {{.red_reg = 0x19ff6, .green_reg = 0x19ff6, .blue_reg = 0x19ff6}, + {.red_reg = 0x1a0cf, .green_reg = 0x1a0cf, .blue_reg = 0x1a0cf}, + {.red_reg = 0x1a192, .green_reg = 0x1a192, .blue_reg = 0x1a192}, + {.red_reg = 0x1a248, .green_reg = 0x1a248, .blue_reg = 0x1a248}, + {.red_reg = 0x1a2f3, .green_reg = 0x1a2f3, .blue_reg = 0x1a2f3}, + {.red_reg = 0x1a398, .green_reg = 0x1a398, .blue_reg = 0x1a398}, + {.red_reg = 0x1a435, .green_reg = 0x1a435, .blue_reg = 0x1a435}, + {.red_reg = 0x1a4c6, .green_reg = 0x1a4c6, .blue_reg = 0x1a4c6}, + {.red_reg = 0x1a55b, .green_reg = 0x1a55b, .blue_reg = 0x1a55b}, + {.red_reg = 0x1a5e7, .green_reg = 0x1a5e7, .blue_reg = 0x1a5e7}, + {.red_reg = 0x1a66e, .green_reg = 0x1a66e, .blue_reg = 0x1a66e}, + {.red_reg = 0x1a6f1, .green_reg = 0x1a6f1, .blue_reg = 0x1a6f1}, + {.red_reg = 0x1a770, .green_reg = 0x1a770, .blue_reg = 0x1a770}, + {.red_reg = 0x1a7eb, .green_reg = 0x1a7eb, .blue_reg = 0x1a7eb}, + {.red_reg = 0x1a863, .green_reg = 0x1a863, .blue_reg = 0x1a863}, + {.red_reg = 0x1a8d8, .green_reg = 0x1a8d8, .blue_reg = 0x1a8d8}, + {.red_reg = 0x1a949, .green_reg = 0x1a949, .blue_reg = 0x1a949}, + {.red_reg = 0x1a9b8, .green_reg = 0x1a9b8, .blue_reg = 0x1a9b8}, + {.red_reg = 0x1aa25, .green_reg = 0x1aa25, .blue_reg = 0x1aa25}, + {.red_reg = 0x1aa8f, .green_reg = 0x1aa8f, .blue_reg = 0x1aa8f}, + {.red_reg = 0x1aaf7, .green_reg = 0x1aaf7, .blue_reg = 0x1aaf7}, + {.red_reg = 0x1ab5c, .green_reg = 0x1ab5c, .blue_reg = 0x1ab5c}, + {.red_reg = 0x1abc0, .green_reg = 0x1abc0, .blue_reg = 0x1abc0}, + {.red_reg = 0x1ac22, .green_reg = 0x1ac22, .blue_reg = 0x1ac22}, + {.red_reg = 0x1ac82, .green_reg = 0x1ac82, .blue_reg = 0x1ac82}, + {.red_reg = 0x1ad3c, .green_reg = 0x1ad3c, .blue_reg = 0x1ad3c}, + {.red_reg = 0x1adf1, .green_reg = 0x1adf1, .blue_reg = 0x1adf1}, + {.red_reg = 0x1ae9f, .green_reg = 0x1ae9f, .blue_reg = 0x1ae9f}, + {.red_reg = 0x1af49, .green_reg = 0x1af49, .blue_reg = 0x1af49}, + {.red_reg = 0x1afed, .green_reg = 0x1afed, .blue_reg = 0x1afed}, + {.red_reg = 0x1b046, .green_reg = 0x1b046, .blue_reg = 0x1b046}, + {.red_reg = 0x1b094, .green_reg = 0x1b094, .blue_reg = 0x1b094}, + {.red_reg = 0x1b0e0, .green_reg = 0x1b0e0, .blue_reg = 0x1b0e0}, + {.red_reg = 0x1b12a, .green_reg = 0x1b12a, .blue_reg = 0x1b12a}, + {.red_reg = 0x1b173, .green_reg = 0x1b173, .blue_reg = 0x1b173}, + {.red_reg = 0x1b1ba, .green_reg = 0x1b1ba, .blue_reg = 0x1b1ba}, + {.red_reg = 0x1b1ff, .green_reg = 0x1b1ff, .blue_reg = 0x1b1ff}, + {.red_reg = 0x1b243, .green_reg = 0x1b243, .blue_reg = 0x1b243}, + {.red_reg = 0x1b285, .green_reg = 0x1b285, .blue_reg = 0x1b285}, + {.red_reg = 0x1b2c6, .green_reg = 0x1b2c6, .blue_reg = 0x1b2c6}, + {.red_reg = 0x1b306, .green_reg = 0x1b306, .blue_reg = 0x1b306}, + {.red_reg = 0x1b383, .green_reg = 0x1b383, .blue_reg = 0x1b383}, + {.red_reg = 0x1b3fc, .green_reg = 0x1b3fc, .blue_reg = 0x1b3fc}, + {.red_reg = 0x1b470, .green_reg = 0x1b470, .blue_reg = 0x1b470}, + {.red_reg = 0x1b4e1, .green_reg = 0x1b4e1, .blue_reg = 0x1b4e1}, + {.red_reg = 0x1b54f, .green_reg = 0x1b54f, .blue_reg = 0x1b54f}, + {.red_reg = 0x1b5ba, .green_reg = 0x1b5ba, .blue_reg = 0x1b5ba}, + {.red_reg = 0x1b622, .green_reg = 0x1b622, .blue_reg = 0x1b622}, + {.red_reg = 0x1b687, .green_reg = 0x1b687, .blue_reg = 0x1b687}, + {.red_reg = 0x1b6ea, .green_reg = 0x1b6ea, .blue_reg = 0x1b6ea}, + {.red_reg = 0x1b74b, .green_reg = 0x1b74b, .blue_reg = 0x1b74b}, + {.red_reg = 0x1b7a9, .green_reg = 0x1b7a9, .blue_reg = 0x1b7a9}, + {.red_reg = 0x1b806, .green_reg = 0x1b806, .blue_reg = 0x1b806}, + {.red_reg = 0x1b860, .green_reg = 0x1b860, .blue_reg = 0x1b860}, + {.red_reg = 0x1b8b9, .green_reg = 0x1b8b9, .blue_reg = 0x1b8b9}, + {.red_reg = 0x1b910, .green_reg = 0x1b910, .blue_reg = 0x1b910}, + {.red_reg = 0x1b965, .green_reg = 0x1b965, .blue_reg = 0x1b965}, + {.red_reg = 0x1ba0c, .green_reg = 0x1ba0c, .blue_reg = 0x1ba0c}, + {.red_reg = 0x1baad, .green_reg = 0x1baad, .blue_reg = 0x1baad}, + {.red_reg = 0x1bb48, .green_reg = 0x1bb48, .blue_reg = 0x1bb48}, + {.red_reg = 0x1bbdf, .green_reg = 0x1bbdf, .blue_reg = 0x1bbdf}, + {.red_reg = 0x1bc72, .green_reg = 0x1bc72, .blue_reg = 0x1bc72}, + {.red_reg = 0x1bd00, .green_reg = 0x1bd00, .blue_reg = 0x1bd00}, + {.red_reg = 0x1bd8b, .green_reg = 0x1bd8b, .blue_reg = 0x1bd8b}, + {.red_reg = 0x1be12, .green_reg = 0x1be12, .blue_reg = 0x1be12}, + {.red_reg = 0x1be96, .green_reg = 0x1be96, .blue_reg = 0x1be96}, + {.red_reg = 0x1bf17, .green_reg = 0x1bf17, .blue_reg = 0x1bf17}, + {.red_reg = 0x1bf95, .green_reg = 0x1bf95, .blue_reg = 0x1bf95}, + {.red_reg = 0x1c008, .green_reg = 0x1c008, .blue_reg = 0x1c008}, + {.red_reg = 0x1c045, .green_reg = 0x1c045, .blue_reg = 0x1c045}, + {.red_reg = 0x1c080, .green_reg = 0x1c080, .blue_reg = 0x1c080}, + {.red_reg = 0x1c0ba, .green_reg = 0x1c0ba, .blue_reg = 0x1c0ba}, + {.red_reg = 0x1c0f3, .green_reg = 0x1c0f3, .blue_reg = 0x1c0f3}, + {.red_reg = 0x1c162, .green_reg = 0x1c162, .blue_reg = 0x1c162}, + {.red_reg = 0x1c1cd, .green_reg = 0x1c1cd, .blue_reg = 0x1c1cd}, + {.red_reg = 0x1c235, .green_reg = 0x1c235, .blue_reg = 0x1c235}, + {.red_reg = 0x1c29a, .green_reg = 0x1c29a, .blue_reg = 0x1c29a}, + {.red_reg = 0x1c2fc, .green_reg = 0x1c2fc, .blue_reg = 0x1c2fc}, + {.red_reg = 0x1c35b, .green_reg = 0x1c35b, .blue_reg = 0x1c35b}, + {.red_reg = 0x1c3b7, .green_reg = 0x1c3b7, .blue_reg = 0x1c3b7}, + {.red_reg = 0x1c412, .green_reg = 0x1c412, .blue_reg = 0x1c412}, + {.red_reg = 0x1c46a, .green_reg = 0x1c46a, .blue_reg = 0x1c46a}, + {.red_reg = 0x1c4c0, .green_reg = 0x1c4c0, .blue_reg = 0x1c4c0}, + {.red_reg = 0x1c514, .green_reg = 0x1c514, .blue_reg = 0x1c514}, + {.red_reg = 0x1c567, .green_reg = 0x1c567, .blue_reg = 0x1c567}, + {.red_reg = 0x1c5b7, .green_reg = 0x1c5b7, .blue_reg = 0x1c5b7}, + {.red_reg = 0x1c606, .green_reg = 0x1c606, .blue_reg = 0x1c606}, + {.red_reg = 0x1c654, .green_reg = 0x1c654, .blue_reg = 0x1c654}, + {.red_reg = 0x1c6a0, .green_reg = 0x1c6a0, .blue_reg = 0x1c6a0}, + {.red_reg = 0x1c734, .green_reg = 0x1c734, .blue_reg = 0x1c734}, + {.red_reg = 0x1c7c3, .green_reg = 0x1c7c3, .blue_reg = 0x1c7c3}, + {.red_reg = 0x1c84e, .green_reg = 0x1c84e, .blue_reg = 0x1c84e}, + {.red_reg = 0x1c8d5, .green_reg = 0x1c8d5, .blue_reg = 0x1c8d5}, + {.red_reg = 0x1c957, .green_reg = 0x1c957, .blue_reg = 0x1c957}, + {.red_reg = 0x1c9d6, .green_reg = 0x1c9d6, .blue_reg = 0x1c9d6}, + {.red_reg = 0x1ca52, .green_reg = 0x1ca52, .blue_reg = 0x1ca52}, + {.red_reg = 0x1caca, .green_reg = 0x1caca, .blue_reg = 0x1caca}, + {.red_reg = 0x1cb40, .green_reg = 0x1cb40, .blue_reg = 0x1cb40}, + {.red_reg = 0x1cbb3, .green_reg = 0x1cbb3, .blue_reg = 0x1cbb3}, + {.red_reg = 0x1cc23, .green_reg = 0x1cc23, .blue_reg = 0x1cc23}, + {.red_reg = 0x1cc91, .green_reg = 0x1cc91, .blue_reg = 0x1cc91}, + {.red_reg = 0x1ccfd, .green_reg = 0x1ccfd, .blue_reg = 0x1ccfd}, + {.red_reg = 0x1cd67, .green_reg = 0x1cd67, .blue_reg = 0x1cd67}, + {.red_reg = 0x1cdce, .green_reg = 0x1cdce, .blue_reg = 0x1cdce}, + {.red_reg = 0x1ce34, .green_reg = 0x1ce34, .blue_reg = 0x1ce34}, + {.red_reg = 0x1cefa, .green_reg = 0x1cefa, .blue_reg = 0x1cefa}, + {.red_reg = 0x1cfb9, .green_reg = 0x1cfb9, .blue_reg = 0x1cfb9}, + {.red_reg = 0x1d039, .green_reg = 0x1d039, .blue_reg = 0x1d039}, + {.red_reg = 0x1d092, .green_reg = 0x1d092, .blue_reg = 0x1d092}, + {.red_reg = 0x1d0e9, .green_reg = 0x1d0e9, .blue_reg = 0x1d0e9}, + {.red_reg = 0x1d13e, .green_reg = 0x1d13e, .blue_reg = 0x1d13e}, + {.red_reg = 0x1d191, .green_reg = 0x1d191, .blue_reg = 0x1d191}, + {.red_reg = 0x1d1e1, .green_reg = 0x1d1e1, .blue_reg = 0x1d1e1}, + {.red_reg = 0x1d230, .green_reg = 0x1d230, .blue_reg = 0x1d230}, + {.red_reg = 0x1d27c, .green_reg = 0x1d27c, .blue_reg = 0x1d27c}, + {.red_reg = 0x1d2c7, .green_reg = 0x1d2c7, .blue_reg = 0x1d2c7}, + {.red_reg = 0x1d311, .green_reg = 0x1d311, .blue_reg = 0x1d311}, + {.red_reg = 0x1d359, .green_reg = 0x1d359, .blue_reg = 0x1d359}, + {.red_reg = 0x1d39f, .green_reg = 0x1d39f, .blue_reg = 0x1d39f}, + {.red_reg = 0x1d3e4, .green_reg = 0x1d3e4, .blue_reg = 0x1d3e4}, + {.red_reg = 0x1d428, .green_reg = 0x1d428, .blue_reg = 0x1d428}, + {.red_reg = 0x1d4ac, .green_reg = 0x1d4ac, .blue_reg = 0x1d4ac}, + {.red_reg = 0x1d52c, .green_reg = 0x1d52c, .blue_reg = 0x1d52c}, + {.red_reg = 0x1d5a7, .green_reg = 0x1d5a7, .blue_reg = 0x1d5a7}, + {.red_reg = 0x1d61f, .green_reg = 0x1d61f, .blue_reg = 0x1d61f}, + {.red_reg = 0x1d693, .green_reg = 0x1d693, .blue_reg = 0x1d693}, + {.red_reg = 0x1d704, .green_reg = 0x1d704, .blue_reg = 0x1d704}, + {.red_reg = 0x1d773, .green_reg = 0x1d773, .blue_reg = 0x1d773}, + {.red_reg = 0x1d7de, .green_reg = 0x1d7de, .blue_reg = 0x1d7de}, + {.red_reg = 0x1d847, .green_reg = 0x1d847, .blue_reg = 0x1d847}, + {.red_reg = 0x1d8ad, .green_reg = 0x1d8ad, .blue_reg = 0x1d8ad}, + {.red_reg = 0x1d911, .green_reg = 0x1d911, .blue_reg = 0x1d911}, + {.red_reg = 0x1d973, .green_reg = 0x1d973, .blue_reg = 0x1d973}, + {.red_reg = 0x1d9d3, .green_reg = 0x1d9d3, .blue_reg = 0x1d9d3}, + {.red_reg = 0x1da31, .green_reg = 0x1da31, .blue_reg = 0x1da31}, + {.red_reg = 0x1da8e, .green_reg = 0x1da8e, .blue_reg = 0x1da8e}, + {.red_reg = 0x1dae8, .green_reg = 0x1dae8, .blue_reg = 0x1dae8}, + {.red_reg = 0x1db98, .green_reg = 0x1db98, .blue_reg = 0x1db98}, + {.red_reg = 0x1dc43, .green_reg = 0x1dc43, .blue_reg = 0x1dc43}, + {.red_reg = 0x1dce7, .green_reg = 0x1dce7, .blue_reg = 0x1dce7}, + {.red_reg = 0x1dd87, .green_reg = 0x1dd87, .blue_reg = 0x1dd87}, + {.red_reg = 0x1de23, .green_reg = 0x1de23, .blue_reg = 0x1de23}, + {.red_reg = 0x1deba, .green_reg = 0x1deba, .blue_reg = 0x1deba}, + {.red_reg = 0x1df4d, .green_reg = 0x1df4d, .blue_reg = 0x1df4d}, + {.red_reg = 0x1dfdc, .green_reg = 0x1dfdc, .blue_reg = 0x1dfdc}, + {.red_reg = 0x1e034, .green_reg = 0x1e034, .blue_reg = 0x1e034}, + {.red_reg = 0x1e078, .green_reg = 0x1e078, .blue_reg = 0x1e078}, + {.red_reg = 0x1e0bb, .green_reg = 0x1e0bb, .blue_reg = 0x1e0bb}, + {.red_reg = 0x1e0fc, .green_reg = 0x1e0fc, .blue_reg = 0x1e0fc}, + {.red_reg = 0x1e13c, .green_reg = 0x1e13c, .blue_reg = 0x1e13c}, + {.red_reg = 0x1e17b, .green_reg = 0x1e17b, .blue_reg = 0x1e17b}, + {.red_reg = 0x1e1b9, .green_reg = 0x1e1b9, .blue_reg = 0x1e1b9}, + {.red_reg = 0x1e1f5, .green_reg = 0x1e1f5, .blue_reg = 0x1e1f5}, + {.red_reg = 0x1e26b, .green_reg = 0x1e26b, .blue_reg = 0x1e26b}, + {.red_reg = 0x1e2dc, .green_reg = 0x1e2dc, .blue_reg = 0x1e2dc}, + {.red_reg = 0x1e34a, .green_reg = 0x1e34a, .blue_reg = 0x1e34a}, + {.red_reg = 0x1e3b5, .green_reg = 0x1e3b5, .blue_reg = 0x1e3b5}, + {.red_reg = 0x1e41d, .green_reg = 0x1e41d, .blue_reg = 0x1e41d}, + {.red_reg = 0x1e481, .green_reg = 0x1e481, .blue_reg = 0x1e481}, + {.red_reg = 0x1e4e4, .green_reg = 0x1e4e4, .blue_reg = 0x1e4e4}, + {.red_reg = 0x1e543, .green_reg = 0x1e543, .blue_reg = 0x1e543}, + {.red_reg = 0x1e5a1, .green_reg = 0x1e5a1, .blue_reg = 0x1e5a1}, + {.red_reg = 0x1e5fc, .green_reg = 0x1e5fc, .blue_reg = 0x1e5fc}, + {.red_reg = 0x1e655, .green_reg = 0x1e655, .blue_reg = 0x1e655}, + {.red_reg = 0x1e6ac, .green_reg = 0x1e6ac, .blue_reg = 0x1e6ac}, + {.red_reg = 0x1e702, .green_reg = 0x1e702, .blue_reg = 0x1e702}, + {.red_reg = 0x1e756, .green_reg = 0x1e756, .blue_reg = 0x1e756}, + {.red_reg = 0x1e7a8, .green_reg = 0x1e7a8, .blue_reg = 0x1e7a8}, + {.red_reg = 0x1e7f9, .green_reg = 0x1e7f9, .blue_reg = 0x1e7f9}, + {.red_reg = 0x1e896, .green_reg = 0x1e896, .blue_reg = 0x1e896}, + {.red_reg = 0x1e92d, .green_reg = 0x1e92d, .blue_reg = 0x1e92d}, + {.red_reg = 0x1e9c0, .green_reg = 0x1e9c0, .blue_reg = 0x1e9c0}, + {.red_reg = 0x1ea4f, .green_reg = 0x1ea4f, .blue_reg = 0x1ea4f}, + {.red_reg = 0x1ead9, .green_reg = 0x1ead9, .blue_reg = 0x1ead9}, + {.red_reg = 0x1eb5f, .green_reg = 0x1eb5f, .blue_reg = 0x1eb5f}, + {.red_reg = 0x1ebe2, .green_reg = 0x1ebe2, .blue_reg = 0x1ebe2}, + {.red_reg = 0x1ec62, .green_reg = 0x1ec62, .blue_reg = 0x1ec62}, + {.red_reg = 0x1ecdf, .green_reg = 0x1ecdf, .blue_reg = 0x1ecdf}, + {.red_reg = 0x1ed59, .green_reg = 0x1ed59, .blue_reg = 0x1ed59}, + {.red_reg = 0x1edd0, .green_reg = 0x1edd0, .blue_reg = 0x1edd0}, + {.red_reg = 0x1ee44, .green_reg = 0x1ee44, .blue_reg = 0x1ee44}, + {.red_reg = 0x1eeb6, .green_reg = 0x1eeb6, .blue_reg = 0x1eeb6}, + {.red_reg = 0x1ef26, .green_reg = 0x1ef26, .blue_reg = 0x1ef26}, + {.red_reg = 0x1ef94, .green_reg = 0x1ef94, .blue_reg = 0x1ef94}, + {.red_reg = 0x1f000, .green_reg = 0x1f000, .blue_reg = 0x1f000}, + {.red_reg = 0x1f000, .green_reg = 0x1f000, .blue_reg = 0x1f000}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}}}, + {.hw_points_num = NUM_OF_LUT_DATA_REGAM_PQ, + .arr_curve_points = {{0x0, 0x3}, {0x8, 0x3}, {0x10, 0x3}, {0x18, 0x3}, {0x20, 0x3}, + {0x28, 0x3}, {0x30, 0x3}, {0x38, 0x3}, {0x40, 0x3}, {0x48, 0x3}, {0x50, 0x3}, + {0x58, 0x3}, {0x60, 0x3}, {0x68, 0x3}, {0x70, 0x3}, {0x78, 0x3}, {0x80, 0x3}, + {0x88, 0x3}, {0x90, 0x3}, {0x98, 0x3}, {0xa0, 0x3}, {0xa8, 0x3}, {0xb0, 0x3}, + {0xb8, 0x3}, {0xc0, 0x3}, {0xc8, 0x1}, {0xca, 0x0}, {0x0, 0x0}, {0x0, 0x0}, + {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}}, + .corner_points = {{.red.custom_float_x = 0x6000, + .red.custom_float_y = 0x0, + .red.custom_float_slope = 0x2ec7c, + .green.custom_float_x = 0x6000, + .green.custom_float_y = 0x0, + .green.custom_float_slope = 0x2ec7c, + .blue.custom_float_x = 0x6000, + .blue.custom_float_y = 0x0, + .blue.custom_float_slope = 0x2ec7c}, + {.red.custom_float_x = 0x8000, + .red.custom_float_y = 0x1f000, + .red.custom_float_slope = 0x0, + .green.custom_float_x = 0x8000, + .green.custom_float_y = 0x1f000, + .green.custom_float_slope = 0x0, + .blue.custom_float_x = 0x8000, + .blue.custom_float_y = 0x1f000, + .blue.custom_float_slope = 0x0}}, + .rgb_resulted = {{.red_reg = 0x15c7c, .green_reg = 0x15c7c, .blue_reg = 0x15c7c}, + {.red_reg = 0x16006, .green_reg = 0x16006, .blue_reg = 0x16006}, + {.red_reg = 0x161ce, .green_reg = 0x161ce, .blue_reg = 0x161ce}, + {.red_reg = 0x16395, .green_reg = 0x16395, .blue_reg = 0x16395}, + {.red_reg = 0x1655d, .green_reg = 0x1655d, .blue_reg = 0x1655d}, + {.red_reg = 0x16725, .green_reg = 0x16725, .blue_reg = 0x16725}, + {.red_reg = 0x168ed, .green_reg = 0x168ed, .blue_reg = 0x168ed}, + {.red_reg = 0x16ab5, .green_reg = 0x16ab5, .blue_reg = 0x16ab5}, + {.red_reg = 0x16c7c, .green_reg = 0x16c7c, .blue_reg = 0x16c7c}, + {.red_reg = 0x17006, .green_reg = 0x17006, .blue_reg = 0x17006}, + {.red_reg = 0x171ce, .green_reg = 0x171ce, .blue_reg = 0x171ce}, + {.red_reg = 0x17395, .green_reg = 0x17395, .blue_reg = 0x17395}, + {.red_reg = 0x1755d, .green_reg = 0x1755d, .blue_reg = 0x1755d}, + {.red_reg = 0x17725, .green_reg = 0x17725, .blue_reg = 0x17725}, + {.red_reg = 0x178ed, .green_reg = 0x178ed, .blue_reg = 0x178ed}, + {.red_reg = 0x17ab5, .green_reg = 0x17ab5, .blue_reg = 0x17ab5}, + {.red_reg = 0x17c7c, .green_reg = 0x17c7c, .blue_reg = 0x17c7c}, + {.red_reg = 0x17e68, .green_reg = 0x17e68, .blue_reg = 0x17e68}, + {.red_reg = 0x1801b, .green_reg = 0x1801b, .blue_reg = 0x1801b}, + {.red_reg = 0x180fa, .green_reg = 0x180fa, .blue_reg = 0x180fa}, + {.red_reg = 0x181ce, .green_reg = 0x181ce, .blue_reg = 0x181ce}, + {.red_reg = 0x1829b, .green_reg = 0x1829b, .blue_reg = 0x1829b}, + {.red_reg = 0x18361, .green_reg = 0x18361, .blue_reg = 0x18361}, + {.red_reg = 0x1841e, .green_reg = 0x1841e, .blue_reg = 0x1841e}, + {.red_reg = 0x184d4, .green_reg = 0x184d4, .blue_reg = 0x184d4}, + {.red_reg = 0x18632, .green_reg = 0x18632, .blue_reg = 0x18632}, + {.red_reg = 0x1877d, .green_reg = 0x1877d, .blue_reg = 0x1877d}, + {.red_reg = 0x188b8, .green_reg = 0x188b8, .blue_reg = 0x188b8}, + {.red_reg = 0x189e2, .green_reg = 0x189e2, .blue_reg = 0x189e2}, + {.red_reg = 0x18b02, .green_reg = 0x18b02, .blue_reg = 0x18b02}, + {.red_reg = 0x18c14, .green_reg = 0x18c14, .blue_reg = 0x18c14}, + {.red_reg = 0x18d1f, .green_reg = 0x18d1f, .blue_reg = 0x18d1f}, + {.red_reg = 0x18e1f, .green_reg = 0x18e1f, .blue_reg = 0x18e1f}, + {.red_reg = 0x19003, .green_reg = 0x19003, .blue_reg = 0x19003}, + {.red_reg = 0x190e9, .green_reg = 0x190e9, .blue_reg = 0x190e9}, + {.red_reg = 0x191c3, .green_reg = 0x191c3, .blue_reg = 0x191c3}, + {.red_reg = 0x19292, .green_reg = 0x19292, .blue_reg = 0x19292}, + {.red_reg = 0x19358, .green_reg = 0x19358, .blue_reg = 0x19358}, + {.red_reg = 0x19416, .green_reg = 0x19416, .blue_reg = 0x19416}, + {.red_reg = 0x194cc, .green_reg = 0x194cc, .blue_reg = 0x194cc}, + {.red_reg = 0x1957c, .green_reg = 0x1957c, .blue_reg = 0x1957c}, + {.red_reg = 0x196ca, .green_reg = 0x196ca, .blue_reg = 0x196ca}, + {.red_reg = 0x19803, .green_reg = 0x19803, .blue_reg = 0x19803}, + {.red_reg = 0x1992b, .green_reg = 0x1992b, .blue_reg = 0x1992b}, + {.red_reg = 0x19a44, .green_reg = 0x19a44, .blue_reg = 0x19a44}, + {.red_reg = 0x19b50, .green_reg = 0x19b50, .blue_reg = 0x19b50}, + {.red_reg = 0x19c50, .green_reg = 0x19c50, .blue_reg = 0x19c50}, + {.red_reg = 0x19d46, .green_reg = 0x19d46, .blue_reg = 0x19d46}, + {.red_reg = 0x19e33, .green_reg = 0x19e33, .blue_reg = 0x19e33}, + {.red_reg = 0x19ff2, .green_reg = 0x19ff2, .blue_reg = 0x19ff2}, + {.red_reg = 0x1a0cb, .green_reg = 0x1a0cb, .blue_reg = 0x1a0cb}, + {.red_reg = 0x1a190, .green_reg = 0x1a190, .blue_reg = 0x1a190}, + {.red_reg = 0x1a24b, .green_reg = 0x1a24b, .blue_reg = 0x1a24b}, + {.red_reg = 0x1a2fc, .green_reg = 0x1a2fc, .blue_reg = 0x1a2fc}, + {.red_reg = 0x1a3a6, .green_reg = 0x1a3a6, .blue_reg = 0x1a3a6}, + {.red_reg = 0x1a448, .green_reg = 0x1a448, .blue_reg = 0x1a448}, + {.red_reg = 0x1a4e4, .green_reg = 0x1a4e4, .blue_reg = 0x1a4e4}, + {.red_reg = 0x1a60a, .green_reg = 0x1a60a, .blue_reg = 0x1a60a}, + {.red_reg = 0x1a71c, .green_reg = 0x1a71c, .blue_reg = 0x1a71c}, + {.red_reg = 0x1a81e, .green_reg = 0x1a81e, .blue_reg = 0x1a81e}, + {.red_reg = 0x1a911, .green_reg = 0x1a911, .blue_reg = 0x1a911}, + {.red_reg = 0x1a9f8, .green_reg = 0x1a9f8, .blue_reg = 0x1a9f8}, + {.red_reg = 0x1aad3, .green_reg = 0x1aad3, .blue_reg = 0x1aad3}, + {.red_reg = 0x1aba5, .green_reg = 0x1aba5, .blue_reg = 0x1aba5}, + {.red_reg = 0x1ac6e, .green_reg = 0x1ac6e, .blue_reg = 0x1ac6e}, + {.red_reg = 0x1ade8, .green_reg = 0x1ade8, .blue_reg = 0x1ade8}, + {.red_reg = 0x1af48, .green_reg = 0x1af48, .blue_reg = 0x1af48}, + {.red_reg = 0x1b048, .green_reg = 0x1b048, .blue_reg = 0x1b048}, + {.red_reg = 0x1b0e3, .green_reg = 0x1b0e3, .blue_reg = 0x1b0e3}, + {.red_reg = 0x1b176, .green_reg = 0x1b176, .blue_reg = 0x1b176}, + {.red_reg = 0x1b201, .green_reg = 0x1b201, .blue_reg = 0x1b201}, + {.red_reg = 0x1b285, .green_reg = 0x1b285, .blue_reg = 0x1b285}, + {.red_reg = 0x1b304, .green_reg = 0x1b304, .blue_reg = 0x1b304}, + {.red_reg = 0x1b3f2, .green_reg = 0x1b3f2, .blue_reg = 0x1b3f2}, + {.red_reg = 0x1b4cf, .green_reg = 0x1b4cf, .blue_reg = 0x1b4cf}, + {.red_reg = 0x1b59c, .green_reg = 0x1b59c, .blue_reg = 0x1b59c}, + {.red_reg = 0x1b65e, .green_reg = 0x1b65e, .blue_reg = 0x1b65e}, + {.red_reg = 0x1b714, .green_reg = 0x1b714, .blue_reg = 0x1b714}, + {.red_reg = 0x1b7c0, .green_reg = 0x1b7c0, .blue_reg = 0x1b7c0}, + {.red_reg = 0x1b864, .green_reg = 0x1b864, .blue_reg = 0x1b864}, + {.red_reg = 0x1b901, .green_reg = 0x1b901, .blue_reg = 0x1b901}, + {.red_reg = 0x1ba26, .green_reg = 0x1ba26, .blue_reg = 0x1ba26}, + {.red_reg = 0x1bb35, .green_reg = 0x1bb35, .blue_reg = 0x1bb35}, + {.red_reg = 0x1bc31, .green_reg = 0x1bc31, .blue_reg = 0x1bc31}, + {.red_reg = 0x1bd1d, .green_reg = 0x1bd1d, .blue_reg = 0x1bd1d}, + {.red_reg = 0x1bdfa, .green_reg = 0x1bdfa, .blue_reg = 0x1bdfa}, + {.red_reg = 0x1becc, .green_reg = 0x1becc, .blue_reg = 0x1becc}, + {.red_reg = 0x1bf93, .green_reg = 0x1bf93, .blue_reg = 0x1bf93}, + {.red_reg = 0x1c028, .green_reg = 0x1c028, .blue_reg = 0x1c028}, + {.red_reg = 0x1c0d9, .green_reg = 0x1c0d9, .blue_reg = 0x1c0d9}, + {.red_reg = 0x1c17b, .green_reg = 0x1c17b, .blue_reg = 0x1c17b}, + {.red_reg = 0x1c212, .green_reg = 0x1c212, .blue_reg = 0x1c212}, + {.red_reg = 0x1c29f, .green_reg = 0x1c29f, .blue_reg = 0x1c29f}, + {.red_reg = 0x1c323, .green_reg = 0x1c323, .blue_reg = 0x1c323}, + {.red_reg = 0x1c3a0, .green_reg = 0x1c3a0, .blue_reg = 0x1c3a0}, + {.red_reg = 0x1c416, .green_reg = 0x1c416, .blue_reg = 0x1c416}, + {.red_reg = 0x1c486, .green_reg = 0x1c486, .blue_reg = 0x1c486}, + {.red_reg = 0x1c557, .green_reg = 0x1c557, .blue_reg = 0x1c557}, + {.red_reg = 0x1c616, .green_reg = 0x1c616, .blue_reg = 0x1c616}, + {.red_reg = 0x1c6c7, .green_reg = 0x1c6c7, .blue_reg = 0x1c6c7}, + {.red_reg = 0x1c76c, .green_reg = 0x1c76c, .blue_reg = 0x1c76c}, + {.red_reg = 0x1c807, .green_reg = 0x1c807, .blue_reg = 0x1c807}, + {.red_reg = 0x1c898, .green_reg = 0x1c898, .blue_reg = 0x1c898}, + {.red_reg = 0x1c921, .green_reg = 0x1c921, .blue_reg = 0x1c921}, + {.red_reg = 0x1c9a3, .green_reg = 0x1c9a3, .blue_reg = 0x1c9a3}, + {.red_reg = 0x1ca95, .green_reg = 0x1ca95, .blue_reg = 0x1ca95}, + {.red_reg = 0x1cb72, .green_reg = 0x1cb72, .blue_reg = 0x1cb72}, + {.red_reg = 0x1cc3e, .green_reg = 0x1cc3e, .blue_reg = 0x1cc3e}, + {.red_reg = 0x1ccfb, .green_reg = 0x1ccfb, .blue_reg = 0x1ccfb}, + {.red_reg = 0x1cdac, .green_reg = 0x1cdac, .blue_reg = 0x1cdac}, + {.red_reg = 0x1ce52, .green_reg = 0x1ce52, .blue_reg = 0x1ce52}, + {.red_reg = 0x1ceee, .green_reg = 0x1ceee, .blue_reg = 0x1ceee}, + {.red_reg = 0x1cf82, .green_reg = 0x1cf82, .blue_reg = 0x1cf82}, + {.red_reg = 0x1d04a, .green_reg = 0x1d04a, .blue_reg = 0x1d04a}, + {.red_reg = 0x1d0c7, .green_reg = 0x1d0c7, .blue_reg = 0x1d0c7}, + {.red_reg = 0x1d13a, .green_reg = 0x1d13a, .blue_reg = 0x1d13a}, + {.red_reg = 0x1d1a5, .green_reg = 0x1d1a5, .blue_reg = 0x1d1a5}, + {.red_reg = 0x1d208, .green_reg = 0x1d208, .blue_reg = 0x1d208}, + {.red_reg = 0x1d265, .green_reg = 0x1d265, .blue_reg = 0x1d265}, + {.red_reg = 0x1d2bc, .green_reg = 0x1d2bc, .blue_reg = 0x1d2bc}, + {.red_reg = 0x1d30f, .green_reg = 0x1d30f, .blue_reg = 0x1d30f}, + {.red_reg = 0x1d3a8, .green_reg = 0x1d3a8, .blue_reg = 0x1d3a8}, + {.red_reg = 0x1d433, .green_reg = 0x1d433, .blue_reg = 0x1d433}, + {.red_reg = 0x1d4b3, .green_reg = 0x1d4b3, .blue_reg = 0x1d4b3}, + {.red_reg = 0x1d528, .green_reg = 0x1d528, .blue_reg = 0x1d528}, + {.red_reg = 0x1d596, .green_reg = 0x1d596, .blue_reg = 0x1d596}, + {.red_reg = 0x1d5fc, .green_reg = 0x1d5fc, .blue_reg = 0x1d5fc}, + {.red_reg = 0x1d65d, .green_reg = 0x1d65d, .blue_reg = 0x1d65d}, + {.red_reg = 0x1d6b7, .green_reg = 0x1d6b7, .blue_reg = 0x1d6b7}, + {.red_reg = 0x1d75f, .green_reg = 0x1d75f, .blue_reg = 0x1d75f}, + {.red_reg = 0x1d7f6, .green_reg = 0x1d7f6, .blue_reg = 0x1d7f6}, + {.red_reg = 0x1d881, .green_reg = 0x1d881, .blue_reg = 0x1d881}, + {.red_reg = 0x1d901, .green_reg = 0x1d901, .blue_reg = 0x1d901}, + {.red_reg = 0x1d978, .green_reg = 0x1d978, .blue_reg = 0x1d978}, + {.red_reg = 0x1d9e7, .green_reg = 0x1d9e7, .blue_reg = 0x1d9e7}, + {.red_reg = 0x1da4f, .green_reg = 0x1da4f, .blue_reg = 0x1da4f}, + {.red_reg = 0x1dab1, .green_reg = 0x1dab1, .blue_reg = 0x1dab1}, + {.red_reg = 0x1db65, .green_reg = 0x1db65, .blue_reg = 0x1db65}, + {.red_reg = 0x1dc08, .green_reg = 0x1dc08, .blue_reg = 0x1dc08}, + {.red_reg = 0x1dc9d, .green_reg = 0x1dc9d, .blue_reg = 0x1dc9d}, + {.red_reg = 0x1dd26, .green_reg = 0x1dd26, .blue_reg = 0x1dd26}, + {.red_reg = 0x1dda5, .green_reg = 0x1dda5, .blue_reg = 0x1dda5}, + {.red_reg = 0x1de1b, .green_reg = 0x1de1b, .blue_reg = 0x1de1b}, + {.red_reg = 0x1de89, .green_reg = 0x1de89, .blue_reg = 0x1de89}, + {.red_reg = 0x1def1, .green_reg = 0x1def1, .blue_reg = 0x1def1}, + {.red_reg = 0x1dfb1, .green_reg = 0x1dfb1, .blue_reg = 0x1dfb1}, + {.red_reg = 0x1e02e, .green_reg = 0x1e02e, .blue_reg = 0x1e02e}, + {.red_reg = 0x1e07d, .green_reg = 0x1e07d, .blue_reg = 0x1e07d}, + {.red_reg = 0x1e0c5, .green_reg = 0x1e0c5, .blue_reg = 0x1e0c5}, + {.red_reg = 0x1e107, .green_reg = 0x1e107, .blue_reg = 0x1e107}, + {.red_reg = 0x1e145, .green_reg = 0x1e145, .blue_reg = 0x1e145}, + {.red_reg = 0x1e17f, .green_reg = 0x1e17f, .blue_reg = 0x1e17f}, + {.red_reg = 0x1e1b6, .green_reg = 0x1e1b6, .blue_reg = 0x1e1b6}, + {.red_reg = 0x1e21a, .green_reg = 0x1e21a, .blue_reg = 0x1e21a}, + {.red_reg = 0x1e273, .green_reg = 0x1e273, .blue_reg = 0x1e273}, + {.red_reg = 0x1e2c5, .green_reg = 0x1e2c5, .blue_reg = 0x1e2c5}, + {.red_reg = 0x1e310, .green_reg = 0x1e310, .blue_reg = 0x1e310}, + {.red_reg = 0x1e355, .green_reg = 0x1e355, .blue_reg = 0x1e355}, + {.red_reg = 0x1e395, .green_reg = 0x1e395, .blue_reg = 0x1e395}, + {.red_reg = 0x1e3d1, .green_reg = 0x1e3d1, .blue_reg = 0x1e3d1}, + {.red_reg = 0x1e409, .green_reg = 0x1e409, .blue_reg = 0x1e409}, + {.red_reg = 0x1e470, .green_reg = 0x1e470, .blue_reg = 0x1e470}, + {.red_reg = 0x1e4cd, .green_reg = 0x1e4cd, .blue_reg = 0x1e4cd}, + {.red_reg = 0x1e520, .green_reg = 0x1e520, .blue_reg = 0x1e520}, + {.red_reg = 0x1e56d, .green_reg = 0x1e56d, .blue_reg = 0x1e56d}, + {.red_reg = 0x1e5b4, .green_reg = 0x1e5b4, .blue_reg = 0x1e5b4}, + {.red_reg = 0x1e5f5, .green_reg = 0x1e5f5, .blue_reg = 0x1e5f5}, + {.red_reg = 0x1e633, .green_reg = 0x1e633, .blue_reg = 0x1e633}, + {.red_reg = 0x1e66c, .green_reg = 0x1e66c, .blue_reg = 0x1e66c}, + {.red_reg = 0x1e6d4, .green_reg = 0x1e6d4, .blue_reg = 0x1e6d4}, + {.red_reg = 0x1e732, .green_reg = 0x1e732, .blue_reg = 0x1e732}, + {.red_reg = 0x1e787, .green_reg = 0x1e787, .blue_reg = 0x1e787}, + {.red_reg = 0x1e7d5, .green_reg = 0x1e7d5, .blue_reg = 0x1e7d5}, + {.red_reg = 0x1e81c, .green_reg = 0x1e81c, .blue_reg = 0x1e81c}, + {.red_reg = 0x1e85f, .green_reg = 0x1e85f, .blue_reg = 0x1e85f}, + {.red_reg = 0x1e89c, .green_reg = 0x1e89c, .blue_reg = 0x1e89c}, + {.red_reg = 0x1e8d6, .green_reg = 0x1e8d6, .blue_reg = 0x1e8d6}, + {.red_reg = 0x1e93f, .green_reg = 0x1e93f, .blue_reg = 0x1e93f}, + {.red_reg = 0x1e99d, .green_reg = 0x1e99d, .blue_reg = 0x1e99d}, + {.red_reg = 0x1e9f2, .green_reg = 0x1e9f2, .blue_reg = 0x1e9f2}, + {.red_reg = 0x1ea40, .green_reg = 0x1ea40, .blue_reg = 0x1ea40}, + {.red_reg = 0x1ea88, .green_reg = 0x1ea88, .blue_reg = 0x1ea88}, + {.red_reg = 0x1eaca, .green_reg = 0x1eaca, .blue_reg = 0x1eaca}, + {.red_reg = 0x1eb07, .green_reg = 0x1eb07, .blue_reg = 0x1eb07}, + {.red_reg = 0x1eb41, .green_reg = 0x1eb41, .blue_reg = 0x1eb41}, + {.red_reg = 0x1eba9, .green_reg = 0x1eba9, .blue_reg = 0x1eba9}, + {.red_reg = 0x1ec07, .green_reg = 0x1ec07, .blue_reg = 0x1ec07}, + {.red_reg = 0x1ec5b, .green_reg = 0x1ec5b, .blue_reg = 0x1ec5b}, + {.red_reg = 0x1eca8, .green_reg = 0x1eca8, .blue_reg = 0x1eca8}, + {.red_reg = 0x1ecef, .green_reg = 0x1ecef, .blue_reg = 0x1ecef}, + {.red_reg = 0x1ed30, .green_reg = 0x1ed30, .blue_reg = 0x1ed30}, + {.red_reg = 0x1ed6d, .green_reg = 0x1ed6d, .blue_reg = 0x1ed6d}, + {.red_reg = 0x1eda6, .green_reg = 0x1eda6, .blue_reg = 0x1eda6}, + {.red_reg = 0x1ee0d, .green_reg = 0x1ee0d, .blue_reg = 0x1ee0d}, + {.red_reg = 0x1ee69, .green_reg = 0x1ee69, .blue_reg = 0x1ee69}, + {.red_reg = 0x1eebc, .green_reg = 0x1eebc, .blue_reg = 0x1eebc}, + {.red_reg = 0x1ef07, .green_reg = 0x1ef07, .blue_reg = 0x1ef07}, + {.red_reg = 0x1ef4d, .green_reg = 0x1ef4d, .blue_reg = 0x1ef4d}, + {.red_reg = 0x1ef8d, .green_reg = 0x1ef8d, .blue_reg = 0x1ef8d}, + {.red_reg = 0x1efc8, .green_reg = 0x1efc8, .blue_reg = 0x1efc8}, + {.red_reg = 0x1f000, .green_reg = 0x1f000, .blue_reg = 0x1f000}, + {.red_reg = 0x1f000, .green_reg = 0x1f000, .blue_reg = 0x1f000}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}}}, + {.hw_points_num = NUM_OF_LUT_DATA_REGAM_LINEAR, + .arr_curve_points = {{0x0, 0x3}, {0x8, 0x3}, {0x10, 0x3}, {0x18, 0x3}, {0x20, 0x3}, + {0x28, 0x3}, {0x30, 0x3}, {0x38, 0x3}, {0x40, 0x3}, {0x48, 0x3}, {0x50, 0x3}, + {0x58, 0x3}, {0x60, 0x3}, {0x68, 0x3}, {0x70, 0x3}, {0x78, 0x3}, {0x80, 0x3}, + {0x88, 0x3}, {0x90, 0x3}, {0x98, 0x3}, {0xa0, 0x3}, {0xa8, 0x3}, {0xb0, 0x3}, + {0xb8, 0x3}, {0xc0, 0x3}, {0xc8, 0x3}, {0xd0, 0x3}, {0xd8, 0x3}, {0xe0, 0x0}, + {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}}, + .corner_points = {{.red.custom_float_x = 0x6000, + .red.custom_float_y = 0x0, + .red.custom_float_slope = 0x25f40, + .green.custom_float_x = 0x6000, + .green.custom_float_y = 0x0, + .green.custom_float_slope = 0x25f40, + .blue.custom_float_x = 0x6000, + .blue.custom_float_y = 0x0, + .blue.custom_float_slope = 0x25f40}, + {.red.custom_float_x = 0x8800, + .red.custom_float_y = 0x28f40, + .red.custom_float_slope = 0x0, + .green.custom_float_x = 0x8800, + .green.custom_float_y = 0x28f40, + .green.custom_float_slope = 0x0, + .blue.custom_float_x = 0x8800, + .blue.custom_float_y = 0x28f40, + .blue.custom_float_slope = 0x0}}, + .rgb_resulted = {{.red_reg = 0xcf40, .green_reg = 0xcf40, .blue_reg = 0xcf40}, + {.red_reg = 0xd194, .green_reg = 0xd194, .blue_reg = 0xd194}, + {.red_reg = 0xd388, .green_reg = 0xd388, .blue_reg = 0xd388}, + {.red_reg = 0xd57c, .green_reg = 0xd57c, .blue_reg = 0xd57c}, + {.red_reg = 0xd770, .green_reg = 0xd770, .blue_reg = 0xd770}, + {.red_reg = 0xd964, .green_reg = 0xd964, .blue_reg = 0xd964}, + {.red_reg = 0xdb58, .green_reg = 0xdb58, .blue_reg = 0xdb58}, + {.red_reg = 0xdd4c, .green_reg = 0xdd4c, .blue_reg = 0xdd4c}, + {.red_reg = 0xdf40, .green_reg = 0xdf40, .blue_reg = 0xdf40}, + {.red_reg = 0xe194, .green_reg = 0xe194, .blue_reg = 0xe194}, + {.red_reg = 0xe388, .green_reg = 0xe388, .blue_reg = 0xe388}, + {.red_reg = 0xe57c, .green_reg = 0xe57c, .blue_reg = 0xe57c}, + {.red_reg = 0xe770, .green_reg = 0xe770, .blue_reg = 0xe770}, + {.red_reg = 0xe964, .green_reg = 0xe964, .blue_reg = 0xe964}, + {.red_reg = 0xeb58, .green_reg = 0xeb58, .blue_reg = 0xeb58}, + {.red_reg = 0xed4c, .green_reg = 0xed4c, .blue_reg = 0xed4c}, + {.red_reg = 0xef40, .green_reg = 0xef40, .blue_reg = 0xef40}, + {.red_reg = 0xf194, .green_reg = 0xf194, .blue_reg = 0xf194}, + {.red_reg = 0xf388, .green_reg = 0xf388, .blue_reg = 0xf388}, + {.red_reg = 0xf57c, .green_reg = 0xf57c, .blue_reg = 0xf57c}, + {.red_reg = 0xf770, .green_reg = 0xf770, .blue_reg = 0xf770}, + {.red_reg = 0xf964, .green_reg = 0xf964, .blue_reg = 0xf964}, + {.red_reg = 0xfb58, .green_reg = 0xfb58, .blue_reg = 0xfb58}, + {.red_reg = 0xfd4c, .green_reg = 0xfd4c, .blue_reg = 0xfd4c}, + {.red_reg = 0xff40, .green_reg = 0xff40, .blue_reg = 0xff40}, + {.red_reg = 0x10194, .green_reg = 0x10194, .blue_reg = 0x10194}, + {.red_reg = 0x10388, .green_reg = 0x10388, .blue_reg = 0x10388}, + {.red_reg = 0x1057c, .green_reg = 0x1057c, .blue_reg = 0x1057c}, + {.red_reg = 0x10770, .green_reg = 0x10770, .blue_reg = 0x10770}, + {.red_reg = 0x10964, .green_reg = 0x10964, .blue_reg = 0x10964}, + {.red_reg = 0x10b58, .green_reg = 0x10b58, .blue_reg = 0x10b58}, + {.red_reg = 0x10d4c, .green_reg = 0x10d4c, .blue_reg = 0x10d4c}, + {.red_reg = 0x10f40, .green_reg = 0x10f40, .blue_reg = 0x10f40}, + {.red_reg = 0x11194, .green_reg = 0x11194, .blue_reg = 0x11194}, + {.red_reg = 0x11388, .green_reg = 0x11388, .blue_reg = 0x11388}, + {.red_reg = 0x1157c, .green_reg = 0x1157c, .blue_reg = 0x1157c}, + {.red_reg = 0x11770, .green_reg = 0x11770, .blue_reg = 0x11770}, + {.red_reg = 0x11964, .green_reg = 0x11964, .blue_reg = 0x11964}, + {.red_reg = 0x11b58, .green_reg = 0x11b58, .blue_reg = 0x11b58}, + {.red_reg = 0x11d4c, .green_reg = 0x11d4c, .blue_reg = 0x11d4c}, + {.red_reg = 0x11f40, .green_reg = 0x11f40, .blue_reg = 0x11f40}, + {.red_reg = 0x12194, .green_reg = 0x12194, .blue_reg = 0x12194}, + {.red_reg = 0x12388, .green_reg = 0x12388, .blue_reg = 0x12388}, + {.red_reg = 0x1257c, .green_reg = 0x1257c, .blue_reg = 0x1257c}, + {.red_reg = 0x12770, .green_reg = 0x12770, .blue_reg = 0x12770}, + {.red_reg = 0x12964, .green_reg = 0x12964, .blue_reg = 0x12964}, + {.red_reg = 0x12b58, .green_reg = 0x12b58, .blue_reg = 0x12b58}, + {.red_reg = 0x12d4c, .green_reg = 0x12d4c, .blue_reg = 0x12d4c}, + {.red_reg = 0x12f40, .green_reg = 0x12f40, .blue_reg = 0x12f40}, + {.red_reg = 0x13194, .green_reg = 0x13194, .blue_reg = 0x13194}, + {.red_reg = 0x13388, .green_reg = 0x13388, .blue_reg = 0x13388}, + {.red_reg = 0x1357c, .green_reg = 0x1357c, .blue_reg = 0x1357c}, + {.red_reg = 0x13770, .green_reg = 0x13770, .blue_reg = 0x13770}, + {.red_reg = 0x13964, .green_reg = 0x13964, .blue_reg = 0x13964}, + {.red_reg = 0x13b58, .green_reg = 0x13b58, .blue_reg = 0x13b58}, + {.red_reg = 0x13d4c, .green_reg = 0x13d4c, .blue_reg = 0x13d4c}, + {.red_reg = 0x13f40, .green_reg = 0x13f40, .blue_reg = 0x13f40}, + {.red_reg = 0x14194, .green_reg = 0x14194, .blue_reg = 0x14194}, + {.red_reg = 0x14388, .green_reg = 0x14388, .blue_reg = 0x14388}, + {.red_reg = 0x1457c, .green_reg = 0x1457c, .blue_reg = 0x1457c}, + {.red_reg = 0x14770, .green_reg = 0x14770, .blue_reg = 0x14770}, + {.red_reg = 0x14964, .green_reg = 0x14964, .blue_reg = 0x14964}, + {.red_reg = 0x14b58, .green_reg = 0x14b58, .blue_reg = 0x14b58}, + {.red_reg = 0x14d4c, .green_reg = 0x14d4c, .blue_reg = 0x14d4c}, + {.red_reg = 0x14f40, .green_reg = 0x14f40, .blue_reg = 0x14f40}, + {.red_reg = 0x15194, .green_reg = 0x15194, .blue_reg = 0x15194}, + {.red_reg = 0x15388, .green_reg = 0x15388, .blue_reg = 0x15388}, + {.red_reg = 0x1557c, .green_reg = 0x1557c, .blue_reg = 0x1557c}, + {.red_reg = 0x15770, .green_reg = 0x15770, .blue_reg = 0x15770}, + {.red_reg = 0x15964, .green_reg = 0x15964, .blue_reg = 0x15964}, + {.red_reg = 0x15b58, .green_reg = 0x15b58, .blue_reg = 0x15b58}, + {.red_reg = 0x15d4c, .green_reg = 0x15d4c, .blue_reg = 0x15d4c}, + {.red_reg = 0x15f40, .green_reg = 0x15f40, .blue_reg = 0x15f40}, + {.red_reg = 0x16194, .green_reg = 0x16194, .blue_reg = 0x16194}, + {.red_reg = 0x16388, .green_reg = 0x16388, .blue_reg = 0x16388}, + {.red_reg = 0x1657c, .green_reg = 0x1657c, .blue_reg = 0x1657c}, + {.red_reg = 0x16770, .green_reg = 0x16770, .blue_reg = 0x16770}, + {.red_reg = 0x16964, .green_reg = 0x16964, .blue_reg = 0x16964}, + {.red_reg = 0x16b58, .green_reg = 0x16b58, .blue_reg = 0x16b58}, + {.red_reg = 0x16d4c, .green_reg = 0x16d4c, .blue_reg = 0x16d4c}, + {.red_reg = 0x16f40, .green_reg = 0x16f40, .blue_reg = 0x16f40}, + {.red_reg = 0x17194, .green_reg = 0x17194, .blue_reg = 0x17194}, + {.red_reg = 0x17388, .green_reg = 0x17388, .blue_reg = 0x17388}, + {.red_reg = 0x1757c, .green_reg = 0x1757c, .blue_reg = 0x1757c}, + {.red_reg = 0x17770, .green_reg = 0x17770, .blue_reg = 0x17770}, + {.red_reg = 0x17964, .green_reg = 0x17964, .blue_reg = 0x17964}, + {.red_reg = 0x17b58, .green_reg = 0x17b58, .blue_reg = 0x17b58}, + {.red_reg = 0x17d4c, .green_reg = 0x17d4c, .blue_reg = 0x17d4c}, + {.red_reg = 0x17f40, .green_reg = 0x17f40, .blue_reg = 0x17f40}, + {.red_reg = 0x18194, .green_reg = 0x18194, .blue_reg = 0x18194}, + {.red_reg = 0x18388, .green_reg = 0x18388, .blue_reg = 0x18388}, + {.red_reg = 0x1857c, .green_reg = 0x1857c, .blue_reg = 0x1857c}, + {.red_reg = 0x18770, .green_reg = 0x18770, .blue_reg = 0x18770}, + {.red_reg = 0x18964, .green_reg = 0x18964, .blue_reg = 0x18964}, + {.red_reg = 0x18b58, .green_reg = 0x18b58, .blue_reg = 0x18b58}, + {.red_reg = 0x18d4c, .green_reg = 0x18d4c, .blue_reg = 0x18d4c}, + {.red_reg = 0x18f40, .green_reg = 0x18f40, .blue_reg = 0x18f40}, + {.red_reg = 0x19194, .green_reg = 0x19194, .blue_reg = 0x19194}, + {.red_reg = 0x19388, .green_reg = 0x19388, .blue_reg = 0x19388}, + {.red_reg = 0x1957c, .green_reg = 0x1957c, .blue_reg = 0x1957c}, + {.red_reg = 0x19770, .green_reg = 0x19770, .blue_reg = 0x19770}, + {.red_reg = 0x19964, .green_reg = 0x19964, .blue_reg = 0x19964}, + {.red_reg = 0x19b58, .green_reg = 0x19b58, .blue_reg = 0x19b58}, + {.red_reg = 0x19d4c, .green_reg = 0x19d4c, .blue_reg = 0x19d4c}, + {.red_reg = 0x19f40, .green_reg = 0x19f40, .blue_reg = 0x19f40}, + {.red_reg = 0x1a194, .green_reg = 0x1a194, .blue_reg = 0x1a194}, + {.red_reg = 0x1a388, .green_reg = 0x1a388, .blue_reg = 0x1a388}, + {.red_reg = 0x1a57c, .green_reg = 0x1a57c, .blue_reg = 0x1a57c}, + {.red_reg = 0x1a770, .green_reg = 0x1a770, .blue_reg = 0x1a770}, + {.red_reg = 0x1a964, .green_reg = 0x1a964, .blue_reg = 0x1a964}, + {.red_reg = 0x1ab58, .green_reg = 0x1ab58, .blue_reg = 0x1ab58}, + {.red_reg = 0x1ad4c, .green_reg = 0x1ad4c, .blue_reg = 0x1ad4c}, + {.red_reg = 0x1af40, .green_reg = 0x1af40, .blue_reg = 0x1af40}, + {.red_reg = 0x1b194, .green_reg = 0x1b194, .blue_reg = 0x1b194}, + {.red_reg = 0x1b388, .green_reg = 0x1b388, .blue_reg = 0x1b388}, + {.red_reg = 0x1b57c, .green_reg = 0x1b57c, .blue_reg = 0x1b57c}, + {.red_reg = 0x1b770, .green_reg = 0x1b770, .blue_reg = 0x1b770}, + {.red_reg = 0x1b964, .green_reg = 0x1b964, .blue_reg = 0x1b964}, + {.red_reg = 0x1bb58, .green_reg = 0x1bb58, .blue_reg = 0x1bb58}, + {.red_reg = 0x1bd4c, .green_reg = 0x1bd4c, .blue_reg = 0x1bd4c}, + {.red_reg = 0x1bf40, .green_reg = 0x1bf40, .blue_reg = 0x1bf40}, + {.red_reg = 0x1c194, .green_reg = 0x1c194, .blue_reg = 0x1c194}, + {.red_reg = 0x1c388, .green_reg = 0x1c388, .blue_reg = 0x1c388}, + {.red_reg = 0x1c57c, .green_reg = 0x1c57c, .blue_reg = 0x1c57c}, + {.red_reg = 0x1c770, .green_reg = 0x1c770, .blue_reg = 0x1c770}, + {.red_reg = 0x1c964, .green_reg = 0x1c964, .blue_reg = 0x1c964}, + {.red_reg = 0x1cb58, .green_reg = 0x1cb58, .blue_reg = 0x1cb58}, + {.red_reg = 0x1cd4c, .green_reg = 0x1cd4c, .blue_reg = 0x1cd4c}, + {.red_reg = 0x1cf40, .green_reg = 0x1cf40, .blue_reg = 0x1cf40}, + {.red_reg = 0x1d194, .green_reg = 0x1d194, .blue_reg = 0x1d194}, + {.red_reg = 0x1d388, .green_reg = 0x1d388, .blue_reg = 0x1d388}, + {.red_reg = 0x1d57c, .green_reg = 0x1d57c, .blue_reg = 0x1d57c}, + {.red_reg = 0x1d770, .green_reg = 0x1d770, .blue_reg = 0x1d770}, + {.red_reg = 0x1d964, .green_reg = 0x1d964, .blue_reg = 0x1d964}, + {.red_reg = 0x1db58, .green_reg = 0x1db58, .blue_reg = 0x1db58}, + {.red_reg = 0x1dd4c, .green_reg = 0x1dd4c, .blue_reg = 0x1dd4c}, + {.red_reg = 0x1df40, .green_reg = 0x1df40, .blue_reg = 0x1df40}, + {.red_reg = 0x1e194, .green_reg = 0x1e194, .blue_reg = 0x1e194}, + {.red_reg = 0x1e388, .green_reg = 0x1e388, .blue_reg = 0x1e388}, + {.red_reg = 0x1e57c, .green_reg = 0x1e57c, .blue_reg = 0x1e57c}, + {.red_reg = 0x1e770, .green_reg = 0x1e770, .blue_reg = 0x1e770}, + {.red_reg = 0x1e964, .green_reg = 0x1e964, .blue_reg = 0x1e964}, + {.red_reg = 0x1eb58, .green_reg = 0x1eb58, .blue_reg = 0x1eb58}, + {.red_reg = 0x1ed4c, .green_reg = 0x1ed4c, .blue_reg = 0x1ed4c}, + {.red_reg = 0x1ef40, .green_reg = 0x1ef40, .blue_reg = 0x1ef40}, + {.red_reg = 0x1f194, .green_reg = 0x1f194, .blue_reg = 0x1f194}, + {.red_reg = 0x1f388, .green_reg = 0x1f388, .blue_reg = 0x1f388}, + {.red_reg = 0x1f57c, .green_reg = 0x1f57c, .blue_reg = 0x1f57c}, + {.red_reg = 0x1f770, .green_reg = 0x1f770, .blue_reg = 0x1f770}, + {.red_reg = 0x1f964, .green_reg = 0x1f964, .blue_reg = 0x1f964}, + {.red_reg = 0x1fb58, .green_reg = 0x1fb58, .blue_reg = 0x1fb58}, + {.red_reg = 0x1fd4c, .green_reg = 0x1fd4c, .blue_reg = 0x1fd4c}, + {.red_reg = 0x1ff40, .green_reg = 0x1ff40, .blue_reg = 0x1ff40}, + {.red_reg = 0x20194, .green_reg = 0x20194, .blue_reg = 0x20194}, + {.red_reg = 0x20388, .green_reg = 0x20388, .blue_reg = 0x20388}, + {.red_reg = 0x2057c, .green_reg = 0x2057c, .blue_reg = 0x2057c}, + {.red_reg = 0x20770, .green_reg = 0x20770, .blue_reg = 0x20770}, + {.red_reg = 0x20964, .green_reg = 0x20964, .blue_reg = 0x20964}, + {.red_reg = 0x20b58, .green_reg = 0x20b58, .blue_reg = 0x20b58}, + {.red_reg = 0x20d4c, .green_reg = 0x20d4c, .blue_reg = 0x20d4c}, + {.red_reg = 0x20f40, .green_reg = 0x20f40, .blue_reg = 0x20f40}, + {.red_reg = 0x21194, .green_reg = 0x21194, .blue_reg = 0x21194}, + {.red_reg = 0x21388, .green_reg = 0x21388, .blue_reg = 0x21388}, + {.red_reg = 0x2157c, .green_reg = 0x2157c, .blue_reg = 0x2157c}, + {.red_reg = 0x21770, .green_reg = 0x21770, .blue_reg = 0x21770}, + {.red_reg = 0x21964, .green_reg = 0x21964, .blue_reg = 0x21964}, + {.red_reg = 0x21b58, .green_reg = 0x21b58, .blue_reg = 0x21b58}, + {.red_reg = 0x21d4c, .green_reg = 0x21d4c, .blue_reg = 0x21d4c}, + {.red_reg = 0x21f40, .green_reg = 0x21f40, .blue_reg = 0x21f40}, + {.red_reg = 0x22194, .green_reg = 0x22194, .blue_reg = 0x22194}, + {.red_reg = 0x22388, .green_reg = 0x22388, .blue_reg = 0x22388}, + {.red_reg = 0x2257c, .green_reg = 0x2257c, .blue_reg = 0x2257c}, + {.red_reg = 0x22770, .green_reg = 0x22770, .blue_reg = 0x22770}, + {.red_reg = 0x22964, .green_reg = 0x22964, .blue_reg = 0x22964}, + {.red_reg = 0x22b58, .green_reg = 0x22b58, .blue_reg = 0x22b58}, + {.red_reg = 0x22d4c, .green_reg = 0x22d4c, .blue_reg = 0x22d4c}, + {.red_reg = 0x22f40, .green_reg = 0x22f40, .blue_reg = 0x22f40}, + {.red_reg = 0x23194, .green_reg = 0x23194, .blue_reg = 0x23194}, + {.red_reg = 0x23388, .green_reg = 0x23388, .blue_reg = 0x23388}, + {.red_reg = 0x2357c, .green_reg = 0x2357c, .blue_reg = 0x2357c}, + {.red_reg = 0x23770, .green_reg = 0x23770, .blue_reg = 0x23770}, + {.red_reg = 0x23964, .green_reg = 0x23964, .blue_reg = 0x23964}, + {.red_reg = 0x23b58, .green_reg = 0x23b58, .blue_reg = 0x23b58}, + {.red_reg = 0x23d4c, .green_reg = 0x23d4c, .blue_reg = 0x23d4c}, + {.red_reg = 0x23f40, .green_reg = 0x23f40, .blue_reg = 0x23f40}, + {.red_reg = 0x24194, .green_reg = 0x24194, .blue_reg = 0x24194}, + {.red_reg = 0x24388, .green_reg = 0x24388, .blue_reg = 0x24388}, + {.red_reg = 0x2457c, .green_reg = 0x2457c, .blue_reg = 0x2457c}, + {.red_reg = 0x24770, .green_reg = 0x24770, .blue_reg = 0x24770}, + {.red_reg = 0x24964, .green_reg = 0x24964, .blue_reg = 0x24964}, + {.red_reg = 0x24b58, .green_reg = 0x24b58, .blue_reg = 0x24b58}, + {.red_reg = 0x24d4c, .green_reg = 0x24d4c, .blue_reg = 0x24d4c}, + {.red_reg = 0x24f40, .green_reg = 0x24f40, .blue_reg = 0x24f40}, + {.red_reg = 0x25194, .green_reg = 0x25194, .blue_reg = 0x25194}, + {.red_reg = 0x25388, .green_reg = 0x25388, .blue_reg = 0x25388}, + {.red_reg = 0x2557c, .green_reg = 0x2557c, .blue_reg = 0x2557c}, + {.red_reg = 0x25770, .green_reg = 0x25770, .blue_reg = 0x25770}, + {.red_reg = 0x25964, .green_reg = 0x25964, .blue_reg = 0x25964}, + {.red_reg = 0x25b58, .green_reg = 0x25b58, .blue_reg = 0x25b58}, + {.red_reg = 0x25d4c, .green_reg = 0x25d4c, .blue_reg = 0x25d4c}, + {.red_reg = 0x25f40, .green_reg = 0x25f40, .blue_reg = 0x25f40}, + {.red_reg = 0x26194, .green_reg = 0x26194, .blue_reg = 0x26194}, + {.red_reg = 0x26388, .green_reg = 0x26388, .blue_reg = 0x26388}, + {.red_reg = 0x2657c, .green_reg = 0x2657c, .blue_reg = 0x2657c}, + {.red_reg = 0x26770, .green_reg = 0x26770, .blue_reg = 0x26770}, + {.red_reg = 0x26964, .green_reg = 0x26964, .blue_reg = 0x26964}, + {.red_reg = 0x26b58, .green_reg = 0x26b58, .blue_reg = 0x26b58}, + {.red_reg = 0x26d4c, .green_reg = 0x26d4c, .blue_reg = 0x26d4c}, + {.red_reg = 0x26f40, .green_reg = 0x26f40, .blue_reg = 0x26f40}, + {.red_reg = 0x27194, .green_reg = 0x27194, .blue_reg = 0x27194}, + {.red_reg = 0x27388, .green_reg = 0x27388, .blue_reg = 0x27388}, + {.red_reg = 0x2757c, .green_reg = 0x2757c, .blue_reg = 0x2757c}, + {.red_reg = 0x27770, .green_reg = 0x27770, .blue_reg = 0x27770}, + {.red_reg = 0x27964, .green_reg = 0x27964, .blue_reg = 0x27964}, + {.red_reg = 0x27b58, .green_reg = 0x27b58, .blue_reg = 0x27b58}, + {.red_reg = 0x27d4c, .green_reg = 0x27d4c, .blue_reg = 0x27d4c}, + {.red_reg = 0x27f40, .green_reg = 0x27f40, .blue_reg = 0x27f40}, + {.red_reg = 0x28194, .green_reg = 0x28194, .blue_reg = 0x28194}, + {.red_reg = 0x28388, .green_reg = 0x28388, .blue_reg = 0x28388}, + {.red_reg = 0x2857c, .green_reg = 0x2857c, .blue_reg = 0x2857c}, + {.red_reg = 0x28770, .green_reg = 0x28770, .blue_reg = 0x28770}, + {.red_reg = 0x28964, .green_reg = 0x28964, .blue_reg = 0x28964}, + {.red_reg = 0x28b58, .green_reg = 0x28b58, .blue_reg = 0x28b58}, + {.red_reg = 0x28f40, .green_reg = 0x28f40, .blue_reg = 0x28f40}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}, + {.red_reg = 0x0, .green_reg = 0x0, .blue_reg = 0x0}}}, + }}; + +#ifdef __cplusplus +} +#endif diff --git a/src/amd/vpelib/src/core/inc/color_table.h b/src/amd/vpelib/src/core/inc/color_table.h new file mode 100644 index 00000000000..c4212b4f03e --- /dev/null +++ b/src/amd/vpelib/src/core/inc/color_table.h @@ -0,0 +1,66 @@ +/* Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#pragma once + +#include "fixed31_32.h" +#include "color.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define NUM_PTS_IN_REGION 16 +#define NUM_REGIONS 32 +#define MAX_HW_POINTS (NUM_PTS_IN_REGION * NUM_REGIONS) +#define MAX_HW_POINTS_DEGAMMA 257 + +enum table_type { + type_pq_table, + type_de_pq_table +}; + +bool vpe_color_is_table_init(enum table_type type); + +struct fixed31_32 *vpe_color_get_table(enum table_type type); + +void vpe_color_set_table_init_state(enum table_type type, bool state); + +struct vpe_csc_matrix { + enum color_space cs; + uint16_t regval[12]; +}; + +static const struct vpe_csc_matrix vpe_input_csc_matrix_fixed[] = { + {COLOR_SPACE_SRGB, {0x2000, 0, 0, 0, 0, 0x2000, 0, 0, 0, 0, 0x2000, 0}}, + {COLOR_SPACE_YCBCR601, + {0x2cdd, 0x2000, 0, 0xe991, 0xe926, 0x2000, 0xf4fd, 0x10ef, 0, 0x2000, 0x38b4, 0xe3a6}}, + {COLOR_SPACE_YCBCR709, + {0x3265, 0x2000, 0, 0xe6ce, 0xf105, 0x2000, 0xfa01, 0xa7d, 0, 0x2000, 0x3b61, 0xe24f}}, + {COLOR_SPACE_2020_YCBCR, + {0x2f2f, 0x2000, 0, 0xe869, 0xedb8, 0x2000, 0xfabc, 0xbc6, 0x0, 0x2000, 0x3c34, 0xe1e6}}}; + +#ifdef __cplusplus +} +#endif diff --git a/src/amd/vpelib/src/core/inc/color_test_values.h b/src/amd/vpelib/src/core/inc/color_test_values.h new file mode 100644 index 00000000000..629a889ce83 --- /dev/null +++ b/src/amd/vpelib/src/core/inc/color_test_values.h @@ -0,0 +1,48 @@ +/* Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#pragma once + +#include "common.h" +#include "fixed31_32.h" +#include "color_table.h" + +#ifdef __cplusplus +extern "C" { +#endif + +enum test3d_type { + lut3d_identity = 0, + lut3d_sce +}; + +bool build_test_shaper_sdr(struct transfer_func *shaper); + +bool build_test_post1dlut_sdr(struct transfer_func *post1D); + +bool build_test_3dlut(enum test3d_type type, struct vpe_3dlut *lut3d); + +#ifdef __cplusplus +} +#endif diff --git a/src/amd/vpelib/src/core/inc/common.h b/src/amd/vpelib/src/core/inc/common.h new file mode 100644 index 00000000000..e9898cef8d8 --- /dev/null +++ b/src/amd/vpelib/src/core/inc/common.h @@ -0,0 +1,91 @@ +/* Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#pragma once + +#include +#include "vpe_types.h" +#include "color.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define ADDR_LO(addr) ((addr) & 0xFFFFFFFF) +#define ADDR_HI(addr) (((addr) >> 32) & 0xFFFFFFFF) + +#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0])) + +#define swap(x, y) \ + do { \ + unsigned char swap_temp[sizeof(x) == sizeof(y) ? (signed int)sizeof(x) : -1]; \ + memcpy(swap_temp, &y, sizeof(x)); \ + y = x; \ + memcpy(&x, swap_temp, sizeof(x)); \ + } while (0) + +#ifndef min +#define min(x, y) (((x) < (y)) ? (x) : (y)) +#endif + +#ifndef max +#define max(x, y) (((x) > (y)) ? (x) : (y)) +#endif + +bool vpe_find_color_space_from_table( + const struct vpe_color_space *table, int table_size, const struct vpe_color_space *cs); + +bool vpe_is_dual_plane_format(enum vpe_surface_pixel_format format); + +// RGB checkers +bool vpe_is_32bit_packed_rgb(enum vpe_surface_pixel_format format); +bool vpe_is_rgb8(enum vpe_surface_pixel_format format); +bool vpe_is_rgb10(enum vpe_surface_pixel_format format); +bool vpe_is_fp16(enum vpe_surface_pixel_format format); + +// yuv 4:2:0 check +bool vpe_is_yuv420_8(enum vpe_surface_pixel_format format); +bool vpe_is_yuv420_10(enum vpe_surface_pixel_format format); +bool vpe_is_yuv420(enum vpe_surface_pixel_format format); + +// yuv 4:4:4 check +bool vpe_is_yuv444_8(enum vpe_surface_pixel_format format); +bool vpe_is_yuv444_10(enum vpe_surface_pixel_format format); + +enum color_depth vpe_get_color_depth(enum vpe_surface_pixel_format format); + +bool vpe_has_per_pixel_alpha(enum vpe_surface_pixel_format format); + +enum vpe_status vpe_check_output_support(struct vpe *vpe, const struct vpe_build_param *param); + +enum vpe_status vpe_check_input_support(struct vpe *vpe, const struct vpe_stream *stream); + +enum vpe_status vpe_cache_tone_map_params(struct stream_ctx *, const struct vpe_build_param *param); + +enum vpe_status vpe_check_tone_map_support( + struct vpe *vpe, const struct vpe_stream *stream, const struct vpe_build_param *param); + +#ifdef __cplusplus +} +#endif diff --git a/src/amd/vpelib/src/core/inc/config_writer.h b/src/amd/vpelib/src/core/inc/config_writer.h new file mode 100644 index 00000000000..59512d17224 --- /dev/null +++ b/src/amd/vpelib/src/core/inc/config_writer.h @@ -0,0 +1,167 @@ +/* Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#pragma once + +#include "vpe_types.h" + +#if defined(LITTLEENDIAN_CPU) +#elif defined(BIGENDIAN_CPU) +#else +#error "BIGENDIAN_CPU or LITTLEENDIAN_CPU must be defined" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +enum config_type { + CONFIG_TYPE_UNKNOWN, + CONFIG_TYPE_DIRECT, + CONFIG_TYPE_INDIRECT +}; + +typedef void (*config_callback_t)( + void *ctx, uint64_t cfg_base_gpu, uint64_t cfg_base_cpu, int64_t size); + +#define MAX_CONFIG_PACKET_DATA_SIZE_DWORD 0x01000 + +struct vpep_direct_config_packet { + union { + struct { +#if defined(LITTLEENDIAN_CPU) + uint32_t INC : 1; + uint32_t : 1; + uint32_t VPEP_CONFIG_REGISTER_OFFSET : 18; + uint32_t VPEP_CONFIG_DATA_SIZE : 12; +#elif defined(BIGENDIAN_CPU) + uint32_t VPEP_CONFIG_DATA_SIZE : 12; + uint32_t VPEP_CONFIG_REGISTER_OFFSET : 18; + uint32_t : 1; + uint32_t INC : 1; +#endif + } bitfields, bits; + uint32_t u32all; + }; + uint32_t data[1]; +}; + +/* config writer only help initialize the 1st DWORD, + * and 'close' the config (i.e. finalize the size) once it is completed. + * it doesn't help generate the content, which shall be prepared by the caller + * and then call config_writer_fill() + */ +struct config_writer { + struct vpe_buf *buf; /**< store the current buf pointer */ + + /* store the base addr of the currnet config + * i.e. config header + * it is always constructed in emb_buf + */ + uint64_t base_gpu_va; + uint64_t base_cpu_va; + + enum config_type type; + bool completed; + + void *callback_ctx; + config_callback_t callback; + enum vpe_status status; +}; + +/** initialize the config writer. + * Calls right before building any VPEP configs + * + * /param writer writer instance + * /param emb_buf points to the current cmd_buf, + * each config_writer_fill will update the address + */ +void config_writer_init(struct config_writer *writer, struct vpe_buf *emb_buf); + +/** set the callback function (can be null) for notifying any config completion + * In the callback, caller can: + * 1. save the config for later reuse + * 2. write it to vpe descriptor + */ +void config_writer_set_callback( + struct config_writer *writer, void *callback_ctx, config_callback_t callback); + +/** set the config type before config_writer_fill() + * if the config_type has changed, it will finalize the current one, + * 1) direct config + * VPEP_DIRECT_CONFIG_ARRAY_SIZE is finalized (in DW0) automatically. + * 2) indirect config + * NUM_DST is finalized (in DW0) automatically. + * and run callback (if set) to notify the completion. + * A new config desc header DW0 will be generated. + * + * /param writer writer instance + * /param type config type + */ +void config_writer_set_type(struct config_writer *writer, enum config_type type); + +/** fill the value to the buffer. + * If the dword exceeds the config packet size limit, + * callback will be called and a new config desc is created. + * + * /param writer writer instance + * /param value fill the DW to the config desc body + */ +void config_writer_fill(struct config_writer *writer, uint32_t value); + +/** fill the header value to the buffer. + * If the current size + number of dwords in the array + * exceeds the config packet size limit, + * callback will be called and a new config desc is created. + * + * /param writer writer instance + * /param packet config packet with header filled properly + */ +void config_writer_fill_direct_config_packet_header( + struct config_writer *writer, struct vpep_direct_config_packet *packet); + +/** fill the header and data value to the buffer. + * For single DATA element ONLY. + * If the current size + number of dwords in the array + * exceeds the config packet size limit, + * callback will be called and a new config desc is created. + * + * /param writer writer instance + * /param packet config packet with valid header and data + */ +void config_writer_fill_direct_config_packet( + struct config_writer *writer, struct vpep_direct_config_packet *packet); + +void config_writer_fill_indirect_data_array( + struct config_writer *writer, const uint64_t data_gpuva, uint32_t size); + +void config_writer_fill_indirect_destination(struct config_writer *writer, + const uint32_t offset_index, const uint32_t start_index, const uint32_t offset_data); + +/** explicitly complete the config */ +void config_writer_complete(struct config_writer *writer); + +#ifdef __cplusplus +} +#endif diff --git a/src/amd/vpelib/src/core/inc/diag_reg_helper.h b/src/amd/vpelib/src/core/inc/diag_reg_helper.h new file mode 100644 index 00000000000..d042785d00e --- /dev/null +++ b/src/amd/vpelib/src/core/inc/diag_reg_helper.h @@ -0,0 +1,60 @@ +/* + * Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + */ + +#ifndef DRIVERS_VPELIB_INC_DIAG_REG_HELPER_H_ +#define DRIVERS_VPELIB_INC_DIAG_REG_HELPER_H_ + +#pragma once + +#include "reg_helper.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** CTX is defined in the .c files */ +#define DIAG_PROGRAM_ENTRY() \ + struct vpe_priv *vpe_priv = CTX_BASE->vpe_priv; \ + struct CTX *CTX = (struct CTX *)CTX_BASE; \ + struct config_writer *config_writer = &vpe_priv->config_diag_writer; \ + struct vpep_direct_config_packet packet = {0} + +#define DIAG_REG_SET(reg_name, val) \ + do { \ + packet.bits.INC = 0; \ + packet.bits.VPEP_CONFIG_DATA_SIZE = 0; \ + packet.bits.VPEP_CONFIG_REGISTER_OFFSET = REG_OFFSET(reg_name); \ + REG_IS_WRITTEN(reg_name) = true; \ + packet.data[0] = REG_LAST_WRITTEN_VAL(reg_name) = (uint32_t)val; \ + config_writer_fill_direct_config_packet(config_writer, &packet); \ + } while (0) + +#define DIAG_REG_CURRENT(reg_name) REG_CURRENT(reg_name) +#define DIAG_REG_UPDATE(reg, field, val) REG_UPDATE(reg, field, val) + +#ifdef __cplusplus +} +#endif + +#endif /* DRIVERS_VPELIB_INC_REG_HELPER_H_ */ diff --git a/src/amd/vpelib/src/core/inc/dpp.h b/src/amd/vpelib/src/core/inc/dpp.h new file mode 100644 index 00000000000..ed3ec13d1fb --- /dev/null +++ b/src/amd/vpelib/src/core/inc/dpp.h @@ -0,0 +1,121 @@ +/* Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#pragma once + +#include "vpe_types.h" +#include "hw_shared.h" +#include "color.h" +#include "transform.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct dpp; +struct vpe_priv; +struct vpe_csc_matrix; + +struct cnv_alpha_2bit_lut { + int lut0; + int lut1; + int lut2; + int lut3; +}; + +enum CNV_COLOR_KEYER_MODE { + CNV_COLOR_KEYER_MODE_FORCE_00 = 0, + CNV_COLOR_KEYER_MODE_FORCE_FF = 1, + CNV_COLOR_KEYER_MODE_RANGE_00 = 2, + CNV_COLOR_KEYER_MODE_RANGE_FF = 3 +}; + +struct cnv_color_keyer_params { + int color_keyer_en; + int color_keyer_mode; + int color_keyer_alpha_low; + int color_keyer_alpha_high; + int color_keyer_red_low; + int color_keyer_red_high; + int color_keyer_green_low; + int color_keyer_green_high; + int color_keyer_blue_low; + int color_keyer_blue_high; +}; + +enum input_csc_select { + INPUT_CSC_SELECT_BYPASS = 0, + INPUT_CSC_SELECT_ICSC = 1, +}; + +struct dpp_funcs { + + bool (*get_optimal_number_of_taps)( + struct dpp *dpp, struct scaler_data *scl_data, const struct vpe_scaling_taps *taps); + + void (*dscl_calc_lb_num_partitions)(const struct scaler_data *scl_data, + enum lb_memory_config lb_config, uint32_t *num_part_y, uint32_t *num_part_c); + + /** non segment specific */ + void (*program_cnv)( + struct dpp *dpp, enum vpe_surface_pixel_format format, enum vpe_expansion_mode mode); + + void (*program_pre_dgam)(struct dpp *dpp, enum color_transfer_func tr); + + void (*program_cnv_bias_scale)(struct dpp *dpp, struct bias_and_scale *bias_and_scale); + + void (*program_alpha_keyer)(struct dpp *dpp, struct cnv_color_keyer_params *color_keyer); + + void (*program_input_transfer_func)(struct dpp *dpp, struct transfer_func *input_tf); + + void (*program_gamut_remap)(struct dpp *dpp, struct colorspace_transform *gamut_remap); + + /*program post scaler scs block in dpp CM*/ + void (*program_post_csc)(struct dpp *dpp, enum color_space color_space, + enum input_csc_select input_select, struct vpe_csc_matrix *input_cs); + + void (*set_hdr_multiplier)(struct dpp *dpp, uint32_t multiplier); + + /** scaler */ + void (*set_segment_scaler)(struct dpp *dpp, const struct scaler_data *scl_data); + + void (*set_frame_scaler)(struct dpp *dpp, const struct scaler_data *scl_data); + + uint32_t (*get_line_buffer_size)(void); + + bool (*validate_number_of_taps)(struct dpp *dpp, struct scaler_data *scl_data); + + void (*program_crc)(struct dpp *opp, bool enable); +}; + +struct dpp { + struct vpe_priv *vpe_priv; + struct dpp_funcs *funcs; + + struct pwl_params degamma_params; +}; + +#ifdef __cplusplus +} +#endif diff --git a/src/amd/vpelib/src/core/inc/hw_shared.h b/src/amd/vpelib/src/core/inc/hw_shared.h new file mode 100644 index 00000000000..43e477fb367 --- /dev/null +++ b/src/amd/vpelib/src/core/inc/hw_shared.h @@ -0,0 +1,193 @@ +/* Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#pragma once + +#include "fixed31_32.h" + +#ifdef __cplusplus +extern "C" { +#endif + +enum cm_type { + CM_DEGAM, + CM_REGAM, +}; + +struct bias_and_scale { + uint32_t scale_red; + uint32_t bias_red; + uint32_t scale_green; + uint32_t bias_green; + uint32_t scale_blue; + uint32_t bias_blue; +}; + +struct gamma_curve { + uint32_t offset; + uint32_t segments_num; +}; + +struct curve_points { + struct fixed31_32 x; + struct fixed31_32 y; + struct fixed31_32 offset; + struct fixed31_32 slope; + + uint32_t custom_float_x; + uint32_t custom_float_y; + uint32_t custom_float_offset; + uint32_t custom_float_slope; +}; + +struct curve_points3 { + struct curve_points red; + struct curve_points green; + struct curve_points blue; +}; + +struct pwl_result_data { + struct fixed31_32 red; + struct fixed31_32 green; + struct fixed31_32 blue; + + struct fixed31_32 delta_red; + struct fixed31_32 delta_green; + struct fixed31_32 delta_blue; + + uint32_t red_reg; + uint32_t green_reg; + uint32_t blue_reg; + + uint32_t delta_red_reg; + uint32_t delta_green_reg; + uint32_t delta_blue_reg; +}; + +/* arr_curve_points - regamma regions/segments specification + * arr_points - beginning and end point specified separately (only one on DCE) + * corner_points - beginning and end point for all 3 colors (DCN) + * rgb_resulted - final curve + */ +struct pwl_params { + struct gamma_curve arr_curve_points[34]; + union { + struct curve_points arr_points[2]; + struct curve_points3 corner_points[2]; + }; + struct pwl_result_data rgb_resulted[256 + 3]; + uint32_t hw_points_num; +}; + +struct hw_x_point { + uint32_t custom_float_x; + struct fixed31_32 x; + struct fixed31_32 regamma_y_red; + struct fixed31_32 regamma_y_green; + struct fixed31_32 regamma_y_blue; +}; + +struct gamma_coefficients { + struct fixed31_32 a0[3]; + struct fixed31_32 a1[3]; + struct fixed31_32 a2[3]; + struct fixed31_32 a3[3]; + struct fixed31_32 user_gamma[3]; + struct fixed31_32 user_contrast; + struct fixed31_32 user_brightness; +}; + +struct pwl_float_data_ex { + struct fixed31_32 r; + struct fixed31_32 g; + struct fixed31_32 b; + struct fixed31_32 delta_r; + struct fixed31_32 delta_g; + struct fixed31_32 delta_b; +}; + +enum hw_point_position { + /* hw point sits between left and right sw points */ + HW_POINT_POSITION_MIDDLE, + /* hw point lays left from left (smaller) sw point */ + HW_POINT_POSITION_LEFT, + /* hw point lays stays from right (bigger) sw point */ + HW_POINT_POSITION_RIGHT +}; + +struct gamma_point { + int32_t left_index; + int32_t right_index; + enum hw_point_position pos; + struct fixed31_32 coeff; +}; + +struct pixel_gamma_point { + struct gamma_point r; + struct gamma_point g; + struct gamma_point b; +}; + +enum gamut_remap_select { + GAMUT_REMAP_BYPASS = 0, + GAMUT_REMAP_COMA_COEFF, +}; + +struct vpe_rgb { + uint32_t red; + uint32_t green; + uint32_t blue; +}; + +struct tetrahedral_17x17x17 { + struct vpe_rgb lut0[1229]; + struct vpe_rgb lut1[1228]; + struct vpe_rgb lut2[1228]; + struct vpe_rgb lut3[1228]; +}; +struct tetrahedral_9x9x9 { + struct vpe_rgb lut0[183]; + struct vpe_rgb lut1[182]; + struct vpe_rgb lut2[182]; + struct vpe_rgb lut3[182]; +}; + +struct tetrahedral_params { + union { + struct tetrahedral_17x17x17 tetrahedral_17; + struct tetrahedral_9x9x9 tetrahedral_9; + }; + bool use_tetrahedral_9; + bool use_12bits; +}; + +enum vpe_lut_mode { + LUT_BYPASS, + LUT_RAM_A, + LUT_RAM_B +}; + +#ifdef __cplusplus +} +#endif diff --git a/src/amd/vpelib/src/core/inc/mpc.h b/src/amd/vpelib/src/core/inc/mpc.h new file mode 100644 index 00000000000..7ac9fac4e56 --- /dev/null +++ b/src/amd/vpelib/src/core/inc/mpc.h @@ -0,0 +1,183 @@ +/* Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#pragma once + +#include "vpe_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct mpc; +struct vpe_priv; +struct output_ctx; + +enum mpc_mpccid { + MPC_MPCCID_0 = 0, + MPC_MPCCID_COUNT, +}; + +enum mpc_mux_topsel { + MPC_MUX_TOPSEL_DPP0 = 0, + MPC_MUX_TOPSEL_DISABLE = 0x0f, +}; + +enum mpc_mux_botsel { + MPC_MUX_BOTSEL_MPCC0 = 0, + MPC_MUX_BOTSEL_DISABLE = 0x0f, +}; + +enum mpc_mux_outmux { + MPC_MUX_OUTMUX_MPCC0 = 0, + MPC_MUX_OUTMUX_DISABLE = 0x0f, +}; + +enum mpc_mux_oppid { + MPC_MUX_OPPID_OPP0 = 0, + MPC_MUX_OPPID_DISABLE = 0x0f, +}; + +enum mpcc_blend_mode { + MPCC_BLEND_MODE_BYPASS, // Direct digital bypass + MPCC_BLEND_MODE_TOP_LAYER_PASSTHROUGH, // Top layer pass-through + MPCC_BLEND_MODE_TOP_LAYER_ONLY, // Top layer bleneded with background color + MPCC_BLEND_MODE_TOP_BOT_BLENDING // Top and bottom blending +}; + +enum mpcc_alpha_blend_mode { + MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA, + MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN, + MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA +}; + +/* + * MPCC blending configuration + */ +struct mpcc_blnd_cfg { + struct vpe_color bg_color; /* background color */ + enum mpcc_alpha_blend_mode alpha_mode; /* alpha blend mode */ + bool pre_multiplied_alpha; /* alpha pre-multiplied mode flag */ + uint8_t global_gain; + uint8_t global_alpha; + bool overlap_only; + + /* MPCC top/bottom gain settings */ + int bottom_gain_mode; + int background_color_bpc; + int top_gain; + int bottom_inside_gain; + int bottom_outside_gain; +}; + +enum mpc_output_csc_mode { + MPC_OUTPUT_CSC_DISABLE = 0, + MPC_OUTPUT_CSC_COEF_A, +}; + +struct mpc_denorm_clamp { + int clamp_max_r_cr; + int clamp_min_r_cr; + int clamp_max_g_y; + int clamp_min_g_y; + int clamp_max_b_cb; + int clamp_min_b_cb; +}; + +struct mpc_funcs { + // TODO finalize it + void (*program_mpcc_mux)(struct mpc *mpc, enum mpc_mpccid mpcc_idx, enum mpc_mux_topsel topsel, + enum mpc_mux_botsel botsel, enum mpc_mux_outmux outmux, enum mpc_mux_oppid oppid); + + void (*program_mpcc_blending)( + struct mpc *mpc, enum mpc_mpccid mpcc_idx, struct mpcc_blnd_cfg *blnd_cfg); + + void (*program_mpc_bypass_bg_color)(struct mpc *mpc, struct mpcc_blnd_cfg *blnd_cfg); + + void (*power_on_ogam_lut)(struct mpc *mpc, bool power_on); + + void (*set_output_csc)( + struct mpc *mpc, const uint16_t *regval, enum mpc_output_csc_mode ocsc_mode); + + void (*set_ocsc_default)(struct mpc *mpc, enum vpe_surface_pixel_format pixel_format, + enum color_space color_space, enum mpc_output_csc_mode ocsc_mode); + + void (*program_output_csc)(struct mpc *mpc, enum vpe_surface_pixel_format pixel_format, + enum color_space colorspace, uint16_t *matrix); + + void (*set_output_gamma)(struct mpc *mpc, const struct pwl_params *params); + + void (*set_gamut_remap)(struct mpc *mpc, struct colorspace_transform *gamut_remap); + + void (*power_on_1dlut_shaper_3dlut)(struct mpc *mpc, bool power_on); + + bool (*program_shaper)(struct mpc *mpc, const struct pwl_params *params); + + // using direct config to program the 3dlut specified in params + void (*program_3dlut)(struct mpc *mpc, const struct tetrahedral_params *params); + + // using indirect config to configure the 3DLut + bool (*program_3dlut_indirect)(struct mpc *mpc, + struct vpe_buf *lut0_3_buf, // 3d lut buf which contains the data for lut0-lut3 + bool use_tetrahedral_9, bool use_12bits); + + // Blend-gamma control. + void (*program_1dlut)(struct mpc *mpc, const struct pwl_params *params); + + void (*program_cm_location)(struct mpc *mpc, uint8_t location); + + void (*set_denorm)(struct mpc *mpc, int opp_id, enum color_depth output_depth, + struct mpc_denorm_clamp *denorm_clamp); + + void (*set_out_float_en)(struct mpc *mpc, bool float_enable); + + void (*program_mpc_out)(struct mpc *mpc, enum vpe_surface_pixel_format format); + + void (*set_output_transfer_func)(struct mpc *mpc, struct output_ctx *output_ctx); + + void (*set_mpc_shaper_3dlut)(struct mpc *mpc, const struct transfer_func *func_shaper, + const struct vpe_3dlut *lut3d_func); + + void (*set_blend_lut)(struct mpc *mpc, const struct transfer_func *blend_tf); + + bool (*program_movable_cm)(struct mpc *mpc, const struct transfer_func *func_shaper, + const struct vpe_3dlut *lut3d_func, const struct transfer_func *blend_tf, bool afterblend); + void (*program_crc)(struct mpc *mpc, bool enable); + +}; + +struct mpc { + struct vpe_priv *vpe_priv; + struct mpc_funcs *funcs; + struct pwl_params regamma_params; + struct pwl_params blender_params; + struct pwl_params shaper_params; +}; + +const uint16_t *vpe_find_color_matrix( + enum color_space color_space, enum vpe_surface_pixel_format pixel_format, uint32_t *array_size); + +#ifdef __cplusplus +} +#endif diff --git a/src/amd/vpelib/src/core/inc/opp.h b/src/amd/vpelib/src/core/inc/opp.h new file mode 100644 index 00000000000..c202228f948 --- /dev/null +++ b/src/amd/vpelib/src/core/inc/opp.h @@ -0,0 +1,128 @@ +/* Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#pragma once +#include "vpe_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct opp; +struct vpe_priv; + +enum clamping_range { + CLAMPING_FULL_RANGE = 0, /* No Clamping */ + CLAMPING_LIMITED_RANGE_8BPC, /* 8 bpc: Clamping 1 to FE */ + CLAMPING_LIMITED_RANGE_10BPC, /* 10 bpc: Clamping 4 to 3FB */ + CLAMPING_LIMITED_RANGE_12BPC, /* 12 bpc: Clamping 10 to FEF */ + /* Use programmable clampping value on FMT_CLAMP_COMPONENT_R/G/B. */ + CLAMPING_LIMITED_RANGE_PROGRAMMABLE +}; + +struct clamping_and_pixel_encoding_params { + // enum vpe_pixel_encoding pixel_encoding; /* Pixel Encoding, not used and not initialized yet + // */ + enum clamping_range clamping_level; /* Clamping identifier */ + enum color_depth c_depth; /* Deep color use. */ + uint32_t r_clamp_component_upper; + uint32_t b_clamp_component_upper; + uint32_t g_clamp_component_upper; + uint32_t r_clamp_component_lower; + uint32_t b_clamp_component_lower; + uint32_t g_clamp_component_lower; +}; + +struct bit_depth_reduction_params { + struct { + /* truncate/round */ + /* trunc/round enabled*/ + uint32_t TRUNCATE_ENABLED : 1; + /* 2 bits: 0=6 bpc, 1=8 bpc, 2 = 10bpc*/ + uint32_t TRUNCATE_DEPTH : 2; + /* truncate or round*/ + uint32_t TRUNCATE_MODE : 1; + + /* spatial dither */ + /* Spatial Bit Depth Reduction enabled*/ + uint32_t SPATIAL_DITHER_ENABLED : 1; + /* 2 bits: 0=6 bpc, 1 = 8 bpc, 2 = 10bpc*/ + uint32_t SPATIAL_DITHER_DEPTH : 2; + /* 0-3 to select patterns*/ + uint32_t SPATIAL_DITHER_MODE : 2; + /* Enable RGB random dithering*/ + uint32_t RGB_RANDOM : 1; + /* Enable Frame random dithering*/ + uint32_t FRAME_RANDOM : 1; + /* Enable HighPass random dithering*/ + uint32_t HIGHPASS_RANDOM : 1; + + /* temporal dither*/ + /* frame modulation enabled*/ + uint32_t FRAME_MODULATION_ENABLED : 1; + /* same as for trunc/spatial*/ + uint32_t FRAME_MODULATION_DEPTH : 2; + /* 2/4 gray levels*/ + uint32_t TEMPORAL_LEVEL : 1; + uint32_t FRC25 : 2; + uint32_t FRC50 : 2; + uint32_t FRC75 : 2; + } flags; + + uint32_t r_seed_value; + uint32_t b_seed_value; + uint32_t g_seed_value; + // enum vpe_pixel_encoding pixel_encoding; // not used and not initialized yet +}; + +struct opp_funcs { + + void (*set_clamping)(struct opp *opp, const struct clamping_and_pixel_encoding_params *params); + + void (*set_dyn_expansion)(struct opp *opp, bool enable, enum color_depth color_dpth); + + void (*set_truncation)(struct opp *opp, const struct bit_depth_reduction_params *params); + + void (*set_spatial_dither)(struct opp *opp, const struct bit_depth_reduction_params *params); + + void (*program_bit_depth_reduction)( + struct opp *opp, const struct bit_depth_reduction_params *params); + + void (*program_fmt)(struct opp *opp, struct bit_depth_reduction_params *fmt_bit_depth, + struct clamping_and_pixel_encoding_params *clamping); + + void (*program_pipe_alpha)(struct opp *opp, uint16_t alpha); + + void (*program_pipe_bypass)(struct opp *opp, bool enable); + void (*program_pipe_crc)(struct opp *opp, bool enable); +}; + +struct opp { + struct vpe_priv *vpe_priv; + struct opp_funcs *funcs; +}; + +#ifdef __cplusplus +} +#endif diff --git a/src/amd/vpelib/src/core/inc/plane_desc_writer.h b/src/amd/vpelib/src/core/inc/plane_desc_writer.h new file mode 100644 index 00000000000..a289b247bdc --- /dev/null +++ b/src/amd/vpelib/src/core/inc/plane_desc_writer.h @@ -0,0 +1,101 @@ +/* Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#pragma once + +#include "vpe_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct plane_desc_writer { + struct vpe_buf *buf; /**< store the current buf pointer */ + + /* store the base addr of the currnet config + * i.e. config header + * it is always constructed in emb_buf + */ + uint64_t base_gpu_va; + uint64_t base_cpu_va; + + int32_t num_src; + int32_t num_dst; + enum vpe_status status; +}; + +struct plane_desc_src { + bool tmz; + enum vpe_swizzle_mode_values swizzle; + enum vpe_rotation_angle rotation; + uint32_t base_addr_lo; + uint32_t base_addr_hi; + uint16_t pitch; + uint16_t viewport_x; + uint16_t viewport_y; + uint16_t viewport_w; + uint16_t viewport_h; + uint8_t elem_size; +}; + +struct plane_desc_dst { + bool tmz; + enum vpe_swizzle_mode_values swizzle; + enum vpe_mirror mirror; + uint32_t base_addr_lo; + uint32_t base_addr_hi; + uint16_t pitch; + uint16_t viewport_x; + uint16_t viewport_y; + uint16_t viewport_w; + uint16_t viewport_h; + uint8_t elem_size; +}; + +/** initialize the plane descriptor writer. + * Calls right before building any plane descriptor + * + * /param writer writer instance + * /param buf points to the current buf, + * each config_writer_fill will update the address + * /param nps0 number of plane for source 0 + * /param npd0 number of plane for desination 0 + * /param nps1 number of plane for source 1 + * /param npd1 number of plane for desination 1 + * /param subop subop code + */ +void plane_desc_writer_init(struct plane_desc_writer *writer, struct vpe_buf *buf, int32_t nps0, + int32_t npd0, int32_t nps1, int32_t npd1, int32_t subop); + +/** fill the value to the embedded buffer. */ +void plane_desc_writer_add_source( + struct plane_desc_writer *writer, struct plane_desc_src *source, bool is_plane0); + +/** fill the value to the embedded buffer. */ +void plane_desc_writer_add_destination( + struct plane_desc_writer *writer, struct plane_desc_dst *destination, bool is_plane0); + +#ifdef __cplusplus +} +#endif diff --git a/src/amd/vpelib/src/core/inc/reg_helper.h b/src/amd/vpelib/src/core/inc/reg_helper.h new file mode 100644 index 00000000000..da4641add5c --- /dev/null +++ b/src/amd/vpelib/src/core/inc/reg_helper.h @@ -0,0 +1,275 @@ +/* + * Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + */ + +#ifndef DRIVERS_VPELIB_INC_REG_HELPER_H_ +#define DRIVERS_VPELIB_INC_REG_HELPER_H_ + +#pragma once + +#include +#include "vpe_command.h" +#include "config_writer.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct reg_id_val { + const uint32_t id; + const uint32_t default_value; + uint32_t lastWritten_value; + bool isWritten; +} reg_id_val; + +/** CTX is defined in the .c files */ +#define PROGRAM_ENTRY() \ + struct vpe_priv *vpe_priv = CTX_BASE->vpe_priv; \ + struct CTX *CTX = (struct CTX *)CTX_BASE; \ + struct config_writer *config_writer = &vpe_priv->config_writer; \ + struct vpep_direct_config_packet packet = {0} + +// for use with reg_id_val struct that stores id, default and current val together +#define REG_OFFSET(reg_name) CTX->regs->reg_name.id // Register offset in DWORD +#define REG_DEFAULT(reg_name) CTX->regs->reg_name.default_value +#define REG_IS_WRITTEN(reg_name) CTX->regs->reg_name.isWritten +#define REG_LAST_WRITTEN_VAL(reg_name) CTX->regs->reg_name.lastWritten_value +#define REG_CURRENT(reg_name) \ + (REG_IS_WRITTEN(reg_name) ? REG_LAST_WRITTEN_VAL(reg_name) : REG_DEFAULT(reg_name)) + +#define REG_FIELD_VALUE(field, value) ((uint32_t)((value) << CTX->shift->field) & CTX->mask->field) +#define REG_FIELD_SHIFT(field) CTX->shift->field +#define REG_FIELD_MASK(field) CTX->mask->field +#define VPEC_FIELD_VALUE(field, data) ((uint32_t)((data) << field##__SHIFT) & field##_MASK) + +/* macro to set register fields. */ +#define REG_SET_DEFAULT(reg_name) \ + do { \ + packet.bits.INC = 0; \ + packet.bits.VPEP_CONFIG_DATA_SIZE = 0; \ + packet.bits.VPEP_CONFIG_REGISTER_OFFSET = REG_OFFSET(reg_name); \ + REG_IS_WRITTEN(reg_name) = true; \ + packet.data[0] = REG_LAST_WRITTEN_VAL(reg_name) = REG_DEFAULT(reg_name); \ + config_writer_fill_direct_config_packet(config_writer, &packet); \ + } while (0) + +#define REG_SET(reg_name, init_val, field, val) \ + do { \ + packet.bits.INC = 0; \ + packet.bits.VPEP_CONFIG_DATA_SIZE = 0; \ + packet.bits.VPEP_CONFIG_REGISTER_OFFSET = REG_OFFSET(reg_name); \ + REG_IS_WRITTEN(reg_name) = true; \ + packet.data[0] = REG_LAST_WRITTEN_VAL(reg_name) = \ + (((uint32_t)init_val & ~(REG_FIELD_MASK(field))) | \ + REG_FIELD_VALUE(field, (uint32_t)val)); \ + config_writer_fill_direct_config_packet(config_writer, &packet); \ + } while (0) + +#define REG_SET_2(reg_name, init_val, f1, v1, f2, v2) \ + do { \ + packet.bits.INC = 0; \ + packet.bits.VPEP_CONFIG_DATA_SIZE = 0; \ + packet.bits.VPEP_CONFIG_REGISTER_OFFSET = REG_OFFSET(reg_name); \ + REG_IS_WRITTEN(reg_name) = true; \ + packet.data[0] = REG_LAST_WRITTEN_VAL(reg_name) = \ + (((uint32_t)init_val & ~(REG_FIELD_MASK(f1)) & ~(REG_FIELD_MASK(f2))) | \ + REG_FIELD_VALUE(f1, (uint32_t)v1) | REG_FIELD_VALUE(f2, (uint32_t)v2)); \ + config_writer_fill_direct_config_packet(config_writer, &packet); \ + } while (0) + +#define REG_SET_3(reg_name, init_val, f1, v1, f2, v2, f3, v3) \ + do { \ + packet.bits.INC = 0; \ + packet.bits.VPEP_CONFIG_DATA_SIZE = 0; \ + packet.bits.VPEP_CONFIG_REGISTER_OFFSET = REG_OFFSET(reg_name); \ + REG_IS_WRITTEN(reg_name) = true; \ + packet.data[0] = REG_LAST_WRITTEN_VAL(reg_name) = \ + (((uint32_t)init_val & ~(REG_FIELD_MASK(f1)) & ~(REG_FIELD_MASK(f2)) & \ + ~(REG_FIELD_MASK(f3))) | \ + REG_FIELD_VALUE(f1, (uint32_t)v1) | REG_FIELD_VALUE(f2, (uint32_t)v2) | \ + REG_FIELD_VALUE(f3, (uint32_t)v3)); \ + config_writer_fill_direct_config_packet(config_writer, &packet); \ + } while (0) + +#define REG_SET_4(reg_name, init_val, f1, v1, f2, v2, f3, v3, f4, v4) \ + do { \ + packet.bits.INC = 0; \ + packet.bits.VPEP_CONFIG_DATA_SIZE = 0; \ + packet.bits.VPEP_CONFIG_REGISTER_OFFSET = REG_OFFSET(reg_name); \ + REG_IS_WRITTEN(reg_name) = true; \ + packet.data[0] = REG_LAST_WRITTEN_VAL(reg_name) = \ + (((uint32_t)init_val & ~(REG_FIELD_MASK(f1)) & ~(REG_FIELD_MASK(f2)) & \ + ~(REG_FIELD_MASK(f3)) & ~(REG_FIELD_MASK(f4))) | \ + REG_FIELD_VALUE(f1, (uint32_t)v1) | REG_FIELD_VALUE(f2, (uint32_t)v2) | \ + REG_FIELD_VALUE(f3, (uint32_t)v3) | REG_FIELD_VALUE(f4, (uint32_t)v4)); \ + config_writer_fill_direct_config_packet(config_writer, &packet); \ + } while (0) + +#define REG_SET_5(reg_name, init_val, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \ + do { \ + packet.bits.INC = 0; \ + packet.bits.VPEP_CONFIG_DATA_SIZE = 0; \ + packet.bits.VPEP_CONFIG_REGISTER_OFFSET = REG_OFFSET(reg_name); \ + REG_IS_WRITTEN(reg_name) = true; \ + packet.data[0] = REG_LAST_WRITTEN_VAL(reg_name) = \ + (((uint32_t)init_val & ~(REG_FIELD_MASK(f1)) & ~(REG_FIELD_MASK(f2)) & \ + ~(REG_FIELD_MASK(f3)) & ~(REG_FIELD_MASK(f4)) & ~(REG_FIELD_MASK(f5))) | \ + REG_FIELD_VALUE(f1, (uint32_t)v1) | REG_FIELD_VALUE(f2, (uint32_t)v2) | \ + REG_FIELD_VALUE(f3, (uint32_t)v3) | REG_FIELD_VALUE(f4, (uint32_t)v4) | \ + REG_FIELD_VALUE(f5, (uint32_t)v5)); \ + config_writer_fill_direct_config_packet(config_writer, &packet); \ + } while (0) + +#define REG_SET_6(reg_name, init_val, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \ + do { \ + packet.bits.INC = 0; \ + packet.bits.VPEP_CONFIG_DATA_SIZE = 0; \ + packet.bits.VPEP_CONFIG_REGISTER_OFFSET = REG_OFFSET(reg_name); \ + REG_IS_WRITTEN(reg_name) = true; \ + packet.data[0] = REG_LAST_WRITTEN_VAL(reg_name) = \ + (((uint32_t)init_val & ~(REG_FIELD_MASK(f1)) & ~(REG_FIELD_MASK(f2)) & \ + ~(REG_FIELD_MASK(f3)) & ~(REG_FIELD_MASK(f4)) & ~(REG_FIELD_MASK(f5)) & \ + ~(REG_FIELD_MASK(f6))) | \ + REG_FIELD_VALUE(f1, (uint32_t)v1) | REG_FIELD_VALUE(f2, (uint32_t)v2) | \ + REG_FIELD_VALUE(f3, (uint32_t)v3) | REG_FIELD_VALUE(f4, (uint32_t)v4) | \ + REG_FIELD_VALUE(f5, (uint32_t)v5) | REG_FIELD_VALUE(f6, (uint32_t)v6)); \ + config_writer_fill_direct_config_packet(config_writer, &packet); \ + } while (0) + +#define REG_SET_7(reg_name, init_val, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \ + do { \ + packet.bits.INC = 0; \ + packet.bits.VPEP_CONFIG_DATA_SIZE = 0; \ + packet.bits.VPEP_CONFIG_REGISTER_OFFSET = REG_OFFSET(reg_name); \ + REG_IS_WRITTEN(reg_name) = true; \ + packet.data[0] = REG_LAST_WRITTEN_VAL(reg_name) = \ + (((uint32_t)init_val & ~(REG_FIELD_MASK(f1)) & ~(REG_FIELD_MASK(f2)) & \ + ~(REG_FIELD_MASK(f3)) & ~(REG_FIELD_MASK(f4)) & ~(REG_FIELD_MASK(f5)) & \ + ~(REG_FIELD_MASK(f6)) & ~(REG_FIELD_MASK(f7))) | \ + REG_FIELD_VALUE(f1, (uint32_t)v1) | REG_FIELD_VALUE(f2, (uint32_t)v2) | \ + REG_FIELD_VALUE(f3, (uint32_t)v3) | REG_FIELD_VALUE(f4, (uint32_t)v4) | \ + REG_FIELD_VALUE(f5, (uint32_t)v5) | REG_FIELD_VALUE(f6, (uint32_t)v6) | \ + REG_FIELD_VALUE(f7, (uint32_t)v7)); \ + config_writer_fill_direct_config_packet(config_writer, &packet); \ + } while (0) + +#define REG_SET_8( \ + reg_name, init_val, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \ + do { \ + packet.bits.INC = 0; \ + packet.bits.VPEP_CONFIG_DATA_SIZE = 0; \ + packet.bits.VPEP_CONFIG_REGISTER_OFFSET = REG_OFFSET(reg_name); \ + REG_IS_WRITTEN(reg_name) = true; \ + packet.data[0] = REG_LAST_WRITTEN_VAL(reg_name) = \ + (((uint32_t)init_val & ~(REG_FIELD_MASK(f1)) & ~(REG_FIELD_MASK(f2)) & \ + ~(REG_FIELD_MASK(f3)) & ~(REG_FIELD_MASK(f4)) & ~(REG_FIELD_MASK(f5)) & \ + ~(REG_FIELD_MASK(f6)) & ~(REG_FIELD_MASK(f7)) & ~(REG_FIELD_MASK(f8))) | \ + REG_FIELD_VALUE(f1, (uint32_t)v1) | REG_FIELD_VALUE(f2, (uint32_t)v2) | \ + REG_FIELD_VALUE(f3, (uint32_t)v3) | REG_FIELD_VALUE(f4, (uint32_t)v4) | \ + REG_FIELD_VALUE(f5, (uint32_t)v5) | REG_FIELD_VALUE(f6, (uint32_t)v6) | \ + REG_FIELD_VALUE(f7, (uint32_t)v7) | REG_FIELD_VALUE(f8, (uint32_t)v8)); \ + config_writer_fill_direct_config_packet(config_writer, &packet); \ + } while (0) + +#define REG_SET_9( \ + reg_name, init_val, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9) \ + do { \ + packet.bits.INC = 0; \ + packet.bits.VPEP_CONFIG_DATA_SIZE = 0; \ + packet.bits.VPEP_CONFIG_REGISTER_OFFSET = REG_OFFSET(reg_name); \ + REG_IS_WRITTEN(reg_name) = true; \ + packet.data[0] = REG_LAST_WRITTEN_VAL(reg_name) = \ + (((uint32_t)init_val & ~(REG_FIELD_MASK(f1)) & ~(REG_FIELD_MASK(f2)) & \ + ~(REG_FIELD_MASK(f3)) & ~(REG_FIELD_MASK(f4)) & ~(REG_FIELD_MASK(f5)) & \ + ~(REG_FIELD_MASK(f6)) & ~(REG_FIELD_MASK(f7)) & ~(REG_FIELD_MASK(f8)) & \ + ~(REG_FIELD_MASK(f9))) | \ + REG_FIELD_VALUE(f1, (uint32_t)v1) | REG_FIELD_VALUE(f2, (uint32_t)v2) | \ + REG_FIELD_VALUE(f3, (uint32_t)v3) | REG_FIELD_VALUE(f4, (uint32_t)v4) | \ + REG_FIELD_VALUE(f5, (uint32_t)v5) | REG_FIELD_VALUE(f6, (uint32_t)v6) | \ + REG_FIELD_VALUE(f7, (uint32_t)v7) | REG_FIELD_VALUE(f8, (uint32_t)v8) | \ + REG_FIELD_VALUE(f9, (uint32_t)v9)); \ + config_writer_fill_direct_config_packet(config_writer, &packet); \ + } while (0) + +#define REG_SET_10(reg_name, init_val, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, \ + v8, f9, v9, f10, v10) \ + do { \ + packet.bits.INC = 0; \ + packet.bits.VPEP_CONFIG_DATA_SIZE = 0; \ + packet.bits.VPEP_CONFIG_REGISTER_OFFSET = REG_OFFSET(reg_name); \ + REG_IS_WRITTEN(reg_name) = true; \ + packet.data[0] = REG_LAST_WRITTEN_VAL(reg_name) = \ + (((uint32_t)init_val & ~(REG_FIELD_MASK(f1)) & ~(REG_FIELD_MASK(f2)) & \ + ~(REG_FIELD_MASK(f3)) & ~(REG_FIELD_MASK(f4)) & ~(REG_FIELD_MASK(f5)) & \ + ~(REG_FIELD_MASK(f6)) & ~(REG_FIELD_MASK(f7)) & ~(REG_FIELD_MASK(f8)) & \ + ~(REG_FIELD_MASK(f9)) & ~(REG_FIELD_MASK(f10))) | \ + REG_FIELD_VALUE(f1, (uint32_t)v1) | REG_FIELD_VALUE(f2, (uint32_t)v2) | \ + REG_FIELD_VALUE(f3, (uint32_t)v3) | REG_FIELD_VALUE(f4, (uint32_t)v4) | \ + REG_FIELD_VALUE(f5, (uint32_t)v5) | REG_FIELD_VALUE(f6, (uint32_t)v6) | \ + REG_FIELD_VALUE(f7, (uint32_t)v7) | REG_FIELD_VALUE(f8, (uint32_t)v8) | \ + REG_FIELD_VALUE(f9, (uint32_t)v9) | REG_FIELD_VALUE(f10, (uint32_t)v10)); \ + config_writer_fill_direct_config_packet(config_writer, &packet); \ + } while (0) + +#define REG_UPDATE(reg, field, val) REG_SET(reg, REG_CURRENT(reg), field, val) +#define REG_UPDATE_2(reg, f1, v1, f2, v2) REG_SET_2(reg, REG_CURRENT(reg), f1, v1, f2, v2) +#define REG_UPDATE_3(reg, f1, v1, f2, v2, f3, v3) \ + REG_SET_3(reg, REG_CURRENT(reg), f1, v1, f2, v2, f3, v3) +#define REG_UPDATE_4(reg, f1, v1, f2, v2, f3, v3, f4, v4) \ + REG_SET_4(reg, REG_CURRENT(reg), f1, v1, f2, v2, f3, v3, f4, v4) +#define REG_UPDATE_5(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \ + REG_SET_5(reg, REG_CURRENT(reg), f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) + +#define REG_UPDATE_6(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \ + REG_SET_6(reg, REG_CURRENT(reg), f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) + +#define REG_UPDATE_7(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \ + REG_SET_7(reg, REG_CURRENT(reg), f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) + +#define REG_UPDATE_8(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \ + REG_SET_8(reg, REG_CURRENT(reg), f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) + +#define REG_UPDATE_9(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9) \ + REG_SET_9(reg, REG_CURRENT(reg), f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, \ + v8, f9, v9) + +#define REG_UPDATE_10( \ + reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10, v10) \ + REG_SET_10(reg, REG_CURRENT(reg), f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, \ + v8, f9, v9, f10, v10) + +#define REG_SET_DEFAULT(reg_name) \ + do { \ + packet.bits.INC = 0; \ + packet.bits.VPEP_CONFIG_DATA_SIZE = 0; \ + packet.bits.VPEP_CONFIG_REGISTER_OFFSET = REG_OFFSET(reg_name); \ + REG_IS_WRITTEN(reg_name) = true; \ + packet.data[0] = REG_LAST_WRITTEN_VAL(reg_name) = REG_DEFAULT(reg_name); \ + config_writer_fill_direct_config_packet(config_writer, &packet); \ + } while (0) + +#ifdef __cplusplus +} +#endif + +#endif /* DRIVERS_VPELIB_INC_REG_HELPER_H_ */ diff --git a/src/amd/vpelib/src/core/inc/resource.h b/src/amd/vpelib/src/core/inc/resource.h new file mode 100644 index 00000000000..e35c28f8737 --- /dev/null +++ b/src/amd/vpelib/src/core/inc/resource.h @@ -0,0 +1,160 @@ +/* Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#pragma once + +#include "vpe_types.h" +#include "cmd_builder.h" +#include "vpec.h" +#include "cdc.h" +#include "dpp.h" +#include "mpc.h" +#include "opp.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct vpe_priv; +struct vpe_cmd_info; +struct segment_ctx; + +#define MAX_PIPE 2 + +enum vpe_cmd_ops; + +/** struct resource stores all the hw subblocks function pointers + * which assist in constructing the command packets. + * + * As differnt asic may have its own deviation in the subblocks, + * each hw ip has its own set of function pointers to expose + * the programming interface of the blocks. + * + * The upper level should have a sequencer that constructs the + * final programming sequence using subblock functions + */ +struct resource { + struct vpe_priv *vpe_priv; + struct vpec vpec; + + bool (*check_input_color_space)(struct vpe_priv *vpe_priv, enum vpe_surface_pixel_format format, + const struct vpe_color_space *vcs); + + bool (*check_output_color_space)(struct vpe_priv *vpe_priv, + enum vpe_surface_pixel_format format, const struct vpe_color_space *vcs); + + bool (*check_h_mirror_support)(bool *input_mirror, bool *output_miror); + + enum vpe_status (*calculate_segments)( + struct vpe_priv *vpe_priv, const struct vpe_build_param *params); + + enum vpe_status (*set_num_segments)(struct vpe_priv *vpe_priv, struct stream_ctx *stream_ctx, + struct scaler_data *scl_data, struct vpe_rect *src_rect, struct vpe_rect *dst_rect, + uint32_t *max_seg_width); + + bool (*split_bg_gap)(struct vpe_rect *gaps, const struct vpe_rect *target_rect, + uint32_t max_width, uint16_t max_gaps, uint16_t *num_gaps, uint16_t num_instances); + + void (*calculate_dst_viewport_and_active)( + struct segment_ctx *segment_ctx, uint32_t max_seg_width); + + uint16_t (*find_bg_gaps)(struct vpe_priv *vpe_priv, const struct vpe_rect *target_rect, + struct vpe_rect *gaps, uint16_t max_gaps); + + void (*create_bg_segments)( + struct vpe_priv *vpe_priv, struct vpe_rect *gaps, uint16_t gaps_cnt, enum vpe_cmd_ops ops); + + enum vpe_status (*populate_cmd_info)(struct vpe_priv *vpe_priv); + + int32_t (*program_frontend)(struct vpe_priv *vpe_priv, uint32_t pipe_idx, uint32_t cmd_idx, + uint32_t cmd_input_idx, bool seg_only); + + int32_t (*program_backend)( + struct vpe_priv *vpe_priv, uint32_t pipe_idx, uint32_t cmd_idx, bool seg_only); + + void (*get_bufs_req)(struct vpe_priv *vpe_priv, struct vpe_bufs_req *req); + + void (*get_tf_pwl_params)(const struct transfer_func *output_tf, struct pwl_params **lut_params, + enum cm_type vpe_cm_type); + + // Indicates the nominal range hdr input content should be in during processing. + int internal_hdr_normalization; + + // vpep components + struct cdc *cdc[MAX_PIPE]; + struct dpp *dpp[MAX_PIPE]; + struct opp *opp[MAX_PIPE]; + struct mpc *mpc[MAX_PIPE]; + struct cmd_builder cmd_builder; +}; + +/** translate the vpe ip version into vpe hw level */ +enum vpe_ip_level vpe_resource_parse_ip_version( + uint8_t mj, uint8_t mi, uint8_t rv); + +/** initialize the resource ased on vpe hw level */ +enum vpe_status vpe_construct_resource( + struct vpe_priv *vpe_priv, enum vpe_ip_level level, struct resource *resource); + +/** destroy the resource */ +void vpe_destroy_resource(struct vpe_priv *vpe_priv, struct resource *res); + +/** alloc segment ctx*/ +struct segment_ctx *vpe_alloc_segment_ctx(struct vpe_priv *vpe_priv, uint16_t num_segments); + +/** stream ctx */ +struct stream_ctx *vpe_alloc_stream_ctx(struct vpe_priv *vpe_priv, uint32_t num_streams); + +void vpe_free_stream_ctx(struct vpe_priv *vpe_priv); + +/** output ctx */ +void vpe_free_output_ctx(struct vpe_priv *vpe_priv); + +/** pipe resource management */ +void vpe_pipe_reset(struct vpe_priv *vpe_priv); + +void vpe_pipe_reclaim(struct vpe_priv *vpe_priv, struct vpe_cmd_info *cmd_info); + +struct pipe_ctx *vpe_pipe_find_owner(struct vpe_priv *vpe_priv, uint32_t stream_idx, bool *reuse); + +/** resource helper */ +void vpe_clip_stream( + struct vpe_rect *src_rect, struct vpe_rect *dst_rect, const struct vpe_rect *target_rect); + +void calculate_scaling_ratios(struct scaler_data *scl_data, struct vpe_rect *src_rect, + struct vpe_rect *dst_rect, enum vpe_surface_pixel_format format); + +uint16_t vpe_get_num_segments(struct vpe_priv *vpe_priv, const struct vpe_rect *src, + const struct vpe_rect *dst, const uint32_t max_seg_width); + +enum vpe_status vpe_resource_build_scaling_params(struct segment_ctx *segment); + +void vpe_handle_output_h_mirror(struct vpe_priv *vpe_priv); + +void vpe_resource_build_bit_depth_reduction_params( + struct opp *opp, struct bit_depth_reduction_params *fmt_bit_depth); + +#ifdef __cplusplus +} +#endif diff --git a/src/amd/vpelib/src/core/inc/shaper_builder.h b/src/amd/vpelib/src/core/inc/shaper_builder.h new file mode 100644 index 00000000000..a3b2f187758 --- /dev/null +++ b/src/amd/vpelib/src/core/inc/shaper_builder.h @@ -0,0 +1,40 @@ +/* Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#pragma once +#include "vpe_types.h" +#include "hw_shared.h" +#include + +#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0])) +#define SHAPER_EXP_MAX_IN 16 + +struct vpe_shaper_setup_in { + double source_luminance; + double shaper_in_max; + bool use_const_hdr_mult; +}; + +enum vpe_status vpe_build_shaper( + const struct vpe_shaper_setup_in *shaper_in, struct pwl_params *shaper_out); diff --git a/src/amd/vpelib/src/core/inc/transform.h b/src/amd/vpelib/src/core/inc/transform.h new file mode 100644 index 00000000000..cb468aa7c9c --- /dev/null +++ b/src/amd/vpelib/src/core/inc/transform.h @@ -0,0 +1,113 @@ +/* Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#pragma once + +#include +#include +#include +#include "vpe_hw_types.h" +#include "fixed31_32.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define VPE_GAMUT_REMAP_MATRIX_SIZE 12 + +enum gamut_adjust_type { + GAMUT_ADJUST_TYPE_BYPASS = 0, + GAMUT_ADJUST_TYPE_SW /* use adjustments */ +}; + +struct gamut_remap_matrix { + struct fixed31_32 matrix[VPE_GAMUT_REMAP_MATRIX_SIZE]; + enum gamut_adjust_type adjust_type; +}; + +enum lb_memory_config { + /* Enable all 3 pieces of memory */ + LB_MEMORY_CONFIG_0 = 0, + + /* Enable only the first piece of memory */ + LB_MEMORY_CONFIG_1 = 1, + + /* Enable only the second piece of memory */ + LB_MEMORY_CONFIG_2 = 2, + + /* Only applicable in 4:2:0 mode, enable all 3 pieces of memory and the + * last piece of chroma memory used for the luma storage + */ + LB_MEMORY_CONFIG_3 = 3 +}; + +struct scaling_ratios { + struct fixed31_32 horz; + struct fixed31_32 vert; + struct fixed31_32 horz_c; + struct fixed31_32 vert_c; +}; + +struct sharpness_adj { + int horz; + int vert; +}; + +struct line_buffer_params { + bool alpha_en; +}; + +struct scl_inits { + struct fixed31_32 h; + struct fixed31_32 h_c; + struct fixed31_32 v; + struct fixed31_32 v_c; +}; + +struct scaler_data { + uint32_t h_active; + uint32_t v_active; + struct vpe_scaling_taps taps; + struct vpe_rect viewport; + struct vpe_rect viewport_c; + struct vpe_rect dst_viewport; + struct vpe_rect dst_viewport_c; + struct vpe_rect recout; + struct scaling_ratios ratios; + struct scl_inits inits; + struct sharpness_adj sharpness; + enum vpe_surface_pixel_format format; + struct line_buffer_params lb_params; + struct vpe_scaling_filter_coeffs *polyphase_filter_coeffs; +}; + +const uint16_t *vpe_get_filter_2tap_64p(void); +const uint16_t *vpe_get_2tap_bilinear_64p(void); +const uint16_t *vpe_get_filter_4tap_64p(struct fixed31_32 ratio); +const uint16_t *vpe_get_filter_6tap_64p(struct fixed31_32 ratio); +const uint16_t *vpe_get_filter_8tap_64p(struct fixed31_32 ratio); + +#ifdef __cplusplus +} +#endif diff --git a/src/amd/vpelib/src/core/inc/vpe_assert.h b/src/amd/vpelib/src/core/inc/vpe_assert.h new file mode 100644 index 00000000000..df67d3ce6bd --- /dev/null +++ b/src/amd/vpelib/src/core/inc/vpe_assert.h @@ -0,0 +1,52 @@ +/* Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#if defined(_WIN32) + +#define VPE_DEBUG_BREAK() __debugbreak() + +#else + +#include +#define VPE_DEBUG_BREAK() raise(SIGTRAP); + +#endif + +#ifdef _DEBUG +#define VPE_ASSERT(_expr) assert(_expr) +#else +#define VPE_ASSERT(_expr) ((void)0) +#endif + +#ifdef __cplusplus +} +#endif diff --git a/src/amd/vpelib/src/core/inc/vpe_command.h b/src/amd/vpelib/src/core/inc/vpe_command.h new file mode 100644 index 00000000000..75286f19018 --- /dev/null +++ b/src/amd/vpelib/src/core/inc/vpe_command.h @@ -0,0 +1,206 @@ +/* Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +/**************** + * VPE OP Codes + ****************/ +enum VPE_CMD_OPCODE { + VPE_CMD_OPCODE_NOP = 0x0, + VPE_CMD_OPCODE_VPE_DESC = 0x1, + VPE_CMD_OPCODE_PLANE_CFG = 0x2, + VPE_CMD_OPCODE_VPEP_CFG = 0x3, + VPE_CMD_OPCODE_FENCE = 0x5, + VPE_CMD_OPCODE_TRAP = 0x6, + VPE_CMD_OPCODE_REG_WRITE = 0x7, + VPE_CMD_OPCODE_POLL_REGMEM = 0x8, + VPE_CMD_OPCODE_ATOMIC = 0xA, + VPE_CMD_OPCODE_PLANE_FILL = 0xB, + VPE_CMD_OPCODE_TIMESTAMP = 0xD +}; + +/** Generic Command Header + * Generic Commands include: + * Noop, Fence, Trap, + * RegisterWrite, PollRegisterWriteMemory, + * SetLocalTimestamp, GetLocalTimestamp + * GetGlobalGPUTimestamp */ +#define VPE_HEADER_SUB_OPCODE__SHIFT 8 +#define VPE_HEADER_SUB_OPCODE_MASK 0x0000FF00 +#define VPE_HEADER_OPCODE__SHIFT 0 +#define VPE_HEADER_OPCODE_MASK 0x000000FF + +#define VPE_CMD_HEADER(op, subop) \ + (((subop << VPE_HEADER_SUB_OPCODE__SHIFT) & VPE_HEADER_SUB_OPCODE_MASK) | \ + ((op << VPE_HEADER_OPCODE__SHIFT) & VPE_HEADER_OPCODE_MASK)) + +/*************************** + * VPE Descriptor + ***************************/ +#define VPE_DESC_CD__SHIFT 16 +#define VPE_DESC_CD_MASK 0x000F0000 + +#define VPE_DESC_ADDR__SHIFT 32 +#define VPE_DESC_HIGH_ADDR_MASK 0xFFFFFFFF00000000 +/* The lowest bits are reuse and tmz as bit 1 and bit 0. + Smibs will substract the address with emb gpuva to + get offset and then reuse bit will be preserved + So as long as the embedded buffer is allocated + at correct alignment (currently low addr is [31:2] + which means we need a 4 byte(2 bit) alignment), + the offset generated will still cover the + reuse bit as part of it. + Ex : Address : 0x200036 GPU Virtual Address : 0x200000 + offset is 0x36 which keeps the reuse bit */ +#define VPE_DESC_LOW_ADDR_MASK 0x00000000FFFFFFFF +#define VPE_DESC_REUSE_TMZ_MASK 0x0000000000000003 + +#define VPE_DESC_NUM_CONFIG_DESCRIPTOR__SHIFT 0 +#define VPE_DESC_NUM_CONFIG_DESCRIPTOR_MASK 0x000000FF + +#define VPE_DESC_REUSE__MASK 0x00000002 + +#define VPE_DESC_CMD_HEADER(cd) \ + (VPE_CMD_HEADER(VPE_CMD_OPCODE_VPE_DESC, 0) | (((cd) << VPE_DESC_CD__SHIFT) & VPE_DESC_CD_MASK)) + +/*************************** + * VPE Plane Config + ***************************/ +enum VPE_PLANE_CFG_SUBOP { + VPE_PLANE_CFG_SUBOP_1_TO_1 = 0x0, + VPE_PLANE_CFG_SUBOP_2_TO_1 = 0x1, + VPE_PLANE_CFG_SUBOP_2_TO_2 = 0x2 +}; + +#define VPE_PLANE_CFG_ONE_PLANE 0 +#define VPE_PLANE_CFG_TWO_PLANES 1 + +#define VPE_PLANE_CFG_NPS0__SHIFT 16 +#define VPE_PLANE_CFG_NPS0_MASK 0x00030000 + +#define VPE_PLANE_CFG_NPD0__SHIFT 18 +#define VPE_PLANE_CFG_NPD0_MASK 0x000C0000 + +#define VPE_PLANE_CFG_NPS1__SHIFT 20 +#define VPE_PLANE_CFG_NPS1_MASK 0x00300000 + +#define VPE_PLANE_CFG_NPD1__SHIFT 22 +#define VPE_PLANE_CFG_NPD1_MASK 0x00C00000 + +#define VPE_PLANE_CFG_TMZ__SHIFT 16 +#define VPE_PLANE_CFG_TMZ_MASK 0x00010000 + +#define VPE_PLANE_CFG_SWIZZLE_MODE__SHIFT 3 +#define VPE_PLANE_CFG_SWIZZLE_MODE_MASK 0x000000F8 + +#define VPE_PLANE_CFG_ROTATION__SHIFT 0 +#define VPE_PLANE_CFG_ROTATION_MASK 0x00000003 + +#define VPE_PLANE_CFG_MIRROR__SHIFT 0 +#define VPE_PLANE_CFG_MIRROR_MASK 0x00000003 + +#define VPE_PLANE_ADDR_LO__SHIFT 0 +#define VPE_PLANE_ADDR_LO_MASK 0xFFFFFF00 + +#define VPE_PLANE_CFG_PITCH__SHIFT 0 +#define VPE_PLANE_CFG_PITCH_MASK 0x00003FFF + +#define VPE_PLANE_CFG_VIEWPORT_Y__SHIFT 16 +#define VPE_PLANE_CFG_VIEWPORT_Y_MASK 0x3FFF0000 +#define VPE_PLANE_CFG_VIEWPORT_X__SHIFT 0 +#define VPE_PLANE_CFG_VIEWPORT_X_MASK 0x00003FFF + +#define VPE_PLANE_CFG_VIEWPORT_HEIGHT__SHIFT 16 +#define VPE_PLANE_CFG_VIEWPORT_HEIGHT_MASK 0x1FFF0000 +#define VPE_PLANE_CFG_VIEWPORT_ELEMENT_SIZE__SHIFT 13 +#define VPE_PLANE_CFG_VIEWPORT_ELEMENT_SIZE_MASK 0x0000E000 +#define VPE_PLANE_CFG_VIEWPORT_WIDTH__SHIFT 0 +#define VPE_PLANE_CFG_VIEWPORT_WIDTH_MASK 0x00001FFF + +enum VPE_PLANE_CFG_ELEMENT_SIZE { + VPE_PLANE_CFG_ELEMENT_SIZE_8BPE = 0, + VPE_PLANE_CFG_ELEMENT_SIZE_16BPE = 1, + VPE_PLANE_CFG_ELEMENT_SIZE_32BPE = 2, + VPE_PLANE_CFG_ELEMENT_SIZE_64BPE = 3 +}; + +#define VPE_PLANE_CFG_CMD_HEADER(subop, nps0, npd0, nps1, npd1) \ + (VPE_CMD_HEADER(VPE_CMD_OPCODE_PLANE_CFG, subop) | \ + (((nps0) << VPE_PLANE_CFG_NPS0__SHIFT) & VPE_PLANE_CFG_NPS0_MASK) | \ + (((npd0) << VPE_PLANE_CFG_NPD0__SHIFT) & VPE_PLANE_CFG_NPD0_MASK) | \ + (((nps1) << VPE_PLANE_CFG_NPS1__SHIFT) & VPE_PLANE_CFG_NPS1_MASK) | \ + (((npd0) << VPE_PLANE_CFG_NPD1__SHIFT) & VPE_PLANE_CFG_NPD1_MASK)) + +/************************ + * VPEP Config + ************************/ +enum VPE_VPEP_CFG_SUBOP { + VPE_VPEP_CFG_SUBOP_DIR_CFG = 0x0, + VPE_VPEP_CFG_SUBOP_IND_CFG = 0x1 +}; + +// Direct Config Command Header +#define VPE_DIR_CFG_HEADER_ARRAY_SIZE__SHIFT 16 +#define VPE_DIR_CFG_HEADER_ARRAY_SIZE_MASK 0xFFFF0000 + +#define VPE_DIR_CFG_CMD_HEADER(arr_sz) \ + (VPE_CMD_HEADER(VPE_CMD_OPCODE_VPEP_CFG, VPE_VPEP_CFG_SUBOP_DIR_CFG) | \ + (((arr_sz) << VPE_DIR_CFG_HEADER_ARRAY_SIZE__SHIFT) & VPE_DIR_CFG_HEADER_ARRAY_SIZE_MASK)) + +#define VPE_DIR_CFG_PKT_REGISTER_OFFSET__SHIFT 2 +#define VPE_DIR_CFG_PKT_REGISTER_OFFSET_MASK 0x000FFFFC + +#define VPE_DIR_CFG_PKT_DATA_SIZE__SHIFT 20 +#define VPE_DIR_CFG_PKT_DATA_SIZE_MASK 0xFFF00000 + +// InDirect Config Command Header +#define VPE_IND_CFG_HEADER_NUM_DST__SHIFT 28 +#define VPE_IND_CFG_HEADER_NUM_DST_MASK 0xF0000000 + +#define VPE_IND_CFG_CMD_HEADER(num_dst) \ + (VPE_CMD_HEADER(VPE_CMD_OPCODE_VPEP_CFG, VPE_VPEP_CFG_SUBOP_IND_CFG) | \ + ((((uint32_t)num_dst) << VPE_IND_CFG_HEADER_NUM_DST__SHIFT) & \ + VPE_IND_CFG_HEADER_NUM_DST_MASK)) + +#define VPE_IND_CFG_DATA_ARRAY_SIZE__SHIFT 0 +#define VPE_IND_CFG_DATA_ARRAY_SIZE_MASK 0x0007FFFF + +#define VPE_IND_CFG_PKT_REGISTER_OFFSET__SHIFT 2 +#define VPE_IND_CFG_PKT_REGISTER_OFFSET_MASK 0x000FFFFC + +/************************** + * Poll Reg/Mem Sub-OpCode + **************************/ +enum VPE_POLL_REGMEM_SUBOP { + VPE_POLL_REGMEM_SUBOP_REGMEM = 0x0, + VPE_POLL_REGMEM_SUBOP_REGMEM_WRITE = 0x1 +}; + +#ifdef __cplusplus +} +#endif diff --git a/src/amd/vpelib/src/core/inc/vpe_desc_writer.h b/src/amd/vpelib/src/core/inc/vpe_desc_writer.h new file mode 100644 index 00000000000..e9c2a92c289 --- /dev/null +++ b/src/amd/vpelib/src/core/inc/vpe_desc_writer.h @@ -0,0 +1,70 @@ +/* Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#pragma once + +#include "vpe_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct vpe_desc_writer { + struct vpe_buf *buf; /**< store the current buf pointer */ + + /* store the base addr of the currnet config + * i.e. config header + * it is always constructed in emb_buf + */ + uint64_t base_gpu_va; + uint64_t base_cpu_va; + + uint32_t num_config_desc; + bool plane_desc_added; + enum vpe_status status; +}; + +/** initialize the vpe descriptor writer. + * Calls right before building any vpe descriptor + * + * /param writer writer instance + * /param buf points to the current buf, + * each config_writer_fill will update the address + * /param cd count down of slice in a frame + */ +void vpe_desc_writer_init(struct vpe_desc_writer *writer, struct vpe_buf *buf, int cd); + +/** fill the value to the command buffer. */ +void vpe_desc_writer_add_plane_desc( + struct vpe_desc_writer *writer, uint64_t plane_desc_addr, bool tmz); + +/** fill the value to the command buffer. */ +void vpe_desc_writer_add_config_desc( + struct vpe_desc_writer *writer, uint64_t config_desc_addr, bool reuse, bool tmz); + +void vpe_desc_writer_complete(struct vpe_desc_writer *writer); + +#ifdef __cplusplus +} +#endif diff --git a/src/amd/vpelib/src/core/inc/vpe_priv.h b/src/amd/vpelib/src/core/inc/vpe_priv.h new file mode 100644 index 00000000000..aa3fa0bd57f --- /dev/null +++ b/src/amd/vpelib/src/core/inc/vpe_priv.h @@ -0,0 +1,262 @@ +/* Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#pragma once + +#include "vpe_types.h" +#include "resource.h" +#include "transform.h" +#include "color.h" +#include "color_gamma.h" +#include "vpe_desc_writer.h" +#include "plane_desc_writer.h" +#include "config_writer.h" +#include "color_cs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define vpe_zalloc(size) vpe_priv->init.funcs.zalloc(vpe_priv->init.funcs.mem_ctx, size) +#define vpe_free(ptr) vpe_priv->init.funcs.free(vpe_priv->init.funcs.mem_ctx, (ptr)) +#define vpe_log(...) \ + do { \ + vpe_priv->init.funcs.log(vpe_priv->init.funcs.log_ctx, "vpe: "); \ + vpe_priv->init.funcs.log(vpe_priv->init.funcs.log_ctx, __VA_ARGS__); \ + } while (0) + +#define container_of(ptr, type, member) (type *)(void *)((char *)ptr - offsetof(type, member)) + +#define VPE_MIN_VIEWPORT_SIZE \ + 2 // chroma viewport size is half of it, thus need to be 2 for YUV420 + // for simplication we just use 2 for all types +#define MAX_VPE_CMD 256 // TODO Dynamic allocation + +#define MAX_LINE_SIZE 1024 // without 16 pixels for the seams +#define MAX_LINE_CNT 4 + +enum vpe_cmd_ops { + VPE_CMD_OPS_BLENDING, + VPE_CMD_OPS_BG, + VPE_CMD_OPS_COMPOSITING, + VPE_CMD_OPS_BG_VSCF_INPUT, // For visual confirm input + VPE_CMD_OPS_BG_VSCF_OUTPUT, // For visual confirm output +}; + +enum vpe_cmd_type { + VPE_CMD_TYPE_COMPOSITING, + VPE_CMD_TYPE_BG, + VPE_CMD_TYPE_BG_VSCF_INPUT, // For visual confirm input + VPE_CMD_TYPE_BG_VSCF_OUTPUT, // For visual confirm output + VPE_CMD_TYPE_COUNT +}; + +/** this represents a segement context. + * each segment has its own version of data */ +struct segment_ctx { + uint16_t segment_idx; + struct stream_ctx *stream_ctx; + struct scaler_data scaler_data; +}; + +struct vpe_cmd_input { + uint16_t stream_idx; + struct scaler_data scaler_data; +}; + +struct vpe_cmd_info { + enum vpe_cmd_ops ops; + uint8_t cd; // count down value + + // input + uint16_t num_inputs; + struct vpe_cmd_input inputs[MAX_PIPE]; + + // output + struct vpe_rect dst_viewport; + struct vpe_rect dst_viewport_c; + + bool tm_enabled; + bool is_begin; + bool is_end; +}; + +struct config_record { + uint64_t config_base_addr; + int64_t config_size; +}; + +/** represents a stream input, i.e. common to all segments */ +struct stream_ctx { + struct vpe_priv *vpe_priv; + + int32_t stream_idx; + struct vpe_stream stream; /**< stores all the input data */ + + uint16_t num_segments; + struct segment_ctx *segment_ctx; + + uint16_t num_configs; // shared among same stream + uint16_t num_stream_op_configs[VPE_CMD_TYPE_COUNT]; // shared among same cmd type within the + // same stream + struct config_record configs[16]; + struct config_record stream_op_configs[VPE_CMD_TYPE_COUNT][16]; + + // cached color properties + bool per_pixel_alpha; + enum color_transfer_func tf; + enum color_space cs; + bool enable_3dlut; + bool update_3dlut; + + union { + struct { + unsigned int color_space : 1; + unsigned int transfer_function : 1; + unsigned int pixel_format : 1; + unsigned int reserved : 1; + }; + unsigned int u32All; + } dirty_bits; + + struct bias_and_scale *bias_scale; + struct transfer_func *input_tf; + struct vpe_csc_matrix *input_cs; + struct colorspace_transform *gamut_remap; + struct transfer_func *in_shaper_func; // for shaper lut + struct vpe_3dlut *lut3d_func; // for 3dlut + struct transfer_func *blend_tf; // for 1dlut + white_point_gain white_point_gain; + + bool flip_horizonal_output; + struct vpe_color_adjust color_adjustments; // stores the current color adjustments params + struct fixed31_32 + tf_scaling_factor; // a scaling factor that acts as a gain on the transfer function +}; + +struct output_ctx { + // stores the paramters built for generating vpep configs + struct vpe_surface_info surface; + struct vpe_color bg_color; + struct vpe_rect target_rect; + enum vpe_alpha_mode alpha_mode; + struct vpe_clamping_params clamping_params; + + // cached color properties + enum color_transfer_func tf; + enum color_space cs; + + uint32_t num_configs; + struct config_record configs[8]; + + union { + struct { + unsigned int color_space : 1; + unsigned int transfer_function : 1; + unsigned int lut3d : 1; + unsigned int reserved : 1; + }; + unsigned int u32All; + } dirty_bits; + + struct transfer_func *output_tf; + const struct transfer_func *in_shaper_func; // for shaper lut + const struct vpe_3dlut *lut3d_func; // for 3dlut + const struct transfer_func *blend_tf; // for 1dlut + struct colorspace_transform *gamut_remap; // post blend gamut remap + + struct { + uint32_t hdr_metadata : 1; + uint32_t reserved : 31; + } flags; + struct vpe_hdr_metadata hdr_metadata; +}; + +#define PIPE_CTX_NO_OWNER ((uint32_t)(-1)) + +struct pipe_ctx { + uint32_t pipe_idx; + uint32_t owner; // stream_idx + bool is_top_pipe; + int32_t top_pipe_idx; +}; + +struct config_frontend_cb_ctx { + struct vpe_priv *vpe_priv; + uint32_t stream_idx; + bool stream_sharing; + bool stream_op_sharing; + enum vpe_cmd_type cmd_type; // command type, i.e. bg or compositing +}; + +struct config_backend_cb_ctx { + struct vpe_priv *vpe_priv; + bool share; // add to output_ctx if true +}; + +/** internal vpe instance */ +struct vpe_priv { + /** public */ + struct vpe pub; /**< public member */ + + /** internal */ + struct vpe_init_data init; + struct resource resource; + struct calculate_buffer cal_buffer; + struct vpe_bufs_req bufs_required; /**< cached required buffer size for the checked ops */ + + // number of total vpe cmds + uint16_t num_vpe_cmds; + struct vpe_cmd_info vpe_cmd_info[MAX_VPE_CMD]; + bool ops_support; + + // writers + struct vpe_desc_writer vpe_desc_writer; + struct plane_desc_writer plane_desc_writer; + struct config_writer config_writer; + struct config_frontend_cb_ctx fe_cb_ctx; + struct config_backend_cb_ctx be_cb_ctx; + + // input ctx + uint32_t num_streams; + struct stream_ctx *stream_ctx; + + // output ctx + struct output_ctx output_ctx; + + uint16_t num_pipe; + struct pipe_ctx pipe_ctx[MAX_PIPE]; + + // internal temp structure for creating pure BG filling + struct vpe_build_param *dummy_input_param; + struct vpe_stream *dummy_stream; + bool scale_yuv_matrix; // this is a flag that forces scaling the yuv->rgb matrix + // when embedding the color adjustments + + enum vpe_expansion_mode expansion_mode; +}; + +#ifdef __cplusplus +} +#endif diff --git a/src/amd/vpelib/src/core/inc/vpe_visual_confirm.h b/src/amd/vpelib/src/core/inc/vpe_visual_confirm.h new file mode 100644 index 00000000000..9206d6d6f9c --- /dev/null +++ b/src/amd/vpelib/src/core/inc/vpe_visual_confirm.h @@ -0,0 +1,43 @@ +/* Copyright 2023 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include "resource.h" +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#define VISUAL_CONFIRM_HEIGHT 8 + +struct vpe_color vpe_get_visual_confirm_color(enum vpe_surface_pixel_format format, + struct vpe_color_space cs, enum color_space output_cs, struct transfer_func *output_tf, + bool enable_3dLut); + +enum vpe_status vpe_create_visual_confirm_segs( + struct vpe_priv *vpe_priv, const struct vpe_build_param *params, uint32_t max_seg_width); + +#ifdef __cplusplus +} +#endif diff --git a/src/amd/vpelib/src/core/inc/vpec.h b/src/amd/vpelib/src/core/inc/vpec.h new file mode 100644 index 00000000000..66633b91150 --- /dev/null +++ b/src/amd/vpelib/src/core/inc/vpec.h @@ -0,0 +1,51 @@ +/* Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#pragma once + +#include "vpe_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct vpec; +struct vpe_priv; + +struct vpec_funcs { + /** functions for capability check */ + bool (*check_swmode_support)(struct vpec *vpec, enum vpe_swizzle_mode_values sw_mode); + + bool (*get_dcc_compression_cap)(struct vpec *vpec, const struct vpe_dcc_surface_param *input, + struct vpe_surface_dcc_cap *output); +}; + +struct vpec { + struct vpe_priv *vpe_priv; + struct vpec_funcs *funcs; +}; + +#ifdef __cplusplus +} +#endif diff --git a/src/amd/vpelib/src/core/mpc.c b/src/amd/vpelib/src/core/mpc.c new file mode 100644 index 00000000000..f7a4acb2130 --- /dev/null +++ b/src/amd/vpelib/src/core/mpc.c @@ -0,0 +1,179 @@ +/* Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include +#include "vpe_priv.h" +#include "common.h" +#include "mpc.h" + +enum mpc_color_space_type { + COLOR_SPACE_RGB_TYPE, + COLOR_SPACE_RGB_LIMITED_8PBC_TYPE, + COLOR_SPACE_RGB_LIMITED_10PBC_TYPE, + COLOR_SPACE_YCBCR601_TYPE, + COLOR_SPACE_YCBCR709_TYPE, + COLOR_SPACE_YCBCR2020_TYPE, + COLOR_SPACE_YCBCR601_LIMITED_TYPE, + COLOR_SPACE_YCBCR709_LIMITED_TYPE, + // COLOR_SPACE_YCBCR709_BLACK_TYPE, +}; +struct out_csc_color_matrix_type { + enum mpc_color_space_type color_space_type; + uint16_t regval[12]; +}; + +static const struct out_csc_color_matrix_type output_csc_matrix[] = { + {COLOR_SPACE_RGB_TYPE, {0x2000, 0, 0, 0, 0, 0x2000, 0, 0, 0, 0, 0x2000, 0}}, + {COLOR_SPACE_RGB_LIMITED_8PBC_TYPE, + {0x1B7B, 0, 0, 0x202, 0, 0x1B7B, 0, 0x202, 0, 0, 0x1B7B, 0x202}}, + {COLOR_SPACE_RGB_LIMITED_10PBC_TYPE, + {0x1B66, 0, 0, 0x200, 0, 0x1B66, 0, 0x200, 0, 0, 0x1B66, 0x200}}, + {COLOR_SPACE_YCBCR601_TYPE, {0xE04, 0xF444, 0xFDB9, 0x1004, 0x831, 0x1016, 0x320, 0x201, 0xFB45, + 0xF6B7, 0xE04, 0x1004}}, + {COLOR_SPACE_YCBCR709_TYPE, {0xE04, 0xF345, 0xFEB7, 0x1004, 0x5D3, 0x1399, 0x1FA, 0x201, 0xFCCA, + 0xF533, 0xE04, 0x1004}}, + /* TODO: correct values below */ + {COLOR_SPACE_YCBCR601_LIMITED_TYPE, {0xE00, 0xF447, 0xFDB9, 0x1000, 0x991, 0x12C9, 0x3A6, 0x200, + 0xFB47, 0xF6B9, 0xE00, 0x1000}}, + {COLOR_SPACE_YCBCR709_LIMITED_TYPE, {0xE00, 0xF349, 0xFEB7, 0x1000, 0x6CE, 0x16E3, 0x24F, 0x200, + 0xFCCB, 0xF535, 0xE00, 0x1000}}, + {COLOR_SPACE_YCBCR2020_TYPE, {0x1000, 0xF149, 0xFEB7, 0x0000, 0x0868, 0x15B2, 0x01E6, 0x0000, + 0xFB88, 0xF478, 0x1000, 0x0000}}, +}; + +static bool is_rgb_full_type(enum color_space color_space) +{ + bool ret = false; + + if (color_space == COLOR_SPACE_SRGB || color_space == COLOR_SPACE_MSREF_SCRGB || + color_space == COLOR_SPACE_2020_RGB_FULLRANGE) + ret = true; + + return ret; +} + +static bool is_rgb_limited_type(enum color_space color_space) +{ + bool ret = false; + + if (color_space == COLOR_SPACE_SRGB_LIMITED || color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE) + ret = true; + + return ret; +} + +static bool is_ycbcr601_full_type(enum color_space color_space) +{ + bool ret = false; + + if (color_space == COLOR_SPACE_YCBCR601) + ret = true; + + return ret; +} + +static bool is_ycbcr601_limited_type(enum color_space color_space) +{ + bool ret = false; + + if (color_space == COLOR_SPACE_YCBCR601_LIMITED) + ret = true; + + return ret; +} + +static bool is_ycbcr709_full_type(enum color_space color_space) +{ + bool ret = false; + + if (color_space == COLOR_SPACE_YCBCR709) + ret = true; + + return ret; +} + +static bool is_ycbcr709_limited_type(enum color_space color_space) +{ + bool ret = false; + + if (color_space == COLOR_SPACE_YCBCR709_LIMITED) + ret = true; + + return ret; +} + +static bool is_ycbcr2020_type(enum color_space color_space) +{ + bool ret = false; + + if (color_space == COLOR_SPACE_2020_YCBCR) + ret = true; + + return ret; +} + +static enum mpc_color_space_type get_color_space_type( + enum color_space color_space, enum vpe_surface_pixel_format pixel_format) +{ + enum mpc_color_space_type type = COLOR_SPACE_RGB_TYPE; + + if (is_rgb_full_type(color_space)) + type = COLOR_SPACE_RGB_TYPE; + else if (is_rgb_limited_type(color_space)) + type = vpe_is_rgb8(pixel_format) ? COLOR_SPACE_RGB_LIMITED_8PBC_TYPE + : COLOR_SPACE_RGB_LIMITED_10PBC_TYPE; + else if (is_ycbcr601_full_type(color_space)) + type = COLOR_SPACE_YCBCR601_TYPE; + else if (is_ycbcr709_full_type(color_space)) + type = COLOR_SPACE_YCBCR709_TYPE; + else if (is_ycbcr601_limited_type(color_space)) + type = COLOR_SPACE_YCBCR601_LIMITED_TYPE; + else if (is_ycbcr709_limited_type(color_space)) + type = COLOR_SPACE_YCBCR709_LIMITED_TYPE; + else if (is_ycbcr2020_type(color_space)) + type = COLOR_SPACE_YCBCR2020_TYPE; + + return type; +} + +#define NUM_ELEMENTS(a) (sizeof(a) / sizeof((a)[0])) + +const uint16_t *vpe_find_color_matrix( + enum color_space color_space, enum vpe_surface_pixel_format pixel_format, uint32_t *array_size) +{ + int i; + enum mpc_color_space_type type; + const uint16_t *val = NULL; + int arr_size = NUM_ELEMENTS(output_csc_matrix); + + type = get_color_space_type(color_space, pixel_format); + for (i = 0; i < arr_size; i++) + if (output_csc_matrix[i].color_space_type == type) { + val = output_csc_matrix[i].regval; + *array_size = 12; + break; + } + + return val; +} diff --git a/src/amd/vpelib/src/core/plane_desc_writer.c b/src/amd/vpelib/src/core/plane_desc_writer.c new file mode 100644 index 00000000000..9eeb9b3fea1 --- /dev/null +++ b/src/amd/vpelib/src/core/plane_desc_writer.c @@ -0,0 +1,143 @@ +/* Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include "vpe_assert.h" +#include "vpe_command.h" +#include "plane_desc_writer.h" +#include "reg_helper.h" + +void plane_desc_writer_init(struct plane_desc_writer *writer, struct vpe_buf *buf, int32_t nps0, + int32_t npd0, int32_t nps1, int32_t npd1, int32_t subop) +{ + uint32_t *cmd_space; + uint64_t size = 4; + writer->status = VPE_STATUS_OK; + writer->base_cpu_va = buf->cpu_va; + writer->base_gpu_va = buf->gpu_va; + writer->buf = buf; + writer->num_src = 0; + writer->num_dst = 0; + + /* Buffer does not have enough space to write */ + if (buf->size < (int64_t)size) { + writer->status = VPE_STATUS_BUFFER_OVERFLOW; + return; + } + + cmd_space = (uint32_t *)(uintptr_t)writer->buf->cpu_va; + *cmd_space++ = VPE_PLANE_CFG_CMD_HEADER(subop, nps0, npd0, nps1, npd1); + + writer->buf->cpu_va += size; + writer->buf->gpu_va += size; + writer->buf->size -= size; +} + +/** fill the value to the embedded buffer. */ +void plane_desc_writer_add_source( + struct plane_desc_writer *writer, struct plane_desc_src *src, bool is_plane0) +{ + uint32_t *cmd_space, *cmd_start; + uint32_t num_wd = is_plane0 ? 6 : 5; + uint64_t size = num_wd * sizeof(uint32_t); + + if (writer->status != VPE_STATUS_OK) + return; + + /* Buffer does not have enough space to write */ + if (writer->buf->size < (int64_t)size) { + writer->status = VPE_STATUS_BUFFER_OVERFLOW; + return; + } + cmd_start = cmd_space = (uint32_t *)(uintptr_t)writer->buf->cpu_va; + + if (is_plane0) { + *cmd_space++ = VPEC_FIELD_VALUE(VPE_PLANE_CFG_TMZ, src->tmz) | + VPEC_FIELD_VALUE(VPE_PLANE_CFG_SWIZZLE_MODE, src->swizzle) | + VPEC_FIELD_VALUE(VPE_PLANE_CFG_ROTATION, src->rotation); + writer->num_src++; + } + + VPE_ASSERT(!(src->base_addr_lo & 0xFF)); + + *cmd_space++ = src->base_addr_lo; + *cmd_space++ = src->base_addr_hi; + + *cmd_space++ = + VPEC_FIELD_VALUE(VPE_PLANE_CFG_PITCH, src->pitch - 1); // 1-based number of element + *cmd_space++ = VPEC_FIELD_VALUE(VPE_PLANE_CFG_VIEWPORT_X, src->viewport_x) | + VPEC_FIELD_VALUE(VPE_PLANE_CFG_VIEWPORT_Y, src->viewport_y); + + *cmd_space++ = VPEC_FIELD_VALUE(VPE_PLANE_CFG_VIEWPORT_WIDTH, src->viewport_w - 1) | + VPEC_FIELD_VALUE(VPE_PLANE_CFG_VIEWPORT_HEIGHT, src->viewport_h - 1) | + VPEC_FIELD_VALUE(VPE_PLANE_CFG_VIEWPORT_ELEMENT_SIZE, src->elem_size); + + writer->buf->cpu_va += size; + writer->buf->gpu_va += size; + writer->buf->size -= size; +} + +/** fill the value to the embedded buffer. */ +void plane_desc_writer_add_destination( + struct plane_desc_writer *writer, struct plane_desc_dst *dst, bool is_plane0) +{ + uint32_t *cmd_space, *cmd_start; + uint32_t num_wd = is_plane0 ? 6 : 5; + uint64_t size = num_wd * sizeof(uint32_t); + + if (writer->status != VPE_STATUS_OK) + return; + + /* Buffer does not have enough space to write */ + if (writer->buf->size < (int64_t)size) { + writer->status = VPE_STATUS_BUFFER_OVERFLOW; + return; + } + + cmd_start = cmd_space = (uint32_t *)(uintptr_t)writer->buf->cpu_va; + + if (is_plane0) { + *cmd_space++ = VPEC_FIELD_VALUE(VPE_PLANE_CFG_TMZ, dst->tmz) | + VPEC_FIELD_VALUE(VPE_PLANE_CFG_SWIZZLE_MODE, dst->swizzle) | + VPEC_FIELD_VALUE(VPE_PLANE_CFG_MIRROR, dst->mirror); + writer->num_dst++; + } + + VPE_ASSERT(!(dst->base_addr_lo & 0xFF)); + + *cmd_space++ = dst->base_addr_lo; + *cmd_space++ = dst->base_addr_hi; + + *cmd_space++ = + VPEC_FIELD_VALUE(VPE_PLANE_CFG_PITCH, dst->pitch - 1); // 1-based number of element + *cmd_space++ = VPEC_FIELD_VALUE(VPE_PLANE_CFG_VIEWPORT_X, dst->viewport_x) | + VPEC_FIELD_VALUE(VPE_PLANE_CFG_VIEWPORT_Y, dst->viewport_y); + + *cmd_space++ = VPEC_FIELD_VALUE(VPE_PLANE_CFG_VIEWPORT_WIDTH, dst->viewport_w - 1) | + VPEC_FIELD_VALUE(VPE_PLANE_CFG_VIEWPORT_HEIGHT, dst->viewport_h - 1) | + VPEC_FIELD_VALUE(VPE_PLANE_CFG_VIEWPORT_ELEMENT_SIZE, dst->elem_size); + + writer->buf->cpu_va += size; + writer->buf->gpu_va += size; + writer->buf->size -= size; +} diff --git a/src/amd/vpelib/src/core/resource.c b/src/amd/vpelib/src/core/resource.c new file mode 100644 index 00000000000..ffaa2ee8519 --- /dev/null +++ b/src/amd/vpelib/src/core/resource.c @@ -0,0 +1,660 @@ +/* Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ +#include +#include "vpe_types.h" +#include "vpe_priv.h" +#include "vpe_version.h" +#include "common.h" + +#ifdef VPE_BUILD_1_0 +#include "vpe10_resource.h" +#endif + +static const struct vpe_debug_options debug_defaults = { + .flags = {0}, + .cm_in_bypass = 0, + .vpcnvc_bypass = 0, + .mpc_bypass = 0, + .identity_3dlut = 0, + .sce_3dlut = 0, + .disable_reuse_bit = 0, + .bg_bit_depth = 0, + .bypass_gamcor = 0, + .bypass_ogam = 0, + .bypass_dpp_gamut_remap = 0, + .bypass_post_csc = 0, + .bg_color_fill_only = 0, + .assert_when_not_support = 0, + .enable_mem_low_power = + { + .bits = + { + .cm = false, + .dscl = false, + .mpc = false, + }, + }, + .force_tf_calculation = 1, + .expansion_mode = 1, + .clamping_setting = 1, + .clamping_params = + { + .r_clamp_component_lower = 0x1000, + .g_clamp_component_lower = 0x1000, + .b_clamp_component_lower = 0x1000, + .r_clamp_component_upper = 0xEB00, + .g_clamp_component_upper = 0xEB00, + .b_clamp_component_upper = 0xEB00, + .clamping_range = 4, + }, + .bypass_per_pixel_alpha = 0, + .opp_pipe_crc_ctrl = 0, + .dpp_crc_ctrl = 0, + .mpc_crc_ctrl = 0, + .visual_confirm_params = {{{0}}}, +}; + +enum vpe_ip_level vpe_resource_parse_ip_version( + uint8_t mj, uint8_t mn, uint8_t rv) +{ + enum vpe_ip_level ip_level = VPE_IP_LEVEL_UNKNOWN; + switch (VPE_VERSION(mj, mn, rv)) { +#if VPE_BUILD_1_X +#if VPE_BUILD_1_0 + case VPE_VERSION(6, 1, 0): + ip_level = VPE_IP_LEVEL_1_0; +#endif + break; +#endif + default: + ip_level = VPE_IP_LEVEL_UNKNOWN; + break; + } + return ip_level; +} + +enum vpe_status vpe_construct_resource( + struct vpe_priv *vpe_priv, enum vpe_ip_level level, struct resource *res) +{ + enum vpe_status status = VPE_STATUS_OK; + switch (level) { +#ifdef VPE_BUILD_1_0 + case VPE_IP_LEVEL_1_0: + status = vpe10_construct_resource(vpe_priv, res); + break; +#endif + default: + status = VPE_STATUS_NOT_SUPPORTED; + vpe_log("invalid ip level: %d", (int)level); + break; + } + + vpe_priv->init.debug = debug_defaults; + vpe_priv->expansion_mode = vpe_priv->init.debug.expansion_mode; + if (res) + res->vpe_priv = vpe_priv; + + return status; +} + +void vpe_destroy_resource(struct vpe_priv *vpe_priv, struct resource *res) +{ + switch (vpe_priv->pub.level) { +#ifdef VPE_BUILD_1_0 + case VPE_IP_LEVEL_1_0: + vpe10_destroy_resource(vpe_priv, res); + break; +#endif + default: + break; + } +} + +struct segment_ctx *vpe_alloc_segment_ctx(struct vpe_priv *vpe_priv, uint16_t num_segments) +{ + struct segment_ctx *segment_ctx_base; + + segment_ctx_base = (struct segment_ctx *)vpe_zalloc(sizeof(struct segment_ctx) * num_segments); + + if (!segment_ctx_base) + return NULL; + + return segment_ctx_base; +} + +struct stream_ctx *vpe_alloc_stream_ctx(struct vpe_priv *vpe_priv, uint32_t num_streams) +{ + struct stream_ctx *ctx_base, *ctx; + uint32_t i; + + ctx_base = (struct stream_ctx *)vpe_zalloc(sizeof(struct stream_ctx) * num_streams); + if (!ctx_base) + return NULL; + + for (i = 0; i < num_streams; i++) { + ctx = &ctx_base[i]; + ctx->cs = COLOR_SPACE_UNKNOWN; + ctx->tf = TRANSFER_FUNC_UNKNOWN; + ctx->vpe_priv = vpe_priv; + vpe_color_set_adjustments_to_default(&ctx->color_adjustments); + ctx->tf_scaling_factor = vpe_fixpt_one; + } + + return ctx_base; +} + +void vpe_free_stream_ctx(struct vpe_priv *vpe_priv) +{ + uint16_t i; + struct stream_ctx *ctx; + + if (!vpe_priv->stream_ctx || !vpe_priv->num_streams) + return; + + for (i = 0; i < vpe_priv->num_streams; i++) { + ctx = &vpe_priv->stream_ctx[i]; + if (ctx->input_tf) { + vpe_free(ctx->input_tf); + ctx->input_tf = NULL; + } + + if (ctx->bias_scale) { + vpe_free(ctx->bias_scale); + ctx->bias_scale = NULL; + } + + if (ctx->input_cs) { + vpe_free(ctx->input_cs); + ctx->input_cs = NULL; + } + + if (ctx->gamut_remap) { + vpe_free(ctx->gamut_remap); + ctx->gamut_remap = NULL; + } + + if (ctx->in_shaper_func) { + vpe_free(ctx->in_shaper_func); + ctx->in_shaper_func = NULL; + } + + if (ctx->blend_tf) { + vpe_free(ctx->blend_tf); + ctx->blend_tf = NULL; + } + + if (ctx->lut3d_func) { + vpe_free(ctx->lut3d_func); + ctx->lut3d_func = NULL; + } + + if (ctx->segment_ctx) { + vpe_free(ctx->segment_ctx); + ctx->segment_ctx = NULL; + } + } + vpe_free(vpe_priv->stream_ctx); + vpe_priv->stream_ctx = NULL; + vpe_priv->num_streams = 0; +} + +void vpe_free_output_ctx(struct vpe_priv *vpe_priv) +{ + if (vpe_priv->output_ctx.gamut_remap) + vpe_free(vpe_priv->output_ctx.gamut_remap); + + if (vpe_priv->output_ctx.output_tf) + vpe_free(vpe_priv->output_ctx.output_tf); +} + +void vpe_pipe_reset(struct vpe_priv *vpe_priv) +{ + int i; + struct pipe_ctx *pipe_ctx; + + for (i = 0; i < vpe_priv->num_pipe; i++) { + pipe_ctx = &vpe_priv->pipe_ctx[i]; + pipe_ctx->is_top_pipe = true; + pipe_ctx->owner = PIPE_CTX_NO_OWNER; + pipe_ctx->top_pipe_idx = 0xff; + } +} + +void vpe_pipe_reclaim(struct vpe_priv *vpe_priv, struct vpe_cmd_info *cmd_info) +{ + int i, j; + struct pipe_ctx *pipe_ctx; + + for (i = 0; i < vpe_priv->num_pipe; i++) { + pipe_ctx = &vpe_priv->pipe_ctx[i]; + if (pipe_ctx->owner != PIPE_CTX_NO_OWNER) { + for (j = 0; j < cmd_info->num_inputs; j++) + if (pipe_ctx->owner == cmd_info->inputs[j].stream_idx) + break; + + if (j == cmd_info->num_inputs) { + // that stream no longer exists + pipe_ctx->is_top_pipe = true; + pipe_ctx->owner = PIPE_CTX_NO_OWNER; + pipe_ctx->top_pipe_idx = 0xff; + } + } + } +} + +struct pipe_ctx *vpe_pipe_find_owner(struct vpe_priv *vpe_priv, uint32_t stream_idx, bool *reuse) +{ + int i; + struct pipe_ctx *pipe_ctx; + struct pipe_ctx *free_pipe = NULL; + + for (i = 0; i < vpe_priv->num_pipe; i++) { + pipe_ctx = &vpe_priv->pipe_ctx[i]; + + if (!free_pipe && (pipe_ctx->owner == PIPE_CTX_NO_OWNER)) + free_pipe = pipe_ctx; + // re-use the same pipe + else if (pipe_ctx->owner == stream_idx) { + *reuse = true; + return pipe_ctx; + } + } + + if (free_pipe) { + free_pipe->owner = stream_idx; + } + *reuse = false; + return free_pipe; +} + +static void calculate_recout(struct segment_ctx *segment) +{ + struct stream_ctx *stream_ctx = segment->stream_ctx; + struct scaler_data *data = &segment->scaler_data; + struct vpe_rect *dst_rect; + int32_t split_count, split_idx; + + dst_rect = &stream_ctx->stream.scaling_info.dst_rect; + + split_count = stream_ctx->num_segments - 1; + split_idx = segment->segment_idx; + + // src & dst rect has been clipped earlier + data->recout.x = 0; + data->recout.y = 0; + data->recout.width = dst_rect->width; + data->recout.height = dst_rect->height; + + if (split_count) { + /* extra pixels in the division remainder need to go to pipes after + * the extra pixel index minus one(epimo) defined here as: + */ + int32_t epimo = split_count - (int32_t)data->recout.width % (split_count + 1); + + data->recout.x += ((int32_t)data->recout.width / (split_count + 1)) * split_idx; + if (split_idx > epimo) + data->recout.x += split_idx - epimo - 1; + + data->recout.width = + data->recout.width / (uint32_t)(split_count + 1) + (split_idx > epimo ? 1 : 0); + } +} + +void calculate_scaling_ratios(struct scaler_data *scl_data, struct vpe_rect *src_rect, + struct vpe_rect *dst_rect, enum vpe_surface_pixel_format format) +{ + // no rotation support + + scl_data->ratios.horz = vpe_fixpt_from_fraction(src_rect->width, dst_rect->width); + scl_data->ratios.vert = vpe_fixpt_from_fraction(src_rect->height, dst_rect->height); + scl_data->ratios.horz_c = scl_data->ratios.horz; + scl_data->ratios.vert_c = scl_data->ratios.vert; + + if (vpe_is_yuv420(format)) { + scl_data->ratios.horz_c.value /= 2; + scl_data->ratios.vert_c.value /= 2; + } + + scl_data->ratios.horz = vpe_fixpt_truncate(scl_data->ratios.horz, 19); + scl_data->ratios.vert = vpe_fixpt_truncate(scl_data->ratios.vert, 19); + scl_data->ratios.horz_c = vpe_fixpt_truncate(scl_data->ratios.horz_c, 19); + scl_data->ratios.vert_c = vpe_fixpt_truncate(scl_data->ratios.vert_c, 19); +} + +/* + * This is a preliminary vp size calculation to allow us to check taps support. + * The result is completely overridden afterwards. + */ +static void calculate_viewport_size(struct segment_ctx *segment_ctx) +{ + struct scaler_data *data = &segment_ctx->scaler_data; + + data->viewport.width = + (uint32_t)vpe_fixpt_ceil(vpe_fixpt_mul_int(data->ratios.horz, (int)data->recout.width)); + data->viewport.height = + (uint32_t)vpe_fixpt_ceil(vpe_fixpt_mul_int(data->ratios.vert, (int)data->recout.height)); + data->viewport_c.width = + (uint32_t)vpe_fixpt_ceil(vpe_fixpt_mul_int(data->ratios.horz_c, (int)data->recout.width)); + data->viewport_c.height = + (uint32_t)vpe_fixpt_ceil(vpe_fixpt_mul_int(data->ratios.vert_c, (int)data->recout.height)); +} + +/* + * We completely calculate vp offset, size and inits here based entirely on scaling + * ratios and recout for pixel perfect pipe combine. + */ +static void calculate_init_and_vp(bool flip_scan_dir, int32_t recout_offset, uint32_t recout_size, + uint32_t src_size, uint32_t taps, struct fixed31_32 ratio, struct fixed31_32 init_adj, + struct fixed31_32 *init, int32_t *vp_offset, uint32_t *vp_size) +{ + + struct fixed31_32 src_offset, temp; + int32_t int_part; + + /* + * First of the taps starts sampling pixel number corresponding to recout + * pixel 1. Next recout pixel samples int part of and so on. + * All following calculations are based on this logic. + */ + src_offset = vpe_fixpt_mul_int(ratio, recout_offset); + *vp_offset = vpe_fixpt_floor(src_offset); + + // calculate the phase + init->value = src_offset.value & 0xffffffff; // for phase accumulation + *init = vpe_fixpt_add(*init, init_adj); + int_part = vpe_fixpt_floor(vpe_fixpt_from_fraction(taps, 2)) + + 1; // middle point of the sampling window + *init = vpe_fixpt_add_int(*init, int_part); + *init = vpe_fixpt_truncate(*init, 19); + /* + * If there are more pixels on the left hand side (top for vertical scaling) of the + * sampling point which can be covered by the taps, init value needs go get increased + * to be able to buffer the pixels as much as taps. + */ + if (int_part < (int32_t)taps) { + int32_t left = (int32_t)taps - int_part; + if (left > *vp_offset) + left = *vp_offset; + *vp_offset -= left; + *init = vpe_fixpt_add_int(*init, left); + } + /* + * If taps are sampling outside of viewport at end of recout and there are more pixels + * available in the surface we should increase the viewport size, regardless set vp to + * only what is used. + */ + temp = vpe_fixpt_add(*init, vpe_fixpt_mul_int(ratio, (int)(recout_size - 1))); + *vp_size = (uint32_t)vpe_fixpt_floor(temp); + if ((uint32_t)((int32_t)*vp_size + *vp_offset) > src_size) + *vp_size = (uint32_t)((int32_t)src_size - *vp_offset); + /* We did all the math assuming we are scanning same direction as display does, + * however mirror/rotation changes how vp scans vs how it is offset. If scan direction + * is flipped we simply need to calculate offset from the other side of plane. + * Note that outside of viewport all scaling hardware works in recout space. + */ + if (flip_scan_dir) + *vp_offset = (int32_t)src_size - *vp_offset - (int32_t)*vp_size; +} + +static inline void get_vp_scan_direction(enum vpe_rotation_angle rotation, bool horizontal_mirror, + bool *orthogonal_rotation, bool *flip_vert_scan_dir, bool *flip_horz_scan_dir) +{ + *orthogonal_rotation = false; + *flip_vert_scan_dir = false; + *flip_horz_scan_dir = false; + if (rotation == VPE_ROTATION_ANGLE_180) { + *flip_vert_scan_dir = true; + *flip_horz_scan_dir = true; + } else if (rotation == VPE_ROTATION_ANGLE_90) { + *orthogonal_rotation = true; + *flip_horz_scan_dir = true; + } else if (rotation == VPE_ROTATION_ANGLE_270) { + *orthogonal_rotation = true; + *flip_vert_scan_dir = true; + } + + if (horizontal_mirror) + *flip_horz_scan_dir = !*flip_horz_scan_dir; +} + +static enum vpe_status calculate_inits_and_viewports(struct segment_ctx *segment_ctx) +{ + struct stream_ctx *stream_ctx = segment_ctx->stream_ctx; + struct vpe_surface_info *surface_info = &stream_ctx->stream.surface_info; + struct vpe_rect src_rect = stream_ctx->stream.scaling_info.src_rect; + struct vpe_rect *dst_rect = &stream_ctx->stream.scaling_info.dst_rect; + struct scaler_data *data = &segment_ctx->scaler_data; + uint32_t vpc_div = vpe_is_yuv420(data->format) ? 2 : 1; + bool orthogonal_rotation, flip_vert_scan_dir, flip_horz_scan_dir; + struct fixed31_32 init_adj_h = vpe_fixpt_zero; + struct fixed31_32 init_adj_v = vpe_fixpt_zero; + + get_vp_scan_direction(stream_ctx->stream.rotation, stream_ctx->stream.horizontal_mirror, + &orthogonal_rotation, &flip_vert_scan_dir, &flip_horz_scan_dir); + + if (orthogonal_rotation) { + swap(src_rect.width, src_rect.height); + swap(flip_vert_scan_dir, flip_horz_scan_dir); + } + + if (flip_horz_scan_dir) { + if (stream_ctx->flip_horizonal_output) + // flip at the output instead + flip_horz_scan_dir = false; + } + + if (vpe_is_yuv420(data->format)) { + int sign = -1; // this gives the direction of the cositing (negative will move left, right + // otherwise) + switch (surface_info->cs.cositing) { + + case VPE_CHROMA_COSITING_LEFT: + init_adj_h = vpe_fixpt_zero; + init_adj_v = vpe_fixpt_from_fraction(sign, 4); + break; + case VPE_CHROMA_COSITING_NONE: + init_adj_h = vpe_fixpt_from_fraction(sign, 4); + init_adj_v = vpe_fixpt_from_fraction(sign, 4); + break; + case VPE_CHROMA_COSITING_TOPLEFT: + default: + init_adj_h = vpe_fixpt_zero; + init_adj_v = vpe_fixpt_zero; + break; + } + } + + calculate_init_and_vp(flip_horz_scan_dir, data->recout.x, data->recout.width, src_rect.width, + data->taps.h_taps, data->ratios.horz, vpe_fixpt_zero, &data->inits.h, &data->viewport.x, + &data->viewport.width); + calculate_init_and_vp(flip_horz_scan_dir, data->recout.x, data->recout.width, + src_rect.width / vpc_div, data->taps.h_taps_c, data->ratios.horz_c, init_adj_h, + &data->inits.h_c, &data->viewport_c.x, &data->viewport_c.width); + calculate_init_and_vp(flip_vert_scan_dir, data->recout.y, data->recout.height, src_rect.height, + data->taps.v_taps, data->ratios.vert, vpe_fixpt_zero, &data->inits.v, &data->viewport.y, + &data->viewport.height); + calculate_init_and_vp(flip_vert_scan_dir, data->recout.y, data->recout.height, + src_rect.height / vpc_div, data->taps.v_taps_c, data->ratios.vert_c, init_adj_v, + &data->inits.v_c, &data->viewport_c.y, &data->viewport_c.height); + + // convert to absolute address + data->viewport.x += src_rect.x; + data->viewport.y += src_rect.y; + data->viewport_c.x += src_rect.x / (int32_t)vpc_div; + data->viewport_c.y += src_rect.y / (int32_t)vpc_div; + + return VPE_STATUS_OK; +} + +uint16_t vpe_get_num_segments(struct vpe_priv *vpe_priv, const struct vpe_rect *src, + const struct vpe_rect *dst, const uint32_t max_seg_width) +{ + int num_seg_src = (int)(ceil((double)src->width / max_seg_width)); + int num_seg_dst = (int)(ceil((double)dst->width / max_seg_width)); + return (uint16_t)(max(max(num_seg_src, num_seg_dst), 1)); +} + +void vpe_clip_stream( + struct vpe_rect *src_rect, struct vpe_rect *dst_rect, const struct vpe_rect *target_rect) +{ + struct fixed31_32 scaling_ratio_h; + struct fixed31_32 scaling_ratio_v; + + struct vpe_rect clipped_dst_rect, clipped_src_rect; + uint32_t clipped_pixels; + + clipped_dst_rect = *dst_rect; + clipped_src_rect = *src_rect; + + scaling_ratio_h = vpe_fixpt_from_fraction(src_rect->width, dst_rect->width); + scaling_ratio_v = vpe_fixpt_from_fraction(src_rect->height, dst_rect->height); + + if (dst_rect->x < target_rect->x) { + clipped_pixels = (uint32_t)(target_rect->x - dst_rect->x); + clipped_dst_rect.x = target_rect->x; + clipped_dst_rect.width -= clipped_pixels; + clipped_pixels = (uint32_t)vpe_fixpt_round( + vpe_fixpt_mul_int(scaling_ratio_h, (int)(target_rect->x - dst_rect->x))); + clipped_src_rect.x += (int32_t)clipped_pixels; + clipped_src_rect.width -= clipped_pixels; + } + if (dst_rect->y < target_rect->y) { + clipped_pixels = (uint32_t)(target_rect->y - dst_rect->y); + clipped_dst_rect.y = target_rect->y; + clipped_dst_rect.height -= clipped_pixels; + clipped_pixels = (uint32_t)vpe_fixpt_round( + vpe_fixpt_mul_int(scaling_ratio_v, (int)(target_rect->y - dst_rect->y))); + clipped_src_rect.y += (int32_t)clipped_pixels; + clipped_src_rect.height -= clipped_pixels; + } + if (dst_rect->x + (int32_t)dst_rect->width > target_rect->x + (int32_t)target_rect->width) { + clipped_dst_rect.width = + (uint32_t)(target_rect->x + (int32_t)target_rect->width - clipped_dst_rect.x); + clipped_src_rect.width = (uint32_t)vpe_fixpt_round( + vpe_fixpt_mul_int(scaling_ratio_h, (int)clipped_dst_rect.width)); + } + if (dst_rect->y + (int32_t)dst_rect->height > target_rect->y + (int32_t)target_rect->height) { + clipped_dst_rect.height = + (uint32_t)(target_rect->y + (int32_t)target_rect->height - clipped_dst_rect.y); + clipped_src_rect.height = (uint32_t)vpe_fixpt_round( + vpe_fixpt_mul_int(scaling_ratio_v, (int)clipped_dst_rect.height)); + } + + *src_rect = clipped_src_rect; + *dst_rect = clipped_dst_rect; +} + +enum vpe_status vpe_resource_build_scaling_params(struct segment_ctx *segment_ctx) +{ + struct stream_ctx *stream_ctx = segment_ctx->stream_ctx; + struct scaler_data *scl_data = &segment_ctx->scaler_data; + struct dpp *dpp = stream_ctx->vpe_priv->resource.dpp[0]; + + scl_data->format = stream_ctx->stream.surface_info.format; + scl_data->lb_params.alpha_en = stream_ctx->per_pixel_alpha; + + // h/v active will be set later + + /* recout.x is temporary for viewport calculation, + * will be finalized in calculate_dst_viewport_and_active() + */ + + calculate_recout(segment_ctx); + calculate_viewport_size(segment_ctx); + + if (scl_data->viewport.height < 1 || scl_data->viewport.width < 1) + return VPE_STATUS_VIEWPORT_SIZE_NOT_SUPPORTED; + + if (!dpp->funcs->validate_number_of_taps(dpp, scl_data)) { + return VPE_STATUS_SCALING_RATIO_NOT_SUPPORTED; + } + + calculate_inits_and_viewports(segment_ctx); + + if (scl_data->viewport.height < VPE_MIN_VIEWPORT_SIZE || + scl_data->viewport.width < VPE_MIN_VIEWPORT_SIZE) + return VPE_STATUS_VIEWPORT_SIZE_NOT_SUPPORTED; + + return VPE_STATUS_OK; +} + +void vpe_handle_output_h_mirror(struct vpe_priv *vpe_priv) +{ + uint16_t stream_idx; + int seg_idx; + struct stream_ctx *stream_ctx; + + // swap the stream output location + for (stream_idx = 0; stream_idx < vpe_priv->num_streams; stream_idx++) { + stream_ctx = &vpe_priv->stream_ctx[stream_idx]; + if (stream_ctx->flip_horizonal_output) { + struct segment_ctx *first_seg, *last_seg; + + // swap the segment output order, init the last segment first + first_seg = &stream_ctx->segment_ctx[0]; + last_seg = &stream_ctx->segment_ctx[stream_ctx->num_segments - 1]; + + // last segment becomes first + last_seg->scaler_data.dst_viewport.x = first_seg->scaler_data.dst_viewport.x; + + for (seg_idx = (int)(stream_ctx->num_segments - 2); seg_idx >= 0; seg_idx--) { + struct segment_ctx *prev_seg, *curr_seg; + + // set the x in reverse order + prev_seg = &stream_ctx->segment_ctx[seg_idx + 1]; + curr_seg = &stream_ctx->segment_ctx[seg_idx]; + + curr_seg->scaler_data.dst_viewport.x = + prev_seg->scaler_data.dst_viewport.x + + (int32_t)prev_seg->scaler_data.dst_viewport.width; + + curr_seg->scaler_data.dst_viewport_c.x = + prev_seg->scaler_data.dst_viewport_c.x + + (int32_t)prev_seg->scaler_data.dst_viewport_c.width; + } + } + } +} + +void vpe_resource_build_bit_depth_reduction_params( + struct opp *opp, struct bit_depth_reduction_params *fmt_bit_depth) +{ + struct vpe_priv *vpe_priv = opp->vpe_priv; + struct vpe_surface_info *dst_surface = &vpe_priv->output_ctx.surface; + enum color_depth display_color_depth; + memset(fmt_bit_depth, 0, sizeof(*fmt_bit_depth)); + + display_color_depth = vpe_get_color_depth(dst_surface->format); + + switch (display_color_depth) { + case COLOR_DEPTH_888: + case COLOR_DEPTH_101010: + fmt_bit_depth->flags.TRUNCATE_ENABLED = 1; + fmt_bit_depth->flags.TRUNCATE_DEPTH = (display_color_depth == COLOR_DEPTH_888) ? 1 : 2; + fmt_bit_depth->flags.TRUNCATE_MODE = 1; + break; + default: + break; + } +} diff --git a/src/amd/vpelib/src/core/shaper_builder.c b/src/amd/vpelib/src/core/shaper_builder.c new file mode 100644 index 00000000000..638f1bee5b6 --- /dev/null +++ b/src/amd/vpelib/src/core/shaper_builder.c @@ -0,0 +1,272 @@ +/* Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include "shaper_builder.h" +#include "custom_fp16.h" +#include "fixed31_32.h" + +struct x_axis_config { + int offset; + int segments_num; +}; + +struct point_config { + int custom_float_x; + int custom_float_y; + int custom_float_slope; +}; + +struct curve_points32 { + struct point_config red; + struct point_config green; + struct point_config blue; +}; + +struct lut_point { + int red; + int green; + int blue; + int delta_red; + int delta_green; + int delta_blue; +}; + +struct pwl_parameter2 { + struct x_axis_config arr_curve_points[34]; + struct curve_points32 corner_points[2]; + struct lut_point rgb_resulted[256]; + int hw_points_num; +}; + +struct shaper_setup_out { + int exp_begin_raw; + int exp_end_raw; + int begin_custom_1_6_12; + int end_custom_0_6_10; + int end_base_fixed_0_14; +}; + +static bool calculate_shaper_properties_const_hdr_mult( + const struct vpe_shaper_setup_in *shaper_in, struct shaper_setup_out *shaper_out) +{ + double x; + struct vpe_custom_float_format2 fmt; + struct vpe_custom_float_value2 custom_float; + int num_exp; + + bool ret = false; + int isize = 1 << 14; + double divider = isize - 1; + double x_double_begin; + + double multiplyer = shaper_in->source_luminance / 10000.0 * shaper_in->shaper_in_max; + + fmt.flags.Uint = 0; + fmt.flags.bits.sign = 1; + fmt.mantissaBits = 12; + fmt.exponentaBits = 6; + + x = pow(1.0 / divider, 2.2) * multiplyer; + if (!vpe_convert_to_custom_float_ex_generic(x, &fmt, &custom_float)) + goto release; + shaper_out->exp_begin_raw = custom_float.exponenta; + + if (!vpe_from_1_6_12_to_double(false, custom_float.exponenta, 0, &x_double_begin)) + goto release; + + if (!vpe_convert_to_custom_float_generic( + x_double_begin, &fmt, &shaper_out->begin_custom_1_6_12)) + goto release; + + fmt.flags.bits.sign = 0; + fmt.mantissaBits = 10; + if (!vpe_convert_to_custom_float_ex_generic(multiplyer, &fmt, &custom_float)) + goto release; + shaper_out->exp_end_raw = custom_float.exponenta; + if (!vpe_convert_to_custom_float_generic(multiplyer, &fmt, &shaper_out->end_custom_0_6_10)) + goto release; + shaper_out->end_base_fixed_0_14 = isize - 1; + num_exp = shaper_out->exp_end_raw - shaper_out->exp_begin_raw + 1; + if (num_exp > 34) + goto release; + ret = true; +release: + return ret; +} + +static bool calculate_shaper_properties_variable_hdr_mult( + const struct vpe_shaper_setup_in *shaper_in, struct shaper_setup_out *shaper_out) +{ + struct vpe_custom_float_format2 fmt; + struct vpe_custom_float_value2 custom_float; + int num_exp; + + bool ret = false; + int isize = 1 << 14; + double divider = isize - 1; + double x_double_begin = 0; + + fmt.flags.Uint = 0; + fmt.exponentaBits = 6; + fmt.mantissaBits = 10; + if (!vpe_convert_to_custom_float_ex_generic(shaper_in->shaper_in_max, &fmt, &custom_float)) + goto release; + + if (!vpe_convert_to_custom_float_generic( + shaper_in->shaper_in_max, &fmt, &shaper_out->end_custom_0_6_10)) + goto release; + + shaper_out->exp_end_raw = custom_float.exponenta; + shaper_out->exp_begin_raw = shaper_out->exp_end_raw - 33; + + shaper_out->end_base_fixed_0_14 = isize - 1; + + if (!vpe_from_1_6_12_to_double(false, shaper_out->exp_begin_raw, 0, &x_double_begin)) + goto release; + + fmt.mantissaBits = 12; + fmt.flags.bits.sign = 1; + + if (!vpe_convert_to_custom_float_generic( + x_double_begin, &fmt, &shaper_out->begin_custom_1_6_12)) + goto release; + + num_exp = shaper_out->exp_end_raw - shaper_out->exp_begin_raw + 1; + if (num_exp > 34) + goto release; + ret = true; +release: + return ret; +} + +static int build_shaper_2_2_segments_distribution(int num_regions, int *arr_segments) +{ + int i; + int counter; + int num_segments = 0; + int num_segments_total = 0; + const int proposed_2_2_distribution[] = {5, 5, 5, 5, 4, 4, 4, 4, 4, 3, 3, 2, 2, 1, 1, 1, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; + int proposed_regions = ARRAY_SIZE(proposed_2_2_distribution); + + if (proposed_regions < num_regions) + goto release; + counter = 0; + + for (i = num_regions - 1; i >= 0; i--) { + arr_segments[counter] = proposed_2_2_distribution[i]; + num_segments += 1 << proposed_2_2_distribution[i]; + counter++; + } +release: + return num_segments; +} + +enum vpe_status vpe_build_shaper( + const struct vpe_shaper_setup_in *shaper_in, struct pwl_params *shaper) +{ + enum vpe_status ret = VPE_STATUS_ERROR; + + int num_points = 0; + int arr_regions[34]; + struct shaper_setup_out shaper_params; + int i, j; + int num_exp; + + unsigned int exp; + double x, delta_segments; + int lut_counter = 0; + int segments_current; + int segments_offset; + + unsigned int decimalBits = 14; + + unsigned int mask = (1 << decimalBits) - 1; + double d_norm = mask; + double divider = shaper_in->shaper_in_max; + + if (shaper_in->use_const_hdr_mult && + !calculate_shaper_properties_const_hdr_mult(shaper_in, &shaper_params)) + goto release; + else if (!calculate_shaper_properties_variable_hdr_mult(shaper_in, &shaper_params)) + goto release; + + exp = shaper_params.exp_begin_raw; + + num_exp = shaper_params.exp_end_raw - shaper_params.exp_begin_raw + 1; + num_points = build_shaper_2_2_segments_distribution(num_exp, arr_regions); + + segments_offset = 0; + + for (i = 0; i < num_exp; i++) { + segments_current = 1 << arr_regions[i]; + shaper->arr_curve_points[i].segments_num = arr_regions[i]; + shaper->arr_curve_points[i].offset = segments_offset; + segments_offset = segments_offset + segments_current; + if (!vpe_from_1_6_12_to_double(false, exp, 0, &x)) + goto release; + x /= divider; + shaper->rgb_resulted[lut_counter].red_reg = + vpe_to_fixed_point(decimalBits, x, mask, d_norm); + shaper->rgb_resulted[lut_counter].green_reg = shaper->rgb_resulted[lut_counter].red_reg; + shaper->rgb_resulted[lut_counter].blue_reg = shaper->rgb_resulted[lut_counter].red_reg; + + delta_segments = x / segments_current; + lut_counter++; + for (j = 0; j < segments_current - 1; j++) { + x += delta_segments; + shaper->rgb_resulted[lut_counter].red_reg = + vpe_to_fixed_point(decimalBits, x, mask, d_norm); + shaper->rgb_resulted[lut_counter].green_reg = shaper->rgb_resulted[lut_counter].red_reg; + shaper->rgb_resulted[lut_counter].blue_reg = shaper->rgb_resulted[lut_counter].red_reg; + lut_counter++; + } + exp++; + } + + shaper->corner_points[0].red.custom_float_x = shaper_params.begin_custom_1_6_12; + shaper->corner_points[0].green.custom_float_x = shaper->corner_points[0].red.custom_float_x; + shaper->corner_points[0].blue.custom_float_x = shaper->corner_points[0].red.custom_float_x; + + shaper->corner_points[1].red.custom_float_x = shaper_params.end_custom_0_6_10; + shaper->corner_points[1].green.custom_float_x = shaper->corner_points[1].red.custom_float_x; + shaper->corner_points[1].blue.custom_float_x = shaper->corner_points[1].red.custom_float_x; + + shaper->corner_points[1].red.custom_float_y = shaper_params.end_base_fixed_0_14; + shaper->corner_points[1].green.custom_float_y = shaper->corner_points[1].red.custom_float_y; + shaper->corner_points[1].blue.custom_float_y = shaper->corner_points[1].red.custom_float_y; + + for (i = 1; i < num_points; i++) { + shaper->rgb_resulted[i - 1].delta_red_reg = + shaper->rgb_resulted[i].red_reg - shaper->rgb_resulted[i - 1].red_reg; + shaper->rgb_resulted[i - 1].delta_green_reg = shaper->rgb_resulted[i - 1].delta_red_reg; + shaper->rgb_resulted[i - 1].delta_blue_reg = shaper->rgb_resulted[i - 1].delta_red_reg; + } + + shaper->hw_points_num = num_points; + ret = VPE_STATUS_OK; + +release: + return ret; +} diff --git a/src/amd/vpelib/src/core/vpe_desc_writer.c b/src/amd/vpelib/src/core/vpe_desc_writer.c new file mode 100644 index 00000000000..d3690cc7c4a --- /dev/null +++ b/src/amd/vpelib/src/core/vpe_desc_writer.c @@ -0,0 +1,129 @@ +/* Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include "vpe_assert.h" +#include "common.h" +#include "reg_helper.h" +#include "vpe_desc_writer.h" +#include "vpe_command.h" + +void vpe_desc_writer_init(struct vpe_desc_writer *writer, struct vpe_buf *buf, int cd) +{ + uint32_t *cmd_space; + uint64_t size = sizeof(uint32_t); + + writer->base_cpu_va = buf->cpu_va; + writer->base_gpu_va = buf->gpu_va; + writer->buf = buf; + writer->num_config_desc = 0; + writer->plane_desc_added = false; + writer->status = VPE_STATUS_OK; + + if (buf->size < (int64_t)size) { + writer->status = VPE_STATUS_BUFFER_OVERFLOW; + return; + } + cmd_space = (uint32_t *)(uintptr_t)writer->buf->cpu_va; + *cmd_space++ = VPE_DESC_CMD_HEADER(cd); + + writer->buf->cpu_va += size; + writer->buf->gpu_va += size; + writer->buf->size -= size; +} + +/** fill the value to the command buffer. */ +void vpe_desc_writer_add_plane_desc( + struct vpe_desc_writer *writer, uint64_t plane_desc_addr, bool tmz) +{ + uint32_t *cmd_space; + uint64_t size = 3 * sizeof(uint32_t); + + if (writer->status != VPE_STATUS_OK) + return; + + /* Buffer does not have enough space to write */ + if (writer->buf->size < (int64_t)size) { + writer->status = VPE_STATUS_BUFFER_OVERFLOW; + return; + } + + cmd_space = (uint32_t *)(uintptr_t)writer->buf->cpu_va; + + VPE_ASSERT(!(plane_desc_addr & 0x3)); + VPE_ASSERT(!writer->plane_desc_added); + + *cmd_space++ = (ADDR_LO(plane_desc_addr) | (unsigned)tmz); + *cmd_space++ = ADDR_HI(plane_desc_addr); + + // skip the DW3 as well, which is finalized during complete + + writer->buf->cpu_va += size; + writer->buf->gpu_va += size; + writer->buf->size -= size; + writer->plane_desc_added = true; +} + +/** fill the value to the command buffer. */ +void vpe_desc_writer_add_config_desc( + struct vpe_desc_writer *writer, uint64_t config_desc_addr, bool reuse, bool tmz) +{ + uint32_t *cmd_space; + uint64_t size = 2 * sizeof(uint32_t); + + if (writer->status != VPE_STATUS_OK) + return; + + /* Buffer does not have enough space to write */ + if (writer->buf->size < (int64_t)size) { + writer->status = VPE_STATUS_BUFFER_OVERFLOW; + return; + } + + cmd_space = (uint32_t *)(uintptr_t)writer->buf->cpu_va; + + VPE_ASSERT(!(config_desc_addr & 0x3)); + + *cmd_space++ = (ADDR_LO(config_desc_addr) | ((unsigned)reuse << 1) | (unsigned)tmz); + *cmd_space++ = ADDR_HI(config_desc_addr); + + writer->buf->cpu_va += size; + writer->buf->gpu_va += size; + writer->buf->size -= size; + writer->num_config_desc++; +} + +void vpe_desc_writer_complete(struct vpe_desc_writer *writer) +{ + uint32_t *cmd_space; + if (writer->status != VPE_STATUS_OK) + return; + + // NUM_CONFIG_DESCRIPTOR is at DW3 + cmd_space = (uint32_t *)(uintptr_t)(writer->base_cpu_va + 3 * sizeof(uint32_t)); + + VPE_ASSERT(!(writer->num_config_desc & 0xFFFFFF00)); + VPE_ASSERT(writer->num_config_desc > 0); + // NUM_CONFIG_DESCRIPTOR is 1-based + *cmd_space = (writer->num_config_desc - 1) & 0xFF; +} diff --git a/src/amd/vpelib/src/core/vpe_scl_filters.c b/src/amd/vpelib/src/core/vpe_scl_filters.c new file mode 100644 index 00000000000..e99c450a8b7 --- /dev/null +++ b/src/amd/vpelib/src/core/vpe_scl_filters.c @@ -0,0 +1,429 @@ +/* + * Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ +#include "transform.h" + +//========================================= +// = 2 +// = 64 +// = Bilinear +//========================================= +static const uint16_t filter_2tap_bilinear_64p[66] = {0x1000, 0x0000, 0x0fc0, 0x0040, 0x0f80, + 0x0080, 0x0f40, 0x00c0, 0x0f00, 0x0100, 0x0ec0, 0x0140, 0x0e80, 0x0180, 0x0e40, 0x01c0, 0x0e00, + 0x0200, 0x0dc0, 0x0240, 0x0d80, 0x0280, 0x0d40, 0x02c0, 0x0d00, 0x0300, 0x0cc0, 0x0340, 0x0c80, + 0x0380, 0x0c40, 0x03c0, 0x0c00, 0x0400, 0x0bc0, 0x0440, 0x0b80, 0x0480, 0x0b40, 0x04c0, 0x0b00, + 0x0500, 0x0ac0, 0x0540, 0x0a80, 0x0580, 0x0a40, 0x05c0, 0x0a00, 0x0600, 0x09c0, 0x0640, 0x0980, + 0x0680, 0x0940, 0x06c0, 0x0900, 0x0700, 0x08c0, 0x0740, 0x0880, 0x0780, 0x0840, 0x07c0, 0x0800, + 0x0800}; + +//========================================= +// = 2 +// = 64 +// = 0.833333 (input/output) +// = 0 +// = ModifiedLanczos +// = s1.10 +// = s1.12 +//========================================= +static const uint16_t filter_2tap_64p[66] = {0x1000, 0x0000, 0x1000, 0x0000, 0x0FFC, 0x0004, 0x0FF8, + 0x0008, 0x0FF0, 0x0010, 0x0FE4, 0x001C, 0x0FD8, 0x0028, 0x0FC4, 0x003C, 0x0FB0, 0x0050, 0x0F98, + 0x0068, 0x0F7C, 0x0084, 0x0F58, 0x00A8, 0x0F34, 0x00CC, 0x0F08, 0x00F8, 0x0ED8, 0x0128, 0x0EA4, + 0x015C, 0x0E68, 0x0198, 0x0E28, 0x01D8, 0x0DE4, 0x021C, 0x0D98, 0x0268, 0x0D44, 0x02BC, 0x0CEC, + 0x0314, 0x0C90, 0x0370, 0x0C2C, 0x03D4, 0x0BC4, 0x043C, 0x0B58, 0x04A8, 0x0AE8, 0x0518, 0x0A74, + 0x058C, 0x09FC, 0x0604, 0x0980, 0x0680, 0x0900, 0x0700, 0x0880, 0x0780, 0x0800, 0x0800}; + +//========================================= +// = 4 +// = 64 +// = 0.83333 (input/output) +// = 0 +// = ModifiedLanczos +// = 1.10 +// = 1.12 +//========================================= +static const uint16_t filter_4tap_64p_upscale[132] = {0x0000, 0x1000, 0x0000, 0x0000, 0x3FDC, + 0x0FFC, 0x0028, 0x0000, 0x3FB4, 0x0FF8, 0x0054, 0x0000, 0x3F94, 0x0FE8, 0x0084, 0x0000, 0x3F74, + 0x0FDC, 0x00B4, 0x3FFC, 0x3F58, 0x0FC4, 0x00E8, 0x3FFC, 0x3F3C, 0x0FAC, 0x0120, 0x3FF8, 0x3F24, + 0x0F90, 0x0158, 0x3FF4, 0x3F0C, 0x0F70, 0x0194, 0x3FF0, 0x3EF8, 0x0F4C, 0x01D0, 0x3FEC, 0x3EE8, + 0x0F20, 0x0210, 0x3FE8, 0x3ED8, 0x0EF4, 0x0254, 0x3FE0, 0x3ECC, 0x0EC4, 0x0298, 0x3FD8, 0x3EC0, + 0x0E90, 0x02DC, 0x3FD4, 0x3EB8, 0x0E58, 0x0324, 0x3FCC, 0x3EB0, 0x0E20, 0x036C, 0x3FC4, 0x3EAC, + 0x0DE4, 0x03B8, 0x3FB8, 0x3EA8, 0x0DA4, 0x0404, 0x3FB0, 0x3EA4, 0x0D60, 0x0454, 0x3FA8, 0x3EA4, + 0x0D1C, 0x04A4, 0x3F9C, 0x3EA4, 0x0CD8, 0x04F4, 0x3F90, 0x3EA8, 0x0C88, 0x0548, 0x3F88, 0x3EAC, + 0x0C3C, 0x059C, 0x3F7C, 0x3EB0, 0x0BF0, 0x05F0, 0x3F70, 0x3EB8, 0x0BA0, 0x0644, 0x3F64, 0x3EBC, + 0x0B54, 0x0698, 0x3F58, 0x3EC4, 0x0B00, 0x06F0, 0x3F4C, 0x3ECC, 0x0AAC, 0x0748, 0x3F40, 0x3ED8, + 0x0A54, 0x07A0, 0x3F34, 0x3EE0, 0x0A04, 0x07F8, 0x3F24, 0x3EEC, 0x09AC, 0x0850, 0x3F18, 0x3EF8, + 0x0954, 0x08A8, 0x3F0C, 0x3F00, 0x08FC, 0x0900, 0x3F04}; + +//========================================= +// = 4 +// = 64 +// = 1.16666 (input/output) +// = 0 +// = ModifiedLanczos +// = 1.10 +// = 1.12 +//========================================= +static const uint16_t filter_4tap_64p_116[132] = {0x01A8, 0x0CB4, 0x01A4, 0x0000, 0x017C, 0x0CB8, + 0x01D0, 0x3FFC, 0x0158, 0x0CB8, 0x01F8, 0x3FF8, 0x0130, 0x0CB4, 0x0228, 0x3FF4, 0x0110, 0x0CB0, + 0x0254, 0x3FEC, 0x00EC, 0x0CA8, 0x0284, 0x3FE8, 0x00CC, 0x0C9C, 0x02B4, 0x3FE4, 0x00AC, 0x0C90, + 0x02E8, 0x3FDC, 0x0090, 0x0C80, 0x031C, 0x3FD4, 0x0070, 0x0C70, 0x0350, 0x3FD0, 0x0058, 0x0C5C, + 0x0384, 0x3FC8, 0x003C, 0x0C48, 0x03BC, 0x3FC0, 0x0024, 0x0C2C, 0x03F4, 0x3FBC, 0x0010, 0x0C10, + 0x042C, 0x3FB4, 0x3FFC, 0x0BF4, 0x0464, 0x3FAC, 0x3FE8, 0x0BD4, 0x04A0, 0x3FA4, 0x3FD8, 0x0BAC, + 0x04DC, 0x3FA0, 0x3FC4, 0x0B8C, 0x0518, 0x3F98, 0x3FB4, 0x0B68, 0x0554, 0x3F90, 0x3FA8, 0x0B40, + 0x0590, 0x3F88, 0x3F9C, 0x0B14, 0x05CC, 0x3F84, 0x3F90, 0x0AEC, 0x0608, 0x3F7C, 0x3F84, 0x0ABC, + 0x0648, 0x3F78, 0x3F7C, 0x0A90, 0x0684, 0x3F70, 0x3F70, 0x0A60, 0x06C4, 0x3F6C, 0x3F6C, 0x0A2C, + 0x0700, 0x3F68, 0x3F64, 0x09F8, 0x0740, 0x3F64, 0x3F60, 0x09C4, 0x077C, 0x3F60, 0x3F5C, 0x098C, + 0x07BC, 0x3F5C, 0x3F58, 0x0958, 0x07F8, 0x3F58, 0x3F58, 0x091C, 0x0834, 0x3F58, 0x3F54, 0x08E4, + 0x0870, 0x3F58, 0x3F54, 0x08AC, 0x08AC, 0x3F54}; + +//========================================= +// = 4 +// = 64 +// = 1.49999 (input/output) +// = 0 +// = ModifiedLanczos +// = 1.10 +// = 1.12 +//========================================= +static const uint16_t filter_4tap_64p_149[132] = {0x02B8, 0x0A90, 0x02B8, 0x0000, 0x0294, 0x0A94, + 0x02DC, 0x3FFC, 0x0274, 0x0A94, 0x0300, 0x3FF8, 0x0250, 0x0A94, 0x0328, 0x3FF4, 0x0230, 0x0A90, + 0x0350, 0x3FF0, 0x0214, 0x0A8C, 0x0374, 0x3FEC, 0x01F0, 0x0A88, 0x03A0, 0x3FE8, 0x01D4, 0x0A80, + 0x03C8, 0x3FE4, 0x01B8, 0x0A78, 0x03F0, 0x3FE0, 0x0198, 0x0A70, 0x041C, 0x3FDC, 0x0180, 0x0A64, + 0x0444, 0x3FD8, 0x0164, 0x0A54, 0x0470, 0x3FD8, 0x0148, 0x0A48, 0x049C, 0x3FD4, 0x0130, 0x0A38, + 0x04C8, 0x3FD0, 0x0118, 0x0A24, 0x04F4, 0x3FD0, 0x0100, 0x0A14, 0x0520, 0x3FCC, 0x00E8, 0x0A00, + 0x054C, 0x3FCC, 0x00D4, 0x09E8, 0x057C, 0x3FC8, 0x00C0, 0x09D0, 0x05A8, 0x3FC8, 0x00AC, 0x09B8, + 0x05D4, 0x3FC8, 0x0098, 0x09A0, 0x0600, 0x3FC8, 0x0084, 0x0984, 0x0630, 0x3FC8, 0x0074, 0x0964, + 0x065C, 0x3FCC, 0x0064, 0x0948, 0x0688, 0x3FCC, 0x0054, 0x0928, 0x06B4, 0x3FD0, 0x0044, 0x0908, + 0x06E0, 0x3FD4, 0x0038, 0x08E8, 0x070C, 0x3FD4, 0x002C, 0x08C4, 0x0738, 0x3FD8, 0x001C, 0x08A4, + 0x0760, 0x3FE0, 0x0014, 0x087C, 0x078C, 0x3FE4, 0x0008, 0x0858, 0x07B4, 0x3FEC, 0x0000, 0x0830, + 0x07DC, 0x3FF4, 0x3FFC, 0x0804, 0x0804, 0x3FFC}; + +//========================================= +// = 4 +// = 64 +// = 1.83332 (input/output) +// = 0 +// = ModifiedLanczos +// = 1.10 +// = 1.12 +//========================================= +static const uint16_t filter_4tap_64p_183[132] = {0x03B0, 0x08A0, 0x03B0, 0x0000, 0x0394, 0x08A0, + 0x03CC, 0x0000, 0x037C, 0x089C, 0x03E8, 0x0000, 0x0360, 0x089C, 0x0400, 0x0004, 0x0348, 0x0898, + 0x041C, 0x0004, 0x032C, 0x0894, 0x0438, 0x0008, 0x0310, 0x0890, 0x0454, 0x000C, 0x02F8, 0x0888, + 0x0474, 0x000C, 0x02DC, 0x0884, 0x0490, 0x0010, 0x02C4, 0x087C, 0x04AC, 0x0014, 0x02AC, 0x0874, + 0x04C8, 0x0018, 0x0290, 0x086C, 0x04E4, 0x0020, 0x0278, 0x0864, 0x0500, 0x0024, 0x0264, 0x0858, + 0x051C, 0x0028, 0x024C, 0x084C, 0x0538, 0x0030, 0x0234, 0x0844, 0x0554, 0x0034, 0x021C, 0x0838, + 0x0570, 0x003C, 0x0208, 0x0828, 0x058C, 0x0044, 0x01F0, 0x081C, 0x05A8, 0x004C, 0x01DC, 0x080C, + 0x05C4, 0x0054, 0x01C8, 0x07FC, 0x05E0, 0x005C, 0x01B4, 0x07EC, 0x05FC, 0x0064, 0x019C, 0x07DC, + 0x0618, 0x0070, 0x018C, 0x07CC, 0x0630, 0x0078, 0x0178, 0x07B8, 0x064C, 0x0084, 0x0164, 0x07A8, + 0x0664, 0x0090, 0x0150, 0x0794, 0x0680, 0x009C, 0x0140, 0x0780, 0x0698, 0x00A8, 0x0130, 0x076C, + 0x06B0, 0x00B4, 0x0120, 0x0758, 0x06C8, 0x00C0, 0x0110, 0x0740, 0x06E0, 0x00D0, 0x0100, 0x072C, + 0x06F8, 0x00DC, 0x00F0, 0x0714, 0x0710, 0x00EC}; + +//========================================= +// = 6 +// = 64 +// = 0.83333 (input/output) +// = 0 +// = ModifiedLanczos +// = 1.10 +// = 1.12 +//========================================= +static const uint16_t filter_6tap_64p_upscale[198] = {0x0000, 0x0000, 0x1000, 0x0000, 0x0000, + 0x0000, 0x000C, 0x3FD0, 0x0FFC, 0x0034, 0x3FF4, 0x0000, 0x0018, 0x3F9C, 0x0FF8, 0x006C, 0x3FE8, + 0x0000, 0x0024, 0x3F6C, 0x0FF0, 0x00A8, 0x3FD8, 0x0000, 0x002C, 0x3F44, 0x0FE4, 0x00E4, 0x3FC8, + 0x0000, 0x0038, 0x3F18, 0x0FD4, 0x0124, 0x3FB8, 0x0000, 0x0040, 0x3EF0, 0x0FC0, 0x0164, 0x3FA8, + 0x0004, 0x0048, 0x3EC8, 0x0FAC, 0x01A8, 0x3F98, 0x0004, 0x0050, 0x3EA8, 0x0F94, 0x01EC, 0x3F84, + 0x0004, 0x0058, 0x3E84, 0x0F74, 0x0234, 0x3F74, 0x0008, 0x0060, 0x3E68, 0x0F54, 0x027C, 0x3F60, + 0x0008, 0x0064, 0x3E4C, 0x0F30, 0x02C8, 0x3F4C, 0x000C, 0x006C, 0x3E30, 0x0F04, 0x0314, 0x3F3C, + 0x0010, 0x0070, 0x3E18, 0x0EDC, 0x0360, 0x3F28, 0x0014, 0x0074, 0x3E04, 0x0EB0, 0x03B0, 0x3F14, + 0x0014, 0x0078, 0x3DF0, 0x0E80, 0x0400, 0x3F00, 0x0018, 0x0078, 0x3DE0, 0x0E4C, 0x0454, 0x3EEC, + 0x001C, 0x007C, 0x3DD0, 0x0E14, 0x04A8, 0x3ED8, 0x0020, 0x007C, 0x3DC4, 0x0DDC, 0x04FC, 0x3EC4, + 0x0024, 0x007C, 0x3DBC, 0x0DA0, 0x0550, 0x3EB0, 0x0028, 0x0080, 0x3DB4, 0x0D5C, 0x05A8, 0x3E9C, + 0x002C, 0x0080, 0x3DAC, 0x0D1C, 0x0600, 0x3E88, 0x0030, 0x007C, 0x3DA8, 0x0CDC, 0x0658, 0x3E74, + 0x0034, 0x007C, 0x3DA4, 0x0C94, 0x06B0, 0x3E64, 0x0038, 0x007C, 0x3DA4, 0x0C48, 0x0708, 0x3E50, + 0x0040, 0x0078, 0x3DA4, 0x0C00, 0x0760, 0x3E40, 0x0044, 0x0078, 0x3DA8, 0x0BB4, 0x07B8, 0x3E2C, + 0x0048, 0x0074, 0x3DAC, 0x0B68, 0x0810, 0x3E1C, 0x004C, 0x0070, 0x3DB4, 0x0B18, 0x0868, 0x3E0C, + 0x0050, 0x006C, 0x3DBC, 0x0AC4, 0x08C4, 0x3DFC, 0x0054, 0x0068, 0x3DC4, 0x0A74, 0x0918, 0x3DF0, + 0x0058, 0x0068, 0x3DCC, 0x0A20, 0x0970, 0x3DE0, 0x005C, 0x0064, 0x3DD4, 0x09C8, 0x09C8, 0x3DD4, + 0x0064}; + +//========================================= +// = 6 +// = 64 +// = 1.16666 (input/output) +// = 0 +// = ModifiedLanczos +// = 1.10 +// = 1.12 +//========================================= +static const uint16_t filter_6tap_64p_116[198] = {0x3F0C, 0x0240, 0x0D68, 0x0240, 0x3F0C, 0x0000, + 0x3F18, 0x0210, 0x0D64, 0x0274, 0x3F00, 0x0000, 0x3F24, 0x01E0, 0x0D58, 0x02A8, 0x3EF8, 0x0004, + 0x3F2C, 0x01B0, 0x0D58, 0x02DC, 0x3EEC, 0x0004, 0x3F38, 0x0180, 0x0D50, 0x0310, 0x3EE0, 0x0008, + 0x3F44, 0x0154, 0x0D40, 0x0348, 0x3ED8, 0x0008, 0x3F50, 0x0128, 0x0D34, 0x037C, 0x3ECC, 0x000C, + 0x3F5C, 0x00FC, 0x0D20, 0x03B4, 0x3EC4, 0x0010, 0x3F64, 0x00D4, 0x0D14, 0x03EC, 0x3EB8, 0x0010, + 0x3F70, 0x00AC, 0x0CFC, 0x0424, 0x3EB0, 0x0014, 0x3F78, 0x0084, 0x0CE8, 0x0460, 0x3EA8, 0x0014, + 0x3F84, 0x0060, 0x0CCC, 0x0498, 0x3EA0, 0x0018, 0x3F90, 0x003C, 0x0CB4, 0x04D0, 0x3E98, 0x0018, + 0x3F98, 0x0018, 0x0C9C, 0x050C, 0x3E90, 0x0018, 0x3FA0, 0x3FFC, 0x0C78, 0x0548, 0x3E88, 0x001C, + 0x3FAC, 0x3FDC, 0x0C54, 0x0584, 0x3E84, 0x001C, 0x3FB4, 0x3FBC, 0x0C3C, 0x05BC, 0x3E7C, 0x001C, + 0x3FBC, 0x3FA0, 0x0C14, 0x05F8, 0x3E78, 0x0020, 0x3FC4, 0x3F84, 0x0BF0, 0x0634, 0x3E74, 0x0020, + 0x3FCC, 0x3F68, 0x0BCC, 0x0670, 0x3E70, 0x0020, 0x3FD4, 0x3F50, 0x0BA4, 0x06AC, 0x3E6C, 0x0020, + 0x3FDC, 0x3F38, 0x0B78, 0x06E8, 0x3E6C, 0x0020, 0x3FE0, 0x3F24, 0x0B50, 0x0724, 0x3E68, 0x0020, + 0x3FE8, 0x3F0C, 0x0B24, 0x0760, 0x3E68, 0x0020, 0x3FF0, 0x3EFC, 0x0AF4, 0x0798, 0x3E68, 0x0020, + 0x3FF4, 0x3EE8, 0x0AC8, 0x07D4, 0x3E68, 0x0020, 0x3FFC, 0x3ED8, 0x0A94, 0x0810, 0x3E6C, 0x001C, + 0x0000, 0x3EC8, 0x0A64, 0x0848, 0x3E70, 0x001C, 0x0000, 0x3EB8, 0x0A38, 0x0880, 0x3E74, 0x001C, + 0x0004, 0x3EAC, 0x0A04, 0x08BC, 0x3E78, 0x0018, 0x0008, 0x3EA4, 0x09D0, 0x08F4, 0x3E7C, 0x0014, + 0x000C, 0x3E98, 0x0998, 0x092C, 0x3E84, 0x0014, 0x0010, 0x3E90, 0x0964, 0x0960, 0x3E8C, 0x0010}; + +//========================================= +// = 6 +// = 64 +// = 1.49999 (input/output) +// = 0 +// = ModifiedLanczos +// = 1.10 +// = 1.12 +//========================================= +static const uint16_t filter_6tap_64p_149[198] = {0x3F14, 0x0394, 0x0AB0, 0x0394, 0x3F14, 0x0000, + 0x3F18, 0x036C, 0x0AB0, 0x03B8, 0x3F14, 0x0000, 0x3F18, 0x0348, 0x0AAC, 0x03E0, 0x3F14, 0x0000, + 0x3F1C, 0x0320, 0x0AAC, 0x0408, 0x3F10, 0x0000, 0x3F20, 0x02FC, 0x0AA8, 0x042C, 0x3F10, 0x0000, + 0x3F24, 0x02D8, 0x0AA0, 0x0454, 0x3F10, 0x0000, 0x3F28, 0x02B4, 0x0A98, 0x047C, 0x3F10, 0x0000, + 0x3F28, 0x0290, 0x0A90, 0x04A4, 0x3F14, 0x0000, 0x3F30, 0x026C, 0x0A84, 0x04CC, 0x3F14, 0x0000, + 0x3F34, 0x024C, 0x0A7C, 0x04F4, 0x3F14, 0x3FFC, 0x3F38, 0x0228, 0x0A70, 0x051C, 0x3F18, 0x3FFC, + 0x3F3C, 0x0208, 0x0A64, 0x0544, 0x3F1C, 0x3FF8, 0x3F40, 0x01E8, 0x0A54, 0x056C, 0x3F20, 0x3FF8, + 0x3F44, 0x01C8, 0x0A48, 0x0594, 0x3F24, 0x3FF4, 0x3F4C, 0x01A8, 0x0A34, 0x05BC, 0x3F28, 0x3FF4, + 0x3F50, 0x0188, 0x0A28, 0x05E4, 0x3F2C, 0x3FF0, 0x3F54, 0x016C, 0x0A10, 0x060C, 0x3F34, 0x3FF0, + 0x3F5C, 0x014C, 0x09FC, 0x0634, 0x3F3C, 0x3FEC, 0x3F60, 0x0130, 0x09EC, 0x065C, 0x3F40, 0x3FE8, + 0x3F68, 0x0114, 0x09D0, 0x0684, 0x3F48, 0x3FE8, 0x3F6C, 0x00F8, 0x09B8, 0x06AC, 0x3F54, 0x3FE4, + 0x3F74, 0x00E0, 0x09A0, 0x06D0, 0x3F5C, 0x3FE0, 0x3F78, 0x00C4, 0x098C, 0x06F8, 0x3F64, 0x3FDC, + 0x3F7C, 0x00AC, 0x0970, 0x0720, 0x3F70, 0x3FD8, 0x3F84, 0x0094, 0x0954, 0x0744, 0x3F7C, 0x3FD4, + 0x3F88, 0x007C, 0x093C, 0x0768, 0x3F88, 0x3FD0, 0x3F90, 0x0064, 0x091C, 0x0790, 0x3F94, 0x3FCC, + 0x3F94, 0x0050, 0x08FC, 0x07B4, 0x3FA4, 0x3FC8, 0x3F98, 0x003C, 0x08E0, 0x07D8, 0x3FB0, 0x3FC4, + 0x3FA0, 0x0024, 0x08C0, 0x07FC, 0x3FC0, 0x3FC0, 0x3FA4, 0x0014, 0x08A4, 0x081C, 0x3FD0, 0x3FB8, + 0x3FAC, 0x0000, 0x0880, 0x0840, 0x3FE0, 0x3FB4, 0x3FB0, 0x3FF0, 0x0860, 0x0860, 0x3FF0, 0x3FB0}; + +//========================================= +// = 6 +// = 64 +// = 1.83332 (input/output) +// = 0 +// = ModifiedLanczos +// = 1.10 +// = 1.12 +//========================================= +static const uint16_t filter_6tap_64p_183[198] = {0x002C, 0x0420, 0x076C, 0x041C, 0x002C, 0x0000, + 0x0028, 0x040C, 0x0768, 0x0430, 0x0034, 0x0000, 0x0020, 0x03F8, 0x0768, 0x0448, 0x003C, 0x3FFC, + 0x0018, 0x03E4, 0x0768, 0x045C, 0x0044, 0x3FFC, 0x0014, 0x03D0, 0x0768, 0x0470, 0x004C, 0x3FF8, + 0x000C, 0x03BC, 0x0764, 0x0484, 0x0058, 0x3FF8, 0x0008, 0x03A4, 0x0764, 0x049C, 0x0060, 0x3FF4, + 0x0004, 0x0390, 0x0760, 0x04B0, 0x0068, 0x3FF4, 0x0000, 0x037C, 0x0760, 0x04C4, 0x0070, 0x3FF0, + 0x3FFC, 0x0364, 0x075C, 0x04D8, 0x007C, 0x3FF0, 0x3FF8, 0x0350, 0x0758, 0x04F0, 0x0084, 0x3FEC, + 0x3FF4, 0x033C, 0x0750, 0x0504, 0x0090, 0x3FEC, 0x3FF0, 0x0328, 0x074C, 0x0518, 0x009C, 0x3FE8, + 0x3FEC, 0x0314, 0x0744, 0x052C, 0x00A8, 0x3FE8, 0x3FE8, 0x0304, 0x0740, 0x0540, 0x00B0, 0x3FE4, + 0x3FE4, 0x02EC, 0x073C, 0x0554, 0x00BC, 0x3FE4, 0x3FE0, 0x02DC, 0x0734, 0x0568, 0x00C8, 0x3FE0, + 0x3FE0, 0x02C4, 0x072C, 0x057C, 0x00D4, 0x3FE0, 0x3FDC, 0x02B4, 0x0724, 0x058C, 0x00E4, 0x3FDC, + 0x3FDC, 0x02A0, 0x0718, 0x05A0, 0x00F0, 0x3FDC, 0x3FD8, 0x028C, 0x0714, 0x05B4, 0x00FC, 0x3FD8, + 0x3FD8, 0x0278, 0x0704, 0x05C8, 0x010C, 0x3FD8, 0x3FD4, 0x0264, 0x0700, 0x05D8, 0x0118, 0x3FD8, + 0x3FD4, 0x0254, 0x06F0, 0x05EC, 0x0128, 0x3FD4, 0x3FD0, 0x0244, 0x06E8, 0x05FC, 0x0134, 0x3FD4, + 0x3FD0, 0x0230, 0x06DC, 0x060C, 0x0144, 0x3FD4, 0x3FD0, 0x021C, 0x06D0, 0x0620, 0x0154, 0x3FD0, + 0x3FD0, 0x0208, 0x06C4, 0x0630, 0x0164, 0x3FD0, 0x3FD0, 0x01F8, 0x06B8, 0x0640, 0x0170, 0x3FD0, + 0x3FCC, 0x01E8, 0x06AC, 0x0650, 0x0180, 0x3FD0, 0x3FCC, 0x01D8, 0x069C, 0x0660, 0x0190, 0x3FD0, + 0x3FCC, 0x01C4, 0x068C, 0x0670, 0x01A4, 0x3FD0, 0x3FCC, 0x01B8, 0x0680, 0x067C, 0x01B4, 0x3FCC}; + +//========================================= +// = 8 +// = 64 +// = 0.83333 (input/output) +// = 0 +// = ModifiedLanczos +// = 1.10 +// = 1.12 +//========================================= +static const uint16_t filter_8tap_64p_upscale[264] = {0x0000, 0x0000, 0x0000, 0x1000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x3FFC, 0x0014, 0x3FC8, 0x1000, 0x0038, 0x3FEC, 0x0004, 0x0000, 0x3FF4, + 0x0024, 0x3F94, 0x0FFC, 0x0074, 0x3FD8, 0x000C, 0x0000, 0x3FF0, 0x0038, 0x3F60, 0x0FEC, 0x00B4, + 0x3FC4, 0x0014, 0x0000, 0x3FEC, 0x004C, 0x3F2C, 0x0FE4, 0x00F4, 0x3FAC, 0x0018, 0x0000, 0x3FE4, + 0x005C, 0x3F00, 0x0FD4, 0x0138, 0x3F94, 0x0020, 0x0000, 0x3FE0, 0x006C, 0x3ED0, 0x0FC4, 0x017C, + 0x3F7C, 0x0028, 0x0000, 0x3FDC, 0x007C, 0x3EA8, 0x0FA4, 0x01C4, 0x3F68, 0x0030, 0x0000, 0x3FD8, + 0x0088, 0x3E80, 0x0F90, 0x020C, 0x3F50, 0x0038, 0x3FFC, 0x3FD4, 0x0098, 0x3E58, 0x0F70, 0x0258, + 0x3F38, 0x0040, 0x3FFC, 0x3FD0, 0x00A4, 0x3E34, 0x0F54, 0x02A0, 0x3F1C, 0x004C, 0x3FFC, 0x3FD0, + 0x00B0, 0x3E14, 0x0F28, 0x02F0, 0x3F04, 0x0054, 0x3FFC, 0x3FCC, 0x00BC, 0x3DF4, 0x0F08, 0x033C, + 0x3EEC, 0x005C, 0x3FF8, 0x3FC8, 0x00C8, 0x3DD8, 0x0EDC, 0x038C, 0x3ED4, 0x0064, 0x3FF8, 0x3FC8, + 0x00D0, 0x3DC0, 0x0EAC, 0x03E0, 0x3EBC, 0x006C, 0x3FF4, 0x3FC4, 0x00D8, 0x3DA8, 0x0E7C, 0x0430, + 0x3EA4, 0x0078, 0x3FF4, 0x3FC4, 0x00E0, 0x3D94, 0x0E48, 0x0484, 0x3E8C, 0x0080, 0x3FF0, 0x3FC4, + 0x00E8, 0x3D80, 0x0E10, 0x04D8, 0x3E74, 0x0088, 0x3FF0, 0x3FC4, 0x00F0, 0x3D70, 0x0DD8, 0x052C, + 0x3E5C, 0x0090, 0x3FEC, 0x3FC0, 0x00F4, 0x3D60, 0x0DA0, 0x0584, 0x3E44, 0x0098, 0x3FEC, 0x3FC0, + 0x00F8, 0x3D54, 0x0D68, 0x05D8, 0x3E2C, 0x00A0, 0x3FE8, 0x3FC0, 0x00FC, 0x3D48, 0x0D20, 0x0630, + 0x3E18, 0x00AC, 0x3FE8, 0x3FC0, 0x0100, 0x3D40, 0x0CE0, 0x0688, 0x3E00, 0x00B4, 0x3FE4, 0x3FC4, + 0x0100, 0x3D3C, 0x0C98, 0x06DC, 0x3DEC, 0x00BC, 0x3FE4, 0x3FC4, 0x0100, 0x3D38, 0x0C58, 0x0734, + 0x3DD8, 0x00C0, 0x3FE0, 0x3FC4, 0x0104, 0x3D38, 0x0C0C, 0x078C, 0x3DC4, 0x00C8, 0x3FDC, 0x3FC4, + 0x0100, 0x3D38, 0x0BC4, 0x07E4, 0x3DB0, 0x00D0, 0x3FDC, 0x3FC4, 0x0100, 0x3D38, 0x0B78, 0x083C, + 0x3DA0, 0x00D8, 0x3FD8, 0x3FC8, 0x0100, 0x3D3C, 0x0B28, 0x0890, 0x3D90, 0x00DC, 0x3FD8, 0x3FC8, + 0x00FC, 0x3D40, 0x0ADC, 0x08E8, 0x3D80, 0x00E4, 0x3FD4, 0x3FCC, 0x00FC, 0x3D48, 0x0A84, 0x093C, + 0x3D74, 0x00E8, 0x3FD4, 0x3FCC, 0x00F8, 0x3D50, 0x0A38, 0x0990, 0x3D64, 0x00F0, 0x3FD0, 0x3FD0, + 0x00F4, 0x3D58, 0x09E0, 0x09E4, 0x3D5C, 0x00F4, 0x3FD0}; + +//========================================= +// = 8 +// = 64 +// = 1.16666 (input/output) +// = 0 +// = ModifiedLanczos +// = 1.10 +// = 1.12 +//========================================= +static const uint16_t filter_8tap_64p_116[264] = {0x0080, 0x3E90, 0x0268, 0x0D14, 0x0264, 0x3E90, + 0x0080, 0x0000, 0x007C, 0x3E9C, 0x0238, 0x0D14, 0x0298, 0x3E84, 0x0080, 0x0000, 0x0078, 0x3EAC, + 0x0200, 0x0D10, 0x02D0, 0x3E78, 0x0084, 0x0000, 0x0078, 0x3EB8, 0x01D0, 0x0D0C, 0x0304, 0x3E6C, + 0x0084, 0x0000, 0x0074, 0x3EC8, 0x01A0, 0x0D00, 0x033C, 0x3E60, 0x0088, 0x0000, 0x0070, 0x3ED4, + 0x0170, 0x0D00, 0x0374, 0x3E54, 0x0088, 0x3FFC, 0x006C, 0x3EE4, 0x0140, 0x0CF8, 0x03AC, 0x3E48, + 0x0088, 0x3FFC, 0x006C, 0x3EF0, 0x0114, 0x0CE8, 0x03E4, 0x3E3C, 0x008C, 0x3FFC, 0x0068, 0x3F00, + 0x00E8, 0x0CD8, 0x041C, 0x3E34, 0x008C, 0x3FFC, 0x0064, 0x3F10, 0x00BC, 0x0CCC, 0x0454, 0x3E28, + 0x008C, 0x3FFC, 0x0060, 0x3F1C, 0x0090, 0x0CBC, 0x0490, 0x3E20, 0x008C, 0x3FFC, 0x005C, 0x3F2C, + 0x0068, 0x0CA4, 0x04CC, 0x3E18, 0x008C, 0x3FFC, 0x0058, 0x3F38, 0x0040, 0x0C94, 0x0504, 0x3E10, + 0x008C, 0x3FFC, 0x0054, 0x3F48, 0x001C, 0x0C7C, 0x0540, 0x3E08, 0x0088, 0x3FFC, 0x0050, 0x3F54, + 0x3FF8, 0x0C60, 0x057C, 0x3E04, 0x0088, 0x3FFC, 0x004C, 0x3F64, 0x3FD4, 0x0C44, 0x05B8, 0x3DFC, + 0x0088, 0x3FFC, 0x0048, 0x3F70, 0x3FB4, 0x0C28, 0x05F4, 0x3DF8, 0x0084, 0x3FFC, 0x0044, 0x3F80, + 0x3F90, 0x0C0C, 0x0630, 0x3DF4, 0x0080, 0x3FFC, 0x0040, 0x3F8C, 0x3F70, 0x0BE8, 0x066C, 0x3DF4, + 0x0080, 0x3FFC, 0x003C, 0x3F9C, 0x3F50, 0x0BC8, 0x06A8, 0x3DF0, 0x007C, 0x3FFC, 0x0038, 0x3FA8, + 0x3F34, 0x0BA0, 0x06E4, 0x3DF0, 0x0078, 0x0000, 0x0034, 0x3FB4, 0x3F18, 0x0B80, 0x071C, 0x3DF0, + 0x0074, 0x0000, 0x0030, 0x3FC0, 0x3EFC, 0x0B5C, 0x0758, 0x3DF0, 0x0070, 0x0000, 0x002C, 0x3FCC, + 0x3EE4, 0x0B34, 0x0794, 0x3DF4, 0x0068, 0x0000, 0x002C, 0x3FDC, 0x3ECC, 0x0B08, 0x07CC, 0x3DF4, + 0x0064, 0x0000, 0x0028, 0x3FE4, 0x3EB4, 0x0AE0, 0x0808, 0x3DF8, 0x0060, 0x0000, 0x0024, 0x3FF0, + 0x3EA0, 0x0AB0, 0x0840, 0x3E00, 0x0058, 0x0004, 0x0020, 0x3FFC, 0x3E90, 0x0A84, 0x0878, 0x3E04, + 0x0050, 0x0004, 0x001C, 0x0004, 0x3E7C, 0x0A54, 0x08B0, 0x3E0C, 0x004C, 0x0008, 0x0018, 0x000C, + 0x3E68, 0x0A28, 0x08E8, 0x3E18, 0x0044, 0x0008, 0x0018, 0x0018, 0x3E54, 0x09F4, 0x0920, 0x3E20, + 0x003C, 0x000C, 0x0014, 0x0020, 0x3E48, 0x09C0, 0x0954, 0x3E2C, 0x0034, 0x0010, 0x0010, 0x002C, + 0x3E3C, 0x098C, 0x0988, 0x3E38, 0x002C, 0x0010}; + +//========================================= +// = 8 +// = 64 +// = 1.49999 (input/output) +// = 0 +// = ModifiedLanczos +// = 1.10 +// = 1.12 +//========================================= +static const uint16_t filter_8tap_64p_149[264] = {0x0008, 0x3E8C, 0x03F8, 0x0AE8, 0x03F8, 0x3E8C, + 0x0008, 0x0000, 0x000C, 0x3E8C, 0x03D0, 0x0AE8, 0x0420, 0x3E90, 0x0000, 0x0000, 0x000C, 0x3E8C, + 0x03AC, 0x0AE8, 0x0444, 0x3E90, 0x0000, 0x0000, 0x0010, 0x3E90, 0x0384, 0x0AE0, 0x046C, 0x3E94, + 0x3FFC, 0x0000, 0x0014, 0x3E90, 0x035C, 0x0ADC, 0x0494, 0x3E94, 0x3FF8, 0x0004, 0x0018, 0x3E90, + 0x0334, 0x0AD8, 0x04BC, 0x3E98, 0x3FF4, 0x0004, 0x001C, 0x3E94, 0x0310, 0x0AD0, 0x04E4, 0x3E9C, + 0x3FEC, 0x0004, 0x0020, 0x3E98, 0x02E8, 0x0AC4, 0x050C, 0x3EA0, 0x3FE8, 0x0008, 0x0020, 0x3E98, + 0x02C4, 0x0AC0, 0x0534, 0x3EA4, 0x3FE4, 0x0008, 0x0024, 0x3E9C, 0x02A0, 0x0AB4, 0x055C, 0x3EAC, + 0x3FDC, 0x0008, 0x0024, 0x3EA0, 0x027C, 0x0AA8, 0x0584, 0x3EB0, 0x3FD8, 0x000C, 0x0028, 0x3EA4, + 0x0258, 0x0A9C, 0x05AC, 0x3EB8, 0x3FD0, 0x000C, 0x0028, 0x3EA8, 0x0234, 0x0A90, 0x05D4, 0x3EC0, + 0x3FC8, 0x0010, 0x002C, 0x3EAC, 0x0210, 0x0A80, 0x05FC, 0x3EC8, 0x3FC4, 0x0010, 0x002C, 0x3EB4, + 0x01F0, 0x0A70, 0x0624, 0x3ED0, 0x3FBC, 0x0010, 0x002C, 0x3EB8, 0x01CC, 0x0A60, 0x064C, 0x3EDC, + 0x3FB4, 0x0014, 0x0030, 0x3EBC, 0x01A8, 0x0A50, 0x0674, 0x3EE4, 0x3FB0, 0x0014, 0x0030, 0x3EC4, + 0x0188, 0x0A38, 0x069C, 0x3EF0, 0x3FA8, 0x0018, 0x0030, 0x3ECC, 0x0168, 0x0A28, 0x06C0, 0x3EFC, + 0x3FA0, 0x0018, 0x0030, 0x3ED0, 0x0148, 0x0A14, 0x06E8, 0x3F08, 0x3F98, 0x001C, 0x0030, 0x3ED8, + 0x012C, 0x0A00, 0x070C, 0x3F14, 0x3F90, 0x001C, 0x0034, 0x3EE0, 0x0108, 0x09E4, 0x0734, 0x3F24, + 0x3F8C, 0x001C, 0x0034, 0x3EE4, 0x00EC, 0x09CC, 0x0758, 0x3F34, 0x3F84, 0x0020, 0x0034, 0x3EEC, + 0x00D0, 0x09B8, 0x077C, 0x3F40, 0x3F7C, 0x0020, 0x0034, 0x3EF4, 0x00B4, 0x0998, 0x07A4, 0x3F50, + 0x3F74, 0x0024, 0x0030, 0x3EFC, 0x0098, 0x0980, 0x07C8, 0x3F64, 0x3F6C, 0x0024, 0x0030, 0x3F04, + 0x0080, 0x0968, 0x07E8, 0x3F74, 0x3F64, 0x0024, 0x0030, 0x3F0C, 0x0060, 0x094C, 0x080C, 0x3F88, + 0x3F5C, 0x0028, 0x0030, 0x3F14, 0x0048, 0x0930, 0x0830, 0x3F98, 0x3F54, 0x0028, 0x0030, 0x3F1C, + 0x0030, 0x0914, 0x0850, 0x3FAC, 0x3F4C, 0x0028, 0x0030, 0x3F24, 0x0018, 0x08F0, 0x0874, 0x3FC0, + 0x3F44, 0x002C, 0x002C, 0x3F2C, 0x0000, 0x08D4, 0x0894, 0x3FD8, 0x3F3C, 0x002C, 0x002C, 0x3F34, + 0x3FEC, 0x08B4, 0x08B4, 0x3FEC, 0x3F34, 0x002C}; + +//========================================= +// = 8 +// = 64 +// = 1.83332 (input/output) +// = 0 +// = ModifiedLanczos +// = 1.10 +// = 1.12 +//========================================= +static const uint16_t filter_8tap_64p_183[264] = {0x3F88, 0x0048, 0x047C, 0x0768, 0x047C, 0x0048, + 0x3F88, 0x0000, 0x3F88, 0x003C, 0x0468, 0x076C, 0x0490, 0x0054, 0x3F84, 0x0000, 0x3F8C, 0x0034, + 0x0454, 0x0768, 0x04A4, 0x005C, 0x3F84, 0x0000, 0x3F8C, 0x0028, 0x0444, 0x076C, 0x04B4, 0x0068, + 0x3F80, 0x0000, 0x3F90, 0x0020, 0x042C, 0x0768, 0x04C8, 0x0074, 0x3F80, 0x0000, 0x3F90, 0x0018, + 0x041C, 0x0764, 0x04DC, 0x0080, 0x3F7C, 0x0000, 0x3F94, 0x0010, 0x0408, 0x075C, 0x04F0, 0x008C, + 0x3F7C, 0x0000, 0x3F94, 0x0004, 0x03F8, 0x0760, 0x0500, 0x0098, 0x3F7C, 0x3FFC, 0x3F98, 0x0000, + 0x03E0, 0x075C, 0x0514, 0x00A4, 0x3F78, 0x3FFC, 0x3F9C, 0x3FF8, 0x03CC, 0x0754, 0x0528, 0x00B0, + 0x3F78, 0x3FFC, 0x3F9C, 0x3FF0, 0x03B8, 0x0754, 0x0538, 0x00BC, 0x3F78, 0x3FFC, 0x3FA0, 0x3FE8, + 0x03A4, 0x0750, 0x054C, 0x00CC, 0x3F74, 0x3FF8, 0x3FA4, 0x3FE0, 0x0390, 0x074C, 0x055C, 0x00D8, + 0x3F74, 0x3FF8, 0x3FA4, 0x3FDC, 0x037C, 0x0744, 0x0570, 0x00E4, 0x3F74, 0x3FF8, 0x3FA8, 0x3FD4, + 0x0368, 0x0740, 0x0580, 0x00F4, 0x3F74, 0x3FF4, 0x3FA8, 0x3FCC, 0x0354, 0x073C, 0x0590, 0x0104, + 0x3F74, 0x3FF4, 0x3FAC, 0x3FC8, 0x0340, 0x0730, 0x05A4, 0x0110, 0x3F74, 0x3FF4, 0x3FB0, 0x3FC0, + 0x0330, 0x0728, 0x05B4, 0x0120, 0x3F74, 0x3FF0, 0x3FB0, 0x3FBC, 0x031C, 0x0724, 0x05C4, 0x0130, + 0x3F70, 0x3FF0, 0x3FB4, 0x3FB4, 0x0308, 0x0720, 0x05D4, 0x013C, 0x3F70, 0x3FF0, 0x3FB8, 0x3FB0, + 0x02F4, 0x0714, 0x05E4, 0x014C, 0x3F74, 0x3FEC, 0x3FB8, 0x3FAC, 0x02E0, 0x0708, 0x05F8, 0x015C, + 0x3F74, 0x3FEC, 0x3FBC, 0x3FA8, 0x02CC, 0x0704, 0x0604, 0x016C, 0x3F74, 0x3FE8, 0x3FC0, 0x3FA0, + 0x02BC, 0x06F8, 0x0614, 0x017C, 0x3F74, 0x3FE8, 0x3FC0, 0x3F9C, 0x02A8, 0x06F4, 0x0624, 0x018C, + 0x3F74, 0x3FE4, 0x3FC4, 0x3F98, 0x0294, 0x06E8, 0x0634, 0x019C, 0x3F74, 0x3FE4, 0x3FC8, 0x3F94, + 0x0284, 0x06D8, 0x0644, 0x01AC, 0x3F78, 0x3FE0, 0x3FC8, 0x3F90, 0x0270, 0x06D4, 0x0650, 0x01BC, + 0x3F78, 0x3FE0, 0x3FCC, 0x3F8C, 0x025C, 0x06C8, 0x0660, 0x01D0, 0x3F78, 0x3FDC, 0x3FCC, 0x3F8C, + 0x024C, 0x06B8, 0x066C, 0x01E0, 0x3F7C, 0x3FDC, 0x3FD0, 0x3F88, 0x0238, 0x06B0, 0x067C, 0x01F0, + 0x3F7C, 0x3FD8, 0x3FD4, 0x3F84, 0x0228, 0x069C, 0x0688, 0x0204, 0x3F80, 0x3FD8, 0x3FD4, 0x3F84, + 0x0214, 0x0694, 0x0694, 0x0214, 0x3F84, 0x3FD4}; + +const uint16_t *vpe_get_filter_4tap_64p(struct fixed31_32 ratio) +{ + if (ratio.value < vpe_fixpt_one.value) + return filter_4tap_64p_upscale; + else if (ratio.value < vpe_fixpt_from_fraction(4, 3).value) + return filter_4tap_64p_116; + else if (ratio.value < vpe_fixpt_from_fraction(5, 3).value) + return filter_4tap_64p_149; + else + return filter_4tap_64p_183; +} + +const uint16_t *vpe_get_filter_6tap_64p(struct fixed31_32 ratio) +{ + if (ratio.value < vpe_fixpt_one.value) + return filter_6tap_64p_upscale; + else if (ratio.value < vpe_fixpt_from_fraction(4, 3).value) + return filter_6tap_64p_116; + else if (ratio.value < vpe_fixpt_from_fraction(5, 3).value) + return filter_6tap_64p_149; + else + return filter_6tap_64p_183; +} + +const uint16_t *vpe_get_filter_8tap_64p(struct fixed31_32 ratio) +{ + if (ratio.value < vpe_fixpt_one.value) + return filter_8tap_64p_upscale; + else if (ratio.value < vpe_fixpt_from_fraction(4, 3).value) + return filter_8tap_64p_116; + else if (ratio.value < vpe_fixpt_from_fraction(5, 3).value) + return filter_8tap_64p_149; + else + return filter_8tap_64p_183; +} + +const uint16_t *vpe_get_filter_2tap_64p(void) +{ + return filter_2tap_64p; +} + +const uint16_t *vpe_get_2tap_bilinear_64p(void) +{ + return filter_2tap_bilinear_64p; +} diff --git a/src/amd/vpelib/src/core/vpe_visual_confirm.c b/src/amd/vpelib/src/core/vpe_visual_confirm.c new file mode 100644 index 00000000000..0283ee596d3 --- /dev/null +++ b/src/amd/vpelib/src/core/vpe_visual_confirm.c @@ -0,0 +1,217 @@ +/* Copyright 2023 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include "vpe_visual_confirm.h" +#include "common.h" +#include "vpe_priv.h" +#include "color_bg.h" +#include "background.h" +#include "resource.h" + +static uint16_t get_visual_confirm_segs_count(uint32_t max_seg_width, uint32_t target_rect_width) +{ + // Unlike max_gaps logic in vpe10_calculate_segments, we are pure BG seg, no need to worry + // stream splitted among one of the segment. so no need to "+1", just round up the calculated + // number of segments. + uint16_t seg_cnt = (uint16_t)(max((target_rect_width + max_seg_width - 1) / max_seg_width, 1)); + + return seg_cnt; +} + +static uint16_t vpe_get_visual_confirm_total_seg_count( + struct vpe_priv *vpe_priv, uint32_t max_seg_width, const struct vpe_build_param *params) +{ + uint16_t segs_num = 0; + uint16_t total_visual_confirm_segs = 0; + uint16_t stream_idx; + struct stream_ctx *stream_ctx; + + if (vpe_priv->init.debug.visual_confirm_params.input_format) { + for (stream_idx = 0; stream_idx < params->num_streams; stream_idx++) { + stream_ctx = &vpe_priv->stream_ctx[stream_idx]; + total_visual_confirm_segs += get_visual_confirm_segs_count( + max_seg_width, stream_ctx->stream.scaling_info.dst_rect.width); + } + } + + if (vpe_priv->init.debug.visual_confirm_params.output_format) { + total_visual_confirm_segs += + get_visual_confirm_segs_count(max_seg_width, params->target_rect.width); + } + + return total_visual_confirm_segs; +} + +struct vpe_color vpe_get_visual_confirm_color(enum vpe_surface_pixel_format format, + struct vpe_color_space cs, enum color_space output_cs, struct transfer_func *output_tf, + bool enable_3dlut) +{ + struct vpe_color visual_confirm_color; + visual_confirm_color.is_ycbcr = false; + visual_confirm_color.rgba.a = 0.0; + visual_confirm_color.rgba.r = 0.0; + visual_confirm_color.rgba.g = 0.0; + visual_confirm_color.rgba.b = 0.0; + + switch (format) { + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: + // YUV420 8bit: Green + visual_confirm_color.rgba.r = 0.0; + visual_confirm_color.rgba.g = 1.0; + visual_confirm_color.rgba.b = 0.0; + break; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: + // YUV420 10bit: yellow (SDR) + switch (cs.tf) { + case VPE_TF_G22: + case VPE_TF_G24: + visual_confirm_color.rgba.r = 1.0; + visual_confirm_color.rgba.g = 1.0; + visual_confirm_color.rgba.b = 0.0; + break; + // YUV420 10bit: White (HDR) + case VPE_TF_PQ: + case VPE_TF_HLG: + if (enable_3dlut) { + visual_confirm_color.rgba.r = 1.0; + visual_confirm_color.rgba.g = 1.0; + visual_confirm_color.rgba.b = 1.0; + } else { + visual_confirm_color.rgba.r = 1.0; + visual_confirm_color.rgba.g = 0.0; + visual_confirm_color.rgba.b = 0.0; + } + break; + default: + break; + } + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBA8888: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA8888: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_XRGB8888: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_XBGR8888: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBX8888: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRX8888: + // RGBA and RGBX 8 bit and variants : Pink + visual_confirm_color.rgba.r = 1.0; + visual_confirm_color.rgba.g = 0.5; + visual_confirm_color.rgba.b = 1.0; + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBA1010102: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA1010102: + // RGBA 10 bit and variants : Cyan + visual_confirm_color.rgba.r = 0.0; + visual_confirm_color.rgba.g = 1.0; + visual_confirm_color.rgba.b = 1.0; + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBA16161616F: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA16161616F: + // FP16 and variants: orange + visual_confirm_color.rgba.r = 1.0; + visual_confirm_color.rgba.g = 0.21972f; + visual_confirm_color.rgba.b = 0.0; + break; + default: + break; + } + + // Due to there will be regamma (ogam), need convert the bg color for visual confirm + vpe_bg_color_convert(output_cs, output_tf, &visual_confirm_color); + + // Experimental: To make FP16 Linear color looks more visually ok + if (output_tf->tf == TRANSFER_FUNC_LINEAR_0_125) { + visual_confirm_color.rgba.r /= 125; + visual_confirm_color.rgba.g /= 125; + visual_confirm_color.rgba.b /= 125; + } + + return visual_confirm_color; +} + +enum vpe_status vpe_create_visual_confirm_segs( + struct vpe_priv *vpe_priv, const struct vpe_build_param *params, uint32_t max_seg_width) +{ + uint16_t stream_idx; + struct stream_ctx *stream_ctx; + struct vpe_rect visual_confirm_rect; + struct vpe_rect *visual_confirm_gaps; + struct vpe_rect *current_gap; + + uint16_t total_seg_cnt = + vpe_get_visual_confirm_total_seg_count(vpe_priv, max_seg_width, params); + uint16_t seg_cnt = 0; + + if (!total_seg_cnt) + return VPE_STATUS_OK; + + visual_confirm_gaps = vpe_zalloc(sizeof(struct vpe_rect) * total_seg_cnt); + if (!visual_confirm_gaps) + return VPE_STATUS_NO_MEMORY; + + current_gap = visual_confirm_gaps; + + // Do visual confirm bg generation for intput format + if (vpe_priv->init.debug.visual_confirm_params.input_format && + params->target_rect.height > 2 * VISUAL_CONFIRM_HEIGHT) { + for (stream_idx = 0; stream_idx < params->num_streams; stream_idx++) { + stream_ctx = &vpe_priv->stream_ctx[stream_idx]; + visual_confirm_rect = stream_ctx->stream.scaling_info.dst_rect; + visual_confirm_rect.y += 0; + visual_confirm_rect.height = VISUAL_CONFIRM_HEIGHT; + seg_cnt = get_visual_confirm_segs_count( + max_seg_width, stream_ctx->stream.scaling_info.dst_rect.width); + vpe_full_bg_gaps(current_gap, &visual_confirm_rect, seg_cnt); + vpe_priv->resource.create_bg_segments( + vpe_priv, current_gap, seg_cnt, VPE_CMD_OPS_BG_VSCF_INPUT); + current_gap += seg_cnt; + } + } + // Do visual confirm bg generation for output format + if (vpe_priv->init.debug.visual_confirm_params.output_format && + params->target_rect.height > VISUAL_CONFIRM_HEIGHT) { + visual_confirm_rect = params->target_rect; + visual_confirm_rect.y += VISUAL_CONFIRM_HEIGHT; + visual_confirm_rect.height = VISUAL_CONFIRM_HEIGHT; + seg_cnt = get_visual_confirm_segs_count(max_seg_width, params->target_rect.width); + vpe_full_bg_gaps(current_gap, &visual_confirm_rect, seg_cnt); + vpe_priv->resource.create_bg_segments( + vpe_priv, current_gap, seg_cnt, VPE_CMD_OPS_BG_VSCF_OUTPUT); + } + + if (visual_confirm_gaps != NULL) { + vpe_free(visual_confirm_gaps); + visual_confirm_gaps = NULL; + current_gap = NULL; + } + + return VPE_STATUS_OK; +} diff --git a/src/amd/vpelib/src/core/vpelib.c b/src/amd/vpelib/src/core/vpelib.c new file mode 100644 index 00000000000..06cd5af9aab --- /dev/null +++ b/src/amd/vpelib/src/core/vpelib.c @@ -0,0 +1,658 @@ +/* Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include +#include "vpelib.h" +#include "vpe_priv.h" +#include "common.h" +#include "color_bg.h" +#include "color_gamma.h" +#include "cmd_builder.h" +#include "resource.h" +#include "color.h" +#include "vpec.h" +#include "vpe_desc_writer.h" +#include "dpp.h" +#include "mpc.h" +#include "opp.h" + +static void override_debug_option( + struct vpe_debug_options *debug, const struct vpe_debug_options *user_debug) +{ + if (user_debug->flags.bg_bit_depth) + debug->bg_bit_depth = user_debug->bg_bit_depth; + + if (user_debug->flags.cm_in_bypass) + debug->cm_in_bypass = user_debug->cm_in_bypass; + + if (user_debug->flags.vpcnvc_bypass) + debug->vpcnvc_bypass = user_debug->vpcnvc_bypass; + + if (user_debug->flags.mpc_bypass) + debug->mpc_bypass = user_debug->mpc_bypass; + + if (user_debug->flags.disable_reuse_bit) + debug->disable_reuse_bit = user_debug->disable_reuse_bit; + + if (user_debug->flags.identity_3dlut) + debug->identity_3dlut = user_debug->identity_3dlut; + + if (user_debug->flags.sce_3dlut) + debug->sce_3dlut = user_debug->sce_3dlut; + + if (user_debug->enable_mem_low_power.flags.cm) + debug->enable_mem_low_power.bits.cm = user_debug->enable_mem_low_power.bits.cm; + + if (user_debug->enable_mem_low_power.flags.dscl) + debug->enable_mem_low_power.bits.dscl = user_debug->enable_mem_low_power.bits.dscl; + + if (user_debug->enable_mem_low_power.flags.mpc) + debug->enable_mem_low_power.bits.mpc = user_debug->enable_mem_low_power.bits.mpc; + + if (user_debug->flags.bg_color_fill_only) + debug->bg_color_fill_only = user_debug->bg_color_fill_only; + + if (user_debug->flags.assert_when_not_support) + debug->assert_when_not_support = user_debug->assert_when_not_support; + + if (user_debug->flags.bypass_ogam) + debug->bypass_ogam = user_debug->bypass_ogam; + + if (user_debug->flags.bypass_gamcor) + debug->bypass_gamcor = user_debug->bypass_gamcor; + + if (user_debug->flags.bypass_dpp_gamut_remap) + debug->bypass_dpp_gamut_remap = user_debug->bypass_dpp_gamut_remap; + + if (user_debug->flags.bypass_post_csc) + debug->bypass_post_csc = user_debug->bypass_post_csc; + + if (user_debug->flags.force_tf_calculation) + debug->force_tf_calculation = user_debug->force_tf_calculation; + + if (user_debug->flags.clamping_setting) { + debug->clamping_setting = user_debug->clamping_setting; + debug->clamping_params = user_debug->clamping_params; + } + + if (user_debug->flags.expansion_mode) + debug->expansion_mode = user_debug->expansion_mode; + + if (user_debug->flags.bypass_per_pixel_alpha) + debug->bypass_per_pixel_alpha = user_debug->bypass_per_pixel_alpha; + + if (user_debug->flags.opp_pipe_crc_ctrl) + debug->opp_pipe_crc_ctrl = user_debug->opp_pipe_crc_ctrl; + + if (user_debug->flags.dpp_crc_ctrl) + debug->dpp_crc_ctrl = user_debug->dpp_crc_ctrl; + + if (user_debug->flags.mpc_crc_ctrl) + debug->mpc_crc_ctrl = user_debug->mpc_crc_ctrl; + + if (user_debug->flags.visual_confirm) + debug->visual_confirm_params = user_debug->visual_confirm_params; +} + +struct vpe *vpe_create(const struct vpe_init_data *params) +{ + struct vpe_priv *vpe_priv; + enum vpe_status status; + + if (!params || (params->funcs.zalloc == NULL) || (params->funcs.free == NULL) || + (params->funcs.log == NULL)) + return NULL; + + vpe_priv = + (struct vpe_priv *)params->funcs.zalloc(params->funcs.mem_ctx, sizeof(struct vpe_priv)); + if (!vpe_priv) + return NULL; + + vpe_priv->init = *params; + + vpe_priv->pub.level = + vpe_resource_parse_ip_version(params->ver_major, params->ver_minor, params->ver_rev); + + vpe_priv->pub.version = (VPELIB_API_VERSION_MAJOR << VPELIB_API_VERSION_MAJOR_SHIFT) | + (VPELIB_API_VERSION_MINOR << VPELIB_API_VERSION_MINOR_SHIFT); + + status = vpe_construct_resource(vpe_priv, vpe_priv->pub.level, &vpe_priv->resource); + if (status != VPE_STATUS_OK) { + vpe_free(vpe_priv); + return NULL; + } + + override_debug_option(&vpe_priv->init.debug, ¶ms->debug); + + vpe_color_setup_x_points_distribution(); + vpe_color_setup_x_points_distribution_degamma(); + + vpe_priv->ops_support = false; + vpe_priv->scale_yuv_matrix = true; + return &vpe_priv->pub; +} + +void vpe_destroy(struct vpe **vpe) +{ + struct vpe_priv *vpe_priv; + + if (!vpe || ((*vpe) == NULL)) + return; + + vpe_priv = container_of(*vpe, struct vpe_priv, pub); + + vpe_destroy_resource(vpe_priv, &vpe_priv->resource); + + vpe_free_output_ctx(vpe_priv); + + vpe_free_stream_ctx(vpe_priv); + + if (vpe_priv->dummy_input_param) + vpe_free(vpe_priv->dummy_input_param); + + if (vpe_priv->dummy_stream) + vpe_free(vpe_priv->dummy_stream); + + vpe_free(vpe_priv); + + *vpe = NULL; +} + +/***************************************************************************************** + * handle_zero_input + * handle any zero input stream but background output only + * struct vpe* vpe + * [input] vpe context + * const struct vpe_build_param* org_param + * [input] original parameter from caller + * struct vpe_build_param* dummy_input_param + * [output] caller provided param struct for filling with dummy input + * struct struct vpe_stream* dummy_stream + * [output] caller provided vpe_stream struct for use in dummy_input_param->streams + *****************************************************************************************/ +static enum vpe_status handle_zero_input(struct vpe *vpe, const struct vpe_build_param *in_param, + const struct vpe_build_param **out_param) +{ + struct vpe_priv *vpe_priv; + struct vpe_surface_info *surface_info; + struct vpe_scaling_info *scaling_info; + struct vpe_scaling_filter_coeffs *polyphaseCoeffs; + struct vpe_stream *stream; + + vpe_priv = container_of(vpe, struct vpe_priv, pub); + + if (!in_param || !out_param) + return VPE_STATUS_ERROR; + + *out_param = NULL; + + if (in_param->num_streams == 0 || vpe_priv->init.debug.bg_color_fill_only) { + + // if output surface is too small, don't use it as dummy input + // request 2x2 instead of 1x1 for bpc safety + // as we are to treat output as input for RGB 1x1, need 4bytes at least + // but if output is YUV, bpc will be smaller and need larger dimension + + if (in_param->dst_surface.plane_size.surface_size.width < VPE_MIN_VIEWPORT_SIZE || + in_param->dst_surface.plane_size.surface_size.height < VPE_MIN_VIEWPORT_SIZE || + in_param->dst_surface.plane_size.surface_pitch < 256 / 4 || // 256bytes, 4bpp + in_param->target_rect.width < VPE_MIN_VIEWPORT_SIZE || + in_param->target_rect.height < VPE_MIN_VIEWPORT_SIZE) { + return VPE_STATUS_ERROR; + } + + if (!vpe_priv->dummy_input_param) { + vpe_priv->dummy_input_param = vpe_zalloc(sizeof(struct vpe_build_param)); + if (!vpe_priv->dummy_input_param) + return VPE_STATUS_NO_MEMORY; + } + + if (!vpe_priv->dummy_stream) { + vpe_priv->dummy_stream = vpe_zalloc(sizeof(struct vpe_stream)); + if (!vpe_priv->dummy_stream) + return VPE_STATUS_NO_MEMORY; + } + + *vpe_priv->dummy_input_param = *in_param; + + vpe_priv->dummy_input_param->num_streams = 1; + vpe_priv->dummy_input_param->streams = vpe_priv->dummy_stream; + + // set output surface as our dummy input + stream = vpe_priv->dummy_stream; + surface_info = &stream->surface_info; + scaling_info = &stream->scaling_info; + polyphaseCoeffs = &stream->polyphase_scaling_coeffs; + surface_info->address.type = VPE_PLN_ADDR_TYPE_GRAPHICS; + surface_info->address.tmz_surface = in_param->dst_surface.address.tmz_surface; + surface_info->address.grph.addr.quad_part = + in_param->dst_surface.address.grph.addr.quad_part; + + surface_info->swizzle = VPE_SW_LINEAR; // treat it as linear for simple + surface_info->plane_size.surface_size.x = 0; + surface_info->plane_size.surface_size.y = 0; + surface_info->plane_size.surface_size.width = VPE_MIN_VIEWPORT_SIZE; // min width in pixels + surface_info->plane_size.surface_size.height = + VPE_MIN_VIEWPORT_SIZE; // min height in pixels + surface_info->plane_size.surface_pitch = 256 / 4; // pitch in pixels + surface_info->plane_size.surface_aligned_height = VPE_MIN_VIEWPORT_SIZE; + surface_info->dcc.enable = false; + surface_info->format = VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBA8888; + surface_info->cs.encoding = VPE_PIXEL_ENCODING_RGB; + surface_info->cs.range = VPE_COLOR_RANGE_FULL; + surface_info->cs.tf = VPE_TF_G22; + surface_info->cs.cositing = VPE_CHROMA_COSITING_NONE; + surface_info->cs.primaries = VPE_PRIMARIES_BT709; + scaling_info->src_rect.x = 0; + scaling_info->src_rect.y = 0; + scaling_info->src_rect.width = VPE_MIN_VIEWPORT_SIZE; + scaling_info->src_rect.height = VPE_MIN_VIEWPORT_SIZE; + scaling_info->dst_rect.x = in_param->target_rect.x; + scaling_info->dst_rect.y = in_param->target_rect.y; + scaling_info->dst_rect.width = VPE_MIN_VIEWPORT_SIZE; + scaling_info->dst_rect.height = VPE_MIN_VIEWPORT_SIZE; + scaling_info->taps.v_taps = 4; + scaling_info->taps.h_taps = 4; + scaling_info->taps.v_taps_c = 2; + scaling_info->taps.h_taps_c = 2; + + polyphaseCoeffs->taps = scaling_info->taps; + polyphaseCoeffs->nb_phases = 64; + + stream->blend_info.blending = true; + stream->blend_info.pre_multiplied_alpha = false; + stream->blend_info.global_alpha = true; // hardcoded upon DAL request + stream->blend_info.global_alpha_value = 0; // transparent as we are dummy input + + stream->color_adj.brightness = 0.0f; + stream->color_adj.contrast = 1.0f; + stream->color_adj.hue = 0.0f; + stream->color_adj.saturation = 1.0f; + stream->rotation = VPE_ROTATION_ANGLE_0; + stream->horizontal_mirror = false; + stream->vertical_mirror = false; + stream->enable_luma_key = false; + stream->lower_luma_bound = 0; + stream->upper_luma_bound = 0; + stream->flags.hdr_metadata = 0; + stream->use_external_scaling_coeffs = false; + *out_param = vpe_priv->dummy_input_param; + } else { + *out_param = in_param; + } + + return VPE_STATUS_OK; +} + +enum vpe_status vpe_check_support( + struct vpe *vpe, const struct vpe_build_param *param, struct vpe_bufs_req *req) +{ + struct vpe_priv *vpe_priv; + struct vpec *vpec; + struct dpp *dpp; + enum vpe_status status; + struct stream_ctx *stream_ctx; + struct output_ctx *output_ctx = NULL; + uint32_t i; + bool input_h_mirror, output_h_mirror; + + vpe_priv = container_of(vpe, struct vpe_priv, pub); + vpec = &vpe_priv->resource.vpec; + dpp = vpe_priv->resource.dpp[0]; + + status = handle_zero_input(vpe, param, ¶m); + if (status != VPE_STATUS_OK) + status = VPE_STATUS_NUM_STREAM_NOT_SUPPORTED; + + if (!vpe_priv->stream_ctx || vpe_priv->num_streams != param->num_streams) { + if (vpe_priv->stream_ctx) + vpe_free_stream_ctx(vpe_priv); + + vpe_priv->stream_ctx = vpe_alloc_stream_ctx(vpe_priv, param->num_streams); + } + + if (!vpe_priv->stream_ctx) + status = VPE_STATUS_NO_MEMORY; + + // VPElib needs to cache whether or not the 3DLUT has been updated + // This is to deal with case when 3DLUT has been updated but VPE rejects the job. + // Need a sticky bit to tell vpe to program the 3dlut on next jobs submission even + // if 3dlut has not changed + for (i = 0; i < param->num_streams; i++) { + vpe_cache_tone_map_params(&vpe_priv->stream_ctx[i], param); + } + + if (status == VPE_STATUS_OK) { + // output checking - check per asic support + status = vpe_check_output_support(vpe, param); + if (status != VPE_STATUS_OK) { + vpe_log("fail output support check. status %d\n", (int)status); + } + } + + if (status == VPE_STATUS_OK) { + // input checking - check per asic support + for (i = 0; i < param->num_streams; i++) { + status = vpe_check_input_support(vpe, ¶m->streams[i]); + if (status != VPE_STATUS_OK) { + vpe_log("fail input support check. status %d\n", (int)status); + break; + } + } + } + + if (status == VPE_STATUS_OK) { + // input checking - check tone map support + for (i = 0; i < param->num_streams; i++) { + status = vpe_check_tone_map_support(vpe, ¶m->streams[i], param); + if (status != VPE_STATUS_OK) { + vpe_log("fail input support check. status %d\n", (int)status); + break; + } + } + } + + if (status == VPE_STATUS_OK) { + // output resource preparation for further checking (cache the result) + output_ctx = &vpe_priv->output_ctx; + output_ctx->surface = param->dst_surface; + output_ctx->bg_color = param->bg_color; + output_ctx->target_rect = param->target_rect; + output_ctx->alpha_mode = param->alpha_mode; + output_ctx->flags.hdr_metadata = param->flags.hdr_metadata; + output_ctx->hdr_metadata = param->hdr_metadata; + + vpe_priv->num_vpe_cmds = 0; + output_ctx->clamping_params = vpe_priv->init.debug.clamping_params; + + vpe_priv->num_streams = param->num_streams; + } + + if (status == VPE_STATUS_OK) { + // blending support check + vpe_priv->resource.check_h_mirror_support(&input_h_mirror, &output_h_mirror); + + for (i = 0; i < param->num_streams; i++) { + stream_ctx = &vpe_priv->stream_ctx[i]; + stream_ctx->stream_idx = (int32_t)i; + stream_ctx->per_pixel_alpha = + vpe_has_per_pixel_alpha(param->streams[i].surface_info.format); + if (vpe_priv->init.debug.bypass_per_pixel_alpha) { + stream_ctx->per_pixel_alpha = false; + } + if (param->streams[i].horizontal_mirror && !input_h_mirror && output_h_mirror) + stream_ctx->flip_horizonal_output = true; + else + stream_ctx->flip_horizonal_output = false; + + memcpy(&stream_ctx->stream, ¶m->streams[i], sizeof(struct vpe_stream)); + + /* if top-bottom blending is not supported, + * the 1st stream still can support blending with background, + * however, the 2nd stream and onward can't enable blending. + */ + if (i && param->streams[i].blend_info.blending && + !vpe_priv->pub.caps->color_caps.mpc.top_bottom_blending) { + status = VPE_STATUS_ALPHA_BLENDING_NOT_SUPPORTED; + break; + } + } + } + + if (status == VPE_STATUS_OK) { + status = vpe_priv->resource.calculate_segments(vpe_priv, param); + if (status != VPE_STATUS_OK) + vpe_log("failed in calculate segments %d\n", (int)status); + } + + if (status == VPE_STATUS_OK) { + // if the bg_color support is false, there is a flag to verify if the bg_color falls in the + // output gamut + if (!vpe_priv->pub.caps->bg_color_check_support) { + status = vpe_bg_color_outside_cs_gamut(&output_ctx->surface.cs, &output_ctx->bg_color); + if (status != VPE_STATUS_OK) { + vpe_log( + "failed in checking the background color versus the output color space %d\n", + (int)status); + } + } + } + + if (status == VPE_STATUS_OK) { + // Calculate the buffer needed (worst case) + vpe_priv->resource.get_bufs_req(vpe_priv, &vpe_priv->bufs_required); + *req = vpe_priv->bufs_required; + vpe_priv->ops_support = true; + } + + if (vpe_priv->init.debug.assert_when_not_support) + VPE_ASSERT(status == VPE_STATUS_OK); + + return status; +} + +enum vpe_status vpe_build_noops(struct vpe *vpe, uint32_t num_dword, uint32_t **ppcmd_space) +{ + struct vpe_priv *vpe_priv; + struct cmd_builder *builder; + enum vpe_status status; + + if (!vpe || !ppcmd_space || ((*ppcmd_space) == NULL)) + return VPE_STATUS_ERROR; + + vpe_priv = container_of(vpe, struct vpe_priv, pub); + + builder = &vpe_priv->resource.cmd_builder; + + status = builder->build_noops(vpe_priv, ppcmd_space, num_dword); + + return status; +} + +static bool validate_cached_param(struct vpe_priv *vpe_priv, const struct vpe_build_param *param) +{ + uint32_t i; + struct output_ctx *output_ctx; + + if (vpe_priv->num_streams != param->num_streams) + return false; + + for (i = 0; i < param->num_streams; i++) { + struct vpe_stream stream = param->streams[i]; + + vpe_clip_stream( + &stream.scaling_info.src_rect, &stream.scaling_info.dst_rect, ¶m->target_rect); + + if (memcmp(&vpe_priv->stream_ctx[i].stream, &stream, sizeof(struct vpe_stream))) + return false; + } + + output_ctx = &vpe_priv->output_ctx; + if (output_ctx->alpha_mode != param->alpha_mode) + return false; + + if (memcmp(&output_ctx->bg_color, ¶m->bg_color, sizeof(struct vpe_color))) + return false; + + if (memcmp(&output_ctx->target_rect, ¶m->target_rect, sizeof(struct vpe_rect))) + return false; + + if (memcmp(&output_ctx->surface, ¶m->dst_surface, sizeof(struct vpe_surface_info))) + return false; + + return true; +} + +static bool validate_color_pipeline(struct vpe_priv *vpe_priv, const struct vpe_build_param *param) +{ + uint32_t stream_idx; + struct stream_ctx *stream_ctx; + struct output_ctx *output_ctx; + + output_ctx = &vpe_priv->output_ctx; + + /* For BG color, we need to make sure degamm / regamm is not bypass, + * as we want to have input in the range of 0-1 in mpc, + * since mpc only allows 0-1 range for BG color + */ + for (stream_idx = 0; stream_idx < param->num_streams; stream_idx++) { + stream_ctx = &vpe_priv->stream_ctx[stream_idx]; + if (output_ctx->output_tf->type == TF_TYPE_BYPASS && + stream_ctx->input_tf->type == TF_TYPE_BYPASS) + return false; + } + + return true; +} + +enum vpe_status vpe_build_commands( + struct vpe *vpe, const struct vpe_build_param *param, struct vpe_build_bufs *bufs) +{ + struct vpe_priv *vpe_priv; + struct cmd_builder *builder; + enum vpe_status status = VPE_STATUS_OK; + uint32_t cmd_idx, i, j; + struct vpe_build_bufs curr_bufs; + int64_t cmd_buf_size; + int64_t emb_buf_size; + uint64_t cmd_buf_gpu_a, cmd_buf_cpu_a; + uint64_t emb_buf_gpu_a, emb_buf_cpu_a; + + if (!vpe || !param || !bufs) + return VPE_STATUS_ERROR; + + vpe_priv = container_of(vpe, struct vpe_priv, pub); + + if (!vpe_priv->ops_support) { + VPE_ASSERT(vpe_priv->ops_support); + status = VPE_STATUS_NOT_SUPPORTED; + } + + if (status == VPE_STATUS_OK) { + status = handle_zero_input(vpe, param, ¶m); + if (status != VPE_STATUS_OK) + status = VPE_STATUS_NUM_STREAM_NOT_SUPPORTED; + } + + if (status == VPE_STATUS_OK) { + if (!validate_cached_param(vpe_priv, param)) { + status = VPE_STATUS_PARAM_CHECK_ERROR; + } + } + + if (status == VPE_STATUS_OK) { + + if (bufs->cmd_buf.size == 0 || bufs->emb_buf.size == 0) { + /* Here we directly return without setting ops_support to false + * becaues the supported check is already passed + * and the caller can come again with correct buffer size. + */ + bufs->cmd_buf.size = (int64_t)vpe_priv->bufs_required.cmd_buf_size; + bufs->emb_buf.size = (int64_t)vpe_priv->bufs_required.emb_buf_size; + return VPE_STATUS_OK; + } else if ((bufs->cmd_buf.size < (int32_t)vpe_priv->bufs_required.cmd_buf_size) || + (bufs->emb_buf.size < (int32_t)vpe_priv->bufs_required.emb_buf_size)) { + status = VPE_STATUS_INVALID_BUFFER_SIZE; + } + } + + builder = &vpe_priv->resource.cmd_builder; + + // store buffers original values + cmd_buf_cpu_a = bufs->cmd_buf.cpu_va; + cmd_buf_gpu_a = bufs->cmd_buf.gpu_va; + cmd_buf_size = bufs->cmd_buf.size; + + emb_buf_cpu_a = bufs->emb_buf.cpu_va; + emb_buf_gpu_a = bufs->emb_buf.gpu_va; + emb_buf_size = bufs->emb_buf.size; + + // curr_bufs is used for tracking the built size and next pointers + curr_bufs = *bufs; + + // copy the param, reset saved configs + for (i = 0; i < param->num_streams; i++) { + vpe_priv->stream_ctx[i].num_configs = 0; + for (j = 0; j < VPE_CMD_TYPE_COUNT; j++) + vpe_priv->stream_ctx[i].num_stream_op_configs[j] = 0; + } + vpe_priv->output_ctx.num_configs = 0; + + // Reset pipes + vpe_pipe_reset(vpe_priv); + + if (status == VPE_STATUS_OK) { + status = vpe_color_update_color_space_and_tf(vpe_priv, param); + if (status != VPE_STATUS_OK) { + vpe_log("failed in updating color space and tf %d\n", (int)status); + } + } + + if (status == VPE_STATUS_OK) { + status = vpe_color_update_movable_cm(vpe_priv, param); + if (status != VPE_STATUS_OK) { + vpe_log("failed in updating movable 3d lut unit %d\n", (int)status); + } + } + + if (status == VPE_STATUS_OK) { + status = vpe_color_update_whitepoint(vpe_priv, param); + if (status != VPE_STATUS_OK) { + vpe_log("failed updating whitepoint gain %d\n", (int)status); + } + } + if (status == VPE_STATUS_OK) { + VPE_ASSERT(validate_color_pipeline(vpe_priv, param)); + } + if (status == VPE_STATUS_OK) { + vpe_bg_color_convert(vpe_priv->output_ctx.cs, vpe_priv->output_ctx.output_tf, + &vpe_priv->output_ctx.bg_color); + + for (cmd_idx = 0; cmd_idx < vpe_priv->num_vpe_cmds; cmd_idx++) { + + status = builder->build_vpe_cmd(vpe_priv, &curr_bufs, cmd_idx); + if (status != VPE_STATUS_OK) { + vpe_log("failed in building vpe cmd %d\n", (int)status); + } + + } + } + + if (status == VPE_STATUS_OK) { + bufs->cmd_buf.size = cmd_buf_size - curr_bufs.cmd_buf.size; // used cmd buffer size + bufs->cmd_buf.gpu_va = cmd_buf_gpu_a; + bufs->cmd_buf.cpu_va = cmd_buf_cpu_a; + + bufs->emb_buf.size = emb_buf_size - curr_bufs.emb_buf.size; // used emb buffer size + bufs->emb_buf.gpu_va = emb_buf_gpu_a; + bufs->emb_buf.cpu_va = emb_buf_cpu_a; + } + + vpe_priv->ops_support = false; + + if (vpe_priv->init.debug.assert_when_not_support) + VPE_ASSERT(status == VPE_STATUS_OK); + + return status; +} diff --git a/src/amd/vpelib/src/utils/conversion.c b/src/amd/vpelib/src/utils/conversion.c new file mode 100644 index 00000000000..e908261d73e --- /dev/null +++ b/src/amd/vpelib/src/utils/conversion.c @@ -0,0 +1,100 @@ +/* Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ +#include "conversion.h" + +#define DIVIDER 10000 + +/* S2D13 value in [-3.99...3.9999] */ +#define S2D13_MIN ((long long)(-3.999 * DIVIDER)) +#define S2D13_MAX ((long long)(3.999 * DIVIDER)) + +#define FRACTIONAL_PART_MASK ((1ULL << FIXED31_32_BITS_PER_FRACTIONAL_PART) - 1) + +#define GET_INTEGER_PART(x) ((x) >> FIXED31_32_BITS_PER_FRACTIONAL_PART) + +#define GET_FRACTIONAL_PART(x) (FRACTIONAL_PART_MASK & (x)) + +uint16_t conv_fixed_point_to_int_frac( + struct fixed31_32 arg, uint8_t integer_bits, uint8_t fractional_bits) +{ + int32_t numerator; + int32_t divisor = 1 << fractional_bits; + + uint16_t result; + + uint16_t d = (uint16_t)vpe_fixpt_floor(vpe_fixpt_abs(arg)); + + if (d <= (uint16_t)(1 << integer_bits) - (1 / (uint16_t)divisor)) + numerator = (uint16_t)vpe_fixpt_round(vpe_fixpt_mul_int(arg, divisor)); + else { + numerator = vpe_fixpt_floor(vpe_fixpt_sub( + vpe_fixpt_from_int(1LL << integer_bits), vpe_fixpt_recip(vpe_fixpt_from_int(divisor)))); + } + + if (numerator >= 0) + result = (uint16_t)numerator; + else + result = (uint16_t)((1 << (integer_bits + fractional_bits + 1)) + numerator); + + if ((result != 0) && vpe_fixpt_lt(arg, vpe_fixpt_zero)) + result |= 1 << (integer_bits + fractional_bits); + + return result; +} + +void conv_convert_float_matrix(uint16_t *matrix, const struct fixed31_32 *flt, uint32_t buffer_size) +{ + const struct fixed31_32 min_2_13 = vpe_fixpt_from_fraction(S2D13_MIN, DIVIDER); + const struct fixed31_32 max_2_13 = vpe_fixpt_from_fraction(S2D13_MAX, DIVIDER); + uint32_t i; + + for (i = 0; i < buffer_size; ++i) { + uint32_t reg_value = + conv_fixed_point_to_int_frac(vpe_fixpt_clamp(flt[i], min_2_13, max_2_13), 2, 13); + + matrix[i] = (uint16_t)reg_value; + } +} + +struct fixed31_32 vpe_convfix31_32(int16_t inval) +{ + const int integerBits = 2; + const int fractionalBits = 13; + struct fixed31_32 result; + long long outintegerPart; + long long outfractionalPart; + int sign = 1; + if (inval & (1 << (integerBits + fractionalBits + 1))) { + sign = -1; + inval = -inval; + } + outintegerPart = ((long long)inval >> fractionalBits) << 32; + outfractionalPart = ((long long)inval & (((long long)1 << fractionalBits) - 1)); + ; + outfractionalPart <<= (32 - fractionalBits); + result.value = outintegerPart | outfractionalPart; + if (sign < 0) + result.value = -result.value; + return result; +} diff --git a/src/amd/vpelib/src/utils/custom_float.c b/src/amd/vpelib/src/utils/custom_float.c new file mode 100644 index 00000000000..aacec2eaccf --- /dev/null +++ b/src/amd/vpelib/src/utils/custom_float.c @@ -0,0 +1,155 @@ +/* Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ +#include "custom_float.h" + +static bool build_custom_float(struct fixed31_32 value, const struct custom_float_format *format, + bool *negative, uint32_t *mantissa, uint32_t *exponenta) +{ + uint32_t exp_offset = (1 << (format->exponenta_bits - 1)) - 1; + + const struct fixed31_32 mantissa_constant_plus_max_fraction = vpe_fixpt_from_fraction( + (1LL << (format->mantissa_bits + 1)) - 1, 1LL << format->mantissa_bits); + + struct fixed31_32 mantiss; + + if (vpe_fixpt_eq(value, vpe_fixpt_zero)) { + *negative = false; + *mantissa = 0; + *exponenta = 0; + return true; + } + + if (vpe_fixpt_lt(value, vpe_fixpt_zero)) { + *negative = format->sign; + value = vpe_fixpt_neg(value); + } else { + *negative = false; + } + + if (vpe_fixpt_lt(value, vpe_fixpt_one)) { + uint32_t i = 1; + + do { + value = vpe_fixpt_shl(value, 1); + ++i; + } while (vpe_fixpt_lt(value, vpe_fixpt_one)); + + --i; + + if (exp_offset <= i) { + *mantissa = 0; + *exponenta = 0; + return true; + } + + *exponenta = exp_offset - i; + } else if (vpe_fixpt_le(mantissa_constant_plus_max_fraction, value)) { + uint32_t i = 1; + + do { + value = vpe_fixpt_shr(value, 1); + ++i; + } while (vpe_fixpt_lt(mantissa_constant_plus_max_fraction, value)); + + *exponenta = exp_offset + i - 1; + } else { + *exponenta = exp_offset; + } + + mantiss = vpe_fixpt_sub(value, vpe_fixpt_one); + + if (vpe_fixpt_lt(mantiss, vpe_fixpt_zero) || vpe_fixpt_lt(vpe_fixpt_one, mantiss)) + mantiss = vpe_fixpt_zero; + else + mantiss = vpe_fixpt_shl(mantiss, (unsigned char)format->mantissa_bits); + + *mantissa = (uint32_t)vpe_fixpt_floor(mantiss); + + return true; +} + +static bool setup_custom_float(const struct custom_float_format *format, bool negative, + uint32_t mantissa, uint32_t exponenta, uint32_t *result) +{ + uint32_t i = 0; + uint32_t j = 0; + + uint32_t value = 0; + + /* verification code: + * once calculation is ok we can remove it + */ + + const uint32_t mantissa_mask = (1 << (format->mantissa_bits + 1)) - 1; + + const uint32_t exponenta_mask = (1 << (format->exponenta_bits + 1)) - 1; + + if (mantissa & ~mantissa_mask) { + VPE_ASSERT(0); + mantissa = mantissa_mask; + } + + if (exponenta & ~exponenta_mask) { + VPE_ASSERT(0); + exponenta = exponenta_mask; + } + + /* end of verification code */ + + while (i < format->mantissa_bits) { + uint32_t mask = 1 << i; + + if (mantissa & mask) + value |= mask; + + ++i; + } + + while (j < format->exponenta_bits) { + uint32_t mask = 1 << j; + + if (exponenta & mask) + value |= mask << i; + + ++j; + } + + if (negative && format->sign) + value |= 1 << (i + j); + + *result = value; + + return true; +} + +bool vpe_convert_to_custom_float_format( + struct fixed31_32 value, const struct custom_float_format *format, uint32_t *result) +{ + uint32_t mantissa; + uint32_t exponenta; + bool negative; + + return build_custom_float(value, format, &negative, &mantissa, &exponenta) && + setup_custom_float(format, negative, mantissa, exponenta, result); +} diff --git a/src/amd/vpelib/src/utils/custom_fp16.c b/src/amd/vpelib/src/utils/custom_fp16.c new file mode 100644 index 00000000000..a5608c7d2f1 --- /dev/null +++ b/src/amd/vpelib/src/utils/custom_fp16.c @@ -0,0 +1,312 @@ +/* Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include "vpe_assert.h" +#include "custom_fp16.h" +#include +#include + +static bool build_custom_float(double value, const struct vpe_custom_float_format2 *fmt, + bool *pbNegative, unsigned int *pexponent, unsigned int *pmantissa) +{ + bool bRet = false; + double mantissaConstant = 1.0; + double base = 2.0; + int expOffset = (int)(pow(2.0, fmt->exponentaBits - 1) - 1); + double maxFraction = 1.0 - pow(0.5, fmt->mantissaBits); + unsigned int exponent; + double mantissa; + unsigned int Mantissa; + int i; + bool bAlwaysFalse = false; + + // if value negative and we should consider this otherwize just ignore + if (value < 0 && fmt->flags.bits.sign == 1) + *pbNegative = true; + else + *pbNegative = false; + + do { + + if (value == 0.0) { + *pexponent = 0; + *pmantissa = 0; + bRet = true; + break; + } + + if (value < 0) + value = (-1.0) * value; + + if (value < mantissaConstant) { + /*if log works faster then remove the loops!*/ + for (i = 1;; i++) { + value *= base; + if (value >= mantissaConstant) + break; + } + if (expOffset <= i) { + *pexponent = 0; + *pmantissa = 0; + bRet = true; + break; + } + exponent = (unsigned int)(expOffset - i); + } else if (value >= mantissaConstant + maxFraction) { + for (i = 1;; i++) { + value /= base; + if (value <= mantissaConstant + maxFraction) + break; + } + exponent = (unsigned int)(expOffset + i); + } else + exponent = (unsigned int)expOffset; + + mantissa = value - mantissaConstant; + + if (mantissa < 0.0 || mantissa > 1.0) + mantissa = 0; + else + mantissa *= pow(2.0, fmt->mantissaBits); + + Mantissa = (unsigned int)mantissa; + + *pexponent = exponent; + *pmantissa = Mantissa; + + bRet = true; + + } while (bAlwaysFalse); + + return bRet; +} + +static bool setup_custom_float(const struct vpe_custom_float_format2 *fmt, bool bNegative, + unsigned int exponent, unsigned int mantissa, uint16_t *pvalue) +{ + unsigned int value = 0; + unsigned int mask; + unsigned int i; + unsigned int j; + + if (fmt->exponentaBits == 6 && fmt->mantissaBits == 12 && fmt->flags.bits.sign == 0) { + if (exponent & ~(unsigned int)0x3F) + exponent = 0x3F; + if (mantissa & ~(unsigned int)0xFFF) + mantissa = 0xFFF; + } else if (fmt->exponentaBits == 6 && fmt->mantissaBits == 10 && fmt->flags.bits.sign == 0) { + if (exponent & ~(unsigned int)0x3F) + exponent = 0x3F; + if (mantissa & ~(unsigned int)0x3FF) + mantissa = 0x3FF; + } else if (fmt->exponentaBits == 6 && fmt->mantissaBits == 12 && fmt->flags.bits.sign == 1) { + if (exponent & ~(unsigned int)0x3F) + exponent = 0x3F; + if (mantissa & ~(unsigned int)0xFFF) + mantissa = 0xFFF; + } else if (fmt->exponentaBits == 5 && fmt->mantissaBits == 10 && fmt->flags.bits.sign == 1) { + if (exponent & ~(unsigned int)0x1F) + exponent = 0x1F; + if (mantissa & ~(unsigned int)0x3FF) + mantissa = 0x3FF; + } else + return false; + + for (i = 0; i < fmt->mantissaBits; i++) { + mask = 1 << i; + + if (mantissa & mask) + value |= mask; + } + for (j = 0; j < fmt->exponentaBits; j++) { + mask = 1 << j; + + if (exponent & mask) + value |= mask << i; + } + + if (bNegative == true && fmt->flags.bits.sign == 1) + value |= 1 << (i + j); + + *pvalue = (uint16_t)value; + + return true; +} + +bool vpe_convert_from_float_to_custom_float( + double value, const struct vpe_custom_float_format2 *fmt, uint16_t *pvalue) +{ + bool isNegative; + unsigned int exponent; + unsigned int mantissa; + bool ret = false; + + VPE_ASSERT( + (fmt->flags.bits.sign == 1) && (fmt->mantissaBits == 10) && (fmt->exponentaBits == 5)); + + if (!build_custom_float(value, fmt, &isNegative, &exponent, &mantissa)) + goto release; + if (!setup_custom_float(fmt, isNegative, exponent, mantissa, pvalue)) + goto release; + ret = true; +release: + return ret; +} + +static bool setup_custom_float_generic(const struct vpe_custom_float_format2 *fmt, bool bNegative, + unsigned int exponent, unsigned int mantissa, int *pvalue) +{ + unsigned int value = 0; + + int mask; + + if (fmt->exponentaBits == 6 && fmt->mantissaBits == 12 && fmt->flags.bits.sign == 0) { + if (exponent & ~0x3F) + exponent = 0x3F; + if (mantissa & ~0xFFF) + mantissa = 0xFFF; + } else if (fmt->exponentaBits == 6 && fmt->mantissaBits == 10 && fmt->flags.bits.sign == 0) { + if (exponent & ~0x3F) + exponent = 0x3F; + if (mantissa & ~0x3FF) + mantissa = 0x3FF; + + } else if (fmt->exponentaBits == 6 && fmt->mantissaBits == 12 && fmt->flags.bits.sign == 1) { + if (exponent & ~0x3F) + exponent = 0x3F; + if (mantissa & ~0xFFF) + mantissa = 0xFFF; + + } else + return false; + + unsigned int i; + unsigned int j; + + for (i = 0; i < fmt->mantissaBits; i++) { + mask = 1 << i; + + if (mantissa & mask) + value |= mask; + } + for (j = 0; j < fmt->exponentaBits; j++) { + mask = 1 << j; + + if (exponent & mask) + value |= mask << i; + } + + if (bNegative == true && fmt->flags.bits.sign == 1) + value |= 1 << (i + j); + + *pvalue = value; + + return true; +} + +bool vpe_convert_to_custom_float_generic( + double value, const struct vpe_custom_float_format2 *fmt, int *pvalue) +{ + bool isNegative; + unsigned int exponent; + unsigned int mantissa; + + bool ret = false; + + if (!build_custom_float(value, fmt, &isNegative, &exponent, &mantissa)) + goto release; + if (!setup_custom_float_generic(fmt, isNegative, exponent, mantissa, pvalue)) + goto release; + ret = true; +release: + return ret; +} + +bool vpe_convert_to_custom_float_ex_generic(double value, + const struct vpe_custom_float_format2 *fmt, struct vpe_custom_float_value2 *pvalue) +{ + bool ret = false; + + if (!build_custom_float(value, fmt, &pvalue->isNegative, &pvalue->exponenta, &pvalue->mantissa)) + goto release; + if (!setup_custom_float_generic( + fmt, pvalue->isNegative, pvalue->exponenta, pvalue->mantissa, &pvalue->value)) + goto release; + + ret = true; +release: + return ret; +} + +bool vpe_from_1_6_12_to_double( + bool bIsNegative, unsigned int E, unsigned int F, double *DoubleFloat) +{ + double ret = 0; + + double M, F1, A, B, C, D2, e12; + + A = 2.0; + B = 31.0; + C = 1.0; + D2 = -30.0; + e12 = pow(2, 12); + + M = F / e12; + + if (bIsNegative == false) + F1 = 1.0; + else + F1 = -1.0; + + if (E > 0 && E < 63) + ret = F1 * (C + M) * pow(A, E - B); + else if (E == 0 && F != 0) + ret = F1 * M * pow(A, D2); + else if (E == 0 && F == 0 && bIsNegative == true) + ret = -0; + else if (E == 0 && F == 0 && bIsNegative == false) + ret = 0; + else if (E == 63 && F != 0) + return false; // -1; /* Not a number*/ + else if (E == 63 && F == 0 && bIsNegative == true) + return false; //-2; /* -Infinity*/ + else if (E == 63 && F == 0 && bIsNegative == false) + return false; // -3; /* Infinity */ + + *DoubleFloat = ret; + + return true; +} + +bool vpe_convert_from_float_to_fp16(double value, uint16_t *pvalue) +{ + struct vpe_custom_float_format2 fmt; + + fmt.flags.Uint = 0; + fmt.flags.bits.sign = 1; + fmt.mantissaBits = 10; + fmt.exponentaBits = 5; + + return vpe_convert_from_float_to_custom_float(value, &fmt, pvalue); +} diff --git a/src/amd/vpelib/src/utils/fixpt31_32.c b/src/amd/vpelib/src/utils/fixpt31_32.c new file mode 100644 index 00000000000..18dca6041ae --- /dev/null +++ b/src/amd/vpelib/src/utils/fixpt31_32.c @@ -0,0 +1,429 @@ +/* Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include "fixed31_32.h" +#include "calc_u64.h" + +static inline unsigned long long abs_i64(long long arg) +{ + if (arg > 0) + return (unsigned long long)arg; + else + return (unsigned long long)(-arg); +} + +/* + * @brief + * result = dividend / divisor + * *remainder = dividend % divisor + */ +static inline unsigned long long complete_integer_division_u64( + unsigned long long dividend, unsigned long long divisor, unsigned long long *remainder) +{ + unsigned long long result; + + VPE_ASSERT(divisor); + + result = div64_u64_rem(dividend, divisor, (uint64_t *)remainder); + + return result; +} + +#define FRACTIONAL_PART_MASK ((1ULL << FIXED31_32_BITS_PER_FRACTIONAL_PART) - 1) + +#define GET_INTEGER_PART(x) ((x) >> FIXED31_32_BITS_PER_FRACTIONAL_PART) + +#define GET_FRACTIONAL_PART(x) (FRACTIONAL_PART_MASK & (x)) + +struct fixed31_32 vpe_fixpt_from_fraction(long long numerator, long long denominator) +{ + struct fixed31_32 res; + + bool arg1_negative = numerator < 0; + bool arg2_negative = denominator < 0; + + unsigned long long arg1_value = (unsigned long long)(arg1_negative ? -numerator : numerator); + unsigned long long arg2_value = + (unsigned long long)(arg2_negative ? -denominator : denominator); + + unsigned long long remainder; + + /* determine integer part */ + + unsigned long long res_value = + complete_integer_division_u64(arg1_value, arg2_value, &remainder); + + VPE_ASSERT(res_value <= LONG_MAX); + + /* determine fractional part */ + { + unsigned int i = FIXED31_32_BITS_PER_FRACTIONAL_PART; + + do { + remainder <<= 1; + + res_value <<= 1; + + if (remainder >= arg2_value) { + res_value |= 1; + remainder -= arg2_value; + } + } while (--i != 0); + } + + /* round up LSB */ + { + unsigned long long summand = (remainder << 1) >= arg2_value; + + VPE_ASSERT(res_value <= LLONG_MAX - summand); + + res_value += summand; + } + + res.value = (long long)res_value; + + if (arg1_negative ^ arg2_negative) + res.value = -res.value; + + return res; +} + +struct fixed31_32 vpe_fixpt_mul(struct fixed31_32 arg1, struct fixed31_32 arg2) +{ + struct fixed31_32 res; + + bool arg1_negative = arg1.value < 0; + bool arg2_negative = arg2.value < 0; + + unsigned long long arg1_value = (unsigned long long)(arg1_negative ? -arg1.value : arg1.value); + unsigned long long arg2_value = (unsigned long long)(arg2_negative ? -arg2.value : arg2.value); + + unsigned long long arg1_int = GET_INTEGER_PART(arg1_value); + unsigned long long arg2_int = GET_INTEGER_PART(arg2_value); + + unsigned long long arg1_fra = GET_FRACTIONAL_PART(arg1_value); + unsigned long long arg2_fra = GET_FRACTIONAL_PART(arg2_value); + + unsigned long long tmp; + + res.value = (long long)(arg1_int * arg2_int); + + VPE_ASSERT(res.value <= LONG_MAX); + + res.value <<= FIXED31_32_BITS_PER_FRACTIONAL_PART; + + tmp = arg1_int * arg2_fra; + + VPE_ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value)); + + res.value += tmp; + + tmp = arg2_int * arg1_fra; + + VPE_ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value)); + + res.value += tmp; + + tmp = arg1_fra * arg2_fra; + + tmp = (tmp >> FIXED31_32_BITS_PER_FRACTIONAL_PART) + + (tmp >= (unsigned long long)vpe_fixpt_half.value); + + VPE_ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value)); + + res.value += tmp; + + if (arg1_negative ^ arg2_negative) + res.value = -res.value; + + return res; +} + +struct fixed31_32 vpe_fixpt_sqr(struct fixed31_32 arg) +{ + struct fixed31_32 res; + + unsigned long long arg_value = abs_i64(arg.value); + + unsigned long long arg_int = GET_INTEGER_PART(arg_value); + + unsigned long long arg_fra = GET_FRACTIONAL_PART(arg_value); + + unsigned long long tmp; + + res.value = (long long)(arg_int * arg_int); + + VPE_ASSERT(res.value <= LONG_MAX); + + res.value <<= FIXED31_32_BITS_PER_FRACTIONAL_PART; + + tmp = arg_int * arg_fra; + + VPE_ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value)); + + res.value += tmp; + + VPE_ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value)); + + res.value += tmp; + + tmp = arg_fra * arg_fra; + + tmp = (tmp >> FIXED31_32_BITS_PER_FRACTIONAL_PART) + + (tmp >= (unsigned long long)vpe_fixpt_half.value); + + VPE_ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value)); + + res.value += tmp; + + return res; +} + +struct fixed31_32 vpe_fixpt_recip(struct fixed31_32 arg) +{ + /* + * @note + * Good idea to use Newton's method + */ + + VPE_ASSERT(arg.value); + + return vpe_fixpt_from_fraction(vpe_fixpt_one.value, arg.value); +} + +struct fixed31_32 vpe_fixpt_sinc(struct fixed31_32 arg) +{ + struct fixed31_32 square; + + struct fixed31_32 res = vpe_fixpt_one; + + int n = 27; + + struct fixed31_32 arg_norm = arg; + + if (vpe_fixpt_le(vpe_fixpt_two_pi, vpe_fixpt_abs(arg))) { + arg_norm = + vpe_fixpt_sub(arg_norm, vpe_fixpt_mul_int(vpe_fixpt_two_pi, + (int)div64_s64(arg_norm.value, vpe_fixpt_two_pi.value))); + } + + square = vpe_fixpt_sqr(arg_norm); + + do { + res = vpe_fixpt_sub( + vpe_fixpt_one, vpe_fixpt_div_int(vpe_fixpt_mul(square, res), n * (n - 1))); + + n -= 2; + } while (n > 2); + + if (arg.value != arg_norm.value) + res = vpe_fixpt_div(vpe_fixpt_mul(res, arg_norm), arg); + + return res; +} + +struct fixed31_32 vpe_fixpt_sin(struct fixed31_32 arg) +{ + return vpe_fixpt_mul(arg, vpe_fixpt_sinc(arg)); +} + +struct fixed31_32 vpe_fixpt_cos(struct fixed31_32 arg) +{ + /* TODO implement argument normalization */ + + const struct fixed31_32 square = vpe_fixpt_sqr(arg); + + struct fixed31_32 res = vpe_fixpt_one; + + int n = 26; + + do { + res = vpe_fixpt_sub( + vpe_fixpt_one, vpe_fixpt_div_int(vpe_fixpt_mul(square, res), n * (n - 1))); + + n -= 2; + } while (n != 0); + + return res; +} + +/* + * @brief + * result = exp(arg), + * where abs(arg) < 1 + * + * Calculated as Taylor series. + */ +static struct fixed31_32 fixed31_32_exp_from_taylor_series(struct fixed31_32 arg) +{ + unsigned int n = 9; + + struct fixed31_32 res = vpe_fixpt_from_fraction(n + 2, n + 1); + /* TODO find correct res */ + + VPE_ASSERT(vpe_fixpt_lt(arg, vpe_fixpt_one)); + + do + res = vpe_fixpt_add(vpe_fixpt_one, vpe_fixpt_div_int(vpe_fixpt_mul(arg, res), n)); + while (--n != 1); + + return vpe_fixpt_add(vpe_fixpt_one, vpe_fixpt_mul(arg, res)); +} + +struct fixed31_32 vpe_fixpt_exp(struct fixed31_32 arg) +{ + /* + * @brief + * Main equation is: + * exp(x) = exp(r + m * ln(2)) = (1 << m) * exp(r), + * where m = round(x / ln(2)), r = x - m * ln(2) + */ + + if (vpe_fixpt_le(vpe_fixpt_ln2_div_2, vpe_fixpt_abs(arg))) { + int m = vpe_fixpt_round(vpe_fixpt_div(arg, vpe_fixpt_ln2)); + + struct fixed31_32 r = vpe_fixpt_sub(arg, vpe_fixpt_mul_int(vpe_fixpt_ln2, m)); + + VPE_ASSERT(m != 0); + + VPE_ASSERT(vpe_fixpt_lt(vpe_fixpt_abs(r), vpe_fixpt_one)); + + if (m > 0) + return vpe_fixpt_shl(fixed31_32_exp_from_taylor_series(r), (unsigned char)m); + else + return vpe_fixpt_div_int(fixed31_32_exp_from_taylor_series(r), 1LL << -m); + } else if (arg.value != 0) + return fixed31_32_exp_from_taylor_series(arg); + else + return vpe_fixpt_one; +} + +struct fixed31_32 vpe_fixpt_log(struct fixed31_32 arg) +{ + struct fixed31_32 res = vpe_fixpt_neg(vpe_fixpt_one); + /* TODO improve 1st estimation */ + + struct fixed31_32 error; + + VPE_ASSERT(arg.value > 0); + /* TODO if arg is negative, return NaN */ + /* TODO if arg is zero, return -INF */ + + do { + struct fixed31_32 res1 = vpe_fixpt_add( + vpe_fixpt_sub(res, vpe_fixpt_one), vpe_fixpt_div(arg, vpe_fixpt_exp(res))); + + error = vpe_fixpt_sub(res, res1); + + res = res1; + /* TODO determine max_allowed_error based on quality of exp() */ + } while (abs_i64(error.value) > 100ULL); + + return res; +} + +/* this function is a generic helper to translate fixed point value to + * specified integer format that will consist of integer_bits integer part and + * fractional_bits fractional part. For example it is used in + * vpe_fixpt_u2d19 to receive 2 bits integer part and 19 bits fractional + * part in 32 bits. It is used in hw programming (scaler) + */ + +static inline unsigned int ux_dy( + long long value, unsigned int integer_bits, unsigned int fractional_bits) +{ + /* 1. create mask of integer part */ + unsigned int result = (1 << integer_bits) - 1; + /* 2. mask out fractional part */ + unsigned int fractional_part = FRACTIONAL_PART_MASK & (unsigned long long)value; + /* 3. shrink fixed point integer part to be of integer_bits width*/ + result &= GET_INTEGER_PART(value); + /* 4. make space for fractional part to be filled in after integer */ + result <<= fractional_bits; + /* 5. shrink fixed point fractional part to of fractional_bits width*/ + fractional_part >>= FIXED31_32_BITS_PER_FRACTIONAL_PART - fractional_bits; + /* 6. merge the result */ + return result | fractional_part; +} + +static inline unsigned int clamp_ux_dy(long long value, unsigned int integer_bits, + unsigned int fractional_bits, unsigned int min_clamp) +{ + unsigned int truncated_val = ux_dy(value, integer_bits, fractional_bits); + + if (value >= (1LL << (integer_bits + FIXED31_32_BITS_PER_FRACTIONAL_PART))) + return (1 << (integer_bits + fractional_bits)) - 1; + else if (truncated_val > min_clamp) + return truncated_val; + else + return min_clamp; +} + +unsigned int vpe_fixpt_u4d19(struct fixed31_32 arg) +{ + return ux_dy(arg.value, 4, 19); +} + +unsigned int vpe_fixpt_u3d19(struct fixed31_32 arg) +{ + return ux_dy(arg.value, 3, 19); +} + +unsigned int vpe_fixpt_u2d19(struct fixed31_32 arg) +{ + return ux_dy(arg.value, 2, 19); +} + +unsigned int vpe_fixpt_u0d19(struct fixed31_32 arg) +{ + return ux_dy(arg.value, 0, 19); +} + +unsigned int vpe_fixpt_clamp_u0d14(struct fixed31_32 arg) +{ + return clamp_ux_dy(arg.value, 0, 14, 1); +} + +unsigned int vpe_fixpt_clamp_u0d10(struct fixed31_32 arg) +{ + return clamp_ux_dy(arg.value, 0, 10, 1); +} + +int vpe_fixpt_s4d19(struct fixed31_32 arg) +{ + if (arg.value < 0) + return -(int)ux_dy(vpe_fixpt_abs(arg).value, 4, 19); + else + return (int)ux_dy(arg.value, 4, 19); +} + +unsigned int vpe_to_fixed_point( + unsigned int decimalBits, double value, unsigned int mask, double d_pix) +{ + unsigned int d_i; + + d_i = (int)((value * d_pix) + 0.5); + d_i = d_i & mask; + return d_i; +} diff --git a/src/amd/vpelib/src/utils/inc/calc_u64.h b/src/amd/vpelib/src/utils/inc/calc_u64.h new file mode 100644 index 00000000000..82ce921c985 --- /dev/null +++ b/src/amd/vpelib/src/utils/inc/calc_u64.h @@ -0,0 +1,65 @@ +/* Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#pragma once + +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +static inline uint64_t div_u64_rem(uint64_t dividend, uint32_t divisor, uint32_t *remainder) +{ + *remainder = dividend % divisor; + return dividend / divisor; +} + +static inline uint64_t div_u64(uint64_t dividend, uint32_t divisor) +{ + return dividend / divisor; +} + +static inline uint64_t div64_u64(uint64_t dividend, uint64_t divisor) +{ + return dividend / divisor; +} + +static inline uint64_t div64_u64_rem(uint64_t dividend, uint64_t divisor, uint64_t *remainder) +{ + *remainder = dividend % divisor; + return dividend / divisor; +} + +static inline int64_t div64_s64(int64_t dividend, int64_t divisor) +{ + return dividend / divisor; +} + +#ifdef __cplusplus +} +#endif diff --git a/src/amd/vpelib/src/utils/inc/conversion.h b/src/amd/vpelib/src/utils/inc/conversion.h new file mode 100644 index 00000000000..cad23c7ce5f --- /dev/null +++ b/src/amd/vpelib/src/utils/inc/conversion.h @@ -0,0 +1,43 @@ +/* Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#pragma once + +#include "fixed31_32.h" + +#ifdef __cplusplus +extern "C" { +#endif + +uint16_t conv_fixed_point_to_int_frac( + struct fixed31_32 arg, uint8_t integer_bits, uint8_t fractional_bits); + +void conv_convert_float_matrix( + uint16_t *matrix, const struct fixed31_32 *flt, uint32_t buffer_size); + +struct fixed31_32 vpe_convfix31_32(int16_t inval); + +#ifdef __cplusplus +} +#endif diff --git a/src/amd/vpelib/src/utils/inc/custom_float.h b/src/amd/vpelib/src/utils/inc/custom_float.h new file mode 100644 index 00000000000..044eba60429 --- /dev/null +++ b/src/amd/vpelib/src/utils/inc/custom_float.h @@ -0,0 +1,46 @@ +/* Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#pragma once + +#include +#include +#include "fixed31_32.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct custom_float_format { + uint32_t mantissa_bits; + uint32_t exponenta_bits; + bool sign; +}; + +bool vpe_convert_to_custom_float_format( + struct fixed31_32 value, const struct custom_float_format *format, uint32_t *result); + +#ifdef __cplusplus +} +#endif diff --git a/src/amd/vpelib/src/utils/inc/custom_fp16.h b/src/amd/vpelib/src/utils/inc/custom_fp16.h new file mode 100644 index 00000000000..697c6c973ba --- /dev/null +++ b/src/amd/vpelib/src/utils/inc/custom_fp16.h @@ -0,0 +1,59 @@ +/* Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include +#include + +union custom_float_format_flags2 { + unsigned int Uint; + struct { + unsigned int sign : 1; + unsigned int reserved31 : 31; + } bits; +}; +struct vpe_custom_float_format2 { + unsigned int mantissaBits; + unsigned int exponentaBits; + union custom_float_format_flags2 flags; +}; + +struct vpe_custom_float_value2 { + unsigned int mantissa; + unsigned int exponenta; + int value; + bool isNegative; +}; + +bool vpe_convert_from_float_to_custom_float( + double value, const struct vpe_custom_float_format2 *fmt, uint16_t *pvalue); +bool vpe_convert_from_float_to_fp16(double value, uint16_t *pvalue); + +bool vpe_convert_to_custom_float_generic( + double value, const struct vpe_custom_float_format2 *fmt, int *pvalue); + +bool vpe_convert_to_custom_float_ex_generic(double value, + const struct vpe_custom_float_format2 *fmt, struct vpe_custom_float_value2 *pvalue); + +bool vpe_from_1_6_12_to_double( + bool bIsNegative, unsigned int E, unsigned int F, double *DoubleFloat); diff --git a/src/amd/vpelib/src/utils/inc/fixed31_32.h b/src/amd/vpelib/src/utils/inc/fixed31_32.h new file mode 100644 index 00000000000..694b4993132 --- /dev/null +++ b/src/amd/vpelib/src/utils/inc/fixed31_32.h @@ -0,0 +1,548 @@ +/* Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#pragma once + +#include +#include +#include +#include +#include "vpe_assert.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef LLONG_MAX +#define LLONG_MAX 9223372036854775807ll +#endif +#ifndef LLONG_MIN +#define LLONG_MIN (-LLONG_MAX - 1ll) +#endif + +#define FIXED31_32_BITS_PER_FRACTIONAL_PART 32 +#ifndef LLONG_MIN +#define LLONG_MIN (1LL << 63) +#endif +#ifndef LLONG_MAX +#define LLONG_MAX (-1LL >> 1) +#endif + +#ifndef ASSERT +#define ASSERT assert +#endif + +/* + * @brief + * Arithmetic operations on real numbers + * represented as fixed-point numbers. + * There are: 1 bit for sign, + * 31 bit for integer part, + * 32 bits for fractional part. + * + * @note + * Currently, overflows and underflows are asserted; + * no special result returned. + */ + +struct fixed31_32 { + long long value; +}; + +/* + * @brief + * Useful constants + */ + +static const struct fixed31_32 vpe_fixpt_zero = {0}; +static const struct fixed31_32 vpe_fixpt_epsilon = {1LL}; +static const struct fixed31_32 vpe_fixpt_half = {0x80000000LL}; +static const struct fixed31_32 vpe_fixpt_one = {0x100000000LL}; + +static const struct fixed31_32 vpe_fixpt_pi = {13493037705LL}; +static const struct fixed31_32 vpe_fixpt_two_pi = {26986075409LL}; +static const struct fixed31_32 vpe_fixpt_e = {11674931555LL}; +static const struct fixed31_32 vpe_fixpt_ln2 = {2977044471LL}; +static const struct fixed31_32 vpe_fixpt_ln2_div_2 = {1488522236LL}; + +/* + * @brief + * Initialization routines + */ + +/* + * @brief + * result = numerator / denominator + */ +struct fixed31_32 vpe_fixpt_from_fraction(long long numerator, long long denominator); + +/* + * @brief + * result = arg + */ +static inline struct fixed31_32 vpe_fixpt_from_int(long long arg) +{ + struct fixed31_32 res; + + res.value = (long long)arg << FIXED31_32_BITS_PER_FRACTIONAL_PART; + + return res; +} + +/* + * @brief + * Unary operators + */ + +/* + * @brief + * result = -arg + */ +static inline struct fixed31_32 vpe_fixpt_neg(struct fixed31_32 arg) +{ + struct fixed31_32 res; + + res.value = -arg.value; + + return res; +} + +/* + * @brief + * result = abs(arg) := (arg >= 0) ? arg : -arg + */ +static inline struct fixed31_32 vpe_fixpt_abs(struct fixed31_32 arg) +{ + if (arg.value < 0) + return vpe_fixpt_neg(arg); + else + return arg; +} + +/* + * @brief + * Binary relational operators + */ + +/* + * @brief + * result = arg1 < arg2 + */ +static inline bool vpe_fixpt_lt(struct fixed31_32 arg1, struct fixed31_32 arg2) +{ + return arg1.value < arg2.value; +} + +/* + * @brief + * result = arg1 <= arg2 + */ +static inline bool vpe_fixpt_le(struct fixed31_32 arg1, struct fixed31_32 arg2) +{ + return arg1.value <= arg2.value; +} + +/* + * @brief + * result = arg1 == arg2 + */ +static inline bool vpe_fixpt_eq(struct fixed31_32 arg1, struct fixed31_32 arg2) +{ + return arg1.value == arg2.value; +} + +/* + * @brief + * result = min(arg1, arg2) := (arg1 <= arg2) ? arg1 : arg2 + */ +static inline struct fixed31_32 vpe_fixpt_min(struct fixed31_32 arg1, struct fixed31_32 arg2) +{ + if (arg1.value <= arg2.value) + return arg1; + else + return arg2; +} + +/* + * @brief + * result = max(arg1, arg2) := (arg1 <= arg2) ? arg2 : arg1 + */ +static inline struct fixed31_32 vpe_fixpt_max(struct fixed31_32 arg1, struct fixed31_32 arg2) +{ + if (arg1.value <= arg2.value) + return arg2; + else + return arg1; +} + +/* + * @brief + * | min_value, when arg <= min_value + * result = | arg, when min_value < arg < max_value + * | max_value, when arg >= max_value + */ +static inline struct fixed31_32 vpe_fixpt_clamp( + struct fixed31_32 arg, struct fixed31_32 min_value, struct fixed31_32 max_value) +{ + if (vpe_fixpt_le(arg, min_value)) + return min_value; + else if (vpe_fixpt_le(max_value, arg)) + return max_value; + else + return arg; +} + +/* + * @brief + * Binary shift operators + */ + +/* + * @brief + * result = arg << shift + */ +static inline struct fixed31_32 vpe_fixpt_shl(struct fixed31_32 arg, unsigned char shift) +{ + VPE_ASSERT(((arg.value >= 0) && (arg.value <= LLONG_MAX >> shift)) || + ((arg.value < 0) && (arg.value >= ~(LLONG_MAX >> shift)))); + + arg.value = arg.value << shift; + + return arg; +} + +/* + * @brief + * result = arg >> shift + */ +static inline struct fixed31_32 vpe_fixpt_shr(struct fixed31_32 arg, unsigned char shift) +{ + bool negative = arg.value < 0; + + if (negative) + arg.value = -arg.value; + arg.value = arg.value >> shift; + if (negative) + arg.value = -arg.value; + return arg; +} + +/* + * @brief + * Binary additive operators + */ + +/* + * @brief + * result = arg1 + arg2 + */ +static inline struct fixed31_32 vpe_fixpt_add(struct fixed31_32 arg1, struct fixed31_32 arg2) +{ + struct fixed31_32 res; + + VPE_ASSERT(((arg1.value >= 0) && (LLONG_MAX - arg1.value >= arg2.value)) || + ((arg1.value < 0) && (LLONG_MIN - arg1.value <= arg2.value))); + + res.value = arg1.value + arg2.value; + + return res; +} + +/* + * @brief + * result = arg1 + arg2 + */ +static inline struct fixed31_32 vpe_fixpt_add_int(struct fixed31_32 arg1, int arg2) +{ + return vpe_fixpt_add(arg1, vpe_fixpt_from_int(arg2)); +} + +/* + * @brief + * result = arg1 - arg2 + */ +static inline struct fixed31_32 vpe_fixpt_sub(struct fixed31_32 arg1, struct fixed31_32 arg2) +{ + struct fixed31_32 res; + + VPE_ASSERT(((arg2.value >= 0) && (LLONG_MIN + arg2.value <= arg1.value)) || + ((arg2.value < 0) && (LLONG_MAX + arg2.value >= arg1.value))); + + res.value = arg1.value - arg2.value; + + return res; +} + +/* + * @brief + * result = arg1 - arg2 + */ +static inline struct fixed31_32 vpe_fixpt_sub_int(struct fixed31_32 arg1, int arg2) +{ + return vpe_fixpt_sub(arg1, vpe_fixpt_from_int(arg2)); +} + +/* + * @brief + * Binary multiplicative operators + */ + +/* + * @brief + * result = arg1 * arg2 + */ +struct fixed31_32 vpe_fixpt_mul(struct fixed31_32 arg1, struct fixed31_32 arg2); + +/* + * @brief + * result = arg1 * arg2 + */ +static inline struct fixed31_32 vpe_fixpt_mul_int(struct fixed31_32 arg1, int arg2) +{ + return vpe_fixpt_mul(arg1, vpe_fixpt_from_int(arg2)); +} + +/* + * @brief + * result = square(arg) := arg * arg + */ +struct fixed31_32 vpe_fixpt_sqr(struct fixed31_32 arg); + +/* + * @brief + * result = arg1 / arg2 + */ +static inline struct fixed31_32 vpe_fixpt_div_int(struct fixed31_32 arg1, long long arg2) +{ + return vpe_fixpt_from_fraction(arg1.value, vpe_fixpt_from_int(arg2).value); +} + +/* + * @brief + * result = arg1 / arg2 + */ +static inline struct fixed31_32 vpe_fixpt_div(struct fixed31_32 arg1, struct fixed31_32 arg2) +{ + return vpe_fixpt_from_fraction(arg1.value, arg2.value); +} + +/* + * @brief + * Reciprocal function + */ + +/* + * @brief + * result = reciprocal(arg) := 1 / arg + * + * @note + * No special actions taken in case argument is zero. + */ +struct fixed31_32 vpe_fixpt_recip(struct fixed31_32 arg); + +/* + * @brief + * Trigonometric functions + */ + +/* + * @brief + * result = sinc(arg) := sin(arg) / arg + * + * @note + * Argument specified in radians, + * internally it's normalized to [-2pi...2pi] range. + */ +struct fixed31_32 vpe_fixpt_sinc(struct fixed31_32 arg); + +/* + * @brief + * result = sin(arg) + * + * @note + * Argument specified in radians, + * internally it's normalized to [-2pi...2pi] range. + */ +struct fixed31_32 vpe_fixpt_sin(struct fixed31_32 arg); + +/* + * @brief + * result = cos(arg) + * + * @note + * Argument specified in radians + * and should be in [-2pi...2pi] range - + * passing arguments outside that range + * will cause incorrect result! + */ +struct fixed31_32 vpe_fixpt_cos(struct fixed31_32 arg); + +/* + * @brief + * Transcendent functions + */ + +/* + * @brief + * result = exp(arg) + * + * @note + * Currently, function is verified for abs(arg) <= 1. + */ +struct fixed31_32 vpe_fixpt_exp(struct fixed31_32 arg); + +/* + * @brief + * result = log(arg) + * + * @note + * Currently, abs(arg) should be less than 1. + * No normalization is done. + * Currently, no special actions taken + * in case of invalid argument(s). Take care! + */ +struct fixed31_32 vpe_fixpt_log(struct fixed31_32 arg); + +/* + * @brief + * Power function + */ + +/* + * @brief + * result = pow(arg1, arg2) + * + * @note + * Currently, abs(arg1) should be less than 1. Take care! + */ +static inline struct fixed31_32 vpe_fixpt_pow(struct fixed31_32 arg1, struct fixed31_32 arg2) +{ + if (arg1.value == 0) + return arg2.value == 0 ? vpe_fixpt_one : vpe_fixpt_zero; + + return vpe_fixpt_exp(vpe_fixpt_mul(vpe_fixpt_log(arg1), arg2)); +} + +/* + * @brief + * Rounding functions + */ + +/* + * @brief + * result = floor(arg) := greatest integer lower than or equal to arg + */ +static inline int vpe_fixpt_floor(struct fixed31_32 arg) +{ + unsigned long long arg_value = (unsigned long long)(arg.value > 0 ? arg.value : -arg.value); + + if (arg.value >= 0) + return (int)(arg_value >> FIXED31_32_BITS_PER_FRACTIONAL_PART); + else + return -(int)(arg_value >> FIXED31_32_BITS_PER_FRACTIONAL_PART); +} + +/* + * @brief + * result = round(arg) := integer nearest to arg + */ +static inline int vpe_fixpt_round(struct fixed31_32 arg) +{ + unsigned long long arg_value = (unsigned long long)(arg.value > 0 ? arg.value : -arg.value); + + const long long summand = vpe_fixpt_half.value; + + VPE_ASSERT(LLONG_MAX - (long long)arg_value >= summand); + + arg_value += (unsigned long long)summand; + + if (arg.value >= 0) + return (int)(arg_value >> FIXED31_32_BITS_PER_FRACTIONAL_PART); + else + return -(int)(arg_value >> FIXED31_32_BITS_PER_FRACTIONAL_PART); +} + +/* + * @brief + * result = ceil(arg) := lowest integer greater than or equal to arg + */ +static inline int vpe_fixpt_ceil(struct fixed31_32 arg) +{ + unsigned long long arg_value = (unsigned long long)(arg.value > 0 ? arg.value : -arg.value); + + const long long summand = vpe_fixpt_one.value - vpe_fixpt_epsilon.value; + + VPE_ASSERT(LLONG_MAX - (long long)arg_value >= summand); + + arg_value += (unsigned long long)summand; + + if (arg.value >= 0) + return (int)(arg_value >> FIXED31_32_BITS_PER_FRACTIONAL_PART); + else + return -(int)(arg_value >> FIXED31_32_BITS_PER_FRACTIONAL_PART); +} + +/* the following two function are used in scaler hw programming to convert fixed + * point value to format 2 bits from integer part and 19 bits from fractional + * part. The same applies for u0d19, 0 bits from integer part and 19 bits from + * fractional + */ + +unsigned int vpe_fixpt_u4d19(struct fixed31_32 arg); + +unsigned int vpe_fixpt_u3d19(struct fixed31_32 arg); + +unsigned int vpe_fixpt_u2d19(struct fixed31_32 arg); + +unsigned int vpe_fixpt_u0d19(struct fixed31_32 arg); + +unsigned int vpe_fixpt_clamp_u0d14(struct fixed31_32 arg); + +unsigned int vpe_fixpt_clamp_u0d10(struct fixed31_32 arg); + +int vpe_fixpt_s4d19(struct fixed31_32 arg); + +static inline struct fixed31_32 vpe_fixpt_truncate(struct fixed31_32 arg, unsigned int frac_bits) +{ + bool negative = arg.value < 0; + + if (frac_bits >= FIXED31_32_BITS_PER_FRACTIONAL_PART) { + VPE_ASSERT(frac_bits == FIXED31_32_BITS_PER_FRACTIONAL_PART); + return arg; + } + + if (negative) + arg.value = -arg.value; + arg.value &= (~0ULL) << (FIXED31_32_BITS_PER_FRACTIONAL_PART - frac_bits); + if (negative) + arg.value = -arg.value; + return arg; +} + +unsigned int vpe_to_fixed_point( + unsigned int decimalBits, double value, unsigned int mask, double d_pix); + +#ifdef __cplusplus +} +#endif diff --git a/src/gallium/drivers/radeonsi/meson.build b/src/gallium/drivers/radeonsi/meson.build index f5bafbbb7fd..f9b3dc45861 100644 --- a/src/gallium/drivers/radeonsi/meson.build +++ b/src/gallium/drivers/radeonsi/meson.build @@ -165,8 +165,8 @@ libradeonsi = static_library( driver_radeonsi = declare_dependency( compile_args : '-DGALLIUM_RADEONSI', - link_with : radeonsi_gfx_libs + amd_common_libs + [ - libradeonsi, libradeonwinsys, libamdgpuwinsys, libgalliumvl + link_with : radeonsi_gfx_libs + [ + libradeonsi, libradeonwinsys, libamdgpuwinsys, libamd_common, libamd_common_llvm, libgalliumvl, libvpe ], dependencies : idep_nir, )