diff --git a/src/freedreno/registers/adreno/adreno_pm4.xml b/src/freedreno/registers/adreno/adreno_pm4.xml
index e59a84155a5..75571272ce4 100644
--- a/src/freedreno/registers/adreno/adreno_pm4.xml
+++ b/src/freedreno/registers/adreno/adreno_pm4.xml
@@ -8,6 +8,10 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
+
+ Flushes dirty data from UCHE, and also writes a GPU timestamp to
+ the address if one is provided.
+
@@ -24,9 +28,20 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
+
+ If A6XX_RB_SAMPLE_COUNT_CONTROL.copy is true, writes OQ Z passed
+ sample counts to RB_SAMPLE_COUNT_ADDR. This writes to main
+ memory, skipping UCHE.
+
+
+
+ Writes the GPU timestamp to the address that follows, once RB
+ access and flushes are complete.
+
+
@@ -42,12 +57,44 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
+
+
+ Invalidates depth attachment data from the CCU. We assume this
+ happens in the last stage.
+
+
+
+ Invalidates color attachment data from the CCU. We assume this
+ happens in the last stage.
+
+
+
+ Flushes the small cache used by CP_EVENT_WRITE::BLIT (which,
+ along with its registers, would be better named RESOLVE).
+
+
+
+ Flushes depth attachment data from the CCU. We assume this
+ happens in the last stage.
+
+
+
+ Flushes color attachment data from the CCU. We assume this
+ happens in the last stage.
+
+
+
+ 2D blit to resolve GMEM to system memory (skipping CCU) at the
+ end of a render pass. Compare to CP_BLIT's BLIT_OP_SCALE for
+ more general blitting.
+
+
Clears based on GRAS_LRZ_CNTL configuration, could clear
fast-clear buffer or LRZ direction.
@@ -60,6 +107,7 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
Clear of direction means setting the direction to CUR_DIR_UNSET.
+
@@ -69,7 +117,11 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
+
+ Invalidates UCHE.
+
+
@@ -205,7 +257,10 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
indirect buffer dispatch. same as IB, but init is pipelined
- wait for the IDLE state of the engine
+
+ Waits for the IDLE state of the engine before further drawing.
+ This is pipelined, so the CP may continue.
+
wait until a register or memory location is a specific value
@@ -435,6 +490,12 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
+
+
+ General purpose 2D blit engine for image transfers and mipmap
+ generation. Reads through UCHE, writes through the CCU cache in
+ the PS stage.
+