From 16f081bf2a88f7d2b82bfee88da063936c139235 Mon Sep 17 00:00:00 2001 From: Alyssa Rosenzweig Date: Fri, 19 May 2023 18:12:22 -0400 Subject: [PATCH] ail: Page-align layers for writable images This appears to be necessary for PBE writes. Signed-off-by: Alyssa Rosenzweig Part-of: --- src/asahi/layout/layout.c | 10 ++++++++++ src/asahi/layout/layout.h | 5 +++++ 2 files changed, 15 insertions(+) diff --git a/src/asahi/layout/layout.c b/src/asahi/layout/layout.c index 0ae7ef74ab7..1d55d7b4a98 100644 --- a/src/asahi/layout/layout.c +++ b/src/asahi/layout/layout.c @@ -164,6 +164,12 @@ ail_initialize_twiddled(struct ail_layout *layout) !util_format_is_depth_or_stencil(layout->format)) layout->page_aligned_layers = false; + /* For writable images, we require page-aligned layers. This appears to be + * required for PBE stores. + */ + if (layout->writeable_image) + layout->page_aligned_layers = true; + if (layout->page_aligned_layers) layout->layer_stride_B = ALIGN_POT(offset_B, AIL_PAGESIZE); else @@ -235,6 +241,10 @@ ail_make_miptree(struct ail_layout *layout) assert(layout->sample_count_sa >= 1 && "Invalid sample count"); } + assert(!(layout->writeable_image && + layout->tiling == AIL_TILING_TWIDDLED_COMPRESSED) && + "Writeable images must not be compressed"); + /* Hardware strides are based on the maximum number of levels, so always * allocate them all. */ diff --git a/src/asahi/layout/layout.h b/src/asahi/layout/layout.h index 7d70a3f0313..9d7f81ae7a8 100644 --- a/src/asahi/layout/layout.h +++ b/src/asahi/layout/layout.h @@ -118,6 +118,11 @@ struct ail_layout { /* Size of entire texture */ uint32_t size_B; + + /* Must the layout support writeable images? If false, the layout MUST NOT be + * used as a writeable image (either PBE or image atomics). + */ + bool writeable_image; }; static inline uint32_t