diff --git a/src/amd/compiler/aco_ir.cpp b/src/amd/compiler/aco_ir.cpp
index 03f6931be1c..6c9e64ff43c 100644
--- a/src/amd/compiler/aco_ir.cpp
+++ b/src/amd/compiler/aco_ir.cpp
@@ -480,22 +480,23 @@ can_use_opsel(amd_gfx_level gfx_level, aco_opcode op, int idx)
 }
 
 bool
-can_write_m0(amd_gfx_level gfx_level, const aco_ptr<Instruction>& instr)
+can_write_m0(const aco_ptr<Instruction>& instr)
 {
    if (instr->isSALU())
       return true;
 
+   /* VALU can't write m0 on any GPU generations. */
    if (instr->isVALU())
-      return gfx_level >= GFX9;
+      return false;
 
    switch (instr->opcode) {
    case aco_opcode::p_parallelcopy:
    case aco_opcode::p_extract:
    case aco_opcode::p_insert:
+      /* These pseudo instructions are implemented with SALU when writing m0. */
       return true;
-   case aco_opcode::p_reload:
-      return gfx_level >= GFX9;
    default:
+      /* Assume that no other instructions can write m0. */
       return false;
    }
 }
diff --git a/src/amd/compiler/aco_ir.h b/src/amd/compiler/aco_ir.h
index a39e949847f..528e0c36f40 100644
--- a/src/amd/compiler/aco_ir.h
+++ b/src/amd/compiler/aco_ir.h
@@ -1804,7 +1804,7 @@ bool instr_is_16bit(amd_gfx_level gfx_level, aco_opcode op);
 uint8_t get_gfx11_true16_mask(aco_opcode op);
 bool can_use_SDWA(amd_gfx_level gfx_level, const aco_ptr<Instruction>& instr, bool pre_ra);
 bool can_use_DPP(const aco_ptr<Instruction>& instr, bool pre_ra, bool dpp8);
-bool can_write_m0(amd_gfx_level gfx_level, const aco_ptr<Instruction>& instr);
+bool can_write_m0(const aco_ptr<Instruction>& instr);
 /* updates "instr" and returns the old instruction (or NULL if no update was needed) */
 aco_ptr<Instruction> convert_to_SDWA(amd_gfx_level gfx_level, aco_ptr<Instruction>& instr);
 aco_ptr<Instruction> convert_to_DPP(aco_ptr<Instruction>& instr, bool dpp8);
diff --git a/src/amd/compiler/aco_register_allocation.cpp b/src/amd/compiler/aco_register_allocation.cpp
index fba6e1c012c..0b360109a08 100644
--- a/src/amd/compiler/aco_register_allocation.cpp
+++ b/src/amd/compiler/aco_register_allocation.cpp
@@ -1656,7 +1656,7 @@ get_reg(ra_ctx& ctx, RegisterFile& reg_file, Temp temp,
    }
    if (ctx.assignments[temp.id()].m0) {
       if (get_reg_specified(ctx, reg_file, temp.regClass(), instr, m0) &&
-          can_write_m0(ctx.program->gfx_level, instr))
+          can_write_m0(instr))
          return m0;
    }