From 16793c8efae35b2a80589f014fe6d0d4861fda5d Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Tue, 3 Aug 2021 13:35:25 +0200 Subject: [PATCH] ac/surface: implement CmaskAddrFromCoord in NIR on GFX10+ MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Samuel Pitoiset Reviewed-by: Marek Olšák Part-of: --- src/amd/common/ac_surface.c | 26 ++++++++++++++++++-------- src/amd/common/ac_surface.h | 1 + 2 files changed, 19 insertions(+), 8 deletions(-) diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c index 597e814431b..3bcec29292a 100644 --- a/src/amd/common/ac_surface.c +++ b/src/amd/common/ac_surface.c @@ -2910,7 +2910,8 @@ static nir_ssa_def *gfx10_nir_meta_addr_from_coord(nir_builder *b, const struct int blkSizeBias, unsigned blkStart, nir_ssa_def *meta_pitch, nir_ssa_def *meta_slice_size, nir_ssa_def *x, nir_ssa_def *y, nir_ssa_def *z, - nir_ssa_def *pipe_xor) + nir_ssa_def *pipe_xor, + nir_ssa_def **bit_position) { nir_ssa_def *zero = nir_imm_int(b, 0); nir_ssa_def *one = nir_imm_int(b, 1); @@ -2951,6 +2952,10 @@ static nir_ssa_def *gfx10_nir_meta_addr_from_coord(nir_builder *b, const struct nir_ssa_def *pipeXor = nir_iand_imm(b, nir_ishl(b, nir_iand_imm(b, pipe_xor, pipeMask), nir_imm_int(b, m_pipeInterleaveLog2)), blkMask); + if (bit_position) + *bit_position = nir_ishl(b, nir_iand(b, address, nir_imm_int(b, 1)), + nir_imm_int(b, 2)); + return nir_iadd(b, nir_iadd(b, nir_imul(b, meta_slice_size, z), nir_imul(b, blkIndex, nir_ishl(b, one, nir_imm_int(b, blkSizeLog2)))), nir_ixor(b, nir_ushr(b, address, one), pipeXor)); @@ -3036,7 +3041,7 @@ nir_ssa_def *ac_nir_dcc_addr_from_coord(nir_builder *b, const struct radeon_info return gfx10_nir_meta_addr_from_coord(b, info, equation, bpp_log2 - 8, 1, dcc_pitch, dcc_slice_size, - x, y, z, pipe_xor); + x, y, z, pipe_xor, NULL); } else { return gfx9_nir_meta_addr_from_coord(b, info, equation, dcc_pitch, dcc_height, x, y, z, @@ -3047,17 +3052,22 @@ nir_ssa_def *ac_nir_dcc_addr_from_coord(nir_builder *b, const struct radeon_info nir_ssa_def *ac_nir_cmask_addr_from_coord(nir_builder *b, const struct radeon_info *info, struct gfx9_meta_equation *equation, nir_ssa_def *cmask_pitch, nir_ssa_def *cmask_height, + nir_ssa_def *cmask_slice_size, nir_ssa_def *x, nir_ssa_def *y, nir_ssa_def *z, nir_ssa_def *pipe_xor, nir_ssa_def **bit_position) { nir_ssa_def *zero = nir_imm_int(b, 0); - assert(info->chip_class == GFX9); - - return gfx9_nir_meta_addr_from_coord(b, info, equation, cmask_pitch, - cmask_height, x, y, z, zero, - pipe_xor, bit_position); + if (info->chip_class >= GFX10) { + return gfx10_nir_meta_addr_from_coord(b, info, equation, -7, 1, + cmask_pitch, cmask_slice_size, + x, y, z, pipe_xor, bit_position); + } else { + return gfx9_nir_meta_addr_from_coord(b, info, equation, cmask_pitch, + cmask_height, x, y, z, zero, + pipe_xor, bit_position); + } } nir_ssa_def *ac_nir_htile_addr_from_coord(nir_builder *b, const struct radeon_info *info, @@ -3069,5 +3079,5 @@ nir_ssa_def *ac_nir_htile_addr_from_coord(nir_builder *b, const struct radeon_in { return gfx10_nir_meta_addr_from_coord(b, info, equation, -4, 2, htile_pitch, htile_slice_size, - x, y, z, pipe_xor); + x, y, z, pipe_xor, NULL); } diff --git a/src/amd/common/ac_surface.h b/src/amd/common/ac_surface.h index 91230fcc322..d52a62de027 100644 --- a/src/amd/common/ac_surface.h +++ b/src/amd/common/ac_surface.h @@ -480,6 +480,7 @@ nir_ssa_def *ac_nir_dcc_addr_from_coord(nir_builder *b, const struct radeon_info nir_ssa_def *ac_nir_cmask_addr_from_coord(nir_builder *b, const struct radeon_info *info, struct gfx9_meta_equation *equation, nir_ssa_def *cmask_pitch, nir_ssa_def *cmask_height, + nir_ssa_def *cmask_slice_size, nir_ssa_def *x, nir_ssa_def *y, nir_ssa_def *z, nir_ssa_def *pipe_xor, nir_ssa_def **bit_position);