From 153ff5dd8a46336abb1ed9436569b0cb1d66df5e Mon Sep 17 00:00:00 2001 From: David Rosca Date: Mon, 10 Nov 2025 11:00:43 +0100 Subject: [PATCH] radeonsi/vcn: Cleanup HEVC encode deblock params handling This should consider values from PPS and overrides from slice header if enabled. Reviewed-by: Ruijing Dong Part-of: --- src/gallium/drivers/radeonsi/radeon_vcn_enc.c | 42 +++++++++++++++---- .../drivers/radeonsi/radeon_vcn_enc_1_2.c | 4 +- 2 files changed, 35 insertions(+), 11 deletions(-) diff --git a/src/gallium/drivers/radeonsi/radeon_vcn_enc.c b/src/gallium/drivers/radeonsi/radeon_vcn_enc.c index 77a4ff8037e..d12503b906d 100644 --- a/src/gallium/drivers/radeonsi/radeon_vcn_enc.c +++ b/src/gallium/drivers/radeonsi/radeon_vcn_enc.c @@ -609,17 +609,43 @@ static void radeon_vcn_enc_hevc_get_dbk_param(struct radeon_encoder *enc, { struct si_screen *sscreen = (struct si_screen *)enc->screen; - enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled = - pic->pic.pps_loop_filter_across_slices_enabled_flag; - enc->enc_pic.hevc_deblock.deblocking_filter_disabled = - pic->slice.slice_deblocking_filter_disabled_flag; - enc->enc_pic.hevc_deblock.beta_offset_div2 = pic->slice.slice_beta_offset_div2; - enc->enc_pic.hevc_deblock.tc_offset_div2 = pic->slice.slice_tc_offset_div2; - enc->enc_pic.hevc_deblock.cb_qp_offset = pic->slice.slice_cb_qp_offset; - enc->enc_pic.hevc_deblock.cr_qp_offset = pic->slice.slice_cr_qp_offset; + enc->enc_pic.hevc_deblock.deblocking_filter_disabled = 0; + enc->enc_pic.hevc_deblock.beta_offset_div2 = 0; + enc->enc_pic.hevc_deblock.tc_offset_div2 = 0; enc->enc_pic.hevc_deblock.disable_sao = sscreen->info.vcn_ip_version < VCN_2_0_0 || !pic->seq.sample_adaptive_offset_enabled_flag; + + if (pic->pic.deblocking_filter_override_enabled_flag && + pic->slice.deblocking_filter_override_flag) { + enc->enc_pic.hevc_deblock.deblocking_filter_disabled = + pic->slice.slice_deblocking_filter_disabled_flag; + enc->enc_pic.hevc_deblock.beta_offset_div2 = pic->slice.slice_beta_offset_div2; + enc->enc_pic.hevc_deblock.tc_offset_div2 = pic->slice.slice_tc_offset_div2; + } else if (pic->pic.deblocking_filter_control_present_flag) { + enc->enc_pic.hevc_deblock.deblocking_filter_disabled = + pic->pic.pps_deblocking_filter_disabled_flag; + enc->enc_pic.hevc_deblock.beta_offset_div2 = pic->slice.slice_beta_offset_div2; + enc->enc_pic.hevc_deblock.tc_offset_div2 = pic->slice.slice_tc_offset_div2; + } + + if (pic->pic.pps_slice_chroma_qp_offsets_present_flag) { + enc->enc_pic.hevc_deblock.cb_qp_offset = pic->slice.slice_cb_qp_offset; + enc->enc_pic.hevc_deblock.cr_qp_offset = pic->slice.slice_cr_qp_offset; + } else { + enc->enc_pic.hevc_deblock.cb_qp_offset = pic->pic.pps_cb_qp_offset; + enc->enc_pic.hevc_deblock.cr_qp_offset = pic->pic.pps_cr_qp_offset; + } + + if (pic->pic.pps_loop_filter_across_slices_enabled_flag && + (!enc->enc_pic.hevc_deblock.disable_sao || + !enc->enc_pic.hevc_deblock.deblocking_filter_disabled)) { + enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled = + pic->slice.slice_loop_filter_across_slices_enabled_flag; + } else { + enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled = + pic->pic.pps_loop_filter_across_slices_enabled_flag; + } } static bool cu_qp_delta_supported(struct si_screen *sscreen) diff --git a/src/gallium/drivers/radeonsi/radeon_vcn_enc_1_2.c b/src/gallium/drivers/radeonsi/radeon_vcn_enc_1_2.c index 4e87e2d9107..a5471b4b0fd 100644 --- a/src/gallium/drivers/radeonsi/radeon_vcn_enc_1_2.c +++ b/src/gallium/drivers/radeonsi/radeon_vcn_enc_1_2.c @@ -225,8 +225,6 @@ unsigned int radeon_enc_write_pps_hevc(struct radeon_encoder *enc, uint8_t *out) pps.constrained_intra_pred_flag = enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag; pps.transform_skip_enabled_flag = !enc->enc_pic.hevc_spec_misc.transform_skip_disabled; pps.cu_qp_delta_enabled_flag = enc->enc_pic.hevc_spec_misc.cu_qp_delta_enabled_flag; - pps.pps_beta_offset_div2 = enc->enc_pic.hevc_deblock.beta_offset_div2; - pps.pps_tc_offset_div2 = enc->enc_pic.hevc_deblock.tc_offset_div2; struct radeon_bitstream bs; radeon_bs_reset(&bs, out, NULL); @@ -603,7 +601,7 @@ static void radeon_enc_slice_header_hevc(struct radeon_encoder *enc) } } - if ((enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled) && + if (pps->pps_loop_filter_across_slices_enabled_flag && (!enc->enc_pic.hevc_deblock.deblocking_filter_disabled || !enc->enc_pic.hevc_deblock.disable_sao)) { if (!enc->enc_pic.hevc_deblock.disable_sao) {