diff --git a/src/broadcom/compiler/nir_to_vir.c b/src/broadcom/compiler/nir_to_vir.c index 2bdbccad308..904f0a562f3 100644 --- a/src/broadcom/compiler/nir_to_vir.c +++ b/src/broadcom/compiler/nir_to_vir.c @@ -1263,6 +1263,18 @@ ntq_emit_cond_to_bool(struct v3d_compile *c, enum v3d_qpu_cond cond) return result; } +static struct qreg +ntq_emit_cond_to_int(struct v3d_compile *c, enum v3d_qpu_cond cond) +{ + struct qreg result = + vir_MOV(c, vir_SEL(c, cond, + vir_uniform_ui(c, 1), + vir_uniform_ui(c, 0))); + c->flags_temp = result.index; + c->flags_cond = cond; + return result; +} + static struct qreg f2f16_rtz(struct v3d_compile *c, struct qreg f32) { @@ -1713,7 +1725,13 @@ ntq_emit_alu(struct v3d_compile *c, nir_alu_instr *instr) case nir_op_uadd_carry: vir_set_pf(c, vir_ADD_dest(c, vir_nop_reg(), src[0], src[1]), V3D_QPU_PF_PUSHC); - result = ntq_emit_cond_to_bool(c, V3D_QPU_COND_IFA); + result = ntq_emit_cond_to_int(c, V3D_QPU_COND_IFA); + break; + + case nir_op_usub_borrow: + vir_set_pf(c, vir_SUB_dest(c, vir_nop_reg(), src[0], src[1]), + V3D_QPU_PF_PUSHC); + result = ntq_emit_cond_to_int(c, V3D_QPU_COND_IFA); break; case nir_op_pack_half_2x16_split: diff --git a/src/broadcom/vulkan/v3dv_pipeline.c b/src/broadcom/vulkan/v3dv_pipeline.c index a441c74ac07..82058c270e1 100644 --- a/src/broadcom/vulkan/v3dv_pipeline.c +++ b/src/broadcom/vulkan/v3dv_pipeline.c @@ -214,11 +214,6 @@ const nir_shader_compiler_options v3dv_nir_options = { .lower_pack_32_2x16 = true, .lower_pack_32_2x16_split = true, .lower_unpack_32_2x16_split = true, - /* FIXME: see if we can avoid the uadd_carry and usub_borrow lowering and - * get the tests to pass since it might produce slightly better code. - */ - .lower_uadd_carry = true, - .lower_usub_borrow = true, /* FIXME: check if we can use multop + umul24 to implement mul2x32_64 * without lowering. */