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pvr: drop PVRX macro

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All core-specific selections will take place at runtime.

Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32258>
This commit is contained in:
Simon Perretta
2024-10-01 15:32:05 +01:00
committed by Marge Bot
parent cbc9896264
commit 14d7ade582
31 changed files with 686 additions and 687 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/imagination/vulkan/pvr_cmd_buffer.c
+130 -130
View File
@@ -78,11 +78,11 @@ struct pvr_compute_kernel_info {
uint32_t usc_unified_size;
uint32_t pds_temp_size;
uint32_t pds_data_size;
enum PVRX(CDMCTRL_USC_TARGET) usc_target;
enum ROGUE_CDMCTRL_USC_TARGET usc_target;
bool is_fence;
uint32_t pds_data_offset;
uint32_t pds_code_offset;
enum PVRX(CDMCTRL_SD_TYPE) sd_type;
enum ROGUE_CDMCTRL_SD_TYPE sd_type;
bool usc_common_shared;
uint32_t global_size[PVR_WORKGROUP_DIMENSIONS];
uint32_t local_size[PVR_WORKGROUP_DIMENSIONS];
@@ -526,7 +526,7 @@ static VkResult pvr_sub_cmd_gfx_per_job_fragment_programs_create_and_upload(
pvr_pds_setup_doutu(&pixel_event_program.task_control,
usc_eot_program->dev_addr.addr,
usc_temp_count,
PVRX(PDSINST_DOUTU_SAMPLE_RATE_INSTANCE),
ROGUE_PDSINST_DOUTU_SAMPLE_RATE_INSTANCE,
false);
/* TODO: We could skip allocating this and generate directly into the device
@@ -645,11 +645,11 @@ static VkResult pvr_setup_texture_state_words(
TEXSTATE_SAMPLER,
sampler) {
sampler.non_normalized_coords = true;
sampler.addrmode_v = PVRX(TEXSTATE_ADDRMODE_CLAMP_TO_EDGE);
sampler.addrmode_u = PVRX(TEXSTATE_ADDRMODE_CLAMP_TO_EDGE);
sampler.minfilter = PVRX(TEXSTATE_FILTER_POINT);
sampler.magfilter = PVRX(TEXSTATE_FILTER_POINT);
sampler.dadjust = PVRX(TEXSTATE_DADJUST_ZERO_UINT);
sampler.addrmode_v = ROGUE_TEXSTATE_ADDRMODE_CLAMP_TO_EDGE;
sampler.addrmode_u = ROGUE_TEXSTATE_ADDRMODE_CLAMP_TO_EDGE;
sampler.minfilter = ROGUE_TEXSTATE_FILTER_POINT;
sampler.magfilter = ROGUE_TEXSTATE_FILTER_POINT;
sampler.dadjust = ROGUE_TEXSTATE_DADJUST_ZERO_UINT;
}
return VK_SUCCESS;
@@ -815,7 +815,7 @@ static VkResult pvr_load_op_pds_data_create_and_upload(
pvr_csb_pack (&program.texture_dma_control[0],
PDSINST_DOUT_FIELDS_DOUTD_SRC1,
value) {
value.dest = PVRX(PDSINST_DOUTD_DEST_COMMON_STORE);
value.dest = ROGUE_PDSINST_DOUTD_DEST_COMMON_STORE;
value.a0 = load_op->shareds_dest_offset;
value.bsize = load_op->shareds_count;
}
@@ -892,13 +892,13 @@ static void pvr_pds_bgnd_pack_state(
pvr_csb_pack (&pds_reg_values[2], CR_PDS_BGRND3_SIZEINFO, value) {
value.usc_sharedsize =
DIV_ROUND_UP(load_op->const_shareds_count,
PVRX(CR_PDS_BGRND3_SIZEINFO_USC_SHAREDSIZE_UNIT_SIZE));
ROGUE_CR_PDS_BGRND3_SIZEINFO_USC_SHAREDSIZE_UNIT_SIZE);
value.pds_texturestatesize = DIV_ROUND_UP(
load_op_program->data_size,
PVRX(CR_PDS_BGRND3_SIZEINFO_PDS_TEXTURESTATESIZE_UNIT_SIZE));
ROGUE_CR_PDS_BGRND3_SIZEINFO_PDS_TEXTURESTATESIZE_UNIT_SIZE);
value.pds_tempsize =
DIV_ROUND_UP(load_op->temps_count,
PVRX(CR_PDS_BGRND3_SIZEINFO_PDS_TEMPSIZE_UNIT_SIZE));
ROGUE_CR_PDS_BGRND3_SIZEINFO_PDS_TEMPSIZE_UNIT_SIZE);
}
}
@@ -1581,16 +1581,16 @@ static VkResult pvr_sub_cmd_gfx_job_init(const struct pvr_device_info *dev_info,
switch (ds_iview->vk.format) {
case VK_FORMAT_D16_UNORM:
job->ds.zls_format = PVRX(CR_ZLS_FORMAT_TYPE_16BITINT);
job->ds.zls_format = ROGUE_CR_ZLS_FORMAT_TYPE_16BITINT;
break;
case VK_FORMAT_S8_UINT:
case VK_FORMAT_D32_SFLOAT:
job->ds.zls_format = PVRX(CR_ZLS_FORMAT_TYPE_F32Z);
job->ds.zls_format = ROGUE_CR_ZLS_FORMAT_TYPE_F32Z;
break;
case VK_FORMAT_D24_UNORM_S8_UINT:
job->ds.zls_format = PVRX(CR_ZLS_FORMAT_TYPE_24BITINT);
job->ds.zls_format = ROGUE_CR_ZLS_FORMAT_TYPE_24BITINT;
break;
default:
@@ -1758,7 +1758,7 @@ pvr_sub_cmd_compute_job_init(const struct pvr_physical_device *pdevice,
}
#define PIXEL_ALLOCATION_SIZE_MAX_IN_BLOCKS \
(1024 / PVRX(CDMCTRL_KERNEL0_USC_COMMON_SIZE_UNIT_SIZE))
(1024 / ROGUE_CDMCTRL_KERNEL0_USC_COMMON_SIZE_UNIT_SIZE)
static uint32_t
pvr_compute_flat_slot_size(const struct pvr_physical_device *pdevice,
@@ -1774,7 +1774,7 @@ pvr_compute_flat_slot_size(const struct pvr_physical_device *pdevice,
dev_runtime_info->cdm_max_local_mem_size_regs;
uint32_t localstore_chunks_count =
DIV_ROUND_UP(PVR_DW_TO_BYTES(coeff_regs_count),
PVRX(CDMCTRL_KERNEL0_USC_COMMON_SIZE_UNIT_SIZE));
ROGUE_CDMCTRL_KERNEL0_USC_COMMON_SIZE_UNIT_SIZE);
/* Ensure that we cannot have more workgroups in a slot than the available
* number of coefficients allow us to have.
@@ -1808,7 +1808,7 @@ pvr_compute_flat_slot_size(const struct pvr_physical_device *pdevice,
*/
uint32_t max_common_store_blocks =
DIV_ROUND_UP(max_avail_coeff_regs * 4U,
PVRX(CDMCTRL_KERNEL0_USC_COMMON_SIZE_UNIT_SIZE));
ROGUE_CDMCTRL_KERNEL0_USC_COMMON_SIZE_UNIT_SIZE);
/* (coefficient_memory_pool_size) - (7 * pixel_allocation_size_max)
*/
@@ -1977,16 +1977,16 @@ pvr_compute_generate_idfwdf(struct pvr_cmd_buffer *cmd_buffer,
.global_offsets_present = false,
.usc_common_size = DIV_ROUND_UP(
PVR_DW_TO_BYTES(cmd_buffer->device->idfwdf_state.usc_shareds),
PVRX(CDMCTRL_KERNEL0_USC_COMMON_SIZE_UNIT_SIZE)),
ROGUE_CDMCTRL_KERNEL0_USC_COMMON_SIZE_UNIT_SIZE),
.usc_unified_size = 0U,
.pds_temp_size = 0U,
.pds_data_size =
DIV_ROUND_UP(PVR_DW_TO_BYTES(program->data_size),
PVRX(CDMCTRL_KERNEL0_PDS_DATA_SIZE_UNIT_SIZE)),
.usc_target = PVRX(CDMCTRL_USC_TARGET_ALL),
ROGUE_CDMCTRL_KERNEL0_PDS_DATA_SIZE_UNIT_SIZE),
.usc_target = ROGUE_CDMCTRL_USC_TARGET_ALL,
.is_fence = false,
.pds_data_offset = program->data_offset,
.sd_type = PVRX(CDMCTRL_SD_TYPE_USC),
.sd_type = ROGUE_CDMCTRL_SD_TYPE_USC,
.usc_common_shared = true,
.pds_code_offset = program->code_offset,
.global_size = { 1U, 1U, 1U },
@@ -2021,11 +2021,11 @@ void pvr_compute_generate_fence(struct pvr_cmd_buffer *cmd_buffer,
.pds_temp_size = 0U,
.pds_data_size =
DIV_ROUND_UP(PVR_DW_TO_BYTES(program->data_size),
PVRX(CDMCTRL_KERNEL0_PDS_DATA_SIZE_UNIT_SIZE)),
.usc_target = PVRX(CDMCTRL_USC_TARGET_ANY),
ROGUE_CDMCTRL_KERNEL0_PDS_DATA_SIZE_UNIT_SIZE),
.usc_target = ROGUE_CDMCTRL_USC_TARGET_ANY,
.is_fence = true,
.pds_data_offset = program->data_offset,
.sd_type = PVRX(CDMCTRL_SD_TYPE_PDS),
.sd_type = ROGUE_CDMCTRL_SD_TYPE_PDS,
.usc_common_shared = deallocate_shareds,
.pds_code_offset = program->code_offset,
.global_size = { 1U, 1U, 1U },
@@ -2271,7 +2271,7 @@ void pvr_reset_graphics_dirty_state(struct pvr_cmd_buffer *const cmd_buffer,
* phase.
*/
cmd_buffer->state.emit_header = (struct PVRX(TA_STATE_HEADER)){
cmd_buffer->state.emit_header = (struct ROGUE_TA_STATE_HEADER){
.pres_stream_out_size = true,
.pres_ppp_ctrl = true,
.pres_varying_word2 = true,
@@ -2286,7 +2286,7 @@ void pvr_reset_graphics_dirty_state(struct pvr_cmd_buffer *const cmd_buffer,
.pres_ispctl = true,
};
} else {
struct PVRX(TA_STATE_HEADER) *const emit_header =
struct ROGUE_TA_STATE_HEADER *const emit_header =
&cmd_buffer->state.emit_header;
emit_header->pres_ppp_ctrl = true;
@@ -3135,11 +3135,11 @@ static VkResult pvr_cs_write_load_op(struct pvr_cmd_buffer *cmd_buffer,
sizeinfo1.pds_texturestatesize = DIV_ROUND_UP(
shareds_update_program.data_size,
PVRX(TA_STATE_PDS_SIZEINFO1_PDS_TEXTURESTATESIZE_UNIT_SIZE));
ROGUE_TA_STATE_PDS_SIZEINFO1_PDS_TEXTURESTATESIZE_UNIT_SIZE);
sizeinfo1.pds_tempsize =
DIV_ROUND_UP(load_op->temps_count,
PVRX(TA_STATE_PDS_SIZEINFO1_PDS_TEMPSIZE_UNIT_SIZE));
ROGUE_TA_STATE_PDS_SIZEINFO1_PDS_TEMPSIZE_UNIT_SIZE);
}
pvr_csb_pack (&pds_state[PVR_STATIC_CLEAR_PPP_PDS_TYPE_SIZEINFO2],
@@ -3147,7 +3147,7 @@ static VkResult pvr_cs_write_load_op(struct pvr_cmd_buffer *cmd_buffer,
sizeinfo2) {
sizeinfo2.usc_sharedsize =
DIV_ROUND_UP(load_op->const_shareds_count,
PVRX(TA_STATE_PDS_SIZEINFO2_USC_SHAREDSIZE_UNIT_SIZE));
ROGUE_TA_STATE_PDS_SIZEINFO2_USC_SHAREDSIZE_UNIT_SIZE);
}
/* Dummy coefficient loading program. */
@@ -4310,13 +4310,13 @@ static void pvr_compute_update_shared(struct pvr_cmd_buffer *cmd_buffer,
info = (struct pvr_compute_kernel_info){
.indirect_buffer_addr = PVR_DEV_ADDR_INVALID,
.sd_type = PVRX(CDMCTRL_SD_TYPE_NONE),
.sd_type = ROGUE_CDMCTRL_SD_TYPE_NONE,
.usc_target = PVRX(CDMCTRL_USC_TARGET_ALL),
.usc_target = ROGUE_CDMCTRL_USC_TARGET_ALL,
.usc_common_shared = true,
.usc_common_size =
DIV_ROUND_UP(const_shared_regs,
PVRX(CDMCTRL_KERNEL0_USC_COMMON_SIZE_UNIT_SIZE)),
ROGUE_CDMCTRL_KERNEL0_USC_COMMON_SIZE_UNIT_SIZE),
.global_size = { 1, 1, 1 },
.local_size = { 1, 1, 1 },
@@ -4334,7 +4334,7 @@ static void pvr_compute_update_shared(struct pvr_cmd_buffer *cmd_buffer,
info.pds_data_offset = state->pds_compute_descriptor_data_offset;
info.pds_data_size =
DIV_ROUND_UP(PVR_DW_TO_BYTES(pds_data_size_in_dwords),
PVRX(CDMCTRL_KERNEL0_PDS_DATA_SIZE_UNIT_SIZE));
ROGUE_CDMCTRL_KERNEL0_PDS_DATA_SIZE_UNIT_SIZE);
/* Check that we have upload the code section. */
assert(pipeline->descriptor_state.pds_code.code_size);
@@ -4345,7 +4345,7 @@ static void pvr_compute_update_shared(struct pvr_cmd_buffer *cmd_buffer,
info.pds_data_offset = program->data_offset;
info.pds_data_size =
DIV_ROUND_UP(PVR_DW_TO_BYTES(program->data_size),
PVRX(CDMCTRL_KERNEL0_PDS_DATA_SIZE_UNIT_SIZE));
ROGUE_CDMCTRL_KERNEL0_PDS_DATA_SIZE_UNIT_SIZE);
info.pds_code_offset = program->code_offset;
}
@@ -4379,14 +4379,14 @@ void pvr_compute_update_shared_private(
.indirect_buffer_addr = PVR_DEV_ADDR_INVALID,
.usc_common_size =
DIV_ROUND_UP(const_shared_regs,
PVRX(CDMCTRL_KERNEL0_USC_COMMON_SIZE_UNIT_SIZE)),
ROGUE_CDMCTRL_KERNEL0_USC_COMMON_SIZE_UNIT_SIZE),
.pds_data_size =
DIV_ROUND_UP(PVR_DW_TO_BYTES(pipeline->pds_shared_update_data_size_dw),
PVRX(CDMCTRL_KERNEL0_PDS_DATA_SIZE_UNIT_SIZE)),
.usc_target = PVRX(CDMCTRL_USC_TARGET_ALL),
ROGUE_CDMCTRL_KERNEL0_PDS_DATA_SIZE_UNIT_SIZE),
.usc_target = ROGUE_CDMCTRL_USC_TARGET_ALL,
.pds_data_offset = pipeline->pds_shared_update_data_offset,
.pds_code_offset = pipeline->pds_shared_update_code_offset,
.sd_type = PVRX(CDMCTRL_SD_TYPE_NONE),
.sd_type = ROGUE_CDMCTRL_SD_TYPE_NONE,
.usc_common_shared = true,
.global_size = { 1, 1, 1 },
.local_size = { 1, 1, 1 },
@@ -4412,7 +4412,7 @@ pvr_compute_flat_pad_workgroup_size(const struct pvr_physical_device *pdevice,
dev_runtime_info->cdm_max_local_mem_size_regs;
uint32_t coeff_regs_count_aligned =
ALIGN_POT(coeff_regs_count,
PVRX(CDMCTRL_KERNEL0_USC_COMMON_SIZE_UNIT_SIZE) >> 2U);
ROGUE_CDMCTRL_KERNEL0_USC_COMMON_SIZE_UNIT_SIZE >> 2U);
/* If the work group size is > ROGUE_MAX_INSTANCES_PER_TASK. We now *always*
* pad the work group size to the next multiple of
@@ -4445,22 +4445,22 @@ void pvr_compute_update_kernel_private(
struct pvr_compute_kernel_info info = {
.indirect_buffer_addr = PVR_DEV_ADDR_INVALID,
.usc_target = PVRX(CDMCTRL_USC_TARGET_ANY),
.usc_target = ROGUE_CDMCTRL_USC_TARGET_ANY,
.pds_temp_size =
DIV_ROUND_UP(pipeline->pds_temps_used << 2U,
PVRX(CDMCTRL_KERNEL0_PDS_TEMP_SIZE_UNIT_SIZE)),
ROGUE_CDMCTRL_KERNEL0_PDS_TEMP_SIZE_UNIT_SIZE),
.pds_data_size =
DIV_ROUND_UP(PVR_DW_TO_BYTES(pipeline->pds_data_size_dw),
PVRX(CDMCTRL_KERNEL0_PDS_DATA_SIZE_UNIT_SIZE)),
ROGUE_CDMCTRL_KERNEL0_PDS_DATA_SIZE_UNIT_SIZE),
.pds_data_offset = pipeline->pds_data_offset,
.pds_code_offset = pipeline->pds_code_offset,
.sd_type = PVRX(CDMCTRL_SD_TYPE_NONE),
.sd_type = ROGUE_CDMCTRL_SD_TYPE_NONE,
.usc_unified_size =
DIV_ROUND_UP(pipeline->unified_store_regs_count << 2U,
PVRX(CDMCTRL_KERNEL0_USC_UNIFIED_SIZE_UNIT_SIZE)),
ROGUE_CDMCTRL_KERNEL0_USC_UNIFIED_SIZE_UNIT_SIZE),
/* clang-format off */
.global_size = {
@@ -4486,7 +4486,7 @@ void pvr_compute_update_kernel_private(
info.usc_common_size =
DIV_ROUND_UP(PVR_DW_TO_BYTES(coeff_regs),
PVRX(CDMCTRL_KERNEL0_USC_COMMON_SIZE_UNIT_SIZE));
ROGUE_CDMCTRL_KERNEL0_USC_COMMON_SIZE_UNIT_SIZE);
/* Use a whole slot per workgroup. */
work_size = MAX2(work_size, ROGUE_MAX_INSTANCES_PER_TASK);
@@ -4494,7 +4494,7 @@ void pvr_compute_update_kernel_private(
coeff_regs += pipeline->const_shared_regs_count;
if (pipeline->const_shared_regs_count > 0)
info.sd_type = PVRX(CDMCTRL_SD_TYPE_USC);
info.sd_type = ROGUE_CDMCTRL_SD_TYPE_USC;
work_size =
pvr_compute_flat_pad_workgroup_size(pdevice, work_size, coeff_regs);
@@ -4530,22 +4530,22 @@ static void pvr_compute_update_kernel(
struct pvr_compute_kernel_info info = {
.indirect_buffer_addr = indirect_addr,
.usc_target = PVRX(CDMCTRL_USC_TARGET_ANY),
.usc_target = ROGUE_CDMCTRL_USC_TARGET_ANY,
.pds_temp_size =
DIV_ROUND_UP(program_info->temps_required << 2U,
PVRX(CDMCTRL_KERNEL0_PDS_TEMP_SIZE_UNIT_SIZE)),
ROGUE_CDMCTRL_KERNEL0_PDS_TEMP_SIZE_UNIT_SIZE),
.pds_data_size =
DIV_ROUND_UP(PVR_DW_TO_BYTES(program_info->data_size_in_dwords),
PVRX(CDMCTRL_KERNEL0_PDS_DATA_SIZE_UNIT_SIZE)),
ROGUE_CDMCTRL_KERNEL0_PDS_DATA_SIZE_UNIT_SIZE),
.pds_data_offset = pipeline->primary_program.data_offset,
.pds_code_offset = pipeline->primary_program.code_offset,
.sd_type = PVRX(CDMCTRL_SD_TYPE_NONE),
.sd_type = ROGUE_CDMCTRL_SD_TYPE_NONE,
.usc_unified_size =
DIV_ROUND_UP(shader_state->input_register_count << 2U,
PVRX(CDMCTRL_KERNEL0_USC_UNIFIED_SIZE_UNIT_SIZE)),
ROGUE_CDMCTRL_KERNEL0_USC_UNIFIED_SIZE_UNIT_SIZE),
/* clang-format off */
.global_size = {
@@ -4569,7 +4569,7 @@ static void pvr_compute_update_kernel(
info.usc_common_size =
DIV_ROUND_UP(PVR_DW_TO_BYTES(coeff_regs),
PVRX(CDMCTRL_KERNEL0_USC_COMMON_SIZE_UNIT_SIZE));
ROGUE_CDMCTRL_KERNEL0_USC_COMMON_SIZE_UNIT_SIZE);
/* Use a whole slot per workgroup. */
work_size = MAX2(work_size, ROGUE_MAX_INSTANCES_PER_TASK);
@@ -4577,7 +4577,7 @@ static void pvr_compute_update_kernel(
coeff_regs += shader_state->const_shared_reg_count;
if (shader_state->const_shared_reg_count > 0)
info.sd_type = PVRX(CDMCTRL_SD_TYPE_USC);
info.sd_type = ROGUE_CDMCTRL_SD_TYPE_USC;
work_size =
pvr_compute_flat_pad_workgroup_size(pdevice, work_size, coeff_regs);
@@ -4807,20 +4807,20 @@ pvr_emit_dirty_pds_state(const struct pvr_cmd_buffer *const cmd_buffer,
pvr_csb_set_relocation_mark(csb);
pvr_csb_emit (csb, VDMCTRL_PDS_STATE0, state0) {
state0.usc_target = PVRX(VDMCTRL_USC_TARGET_ALL);
state0.usc_target = ROGUE_VDMCTRL_USC_TARGET_ALL;
state0.usc_common_size =
DIV_ROUND_UP(vertex_stage_state->const_shared_reg_count << 2,
PVRX(VDMCTRL_PDS_STATE0_USC_COMMON_SIZE_UNIT_SIZE));
ROGUE_VDMCTRL_PDS_STATE0_USC_COMMON_SIZE_UNIT_SIZE);
state0.pds_data_size = DIV_ROUND_UP(
PVR_DW_TO_BYTES(vertex_descriptor_state->pds_info.data_size_in_dwords),
PVRX(VDMCTRL_PDS_STATE0_PDS_DATA_SIZE_UNIT_SIZE));
ROGUE_VDMCTRL_PDS_STATE0_PDS_DATA_SIZE_UNIT_SIZE);
}
pvr_csb_emit (csb, VDMCTRL_PDS_STATE1, state1) {
state1.pds_data_addr = PVR_DEV_ADDR(pds_vertex_descriptor_data_offset);
state1.sd_type = PVRX(VDMCTRL_SD_TYPE_NONE);
state1.sd_type = ROGUE_VDMCTRL_SD_TYPE_NONE;
}
pvr_csb_emit (csb, VDMCTRL_PDS_STATE2, state2) {
@@ -4839,7 +4839,7 @@ static void pvr_setup_output_select(struct pvr_cmd_buffer *const cmd_buffer)
&gfx_pipeline->shader_state.vertex;
struct vk_dynamic_graphics_state *const dynamic_state =
&cmd_buffer->vk.dynamic_graphics_state;
struct PVRX(TA_STATE_HEADER) *const header = &cmd_buffer->state.emit_header;
struct ROGUE_TA_STATE_HEADER *const header = &cmd_buffer->state.emit_header;
struct pvr_ppp_state *const ppp_state = &cmd_buffer->state.ppp_state;
uint32_t output_selects;
@@ -4870,9 +4870,9 @@ static void pvr_setup_output_select(struct pvr_cmd_buffer *const cmd_buffer)
static void
pvr_setup_isp_faces_and_control(struct pvr_cmd_buffer *const cmd_buffer,
struct PVRX(TA_STATE_ISPA) *const ispa_out)
struct ROGUE_TA_STATE_ISPA *const ispa_out)
{
struct PVRX(TA_STATE_HEADER) *const header = &cmd_buffer->state.emit_header;
struct ROGUE_TA_STATE_HEADER *const header = &cmd_buffer->state.emit_header;
const struct pvr_fragment_shader_state *const fragment_shader_state =
&cmd_buffer->state.gfx_pipeline->shader_state.fragment;
const struct pvr_render_pass_info *const pass_info =
@@ -4890,8 +4890,8 @@ pvr_setup_isp_faces_and_control(struct pvr_cmd_buffer *const cmd_buffer,
? &pass_info->pass->attachments[depth_stencil_attachment_idx]
: NULL;
const enum PVRX(TA_OBJTYPE)
obj_type = pvr_ta_objtype(dynamic_state->ia.primitive_topology);
const enum ROGUE_TA_OBJTYPE obj_type =
pvr_ta_objtype(dynamic_state->ia.primitive_topology);
const VkImageAspectFlags ds_aspects =
(!rasterizer_discard && attachment)
@@ -4926,7 +4926,7 @@ pvr_setup_isp_faces_and_control(struct pvr_cmd_buffer *const cmd_buffer,
*/
line_width = (!!line_width) * (line_width - 1);
line_width = MIN2(line_width, PVRX(TA_STATE_ISPA_POINTLINEWIDTH_SIZE_MAX));
line_width = MIN2(line_width, ROGUE_TA_STATE_ISPA_POINTLINEWIDTH_SIZE_MAX);
/* TODO: Part of the logic in this function is duplicated in another part
* of the code. E.g. the dcmpmode, and sop1/2/3. Could we do this earlier?
@@ -4953,10 +4953,10 @@ pvr_setup_isp_faces_and_control(struct pvr_cmd_buffer *const cmd_buffer,
* If not, rename the variable.
*/
pvr_csb_pack (&ispb_stencil_off, TA_STATE_ISPB, ispb) {
ispb.sop3 = PVRX(TA_ISPB_STENCILOP_KEEP);
ispb.sop2 = PVRX(TA_ISPB_STENCILOP_KEEP);
ispb.sop1 = PVRX(TA_ISPB_STENCILOP_KEEP);
ispb.scmpmode = PVRX(TA_CMPMODE_ALWAYS);
ispb.sop3 = ROGUE_TA_ISPB_STENCILOP_KEEP;
ispb.sop2 = ROGUE_TA_ISPB_STENCILOP_KEEP;
ispb.sop1 = ROGUE_TA_ISPB_STENCILOP_KEEP;
ispb.scmpmode = ROGUE_TA_CMPMODE_ALWAYS;
}
/* FIXME: This logic should be redone and improved. Can we also get rid of
@@ -5060,7 +5060,7 @@ pvr_setup_isp_faces_and_control(struct pvr_cmd_buffer *const cmd_buffer,
ispctl.dbenable = !rasterizer_discard &&
dynamic_state->rs.depth_bias.enable &&
obj_type == PVRX(TA_OBJTYPE_TRIANGLE);
obj_type == ROGUE_TA_OBJTYPE_TRIANGLE;
if (!rasterizer_discard && cmd_buffer->state.vis_test_enabled) {
ispctl.vistest = true;
ispctl.visreg = cmd_buffer->state.vis_reg;
@@ -5240,11 +5240,11 @@ pvr_get_geom_region_clip_align_size(struct pvr_device_info *const dev_info)
static void
pvr_setup_isp_depth_bias_scissor_state(struct pvr_cmd_buffer *const cmd_buffer)
{
struct PVRX(TA_STATE_HEADER) *const header = &cmd_buffer->state.emit_header;
struct ROGUE_TA_STATE_HEADER *const header = &cmd_buffer->state.emit_header;
struct pvr_ppp_state *const ppp_state = &cmd_buffer->state.ppp_state;
struct vk_dynamic_graphics_state *const dynamic_state =
&cmd_buffer->vk.dynamic_graphics_state;
const struct PVRX(TA_STATE_ISPCTL) *const ispctl =
const struct ROGUE_TA_STATE_ISPCTL *const ispctl =
&ppp_state->isp.control_struct;
struct pvr_device_info *const dev_info =
&cmd_buffer->device->pdevice->dev_info;
@@ -5344,7 +5344,7 @@ pvr_setup_isp_depth_bias_scissor_state(struct pvr_cmd_buffer *const cmd_buffer)
pvr_csb_pack (&ppp_state->region_clipping.word0, TA_REGION_CLIP0, word0) {
word0.right = right;
word0.left = left;
word0.mode = PVRX(TA_REGION_CLIP_MODE_OUTSIDE);
word0.mode = ROGUE_TA_REGION_CLIP_MODE_OUTSIDE;
}
pvr_csb_pack (&ppp_state->region_clipping.word1, TA_REGION_CLIP1, word1) {
@@ -5367,9 +5367,9 @@ pvr_setup_isp_depth_bias_scissor_state(struct pvr_cmd_buffer *const cmd_buffer)
static void
pvr_setup_triangle_merging_flag(struct pvr_cmd_buffer *const cmd_buffer,
struct PVRX(TA_STATE_ISPA) * ispa)
struct ROGUE_TA_STATE_ISPA *ispa)
{
struct PVRX(TA_STATE_HEADER) *const header = &cmd_buffer->state.emit_header;
struct ROGUE_TA_STATE_HEADER *const header = &cmd_buffer->state.emit_header;
struct pvr_ppp_state *const ppp_state = &cmd_buffer->state.ppp_state;
uint32_t merge_word;
uint32_t mask;
@@ -5378,9 +5378,9 @@ pvr_setup_triangle_merging_flag(struct pvr_cmd_buffer *const cmd_buffer,
/* Disable for lines or punch-through or for DWD and depth compare
* always.
*/
if (ispa->objtype == PVRX(TA_OBJTYPE_LINE) ||
ispa->passtype == PVRX(TA_PASSTYPE_PUNCH_THROUGH) ||
(ispa->dwritedisable && ispa->dcmpmode == PVRX(TA_CMPMODE_ALWAYS))) {
if (ispa->objtype == ROGUE_TA_OBJTYPE_LINE ||
ispa->passtype == ROGUE_TA_PASSTYPE_PUNCH_THROUGH ||
(ispa->dwritedisable && ispa->dcmpmode == ROGUE_TA_CMPMODE_ALWAYS)) {
size_info.pds_tri_merge_disable = true;
}
}
@@ -5413,35 +5413,35 @@ pvr_setup_fragment_state_pointers(struct pvr_cmd_buffer *const cmd_buffer,
&fragment->pds_coeff_program;
const struct pvr_physical_device *pdevice = cmd_buffer->device->pdevice;
struct PVRX(TA_STATE_HEADER) *const header = &state->emit_header;
struct ROGUE_TA_STATE_HEADER *const header = &state->emit_header;
struct pvr_ppp_state *const ppp_state = &state->ppp_state;
const uint32_t pds_uniform_size =
DIV_ROUND_UP(descriptor_shader_state->pds_info.data_size_in_dwords,
PVRX(TA_STATE_PDS_SIZEINFO1_PDS_UNIFORMSIZE_UNIT_SIZE));
ROGUE_TA_STATE_PDS_SIZEINFO1_PDS_UNIFORMSIZE_UNIT_SIZE);
const uint32_t pds_varying_state_size =
DIV_ROUND_UP(pds_coeff_program->data_size,
PVRX(TA_STATE_PDS_SIZEINFO1_PDS_VARYINGSIZE_UNIT_SIZE));
ROGUE_TA_STATE_PDS_SIZEINFO1_PDS_VARYINGSIZE_UNIT_SIZE);
const uint32_t usc_varying_size =
DIV_ROUND_UP(fragment_state->coefficient_size,
PVRX(TA_STATE_PDS_SIZEINFO1_USC_VARYINGSIZE_UNIT_SIZE));
ROGUE_TA_STATE_PDS_SIZEINFO1_USC_VARYINGSIZE_UNIT_SIZE);
const uint32_t pds_temp_size =
DIV_ROUND_UP(fragment_state->pds_temps_count,
PVRX(TA_STATE_PDS_SIZEINFO1_PDS_TEMPSIZE_UNIT_SIZE));
ROGUE_TA_STATE_PDS_SIZEINFO1_PDS_TEMPSIZE_UNIT_SIZE);
const uint32_t usc_shared_size =
DIV_ROUND_UP(fragment_state->const_shared_reg_count,
PVRX(TA_STATE_PDS_SIZEINFO2_USC_SHAREDSIZE_UNIT_SIZE));
ROGUE_TA_STATE_PDS_SIZEINFO2_USC_SHAREDSIZE_UNIT_SIZE);
const uint32_t max_tiles_in_flight =
pvr_calc_fscommon_size_and_tiles_in_flight(
&pdevice->dev_info,
&pdevice->dev_runtime_info,
usc_shared_size *
PVRX(TA_STATE_PDS_SIZEINFO2_USC_SHAREDSIZE_UNIT_SIZE),
ROGUE_TA_STATE_PDS_SIZEINFO2_USC_SHAREDSIZE_UNIT_SIZE,
1);
uint32_t size_info_mask;
uint32_t size_info2;
@@ -5514,7 +5514,7 @@ pvr_setup_fragment_state_pointers(struct pvr_cmd_buffer *const cmd_buffer,
static void pvr_setup_viewport(struct pvr_cmd_buffer *const cmd_buffer)
{
struct pvr_cmd_buffer_state *const state = &cmd_buffer->state;
struct PVRX(TA_STATE_HEADER) *const header = &state->emit_header;
struct ROGUE_TA_STATE_HEADER *const header = &state->emit_header;
struct vk_dynamic_graphics_state *const dynamic_state =
&cmd_buffer->vk.dynamic_graphics_state;
struct pvr_ppp_state *const ppp_state = &state->ppp_state;
@@ -5567,7 +5567,7 @@ static void pvr_setup_ppp_control(struct pvr_cmd_buffer *const cmd_buffer)
&cmd_buffer->vk.dynamic_graphics_state;
const VkPrimitiveTopology topology = dynamic_state->ia.primitive_topology;
struct pvr_cmd_buffer_state *const state = &cmd_buffer->state;
struct PVRX(TA_STATE_HEADER) *const header = &state->emit_header;
struct ROGUE_TA_STATE_HEADER *const header = &state->emit_header;
struct pvr_ppp_state *const ppp_state = &state->ppp_state;
uint32_t ppp_control;
@@ -5576,14 +5576,14 @@ static void pvr_setup_ppp_control(struct pvr_cmd_buffer *const cmd_buffer)
control.wclampen = true;
if (topology == VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN)
control.flatshade_vtx = PVRX(TA_FLATSHADE_VTX_VERTEX_1);
control.flatshade_vtx = ROGUE_TA_FLATSHADE_VTX_VERTEX_1;
else
control.flatshade_vtx = PVRX(TA_FLATSHADE_VTX_VERTEX_0);
control.flatshade_vtx = ROGUE_TA_FLATSHADE_VTX_VERTEX_0;
if (dynamic_state->rs.depth_clamp_enable)
control.clip_mode = PVRX(TA_CLIP_MODE_NO_FRONT_OR_REAR);
control.clip_mode = ROGUE_TA_CLIP_MODE_NO_FRONT_OR_REAR;
else
control.clip_mode = PVRX(TA_CLIP_MODE_FRONT_REAR);
control.clip_mode = ROGUE_TA_CLIP_MODE_FRONT_REAR;
/* +--- FrontIsCCW?
* | +--- Cull Front?
@@ -5598,16 +5598,16 @@ static void pvr_setup_ppp_control(struct pvr_cmd_buffer *const cmd_buffer)
case VK_CULL_MODE_FRONT_BIT:
if ((dynamic_state->rs.front_face == VK_FRONT_FACE_COUNTER_CLOCKWISE) ^
(dynamic_state->rs.cull_mode == VK_CULL_MODE_FRONT_BIT)) {
control.cullmode = PVRX(TA_CULLMODE_CULL_CW);
control.cullmode = ROGUE_TA_CULLMODE_CULL_CW;
} else {
control.cullmode = PVRX(TA_CULLMODE_CULL_CCW);
control.cullmode = ROGUE_TA_CULLMODE_CULL_CCW;
}
break;
case VK_CULL_MODE_FRONT_AND_BACK:
case VK_CULL_MODE_NONE:
control.cullmode = PVRX(TA_CULLMODE_NO_CULLING);
control.cullmode = ROGUE_TA_CULLMODE_NO_CULLING;
break;
default:
@@ -5641,7 +5641,7 @@ static VkResult pvr_emit_ppp_state(struct pvr_cmd_buffer *const cmd_buffer,
{
const bool deferred_secondary = pvr_cmd_uses_deferred_cs_cmds(cmd_buffer);
struct pvr_cmd_buffer_state *const state = &cmd_buffer->state;
struct PVRX(TA_STATE_HEADER) *const header = &state->emit_header;
struct ROGUE_TA_STATE_HEADER *const header = &state->emit_header;
struct pvr_csb *const control_stream = &sub_cmd->control_stream;
struct pvr_ppp_state *const ppp_state = &state->ppp_state;
uint32_t ppp_state_words[PVR_MAX_PPP_STATE_DWORDS];
@@ -5653,7 +5653,7 @@ static VkResult pvr_emit_ppp_state(struct pvr_cmd_buffer *const cmd_buffer,
VkResult result;
#if !defined(NDEBUG)
struct PVRX(TA_STATE_HEADER) emit_mask = *header;
struct ROGUE_TA_STATE_HEADER emit_mask = *header;
uint32_t packed_emit_mask;
static_assert(pvr_cmd_length(TA_STATE_HEADER) == 1,
@@ -5928,7 +5928,7 @@ static VkResult pvr_emit_ppp_state(struct pvr_cmd_buffer *const cmd_buffer,
cmd);
}
state->emit_header = (struct PVRX(TA_STATE_HEADER)){ 0 };
state->emit_header = (struct ROGUE_TA_STATE_HEADER){ 0 };
return VK_SUCCESS;
}
@@ -5939,7 +5939,7 @@ pvr_ppp_state_update_required(const struct pvr_cmd_buffer *cmd_buffer)
const BITSET_WORD *const dynamic_dirty =
cmd_buffer->vk.dynamic_graphics_state.dirty;
const struct pvr_cmd_buffer_state *const state = &cmd_buffer->state;
const struct PVRX(TA_STATE_HEADER) *const header = &state->emit_header;
const struct ROGUE_TA_STATE_HEADER *const header = &state->emit_header;
/* For push constants we only need to worry if they are updated for the
* fragment stage since we're only updating the pds programs used in the
@@ -5990,7 +5990,7 @@ pvr_emit_dirty_ppp_state(struct pvr_cmd_buffer *const cmd_buffer,
return VK_SUCCESS;
if (state->dirty.gfx_pipeline_binding) {
struct PVRX(TA_STATE_ISPA) ispa;
struct ROGUE_TA_STATE_ISPA ispa;
pvr_setup_output_select(cmd_buffer);
pvr_setup_isp_faces_and_control(cmd_buffer, &ispa);
@@ -6122,8 +6122,8 @@ static void pvr_emit_dirty_vdm_state(struct pvr_cmd_buffer *const cmd_buffer,
&cmd_buffer->device->pdevice->dev_info;
ASSERTED const uint32_t max_user_vertex_output_components =
pvr_get_max_user_vertex_output_components(dev_info);
struct PVRX(VDMCTRL_VDM_STATE0)
header = { pvr_cmd_header(VDMCTRL_VDM_STATE0) };
struct ROGUE_VDMCTRL_VDM_STATE0 header = { pvr_cmd_header(
VDMCTRL_VDM_STATE0) };
struct vk_dynamic_graphics_state *const dynamic_state =
&cmd_buffer->vk.dynamic_graphics_state;
const struct pvr_cmd_buffer_state *const state = &cmd_buffer->state;
@@ -6137,7 +6137,7 @@ static void pvr_emit_dirty_vdm_state(struct pvr_cmd_buffer *const cmd_buffer,
/* CAM Calculations and HW state take vertex size aligned to DWORDS. */
vs_output_size =
DIV_ROUND_UP(vertex_shader_state->vertex_output_size,
PVRX(VDMCTRL_VDM_STATE4_VS_OUTPUT_SIZE_UNIT_SIZE));
ROGUE_VDMCTRL_VDM_STATE4_VS_OUTPUT_SIZE_UNIT_SIZE);
assert(vs_output_size <= max_user_vertex_output_components);
@@ -6159,11 +6159,11 @@ static void pvr_emit_dirty_vdm_state(struct pvr_cmd_buffer *const cmd_buffer,
switch (dynamic_state->ia.primitive_topology) {
case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
state0.flatshade_control = PVRX(VDMCTRL_FLATSHADE_CONTROL_VERTEX_1);
state0.flatshade_control = ROGUE_VDMCTRL_FLATSHADE_CONTROL_VERTEX_1;
break;
default:
state0.flatshade_control = PVRX(VDMCTRL_FLATSHADE_CONTROL_VERTEX_0);
state0.flatshade_control = ROGUE_VDMCTRL_FLATSHADE_CONTROL_VERTEX_0;
break;
}
@@ -6190,7 +6190,7 @@ static void pvr_emit_dirty_vdm_state(struct pvr_cmd_buffer *const cmd_buffer,
* always emitted to the UVB.
*/
state0.uvs_scratch_size_select =
PVRX(VDMCTRL_UVS_SCRATCH_SIZE_SELECT_FIVE);
ROGUE_VDMCTRL_UVS_SCRATCH_SIZE_SELECT_FIVE;
header = state0;
}
@@ -6227,13 +6227,13 @@ static void pvr_emit_dirty_vdm_state(struct pvr_cmd_buffer *const cmd_buffer,
state5.vs_usc_common_size = 0U;
state5.vs_usc_unified_size = DIV_ROUND_UP(
usc_unified_store_size_in_bytes,
PVRX(VDMCTRL_VDM_STATE5_VS_USC_UNIFIED_SIZE_UNIT_SIZE));
ROGUE_VDMCTRL_VDM_STATE5_VS_USC_UNIFIED_SIZE_UNIT_SIZE);
state5.vs_pds_temp_size =
DIV_ROUND_UP(state->pds_shader.info->temps_required << 2,
PVRX(VDMCTRL_VDM_STATE5_VS_PDS_TEMP_SIZE_UNIT_SIZE));
ROGUE_VDMCTRL_VDM_STATE5_VS_PDS_TEMP_SIZE_UNIT_SIZE);
state5.vs_pds_data_size = DIV_ROUND_UP(
PVR_DW_TO_BYTES(state->pds_shader.info->data_size_in_dwords),
PVRX(VDMCTRL_VDM_STATE5_VS_PDS_DATA_SIZE_UNIT_SIZE));
ROGUE_VDMCTRL_VDM_STATE5_VS_PDS_DATA_SIZE_UNIT_SIZE);
}
}
@@ -6283,10 +6283,10 @@ static VkResult pvr_validate_draw_state(struct pvr_cmd_buffer *cmd_buffer)
compute_overlap)) {
uint32_t coefficient_size =
DIV_ROUND_UP(fragment_state->coefficient_size,
PVRX(TA_STATE_PDS_SIZEINFO1_USC_VARYINGSIZE_UNIT_SIZE));
ROGUE_TA_STATE_PDS_SIZEINFO1_USC_VARYINGSIZE_UNIT_SIZE);
if (coefficient_size >
PVRX(TA_STATE_PDS_SIZEINFO1_USC_VARYINGSIZE_MAX_SIZE))
ROGUE_TA_STATE_PDS_SIZEINFO1_USC_VARYINGSIZE_MAX_SIZE)
sub_cmd->disable_compute_overlap = true;
}
@@ -6426,27 +6426,27 @@ static uint32_t pvr_get_hw_primitive_topology(VkPrimitiveTopology topology)
{
switch (topology) {
case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
return PVRX(VDMCTRL_PRIMITIVE_TOPOLOGY_POINT_LIST);
return ROGUE_VDMCTRL_PRIMITIVE_TOPOLOGY_POINT_LIST;
case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
return PVRX(VDMCTRL_PRIMITIVE_TOPOLOGY_LINE_LIST);
return ROGUE_VDMCTRL_PRIMITIVE_TOPOLOGY_LINE_LIST;
case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
return PVRX(VDMCTRL_PRIMITIVE_TOPOLOGY_LINE_STRIP);
return ROGUE_VDMCTRL_PRIMITIVE_TOPOLOGY_LINE_STRIP;
case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
return PVRX(VDMCTRL_PRIMITIVE_TOPOLOGY_TRI_LIST);
return ROGUE_VDMCTRL_PRIMITIVE_TOPOLOGY_TRI_LIST;
case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
return PVRX(VDMCTRL_PRIMITIVE_TOPOLOGY_TRI_STRIP);
return ROGUE_VDMCTRL_PRIMITIVE_TOPOLOGY_TRI_STRIP;
case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
return PVRX(VDMCTRL_PRIMITIVE_TOPOLOGY_TRI_FAN);
return ROGUE_VDMCTRL_PRIMITIVE_TOPOLOGY_TRI_FAN;
case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
return PVRX(VDMCTRL_PRIMITIVE_TOPOLOGY_LINE_LIST_ADJ);
return ROGUE_VDMCTRL_PRIMITIVE_TOPOLOGY_LINE_LIST_ADJ;
case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
return PVRX(VDMCTRL_PRIMITIVE_TOPOLOGY_LINE_STRIP_ADJ);
return ROGUE_VDMCTRL_PRIMITIVE_TOPOLOGY_LINE_STRIP_ADJ;
case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
return PVRX(VDMCTRL_PRIMITIVE_TOPOLOGY_TRI_LIST_ADJ);
return ROGUE_VDMCTRL_PRIMITIVE_TOPOLOGY_TRI_LIST_ADJ;
case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
return PVRX(VDMCTRL_PRIMITIVE_TOPOLOGY_TRI_STRIP_ADJ);
return ROGUE_VDMCTRL_PRIMITIVE_TOPOLOGY_TRI_STRIP_ADJ;
case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
return PVRX(VDMCTRL_PRIMITIVE_TOPOLOGY_PATCH_LIST);
return ROGUE_VDMCTRL_PRIMITIVE_TOPOLOGY_PATCH_LIST;
default:
unreachable("Undefined primitive topology");
}
@@ -6461,7 +6461,7 @@ pvr_write_draw_indirect_vdm_stream(struct pvr_cmd_buffer *cmd_buffer,
struct pvr_csb *const csb,
pvr_dev_addr_t idx_buffer_addr,
uint32_t idx_stride,
struct PVRX(VDMCTRL_INDEX_LIST0) * list_hdr,
struct ROGUE_VDMCTRL_INDEX_LIST0 *list_hdr,
struct pvr_buffer *buffer,
VkDeviceSize offset,
uint32_t count,
@@ -6553,15 +6553,15 @@ pvr_write_draw_indirect_vdm_stream(struct pvr_cmd_buffer *cmd_buffer,
pvr_csb_set_relocation_mark(csb);
pvr_csb_emit (csb, VDMCTRL_PDS_STATE0, state0) {
state0.usc_target = PVRX(VDMCTRL_USC_TARGET_ANY);
state0.usc_target = ROGUE_VDMCTRL_USC_TARGET_ANY;
state0.pds_temp_size =
DIV_ROUND_UP(PVR_DW_TO_BYTES(pds_prog.program.temp_size_aligned),
PVRX(VDMCTRL_PDS_STATE0_PDS_TEMP_SIZE_UNIT_SIZE));
ROGUE_VDMCTRL_PDS_STATE0_PDS_TEMP_SIZE_UNIT_SIZE);
state0.pds_data_size =
DIV_ROUND_UP(PVR_DW_TO_BYTES(pds_prog.program.data_size_aligned),
PVRX(VDMCTRL_PDS_STATE0_PDS_DATA_SIZE_UNIT_SIZE));
ROGUE_VDMCTRL_PDS_STATE0_PDS_DATA_SIZE_UNIT_SIZE);
}
pvr_csb_emit (csb, VDMCTRL_PDS_STATE1, state1) {
@@ -6571,8 +6571,8 @@ pvr_write_draw_indirect_vdm_stream(struct pvr_cmd_buffer *cmd_buffer,
cmd_buffer->device->heaps.pds_heap->base_addr.addr;
state1.pds_data_addr = PVR_DEV_ADDR(data_offset);
state1.sd_type = PVRX(VDMCTRL_SD_TYPE_PDS);
state1.sd_next_type = PVRX(VDMCTRL_SD_TYPE_NONE);
state1.sd_type = ROGUE_VDMCTRL_SD_TYPE_PDS;
state1.sd_next_type = ROGUE_VDMCTRL_SD_TYPE_NONE;
}
pvr_csb_emit (csb, VDMCTRL_PDS_STATE2, state2) {
@@ -6594,7 +6594,7 @@ pvr_write_draw_indirect_vdm_stream(struct pvr_cmd_buffer *cmd_buffer,
* before they are ready.
*/
pvr_csb_emit (csb, VDMCTRL_INDEX_LIST0, list0) {
list0.primitive_topology = PVRX(VDMCTRL_PRIMITIVE_TOPOLOGY_TRI_LIST);
list0.primitive_topology = ROGUE_VDMCTRL_PRIMITIVE_TOPOLOGY_TRI_LIST;
}
pvr_csb_clear_relocation_mark(csb);
@@ -6658,8 +6658,8 @@ static void pvr_emit_vdm_index_list(struct pvr_cmd_buffer *cmd_buffer,
struct pvr_cmd_buffer_state *state = &cmd_buffer->state;
const bool vertex_shader_has_side_effects =
state->gfx_pipeline->shader_state.vertex.stage_state.has_side_effects;
struct PVRX(VDMCTRL_INDEX_LIST0)
list_hdr = { pvr_cmd_header(VDMCTRL_INDEX_LIST0) };
struct ROGUE_VDMCTRL_INDEX_LIST0 list_hdr = { pvr_cmd_header(
VDMCTRL_INDEX_LIST0) };
pvr_dev_addr_t index_buffer_addr = PVR_DEV_ADDR_INVALID;
struct pvr_csb *const csb = &sub_cmd->control_stream;
unsigned int index_stride = 0;
@@ -7518,7 +7518,7 @@ void pvr_CmdNextSubpass2(VkCommandBuffer commandBuffer,
/* If hw_subpass_load_op is valid then pvr_write_load_op_control_stream
* has already done a full-screen transparent object.
*/
if (rp_info->isp_userpass == PVRX(CR_ISP_CTL_UPASS_START_SIZE_MAX) &&
if (rp_info->isp_userpass == ROGUE_CR_ISP_CTL_UPASS_START_SIZE_MAX &&
!hw_subpass_load_op) {
pvr_insert_transparent_obj(cmd_buffer, &state->current_sub_cmd->gfx);
}