From 141a225ca136e7a7e6368e5999c793428c363978 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Jos=C3=A9=20Roberto=20de=20Souza?= <jose.souza@intel.com>
Date: Wed, 24 Sep 2025 13:55:00 -0700
Subject: [PATCH] intel/brw: Use ASR over SHR for SHADER_OPCODE_ISUB_SAT
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src[1]/src0 is signed and Xe2+ SHR don't support operations over signed
data types so lets switch this over ASR that supports signed data
types.

Cc: mesa-stable
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37557>
---
 src/intel/compiler/brw_lower.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/intel/compiler/brw_lower.cpp b/src/intel/compiler/brw_lower.cpp
index a1e82968eb1..3ffdc1d5535 100644
--- a/src/intel/compiler/brw_lower.cpp
+++ b/src/intel/compiler/brw_lower.cpp
@@ -235,7 +235,7 @@ brw_lower_sub_sat(brw_shader &s)
             brw_inst *add;
 
             brw_reg tmp = ibld.vgrf(inst->src[0].type);
-            ibld.SHR(tmp, inst->src[1], brw_imm_d(1));
+            ibld.ASR(tmp, inst->src[1], brw_imm_ud(1));
 
             brw_reg s1_sub_t = ibld.ADD(inst->src[1], negate(tmp));
             brw_reg sat_s0_sub_t = ibld.ADD(inst->src[0], negate(tmp), &add);