AlexIndustrial/mesa
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

intel/fs: drop FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GFX7

Browse Source 
We can lower FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD into other more
generic sends and drop this internal opcode.

The idea behind this change is to allow bindless surfaces to be used
for UBO pulls and why it's interesting to be able to reuse
setup_surface_descriptors(). But that will come in a later change.

No shader-db changes on TGL & DG2.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20416>
This commit is contained in:
Lionel Landwerlin
2022-12-21 20:16:27 +02:00
committed by Marge Bot
parent 5bc91550d1
commit 13cca48920
9 changed files with 154 additions and 191 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/intel/compiler/brw_fs_generator.cpp
-67
View File
@@ -1553,67 +1553,6 @@ fs_generator::generate_uniform_pull_constant_load(fs_inst *inst,
read_offset, surf_index);
}
void
fs_generator::generate_uniform_pull_constant_load_gfx7(fs_inst *inst,
struct brw_reg dst,
struct brw_reg index,
struct brw_reg payload)
{
assert(index.type == BRW_REGISTER_TYPE_UD);
assert(payload.file == BRW_GENERAL_REGISTER_FILE);
assert(type_sz(dst.type) == 4);
assert(!devinfo->has_lsc);
if (index.file == BRW_IMMEDIATE_VALUE) {
const uint32_t surf_index = index.ud;
brw_push_insn_state(p);
brw_set_default_mask_control(p, BRW_MASK_DISABLE);
brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
brw_pop_insn_state(p);
brw_inst_set_sfid(devinfo, send, GFX6_SFID_DATAPORT_CONSTANT_CACHE);
brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UD));
brw_set_src0(p, send, retype(payload, BRW_REGISTER_TYPE_UD));
brw_set_desc(p, send,
brw_message_desc(devinfo, 1, DIV_ROUND_UP(inst->size_written,
REG_SIZE), true) |
brw_dp_desc(devinfo, surf_index,
GFX7_DATAPORT_DC_OWORD_BLOCK_READ,
BRW_DATAPORT_OWORD_BLOCK_DWORDS(inst->exec_size)));
} else {
const tgl_swsb swsb = brw_get_default_swsb(p);
struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
brw_push_insn_state(p);
brw_set_default_mask_control(p, BRW_MASK_DISABLE);
/* a0.0 = surf_index & 0xff */
brw_set_default_swsb(p, tgl_swsb_src_dep(swsb));
brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
brw_inst_set_exec_size(p->devinfo, insn_and, BRW_EXECUTE_1);
brw_set_dest(p, insn_and, addr);
brw_set_src0(p, insn_and, vec1(retype(index, BRW_REGISTER_TYPE_UD)));
brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
/* dst = send(payload, a0.0 | <descriptor>) */
brw_set_default_swsb(p, tgl_swsb_dst_dep(swsb, 1));
brw_send_indirect_message(
p, GFX6_SFID_DATAPORT_CONSTANT_CACHE,
retype(dst, BRW_REGISTER_TYPE_UD),
retype(payload, BRW_REGISTER_TYPE_UD), addr,
brw_message_desc(devinfo, 1,
DIV_ROUND_UP(inst->size_written, REG_SIZE), true) |
brw_dp_desc(devinfo, 0 /* surface */,
GFX7_DATAPORT_DC_OWORD_BLOCK_READ,
BRW_DATAPORT_OWORD_BLOCK_DWORDS(inst->exec_size)),
false /* EOT */);
brw_pop_insn_state(p);
}
}
void
fs_generator::generate_varying_pull_constant_load_gfx4(fs_inst *inst,
struct brw_reg dst,
@@ -2294,12 +2233,6 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width,
send_count++;
break;
case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GFX7:
assert(inst->force_writemask_all);
generate_uniform_pull_constant_load_gfx7(inst, dst, src[0], src[1]);
send_count++;
break;
case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GFX4:
generate_varying_pull_constant_load_gfx4(inst, dst, src[0]);
send_count++;