diff --git a/src/freedreno/.gitlab-ci/reference/dEQP-GLES2.functional.texture.specification.basic_teximage2d.rgba16f_2d.log b/src/freedreno/.gitlab-ci/reference/dEQP-GLES2.functional.texture.specification.basic_teximage2d.rgba16f_2d.log
index c13c45826d3..d196b66b0d1 100644
--- a/src/freedreno/.gitlab-ci/reference/dEQP-GLES2.functional.texture.specification.basic_teximage2d.rgba16f_2d.log
+++ b/src/freedreno/.gitlab-ci/reference/dEQP-GLES2.functional.texture.specification.basic_teximage2d.rgba16f_2d.log
@@ -2,158 +2,158 @@ gpu_id: 201
 cmd: deqp-gles2/185: fence=1250
 ############################################################
 cmdstream[0]: 124 dwords
-t0		write RB_BC_CONTROL (0f01)
+		write RB_BC_CONTROL (0f01)
 			RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 }
 0122d000:		0000: 00000f01 1c004046
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 }
 0122d008:		0000: c0012d00 00040293 00000020
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
 0122d014:		0000: c0012d00 00040316 00000002
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 }
 0122d020:		0000: c0012d00 00040317 00000002
-t0		write CP_PERFMON_CNTL (0444)
+		write CP_PERFMON_CNTL (0444)
 			CP_PERFMON_CNTL: 0
 0122d02c:		0000: 00000444 00000000
-t0		write RBBM_PM_OVERRIDE1 (039c)
+		write RBBM_PM_OVERRIDE1 (039c)
 			RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
 			RBBM_PM_OVERRIDE2: 0xfff
 0122d034:		0000: 0001039c ffffffff 00000fff
-t0		write TP0_CHICKEN (0e1e)
+		write TP0_CHICKEN (0e1e)
 			TP0_CHICKEN: 0x2
 0122d040:		0000: 00000e1e 00000002
-t3		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
+		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
 0122d048:		0000: c0003b00 00007fff
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			SQ_VS_CONST: { BASE = 32 | SIZE = 256 }
 0122d050:		0000: c0012d00 00040307 00100020
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			SQ_PS_CONST: { BASE = 288 | SIZE = 224 }
 0122d05c:		0000: c0012d00 00040308 000e0120
-t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
+		opcode: CP_SET_CONSTANT (2d) (4 dwords)
 			VGT_MAX_VTX_INDX: 0xffffffff
 			VGT_MIN_VTX_INDX: 0
 0122d068:		0000: c0022d00 00040100 ffffffff 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			VGT_INDX_OFFSET: 0
 0122d078:		0000: c0012d00 00040102 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			SQ_CONTEXT_MISC: { SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 }
 0122d084:		0000: c0012d00 00040181 00000004
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 }
 0122d090:		0000: c0012d00 00040182 ffffffff
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
 0122d09c:		0000: c0012d00 00040301 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_LINE_CNTL: { BRES_CNTL = 0 }
 0122d0a8:		0000: c0012d00 00040300 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
 0122d0b4:		0000: c0012d00 00040080 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
 0122d0c0:		0000: c0012d00 00040208 00000004
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_SAMPLE_POS: 0x88888888
 0122d0cc:		0000: c0012d00 0004020a 88888888
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_COLOR_DEST_MASK: 0xffffffff
 0122d0d8:		0000: c0012d00 00040326 ffffffff
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 0122d0e4:		0000: c0012d00 0004031b 0003c000
-t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
+		opcode: CP_SET_CONSTANT (2d) (4 dwords)
 			SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 }
 			SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 }
 0122d0f0:		0000: c0022d00 00040183 00000000 00000000
-t3		opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords)
+		opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords)
 0122d100:		0000: c0004b00 00000000
-t3		opcode: CP_WAIT_REG_EQ (52) (5 dwords)
+		opcode: CP_WAIT_REG_EQ (52) (5 dwords)
 0122d108:		0000: c0035200 000005d0 00000000 5f601000 00000001
-t0		write SQ_INST_STORE_MANAGMENT (0d02)
+		write SQ_INST_STORE_MANAGMENT (0d02)
 			SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 }
 0122d11c:		0000: 00000d02 00000180
-t3		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
+		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
 0122d124:		0000: c0003b00 00000300
-t3		opcode: CP_SET_SHADER_BASES (4a) (2 dwords)
+		opcode: CP_SET_SHADER_BASES (4a) (2 dwords)
 0122d12c:		0000: c0004a00 80000180
-t3		opcode: CP_SET_CONSTANT (2d) (14 dwords)
+		opcode: CP_SET_CONSTANT (2d) (14 dwords)
 0122d13c:			0.000000 0.000000 0.000000 0.000000 20000.000000 1.000000 0.500000 0.000000
 0122d15c:			2.000000 0.750000 0.375000 0.250000
 0122d134:		0000: c00c2d00 00000000 00000000 00000000 00000000 00000000 469c4000 3f800000
 0122d154:		0020: 3f000000 00000000 40000000 3f400000 3ec00000 3e800000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 0122d16c:		0000: c0012d00 00040104 0000000f
-t3		opcode: CP_SET_CONSTANT (2d) (6 dwords)
+		opcode: CP_SET_CONSTANT (2d) (6 dwords)
 			RB_BLEND_RED: 0
 			RB_BLEND_GREEN: 0
 			RB_BLEND_BLUE: 0
 			RB_BLEND_ALPHA: 0xff
 0122d178:		0000: c0042d00 00040105 00000000 00000000 00000000 000000ff
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT }
 0122d190:		0000: c0012d00 00040206 0000043f
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_SURFACE_INFO: { SURFACE_PITCH = 64 | MSAA_SAMPLES = 0 }
 0122d19c:		0000: c0012d00 00040000 00000040
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_COLOR_INFO: { FORMAT = COLORX_16_16_16_16_FLOAT | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0x110d000 }
 0122d1a8:		0000: c0012d00 00040001 0110d009
-t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
+		opcode: CP_SET_CONSTANT (2d) (4 dwords)
 			PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 }
 			PA_SC_SCREEN_SCISSOR_BR: { X = 64 | Y = 128 }
 0122d1b4:		0000: c0022d00 0004000e 80000000 00800040
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
 0122d1c4:		0000: c0012d00 00040080 00000000
-t0		write CP_SCRATCH_REG6 (057e)
+		write CP_SCRATCH_REG6 (057e)
 			CP_SCRATCH_REG6: 9
 			:0,0,9,0
 0122d1d0:		0000: 0000057e 00000009
-t3		opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
+		opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
 		ibaddr:0122e000
 		ibsize:000000b6
-t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
+			opcode: CP_SET_CONSTANT (2d) (6 dwords)
 			set shader const 0078
 0122e000:			0000: c0042d00 00010078 0112d003 00100000 0112d003 00100000
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				PA_SC_AA_MASK: 0xffff
 0122e018:			0000: c0012d00 00040312 0000ffff
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
 0122e024:			0000: c0012d00 00040200 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (5 dwords)
+			opcode: CP_SET_CONSTANT (2d) (5 dwords)
 				RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
 				RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
 				RB_ALPHA_REF: 0
 0122e030:			0000: c0032d00 0004010c 00000000 00000000 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
+			opcode: CP_SET_CONSTANT (2d) (4 dwords)
 				PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
 				PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST }
 0122e044:			0000: c0022d00 00040204 00000000 00090244
-t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
+			opcode: CP_SET_CONSTANT (2d) (6 dwords)
 				PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 }
 				PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 }
 				PA_SU_LINE_CNTL: { WIDTH = 0.000000 }
 				PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER }
 0122e054:			0000: c0042d00 00040280 00000000 00000000 00000000 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (7 dwords)
+			opcode: CP_SET_CONSTANT (2d) (7 dwords)
 				PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH }
 				PA_CL_GB_VERT_CLIP_ADJ: 1.000000
 				PA_CL_GB_VERT_DISC_ADJ: 1.000000
 				PA_CL_GB_HORZ_CLIP_ADJ: 1.000000
 				PA_CL_GB_HORZ_DISC_ADJ: 1.000000
 0122e06c:			0000: c0052d00 00040302 00000001 3f800000 3f800000 3f800000 3f800000
-t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
+			opcode: CP_SET_CONSTANT (2d) (4 dwords)
 				PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
 				PA_SC_WINDOW_SCISSOR_BR: { X = 64 | Y = 128 }
 0122e088:			0000: c0022d00 00040081 00000000 00800040
-t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
+			opcode: CP_SET_CONSTANT (2d) (8 dwords)
 				PA_CL_VPORT_XSCALE: 32.000000
 				PA_CL_VPORT_XOFFSET: 32.000000
 				PA_CL_VPORT_YSCALE: 64.000000
@@ -161,11 +161,11 @@ t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
 				PA_CL_VPORT_ZSCALE: 0.000000
 				PA_CL_VPORT_ZOFFSET: 0.000000
 0122e098:			0000: c0062d00 0004010f 42000000 42000000 42800000 42800000 00000000 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (10 dwords)
+			opcode: CP_SET_CONSTANT (2d) (10 dwords)
 0122e0c0:				32.000000 64.000000 0.000000 0.000000 32.000000 64.000000 0.000000 0.000000
 0122e0b8:			0000: c0082d00 00000184 42000000 42800000 00000000 00000000 42000000 42800000
 *
-t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords)
+			opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords)
 			vertex shader, start=0000, size=0015
 					    2003 0007 1000            	EXEC ADDR(0x3) CNT(0x2)
 					03: 19481000 00262688 00000020	   (S)FETCH:	VERTEX	R1.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) CONST(20, 0)
@@ -180,7 +180,7 @@ t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords)
 0122e0e0:			0000: c0162b00 00000000 00000015 00072003 00001000 c2000000 00021005 00001000
 0122e100:			0020: c4000000 00001006 00002000 00000000 19481000 00262688 00000020 13480000
 0122e120:			0040: 40262688 00001020 000f803e 00000000 c2010100 000f8000 00000000 c2000000
-t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
+			opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
 			fragment shader, start=0000, size=000c
 					    1002 0003 1000            	EXEC ADDR(0x2) CNT(0x1)
 					02: 90000001 1ffff688 00000002	   (S)FETCH:	SAMPLE	R0.xyzw = R0.xyz CONST(0) LOCATION(CENTER)
@@ -190,31 +190,31 @@ t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
 					    0000 0000 0000            	NOP
 0122e140:			0000: c00d2b00 00000001 0000000c 00031002 00001000 c4000000 00021003 00002000
 0122e160:			0020: 00000000 90000001 1ffff688 00000002 000f8000 00000000 c2000000
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 }
 0122e17c:			0000: c0012d00 00040181 00000106
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
 0122e188:			0000: c0012d00 00040180 10030002
-t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
+			opcode: CP_SET_CONSTANT (2d) (6 dwords)
 0122e19c:				0.000000 0.000000 0.000000 0.000000
 0122e194:			0000: c0042d00 00000080 00000000 00000000 00000000 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
 0122e1ac:			0000: c0012d00 00040202 00000c20
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
 0122e1b8:			0000: c0012d00 00040201 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 0122e1c4:			0000: c0012d00 00040104 0000000f
-t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
+			opcode: CP_SET_CONSTANT (2d) (6 dwords)
 				RB_BLEND_RED: 0
 				RB_BLEND_GREEN: 0
 				RB_BLEND_BLUE: 0
 				RB_BLEND_ALPHA: 0
 0122e1d0:			0000: c0042d00 00040105 00000000 00000000 00000000 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
+			opcode: CP_SET_CONSTANT (2d) (8 dwords)
 			set texture const 0000
 				clamp x/y/z: clamp-last-texel/clamp-last-texel/clamp-last-texel
 				filter min/mag: point/point
@@ -222,23 +222,23 @@ t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
 				addr=0111d000 (flags=820), size=64x128, pitch=64, format=FMT_1_REVERSE
 				mipaddr=00000000 (flags=200)
 0122e1e8:			0000: c0062d00 00010000 00824800 0111d820 000fe03f 00000d11 00000000 00000200
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				VGT_INDX_OFFSET: 0
 0122e208:			0000: c0012d00 00040102 00000000
-t0			write TC_CNTL_STATUS (0e00)
+			write TC_CNTL_STATUS (0e00)
 				TC_CNTL_STATUS: { L2_INVALIDATE }
 0122e214:			0000: 00000e00 00000001
-t3			opcode: CP_WAIT_REG_EQ (52) (5 dwords)
+			opcode: CP_WAIT_REG_EQ (52) (5 dwords)
 0122e21c:			0000: c0035200 000005d0 00000000 00001000 00000001
-t3			opcode: CP_DRAW_INDX_BIN (34) (7 dwords)
+			opcode: CP_DRAW_INDX_BIN (34) (7 dwords)
 0122e230:			0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 5
 				:0,0,9,5
 0122e24c:			0000: 0000057f 00000005
-t3			opcode: CP_NOP (10) (2 dwords)
+			opcode: CP_NOP (10) (2 dwords)
 0122e254:			0000: c0001000 00000000
-t3			opcode: CP_DRAW_INDX (22) (3 dwords)
+			opcode: CP_DRAW_INDX (22) (3 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRIFAN | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x40000 }
 			draw:          0
@@ -314,220 +314,220 @@ t3			opcode: CP_DRAW_INDX (22) (3 dwords)
 !+	0003c000			RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 !+	ffffffff			RB_COLOR_DEST_MASK: 0xffffffff
 0122e25c:			0000: c0012200 00000000 00040085
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 6
 				:0,0,9,6
 0122e268:			0000: 0000057f 00000006
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 0122e270:			0000: c0002600 00000000
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e278:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e280:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e288:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e290:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e298:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2a0:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2a8:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2b0:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2b8:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2c0:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2c8:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2d0:			0000: c0004600 00000006
 0122d1d8:		0000: c0013700 0122e000 000000b6
-t2		nop
+		nop
 ############################################################
 vertices: 0
 cmd: deqp-gles2/185: fence=1251
 ############################################################
 cmdstream[1]: 124 dwords
-t0		write RB_BC_CONTROL (0f01)
+		write RB_BC_CONTROL (0f01)
 			RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 }
 0122f000:		0000: 00000f01 1c004046
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 }
 0122f008:		0000: c0012d00 00040293 00000020
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
 0122f014:		0000: c0012d00 00040316 00000002
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 }
 0122f020:		0000: c0012d00 00040317 00000002
-t0		write CP_PERFMON_CNTL (0444)
+		write CP_PERFMON_CNTL (0444)
 			CP_PERFMON_CNTL: 0
 0122f02c:		0000: 00000444 00000000
-t0		write RBBM_PM_OVERRIDE1 (039c)
+		write RBBM_PM_OVERRIDE1 (039c)
 			RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
 			RBBM_PM_OVERRIDE2: 0xfff
 0122f034:		0000: 0001039c ffffffff 00000fff
-t0		write TP0_CHICKEN (0e1e)
+		write TP0_CHICKEN (0e1e)
 			TP0_CHICKEN: 0x2
 0122f040:		0000: 00000e1e 00000002
-t3		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
+		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
 0122f048:		0000: c0003b00 00007fff
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			SQ_VS_CONST: { BASE = 32 | SIZE = 256 }
 0122f050:		0000: c0012d00 00040307 00100020
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			SQ_PS_CONST: { BASE = 288 | SIZE = 224 }
 0122f05c:		0000: c0012d00 00040308 000e0120
-t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
+		opcode: CP_SET_CONSTANT (2d) (4 dwords)
 			VGT_MAX_VTX_INDX: 0xffffffff
 			VGT_MIN_VTX_INDX: 0
 0122f068:		0000: c0022d00 00040100 ffffffff 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			VGT_INDX_OFFSET: 0
 0122f078:		0000: c0012d00 00040102 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			SQ_CONTEXT_MISC: { SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 }
 0122f084:		0000: c0012d00 00040181 00000004
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 }
 0122f090:		0000: c0012d00 00040182 ffffffff
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
 0122f09c:		0000: c0012d00 00040301 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_LINE_CNTL: { BRES_CNTL = 0 }
 0122f0a8:		0000: c0012d00 00040300 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
 0122f0b4:		0000: c0012d00 00040080 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
 0122f0c0:		0000: c0012d00 00040208 00000004
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_SAMPLE_POS: 0x88888888
 0122f0cc:		0000: c0012d00 0004020a 88888888
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_COLOR_DEST_MASK: 0xffffffff
 0122f0d8:		0000: c0012d00 00040326 ffffffff
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 0122f0e4:		0000: c0012d00 0004031b 0003c000
-t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
+		opcode: CP_SET_CONSTANT (2d) (4 dwords)
 			SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 }
 			SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 }
 0122f0f0:		0000: c0022d00 00040183 00000000 00000000
-t3		opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords)
+		opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords)
 0122f100:		0000: c0004b00 00000000
-t3		opcode: CP_WAIT_REG_EQ (52) (5 dwords)
+		opcode: CP_WAIT_REG_EQ (52) (5 dwords)
 0122f108:		0000: c0035200 000005d0 00000000 5f601000 00000001
-t0		write SQ_INST_STORE_MANAGMENT (0d02)
+		write SQ_INST_STORE_MANAGMENT (0d02)
 			SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 }
 0122f11c:		0000: 00000d02 00000180
-t3		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
+		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
 0122f124:		0000: c0003b00 00000300
-t3		opcode: CP_SET_SHADER_BASES (4a) (2 dwords)
+		opcode: CP_SET_SHADER_BASES (4a) (2 dwords)
 0122f12c:		0000: c0004a00 80000180
-t3		opcode: CP_SET_CONSTANT (2d) (14 dwords)
+		opcode: CP_SET_CONSTANT (2d) (14 dwords)
 0122f13c:			0.000000 0.000000 0.000000 0.000000 20000.000000 1.000000 0.500000 0.000000
 0122f15c:			2.000000 0.750000 0.375000 0.250000
 0122f134:		0000: c00c2d00 00000000 00000000 00000000 00000000 00000000 469c4000 3f800000
 0122f154:		0020: 3f000000 00000000 40000000 3f400000 3ec00000 3e800000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 0122f16c:		0000: c0012d00 00040104 0000000f
-t3		opcode: CP_SET_CONSTANT (2d) (6 dwords)
+		opcode: CP_SET_CONSTANT (2d) (6 dwords)
 			RB_BLEND_RED: 0
 			RB_BLEND_GREEN: 0
 			RB_BLEND_BLUE: 0
 			RB_BLEND_ALPHA: 0xff
 0122f178:		0000: c0042d00 00040105 00000000 00000000 00000000 000000ff
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT }
 0122f190:		0000: c0012d00 00040206 0000043f
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 }
 0122f19c:		0000: c0012d00 00040000 00000020
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_COLOR_INFO: { FORMAT = COLORX_16_16_16_16_FLOAT | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0x1240000 }
 0122f1a8:		0000: c0012d00 00040001 01240009
-t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
+		opcode: CP_SET_CONSTANT (2d) (4 dwords)
 			PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 }
 			PA_SC_SCREEN_SCISSOR_BR: { X = 32 | Y = 64 }
 0122f1b4:		0000: c0022d00 0004000e 80000000 00400020
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
 0122f1c4:		0000: c0012d00 00040080 00000000
-t0		write CP_SCRATCH_REG6 (057e)
+		write CP_SCRATCH_REG6 (057e)
 			CP_SCRATCH_REG6: 15
 			:0,0,15,6
 0122f1d0:		0000: 0000057e 0000000f
-t3		opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
+		opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
 		ibaddr:0122e000
 		ibsize:000000b6
-t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
+			opcode: CP_SET_CONSTANT (2d) (6 dwords)
 			set shader const 0078
 0122e000:			0000: c0042d00 00010078 0112d083 00100000 0112d083 00100000
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				PA_SC_AA_MASK: 0xffff
 0122e018:			0000: c0012d00 00040312 0000ffff
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
 0122e024:			0000: c0012d00 00040200 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (5 dwords)
+			opcode: CP_SET_CONSTANT (2d) (5 dwords)
 				RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
 				RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
 				RB_ALPHA_REF: 0
 0122e030:			0000: c0032d00 0004010c 00000000 00000000 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
+			opcode: CP_SET_CONSTANT (2d) (4 dwords)
 				PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
 				PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST }
 0122e044:			0000: c0022d00 00040204 00000000 00090244
-t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
+			opcode: CP_SET_CONSTANT (2d) (6 dwords)
 				PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 }
 				PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 }
 				PA_SU_LINE_CNTL: { WIDTH = 0.000000 }
 				PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER }
 0122e054:			0000: c0042d00 00040280 00000000 00000000 00000000 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (7 dwords)
+			opcode: CP_SET_CONSTANT (2d) (7 dwords)
 				PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH }
 				PA_CL_GB_VERT_CLIP_ADJ: 1.000000
 				PA_CL_GB_VERT_DISC_ADJ: 1.000000
 				PA_CL_GB_HORZ_CLIP_ADJ: 1.000000
 				PA_CL_GB_HORZ_DISC_ADJ: 1.000000
 0122e06c:			0000: c0052d00 00040302 00000001 3f800000 3f800000 3f800000 3f800000
-t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
+			opcode: CP_SET_CONSTANT (2d) (4 dwords)
 				PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
 				PA_SC_WINDOW_SCISSOR_BR: { X = 32 | Y = 64 }
 0122e088:			0000: c0022d00 00040081 00000000 00400020
-t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
+			opcode: CP_SET_CONSTANT (2d) (8 dwords)
 				PA_CL_VPORT_XSCALE: 16.000000
 				PA_CL_VPORT_XOFFSET: 16.000000
 				PA_CL_VPORT_YSCALE: 32.000000
@@ -535,11 +535,11 @@ t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
 				PA_CL_VPORT_ZSCALE: 0.000000
 				PA_CL_VPORT_ZOFFSET: 0.000000
 0122e098:			0000: c0062d00 0004010f 41800000 41800000 42000000 42000000 00000000 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (10 dwords)
+			opcode: CP_SET_CONSTANT (2d) (10 dwords)
 0122e0c0:				16.000000 32.000000 0.000000 0.000000 16.000000 32.000000 0.000000 0.000000
 0122e0b8:			0000: c0082d00 00000184 41800000 42000000 00000000 00000000 41800000 42000000
 *
-t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords)
+			opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords)
 			vertex shader, start=0000, size=0015
 					    2003 0007 1000            	EXEC ADDR(0x3) CNT(0x2)
 					03: 19481000 00262688 00000020	   (S)FETCH:	VERTEX	R1.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) CONST(20, 0)
@@ -554,7 +554,7 @@ t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords)
 0122e0e0:			0000: c0162b00 00000000 00000015 00072003 00001000 c2000000 00021005 00001000
 0122e100:			0020: c4000000 00001006 00002000 00000000 19481000 00262688 00000020 13480000
 0122e120:			0040: 40262688 00001020 000f803e 00000000 c2010100 000f8000 00000000 c2000000
-t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
+			opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
 			fragment shader, start=0000, size=000c
 					    1002 0003 1000            	EXEC ADDR(0x2) CNT(0x1)
 					02: 90000001 1ffff688 00000002	   (S)FETCH:	SAMPLE	R0.xyzw = R0.xyz CONST(0) LOCATION(CENTER)
@@ -564,31 +564,31 @@ t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
 					    0000 0000 0000            	NOP
 0122e140:			0000: c00d2b00 00000001 0000000c 00031002 00001000 c4000000 00021003 00002000
 0122e160:			0020: 00000000 90000001 1ffff688 00000002 000f8000 00000000 c2000000
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 }
 0122e17c:			0000: c0012d00 00040181 00000106
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
 0122e188:			0000: c0012d00 00040180 10030002
-t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
+			opcode: CP_SET_CONSTANT (2d) (6 dwords)
 0122e19c:				0.000000 0.000000 0.000000 0.000000
 0122e194:			0000: c0042d00 00000080 00000000 00000000 00000000 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
 0122e1ac:			0000: c0012d00 00040202 00000c20
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
 0122e1b8:			0000: c0012d00 00040201 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 0122e1c4:			0000: c0012d00 00040104 0000000f
-t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
+			opcode: CP_SET_CONSTANT (2d) (6 dwords)
 				RB_BLEND_RED: 0
 				RB_BLEND_GREEN: 0
 				RB_BLEND_BLUE: 0
 				RB_BLEND_ALPHA: 0
 0122e1d0:			0000: c0042d00 00040105 00000000 00000000 00000000 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
+			opcode: CP_SET_CONSTANT (2d) (8 dwords)
 			set texture const 0000
 				clamp x/y/z: clamp-last-texel/clamp-last-texel/clamp-last-texel
 				filter min/mag: point/point
@@ -596,23 +596,23 @@ t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
 				addr=01250000 (flags=820), size=32x64, pitch=32, format=FMT_1_REVERSE
 				mipaddr=00000000 (flags=200)
 0122e1e8:			0000: c0062d00 00010000 00424800 01250820 0007e01f 00000d11 00000000 00000200
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				VGT_INDX_OFFSET: 0
 0122e208:			0000: c0012d00 00040102 00000000
-t0			write TC_CNTL_STATUS (0e00)
+			write TC_CNTL_STATUS (0e00)
 				TC_CNTL_STATUS: { L2_INVALIDATE }
 0122e214:			0000: 00000e00 00000001
-t3			opcode: CP_WAIT_REG_EQ (52) (5 dwords)
+			opcode: CP_WAIT_REG_EQ (52) (5 dwords)
 0122e21c:			0000: c0035200 000005d0 00000000 00001000 00000001
-t3			opcode: CP_DRAW_INDX_BIN (34) (7 dwords)
+			opcode: CP_DRAW_INDX_BIN (34) (7 dwords)
 0122e230:			0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 11
 				:0,0,15,11
 0122e24c:			0000: 0000057f 0000000b
-t3			opcode: CP_NOP (10) (2 dwords)
+			opcode: CP_NOP (10) (2 dwords)
 0122e254:			0000: c0001000 00000000
-t3			opcode: CP_DRAW_INDX (22) (3 dwords)
+			opcode: CP_DRAW_INDX (22) (3 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRIFAN | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x40000 }
 			draw:          0
@@ -688,220 +688,220 @@ t3			opcode: CP_DRAW_INDX (22) (3 dwords)
  +	0003c000			RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
  +	ffffffff			RB_COLOR_DEST_MASK: 0xffffffff
 0122e25c:			0000: c0012200 00000000 00040085
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12
 				:0,0,15,12
 0122e268:			0000: 0000057f 0000000c
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 0122e270:			0000: c0002600 00000000
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e278:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e280:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e288:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e290:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e298:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2a0:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2a8:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2b0:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2b8:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2c0:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2c8:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2d0:			0000: c0004600 00000006
 0122f1d8:		0000: c0013700 0122e000 000000b6
-t2		nop
+		nop
 ############################################################
 vertices: 0
 cmd: deqp-gles2/185: fence=1252
 ############################################################
 cmdstream[2]: 124 dwords
-t0		write RB_BC_CONTROL (0f01)
+		write RB_BC_CONTROL (0f01)
 			RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 }
 0122d000:		0000: 00000f01 1c004046
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 }
 0122d008:		0000: c0012d00 00040293 00000020
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
 0122d014:		0000: c0012d00 00040316 00000002
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 }
 0122d020:		0000: c0012d00 00040317 00000002
-t0		write CP_PERFMON_CNTL (0444)
+		write CP_PERFMON_CNTL (0444)
 			CP_PERFMON_CNTL: 0
 0122d02c:		0000: 00000444 00000000
-t0		write RBBM_PM_OVERRIDE1 (039c)
+		write RBBM_PM_OVERRIDE1 (039c)
 			RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
 			RBBM_PM_OVERRIDE2: 0xfff
 0122d034:		0000: 0001039c ffffffff 00000fff
-t0		write TP0_CHICKEN (0e1e)
+		write TP0_CHICKEN (0e1e)
 			TP0_CHICKEN: 0x2
 0122d040:		0000: 00000e1e 00000002
-t3		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
+		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
 0122d048:		0000: c0003b00 00007fff
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			SQ_VS_CONST: { BASE = 32 | SIZE = 256 }
 0122d050:		0000: c0012d00 00040307 00100020
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			SQ_PS_CONST: { BASE = 288 | SIZE = 224 }
 0122d05c:		0000: c0012d00 00040308 000e0120
-t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
+		opcode: CP_SET_CONSTANT (2d) (4 dwords)
 			VGT_MAX_VTX_INDX: 0xffffffff
 			VGT_MIN_VTX_INDX: 0
 0122d068:		0000: c0022d00 00040100 ffffffff 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			VGT_INDX_OFFSET: 0
 0122d078:		0000: c0012d00 00040102 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			SQ_CONTEXT_MISC: { SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 }
 0122d084:		0000: c0012d00 00040181 00000004
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 }
 0122d090:		0000: c0012d00 00040182 ffffffff
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
 0122d09c:		0000: c0012d00 00040301 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_LINE_CNTL: { BRES_CNTL = 0 }
 0122d0a8:		0000: c0012d00 00040300 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
 0122d0b4:		0000: c0012d00 00040080 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
 0122d0c0:		0000: c0012d00 00040208 00000004
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_SAMPLE_POS: 0x88888888
 0122d0cc:		0000: c0012d00 0004020a 88888888
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_COLOR_DEST_MASK: 0xffffffff
 0122d0d8:		0000: c0012d00 00040326 ffffffff
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 0122d0e4:		0000: c0012d00 0004031b 0003c000
-t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
+		opcode: CP_SET_CONSTANT (2d) (4 dwords)
 			SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 }
 			SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 }
 0122d0f0:		0000: c0022d00 00040183 00000000 00000000
-t3		opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords)
+		opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords)
 0122d100:		0000: c0004b00 00000000
-t3		opcode: CP_WAIT_REG_EQ (52) (5 dwords)
+		opcode: CP_WAIT_REG_EQ (52) (5 dwords)
 0122d108:		0000: c0035200 000005d0 00000000 5f601000 00000001
-t0		write SQ_INST_STORE_MANAGMENT (0d02)
+		write SQ_INST_STORE_MANAGMENT (0d02)
 			SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 }
 0122d11c:		0000: 00000d02 00000180
-t3		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
+		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
 0122d124:		0000: c0003b00 00000300
-t3		opcode: CP_SET_SHADER_BASES (4a) (2 dwords)
+		opcode: CP_SET_SHADER_BASES (4a) (2 dwords)
 0122d12c:		0000: c0004a00 80000180
-t3		opcode: CP_SET_CONSTANT (2d) (14 dwords)
+		opcode: CP_SET_CONSTANT (2d) (14 dwords)
 0122d13c:			0.000000 0.000000 0.000000 0.000000 20000.000000 1.000000 0.500000 0.000000
 0122d15c:			2.000000 0.750000 0.375000 0.250000
 0122d134:		0000: c00c2d00 00000000 00000000 00000000 00000000 00000000 469c4000 3f800000
 0122d154:		0020: 3f000000 00000000 40000000 3f400000 3ec00000 3e800000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 0122d16c:		0000: c0012d00 00040104 0000000f
-t3		opcode: CP_SET_CONSTANT (2d) (6 dwords)
+		opcode: CP_SET_CONSTANT (2d) (6 dwords)
 			RB_BLEND_RED: 0
 			RB_BLEND_GREEN: 0
 			RB_BLEND_BLUE: 0
 			RB_BLEND_ALPHA: 0xff
 0122d178:		0000: c0042d00 00040105 00000000 00000000 00000000 000000ff
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT }
 0122d190:		0000: c0012d00 00040206 0000043f
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 }
 0122d19c:		0000: c0012d00 00040000 00000020
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_COLOR_INFO: { FORMAT = COLORX_16_16_16_16_FLOAT | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0x1244000 }
 0122d1a8:		0000: c0012d00 00040001 01244009
-t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
+		opcode: CP_SET_CONSTANT (2d) (4 dwords)
 			PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 }
 			PA_SC_SCREEN_SCISSOR_BR: { X = 16 | Y = 32 }
 0122d1b4:		0000: c0022d00 0004000e 80000000 00200010
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
 0122d1c4:		0000: c0012d00 00040080 00000000
-t0		write CP_SCRATCH_REG6 (057e)
+		write CP_SCRATCH_REG6 (057e)
 			CP_SCRATCH_REG6: 21
 			:0,0,21,12
 0122d1d0:		0000: 0000057e 00000015
-t3		opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
+		opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
 		ibaddr:0122e000
 		ibsize:000000b6
-t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
+			opcode: CP_SET_CONSTANT (2d) (6 dwords)
 			set shader const 0078
 0122e000:			0000: c0042d00 00010078 0112d103 00100000 0112d103 00100000
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				PA_SC_AA_MASK: 0xffff
 0122e018:			0000: c0012d00 00040312 0000ffff
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
 0122e024:			0000: c0012d00 00040200 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (5 dwords)
+			opcode: CP_SET_CONSTANT (2d) (5 dwords)
 				RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
 				RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
 				RB_ALPHA_REF: 0
 0122e030:			0000: c0032d00 0004010c 00000000 00000000 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
+			opcode: CP_SET_CONSTANT (2d) (4 dwords)
 				PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
 				PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST }
 0122e044:			0000: c0022d00 00040204 00000000 00090244
-t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
+			opcode: CP_SET_CONSTANT (2d) (6 dwords)
 				PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 }
 				PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 }
 				PA_SU_LINE_CNTL: { WIDTH = 0.000000 }
 				PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER }
 0122e054:			0000: c0042d00 00040280 00000000 00000000 00000000 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (7 dwords)
+			opcode: CP_SET_CONSTANT (2d) (7 dwords)
 				PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH }
 				PA_CL_GB_VERT_CLIP_ADJ: 1.000000
 				PA_CL_GB_VERT_DISC_ADJ: 1.000000
 				PA_CL_GB_HORZ_CLIP_ADJ: 1.000000
 				PA_CL_GB_HORZ_DISC_ADJ: 1.000000
 0122e06c:			0000: c0052d00 00040302 00000001 3f800000 3f800000 3f800000 3f800000
-t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
+			opcode: CP_SET_CONSTANT (2d) (4 dwords)
 				PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
 				PA_SC_WINDOW_SCISSOR_BR: { X = 16 | Y = 32 }
 0122e088:			0000: c0022d00 00040081 00000000 00200010
-t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
+			opcode: CP_SET_CONSTANT (2d) (8 dwords)
 				PA_CL_VPORT_XSCALE: 8.000000
 				PA_CL_VPORT_XOFFSET: 8.000000
 				PA_CL_VPORT_YSCALE: 16.000000
@@ -909,11 +909,11 @@ t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
 				PA_CL_VPORT_ZSCALE: 0.000000
 				PA_CL_VPORT_ZOFFSET: 0.000000
 0122e098:			0000: c0062d00 0004010f 41000000 41000000 41800000 41800000 00000000 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (10 dwords)
+			opcode: CP_SET_CONSTANT (2d) (10 dwords)
 0122e0c0:				8.000000 16.000000 0.000000 0.000000 8.000000 16.000000 0.000000 0.000000
 0122e0b8:			0000: c0082d00 00000184 41000000 41800000 00000000 00000000 41000000 41800000
 *
-t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords)
+			opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords)
 			vertex shader, start=0000, size=0015
 					    2003 0007 1000            	EXEC ADDR(0x3) CNT(0x2)
 					03: 19481000 00262688 00000020	   (S)FETCH:	VERTEX	R1.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) CONST(20, 0)
@@ -928,7 +928,7 @@ t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords)
 0122e0e0:			0000: c0162b00 00000000 00000015 00072003 00001000 c2000000 00021005 00001000
 0122e100:			0020: c4000000 00001006 00002000 00000000 19481000 00262688 00000020 13480000
 0122e120:			0040: 40262688 00001020 000f803e 00000000 c2010100 000f8000 00000000 c2000000
-t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
+			opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
 			fragment shader, start=0000, size=000c
 					    1002 0003 1000            	EXEC ADDR(0x2) CNT(0x1)
 					02: 90000001 1ffff688 00000002	   (S)FETCH:	SAMPLE	R0.xyzw = R0.xyz CONST(0) LOCATION(CENTER)
@@ -938,31 +938,31 @@ t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
 					    0000 0000 0000            	NOP
 0122e140:			0000: c00d2b00 00000001 0000000c 00031002 00001000 c4000000 00021003 00002000
 0122e160:			0020: 00000000 90000001 1ffff688 00000002 000f8000 00000000 c2000000
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 }
 0122e17c:			0000: c0012d00 00040181 00000106
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
 0122e188:			0000: c0012d00 00040180 10030002
-t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
+			opcode: CP_SET_CONSTANT (2d) (6 dwords)
 0122e19c:				0.000000 0.000000 0.000000 0.000000
 0122e194:			0000: c0042d00 00000080 00000000 00000000 00000000 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
 0122e1ac:			0000: c0012d00 00040202 00000c20
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
 0122e1b8:			0000: c0012d00 00040201 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 0122e1c4:			0000: c0012d00 00040104 0000000f
-t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
+			opcode: CP_SET_CONSTANT (2d) (6 dwords)
 				RB_BLEND_RED: 0
 				RB_BLEND_GREEN: 0
 				RB_BLEND_BLUE: 0
 				RB_BLEND_ALPHA: 0
 0122e1d0:			0000: c0042d00 00040105 00000000 00000000 00000000 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
+			opcode: CP_SET_CONSTANT (2d) (8 dwords)
 			set texture const 0000
 				clamp x/y/z: clamp-last-texel/clamp-last-texel/clamp-last-texel
 				filter min/mag: point/point
@@ -970,23 +970,23 @@ t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
 				addr=01254000 (flags=820), size=16x32, pitch=32, format=FMT_1_REVERSE
 				mipaddr=00000000 (flags=200)
 0122e1e8:			0000: c0062d00 00010000 00424800 01254820 0003e00f 00000d11 00000000 00000200
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				VGT_INDX_OFFSET: 0
 0122e208:			0000: c0012d00 00040102 00000000
-t0			write TC_CNTL_STATUS (0e00)
+			write TC_CNTL_STATUS (0e00)
 				TC_CNTL_STATUS: { L2_INVALIDATE }
 0122e214:			0000: 00000e00 00000001
-t3			opcode: CP_WAIT_REG_EQ (52) (5 dwords)
+			opcode: CP_WAIT_REG_EQ (52) (5 dwords)
 0122e21c:			0000: c0035200 000005d0 00000000 00001000 00000001
-t3			opcode: CP_DRAW_INDX_BIN (34) (7 dwords)
+			opcode: CP_DRAW_INDX_BIN (34) (7 dwords)
 0122e230:			0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 17
 				:0,0,21,17
 0122e24c:			0000: 0000057f 00000011
-t3			opcode: CP_NOP (10) (2 dwords)
+			opcode: CP_NOP (10) (2 dwords)
 0122e254:			0000: c0001000 00000000
-t3			opcode: CP_DRAW_INDX (22) (3 dwords)
+			opcode: CP_DRAW_INDX (22) (3 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRIFAN | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x40000 }
 			draw:          0
@@ -1062,220 +1062,220 @@ t3			opcode: CP_DRAW_INDX (22) (3 dwords)
  +	0003c000			RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
  +	ffffffff			RB_COLOR_DEST_MASK: 0xffffffff
 0122e25c:			0000: c0012200 00000000 00040085
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 18
 				:0,0,21,18
 0122e268:			0000: 0000057f 00000012
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 0122e270:			0000: c0002600 00000000
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e278:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e280:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e288:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e290:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e298:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2a0:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2a8:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2b0:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2b8:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2c0:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2c8:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2d0:			0000: c0004600 00000006
 0122d1d8:		0000: c0013700 0122e000 000000b6
-t2		nop
+		nop
 ############################################################
 vertices: 0
 cmd: deqp-gles2/185: fence=1253
 ############################################################
 cmdstream[3]: 124 dwords
-t0		write RB_BC_CONTROL (0f01)
+		write RB_BC_CONTROL (0f01)
 			RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 }
 0122f000:		0000: 00000f01 1c004046
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 }
 0122f008:		0000: c0012d00 00040293 00000020
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
 0122f014:		0000: c0012d00 00040316 00000002
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 }
 0122f020:		0000: c0012d00 00040317 00000002
-t0		write CP_PERFMON_CNTL (0444)
+		write CP_PERFMON_CNTL (0444)
 			CP_PERFMON_CNTL: 0
 0122f02c:		0000: 00000444 00000000
-t0		write RBBM_PM_OVERRIDE1 (039c)
+		write RBBM_PM_OVERRIDE1 (039c)
 			RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
 			RBBM_PM_OVERRIDE2: 0xfff
 0122f034:		0000: 0001039c ffffffff 00000fff
-t0		write TP0_CHICKEN (0e1e)
+		write TP0_CHICKEN (0e1e)
 			TP0_CHICKEN: 0x2
 0122f040:		0000: 00000e1e 00000002
-t3		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
+		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
 0122f048:		0000: c0003b00 00007fff
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			SQ_VS_CONST: { BASE = 32 | SIZE = 256 }
 0122f050:		0000: c0012d00 00040307 00100020
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			SQ_PS_CONST: { BASE = 288 | SIZE = 224 }
 0122f05c:		0000: c0012d00 00040308 000e0120
-t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
+		opcode: CP_SET_CONSTANT (2d) (4 dwords)
 			VGT_MAX_VTX_INDX: 0xffffffff
 			VGT_MIN_VTX_INDX: 0
 0122f068:		0000: c0022d00 00040100 ffffffff 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			VGT_INDX_OFFSET: 0
 0122f078:		0000: c0012d00 00040102 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			SQ_CONTEXT_MISC: { SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 }
 0122f084:		0000: c0012d00 00040181 00000004
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 }
 0122f090:		0000: c0012d00 00040182 ffffffff
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
 0122f09c:		0000: c0012d00 00040301 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_LINE_CNTL: { BRES_CNTL = 0 }
 0122f0a8:		0000: c0012d00 00040300 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
 0122f0b4:		0000: c0012d00 00040080 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
 0122f0c0:		0000: c0012d00 00040208 00000004
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_SAMPLE_POS: 0x88888888
 0122f0cc:		0000: c0012d00 0004020a 88888888
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_COLOR_DEST_MASK: 0xffffffff
 0122f0d8:		0000: c0012d00 00040326 ffffffff
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 0122f0e4:		0000: c0012d00 0004031b 0003c000
-t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
+		opcode: CP_SET_CONSTANT (2d) (4 dwords)
 			SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 }
 			SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 }
 0122f0f0:		0000: c0022d00 00040183 00000000 00000000
-t3		opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords)
+		opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords)
 0122f100:		0000: c0004b00 00000000
-t3		opcode: CP_WAIT_REG_EQ (52) (5 dwords)
+		opcode: CP_WAIT_REG_EQ (52) (5 dwords)
 0122f108:		0000: c0035200 000005d0 00000000 5f601000 00000001
-t0		write SQ_INST_STORE_MANAGMENT (0d02)
+		write SQ_INST_STORE_MANAGMENT (0d02)
 			SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 }
 0122f11c:		0000: 00000d02 00000180
-t3		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
+		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
 0122f124:		0000: c0003b00 00000300
-t3		opcode: CP_SET_SHADER_BASES (4a) (2 dwords)
+		opcode: CP_SET_SHADER_BASES (4a) (2 dwords)
 0122f12c:		0000: c0004a00 80000180
-t3		opcode: CP_SET_CONSTANT (2d) (14 dwords)
+		opcode: CP_SET_CONSTANT (2d) (14 dwords)
 0122f13c:			0.000000 0.000000 0.000000 0.000000 20000.000000 1.000000 0.500000 0.000000
 0122f15c:			2.000000 0.750000 0.375000 0.250000
 0122f134:		0000: c00c2d00 00000000 00000000 00000000 00000000 00000000 469c4000 3f800000
 0122f154:		0020: 3f000000 00000000 40000000 3f400000 3ec00000 3e800000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 0122f16c:		0000: c0012d00 00040104 0000000f
-t3		opcode: CP_SET_CONSTANT (2d) (6 dwords)
+		opcode: CP_SET_CONSTANT (2d) (6 dwords)
 			RB_BLEND_RED: 0
 			RB_BLEND_GREEN: 0
 			RB_BLEND_BLUE: 0
 			RB_BLEND_ALPHA: 0xff
 0122f178:		0000: c0042d00 00040105 00000000 00000000 00000000 000000ff
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT }
 0122f190:		0000: c0012d00 00040206 0000043f
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 }
 0122f19c:		0000: c0012d00 00040000 00000020
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_COLOR_INFO: { FORMAT = COLORX_16_16_16_16_FLOAT | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0x1246000 }
 0122f1a8:		0000: c0012d00 00040001 01246009
-t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
+		opcode: CP_SET_CONSTANT (2d) (4 dwords)
 			PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 }
 			PA_SC_SCREEN_SCISSOR_BR: { X = 8 | Y = 16 }
 0122f1b4:		0000: c0022d00 0004000e 80000000 00100008
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
 0122f1c4:		0000: c0012d00 00040080 00000000
-t0		write CP_SCRATCH_REG6 (057e)
+		write CP_SCRATCH_REG6 (057e)
 			CP_SCRATCH_REG6: 27
 			:0,0,27,18
 0122f1d0:		0000: 0000057e 0000001b
-t3		opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
+		opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
 		ibaddr:0122e000
 		ibsize:000000b6
-t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
+			opcode: CP_SET_CONSTANT (2d) (6 dwords)
 			set shader const 0078
 0122e000:			0000: c0042d00 00010078 0112d183 00100000 0112d183 00100000
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				PA_SC_AA_MASK: 0xffff
 0122e018:			0000: c0012d00 00040312 0000ffff
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
 0122e024:			0000: c0012d00 00040200 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (5 dwords)
+			opcode: CP_SET_CONSTANT (2d) (5 dwords)
 				RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
 				RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
 				RB_ALPHA_REF: 0
 0122e030:			0000: c0032d00 0004010c 00000000 00000000 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
+			opcode: CP_SET_CONSTANT (2d) (4 dwords)
 				PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
 				PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST }
 0122e044:			0000: c0022d00 00040204 00000000 00090244
-t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
+			opcode: CP_SET_CONSTANT (2d) (6 dwords)
 				PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 }
 				PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 }
 				PA_SU_LINE_CNTL: { WIDTH = 0.000000 }
 				PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER }
 0122e054:			0000: c0042d00 00040280 00000000 00000000 00000000 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (7 dwords)
+			opcode: CP_SET_CONSTANT (2d) (7 dwords)
 				PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH }
 				PA_CL_GB_VERT_CLIP_ADJ: 1.000000
 				PA_CL_GB_VERT_DISC_ADJ: 1.000000
 				PA_CL_GB_HORZ_CLIP_ADJ: 1.000000
 				PA_CL_GB_HORZ_DISC_ADJ: 1.000000
 0122e06c:			0000: c0052d00 00040302 00000001 3f800000 3f800000 3f800000 3f800000
-t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
+			opcode: CP_SET_CONSTANT (2d) (4 dwords)
 				PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
 				PA_SC_WINDOW_SCISSOR_BR: { X = 8 | Y = 16 }
 0122e088:			0000: c0022d00 00040081 00000000 00100008
-t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
+			opcode: CP_SET_CONSTANT (2d) (8 dwords)
 				PA_CL_VPORT_XSCALE: 4.000000
 				PA_CL_VPORT_XOFFSET: 4.000000
 				PA_CL_VPORT_YSCALE: 8.000000
@@ -1283,11 +1283,11 @@ t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
 				PA_CL_VPORT_ZSCALE: 0.000000
 				PA_CL_VPORT_ZOFFSET: 0.000000
 0122e098:			0000: c0062d00 0004010f 40800000 40800000 41000000 41000000 00000000 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (10 dwords)
+			opcode: CP_SET_CONSTANT (2d) (10 dwords)
 0122e0c0:				4.000000 8.000000 0.000000 0.000000 4.000000 8.000000 0.000000 0.000000
 0122e0b8:			0000: c0082d00 00000184 40800000 41000000 00000000 00000000 40800000 41000000
 *
-t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords)
+			opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords)
 			vertex shader, start=0000, size=0015
 					    2003 0007 1000            	EXEC ADDR(0x3) CNT(0x2)
 					03: 19481000 00262688 00000020	   (S)FETCH:	VERTEX	R1.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) CONST(20, 0)
@@ -1302,7 +1302,7 @@ t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords)
 0122e0e0:			0000: c0162b00 00000000 00000015 00072003 00001000 c2000000 00021005 00001000
 0122e100:			0020: c4000000 00001006 00002000 00000000 19481000 00262688 00000020 13480000
 0122e120:			0040: 40262688 00001020 000f803e 00000000 c2010100 000f8000 00000000 c2000000
-t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
+			opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
 			fragment shader, start=0000, size=000c
 					    1002 0003 1000            	EXEC ADDR(0x2) CNT(0x1)
 					02: 90000001 1ffff688 00000002	   (S)FETCH:	SAMPLE	R0.xyzw = R0.xyz CONST(0) LOCATION(CENTER)
@@ -1312,31 +1312,31 @@ t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
 					    0000 0000 0000            	NOP
 0122e140:			0000: c00d2b00 00000001 0000000c 00031002 00001000 c4000000 00021003 00002000
 0122e160:			0020: 00000000 90000001 1ffff688 00000002 000f8000 00000000 c2000000
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 }
 0122e17c:			0000: c0012d00 00040181 00000106
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
 0122e188:			0000: c0012d00 00040180 10030002
-t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
+			opcode: CP_SET_CONSTANT (2d) (6 dwords)
 0122e19c:				0.000000 0.000000 0.000000 0.000000
 0122e194:			0000: c0042d00 00000080 00000000 00000000 00000000 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
 0122e1ac:			0000: c0012d00 00040202 00000c20
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
 0122e1b8:			0000: c0012d00 00040201 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 0122e1c4:			0000: c0012d00 00040104 0000000f
-t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
+			opcode: CP_SET_CONSTANT (2d) (6 dwords)
 				RB_BLEND_RED: 0
 				RB_BLEND_GREEN: 0
 				RB_BLEND_BLUE: 0
 				RB_BLEND_ALPHA: 0
 0122e1d0:			0000: c0042d00 00040105 00000000 00000000 00000000 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
+			opcode: CP_SET_CONSTANT (2d) (8 dwords)
 			set texture const 0000
 				clamp x/y/z: clamp-last-texel/clamp-last-texel/clamp-last-texel
 				filter min/mag: point/point
@@ -1344,23 +1344,23 @@ t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
 				addr=01254000 (flags=820), size=8x16, pitch=32, format=FMT_1_REVERSE
 				mipaddr=00000000 (flags=200)
 0122e1e8:			0000: c0062d00 00010000 00424800 01254820 0001e007 00000d11 00000000 00000200
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				VGT_INDX_OFFSET: 0
 0122e208:			0000: c0012d00 00040102 00000000
-t0			write TC_CNTL_STATUS (0e00)
+			write TC_CNTL_STATUS (0e00)
 				TC_CNTL_STATUS: { L2_INVALIDATE }
 0122e214:			0000: 00000e00 00000001
-t3			opcode: CP_WAIT_REG_EQ (52) (5 dwords)
+			opcode: CP_WAIT_REG_EQ (52) (5 dwords)
 0122e21c:			0000: c0035200 000005d0 00000000 00001000 00000001
-t3			opcode: CP_DRAW_INDX_BIN (34) (7 dwords)
+			opcode: CP_DRAW_INDX_BIN (34) (7 dwords)
 0122e230:			0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 23
 				:0,0,27,23
 0122e24c:			0000: 0000057f 00000017
-t3			opcode: CP_NOP (10) (2 dwords)
+			opcode: CP_NOP (10) (2 dwords)
 0122e254:			0000: c0001000 00000000
-t3			opcode: CP_DRAW_INDX (22) (3 dwords)
+			opcode: CP_DRAW_INDX (22) (3 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRIFAN | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x40000 }
 			draw:          0
@@ -1436,220 +1436,220 @@ t3			opcode: CP_DRAW_INDX (22) (3 dwords)
  +	0003c000			RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
  +	ffffffff			RB_COLOR_DEST_MASK: 0xffffffff
 0122e25c:			0000: c0012200 00000000 00040085
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 24
 				:0,0,27,24
 0122e268:			0000: 0000057f 00000018
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 0122e270:			0000: c0002600 00000000
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e278:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e280:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e288:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e290:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e298:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2a0:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2a8:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2b0:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2b8:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2c0:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2c8:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2d0:			0000: c0004600 00000006
 0122f1d8:		0000: c0013700 0122e000 000000b6
-t2		nop
+		nop
 ############################################################
 vertices: 0
 cmd: deqp-gles2/185: fence=1254
 ############################################################
 cmdstream[4]: 124 dwords
-t0		write RB_BC_CONTROL (0f01)
+		write RB_BC_CONTROL (0f01)
 			RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 }
 0122d000:		0000: 00000f01 1c004046
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 }
 0122d008:		0000: c0012d00 00040293 00000020
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
 0122d014:		0000: c0012d00 00040316 00000002
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 }
 0122d020:		0000: c0012d00 00040317 00000002
-t0		write CP_PERFMON_CNTL (0444)
+		write CP_PERFMON_CNTL (0444)
 			CP_PERFMON_CNTL: 0
 0122d02c:		0000: 00000444 00000000
-t0		write RBBM_PM_OVERRIDE1 (039c)
+		write RBBM_PM_OVERRIDE1 (039c)
 			RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
 			RBBM_PM_OVERRIDE2: 0xfff
 0122d034:		0000: 0001039c ffffffff 00000fff
-t0		write TP0_CHICKEN (0e1e)
+		write TP0_CHICKEN (0e1e)
 			TP0_CHICKEN: 0x2
 0122d040:		0000: 00000e1e 00000002
-t3		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
+		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
 0122d048:		0000: c0003b00 00007fff
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			SQ_VS_CONST: { BASE = 32 | SIZE = 256 }
 0122d050:		0000: c0012d00 00040307 00100020
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			SQ_PS_CONST: { BASE = 288 | SIZE = 224 }
 0122d05c:		0000: c0012d00 00040308 000e0120
-t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
+		opcode: CP_SET_CONSTANT (2d) (4 dwords)
 			VGT_MAX_VTX_INDX: 0xffffffff
 			VGT_MIN_VTX_INDX: 0
 0122d068:		0000: c0022d00 00040100 ffffffff 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			VGT_INDX_OFFSET: 0
 0122d078:		0000: c0012d00 00040102 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			SQ_CONTEXT_MISC: { SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 }
 0122d084:		0000: c0012d00 00040181 00000004
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 }
 0122d090:		0000: c0012d00 00040182 ffffffff
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
 0122d09c:		0000: c0012d00 00040301 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_LINE_CNTL: { BRES_CNTL = 0 }
 0122d0a8:		0000: c0012d00 00040300 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
 0122d0b4:		0000: c0012d00 00040080 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
 0122d0c0:		0000: c0012d00 00040208 00000004
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_SAMPLE_POS: 0x88888888
 0122d0cc:		0000: c0012d00 0004020a 88888888
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_COLOR_DEST_MASK: 0xffffffff
 0122d0d8:		0000: c0012d00 00040326 ffffffff
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 0122d0e4:		0000: c0012d00 0004031b 0003c000
-t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
+		opcode: CP_SET_CONSTANT (2d) (4 dwords)
 			SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 }
 			SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 }
 0122d0f0:		0000: c0022d00 00040183 00000000 00000000
-t3		opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords)
+		opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords)
 0122d100:		0000: c0004b00 00000000
-t3		opcode: CP_WAIT_REG_EQ (52) (5 dwords)
+		opcode: CP_WAIT_REG_EQ (52) (5 dwords)
 0122d108:		0000: c0035200 000005d0 00000000 5f601000 00000001
-t0		write SQ_INST_STORE_MANAGMENT (0d02)
+		write SQ_INST_STORE_MANAGMENT (0d02)
 			SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 }
 0122d11c:		0000: 00000d02 00000180
-t3		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
+		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
 0122d124:		0000: c0003b00 00000300
-t3		opcode: CP_SET_SHADER_BASES (4a) (2 dwords)
+		opcode: CP_SET_SHADER_BASES (4a) (2 dwords)
 0122d12c:		0000: c0004a00 80000180
-t3		opcode: CP_SET_CONSTANT (2d) (14 dwords)
+		opcode: CP_SET_CONSTANT (2d) (14 dwords)
 0122d13c:			0.000000 0.000000 0.000000 0.000000 20000.000000 1.000000 0.500000 0.000000
 0122d15c:			2.000000 0.750000 0.375000 0.250000
 0122d134:		0000: c00c2d00 00000000 00000000 00000000 00000000 00000000 469c4000 3f800000
 0122d154:		0020: 3f000000 00000000 40000000 3f400000 3ec00000 3e800000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 0122d16c:		0000: c0012d00 00040104 0000000f
-t3		opcode: CP_SET_CONSTANT (2d) (6 dwords)
+		opcode: CP_SET_CONSTANT (2d) (6 dwords)
 			RB_BLEND_RED: 0
 			RB_BLEND_GREEN: 0
 			RB_BLEND_BLUE: 0
 			RB_BLEND_ALPHA: 0xff
 0122d178:		0000: c0042d00 00040105 00000000 00000000 00000000 000000ff
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT }
 0122d190:		0000: c0012d00 00040206 0000043f
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 }
 0122d19c:		0000: c0012d00 00040000 00000020
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_COLOR_INFO: { FORMAT = COLORX_16_16_16_16_FLOAT | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0x1248000 }
 0122d1a8:		0000: c0012d00 00040001 01248009
-t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
+		opcode: CP_SET_CONSTANT (2d) (4 dwords)
 			PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 }
 			PA_SC_SCREEN_SCISSOR_BR: { X = 4 | Y = 8 }
 0122d1b4:		0000: c0022d00 0004000e 80000000 00080004
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
 0122d1c4:		0000: c0012d00 00040080 00000000
-t0		write CP_SCRATCH_REG6 (057e)
+		write CP_SCRATCH_REG6 (057e)
 			CP_SCRATCH_REG6: 33
 			:0,0,33,24
 0122d1d0:		0000: 0000057e 00000021
-t3		opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
+		opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
 		ibaddr:0122e000
 		ibsize:000000b6
-t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
+			opcode: CP_SET_CONSTANT (2d) (6 dwords)
 			set shader const 0078
 0122e000:			0000: c0042d00 00010078 0112d203 00100000 0112d203 00100000
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				PA_SC_AA_MASK: 0xffff
 0122e018:			0000: c0012d00 00040312 0000ffff
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
 0122e024:			0000: c0012d00 00040200 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (5 dwords)
+			opcode: CP_SET_CONSTANT (2d) (5 dwords)
 				RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
 				RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
 				RB_ALPHA_REF: 0
 0122e030:			0000: c0032d00 0004010c 00000000 00000000 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
+			opcode: CP_SET_CONSTANT (2d) (4 dwords)
 				PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
 				PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST }
 0122e044:			0000: c0022d00 00040204 00000000 00090244
-t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
+			opcode: CP_SET_CONSTANT (2d) (6 dwords)
 				PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 }
 				PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 }
 				PA_SU_LINE_CNTL: { WIDTH = 0.000000 }
 				PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER }
 0122e054:			0000: c0042d00 00040280 00000000 00000000 00000000 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (7 dwords)
+			opcode: CP_SET_CONSTANT (2d) (7 dwords)
 				PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH }
 				PA_CL_GB_VERT_CLIP_ADJ: 1.000000
 				PA_CL_GB_VERT_DISC_ADJ: 1.000000
 				PA_CL_GB_HORZ_CLIP_ADJ: 1.000000
 				PA_CL_GB_HORZ_DISC_ADJ: 1.000000
 0122e06c:			0000: c0052d00 00040302 00000001 3f800000 3f800000 3f800000 3f800000
-t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
+			opcode: CP_SET_CONSTANT (2d) (4 dwords)
 				PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
 				PA_SC_WINDOW_SCISSOR_BR: { X = 4 | Y = 8 }
 0122e088:			0000: c0022d00 00040081 00000000 00080004
-t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
+			opcode: CP_SET_CONSTANT (2d) (8 dwords)
 				PA_CL_VPORT_XSCALE: 2.000000
 				PA_CL_VPORT_XOFFSET: 2.000000
 				PA_CL_VPORT_YSCALE: 4.000000
@@ -1657,11 +1657,11 @@ t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
 				PA_CL_VPORT_ZSCALE: 0.000000
 				PA_CL_VPORT_ZOFFSET: 0.000000
 0122e098:			0000: c0062d00 0004010f 40000000 40000000 40800000 40800000 00000000 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (10 dwords)
+			opcode: CP_SET_CONSTANT (2d) (10 dwords)
 0122e0c0:				2.000000 4.000000 0.000000 0.000000 2.000000 4.000000 0.000000 0.000000
 0122e0b8:			0000: c0082d00 00000184 40000000 40800000 00000000 00000000 40000000 40800000
 *
-t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords)
+			opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords)
 			vertex shader, start=0000, size=0015
 					    2003 0007 1000            	EXEC ADDR(0x3) CNT(0x2)
 					03: 19481000 00262688 00000020	   (S)FETCH:	VERTEX	R1.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) CONST(20, 0)
@@ -1676,7 +1676,7 @@ t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords)
 0122e0e0:			0000: c0162b00 00000000 00000015 00072003 00001000 c2000000 00021005 00001000
 0122e100:			0020: c4000000 00001006 00002000 00000000 19481000 00262688 00000020 13480000
 0122e120:			0040: 40262688 00001020 000f803e 00000000 c2010100 000f8000 00000000 c2000000
-t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
+			opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
 			fragment shader, start=0000, size=000c
 					    1002 0003 1000            	EXEC ADDR(0x2) CNT(0x1)
 					02: 90000001 1ffff688 00000002	   (S)FETCH:	SAMPLE	R0.xyzw = R0.xyz CONST(0) LOCATION(CENTER)
@@ -1686,31 +1686,31 @@ t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
 					    0000 0000 0000            	NOP
 0122e140:			0000: c00d2b00 00000001 0000000c 00031002 00001000 c4000000 00021003 00002000
 0122e160:			0020: 00000000 90000001 1ffff688 00000002 000f8000 00000000 c2000000
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 }
 0122e17c:			0000: c0012d00 00040181 00000106
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
 0122e188:			0000: c0012d00 00040180 10030002
-t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
+			opcode: CP_SET_CONSTANT (2d) (6 dwords)
 0122e19c:				0.000000 0.000000 0.000000 0.000000
 0122e194:			0000: c0042d00 00000080 00000000 00000000 00000000 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
 0122e1ac:			0000: c0012d00 00040202 00000c20
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
 0122e1b8:			0000: c0012d00 00040201 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 0122e1c4:			0000: c0012d00 00040104 0000000f
-t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
+			opcode: CP_SET_CONSTANT (2d) (6 dwords)
 				RB_BLEND_RED: 0
 				RB_BLEND_GREEN: 0
 				RB_BLEND_BLUE: 0
 				RB_BLEND_ALPHA: 0
 0122e1d0:			0000: c0042d00 00040105 00000000 00000000 00000000 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
+			opcode: CP_SET_CONSTANT (2d) (8 dwords)
 			set texture const 0000
 				clamp x/y/z: clamp-last-texel/clamp-last-texel/clamp-last-texel
 				filter min/mag: point/point
@@ -1718,23 +1718,23 @@ t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
 				addr=01254000 (flags=820), size=4x8, pitch=32, format=FMT_1_REVERSE
 				mipaddr=00000000 (flags=200)
 0122e1e8:			0000: c0062d00 00010000 00424800 01254820 0000e003 00000d11 00000000 00000200
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				VGT_INDX_OFFSET: 0
 0122e208:			0000: c0012d00 00040102 00000000
-t0			write TC_CNTL_STATUS (0e00)
+			write TC_CNTL_STATUS (0e00)
 				TC_CNTL_STATUS: { L2_INVALIDATE }
 0122e214:			0000: 00000e00 00000001
-t3			opcode: CP_WAIT_REG_EQ (52) (5 dwords)
+			opcode: CP_WAIT_REG_EQ (52) (5 dwords)
 0122e21c:			0000: c0035200 000005d0 00000000 00001000 00000001
-t3			opcode: CP_DRAW_INDX_BIN (34) (7 dwords)
+			opcode: CP_DRAW_INDX_BIN (34) (7 dwords)
 0122e230:			0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 29
 				:0,0,33,29
 0122e24c:			0000: 0000057f 0000001d
-t3			opcode: CP_NOP (10) (2 dwords)
+			opcode: CP_NOP (10) (2 dwords)
 0122e254:			0000: c0001000 00000000
-t3			opcode: CP_DRAW_INDX (22) (3 dwords)
+			opcode: CP_DRAW_INDX (22) (3 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRIFAN | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x40000 }
 			draw:          0
@@ -1810,220 +1810,220 @@ t3			opcode: CP_DRAW_INDX (22) (3 dwords)
  +	0003c000			RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
  +	ffffffff			RB_COLOR_DEST_MASK: 0xffffffff
 0122e25c:			0000: c0012200 00000000 00040085
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 30
 				:0,0,33,30
 0122e268:			0000: 0000057f 0000001e
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 0122e270:			0000: c0002600 00000000
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e278:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e280:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e288:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e290:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e298:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2a0:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2a8:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2b0:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2b8:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2c0:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2c8:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2d0:			0000: c0004600 00000006
 0122d1d8:		0000: c0013700 0122e000 000000b6
-t2		nop
+		nop
 ############################################################
 vertices: 0
 cmd: deqp-gles2/185: fence=1255
 ############################################################
 cmdstream[5]: 124 dwords
-t0		write RB_BC_CONTROL (0f01)
+		write RB_BC_CONTROL (0f01)
 			RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 }
 0122f000:		0000: 00000f01 1c004046
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 }
 0122f008:		0000: c0012d00 00040293 00000020
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
 0122f014:		0000: c0012d00 00040316 00000002
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 }
 0122f020:		0000: c0012d00 00040317 00000002
-t0		write CP_PERFMON_CNTL (0444)
+		write CP_PERFMON_CNTL (0444)
 			CP_PERFMON_CNTL: 0
 0122f02c:		0000: 00000444 00000000
-t0		write RBBM_PM_OVERRIDE1 (039c)
+		write RBBM_PM_OVERRIDE1 (039c)
 			RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
 			RBBM_PM_OVERRIDE2: 0xfff
 0122f034:		0000: 0001039c ffffffff 00000fff
-t0		write TP0_CHICKEN (0e1e)
+		write TP0_CHICKEN (0e1e)
 			TP0_CHICKEN: 0x2
 0122f040:		0000: 00000e1e 00000002
-t3		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
+		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
 0122f048:		0000: c0003b00 00007fff
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			SQ_VS_CONST: { BASE = 32 | SIZE = 256 }
 0122f050:		0000: c0012d00 00040307 00100020
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			SQ_PS_CONST: { BASE = 288 | SIZE = 224 }
 0122f05c:		0000: c0012d00 00040308 000e0120
-t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
+		opcode: CP_SET_CONSTANT (2d) (4 dwords)
 			VGT_MAX_VTX_INDX: 0xffffffff
 			VGT_MIN_VTX_INDX: 0
 0122f068:		0000: c0022d00 00040100 ffffffff 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			VGT_INDX_OFFSET: 0
 0122f078:		0000: c0012d00 00040102 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			SQ_CONTEXT_MISC: { SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 }
 0122f084:		0000: c0012d00 00040181 00000004
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 }
 0122f090:		0000: c0012d00 00040182 ffffffff
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
 0122f09c:		0000: c0012d00 00040301 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_LINE_CNTL: { BRES_CNTL = 0 }
 0122f0a8:		0000: c0012d00 00040300 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
 0122f0b4:		0000: c0012d00 00040080 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
 0122f0c0:		0000: c0012d00 00040208 00000004
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_SAMPLE_POS: 0x88888888
 0122f0cc:		0000: c0012d00 0004020a 88888888
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_COLOR_DEST_MASK: 0xffffffff
 0122f0d8:		0000: c0012d00 00040326 ffffffff
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 0122f0e4:		0000: c0012d00 0004031b 0003c000
-t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
+		opcode: CP_SET_CONSTANT (2d) (4 dwords)
 			SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 }
 			SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 }
 0122f0f0:		0000: c0022d00 00040183 00000000 00000000
-t3		opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords)
+		opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords)
 0122f100:		0000: c0004b00 00000000
-t3		opcode: CP_WAIT_REG_EQ (52) (5 dwords)
+		opcode: CP_WAIT_REG_EQ (52) (5 dwords)
 0122f108:		0000: c0035200 000005d0 00000000 5f601000 00000001
-t0		write SQ_INST_STORE_MANAGMENT (0d02)
+		write SQ_INST_STORE_MANAGMENT (0d02)
 			SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 }
 0122f11c:		0000: 00000d02 00000180
-t3		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
+		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
 0122f124:		0000: c0003b00 00000300
-t3		opcode: CP_SET_SHADER_BASES (4a) (2 dwords)
+		opcode: CP_SET_SHADER_BASES (4a) (2 dwords)
 0122f12c:		0000: c0004a00 80000180
-t3		opcode: CP_SET_CONSTANT (2d) (14 dwords)
+		opcode: CP_SET_CONSTANT (2d) (14 dwords)
 0122f13c:			0.000000 0.000000 0.000000 0.000000 20000.000000 1.000000 0.500000 0.000000
 0122f15c:			2.000000 0.750000 0.375000 0.250000
 0122f134:		0000: c00c2d00 00000000 00000000 00000000 00000000 00000000 469c4000 3f800000
 0122f154:		0020: 3f000000 00000000 40000000 3f400000 3ec00000 3e800000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 0122f16c:		0000: c0012d00 00040104 0000000f
-t3		opcode: CP_SET_CONSTANT (2d) (6 dwords)
+		opcode: CP_SET_CONSTANT (2d) (6 dwords)
 			RB_BLEND_RED: 0
 			RB_BLEND_GREEN: 0
 			RB_BLEND_BLUE: 0
 			RB_BLEND_ALPHA: 0xff
 0122f178:		0000: c0042d00 00040105 00000000 00000000 00000000 000000ff
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT }
 0122f190:		0000: c0012d00 00040206 0000043f
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 }
 0122f19c:		0000: c0012d00 00040000 00000020
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_COLOR_INFO: { FORMAT = COLORX_16_16_16_16_FLOAT | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0x124a000 }
 0122f1a8:		0000: c0012d00 00040001 0124a009
-t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
+		opcode: CP_SET_CONSTANT (2d) (4 dwords)
 			PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 }
 			PA_SC_SCREEN_SCISSOR_BR: { X = 2 | Y = 4 }
 0122f1b4:		0000: c0022d00 0004000e 80000000 00040002
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
 0122f1c4:		0000: c0012d00 00040080 00000000
-t0		write CP_SCRATCH_REG6 (057e)
+		write CP_SCRATCH_REG6 (057e)
 			CP_SCRATCH_REG6: 39
 			:0,0,39,30
 0122f1d0:		0000: 0000057e 00000027
-t3		opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
+		opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
 		ibaddr:0122e000
 		ibsize:000000b6
-t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
+			opcode: CP_SET_CONSTANT (2d) (6 dwords)
 			set shader const 0078
 0122e000:			0000: c0042d00 00010078 0112d283 00100000 0112d283 00100000
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				PA_SC_AA_MASK: 0xffff
 0122e018:			0000: c0012d00 00040312 0000ffff
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
 0122e024:			0000: c0012d00 00040200 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (5 dwords)
+			opcode: CP_SET_CONSTANT (2d) (5 dwords)
 				RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
 				RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
 				RB_ALPHA_REF: 0
 0122e030:			0000: c0032d00 0004010c 00000000 00000000 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
+			opcode: CP_SET_CONSTANT (2d) (4 dwords)
 				PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
 				PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST }
 0122e044:			0000: c0022d00 00040204 00000000 00090244
-t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
+			opcode: CP_SET_CONSTANT (2d) (6 dwords)
 				PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 }
 				PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 }
 				PA_SU_LINE_CNTL: { WIDTH = 0.000000 }
 				PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER }
 0122e054:			0000: c0042d00 00040280 00000000 00000000 00000000 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (7 dwords)
+			opcode: CP_SET_CONSTANT (2d) (7 dwords)
 				PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH }
 				PA_CL_GB_VERT_CLIP_ADJ: 1.000000
 				PA_CL_GB_VERT_DISC_ADJ: 1.000000
 				PA_CL_GB_HORZ_CLIP_ADJ: 1.000000
 				PA_CL_GB_HORZ_DISC_ADJ: 1.000000
 0122e06c:			0000: c0052d00 00040302 00000001 3f800000 3f800000 3f800000 3f800000
-t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
+			opcode: CP_SET_CONSTANT (2d) (4 dwords)
 				PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
 				PA_SC_WINDOW_SCISSOR_BR: { X = 2 | Y = 4 }
 0122e088:			0000: c0022d00 00040081 00000000 00040002
-t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
+			opcode: CP_SET_CONSTANT (2d) (8 dwords)
 				PA_CL_VPORT_XSCALE: 1.000000
 				PA_CL_VPORT_XOFFSET: 1.000000
 				PA_CL_VPORT_YSCALE: 2.000000
@@ -2031,11 +2031,11 @@ t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
 				PA_CL_VPORT_ZSCALE: 0.000000
 				PA_CL_VPORT_ZOFFSET: 0.000000
 0122e098:			0000: c0062d00 0004010f 3f800000 3f800000 40000000 40000000 00000000 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (10 dwords)
+			opcode: CP_SET_CONSTANT (2d) (10 dwords)
 0122e0c0:				1.000000 2.000000 0.000000 0.000000 1.000000 2.000000 0.000000 0.000000
 0122e0b8:			0000: c0082d00 00000184 3f800000 40000000 00000000 00000000 3f800000 40000000
 *
-t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords)
+			opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords)
 			vertex shader, start=0000, size=0015
 					    2003 0007 1000            	EXEC ADDR(0x3) CNT(0x2)
 					03: 19481000 00262688 00000020	   (S)FETCH:	VERTEX	R1.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) CONST(20, 0)
@@ -2050,7 +2050,7 @@ t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords)
 0122e0e0:			0000: c0162b00 00000000 00000015 00072003 00001000 c2000000 00021005 00001000
 0122e100:			0020: c4000000 00001006 00002000 00000000 19481000 00262688 00000020 13480000
 0122e120:			0040: 40262688 00001020 000f803e 00000000 c2010100 000f8000 00000000 c2000000
-t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
+			opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
 			fragment shader, start=0000, size=000c
 					    1002 0003 1000            	EXEC ADDR(0x2) CNT(0x1)
 					02: 90000001 1ffff688 00000002	   (S)FETCH:	SAMPLE	R0.xyzw = R0.xyz CONST(0) LOCATION(CENTER)
@@ -2060,31 +2060,31 @@ t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
 					    0000 0000 0000            	NOP
 0122e140:			0000: c00d2b00 00000001 0000000c 00031002 00001000 c4000000 00021003 00002000
 0122e160:			0020: 00000000 90000001 1ffff688 00000002 000f8000 00000000 c2000000
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 }
 0122e17c:			0000: c0012d00 00040181 00000106
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
 0122e188:			0000: c0012d00 00040180 10030002
-t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
+			opcode: CP_SET_CONSTANT (2d) (6 dwords)
 0122e19c:				0.000000 0.000000 0.000000 0.000000
 0122e194:			0000: c0042d00 00000080 00000000 00000000 00000000 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
 0122e1ac:			0000: c0012d00 00040202 00000c20
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
 0122e1b8:			0000: c0012d00 00040201 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 0122e1c4:			0000: c0012d00 00040104 0000000f
-t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
+			opcode: CP_SET_CONSTANT (2d) (6 dwords)
 				RB_BLEND_RED: 0
 				RB_BLEND_GREEN: 0
 				RB_BLEND_BLUE: 0
 				RB_BLEND_ALPHA: 0
 0122e1d0:			0000: c0042d00 00040105 00000000 00000000 00000000 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
+			opcode: CP_SET_CONSTANT (2d) (8 dwords)
 			set texture const 0000
 				clamp x/y/z: clamp-last-texel/clamp-last-texel/clamp-last-texel
 				filter min/mag: point/point
@@ -2092,23 +2092,23 @@ t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
 				addr=01254000 (flags=820), size=2x4, pitch=32, format=FMT_1_REVERSE
 				mipaddr=00000000 (flags=200)
 0122e1e8:			0000: c0062d00 00010000 00424800 01254820 00006001 00000d11 00000000 00000200
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				VGT_INDX_OFFSET: 0
 0122e208:			0000: c0012d00 00040102 00000000
-t0			write TC_CNTL_STATUS (0e00)
+			write TC_CNTL_STATUS (0e00)
 				TC_CNTL_STATUS: { L2_INVALIDATE }
 0122e214:			0000: 00000e00 00000001
-t3			opcode: CP_WAIT_REG_EQ (52) (5 dwords)
+			opcode: CP_WAIT_REG_EQ (52) (5 dwords)
 0122e21c:			0000: c0035200 000005d0 00000000 00001000 00000001
-t3			opcode: CP_DRAW_INDX_BIN (34) (7 dwords)
+			opcode: CP_DRAW_INDX_BIN (34) (7 dwords)
 0122e230:			0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 35
 				:0,0,39,35
 0122e24c:			0000: 0000057f 00000023
-t3			opcode: CP_NOP (10) (2 dwords)
+			opcode: CP_NOP (10) (2 dwords)
 0122e254:			0000: c0001000 00000000
-t3			opcode: CP_DRAW_INDX (22) (3 dwords)
+			opcode: CP_DRAW_INDX (22) (3 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRIFAN | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x40000 }
 			draw:          0
@@ -2184,220 +2184,220 @@ t3			opcode: CP_DRAW_INDX (22) (3 dwords)
  +	0003c000			RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
  +	ffffffff			RB_COLOR_DEST_MASK: 0xffffffff
 0122e25c:			0000: c0012200 00000000 00040085
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 36
 				:0,0,39,36
 0122e268:			0000: 0000057f 00000024
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 0122e270:			0000: c0002600 00000000
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e278:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e280:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e288:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e290:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e298:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2a0:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2a8:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2b0:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2b8:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2c0:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2c8:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2d0:			0000: c0004600 00000006
 0122f1d8:		0000: c0013700 0122e000 000000b6
-t2		nop
+		nop
 ############################################################
 vertices: 0
 cmd: deqp-gles2/185: fence=1256
 ############################################################
 cmdstream[6]: 124 dwords
-t0		write RB_BC_CONTROL (0f01)
+		write RB_BC_CONTROL (0f01)
 			RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 }
 0122d000:		0000: 00000f01 1c004046
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 }
 0122d008:		0000: c0012d00 00040293 00000020
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
 0122d014:		0000: c0012d00 00040316 00000002
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 }
 0122d020:		0000: c0012d00 00040317 00000002
-t0		write CP_PERFMON_CNTL (0444)
+		write CP_PERFMON_CNTL (0444)
 			CP_PERFMON_CNTL: 0
 0122d02c:		0000: 00000444 00000000
-t0		write RBBM_PM_OVERRIDE1 (039c)
+		write RBBM_PM_OVERRIDE1 (039c)
 			RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
 			RBBM_PM_OVERRIDE2: 0xfff
 0122d034:		0000: 0001039c ffffffff 00000fff
-t0		write TP0_CHICKEN (0e1e)
+		write TP0_CHICKEN (0e1e)
 			TP0_CHICKEN: 0x2
 0122d040:		0000: 00000e1e 00000002
-t3		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
+		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
 0122d048:		0000: c0003b00 00007fff
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			SQ_VS_CONST: { BASE = 32 | SIZE = 256 }
 0122d050:		0000: c0012d00 00040307 00100020
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			SQ_PS_CONST: { BASE = 288 | SIZE = 224 }
 0122d05c:		0000: c0012d00 00040308 000e0120
-t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
+		opcode: CP_SET_CONSTANT (2d) (4 dwords)
 			VGT_MAX_VTX_INDX: 0xffffffff
 			VGT_MIN_VTX_INDX: 0
 0122d068:		0000: c0022d00 00040100 ffffffff 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			VGT_INDX_OFFSET: 0
 0122d078:		0000: c0012d00 00040102 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			SQ_CONTEXT_MISC: { SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 }
 0122d084:		0000: c0012d00 00040181 00000004
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 }
 0122d090:		0000: c0012d00 00040182 ffffffff
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
 0122d09c:		0000: c0012d00 00040301 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_LINE_CNTL: { BRES_CNTL = 0 }
 0122d0a8:		0000: c0012d00 00040300 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
 0122d0b4:		0000: c0012d00 00040080 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
 0122d0c0:		0000: c0012d00 00040208 00000004
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_SAMPLE_POS: 0x88888888
 0122d0cc:		0000: c0012d00 0004020a 88888888
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_COLOR_DEST_MASK: 0xffffffff
 0122d0d8:		0000: c0012d00 00040326 ffffffff
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 0122d0e4:		0000: c0012d00 0004031b 0003c000
-t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
+		opcode: CP_SET_CONSTANT (2d) (4 dwords)
 			SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 }
 			SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 }
 0122d0f0:		0000: c0022d00 00040183 00000000 00000000
-t3		opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords)
+		opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords)
 0122d100:		0000: c0004b00 00000000
-t3		opcode: CP_WAIT_REG_EQ (52) (5 dwords)
+		opcode: CP_WAIT_REG_EQ (52) (5 dwords)
 0122d108:		0000: c0035200 000005d0 00000000 5f601000 00000001
-t0		write SQ_INST_STORE_MANAGMENT (0d02)
+		write SQ_INST_STORE_MANAGMENT (0d02)
 			SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 }
 0122d11c:		0000: 00000d02 00000180
-t3		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
+		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
 0122d124:		0000: c0003b00 00000300
-t3		opcode: CP_SET_SHADER_BASES (4a) (2 dwords)
+		opcode: CP_SET_SHADER_BASES (4a) (2 dwords)
 0122d12c:		0000: c0004a00 80000180
-t3		opcode: CP_SET_CONSTANT (2d) (14 dwords)
+		opcode: CP_SET_CONSTANT (2d) (14 dwords)
 0122d13c:			0.000000 0.000000 0.000000 0.000000 20000.000000 1.000000 0.500000 0.000000
 0122d15c:			2.000000 0.750000 0.375000 0.250000
 0122d134:		0000: c00c2d00 00000000 00000000 00000000 00000000 00000000 469c4000 3f800000
 0122d154:		0020: 3f000000 00000000 40000000 3f400000 3ec00000 3e800000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 0122d16c:		0000: c0012d00 00040104 0000000f
-t3		opcode: CP_SET_CONSTANT (2d) (6 dwords)
+		opcode: CP_SET_CONSTANT (2d) (6 dwords)
 			RB_BLEND_RED: 0
 			RB_BLEND_GREEN: 0
 			RB_BLEND_BLUE: 0
 			RB_BLEND_ALPHA: 0xff
 0122d178:		0000: c0042d00 00040105 00000000 00000000 00000000 000000ff
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT }
 0122d190:		0000: c0012d00 00040206 0000043f
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 }
 0122d19c:		0000: c0012d00 00040000 00000020
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_COLOR_INFO: { FORMAT = COLORX_16_16_16_16_FLOAT | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0x124c000 }
 0122d1a8:		0000: c0012d00 00040001 0124c009
-t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
+		opcode: CP_SET_CONSTANT (2d) (4 dwords)
 			PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 }
 			PA_SC_SCREEN_SCISSOR_BR: { X = 1 | Y = 2 }
 0122d1b4:		0000: c0022d00 0004000e 80000000 00020001
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
 0122d1c4:		0000: c0012d00 00040080 00000000
-t0		write CP_SCRATCH_REG6 (057e)
+		write CP_SCRATCH_REG6 (057e)
 			CP_SCRATCH_REG6: 45
 			:0,0,45,36
 0122d1d0:		0000: 0000057e 0000002d
-t3		opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
+		opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
 		ibaddr:0122e000
 		ibsize:000000b6
-t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
+			opcode: CP_SET_CONSTANT (2d) (6 dwords)
 			set shader const 0078
 0122e000:			0000: c0042d00 00010078 0112d303 00100000 0112d303 00100000
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				PA_SC_AA_MASK: 0xffff
 0122e018:			0000: c0012d00 00040312 0000ffff
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
 0122e024:			0000: c0012d00 00040200 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (5 dwords)
+			opcode: CP_SET_CONSTANT (2d) (5 dwords)
 				RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
 				RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
 				RB_ALPHA_REF: 0
 0122e030:			0000: c0032d00 0004010c 00000000 00000000 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
+			opcode: CP_SET_CONSTANT (2d) (4 dwords)
 				PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
 				PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST }
 0122e044:			0000: c0022d00 00040204 00000000 00090244
-t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
+			opcode: CP_SET_CONSTANT (2d) (6 dwords)
 				PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 }
 				PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 }
 				PA_SU_LINE_CNTL: { WIDTH = 0.000000 }
 				PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER }
 0122e054:			0000: c0042d00 00040280 00000000 00000000 00000000 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (7 dwords)
+			opcode: CP_SET_CONSTANT (2d) (7 dwords)
 				PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH }
 				PA_CL_GB_VERT_CLIP_ADJ: 1.000000
 				PA_CL_GB_VERT_DISC_ADJ: 1.000000
 				PA_CL_GB_HORZ_CLIP_ADJ: 1.000000
 				PA_CL_GB_HORZ_DISC_ADJ: 1.000000
 0122e06c:			0000: c0052d00 00040302 00000001 3f800000 3f800000 3f800000 3f800000
-t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
+			opcode: CP_SET_CONSTANT (2d) (4 dwords)
 				PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
 				PA_SC_WINDOW_SCISSOR_BR: { X = 1 | Y = 2 }
 0122e088:			0000: c0022d00 00040081 00000000 00020001
-t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
+			opcode: CP_SET_CONSTANT (2d) (8 dwords)
 				PA_CL_VPORT_XSCALE: 0.500000
 				PA_CL_VPORT_XOFFSET: 0.500000
 				PA_CL_VPORT_YSCALE: 1.000000
@@ -2405,11 +2405,11 @@ t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
 				PA_CL_VPORT_ZSCALE: 0.000000
 				PA_CL_VPORT_ZOFFSET: 0.000000
 0122e098:			0000: c0062d00 0004010f 3f000000 3f000000 3f800000 3f800000 00000000 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (10 dwords)
+			opcode: CP_SET_CONSTANT (2d) (10 dwords)
 0122e0c0:				0.500000 1.000000 0.000000 0.000000 0.500000 1.000000 0.000000 0.000000
 0122e0b8:			0000: c0082d00 00000184 3f000000 3f800000 00000000 00000000 3f000000 3f800000
 *
-t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords)
+			opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords)
 			vertex shader, start=0000, size=0015
 					    2003 0007 1000            	EXEC ADDR(0x3) CNT(0x2)
 					03: 19481000 00262688 00000020	   (S)FETCH:	VERTEX	R1.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) CONST(20, 0)
@@ -2424,7 +2424,7 @@ t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords)
 0122e0e0:			0000: c0162b00 00000000 00000015 00072003 00001000 c2000000 00021005 00001000
 0122e100:			0020: c4000000 00001006 00002000 00000000 19481000 00262688 00000020 13480000
 0122e120:			0040: 40262688 00001020 000f803e 00000000 c2010100 000f8000 00000000 c2000000
-t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
+			opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
 			fragment shader, start=0000, size=000c
 					    1002 0003 1000            	EXEC ADDR(0x2) CNT(0x1)
 					02: 90000001 1ffff688 00000002	   (S)FETCH:	SAMPLE	R0.xyzw = R0.xyz CONST(0) LOCATION(CENTER)
@@ -2434,31 +2434,31 @@ t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
 					    0000 0000 0000            	NOP
 0122e140:			0000: c00d2b00 00000001 0000000c 00031002 00001000 c4000000 00021003 00002000
 0122e160:			0020: 00000000 90000001 1ffff688 00000002 000f8000 00000000 c2000000
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 }
 0122e17c:			0000: c0012d00 00040181 00000106
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
 0122e188:			0000: c0012d00 00040180 10030002
-t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
+			opcode: CP_SET_CONSTANT (2d) (6 dwords)
 0122e19c:				0.000000 0.000000 0.000000 0.000000
 0122e194:			0000: c0042d00 00000080 00000000 00000000 00000000 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
 0122e1ac:			0000: c0012d00 00040202 00000c20
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
 0122e1b8:			0000: c0012d00 00040201 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 0122e1c4:			0000: c0012d00 00040104 0000000f
-t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
+			opcode: CP_SET_CONSTANT (2d) (6 dwords)
 				RB_BLEND_RED: 0
 				RB_BLEND_GREEN: 0
 				RB_BLEND_BLUE: 0
 				RB_BLEND_ALPHA: 0
 0122e1d0:			0000: c0042d00 00040105 00000000 00000000 00000000 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
+			opcode: CP_SET_CONSTANT (2d) (8 dwords)
 			set texture const 0000
 				clamp x/y/z: clamp-last-texel/clamp-last-texel/clamp-last-texel
 				filter min/mag: point/point
@@ -2466,23 +2466,23 @@ t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
 				addr=01254000 (flags=820), size=1x2, pitch=32, format=FMT_1_REVERSE
 				mipaddr=00000000 (flags=200)
 0122e1e8:			0000: c0062d00 00010000 00424800 01254820 00002000 00000d11 00000000 00000200
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				VGT_INDX_OFFSET: 0
 0122e208:			0000: c0012d00 00040102 00000000
-t0			write TC_CNTL_STATUS (0e00)
+			write TC_CNTL_STATUS (0e00)
 				TC_CNTL_STATUS: { L2_INVALIDATE }
 0122e214:			0000: 00000e00 00000001
-t3			opcode: CP_WAIT_REG_EQ (52) (5 dwords)
+			opcode: CP_WAIT_REG_EQ (52) (5 dwords)
 0122e21c:			0000: c0035200 000005d0 00000000 00001000 00000001
-t3			opcode: CP_DRAW_INDX_BIN (34) (7 dwords)
+			opcode: CP_DRAW_INDX_BIN (34) (7 dwords)
 0122e230:			0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 41
 				:0,0,45,41
 0122e24c:			0000: 0000057f 00000029
-t3			opcode: CP_NOP (10) (2 dwords)
+			opcode: CP_NOP (10) (2 dwords)
 0122e254:			0000: c0001000 00000000
-t3			opcode: CP_DRAW_INDX (22) (3 dwords)
+			opcode: CP_DRAW_INDX (22) (3 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRIFAN | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x40000 }
 			draw:          0
@@ -2558,220 +2558,220 @@ t3			opcode: CP_DRAW_INDX (22) (3 dwords)
  +	0003c000			RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
  +	ffffffff			RB_COLOR_DEST_MASK: 0xffffffff
 0122e25c:			0000: c0012200 00000000 00040085
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 42
 				:0,0,45,42
 0122e268:			0000: 0000057f 0000002a
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 0122e270:			0000: c0002600 00000000
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e278:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e280:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e288:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e290:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e298:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2a0:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2a8:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2b0:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2b8:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2c0:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2c8:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2d0:			0000: c0004600 00000006
 0122d1d8:		0000: c0013700 0122e000 000000b6
-t2		nop
+		nop
 ############################################################
 vertices: 0
 cmd: deqp-gles2/185: fence=1257
 ############################################################
 cmdstream[7]: 124 dwords
-t0		write RB_BC_CONTROL (0f01)
+		write RB_BC_CONTROL (0f01)
 			RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 }
 0122f000:		0000: 00000f01 1c004046
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 }
 0122f008:		0000: c0012d00 00040293 00000020
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
 0122f014:		0000: c0012d00 00040316 00000002
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 }
 0122f020:		0000: c0012d00 00040317 00000002
-t0		write CP_PERFMON_CNTL (0444)
+		write CP_PERFMON_CNTL (0444)
 			CP_PERFMON_CNTL: 0
 0122f02c:		0000: 00000444 00000000
-t0		write RBBM_PM_OVERRIDE1 (039c)
+		write RBBM_PM_OVERRIDE1 (039c)
 			RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
 			RBBM_PM_OVERRIDE2: 0xfff
 0122f034:		0000: 0001039c ffffffff 00000fff
-t0		write TP0_CHICKEN (0e1e)
+		write TP0_CHICKEN (0e1e)
 			TP0_CHICKEN: 0x2
 0122f040:		0000: 00000e1e 00000002
-t3		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
+		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
 0122f048:		0000: c0003b00 00007fff
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			SQ_VS_CONST: { BASE = 32 | SIZE = 256 }
 0122f050:		0000: c0012d00 00040307 00100020
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			SQ_PS_CONST: { BASE = 288 | SIZE = 224 }
 0122f05c:		0000: c0012d00 00040308 000e0120
-t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
+		opcode: CP_SET_CONSTANT (2d) (4 dwords)
 			VGT_MAX_VTX_INDX: 0xffffffff
 			VGT_MIN_VTX_INDX: 0
 0122f068:		0000: c0022d00 00040100 ffffffff 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			VGT_INDX_OFFSET: 0
 0122f078:		0000: c0012d00 00040102 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			SQ_CONTEXT_MISC: { SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 }
 0122f084:		0000: c0012d00 00040181 00000004
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 }
 0122f090:		0000: c0012d00 00040182 ffffffff
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
 0122f09c:		0000: c0012d00 00040301 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_LINE_CNTL: { BRES_CNTL = 0 }
 0122f0a8:		0000: c0012d00 00040300 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
 0122f0b4:		0000: c0012d00 00040080 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
 0122f0c0:		0000: c0012d00 00040208 00000004
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_SAMPLE_POS: 0x88888888
 0122f0cc:		0000: c0012d00 0004020a 88888888
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_COLOR_DEST_MASK: 0xffffffff
 0122f0d8:		0000: c0012d00 00040326 ffffffff
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 0122f0e4:		0000: c0012d00 0004031b 0003c000
-t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
+		opcode: CP_SET_CONSTANT (2d) (4 dwords)
 			SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 }
 			SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 }
 0122f0f0:		0000: c0022d00 00040183 00000000 00000000
-t3		opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords)
+		opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords)
 0122f100:		0000: c0004b00 00000000
-t3		opcode: CP_WAIT_REG_EQ (52) (5 dwords)
+		opcode: CP_WAIT_REG_EQ (52) (5 dwords)
 0122f108:		0000: c0035200 000005d0 00000000 5f601000 00000001
-t0		write SQ_INST_STORE_MANAGMENT (0d02)
+		write SQ_INST_STORE_MANAGMENT (0d02)
 			SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 }
 0122f11c:		0000: 00000d02 00000180
-t3		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
+		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
 0122f124:		0000: c0003b00 00000300
-t3		opcode: CP_SET_SHADER_BASES (4a) (2 dwords)
+		opcode: CP_SET_SHADER_BASES (4a) (2 dwords)
 0122f12c:		0000: c0004a00 80000180
-t3		opcode: CP_SET_CONSTANT (2d) (14 dwords)
+		opcode: CP_SET_CONSTANT (2d) (14 dwords)
 0122f13c:			0.000000 0.000000 0.000000 0.000000 20000.000000 1.000000 0.500000 0.000000
 0122f15c:			2.000000 0.750000 0.375000 0.250000
 0122f134:		0000: c00c2d00 00000000 00000000 00000000 00000000 00000000 469c4000 3f800000
 0122f154:		0020: 3f000000 00000000 40000000 3f400000 3ec00000 3e800000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 0122f16c:		0000: c0012d00 00040104 0000000f
-t3		opcode: CP_SET_CONSTANT (2d) (6 dwords)
+		opcode: CP_SET_CONSTANT (2d) (6 dwords)
 			RB_BLEND_RED: 0
 			RB_BLEND_GREEN: 0
 			RB_BLEND_BLUE: 0
 			RB_BLEND_ALPHA: 0xff
 0122f178:		0000: c0042d00 00040105 00000000 00000000 00000000 000000ff
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT }
 0122f190:		0000: c0012d00 00040206 0000043f
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 }
 0122f19c:		0000: c0012d00 00040000 00000020
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_COLOR_INFO: { FORMAT = COLORX_16_16_16_16_FLOAT | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0x124e000 }
 0122f1a8:		0000: c0012d00 00040001 0124e009
-t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
+		opcode: CP_SET_CONSTANT (2d) (4 dwords)
 			PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 }
 			PA_SC_SCREEN_SCISSOR_BR: { X = 1 | Y = 1 }
 0122f1b4:		0000: c0022d00 0004000e 80000000 00010001
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
 0122f1c4:		0000: c0012d00 00040080 00000000
-t0		write CP_SCRATCH_REG6 (057e)
+		write CP_SCRATCH_REG6 (057e)
 			CP_SCRATCH_REG6: 51
 			:0,0,51,42
 0122f1d0:		0000: 0000057e 00000033
-t3		opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
+		opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
 		ibaddr:0122e000
 		ibsize:000000b6
-t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
+			opcode: CP_SET_CONSTANT (2d) (6 dwords)
 			set shader const 0078
 0122e000:			0000: c0042d00 00010078 0112d383 00100000 0112d383 00100000
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				PA_SC_AA_MASK: 0xffff
 0122e018:			0000: c0012d00 00040312 0000ffff
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
 0122e024:			0000: c0012d00 00040200 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (5 dwords)
+			opcode: CP_SET_CONSTANT (2d) (5 dwords)
 				RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
 				RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
 				RB_ALPHA_REF: 0
 0122e030:			0000: c0032d00 0004010c 00000000 00000000 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
+			opcode: CP_SET_CONSTANT (2d) (4 dwords)
 				PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
 				PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST }
 0122e044:			0000: c0022d00 00040204 00000000 00090244
-t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
+			opcode: CP_SET_CONSTANT (2d) (6 dwords)
 				PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 }
 				PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 }
 				PA_SU_LINE_CNTL: { WIDTH = 0.000000 }
 				PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER }
 0122e054:			0000: c0042d00 00040280 00000000 00000000 00000000 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (7 dwords)
+			opcode: CP_SET_CONSTANT (2d) (7 dwords)
 				PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH }
 				PA_CL_GB_VERT_CLIP_ADJ: 1.000000
 				PA_CL_GB_VERT_DISC_ADJ: 1.000000
 				PA_CL_GB_HORZ_CLIP_ADJ: 1.000000
 				PA_CL_GB_HORZ_DISC_ADJ: 1.000000
 0122e06c:			0000: c0052d00 00040302 00000001 3f800000 3f800000 3f800000 3f800000
-t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
+			opcode: CP_SET_CONSTANT (2d) (4 dwords)
 				PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
 				PA_SC_WINDOW_SCISSOR_BR: { X = 1 | Y = 1 }
 0122e088:			0000: c0022d00 00040081 00000000 00010001
-t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
+			opcode: CP_SET_CONSTANT (2d) (8 dwords)
 				PA_CL_VPORT_XSCALE: 0.500000
 				PA_CL_VPORT_XOFFSET: 0.500000
 				PA_CL_VPORT_YSCALE: 0.500000
@@ -2779,11 +2779,11 @@ t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
 				PA_CL_VPORT_ZSCALE: 0.000000
 				PA_CL_VPORT_ZOFFSET: 0.000000
 0122e098:			0000: c0062d00 0004010f 3f000000 3f000000 3f000000 3f000000 00000000 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (10 dwords)
+			opcode: CP_SET_CONSTANT (2d) (10 dwords)
 0122e0c0:				0.500000 0.500000 0.000000 0.000000 0.500000 0.500000 0.000000 0.000000
 0122e0b8:			0000: c0082d00 00000184 3f000000 3f000000 00000000 00000000 3f000000 3f000000
 *
-t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords)
+			opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords)
 			vertex shader, start=0000, size=0015
 					    2003 0007 1000            	EXEC ADDR(0x3) CNT(0x2)
 					03: 19481000 00262688 00000020	   (S)FETCH:	VERTEX	R1.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) CONST(20, 0)
@@ -2798,7 +2798,7 @@ t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords)
 0122e0e0:			0000: c0162b00 00000000 00000015 00072003 00001000 c2000000 00021005 00001000
 0122e100:			0020: c4000000 00001006 00002000 00000000 19481000 00262688 00000020 13480000
 0122e120:			0040: 40262688 00001020 000f803e 00000000 c2010100 000f8000 00000000 c2000000
-t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
+			opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
 			fragment shader, start=0000, size=000c
 					    1002 0003 1000            	EXEC ADDR(0x2) CNT(0x1)
 					02: 90000001 1ffff688 00000002	   (S)FETCH:	SAMPLE	R0.xyzw = R0.xyz CONST(0) LOCATION(CENTER)
@@ -2808,31 +2808,31 @@ t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
 					    0000 0000 0000            	NOP
 0122e140:			0000: c00d2b00 00000001 0000000c 00031002 00001000 c4000000 00021003 00002000
 0122e160:			0020: 00000000 90000001 1ffff688 00000002 000f8000 00000000 c2000000
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 }
 0122e17c:			0000: c0012d00 00040181 00000106
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
 0122e188:			0000: c0012d00 00040180 10030002
-t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
+			opcode: CP_SET_CONSTANT (2d) (6 dwords)
 0122e19c:				0.000000 0.000000 0.000000 0.000000
 0122e194:			0000: c0042d00 00000080 00000000 00000000 00000000 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
 0122e1ac:			0000: c0012d00 00040202 00000c20
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
 0122e1b8:			0000: c0012d00 00040201 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 0122e1c4:			0000: c0012d00 00040104 0000000f
-t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
+			opcode: CP_SET_CONSTANT (2d) (6 dwords)
 				RB_BLEND_RED: 0
 				RB_BLEND_GREEN: 0
 				RB_BLEND_BLUE: 0
 				RB_BLEND_ALPHA: 0
 0122e1d0:			0000: c0042d00 00040105 00000000 00000000 00000000 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
+			opcode: CP_SET_CONSTANT (2d) (8 dwords)
 			set texture const 0000
 				clamp x/y/z: clamp-last-texel/clamp-last-texel/clamp-last-texel
 				filter min/mag: point/point
@@ -2840,23 +2840,23 @@ t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
 				addr=01254000 (flags=820), size=1x1, pitch=32, format=FMT_1_REVERSE
 				mipaddr=00000000 (flags=200)
 0122e1e8:			0000: c0062d00 00010000 00424800 01254820 00000000 00000d11 00000000 00000200
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				VGT_INDX_OFFSET: 0
 0122e208:			0000: c0012d00 00040102 00000000
-t0			write TC_CNTL_STATUS (0e00)
+			write TC_CNTL_STATUS (0e00)
 				TC_CNTL_STATUS: { L2_INVALIDATE }
 0122e214:			0000: 00000e00 00000001
-t3			opcode: CP_WAIT_REG_EQ (52) (5 dwords)
+			opcode: CP_WAIT_REG_EQ (52) (5 dwords)
 0122e21c:			0000: c0035200 000005d0 00000000 00001000 00000001
-t3			opcode: CP_DRAW_INDX_BIN (34) (7 dwords)
+			opcode: CP_DRAW_INDX_BIN (34) (7 dwords)
 0122e230:			0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 47
 				:0,0,51,47
 0122e24c:			0000: 0000057f 0000002f
-t3			opcode: CP_NOP (10) (2 dwords)
+			opcode: CP_NOP (10) (2 dwords)
 0122e254:			0000: c0001000 00000000
-t3			opcode: CP_DRAW_INDX (22) (3 dwords)
+			opcode: CP_DRAW_INDX (22) (3 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRIFAN | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x40000 }
 			draw:          0
@@ -2932,220 +2932,220 @@ t3			opcode: CP_DRAW_INDX (22) (3 dwords)
  +	0003c000			RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
  +	ffffffff			RB_COLOR_DEST_MASK: 0xffffffff
 0122e25c:			0000: c0012200 00000000 00040085
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 48
 				:0,0,51,48
 0122e268:			0000: 0000057f 00000030
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 0122e270:			0000: c0002600 00000000
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e278:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e280:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e288:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e290:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e298:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2a0:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2a8:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2b0:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2b8:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2c0:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2c8:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2d0:			0000: c0004600 00000006
 0122f1d8:		0000: c0013700 0122e000 000000b6
-t2		nop
+		nop
 ############################################################
 vertices: 0
 cmd: deqp-gles2/185: fence=1258
 ############################################################
 cmdstream[8]: 124 dwords
-t0		write RB_BC_CONTROL (0f01)
+		write RB_BC_CONTROL (0f01)
 			RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 }
 0122d000:		0000: 00000f01 1c004046
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 }
 0122d008:		0000: c0012d00 00040293 00000020
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
 0122d014:		0000: c0012d00 00040316 00000002
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 }
 0122d020:		0000: c0012d00 00040317 00000002
-t0		write CP_PERFMON_CNTL (0444)
+		write CP_PERFMON_CNTL (0444)
 			CP_PERFMON_CNTL: 0
 0122d02c:		0000: 00000444 00000000
-t0		write RBBM_PM_OVERRIDE1 (039c)
+		write RBBM_PM_OVERRIDE1 (039c)
 			RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
 			RBBM_PM_OVERRIDE2: 0xfff
 0122d034:		0000: 0001039c ffffffff 00000fff
-t0		write TP0_CHICKEN (0e1e)
+		write TP0_CHICKEN (0e1e)
 			TP0_CHICKEN: 0x2
 0122d040:		0000: 00000e1e 00000002
-t3		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
+		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
 0122d048:		0000: c0003b00 00007fff
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			SQ_VS_CONST: { BASE = 32 | SIZE = 256 }
 0122d050:		0000: c0012d00 00040307 00100020
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			SQ_PS_CONST: { BASE = 288 | SIZE = 224 }
 0122d05c:		0000: c0012d00 00040308 000e0120
-t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
+		opcode: CP_SET_CONSTANT (2d) (4 dwords)
 			VGT_MAX_VTX_INDX: 0xffffffff
 			VGT_MIN_VTX_INDX: 0
 0122d068:		0000: c0022d00 00040100 ffffffff 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			VGT_INDX_OFFSET: 0
 0122d078:		0000: c0012d00 00040102 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			SQ_CONTEXT_MISC: { SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 }
 0122d084:		0000: c0012d00 00040181 00000004
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 }
 0122d090:		0000: c0012d00 00040182 ffffffff
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
 0122d09c:		0000: c0012d00 00040301 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_LINE_CNTL: { BRES_CNTL = 0 }
 0122d0a8:		0000: c0012d00 00040300 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
 0122d0b4:		0000: c0012d00 00040080 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
 0122d0c0:		0000: c0012d00 00040208 00000004
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_SAMPLE_POS: 0x88888888
 0122d0cc:		0000: c0012d00 0004020a 88888888
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_COLOR_DEST_MASK: 0xffffffff
 0122d0d8:		0000: c0012d00 00040326 ffffffff
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 0122d0e4:		0000: c0012d00 0004031b 0003c000
-t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
+		opcode: CP_SET_CONSTANT (2d) (4 dwords)
 			SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 }
 			SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 }
 0122d0f0:		0000: c0022d00 00040183 00000000 00000000
-t3		opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords)
+		opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords)
 0122d100:		0000: c0004b00 00000000
-t3		opcode: CP_WAIT_REG_EQ (52) (5 dwords)
+		opcode: CP_WAIT_REG_EQ (52) (5 dwords)
 0122d108:		0000: c0035200 000005d0 00000000 5f601000 00000001
-t0		write SQ_INST_STORE_MANAGMENT (0d02)
+		write SQ_INST_STORE_MANAGMENT (0d02)
 			SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 }
 0122d11c:		0000: 00000d02 00000180
-t3		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
+		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
 0122d124:		0000: c0003b00 00000300
-t3		opcode: CP_SET_SHADER_BASES (4a) (2 dwords)
+		opcode: CP_SET_SHADER_BASES (4a) (2 dwords)
 0122d12c:		0000: c0004a00 80000180
-t3		opcode: CP_SET_CONSTANT (2d) (14 dwords)
+		opcode: CP_SET_CONSTANT (2d) (14 dwords)
 0122d13c:			0.000000 0.000000 0.000000 0.000000 20000.000000 1.000000 0.500000 0.000000
 0122d15c:			2.000000 0.750000 0.375000 0.250000
 0122d134:		0000: c00c2d00 00000000 00000000 00000000 00000000 00000000 469c4000 3f800000
 0122d154:		0020: 3f000000 00000000 40000000 3f400000 3ec00000 3e800000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 0122d16c:		0000: c0012d00 00040104 0000000f
-t3		opcode: CP_SET_CONSTANT (2d) (6 dwords)
+		opcode: CP_SET_CONSTANT (2d) (6 dwords)
 			RB_BLEND_RED: 0
 			RB_BLEND_GREEN: 0
 			RB_BLEND_BLUE: 0
 			RB_BLEND_ALPHA: 0xff
 0122d178:		0000: c0042d00 00040105 00000000 00000000 00000000 000000ff
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT }
 0122d190:		0000: c0012d00 00040206 0000043f
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_SURFACE_INFO: { SURFACE_PITCH = 64 | MSAA_SAMPLES = 0 }
 0122d19c:		0000: c0012d00 00040000 00000040
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_COLOR_INFO: { FORMAT = COLORX_16_16_16_16_FLOAT | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0x1230000 }
 0122d1a8:		0000: c0012d00 00040001 01230009
-t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
+		opcode: CP_SET_CONSTANT (2d) (4 dwords)
 			PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 }
 			PA_SC_SCREEN_SCISSOR_BR: { X = 64 | Y = 128 }
 0122d1b4:		0000: c0022d00 0004000e 80000000 00800040
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
 0122d1c4:		0000: c0012d00 00040080 00000000
-t0		write CP_SCRATCH_REG6 (057e)
+		write CP_SCRATCH_REG6 (057e)
 			CP_SCRATCH_REG6: 57
 			:0,0,57,48
 0122d1d0:		0000: 0000057e 00000039
-t3		opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
+		opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
 		ibaddr:0122e000
 		ibsize:000000b6
-t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
+			opcode: CP_SET_CONSTANT (2d) (6 dwords)
 			set shader const 0078
 0122e000:			0000: c0042d00 00010078 0112d403 00100000 0112d403 00100000
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				PA_SC_AA_MASK: 0xffff
 0122e018:			0000: c0012d00 00040312 0000ffff
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
 0122e024:			0000: c0012d00 00040200 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (5 dwords)
+			opcode: CP_SET_CONSTANT (2d) (5 dwords)
 				RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
 				RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
 				RB_ALPHA_REF: 0
 0122e030:			0000: c0032d00 0004010c 00000000 00000000 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
+			opcode: CP_SET_CONSTANT (2d) (4 dwords)
 				PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
 				PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST }
 0122e044:			0000: c0022d00 00040204 00000000 00090244
-t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
+			opcode: CP_SET_CONSTANT (2d) (6 dwords)
 				PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 }
 				PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 }
 				PA_SU_LINE_CNTL: { WIDTH = 0.000000 }
 				PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER }
 0122e054:			0000: c0042d00 00040280 00000000 00000000 00000000 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (7 dwords)
+			opcode: CP_SET_CONSTANT (2d) (7 dwords)
 				PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH }
 				PA_CL_GB_VERT_CLIP_ADJ: 1.000000
 				PA_CL_GB_VERT_DISC_ADJ: 1.000000
 				PA_CL_GB_HORZ_CLIP_ADJ: 1.000000
 				PA_CL_GB_HORZ_DISC_ADJ: 1.000000
 0122e06c:			0000: c0052d00 00040302 00000001 3f800000 3f800000 3f800000 3f800000
-t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
+			opcode: CP_SET_CONSTANT (2d) (4 dwords)
 				PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
 				PA_SC_WINDOW_SCISSOR_BR: { X = 64 | Y = 128 }
 0122e088:			0000: c0022d00 00040081 00000000 00800040
-t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
+			opcode: CP_SET_CONSTANT (2d) (8 dwords)
 				PA_CL_VPORT_XSCALE: 32.000000
 				PA_CL_VPORT_XOFFSET: 32.000000
 				PA_CL_VPORT_YSCALE: 64.000000
@@ -3153,11 +3153,11 @@ t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
 				PA_CL_VPORT_ZSCALE: 0.000000
 				PA_CL_VPORT_ZOFFSET: 0.000000
 0122e098:			0000: c0062d00 0004010f 42000000 42000000 42800000 42800000 00000000 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (10 dwords)
+			opcode: CP_SET_CONSTANT (2d) (10 dwords)
 0122e0c0:				32.000000 64.000000 0.000000 0.000000 32.000000 64.000000 0.000000 0.000000
 0122e0b8:			0000: c0082d00 00000184 42000000 42800000 00000000 00000000 42000000 42800000
 *
-t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords)
+			opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords)
 			vertex shader, start=0000, size=0015
 					    2003 0007 1000            	EXEC ADDR(0x3) CNT(0x2)
 					03: 19481000 00262688 00000020	   (S)FETCH:	VERTEX	R1.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) CONST(20, 0)
@@ -3172,7 +3172,7 @@ t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords)
 0122e0e0:			0000: c0162b00 00000000 00000015 00072003 00001000 c2000000 00021005 00001000
 0122e100:			0020: c4000000 00001006 00002000 00000000 19481000 00262688 00000020 13480000
 0122e120:			0040: 40262688 00001020 000f803e 00000000 c2010100 000f8000 00000000 c2000000
-t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
+			opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
 			fragment shader, start=0000, size=000c
 					    1002 0003 1000            	EXEC ADDR(0x2) CNT(0x1)
 					02: 90000001 1ffff688 00000002	   (S)FETCH:	SAMPLE	R0.xyzw = R0.xyz CONST(0) LOCATION(CENTER)
@@ -3182,31 +3182,31 @@ t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
 					    0000 0000 0000            	NOP
 0122e140:			0000: c00d2b00 00000001 0000000c 00031002 00001000 c4000000 00021003 00002000
 0122e160:			0020: 00000000 90000001 1ffff688 00000002 000f8000 00000000 c2000000
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 }
 0122e17c:			0000: c0012d00 00040181 00000106
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
 0122e188:			0000: c0012d00 00040180 10030002
-t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
+			opcode: CP_SET_CONSTANT (2d) (6 dwords)
 0122e19c:				0.000000 0.000000 0.000000 0.000000
 0122e194:			0000: c0042d00 00000080 00000000 00000000 00000000 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
 0122e1ac:			0000: c0012d00 00040202 00000c20
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
 0122e1b8:			0000: c0012d00 00040201 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 0122e1c4:			0000: c0012d00 00040104 0000000f
-t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
+			opcode: CP_SET_CONSTANT (2d) (6 dwords)
 				RB_BLEND_RED: 0
 				RB_BLEND_GREEN: 0
 				RB_BLEND_BLUE: 0
 				RB_BLEND_ALPHA: 0
 0122e1d0:			0000: c0042d00 00040105 00000000 00000000 00000000 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
+			opcode: CP_SET_CONSTANT (2d) (8 dwords)
 			set texture const 0000
 				clamp x/y/z: clamp-last-texel/clamp-last-texel/clamp-last-texel
 				filter min/mag: point/point
@@ -3214,23 +3214,23 @@ t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
 				addr=0110d000 (flags=820), size=64x128, pitch=16448, format=FMT_1_REVERSE
 				mipaddr=00000000 (flags=200)
 0122e1e8:			0000: c0062d00 00010000 80824800 0110d820 000fe03f 00000d11 00000000 00000200
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				VGT_INDX_OFFSET: 0
 0122e208:			0000: c0012d00 00040102 00000000
-t0			write TC_CNTL_STATUS (0e00)
+			write TC_CNTL_STATUS (0e00)
 				TC_CNTL_STATUS: { L2_INVALIDATE }
 0122e214:			0000: 00000e00 00000001
-t3			opcode: CP_WAIT_REG_EQ (52) (5 dwords)
+			opcode: CP_WAIT_REG_EQ (52) (5 dwords)
 0122e21c:			0000: c0035200 000005d0 00000000 00001000 00000001
-t3			opcode: CP_DRAW_INDX_BIN (34) (7 dwords)
+			opcode: CP_DRAW_INDX_BIN (34) (7 dwords)
 0122e230:			0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 53
 				:0,0,57,53
 0122e24c:			0000: 0000057f 00000035
-t3			opcode: CP_NOP (10) (2 dwords)
+			opcode: CP_NOP (10) (2 dwords)
 0122e254:			0000: c0001000 00000000
-t3			opcode: CP_DRAW_INDX (22) (3 dwords)
+			opcode: CP_DRAW_INDX (22) (3 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRIFAN | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x40000 }
 			draw:          0
@@ -3306,196 +3306,196 @@ t3			opcode: CP_DRAW_INDX (22) (3 dwords)
  +	0003c000			RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
  +	ffffffff			RB_COLOR_DEST_MASK: 0xffffffff
 0122e25c:			0000: c0012200 00000000 00040085
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 54
 				:0,0,57,54
 0122e268:			0000: 0000057f 00000036
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 0122e270:			0000: c0002600 00000000
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e278:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e280:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e288:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e290:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e298:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2a0:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2a8:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2b0:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2b8:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2c0:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2c8:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2d0:			0000: c0004600 00000006
 0122d1d8:		0000: c0013700 0122e000 000000b6
-t2		nop
+		nop
 ############################################################
 vertices: 0
 cmd: deqp-gles2/185: fence=1259
 ############################################################
 cmdstream[9]: 340 dwords
-t0		write RB_BC_CONTROL (0f01)
+		write RB_BC_CONTROL (0f01)
 			RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 }
 0110a000:		0000: 00000f01 1c004046
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 }
 0110a008:		0000: c0012d00 00040293 00000020
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
 0110a014:		0000: c0012d00 00040316 00000002
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 }
 0110a020:		0000: c0012d00 00040317 00000002
-t0		write CP_PERFMON_CNTL (0444)
+		write CP_PERFMON_CNTL (0444)
 			CP_PERFMON_CNTL: 0
 0110a02c:		0000: 00000444 00000000
-t0		write RBBM_PM_OVERRIDE1 (039c)
+		write RBBM_PM_OVERRIDE1 (039c)
 			RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
 			RBBM_PM_OVERRIDE2: 0xfff
 0110a034:		0000: 0001039c ffffffff 00000fff
-t0		write TP0_CHICKEN (0e1e)
+		write TP0_CHICKEN (0e1e)
 			TP0_CHICKEN: 0x2
 0110a040:		0000: 00000e1e 00000002
-t3		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
+		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
 0110a048:		0000: c0003b00 00007fff
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			SQ_VS_CONST: { BASE = 32 | SIZE = 256 }
 0110a050:		0000: c0012d00 00040307 00100020
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			SQ_PS_CONST: { BASE = 288 | SIZE = 224 }
 0110a05c:		0000: c0012d00 00040308 000e0120
-t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
+		opcode: CP_SET_CONSTANT (2d) (4 dwords)
 			VGT_MAX_VTX_INDX: 0xffffffff
 			VGT_MIN_VTX_INDX: 0
 0110a068:		0000: c0022d00 00040100 ffffffff 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			VGT_INDX_OFFSET: 0
 0110a078:		0000: c0012d00 00040102 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			SQ_CONTEXT_MISC: { SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 }
 0110a084:		0000: c0012d00 00040181 00000004
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 }
 0110a090:		0000: c0012d00 00040182 ffffffff
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
 0110a09c:		0000: c0012d00 00040301 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_LINE_CNTL: { BRES_CNTL = 0 }
 0110a0a8:		0000: c0012d00 00040300 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
 0110a0b4:		0000: c0012d00 00040080 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
 0110a0c0:		0000: c0012d00 00040208 00000004
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_SAMPLE_POS: 0x88888888
 0110a0cc:		0000: c0012d00 0004020a 88888888
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_COLOR_DEST_MASK: 0xffffffff
 0110a0d8:		0000: c0012d00 00040326 ffffffff
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 0110a0e4:		0000: c0012d00 0004031b 0003c000
-t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
+		opcode: CP_SET_CONSTANT (2d) (4 dwords)
 			SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 }
 			SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 }
 0110a0f0:		0000: c0022d00 00040183 00000000 00000000
-t3		opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords)
+		opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords)
 0110a100:		0000: c0004b00 00000000
-t3		opcode: CP_WAIT_REG_EQ (52) (5 dwords)
+		opcode: CP_WAIT_REG_EQ (52) (5 dwords)
 0110a108:		0000: c0035200 000005d0 00000000 5f601000 00000001
-t0		write SQ_INST_STORE_MANAGMENT (0d02)
+		write SQ_INST_STORE_MANAGMENT (0d02)
 			SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 }
 0110a11c:		0000: 00000d02 00000180
-t3		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
+		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
 0110a124:		0000: c0003b00 00000300
-t3		opcode: CP_SET_SHADER_BASES (4a) (2 dwords)
+		opcode: CP_SET_SHADER_BASES (4a) (2 dwords)
 0110a12c:		0000: c0004a00 80000180
-t3		opcode: CP_SET_CONSTANT (2d) (14 dwords)
+		opcode: CP_SET_CONSTANT (2d) (14 dwords)
 0110a13c:			0.000000 0.000000 0.000000 0.000000 20000.000000 1.000000 0.500000 0.000000
 0110a15c:			2.000000 0.750000 0.375000 0.250000
 0110a134:		0000: c00c2d00 00000000 00000000 00000000 00000000 00000000 469c4000 3f800000
 0110a154:		0020: 3f000000 00000000 40000000 3f400000 3ec00000 3e800000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 0110a16c:		0000: c0012d00 00040104 0000000f
-t3		opcode: CP_SET_CONSTANT (2d) (6 dwords)
+		opcode: CP_SET_CONSTANT (2d) (6 dwords)
 			RB_BLEND_RED: 0
 			RB_BLEND_GREEN: 0
 			RB_BLEND_BLUE: 0
 			RB_BLEND_ALPHA: 0xff
 0110a178:		0000: c0042d00 00040105 00000000 00000000 00000000 000000ff
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT }
 0110a190:		0000: c0012d00 00040206 0000043f
-t3		opcode: CP_SET_CONSTANT (2d) (5 dwords)
+		opcode: CP_SET_CONSTANT (2d) (5 dwords)
 			RB_SURFACE_INFO: { SURFACE_PITCH = 128 | MSAA_SAMPLES = 0 }
 			RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 1 | BASE = 0 }
 			RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTHX_24_8 | DEPTH_BASE = 65536 }
 0110a19c:		0000: c0032d00 00040000 00000080 00000205 00010001
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			VGT_CURRENT_BIN_ID_MIN: { COLUMN = 0 | ROW = 0 | GUARD_BAND_MASK = 0 }
 0110a1b0:		0000: c0012d00 00040207 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			VGT_CURRENT_BIN_ID_MAX: { COLUMN = 0 | ROW = 0 | GUARD_BAND_MASK = 0 }
 0110a1bc:		0000: c0012d00 00040203 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (6 dwords)
+		opcode: CP_SET_CONSTANT (2d) (6 dwords)
 0110a1d0:			3.069580 0.000000 8441856.000000 8454144.000000
 0110a1c8:		0000: c0042d00 0000000c 40447400 00000000 4b00d000 4b010000
-t3		opcode: CP_SET_CONSTANT (2d) (10 dwords)
+		opcode: CP_SET_CONSTANT (2d) (10 dwords)
 0110a1e8:			0.125490 0.125490 0.500000 0.000000 0.000980 0.000980 0.000000 0.000000
 0110a1e0:		0000: c0082d00 0000018c 3e008081 3e008081 3f000000 00000000 3a808081 3a808081
 *
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 0 }
 0110a208:		0000: c0012d00 00040316 00000000
-t0		write CP_SCRATCH_REG6 (057e)
+		write CP_SCRATCH_REG6 (057e)
 			CP_SCRATCH_REG6: 67
 			:0,0,67,54
 0110a214:		0000: 0000057e 00000043
-t3		opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
+		opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
 		ibaddr:0110c000
 		ibsize:000000c5
-t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
+			opcode: CP_SET_CONSTANT (2d) (6 dwords)
 			set shader const 0078
 0110c000:			0000: c0042d00 00010078 0112d483 00100000 0112d4c3 00100000
-t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (102 dwords)
+			opcode: CP_IM_LOAD_IMMEDIATE (2b) (102 dwords)
 			vertex shader, start=0000, size=0063
 					    0000 0000 c400            	ALLOC PARAM/PIXEL SIZE(0x0)
 					    100b 0003 1000            	EXEC ADDR(0xb) CNT(0x1)
@@ -3555,46 +3555,46 @@ t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (102 dwords)
 0110c158:			0140: 4b010207 000f8021 00000000 4b4c054b 000f8020 20136c00 4b010208 000f8021
 0110c178:			0160: 00000000 4b4e054d 000f8020 20136c00 4b010209 000f8021 00000000 4b50054f
 0110c198:			0180: 000f8020 20136c00 4b01020a 000f8021 00000000 4b520551
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 }
 0110c1b0:			0000: c0012d00 00040181 00000006
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				SQ_PROGRAM_CNTL: { VS_REGS = 5 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 | GEN_INDEX_VTX }
 0110c1bc:			0000: c0012d00 00040180 90030005
-t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
+			opcode: CP_SET_CONSTANT (2d) (6 dwords)
 0110c1d0:				0.000000 0.000000 0.000000 0.000000
 0110c1c8:			0000: c0042d00 00000080 00000000 00000000 00000000 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (10 dwords)
+			opcode: CP_SET_CONSTANT (2d) (10 dwords)
 0110c1e8:				128.000000 128.000000 0.500000 0.000000 128.000000 -128.000000 0.500000 0.000000
 0110c1e0:			0000: c0082d00 00000184 43000000 43000000 3f000000 00000000 43000000 c3000000
 0110c200:			0020: 3f000000 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
 0110c208:			0000: c0012d00 00040201 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 0110c214:			0000: c0012d00 00040104 0000000f
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				PA_SU_SC_MODE_CNTL: { POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_POINTS | BACK_PTYPE = PC_DRAW_POINTS | FACE_KILL_ENABLE }
 0110c220:			0000: c0012d00 00040205 40000000
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				VGT_INDX_OFFSET: 0
 0110c22c:			0000: c0012d00 00040102 00000000
-t0			write TC_CNTL_STATUS (0e00)
+			write TC_CNTL_STATUS (0e00)
 				TC_CNTL_STATUS: { L2_INVALIDATE }
 0110c238:			0000: 00000e00 00000001
-t3			opcode: CP_WAIT_REG_EQ (52) (5 dwords)
+			opcode: CP_WAIT_REG_EQ (52) (5 dwords)
 0110c240:			0000: c0035200 000005d0 00000000 00001000 00000001
-t3			opcode: CP_DRAW_INDX_BIN (34) (7 dwords)
+			opcode: CP_DRAW_INDX_BIN (34) (7 dwords)
 0110c254:			0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006
-t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
+			opcode: CP_SET_CONSTANT (2d) (6 dwords)
 0110c278:				0.000000 0.000000 0.000000 0.000000
 0110c270:			0000: c0042d00 00000180 00000000 00000000 00000000 00000000
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 61
 				:0,0,67,61
 0110c288:			0000: 0000057f 0000003d
-t3			opcode: CP_DRAW_INDX (22) (5 dwords)
+			opcode: CP_DRAW_INDX (22) (5 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x60000 }
 				{ NUM_INDICES = 18011360 }
@@ -3649,123 +3649,123 @@ t3			opcode: CP_DRAW_INDX (22) (5 dwords)
  +	0003c000			RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
  +	ffffffff			RB_COLOR_DEST_MASK: 0xffffffff
 0110c290:			0000: c0032200 00000000 00060004 0112d4e0 0000000c
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 62
 				:0,0,67,62
 0110c2a4:			0000: 0000057f 0000003e
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 0110c2ac:			0000: c0002600 00000000
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0110c2b4:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0110c2bc:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0110c2c4:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0110c2cc:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0110c2d4:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0110c2dc:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0110c2e4:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0110c2ec:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0110c2f4:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0110c2fc:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0110c304:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0110c30c:			0000: c0004600 00000006
 0110a21c:		0000: c0013700 0110c000 000000c5
-t2		nop
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		nop
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
 0110a234:		0000: c0012d00 00040316 00000002
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 1 | BASE = 0 }
 0110a240:		0000: c0012d00 00040001 00000205
-t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
+		opcode: CP_SET_CONSTANT (2d) (4 dwords)
 			PA_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 }
 			PA_SC_SCREEN_SCISSOR_BR: { X = 128 | Y = 128 }
 0110a24c:		0000: c0022d00 0004000e 00000000 00800080
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 1 | BASE = 0 }
 0110a25c:		0000: c0012d00 00040001 00000205
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
 0110a268:		0000: c0012d00 00040080 00000000
-t3		opcode: CP_MEM_WRITE (3d) (3 dwords)
+		opcode: CP_MEM_WRITE (3d) (3 dwords)
 			{ ADDR_LO = 0x100903c }
 			{ ADDR_HI = 0x800080 }
 		gpuaddr:0100903c
 0110a27c:			0.000000
 0110a274:		0000: c0013d00 0100903c 00800080
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_COPY_DEST_OFFSET: { X = 0 | Y = 0 }
 0110a280:		0000: c0012d00 0004031c 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (6 dwords)
+		opcode: CP_SET_CONSTANT (2d) (6 dwords)
 0110a294:			0.000000 0.000000 0.000000 0.000000
 0110a28c:		0000: c0042d00 00000580 00000000 00000000 00000000 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			VGT_CURRENT_BIN_ID_MIN: { COLUMN = 1 | ROW = 1 | GUARD_BAND_MASK = 0 }
 0110a2a4:		0000: c0012d00 00040207 00000009
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			VGT_CURRENT_BIN_ID_MAX: { COLUMN = 1 | ROW = 1 | GUARD_BAND_MASK = 0 }
 0110a2b0:		0000: c0012d00 00040203 00000009
-t3		opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords)
+		opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords)
 0110a2bc:		0000: c0004b00 0111d000
-t0		write CP_SCRATCH_REG6 (057e)
+		write CP_SCRATCH_REG6 (057e)
 			CP_SCRATCH_REG6: 69
 			:0,0,69,62
 0110a2c4:		0000: 0000057e 00000045
-t3		opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
+		opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
 		ibaddr:0110b000
 		ibsize:00000198
-t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
+			opcode: CP_SET_CONSTANT (2d) (4 dwords)
 				PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
 				PA_SC_WINDOW_SCISSOR_BR: { X = 16383 | Y = 16383 }
 0110b000:			0000: c0022d00 00040081 00000000 3fff3fff
-t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
+			opcode: CP_SET_CONSTANT (2d) (6 dwords)
 				PA_CL_VPORT_XSCALE: 4096.000000
 				PA_CL_VPORT_XOFFSET: 4096.000000
 				PA_CL_VPORT_YSCALE: 4096.000000
 				PA_CL_VPORT_YOFFSET: 4096.000000
 0110b010:			0000: c0042d00 0004010f 45800000 45800000 45800000 45800000
-t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
+			opcode: CP_SET_CONSTANT (2d) (4 dwords)
 			set shader const 009c
 0110b028:			0000: c0022d00 0001009c 01009003 00000024
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				VGT_INDX_OFFSET: 0
 0110b038:			0000: c0012d00 00040102 00000000
-t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
+			opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
 			vertex shader, start=0000, size=000c
 					    0000 0000 c400            	ALLOC PARAM/PIXEL SIZE(0x0)
 					    1002 0003 1000            	EXEC ADDR(0x2) CNT(0x1)
@@ -3775,68 +3775,68 @@ t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
 					03: 000f803e 00000000 c2000000	   (S)ALU:	MAXv	export62 = R0, R0	; gl_Position
 0110b044:			0000: c00d2b00 00000000 0000000c 00000000 1002c400 10000003 00000000 1003c200
 0110b064:			0020: 20000002 19a80000 00392a88 0000000c 000f803e 00000000 c2000000
-t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (9 dwords)
+			opcode: CP_IM_LOAD_IMMEDIATE (2b) (9 dwords)
 			fragment shader, start=0000, size=0006
 					    0000 0000 c400            	ALLOC PARAM/PIXEL SIZE(0x0)
 					    1001 0002 2000            	EXEC_END ADDR(0x1) CNT(0x1)
 					01: 000f8000 00000000 02000000	   (S)ALU:	MAXv	export0 = C0, C0	; gl_FragColor
 0110b080:			0000: c0072b00 00000001 00000006 00000000 1001c400 20000002 000f8000 00000000
 0110b0a0:			0020: 02000000
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 }
 0110b0a4:			0000: c0012d00 00040181 00000006
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 128 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
 0110b0b0:			0000: c0012d00 00040180 10038002
-t0			write TC_CNTL_STATUS (0e00)
+			write TC_CNTL_STATUS (0e00)
 				TC_CNTL_STATUS: { L2_INVALIDATE }
 0110b0bc:			0000: 00000e00 00000001
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				RB_DEPTHCONTROL: { STENCIL_ENABLE | Z_ENABLE | Z_WRITE_ENABLE | EARLY_Z_ENABLE | ZFUNC = FUNC_ALWAYS | STENCILFUNC = FUNC_ALWAYS | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_REPLACE | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
 0110b0c4:			0000: c0012d00 00040200 0000877f
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				RB_COLORCONTROL: { ALPHA_FUNC = FUNC_ALWAYS | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
 0110b0d0:			0000: c0012d00 00040202 00000c27
-t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
+			opcode: CP_SET_CONSTANT (2d) (4 dwords)
 				PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
 				PA_SU_SC_MODE_CNTL: { POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | MSAA_ENABLE | PROVOKING_VTX_LAST }
 0110b0dc:			0000: c0022d00 00040204 00000000 00088240
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 3 | MAX_SAMPLE_DIST = 0 }
 0110b0ec:			0000: c0012d00 00040301 00000003
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				PA_SC_AA_MASK: 0xffff
 0110b0f8:			0000: c0012d00 00040312 0000ffff
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 0110b104:			0000: c0012d00 00040104 0000000f
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
 0110b110:			0000: c0012d00 00040201 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				PA_SC_SCREEN_SCISSOR_BR: { X = 32 | Y = 64 }
 0110b11c:			0000: c0012d00 0004000f 00400020
-t3			opcode: CP_SET_CONSTANT (2d) (5 dwords)
+			opcode: CP_SET_CONSTANT (2d) (5 dwords)
 				RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 2 }
 				RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0 }
 				RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTHX_24_8 | DEPTH_BASE = 32768 }
 0110b128:			0000: c0032d00 00040000 00008020 00000005 00008001
-t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
+			opcode: CP_SET_CONSTANT (2d) (6 dwords)
 0110b144:				0.501961 0.250980 0.125490 1.000000
 0110b13c:			0000: c0042d00 00000480 3f008081 3e808081 3e008081 3f800000
-t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
+			opcode: CP_SET_CONSTANT (2d) (4 dwords)
 				PA_CL_VPORT_ZSCALE: 0.000000
 				PA_CL_VPORT_ZOFFSET: 0.996586
 0110b154:			0000: c0022d00 00040113 00000000 3f7f2041
-t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
+			opcode: CP_SET_CONSTANT (2d) (4 dwords)
 				RB_STENCILREFMASK_BF: { STENCILREF = 0x80 | STENCILMASK = 0 | STENCILWRITEMASK = 0xff | 0xff000000 }
 				RB_STENCILREFMASK: { STENCILREF = 0x80 | STENCILMASK = 0 | STENCILWRITEMASK = 0xff | 0xff000000 }
 0110b164:			0000: c0022d00 0004010c ffff0080 ffff0080
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 1
 				:0,0,69,1
 0110b174:			0000: 0000057f 00000001
-t3			opcode: CP_DRAW_INDX (22) (3 dwords)
+			opcode: CP_DRAW_INDX (22) (3 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x30000 }
 			draw:          0
@@ -3881,38 +3881,38 @@ t3			opcode: CP_DRAW_INDX (22) (3 dwords)
 !+	00000002			VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
  +	00000000			RB_COPY_DEST_OFFSET: { X = 0 | Y = 0 }
 0110b17c:			0000: c0012200 00000000 00030088
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 2
 				:0,0,69,2
 0110b188:			0000: 0000057f 00000002
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
 0110b190:			0000: c0012d00 00040301 00000000
-t3			opcode: CP_LOAD_CONSTANT_CONTEXT (2e) (4 dwords)
+			opcode: CP_LOAD_CONSTANT_CONTEXT (2e) (4 dwords)
 0110b19c:			0000: c0022e00 01009000 0004000f 00000001
-t3			opcode: CP_SET_CONSTANT (2d) (5 dwords)
+			opcode: CP_SET_CONSTANT (2d) (5 dwords)
 				RB_SURFACE_INFO: { SURFACE_PITCH = 128 | MSAA_SAMPLES = 0 }
 				RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 1 | BASE = 0 }
 				RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTHX_24_8 | DEPTH_BASE = 65536 }
 0110b1ac:			0000: c0032d00 00040000 00000080 00000205 00010001
-t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
+			opcode: CP_SET_CONSTANT (2d) (4 dwords)
 				PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
 				PA_SC_WINDOW_SCISSOR_BR: { X = 16383 | Y = 16383 }
 0110b1c0:			0000: c0022d00 00040081 00000000 3fff3fff
-t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
+			opcode: CP_SET_CONSTANT (2d) (6 dwords)
 				PA_CL_VPORT_XSCALE: 4096.000000
 				PA_CL_VPORT_XOFFSET: 4096.000000
 				PA_CL_VPORT_YSCALE: 4096.000000
 				PA_CL_VPORT_YOFFSET: 4096.000000
 0110b1d0:			0000: c0042d00 0004010f 45800000 45800000 45800000 45800000
-t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
+			opcode: CP_SET_CONSTANT (2d) (4 dwords)
 			set shader const 009c
 0110b1e8:			0000: c0022d00 0001009c 01009003 00000024
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				VGT_INDX_OFFSET: 0
 0110b1f8:			0000: c0012d00 00040102 00000000
-t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
+			opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
 			vertex shader, start=0000, size=000c
 					    0000 0000 c400            	ALLOC PARAM/PIXEL SIZE(0x0)
 					    1002 0003 1000            	EXEC ADDR(0x2) CNT(0x1)
@@ -3922,70 +3922,70 @@ t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
 					03: 000f803e 00000000 c2000000	   (S)ALU:	MAXv	export62 = R0, R0	; gl_Position
 0110b204:			0000: c00d2b00 00000000 0000000c 00000000 1002c400 10000003 00000000 1003c200
 0110b224:			0020: 20000002 19a80000 00392a88 0000000c 000f803e 00000000 c2000000
-t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (9 dwords)
+			opcode: CP_IM_LOAD_IMMEDIATE (2b) (9 dwords)
 			fragment shader, start=0000, size=0006
 					    0000 0000 c400            	ALLOC PARAM/PIXEL SIZE(0x0)
 					    1001 0002 2000            	EXEC_END ADDR(0x1) CNT(0x1)
 					01: 000f8000 00000000 02000000	   (S)ALU:	MAXv	export0 = C0, C0	; gl_FragColor
 0110b240:			0000: c0072b00 00000001 00000006 00000000 1001c400 20000002 000f8000 00000000
 0110b260:			0020: 02000000
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 }
 0110b264:			0000: c0012d00 00040181 00000006
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 128 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
 0110b270:			0000: c0012d00 00040180 10038002
-t0			write TC_CNTL_STATUS (0e00)
+			write TC_CNTL_STATUS (0e00)
 NEEDS WFI: TC_CNTL_STATUS (e00)
 				TC_CNTL_STATUS: { L2_INVALIDATE }
 0110b27c:			0000: 00000e00 00000001
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				RB_DEPTHCONTROL: { STENCIL_ENABLE | Z_ENABLE | Z_WRITE_ENABLE | EARLY_Z_ENABLE | ZFUNC = FUNC_ALWAYS | STENCILFUNC = FUNC_ALWAYS | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_REPLACE | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
 0110b284:			0000: c0012d00 00040200 0000877f
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				RB_COLORCONTROL: { ALPHA_FUNC = FUNC_ALWAYS | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
 0110b290:			0000: c0012d00 00040202 00000c27
-t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
+			opcode: CP_SET_CONSTANT (2d) (4 dwords)
 				PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
 				PA_SU_SC_MODE_CNTL: { POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | MSAA_ENABLE | PROVOKING_VTX_LAST }
 0110b29c:			0000: c0022d00 00040204 00000000 00088240
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 3 | MAX_SAMPLE_DIST = 0 }
 0110b2ac:			0000: c0012d00 00040301 00000003
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				PA_SC_AA_MASK: 0xffff
 0110b2b8:			0000: c0012d00 00040312 0000ffff
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 0110b2c4:			0000: c0012d00 00040104 0000000f
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
 0110b2d0:			0000: c0012d00 00040201 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				PA_SC_SCREEN_SCISSOR_BR: { X = 32 | Y = 128 }
 0110b2dc:			0000: c0012d00 0004000f 00800020
-t3			opcode: CP_SET_CONSTANT (2d) (5 dwords)
+			opcode: CP_SET_CONSTANT (2d) (5 dwords)
 				RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 2 }
 				RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0 }
 				RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTHX_24_8 | DEPTH_BASE = 65536 }
 0110b2e8:			0000: c0032d00 00040000 00008020 00000005 00010001
-t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
+			opcode: CP_SET_CONSTANT (2d) (6 dwords)
 0110b304:				0.501961 0.250980 0.125490 1.000000
 0110b2fc:			0000: c0042d00 00000480 3f008081 3e808081 3e008081 3f800000
-t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
+			opcode: CP_SET_CONSTANT (2d) (4 dwords)
 				PA_CL_VPORT_ZSCALE: 0.000000
 				PA_CL_VPORT_ZOFFSET: 1.000000
 0110b314:			0000: c0022d00 00040113 00000000 3f800000
-t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
+			opcode: CP_SET_CONSTANT (2d) (4 dwords)
 				RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0xff | 0xff000000 }
 				RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0xff | 0xff000000 }
 0110b324:			0000: c0022d00 0004010c ffff0000 ffff0000
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 3
 				:0,0,69,3
 0110b334:			0000: 0000057f 00000003
-t3			opcode: CP_DRAW_INDX (22) (3 dwords)
+			opcode: CP_DRAW_INDX (22) (3 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x30000 }
 			draw:          1
@@ -4022,57 +4022,57 @@ t3			opcode: CP_DRAW_INDX (22) (3 dwords)
  +	00000003			PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 3 | MAX_SAMPLE_DIST = 0 }
  +	0000ffff			PA_SC_AA_MASK: 0xffff
 0110b33c:			0000: c0012200 00000000 00030088
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 4
 				:0,0,69,4
 0110b348:			0000: 0000057f 00000004
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
 0110b350:			0000: c0012d00 00040301 00000000
-t3			opcode: CP_LOAD_CONSTANT_CONTEXT (2e) (4 dwords)
+			opcode: CP_LOAD_CONSTANT_CONTEXT (2e) (4 dwords)
 0110b35c:			0000: c0022e00 01009000 0004000f 00000001
-t3			opcode: CP_SET_CONSTANT (2d) (5 dwords)
+			opcode: CP_SET_CONSTANT (2d) (5 dwords)
 				RB_SURFACE_INFO: { SURFACE_PITCH = 128 | MSAA_SAMPLES = 0 }
 				RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 1 | BASE = 0 }
 				RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTHX_24_8 | DEPTH_BASE = 65536 }
 0110b36c:			0000: c0032d00 00040000 00000080 00000205 00010001
-t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
+			opcode: CP_SET_CONSTANT (2d) (6 dwords)
 			set shader const 0078
 0110b380:			0000: c0042d00 00010078 0112d483 00100000 0112d4c3 00100000
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				PA_SC_AA_MASK: 0xffff
 0110b398:			0000: c0012d00 00040312 0000ffff
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
 0110b3a4:			0000: c0012d00 00040200 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (5 dwords)
+			opcode: CP_SET_CONSTANT (2d) (5 dwords)
 				RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
 				RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
 				RB_ALPHA_REF: 0
 0110b3b0:			0000: c0032d00 0004010c 00000000 00000000 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
+			opcode: CP_SET_CONSTANT (2d) (4 dwords)
 				PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
 				PA_SU_SC_MODE_CNTL: { POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST }
 0110b3c4:			0000: c0022d00 00040204 00000000 00090240
-t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
+			opcode: CP_SET_CONSTANT (2d) (6 dwords)
 				PA_SU_POINT_SIZE: { HEIGHT = 0.500000 | WIDTH = 0.500000 }
 				PA_SU_POINT_MINMAX: { MIN = 0.500000 | MAX = 0.500000 }
 				PA_SU_LINE_CNTL: { WIDTH = 0.500000 }
 				PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER }
 0110b3d4:			0000: c0042d00 00040280 00080008 00080008 00000008 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (7 dwords)
+			opcode: CP_SET_CONSTANT (2d) (7 dwords)
 				PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH }
 				PA_CL_GB_VERT_CLIP_ADJ: 1.000000
 				PA_CL_GB_VERT_DISC_ADJ: 1.000000
 				PA_CL_GB_HORZ_CLIP_ADJ: 1.000000
 				PA_CL_GB_HORZ_DISC_ADJ: 1.000000
 0110b3ec:			0000: c0052d00 00040302 00000001 3f800000 3f800000 3f800000 3f800000
-t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
+			opcode: CP_SET_CONSTANT (2d) (4 dwords)
 				PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
 				PA_SC_WINDOW_SCISSOR_BR: { X = 256 | Y = 256 }
 0110b408:			0000: c0022d00 00040081 00000000 01000100
-t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
+			opcode: CP_SET_CONSTANT (2d) (8 dwords)
 				PA_CL_VPORT_XSCALE: 128.000000
 				PA_CL_VPORT_XOFFSET: 128.000000
 				PA_CL_VPORT_YSCALE: -128.000000
@@ -4080,11 +4080,11 @@ t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
 				PA_CL_VPORT_ZSCALE: 0.500000
 				PA_CL_VPORT_ZOFFSET: 0.500000
 0110b418:			0000: c0062d00 0004010f 43000000 43000000 c3000000 43000000 3f000000 3f000000
-t3			opcode: CP_SET_CONSTANT (2d) (10 dwords)
+			opcode: CP_SET_CONSTANT (2d) (10 dwords)
 0110b440:				128.000000 128.000000 0.500000 0.000000 128.000000 -128.000000 0.500000 0.000000
 0110b438:			0000: c0082d00 00000184 43000000 43000000 3f000000 00000000 43000000 c3000000
 0110b458:			0020: 3f000000 00000000
-t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords)
+			opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords)
 			vertex shader, start=0000, size=0015
 					    2003 0007 1000            	EXEC ADDR(0x3) CNT(0x2)
 					03: 19481000 00262688 00000010	   (S)FETCH:	VERTEX	R1.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(16) CONST(20, 0)
@@ -4099,7 +4099,7 @@ t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords)
 0110b460:			0000: c0162b00 00000000 00000015 00072003 00001000 c2000000 00021005 00001000
 0110b480:			0020: c4000000 00001006 00002000 00000000 19481000 00262688 00000010 13480000
 0110b4a0:			0040: 40252fc8 00000008 000f803e 00000000 c2010100 00038000 00000000 c2000000
-t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
+			opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
 			fragment shader, start=0000, size=000c
 					    1002 0003 1000            	EXEC ADDR(0x2) CNT(0x1)
 					02: 90000001 1ffff688 00000002	   (S)FETCH:	SAMPLE	R0.xyzw = R0.xyz CONST(0) LOCATION(CENTER)
@@ -4109,31 +4109,31 @@ t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
 					    0000 0000 0000            	NOP
 0110b4c0:			0000: c00d2b00 00000001 0000000c 00031002 00001000 c4000000 00021003 00002000
 0110b4e0:			0020: 00000000 90000001 1ffff688 00000002 000f8000 00000000 c2000000
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 }
 0110b4fc:			0000: c0012d00 00040181 00000106
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
 0110b508:			0000: c0012d00 00040180 10030002
-t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
+			opcode: CP_SET_CONSTANT (2d) (6 dwords)
 0110b51c:				0.000000 0.000000 0.000000 0.000000
 0110b514:			0000: c0042d00 00000080 00000000 00000000 00000000 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_ALWAYS | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
 0110b52c:			0000: c0012d00 00040202 00001c20
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
 0110b538:			0000: c0012d00 00040201 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 0110b544:			0000: c0012d00 00040104 0000000f
-t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
+			opcode: CP_SET_CONSTANT (2d) (6 dwords)
 				RB_BLEND_RED: 0
 				RB_BLEND_GREEN: 0
 				RB_BLEND_BLUE: 0
 				RB_BLEND_ALPHA: 0
 0110b550:			0000: c0042d00 00040105 00000000 00000000 00000000 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
+			opcode: CP_SET_CONSTANT (2d) (8 dwords)
 			set texture const 0000
 				clamp x/y/z: clamp-last-texel/clamp-last-texel/wrap
 				filter min/mag: point/point
@@ -4141,98 +4141,98 @@ t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
 				addr=01230000 (flags=820), size=64x128, pitch=16448, format=FMT_1_REVERSE
 				mipaddr=01240000 (flags=200)
 0110b568:			0000: c0062d00 00010000 80804800 01230820 000fe03f 00000d11 000001c0 01240200
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				VGT_INDX_OFFSET: 0
 0110b588:			0000: c0012d00 00040102 00000000
-t0			write TC_CNTL_STATUS (0e00)
+			write TC_CNTL_STATUS (0e00)
 NEEDS WFI: TC_CNTL_STATUS (e00)
 				TC_CNTL_STATUS: { L2_INVALIDATE }
 0110b594:			0000: 00000e00 00000001
-t3			opcode: CP_WAIT_REG_EQ (52) (5 dwords)
+			opcode: CP_WAIT_REG_EQ (52) (5 dwords)
 0110b59c:			0000: c0035200 000005d0 00000000 00001000 00000001
-t3			opcode: CP_DRAW_INDX_BIN (34) (7 dwords)
+			opcode: CP_DRAW_INDX_BIN (34) (7 dwords)
 0110b5b0:			0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 59
 				:0,0,69,59
 0110b5cc:			0000: 0000057f 0000003b
-t3			opcode: CP_DRAW_INDX_BIN (34) (7 dwords)
+			opcode: CP_DRAW_INDX_BIN (34) (7 dwords)
 0110b5d4:			0000: c0053400 00000000 0006c004 00000000 00000006 0112d4e0 0000000c
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 60
 				:0,0,69,60
 0110b5f0:			0000: 0000057f 0000003c
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 0110b5f8:			0000: c0002600 00000000
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0110b600:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0110b608:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0110b610:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0110b618:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0110b620:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0110b628:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0110b630:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0110b638:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0110b640:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0110b648:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0110b650:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0110b658:			0000: c0004600 00000006
 0110a2cc:		0000: c0013700 0110b000 00000198
-t2		nop
-t0		write CP_SCRATCH_REG6 (057e)
+		nop
+		write CP_SCRATCH_REG6 (057e)
 			CP_SCRATCH_REG6: 71
 			:0,0,71,60
 0110a2e4:		0000: 0000057e 00000047
-t3		opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
+		opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
 		ibaddr:0125e000
 		ibsize:00000064
-t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
+			opcode: CP_SET_CONSTANT (2d) (4 dwords)
 			set shader const 009c
 0125e000:			0000: c0022d00 0001009c 01009003 00000024
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
 0125e010:			0000: c0012d00 00040080 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				VGT_INDX_OFFSET: 0
 0125e01c:			0000: c0012d00 00040102 00000000
-t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
+			opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
 			vertex shader, start=0000, size=000c
 					    0000 0000 c400            	ALLOC PARAM/PIXEL SIZE(0x0)
 					    1002 0003 1000            	EXEC ADDR(0x2) CNT(0x1)
@@ -4242,58 +4242,58 @@ t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
 					03: 000f803e 00000000 c2000000	   (S)ALU:	MAXv	export62 = R0, R0	; gl_Position
 0125e028:			0000: c00d2b00 00000000 0000000c 00000000 1002c400 10000003 00000000 1003c200
 0125e048:			0020: 20000002 19a80000 00392a88 0000000c 000f803e 00000000 c2000000
-t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (9 dwords)
+			opcode: CP_IM_LOAD_IMMEDIATE (2b) (9 dwords)
 			fragment shader, start=0000, size=0006
 					    0000 0000 c400            	ALLOC PARAM/PIXEL SIZE(0x0)
 					    1001 0002 2000            	EXEC_END ADDR(0x1) CNT(0x1)
 					01: 000f8000 00000000 02000000	   (S)ALU:	MAXv	export0 = C0, C0	; gl_FragColor
 0125e064:			0000: c0072b00 00000001 00000006 00000000 1001c400 20000002 000f8000 00000000
 0125e084:			0020: 02000000
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 }
 0125e088:			0000: c0012d00 00040181 00000006
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 128 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
 0125e094:			0000: c0012d00 00040180 10038002
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				PA_SC_AA_MASK: 0xffff
 0125e0a0:			0000: c0012d00 00040312 0000ffff
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				RB_DEPTHCONTROL: { EARLY_Z_ENABLE | ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
 0125e0ac:			0000: c0012d00 00040200 00000008
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				PA_SU_SC_MODE_CNTL: { POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | PROVOKING_VTX_LAST }
 0125e0b8:			0000: c0012d00 00040205 00080240
-t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
+			opcode: CP_SET_CONSTANT (2d) (4 dwords)
 				PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
 				PA_SC_WINDOW_SCISSOR_BR: { X = 256 | Y = 256 }
 0125e0c4:			0000: c0022d00 00040081 00000000 01000100
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
 0125e0d4:			0000: c0012d00 00040204 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
+			opcode: CP_SET_CONSTANT (2d) (6 dwords)
 				PA_CL_VPORT_XSCALE: 64.000000
 				PA_CL_VPORT_XOFFSET: 64.000000
 				PA_CL_VPORT_YSCALE: 64.000000
 				PA_CL_VPORT_YOFFSET: 64.000000
 0125e0e0:			0000: c0042d00 0004010f 42800000 42800000 42800000 42800000
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				RB_MODECONTROL: { EDRAM_MODE = EDRAM_COPY }
 0125e0f8:			0000: c0012d00 00040208 00000006
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0x10000 }
 0125e104:			0000: c0012d00 00040001 00010005
-t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
+			opcode: CP_SET_CONSTANT (2d) (6 dwords)
 				RB_COPY_CONTROL: { COPY_SAMPLE_SELECT = SAMPLE_0 | CLEAR_MASK = 0 }
 				RB_COPY_DEST_BASE: 0x10ca000
 				RB_COPY_DEST_PITCH: 256
 				RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | LINEAR | FORMAT = COLORX_8_8_8_8 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 0125e110:			0000: c0042d00 00040318 00000000 010ca000 00000008 0003c058
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 63
 				:0,0,71,63
 0125e128:			0000: 0000057f 0000003f
-t3			opcode: CP_DRAW_INDX (22) (3 dwords)
+			opcode: CP_DRAW_INDX (22) (3 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x30000 }
 			draw:          0
@@ -4351,26 +4351,26 @@ t3			opcode: CP_DRAW_INDX (22) (3 dwords)
 !+	00000008			RB_COPY_DEST_PITCH: 256
 !+	0003c058			RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | LINEAR | FORMAT = COLORX_8_8_8_8 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 0125e130:			0000: c0012200 00000000 00030088
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 64
 				:0,0,71,64
 0125e13c:			0000: 0000057f 00000040
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0 }
 0125e144:			0000: c0012d00 00040001 00000005
-t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
+			opcode: CP_SET_CONSTANT (2d) (6 dwords)
 				RB_COPY_CONTROL: { COPY_SAMPLE_SELECT = SAMPLE_0 | CLEAR_MASK = 0 }
 				RB_COPY_DEST_BASE: 0x108a000
 				RB_COPY_DEST_PITCH: 256
 				RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_8_8_8_8 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 0125e150:			0000: c0042d00 00040318 00000000 0108a000 00000008 0003c050
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 65
 				:0,0,71,65
 0125e168:			0000: 0000057f 00000041
-t3			opcode: CP_DRAW_INDX (22) (3 dwords)
+			opcode: CP_DRAW_INDX (22) (3 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x30000 }
 			draw:          1
@@ -4386,339 +4386,339 @@ t3			opcode: CP_DRAW_INDX (22) (3 dwords)
  +	00000008			RB_COPY_DEST_PITCH: 256
 !+	0003c050			RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_8_8_8_8 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 0125e170:			0000: c0012200 00000000 00030088
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 66
 				:0,0,71,66
 0125e17c:			0000: 0000057f 00000042
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
 0125e184:			0000: c0012d00 00040208 00000004
 0110a2ec:		0000: c0013700 0125e000 00000064
-t2		nop
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		nop
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 1 | BASE = 0 }
 0110a304:		0000: c0012d00 00040001 00000205
-t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
+		opcode: CP_SET_CONSTANT (2d) (4 dwords)
 			PA_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 }
 			PA_SC_SCREEN_SCISSOR_BR: { X = 128 | Y = 128 }
 0110a310:		0000: c0022d00 0004000e 00000000 00800080
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 1 | BASE = 0 }
 0110a320:		0000: c0012d00 00040001 00000205
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_WINDOW_OFFSET: { X = -128 | Y = 0 }
 0110a32c:		0000: c0012d00 00040080 00007f80
-t3		opcode: CP_MEM_WRITE (3d) (3 dwords)
+		opcode: CP_MEM_WRITE (3d) (3 dwords)
 			{ ADDR_LO = 0x100903c }
 			{ ADDR_HI = 0x800080 }
 		gpuaddr:0100903c
 0110a340:			0.000000
 0110a338:		0000: c0013d00 0100903c 00800080
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_COPY_DEST_OFFSET: { X = 128 | Y = 0 }
 0110a344:		0000: c0012d00 0004031c 00000080
-t3		opcode: CP_SET_CONSTANT (2d) (6 dwords)
+		opcode: CP_SET_CONSTANT (2d) (6 dwords)
 0110a358:			128.000000 0.000000 0.000000 0.000000
 0110a350:		0000: c0042d00 00000580 43000000 00000000 00000000 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			VGT_CURRENT_BIN_ID_MIN: { COLUMN = 2 | ROW = 1 | GUARD_BAND_MASK = 0 }
 0110a368:		0000: c0012d00 00040207 0000000a
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			VGT_CURRENT_BIN_ID_MAX: { COLUMN = 2 | ROW = 1 | GUARD_BAND_MASK = 0 }
 0110a374:		0000: c0012d00 00040203 0000000a
-t3		opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords)
+		opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords)
 0110a380:		0000: c0004b00 0111d000
-t0		write CP_SCRATCH_REG6 (057e)
+		write CP_SCRATCH_REG6 (057e)
 NEEDS WFI: CP_SCRATCH_REG6 (57e)
 			CP_SCRATCH_REG6: 73
 			:0,0,73,66
 0110a388:		0000: 0000057e 00000049
-t3		opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
+		opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
 		ibaddr:0110b000
 		ibsize:00000198
 0110a390:		0000: c0013700 0110b000 00000198
-t2		nop
-t0		write CP_SCRATCH_REG6 (057e)
+		nop
+		write CP_SCRATCH_REG6 (057e)
 NEEDS WFI: CP_SCRATCH_REG6 (57e)
 			CP_SCRATCH_REG6: 75
 			:0,0,75,66
 0110a3a8:		0000: 0000057e 0000004b
-t3		opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
+		opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
 		ibaddr:0125e000
 		ibsize:00000064
 0110a3b0:		0000: c0013700 0125e000 00000064
-t2		nop
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		nop
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 1 | BASE = 0 }
 0110a3c8:		0000: c0012d00 00040001 00000205
-t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
+		opcode: CP_SET_CONSTANT (2d) (4 dwords)
 			PA_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 }
 			PA_SC_SCREEN_SCISSOR_BR: { X = 128 | Y = 128 }
 0110a3d4:		0000: c0022d00 0004000e 00000000 00800080
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 1 | BASE = 0 }
 0110a3e4:		0000: c0012d00 00040001 00000205
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_WINDOW_OFFSET: { X = 0 | Y = -128 }
 0110a3f0:		0000: c0012d00 00040080 7f800000
-t3		opcode: CP_MEM_WRITE (3d) (3 dwords)
+		opcode: CP_MEM_WRITE (3d) (3 dwords)
 			{ ADDR_LO = 0x100903c }
 			{ ADDR_HI = 0x800080 }
 		gpuaddr:0100903c
 0110a404:			0.000000
 0110a3fc:		0000: c0013d00 0100903c 00800080
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_COPY_DEST_OFFSET: { X = 0 | Y = 128 }
 0110a408:		0000: c0012d00 0004031c 00100000
-t3		opcode: CP_SET_CONSTANT (2d) (6 dwords)
+		opcode: CP_SET_CONSTANT (2d) (6 dwords)
 0110a41c:			0.000000 128.000000 0.000000 0.000000
 0110a414:		0000: c0042d00 00000580 00000000 43000000 00000000 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			VGT_CURRENT_BIN_ID_MIN: { COLUMN = 1 | ROW = 2 | GUARD_BAND_MASK = 0 }
 0110a42c:		0000: c0012d00 00040207 00000011
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			VGT_CURRENT_BIN_ID_MAX: { COLUMN = 1 | ROW = 2 | GUARD_BAND_MASK = 0 }
 0110a438:		0000: c0012d00 00040203 00000011
-t3		opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords)
+		opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords)
 0110a444:		0000: c0004b00 0111d000
-t0		write CP_SCRATCH_REG6 (057e)
+		write CP_SCRATCH_REG6 (057e)
 NEEDS WFI: CP_SCRATCH_REG6 (57e)
 			CP_SCRATCH_REG6: 77
 			:0,0,77,66
 0110a44c:		0000: 0000057e 0000004d
-t3		opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
+		opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
 		ibaddr:0110b000
 		ibsize:00000198
 0110a454:		0000: c0013700 0110b000 00000198
-t2		nop
-t0		write CP_SCRATCH_REG6 (057e)
+		nop
+		write CP_SCRATCH_REG6 (057e)
 NEEDS WFI: CP_SCRATCH_REG6 (57e)
 			CP_SCRATCH_REG6: 79
 			:0,0,79,66
 0110a46c:		0000: 0000057e 0000004f
-t3		opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
+		opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
 		ibaddr:0125e000
 		ibsize:00000064
 0110a474:		0000: c0013700 0125e000 00000064
-t2		nop
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		nop
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 1 | BASE = 0 }
 0110a48c:		0000: c0012d00 00040001 00000205
-t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
+		opcode: CP_SET_CONSTANT (2d) (4 dwords)
 			PA_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 }
 			PA_SC_SCREEN_SCISSOR_BR: { X = 128 | Y = 128 }
 0110a498:		0000: c0022d00 0004000e 00000000 00800080
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 1 | BASE = 0 }
 0110a4a8:		0000: c0012d00 00040001 00000205
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_WINDOW_OFFSET: { X = -128 | Y = -128 }
 0110a4b4:		0000: c0012d00 00040080 7f807f80
-t3		opcode: CP_MEM_WRITE (3d) (3 dwords)
+		opcode: CP_MEM_WRITE (3d) (3 dwords)
 			{ ADDR_LO = 0x100903c }
 			{ ADDR_HI = 0x800080 }
 		gpuaddr:0100903c
 0110a4c8:			0.000000
 0110a4c0:		0000: c0013d00 0100903c 00800080
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_COPY_DEST_OFFSET: { X = 128 | Y = 128 }
 0110a4cc:		0000: c0012d00 0004031c 00100080
-t3		opcode: CP_SET_CONSTANT (2d) (6 dwords)
+		opcode: CP_SET_CONSTANT (2d) (6 dwords)
 0110a4e0:			128.000000 128.000000 0.000000 0.000000
 0110a4d8:		0000: c0042d00 00000580 43000000 43000000 00000000 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			VGT_CURRENT_BIN_ID_MIN: { COLUMN = 2 | ROW = 2 | GUARD_BAND_MASK = 0 }
 0110a4f0:		0000: c0012d00 00040207 00000012
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			VGT_CURRENT_BIN_ID_MAX: { COLUMN = 2 | ROW = 2 | GUARD_BAND_MASK = 0 }
 0110a4fc:		0000: c0012d00 00040203 00000012
-t3		opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords)
+		opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords)
 0110a508:		0000: c0004b00 0111d000
-t0		write CP_SCRATCH_REG6 (057e)
+		write CP_SCRATCH_REG6 (057e)
 NEEDS WFI: CP_SCRATCH_REG6 (57e)
 			CP_SCRATCH_REG6: 81
 			:0,0,81,66
 0110a510:		0000: 0000057e 00000051
-t3		opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
+		opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
 		ibaddr:0110b000
 		ibsize:00000198
 0110a518:		0000: c0013700 0110b000 00000198
-t2		nop
-t0		write CP_SCRATCH_REG6 (057e)
+		nop
+		write CP_SCRATCH_REG6 (057e)
 NEEDS WFI: CP_SCRATCH_REG6 (57e)
 			CP_SCRATCH_REG6: 83
 			:0,0,83,66
 0110a530:		0000: 0000057e 00000053
-t3		opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
+		opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
 		ibaddr:0125e000
 		ibsize:00000064
 0110a538:		0000: c0013700 0125e000 00000064
-t2		nop
+		nop
 ############################################################
 vertices: 0
 cmd: deqp-gles2/185: fence=1260
 ############################################################
 cmdstream[10]: 124 dwords
-t0		write RB_BC_CONTROL (0f01)
+		write RB_BC_CONTROL (0f01)
 NEEDS WFI: RB_BC_CONTROL (f01)
 			RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 }
 0122f000:		0000: 00000f01 1c004046
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 }
 0122f008:		0000: c0012d00 00040293 00000020
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
 0122f014:		0000: c0012d00 00040316 00000002
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 }
 0122f020:		0000: c0012d00 00040317 00000002
-t0		write CP_PERFMON_CNTL (0444)
+		write CP_PERFMON_CNTL (0444)
 NEEDS WFI: CP_PERFMON_CNTL (444)
 			CP_PERFMON_CNTL: 0
 0122f02c:		0000: 00000444 00000000
-t0		write RBBM_PM_OVERRIDE1 (039c)
+		write RBBM_PM_OVERRIDE1 (039c)
 NEEDS WFI: RBBM_PM_OVERRIDE1 (39c)
 			RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
 NEEDS WFI: RBBM_PM_OVERRIDE2 (39d)
 			RBBM_PM_OVERRIDE2: 0xfff
 0122f034:		0000: 0001039c ffffffff 00000fff
-t0		write TP0_CHICKEN (0e1e)
+		write TP0_CHICKEN (0e1e)
 NEEDS WFI: TP0_CHICKEN (e1e)
 			TP0_CHICKEN: 0x2
 0122f040:		0000: 00000e1e 00000002
-t3		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
+		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
 0122f048:		0000: c0003b00 00007fff
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			SQ_VS_CONST: { BASE = 32 | SIZE = 256 }
 0122f050:		0000: c0012d00 00040307 00100020
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			SQ_PS_CONST: { BASE = 288 | SIZE = 224 }
 0122f05c:		0000: c0012d00 00040308 000e0120
-t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
+		opcode: CP_SET_CONSTANT (2d) (4 dwords)
 			VGT_MAX_VTX_INDX: 0xffffffff
 			VGT_MIN_VTX_INDX: 0
 0122f068:		0000: c0022d00 00040100 ffffffff 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			VGT_INDX_OFFSET: 0
 0122f078:		0000: c0012d00 00040102 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			SQ_CONTEXT_MISC: { SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 }
 0122f084:		0000: c0012d00 00040181 00000004
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 }
 0122f090:		0000: c0012d00 00040182 ffffffff
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
 0122f09c:		0000: c0012d00 00040301 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_LINE_CNTL: { BRES_CNTL = 0 }
 0122f0a8:		0000: c0012d00 00040300 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
 0122f0b4:		0000: c0012d00 00040080 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
 0122f0c0:		0000: c0012d00 00040208 00000004
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_SAMPLE_POS: 0x88888888
 0122f0cc:		0000: c0012d00 0004020a 88888888
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_COLOR_DEST_MASK: 0xffffffff
 0122f0d8:		0000: c0012d00 00040326 ffffffff
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 0122f0e4:		0000: c0012d00 0004031b 0003c000
-t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
+		opcode: CP_SET_CONSTANT (2d) (4 dwords)
 			SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 }
 			SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 }
 0122f0f0:		0000: c0022d00 00040183 00000000 00000000
-t3		opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords)
+		opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords)
 0122f100:		0000: c0004b00 00000000
-t3		opcode: CP_WAIT_REG_EQ (52) (5 dwords)
+		opcode: CP_WAIT_REG_EQ (52) (5 dwords)
 0122f108:		0000: c0035200 000005d0 00000000 5f601000 00000001
-t0		write SQ_INST_STORE_MANAGMENT (0d02)
+		write SQ_INST_STORE_MANAGMENT (0d02)
 NEEDS WFI: SQ_INST_STORE_MANAGMENT (d02)
 			SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 }
 0122f11c:		0000: 00000d02 00000180
-t3		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
+		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
 0122f124:		0000: c0003b00 00000300
-t3		opcode: CP_SET_SHADER_BASES (4a) (2 dwords)
+		opcode: CP_SET_SHADER_BASES (4a) (2 dwords)
 0122f12c:		0000: c0004a00 80000180
-t3		opcode: CP_SET_CONSTANT (2d) (14 dwords)
+		opcode: CP_SET_CONSTANT (2d) (14 dwords)
 0122f13c:			0.000000 0.000000 0.000000 0.000000 20000.000000 1.000000 0.500000 0.000000
 0122f15c:			2.000000 0.750000 0.375000 0.250000
 0122f134:		0000: c00c2d00 00000000 00000000 00000000 00000000 00000000 469c4000 3f800000
 0122f154:		0020: 3f000000 00000000 40000000 3f400000 3ec00000 3e800000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 0122f16c:		0000: c0012d00 00040104 0000000f
-t3		opcode: CP_SET_CONSTANT (2d) (6 dwords)
+		opcode: CP_SET_CONSTANT (2d) (6 dwords)
 			RB_BLEND_RED: 0
 			RB_BLEND_GREEN: 0
 			RB_BLEND_BLUE: 0
 			RB_BLEND_ALPHA: 0xff
 0122f178:		0000: c0042d00 00040105 00000000 00000000 00000000 000000ff
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT }
 0122f190:		0000: c0012d00 00040206 0000043f
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_SURFACE_INFO: { SURFACE_PITCH = 64 | MSAA_SAMPLES = 0 }
 0122f19c:		0000: c0012d00 00040000 00000040
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | LINEAR | ENDIAN = 0 | SWAP = 1 | BASE = 0x1256000 }
 0122f1a8:		0000: c0012d00 00040001 01256245
-t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
+		opcode: CP_SET_CONSTANT (2d) (4 dwords)
 			PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 }
 			PA_SC_SCREEN_SCISSOR_BR: { X = 64 | Y = 128 }
 0122f1b4:		0000: c0022d00 0004000e 80000000 00800040
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
 0122f1c4:		0000: c0012d00 00040080 00000000
-t0		write CP_SCRATCH_REG6 (057e)
+		write CP_SCRATCH_REG6 (057e)
 NEEDS WFI: CP_SCRATCH_REG6 (57e)
 			CP_SCRATCH_REG6: 89
 			:0,0,89,66
 0122f1d0:		0000: 0000057e 00000059
-t3		opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
+		opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
 		ibaddr:0122e000
 		ibsize:000000b6
-t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
+			opcode: CP_SET_CONSTANT (2d) (6 dwords)
 			set shader const 0078
 0122e000:			0000: c0042d00 00010078 0112d4ef 00100000 0112d4ef 00100000
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				PA_SC_AA_MASK: 0xffff
 0122e018:			0000: c0012d00 00040312 0000ffff
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
 0122e024:			0000: c0012d00 00040200 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (5 dwords)
+			opcode: CP_SET_CONSTANT (2d) (5 dwords)
 				RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
 				RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
 				RB_ALPHA_REF: 0
 0122e030:			0000: c0032d00 0004010c 00000000 00000000 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
+			opcode: CP_SET_CONSTANT (2d) (4 dwords)
 				PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
 				PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST }
 0122e044:			0000: c0022d00 00040204 00000000 00090244
-t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
+			opcode: CP_SET_CONSTANT (2d) (6 dwords)
 				PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 }
 				PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 }
 				PA_SU_LINE_CNTL: { WIDTH = 0.000000 }
 				PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER }
 0122e054:			0000: c0042d00 00040280 00000000 00000000 00000000 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (7 dwords)
+			opcode: CP_SET_CONSTANT (2d) (7 dwords)
 				PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH }
 				PA_CL_GB_VERT_CLIP_ADJ: 1.000000
 				PA_CL_GB_VERT_DISC_ADJ: 1.000000
 				PA_CL_GB_HORZ_CLIP_ADJ: 1.000000
 				PA_CL_GB_HORZ_DISC_ADJ: 1.000000
 0122e06c:			0000: c0052d00 00040302 00000001 3f800000 3f800000 3f800000 3f800000
-t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
+			opcode: CP_SET_CONSTANT (2d) (4 dwords)
 				PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
 				PA_SC_WINDOW_SCISSOR_BR: { X = 64 | Y = 128 }
 0122e088:			0000: c0022d00 00040081 00000000 00800040
-t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
+			opcode: CP_SET_CONSTANT (2d) (8 dwords)
 				PA_CL_VPORT_XSCALE: 32.000000
 				PA_CL_VPORT_XOFFSET: 32.000000
 				PA_CL_VPORT_YSCALE: 64.000000
@@ -4726,11 +4726,11 @@ t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
 				PA_CL_VPORT_ZSCALE: 0.000000
 				PA_CL_VPORT_ZOFFSET: 0.000000
 0122e098:			0000: c0062d00 0004010f 42000000 42000000 42800000 42800000 00000000 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (10 dwords)
+			opcode: CP_SET_CONSTANT (2d) (10 dwords)
 0122e0c0:				32.000000 64.000000 0.000000 0.000000 32.000000 64.000000 0.000000 0.000000
 0122e0b8:			0000: c0082d00 00000184 42000000 42800000 00000000 00000000 42000000 42800000
 *
-t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords)
+			opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords)
 			vertex shader, start=0000, size=0015
 					    2003 0007 1000            	EXEC ADDR(0x3) CNT(0x2)
 					03: 19481000 00262688 00000020	   (S)FETCH:	VERTEX	R1.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) CONST(20, 0)
@@ -4745,7 +4745,7 @@ t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords)
 0122e0e0:			0000: c0162b00 00000000 00000015 00072003 00001000 c2000000 00021005 00001000
 0122e100:			0020: c4000000 00001006 00002000 00000000 19481000 00262688 00000020 13480000
 0122e120:			0040: 40262688 00001020 000f803e 00000000 c2010100 000f8000 00000000 c2000000
-t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
+			opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
 			fragment shader, start=0000, size=000c
 					    1002 0003 1000            	EXEC ADDR(0x2) CNT(0x1)
 					02: 90000001 1ffff688 00000002	   (S)FETCH:	SAMPLE	R0.xyzw = R0.xyz CONST(0) LOCATION(CENTER)
@@ -4755,31 +4755,31 @@ t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
 					    0000 0000 0000            	NOP
 0122e140:			0000: c00d2b00 00000001 0000000c 00031002 00001000 c4000000 00021003 00002000
 0122e160:			0020: 00000000 90000001 1ffff688 00000002 000f8000 00000000 c2000000
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 }
 0122e17c:			0000: c0012d00 00040181 00000106
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
 0122e188:			0000: c0012d00 00040180 10030002
-t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
+			opcode: CP_SET_CONSTANT (2d) (6 dwords)
 0122e19c:				0.000000 0.000000 0.000000 0.000000
 0122e194:			0000: c0042d00 00000080 00000000 00000000 00000000 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
 0122e1ac:			0000: c0012d00 00040202 00000c20
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
 0122e1b8:			0000: c0012d00 00040201 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 0122e1c4:			0000: c0012d00 00040104 0000000f
-t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
+			opcode: CP_SET_CONSTANT (2d) (6 dwords)
 				RB_BLEND_RED: 0
 				RB_BLEND_GREEN: 0
 				RB_BLEND_BLUE: 0
 				RB_BLEND_ALPHA: 0
 0122e1d0:			0000: c0042d00 00040105 00000000 00000000 00000000 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
+			opcode: CP_SET_CONSTANT (2d) (8 dwords)
 			set texture const 0000
 				clamp x/y/z: clamp-last-texel/clamp-last-texel/clamp-last-texel
 				filter min/mag: point/point
@@ -4787,25 +4787,25 @@ t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
 				addr=0108a000 (flags=806), size=256x256, pitch=16640, format=FMT_8_8_8_8
 				mipaddr=00000000 (flags=200)
 0122e1e8:			0000: c0062d00 00010000 82024800 0108a806 001fe0ff 00000c14 00000000 00000200
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				VGT_INDX_OFFSET: 0
 0122e208:			0000: c0012d00 00040102 00000000
-t0			write TC_CNTL_STATUS (0e00)
+			write TC_CNTL_STATUS (0e00)
 NEEDS WFI: TC_CNTL_STATUS (e00)
 				TC_CNTL_STATUS: { L2_INVALIDATE }
 0122e214:			0000: 00000e00 00000001
-t3			opcode: CP_WAIT_REG_EQ (52) (5 dwords)
+			opcode: CP_WAIT_REG_EQ (52) (5 dwords)
 0122e21c:			0000: c0035200 000005d0 00000000 00001000 00000001
-t3			opcode: CP_DRAW_INDX_BIN (34) (7 dwords)
+			opcode: CP_DRAW_INDX_BIN (34) (7 dwords)
 0122e230:			0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 85
 				:0,0,89,85
 0122e24c:			0000: 0000057f 00000055
-t3			opcode: CP_NOP (10) (2 dwords)
+			opcode: CP_NOP (10) (2 dwords)
 0122e254:			0000: c0001000 00000000
-t3			opcode: CP_DRAW_INDX (22) (3 dwords)
+			opcode: CP_DRAW_INDX (22) (3 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRIFAN | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x40000 }
 			draw:          0
@@ -4884,220 +4884,220 @@ t3			opcode: CP_DRAW_INDX (22) (3 dwords)
 !+	00100080			RB_COPY_DEST_OFFSET: { X = 128 | Y = 128 }
  +	ffffffff			RB_COLOR_DEST_MASK: 0xffffffff
 0122e25c:			0000: c0012200 00000000 00040085
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 86
 				:0,0,89,86
 0122e268:			0000: 0000057f 00000056
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 0122e270:			0000: c0002600 00000000
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e278:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e280:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e288:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e290:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e298:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2a0:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2a8:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2b0:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2b8:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2c0:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2c8:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2d0:			0000: c0004600 00000006
 0122f1d8:		0000: c0013700 0122e000 000000b6
-t2		nop
+		nop
 ############################################################
 vertices: 0
 cmd: deqp-gles2/185: fence=1261
 ############################################################
 cmdstream[11]: 124 dwords
-t0		write RB_BC_CONTROL (0f01)
+		write RB_BC_CONTROL (0f01)
 			RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 }
 0110c000:		0000: 00000f01 1c004046
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 }
 0110c008:		0000: c0012d00 00040293 00000020
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
 0110c014:		0000: c0012d00 00040316 00000002
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 }
 0110c020:		0000: c0012d00 00040317 00000002
-t0		write CP_PERFMON_CNTL (0444)
+		write CP_PERFMON_CNTL (0444)
 			CP_PERFMON_CNTL: 0
 0110c02c:		0000: 00000444 00000000
-t0		write RBBM_PM_OVERRIDE1 (039c)
+		write RBBM_PM_OVERRIDE1 (039c)
 			RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
 			RBBM_PM_OVERRIDE2: 0xfff
 0110c034:		0000: 0001039c ffffffff 00000fff
-t0		write TP0_CHICKEN (0e1e)
+		write TP0_CHICKEN (0e1e)
 			TP0_CHICKEN: 0x2
 0110c040:		0000: 00000e1e 00000002
-t3		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
+		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
 0110c048:		0000: c0003b00 00007fff
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			SQ_VS_CONST: { BASE = 32 | SIZE = 256 }
 0110c050:		0000: c0012d00 00040307 00100020
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			SQ_PS_CONST: { BASE = 288 | SIZE = 224 }
 0110c05c:		0000: c0012d00 00040308 000e0120
-t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
+		opcode: CP_SET_CONSTANT (2d) (4 dwords)
 			VGT_MAX_VTX_INDX: 0xffffffff
 			VGT_MIN_VTX_INDX: 0
 0110c068:		0000: c0022d00 00040100 ffffffff 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			VGT_INDX_OFFSET: 0
 0110c078:		0000: c0012d00 00040102 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			SQ_CONTEXT_MISC: { SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 }
 0110c084:		0000: c0012d00 00040181 00000004
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 }
 0110c090:		0000: c0012d00 00040182 ffffffff
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
 0110c09c:		0000: c0012d00 00040301 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_LINE_CNTL: { BRES_CNTL = 0 }
 0110c0a8:		0000: c0012d00 00040300 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
 0110c0b4:		0000: c0012d00 00040080 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
 0110c0c0:		0000: c0012d00 00040208 00000004
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_SAMPLE_POS: 0x88888888
 0110c0cc:		0000: c0012d00 0004020a 88888888
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_COLOR_DEST_MASK: 0xffffffff
 0110c0d8:		0000: c0012d00 00040326 ffffffff
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 0110c0e4:		0000: c0012d00 0004031b 0003c000
-t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
+		opcode: CP_SET_CONSTANT (2d) (4 dwords)
 			SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 }
 			SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 }
 0110c0f0:		0000: c0022d00 00040183 00000000 00000000
-t3		opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords)
+		opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords)
 0110c100:		0000: c0004b00 00000000
-t3		opcode: CP_WAIT_REG_EQ (52) (5 dwords)
+		opcode: CP_WAIT_REG_EQ (52) (5 dwords)
 0110c108:		0000: c0035200 000005d0 00000000 5f601000 00000001
-t0		write SQ_INST_STORE_MANAGMENT (0d02)
+		write SQ_INST_STORE_MANAGMENT (0d02)
 			SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 }
 0110c11c:		0000: 00000d02 00000180
-t3		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
+		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
 0110c124:		0000: c0003b00 00000300
-t3		opcode: CP_SET_SHADER_BASES (4a) (2 dwords)
+		opcode: CP_SET_SHADER_BASES (4a) (2 dwords)
 0110c12c:		0000: c0004a00 80000180
-t3		opcode: CP_SET_CONSTANT (2d) (14 dwords)
+		opcode: CP_SET_CONSTANT (2d) (14 dwords)
 0110c13c:			0.000000 0.000000 0.000000 0.000000 20000.000000 1.000000 0.500000 0.000000
 0110c15c:			2.000000 0.750000 0.375000 0.250000
 0110c134:		0000: c00c2d00 00000000 00000000 00000000 00000000 00000000 469c4000 3f800000
 0110c154:		0020: 3f000000 00000000 40000000 3f400000 3ec00000 3e800000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 0110c16c:		0000: c0012d00 00040104 0000000f
-t3		opcode: CP_SET_CONSTANT (2d) (6 dwords)
+		opcode: CP_SET_CONSTANT (2d) (6 dwords)
 			RB_BLEND_RED: 0
 			RB_BLEND_GREEN: 0
 			RB_BLEND_BLUE: 0
 			RB_BLEND_ALPHA: 0xff
 0110c178:		0000: c0042d00 00040105 00000000 00000000 00000000 000000ff
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT }
 0110c190:		0000: c0012d00 00040206 0000043f
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_SURFACE_INFO: { SURFACE_PITCH = 256 | MSAA_SAMPLES = 0 }
 0110c19c:		0000: c0012d00 00040000 00000100
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 1 | BASE = 0x108a000 }
 0110c1a8:		0000: c0012d00 00040001 0108a205
-t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
+		opcode: CP_SET_CONSTANT (2d) (4 dwords)
 			PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 }
 			PA_SC_SCREEN_SCISSOR_BR: { X = 256 | Y = 256 }
 0110c1b4:		0000: c0022d00 0004000e 80000000 01000100
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
 0110c1c4:		0000: c0012d00 00040080 00000000
-t0		write CP_SCRATCH_REG6 (057e)
+		write CP_SCRATCH_REG6 (057e)
 			CP_SCRATCH_REG6: 95
 			:0,0,95,86
 0110c1d0:		0000: 0000057e 0000005f
-t3		opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
+		opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
 		ibaddr:0110b000
 		ibsize:000000b8
-t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
+			opcode: CP_SET_CONSTANT (2d) (6 dwords)
 			set shader const 0078
 0110b000:			0000: c0042d00 00010078 0112d56f 00100000 0112d5af 00100000
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				PA_SC_AA_MASK: 0xffff
 0110b018:			0000: c0012d00 00040312 0000ffff
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
 0110b024:			0000: c0012d00 00040200 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (5 dwords)
+			opcode: CP_SET_CONSTANT (2d) (5 dwords)
 				RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
 				RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
 				RB_ALPHA_REF: 0
 0110b030:			0000: c0032d00 0004010c 00000000 00000000 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
+			opcode: CP_SET_CONSTANT (2d) (4 dwords)
 				PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
 				PA_SU_SC_MODE_CNTL: { POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST }
 0110b044:			0000: c0022d00 00040204 00000000 00090240
-t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
+			opcode: CP_SET_CONSTANT (2d) (6 dwords)
 				PA_SU_POINT_SIZE: { HEIGHT = 0.500000 | WIDTH = 0.500000 }
 				PA_SU_POINT_MINMAX: { MIN = 0.500000 | MAX = 0.500000 }
 				PA_SU_LINE_CNTL: { WIDTH = 0.500000 }
 				PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER }
 0110b054:			0000: c0042d00 00040280 00080008 00080008 00000008 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (7 dwords)
+			opcode: CP_SET_CONSTANT (2d) (7 dwords)
 				PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH }
 				PA_CL_GB_VERT_CLIP_ADJ: 1.000000
 				PA_CL_GB_VERT_DISC_ADJ: 1.000000
 				PA_CL_GB_HORZ_CLIP_ADJ: 1.000000
 				PA_CL_GB_HORZ_DISC_ADJ: 1.000000
 0110b06c:			0000: c0052d00 00040302 00000001 3f800000 3f800000 3f800000 3f800000
-t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
+			opcode: CP_SET_CONSTANT (2d) (4 dwords)
 				PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
 				PA_SC_WINDOW_SCISSOR_BR: { X = 256 | Y = 256 }
 0110b088:			0000: c0022d00 00040081 00000000 01000100
-t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
+			opcode: CP_SET_CONSTANT (2d) (8 dwords)
 				PA_CL_VPORT_XSCALE: 128.000000
 				PA_CL_VPORT_XOFFSET: 128.000000
 				PA_CL_VPORT_YSCALE: -128.000000
@@ -5105,11 +5105,11 @@ t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
 				PA_CL_VPORT_ZSCALE: 0.500000
 				PA_CL_VPORT_ZOFFSET: 0.500000
 0110b098:			0000: c0062d00 0004010f 43000000 43000000 c3000000 43000000 3f000000 3f000000
-t3			opcode: CP_SET_CONSTANT (2d) (10 dwords)
+			opcode: CP_SET_CONSTANT (2d) (10 dwords)
 0110b0c0:				128.000000 128.000000 0.500000 0.000000 128.000000 -128.000000 0.500000 0.000000
 0110b0b8:			0000: c0082d00 00000184 43000000 43000000 3f000000 00000000 43000000 c3000000
 0110b0d8:			0020: 3f000000 00000000
-t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords)
+			opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords)
 			vertex shader, start=0000, size=0015
 					    2003 0007 1000            	EXEC ADDR(0x3) CNT(0x2)
 					03: 19481000 00262688 00000010	   (S)FETCH:	VERTEX	R1.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(16) CONST(20, 0)
@@ -5124,7 +5124,7 @@ t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords)
 0110b0e0:			0000: c0162b00 00000000 00000015 00072003 00001000 c2000000 00021005 00001000
 0110b100:			0020: c4000000 00001006 00002000 00000000 19481000 00262688 00000010 13480000
 0110b120:			0040: 40252fc8 00000008 000f803e 00000000 c2010100 00038000 00000000 c2000000
-t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
+			opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
 			fragment shader, start=0000, size=000c
 					    1002 0003 1000            	EXEC ADDR(0x2) CNT(0x1)
 					02: 90000001 1ffff688 00000002	   (S)FETCH:	SAMPLE	R0.xyzw = R0.xyz CONST(0) LOCATION(CENTER)
@@ -5134,31 +5134,31 @@ t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
 					    0000 0000 0000            	NOP
 0110b140:			0000: c00d2b00 00000001 0000000c 00031002 00001000 c4000000 00021003 00002000
 0110b160:			0020: 00000000 90000001 1ffff688 00000002 000f8000 00000000 c2000000
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 }
 0110b17c:			0000: c0012d00 00040181 00000106
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
 0110b188:			0000: c0012d00 00040180 10030002
-t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
+			opcode: CP_SET_CONSTANT (2d) (6 dwords)
 0110b19c:				0.000000 0.000000 0.000000 0.000000
 0110b194:			0000: c0042d00 00000080 00000000 00000000 00000000 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_ALWAYS | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
 0110b1ac:			0000: c0012d00 00040202 00001c20
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
 0110b1b8:			0000: c0012d00 00040201 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 0110b1c4:			0000: c0012d00 00040104 0000000f
-t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
+			opcode: CP_SET_CONSTANT (2d) (6 dwords)
 				RB_BLEND_RED: 0
 				RB_BLEND_GREEN: 0
 				RB_BLEND_BLUE: 0
 				RB_BLEND_ALPHA: 0
 0110b1d0:			0000: c0042d00 00040105 00000000 00000000 00000000 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
+			opcode: CP_SET_CONSTANT (2d) (8 dwords)
 			set texture const 0000
 				clamp x/y/z: clamp-last-texel/clamp-last-texel/wrap
 				filter min/mag: point/point
@@ -5166,23 +5166,23 @@ t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
 				addr=01230000 (flags=820), size=64x128, pitch=16448, format=FMT_1_REVERSE
 				mipaddr=01240000 (flags=200)
 0110b1e8:			0000: c0062d00 00010000 80804800 01230820 000fe03f 00000d11 000001c0 01240200
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				VGT_INDX_OFFSET: 0
 0110b208:			0000: c0012d00 00040102 00000000
-t0			write TC_CNTL_STATUS (0e00)
+			write TC_CNTL_STATUS (0e00)
 				TC_CNTL_STATUS: { L2_INVALIDATE }
 0110b214:			0000: 00000e00 00000001
-t3			opcode: CP_WAIT_REG_EQ (52) (5 dwords)
+			opcode: CP_WAIT_REG_EQ (52) (5 dwords)
 0110b21c:			0000: c0035200 000005d0 00000000 00001000 00000001
-t3			opcode: CP_DRAW_INDX_BIN (34) (7 dwords)
+			opcode: CP_DRAW_INDX_BIN (34) (7 dwords)
 0110b230:			0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 91
 				:0,0,95,91
 0110b24c:			0000: 0000057f 0000005b
-t3			opcode: CP_NOP (10) (2 dwords)
+			opcode: CP_NOP (10) (2 dwords)
 0110b254:			0000: c0001000 00000000
-t3			opcode: CP_DRAW_INDX (22) (5 dwords)
+			opcode: CP_DRAW_INDX (22) (5 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x60000 }
 				{ NUM_INDICES = 18011596 }
@@ -5260,220 +5260,220 @@ t3			opcode: CP_DRAW_INDX (22) (5 dwords)
  +	0003c000			RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
  +	ffffffff			RB_COLOR_DEST_MASK: 0xffffffff
 0110b25c:			0000: c0032200 00000000 00060004 0112d5cc 0000000c
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 92
 				:0,0,95,92
 0110b270:			0000: 0000057f 0000005c
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 0110b278:			0000: c0002600 00000000
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0110b280:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0110b288:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0110b290:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0110b298:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0110b2a0:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0110b2a8:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0110b2b0:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0110b2b8:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0110b2c0:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0110b2c8:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0110b2d0:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0110b2d8:			0000: c0004600 00000006
 0110c1d8:		0000: c0013700 0110b000 000000b8
-t2		nop
+		nop
 ############################################################
 vertices: 0
 cmd: deqp-gles2/185: fence=1262
 ############################################################
 cmdstream[12]: 124 dwords
-t0		write RB_BC_CONTROL (0f01)
+		write RB_BC_CONTROL (0f01)
 			RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 }
 0122d000:		0000: 00000f01 1c004046
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 }
 0122d008:		0000: c0012d00 00040293 00000020
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
 0122d014:		0000: c0012d00 00040316 00000002
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 }
 0122d020:		0000: c0012d00 00040317 00000002
-t0		write CP_PERFMON_CNTL (0444)
+		write CP_PERFMON_CNTL (0444)
 			CP_PERFMON_CNTL: 0
 0122d02c:		0000: 00000444 00000000
-t0		write RBBM_PM_OVERRIDE1 (039c)
+		write RBBM_PM_OVERRIDE1 (039c)
 			RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
 			RBBM_PM_OVERRIDE2: 0xfff
 0122d034:		0000: 0001039c ffffffff 00000fff
-t0		write TP0_CHICKEN (0e1e)
+		write TP0_CHICKEN (0e1e)
 			TP0_CHICKEN: 0x2
 0122d040:		0000: 00000e1e 00000002
-t3		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
+		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
 0122d048:		0000: c0003b00 00007fff
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			SQ_VS_CONST: { BASE = 32 | SIZE = 256 }
 0122d050:		0000: c0012d00 00040307 00100020
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			SQ_PS_CONST: { BASE = 288 | SIZE = 224 }
 0122d05c:		0000: c0012d00 00040308 000e0120
-t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
+		opcode: CP_SET_CONSTANT (2d) (4 dwords)
 			VGT_MAX_VTX_INDX: 0xffffffff
 			VGT_MIN_VTX_INDX: 0
 0122d068:		0000: c0022d00 00040100 ffffffff 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			VGT_INDX_OFFSET: 0
 0122d078:		0000: c0012d00 00040102 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			SQ_CONTEXT_MISC: { SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 }
 0122d084:		0000: c0012d00 00040181 00000004
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 }
 0122d090:		0000: c0012d00 00040182 ffffffff
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
 0122d09c:		0000: c0012d00 00040301 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_LINE_CNTL: { BRES_CNTL = 0 }
 0122d0a8:		0000: c0012d00 00040300 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
 0122d0b4:		0000: c0012d00 00040080 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
 0122d0c0:		0000: c0012d00 00040208 00000004
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_SAMPLE_POS: 0x88888888
 0122d0cc:		0000: c0012d00 0004020a 88888888
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_COLOR_DEST_MASK: 0xffffffff
 0122d0d8:		0000: c0012d00 00040326 ffffffff
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 0122d0e4:		0000: c0012d00 0004031b 0003c000
-t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
+		opcode: CP_SET_CONSTANT (2d) (4 dwords)
 			SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 }
 			SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 }
 0122d0f0:		0000: c0022d00 00040183 00000000 00000000
-t3		opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords)
+		opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords)
 0122d100:		0000: c0004b00 00000000
-t3		opcode: CP_WAIT_REG_EQ (52) (5 dwords)
+		opcode: CP_WAIT_REG_EQ (52) (5 dwords)
 0122d108:		0000: c0035200 000005d0 00000000 5f601000 00000001
-t0		write SQ_INST_STORE_MANAGMENT (0d02)
+		write SQ_INST_STORE_MANAGMENT (0d02)
 			SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 }
 0122d11c:		0000: 00000d02 00000180
-t3		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
+		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
 0122d124:		0000: c0003b00 00000300
-t3		opcode: CP_SET_SHADER_BASES (4a) (2 dwords)
+		opcode: CP_SET_SHADER_BASES (4a) (2 dwords)
 0122d12c:		0000: c0004a00 80000180
-t3		opcode: CP_SET_CONSTANT (2d) (14 dwords)
+		opcode: CP_SET_CONSTANT (2d) (14 dwords)
 0122d13c:			0.000000 0.000000 0.000000 0.000000 20000.000000 1.000000 0.500000 0.000000
 0122d15c:			2.000000 0.750000 0.375000 0.250000
 0122d134:		0000: c00c2d00 00000000 00000000 00000000 00000000 00000000 469c4000 3f800000
 0122d154:		0020: 3f000000 00000000 40000000 3f400000 3ec00000 3e800000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 0122d16c:		0000: c0012d00 00040104 0000000f
-t3		opcode: CP_SET_CONSTANT (2d) (6 dwords)
+		opcode: CP_SET_CONSTANT (2d) (6 dwords)
 			RB_BLEND_RED: 0
 			RB_BLEND_GREEN: 0
 			RB_BLEND_BLUE: 0
 			RB_BLEND_ALPHA: 0xff
 0122d178:		0000: c0042d00 00040105 00000000 00000000 00000000 000000ff
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT }
 0122d190:		0000: c0012d00 00040206 0000043f
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 }
 0122d19c:		0000: c0012d00 00040000 00000020
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | LINEAR | ENDIAN = 0 | SWAP = 1 | BASE = 0x1254000 }
 0122d1a8:		0000: c0012d00 00040001 01254245
-t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
+		opcode: CP_SET_CONSTANT (2d) (4 dwords)
 			PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 }
 			PA_SC_SCREEN_SCISSOR_BR: { X = 32 | Y = 64 }
 0122d1b4:		0000: c0022d00 0004000e 80000000 00400020
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
 0122d1c4:		0000: c0012d00 00040080 00000000
-t0		write CP_SCRATCH_REG6 (057e)
+		write CP_SCRATCH_REG6 (057e)
 			CP_SCRATCH_REG6: 101
 			:0,0,101,92
 0122d1d0:		0000: 0000057e 00000065
-t3		opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
+		opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
 		ibaddr:0122e000
 		ibsize:000000b6
-t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
+			opcode: CP_SET_CONSTANT (2d) (6 dwords)
 			set shader const 0078
 0122e000:			0000: c0042d00 00010078 0112d5db 00100000 0112d5db 00100000
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				PA_SC_AA_MASK: 0xffff
 0122e018:			0000: c0012d00 00040312 0000ffff
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
 0122e024:			0000: c0012d00 00040200 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (5 dwords)
+			opcode: CP_SET_CONSTANT (2d) (5 dwords)
 				RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
 				RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
 				RB_ALPHA_REF: 0
 0122e030:			0000: c0032d00 0004010c 00000000 00000000 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
+			opcode: CP_SET_CONSTANT (2d) (4 dwords)
 				PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
 				PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST }
 0122e044:			0000: c0022d00 00040204 00000000 00090244
-t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
+			opcode: CP_SET_CONSTANT (2d) (6 dwords)
 				PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 }
 				PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 }
 				PA_SU_LINE_CNTL: { WIDTH = 0.000000 }
 				PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER }
 0122e054:			0000: c0042d00 00040280 00000000 00000000 00000000 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (7 dwords)
+			opcode: CP_SET_CONSTANT (2d) (7 dwords)
 				PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH }
 				PA_CL_GB_VERT_CLIP_ADJ: 1.000000
 				PA_CL_GB_VERT_DISC_ADJ: 1.000000
 				PA_CL_GB_HORZ_CLIP_ADJ: 1.000000
 				PA_CL_GB_HORZ_DISC_ADJ: 1.000000
 0122e06c:			0000: c0052d00 00040302 00000001 3f800000 3f800000 3f800000 3f800000
-t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
+			opcode: CP_SET_CONSTANT (2d) (4 dwords)
 				PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
 				PA_SC_WINDOW_SCISSOR_BR: { X = 32 | Y = 64 }
 0122e088:			0000: c0022d00 00040081 00000000 00400020
-t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
+			opcode: CP_SET_CONSTANT (2d) (8 dwords)
 				PA_CL_VPORT_XSCALE: 16.000000
 				PA_CL_VPORT_XOFFSET: 16.000000
 				PA_CL_VPORT_YSCALE: 32.000000
@@ -5481,11 +5481,11 @@ t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
 				PA_CL_VPORT_ZSCALE: 0.000000
 				PA_CL_VPORT_ZOFFSET: 0.000000
 0122e098:			0000: c0062d00 0004010f 41800000 41800000 42000000 42000000 00000000 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (10 dwords)
+			opcode: CP_SET_CONSTANT (2d) (10 dwords)
 0122e0c0:				16.000000 32.000000 0.000000 0.000000 16.000000 32.000000 0.000000 0.000000
 0122e0b8:			0000: c0082d00 00000184 41800000 42000000 00000000 00000000 41800000 42000000
 *
-t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords)
+			opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords)
 			vertex shader, start=0000, size=0015
 					    2003 0007 1000            	EXEC ADDR(0x3) CNT(0x2)
 					03: 19481000 00262688 00000020	   (S)FETCH:	VERTEX	R1.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) CONST(20, 0)
@@ -5500,7 +5500,7 @@ t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords)
 0122e0e0:			0000: c0162b00 00000000 00000015 00072003 00001000 c2000000 00021005 00001000
 0122e100:			0020: c4000000 00001006 00002000 00000000 19481000 00262688 00000020 13480000
 0122e120:			0040: 40262688 00001020 000f803e 00000000 c2010100 000f8000 00000000 c2000000
-t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
+			opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
 			fragment shader, start=0000, size=000c
 					    1002 0003 1000            	EXEC ADDR(0x2) CNT(0x1)
 					02: 90000001 1ffff688 00000002	   (S)FETCH:	SAMPLE	R0.xyzw = R0.xyz CONST(0) LOCATION(CENTER)
@@ -5510,31 +5510,31 @@ t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
 					    0000 0000 0000            	NOP
 0122e140:			0000: c00d2b00 00000001 0000000c 00031002 00001000 c4000000 00021003 00002000
 0122e160:			0020: 00000000 90000001 1ffff688 00000002 000f8000 00000000 c2000000
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 }
 0122e17c:			0000: c0012d00 00040181 00000106
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
 0122e188:			0000: c0012d00 00040180 10030002
-t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
+			opcode: CP_SET_CONSTANT (2d) (6 dwords)
 0122e19c:				0.000000 0.000000 0.000000 0.000000
 0122e194:			0000: c0042d00 00000080 00000000 00000000 00000000 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
 0122e1ac:			0000: c0012d00 00040202 00000c20
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
 0122e1b8:			0000: c0012d00 00040201 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 0122e1c4:			0000: c0012d00 00040104 0000000f
-t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
+			opcode: CP_SET_CONSTANT (2d) (6 dwords)
 				RB_BLEND_RED: 0
 				RB_BLEND_GREEN: 0
 				RB_BLEND_BLUE: 0
 				RB_BLEND_ALPHA: 0
 0122e1d0:			0000: c0042d00 00040105 00000000 00000000 00000000 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
+			opcode: CP_SET_CONSTANT (2d) (8 dwords)
 			set texture const 0000
 				clamp x/y/z: clamp-last-texel/clamp-last-texel/clamp-last-texel
 				filter min/mag: point/point
@@ -5542,23 +5542,23 @@ t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
 				addr=0108a000 (flags=806), size=256x256, pitch=16640, format=FMT_8_8_8_8
 				mipaddr=00000000 (flags=200)
 0122e1e8:			0000: c0062d00 00010000 82024800 0108a806 001fe0ff 00000c14 00000000 00000200
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				VGT_INDX_OFFSET: 0
 0122e208:			0000: c0012d00 00040102 00000000
-t0			write TC_CNTL_STATUS (0e00)
+			write TC_CNTL_STATUS (0e00)
 				TC_CNTL_STATUS: { L2_INVALIDATE }
 0122e214:			0000: 00000e00 00000001
-t3			opcode: CP_WAIT_REG_EQ (52) (5 dwords)
+			opcode: CP_WAIT_REG_EQ (52) (5 dwords)
 0122e21c:			0000: c0035200 000005d0 00000000 00001000 00000001
-t3			opcode: CP_DRAW_INDX_BIN (34) (7 dwords)
+			opcode: CP_DRAW_INDX_BIN (34) (7 dwords)
 0122e230:			0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 97
 				:0,0,101,97
 0122e24c:			0000: 0000057f 00000061
-t3			opcode: CP_NOP (10) (2 dwords)
+			opcode: CP_NOP (10) (2 dwords)
 0122e254:			0000: c0001000 00000000
-t3			opcode: CP_DRAW_INDX (22) (3 dwords)
+			opcode: CP_DRAW_INDX (22) (3 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRIFAN | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x40000 }
 			draw:          0
@@ -5634,220 +5634,220 @@ t3			opcode: CP_DRAW_INDX (22) (3 dwords)
  +	0003c000			RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
  +	ffffffff			RB_COLOR_DEST_MASK: 0xffffffff
 0122e25c:			0000: c0012200 00000000 00040085
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 98
 				:0,0,101,98
 0122e268:			0000: 0000057f 00000062
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 0122e270:			0000: c0002600 00000000
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e278:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e280:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e288:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e290:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e298:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2a0:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2a8:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2b0:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2b8:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2c0:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2c8:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2d0:			0000: c0004600 00000006
 0122d1d8:		0000: c0013700 0122e000 000000b6
-t2		nop
+		nop
 ############################################################
 vertices: 0
 cmd: deqp-gles2/185: fence=1263
 ############################################################
 cmdstream[13]: 124 dwords
-t0		write RB_BC_CONTROL (0f01)
+		write RB_BC_CONTROL (0f01)
 			RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 }
 0110a000:		0000: 00000f01 1c004046
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 }
 0110a008:		0000: c0012d00 00040293 00000020
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
 0110a014:		0000: c0012d00 00040316 00000002
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 }
 0110a020:		0000: c0012d00 00040317 00000002
-t0		write CP_PERFMON_CNTL (0444)
+		write CP_PERFMON_CNTL (0444)
 			CP_PERFMON_CNTL: 0
 0110a02c:		0000: 00000444 00000000
-t0		write RBBM_PM_OVERRIDE1 (039c)
+		write RBBM_PM_OVERRIDE1 (039c)
 			RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
 			RBBM_PM_OVERRIDE2: 0xfff
 0110a034:		0000: 0001039c ffffffff 00000fff
-t0		write TP0_CHICKEN (0e1e)
+		write TP0_CHICKEN (0e1e)
 			TP0_CHICKEN: 0x2
 0110a040:		0000: 00000e1e 00000002
-t3		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
+		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
 0110a048:		0000: c0003b00 00007fff
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			SQ_VS_CONST: { BASE = 32 | SIZE = 256 }
 0110a050:		0000: c0012d00 00040307 00100020
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			SQ_PS_CONST: { BASE = 288 | SIZE = 224 }
 0110a05c:		0000: c0012d00 00040308 000e0120
-t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
+		opcode: CP_SET_CONSTANT (2d) (4 dwords)
 			VGT_MAX_VTX_INDX: 0xffffffff
 			VGT_MIN_VTX_INDX: 0
 0110a068:		0000: c0022d00 00040100 ffffffff 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			VGT_INDX_OFFSET: 0
 0110a078:		0000: c0012d00 00040102 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			SQ_CONTEXT_MISC: { SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 }
 0110a084:		0000: c0012d00 00040181 00000004
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 }
 0110a090:		0000: c0012d00 00040182 ffffffff
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
 0110a09c:		0000: c0012d00 00040301 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_LINE_CNTL: { BRES_CNTL = 0 }
 0110a0a8:		0000: c0012d00 00040300 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
 0110a0b4:		0000: c0012d00 00040080 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
 0110a0c0:		0000: c0012d00 00040208 00000004
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_SAMPLE_POS: 0x88888888
 0110a0cc:		0000: c0012d00 0004020a 88888888
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_COLOR_DEST_MASK: 0xffffffff
 0110a0d8:		0000: c0012d00 00040326 ffffffff
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 0110a0e4:		0000: c0012d00 0004031b 0003c000
-t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
+		opcode: CP_SET_CONSTANT (2d) (4 dwords)
 			SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 }
 			SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 }
 0110a0f0:		0000: c0022d00 00040183 00000000 00000000
-t3		opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords)
+		opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords)
 0110a100:		0000: c0004b00 00000000
-t3		opcode: CP_WAIT_REG_EQ (52) (5 dwords)
+		opcode: CP_WAIT_REG_EQ (52) (5 dwords)
 0110a108:		0000: c0035200 000005d0 00000000 5f601000 00000001
-t0		write SQ_INST_STORE_MANAGMENT (0d02)
+		write SQ_INST_STORE_MANAGMENT (0d02)
 			SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 }
 0110a11c:		0000: 00000d02 00000180
-t3		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
+		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
 0110a124:		0000: c0003b00 00000300
-t3		opcode: CP_SET_SHADER_BASES (4a) (2 dwords)
+		opcode: CP_SET_SHADER_BASES (4a) (2 dwords)
 0110a12c:		0000: c0004a00 80000180
-t3		opcode: CP_SET_CONSTANT (2d) (14 dwords)
+		opcode: CP_SET_CONSTANT (2d) (14 dwords)
 0110a13c:			0.000000 0.000000 0.000000 0.000000 20000.000000 1.000000 0.500000 0.000000
 0110a15c:			2.000000 0.750000 0.375000 0.250000
 0110a134:		0000: c00c2d00 00000000 00000000 00000000 00000000 00000000 469c4000 3f800000
 0110a154:		0020: 3f000000 00000000 40000000 3f400000 3ec00000 3e800000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 0110a16c:		0000: c0012d00 00040104 0000000f
-t3		opcode: CP_SET_CONSTANT (2d) (6 dwords)
+		opcode: CP_SET_CONSTANT (2d) (6 dwords)
 			RB_BLEND_RED: 0
 			RB_BLEND_GREEN: 0
 			RB_BLEND_BLUE: 0
 			RB_BLEND_ALPHA: 0xff
 0110a178:		0000: c0042d00 00040105 00000000 00000000 00000000 000000ff
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT }
 0110a190:		0000: c0012d00 00040206 0000043f
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_SURFACE_INFO: { SURFACE_PITCH = 256 | MSAA_SAMPLES = 0 }
 0110a19c:		0000: c0012d00 00040000 00000100
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 1 | BASE = 0x108a000 }
 0110a1a8:		0000: c0012d00 00040001 0108a205
-t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
+		opcode: CP_SET_CONSTANT (2d) (4 dwords)
 			PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 }
 			PA_SC_SCREEN_SCISSOR_BR: { X = 256 | Y = 256 }
 0110a1b4:		0000: c0022d00 0004000e 80000000 01000100
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
 0110a1c4:		0000: c0012d00 00040080 00000000
-t0		write CP_SCRATCH_REG6 (057e)
+		write CP_SCRATCH_REG6 (057e)
 			CP_SCRATCH_REG6: 107
 			:0,0,107,98
 0110a1d0:		0000: 0000057e 0000006b
-t3		opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
+		opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
 		ibaddr:0110b000
 		ibsize:000000b8
-t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
+			opcode: CP_SET_CONSTANT (2d) (6 dwords)
 			set shader const 0078
 0110b000:			0000: c0042d00 00010078 0112d65b 00100000 0112d69b 00100000
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				PA_SC_AA_MASK: 0xffff
 0110b018:			0000: c0012d00 00040312 0000ffff
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
 0110b024:			0000: c0012d00 00040200 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (5 dwords)
+			opcode: CP_SET_CONSTANT (2d) (5 dwords)
 				RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
 				RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
 				RB_ALPHA_REF: 0
 0110b030:			0000: c0032d00 0004010c 00000000 00000000 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
+			opcode: CP_SET_CONSTANT (2d) (4 dwords)
 				PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
 				PA_SU_SC_MODE_CNTL: { POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST }
 0110b044:			0000: c0022d00 00040204 00000000 00090240
-t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
+			opcode: CP_SET_CONSTANT (2d) (6 dwords)
 				PA_SU_POINT_SIZE: { HEIGHT = 0.500000 | WIDTH = 0.500000 }
 				PA_SU_POINT_MINMAX: { MIN = 0.500000 | MAX = 0.500000 }
 				PA_SU_LINE_CNTL: { WIDTH = 0.500000 }
 				PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER }
 0110b054:			0000: c0042d00 00040280 00080008 00080008 00000008 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (7 dwords)
+			opcode: CP_SET_CONSTANT (2d) (7 dwords)
 				PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH }
 				PA_CL_GB_VERT_CLIP_ADJ: 1.000000
 				PA_CL_GB_VERT_DISC_ADJ: 1.000000
 				PA_CL_GB_HORZ_CLIP_ADJ: 1.000000
 				PA_CL_GB_HORZ_DISC_ADJ: 1.000000
 0110b06c:			0000: c0052d00 00040302 00000001 3f800000 3f800000 3f800000 3f800000
-t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
+			opcode: CP_SET_CONSTANT (2d) (4 dwords)
 				PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
 				PA_SC_WINDOW_SCISSOR_BR: { X = 256 | Y = 256 }
 0110b088:			0000: c0022d00 00040081 00000000 01000100
-t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
+			opcode: CP_SET_CONSTANT (2d) (8 dwords)
 				PA_CL_VPORT_XSCALE: 128.000000
 				PA_CL_VPORT_XOFFSET: 128.000000
 				PA_CL_VPORT_YSCALE: -128.000000
@@ -5855,11 +5855,11 @@ t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
 				PA_CL_VPORT_ZSCALE: 0.500000
 				PA_CL_VPORT_ZOFFSET: 0.500000
 0110b098:			0000: c0062d00 0004010f 43000000 43000000 c3000000 43000000 3f000000 3f000000
-t3			opcode: CP_SET_CONSTANT (2d) (10 dwords)
+			opcode: CP_SET_CONSTANT (2d) (10 dwords)
 0110b0c0:				128.000000 128.000000 0.500000 0.000000 128.000000 -128.000000 0.500000 0.000000
 0110b0b8:			0000: c0082d00 00000184 43000000 43000000 3f000000 00000000 43000000 c3000000
 0110b0d8:			0020: 3f000000 00000000
-t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords)
+			opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords)
 			vertex shader, start=0000, size=0015
 					    2003 0007 1000            	EXEC ADDR(0x3) CNT(0x2)
 					03: 19481000 00262688 00000010	   (S)FETCH:	VERTEX	R1.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(16) CONST(20, 0)
@@ -5874,7 +5874,7 @@ t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords)
 0110b0e0:			0000: c0162b00 00000000 00000015 00072003 00001000 c2000000 00021005 00001000
 0110b100:			0020: c4000000 00001006 00002000 00000000 19481000 00262688 00000010 13480000
 0110b120:			0040: 40252fc8 00000008 000f803e 00000000 c2010100 00038000 00000000 c2000000
-t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
+			opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
 			fragment shader, start=0000, size=000c
 					    1002 0003 1000            	EXEC ADDR(0x2) CNT(0x1)
 					02: 90000001 1ffff688 00000002	   (S)FETCH:	SAMPLE	R0.xyzw = R0.xyz CONST(0) LOCATION(CENTER)
@@ -5884,31 +5884,31 @@ t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
 					    0000 0000 0000            	NOP
 0110b140:			0000: c00d2b00 00000001 0000000c 00031002 00001000 c4000000 00021003 00002000
 0110b160:			0020: 00000000 90000001 1ffff688 00000002 000f8000 00000000 c2000000
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 }
 0110b17c:			0000: c0012d00 00040181 00000106
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
 0110b188:			0000: c0012d00 00040180 10030002
-t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
+			opcode: CP_SET_CONSTANT (2d) (6 dwords)
 0110b19c:				0.000000 0.000000 0.000000 0.000000
 0110b194:			0000: c0042d00 00000080 00000000 00000000 00000000 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_ALWAYS | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
 0110b1ac:			0000: c0012d00 00040202 00001c20
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
 0110b1b8:			0000: c0012d00 00040201 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 0110b1c4:			0000: c0012d00 00040104 0000000f
-t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
+			opcode: CP_SET_CONSTANT (2d) (6 dwords)
 				RB_BLEND_RED: 0
 				RB_BLEND_GREEN: 0
 				RB_BLEND_BLUE: 0
 				RB_BLEND_ALPHA: 0
 0110b1d0:			0000: c0042d00 00040105 00000000 00000000 00000000 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
+			opcode: CP_SET_CONSTANT (2d) (8 dwords)
 			set texture const 0000
 				clamp x/y/z: clamp-last-texel/clamp-last-texel/wrap
 				filter min/mag: point/point
@@ -5916,23 +5916,23 @@ t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
 				addr=01230000 (flags=820), size=64x128, pitch=16448, format=FMT_1_REVERSE
 				mipaddr=01240000 (flags=200)
 0110b1e8:			0000: c0062d00 00010000 80804800 01230820 000fe03f 00000d11 000001c0 01240200
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				VGT_INDX_OFFSET: 0
 0110b208:			0000: c0012d00 00040102 00000000
-t0			write TC_CNTL_STATUS (0e00)
+			write TC_CNTL_STATUS (0e00)
 				TC_CNTL_STATUS: { L2_INVALIDATE }
 0110b214:			0000: 00000e00 00000001
-t3			opcode: CP_WAIT_REG_EQ (52) (5 dwords)
+			opcode: CP_WAIT_REG_EQ (52) (5 dwords)
 0110b21c:			0000: c0035200 000005d0 00000000 00001000 00000001
-t3			opcode: CP_DRAW_INDX_BIN (34) (7 dwords)
+			opcode: CP_DRAW_INDX_BIN (34) (7 dwords)
 0110b230:			0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 103
 				:0,0,107,103
 0110b24c:			0000: 0000057f 00000067
-t3			opcode: CP_NOP (10) (2 dwords)
+			opcode: CP_NOP (10) (2 dwords)
 0110b254:			0000: c0001000 00000000
-t3			opcode: CP_DRAW_INDX (22) (5 dwords)
+			opcode: CP_DRAW_INDX (22) (5 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x60000 }
 				{ NUM_INDICES = 18011832 }
@@ -6010,220 +6010,220 @@ t3			opcode: CP_DRAW_INDX (22) (5 dwords)
  +	0003c000			RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
  +	ffffffff			RB_COLOR_DEST_MASK: 0xffffffff
 0110b25c:			0000: c0032200 00000000 00060004 0112d6b8 0000000c
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 104
 				:0,0,107,104
 0110b270:			0000: 0000057f 00000068
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 0110b278:			0000: c0002600 00000000
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0110b280:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0110b288:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0110b290:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0110b298:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0110b2a0:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0110b2a8:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0110b2b0:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0110b2b8:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0110b2c0:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0110b2c8:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0110b2d0:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0110b2d8:			0000: c0004600 00000006
 0110a1d8:		0000: c0013700 0110b000 000000b8
-t2		nop
+		nop
 ############################################################
 vertices: 0
 cmd: deqp-gles2/185: fence=1264
 ############################################################
 cmdstream[14]: 124 dwords
-t0		write RB_BC_CONTROL (0f01)
+		write RB_BC_CONTROL (0f01)
 			RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 }
 0122f000:		0000: 00000f01 1c004046
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 }
 0122f008:		0000: c0012d00 00040293 00000020
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
 0122f014:		0000: c0012d00 00040316 00000002
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 }
 0122f020:		0000: c0012d00 00040317 00000002
-t0		write CP_PERFMON_CNTL (0444)
+		write CP_PERFMON_CNTL (0444)
 			CP_PERFMON_CNTL: 0
 0122f02c:		0000: 00000444 00000000
-t0		write RBBM_PM_OVERRIDE1 (039c)
+		write RBBM_PM_OVERRIDE1 (039c)
 			RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
 			RBBM_PM_OVERRIDE2: 0xfff
 0122f034:		0000: 0001039c ffffffff 00000fff
-t0		write TP0_CHICKEN (0e1e)
+		write TP0_CHICKEN (0e1e)
 			TP0_CHICKEN: 0x2
 0122f040:		0000: 00000e1e 00000002
-t3		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
+		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
 0122f048:		0000: c0003b00 00007fff
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			SQ_VS_CONST: { BASE = 32 | SIZE = 256 }
 0122f050:		0000: c0012d00 00040307 00100020
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			SQ_PS_CONST: { BASE = 288 | SIZE = 224 }
 0122f05c:		0000: c0012d00 00040308 000e0120
-t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
+		opcode: CP_SET_CONSTANT (2d) (4 dwords)
 			VGT_MAX_VTX_INDX: 0xffffffff
 			VGT_MIN_VTX_INDX: 0
 0122f068:		0000: c0022d00 00040100 ffffffff 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			VGT_INDX_OFFSET: 0
 0122f078:		0000: c0012d00 00040102 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			SQ_CONTEXT_MISC: { SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 }
 0122f084:		0000: c0012d00 00040181 00000004
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 }
 0122f090:		0000: c0012d00 00040182 ffffffff
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
 0122f09c:		0000: c0012d00 00040301 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_LINE_CNTL: { BRES_CNTL = 0 }
 0122f0a8:		0000: c0012d00 00040300 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
 0122f0b4:		0000: c0012d00 00040080 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
 0122f0c0:		0000: c0012d00 00040208 00000004
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_SAMPLE_POS: 0x88888888
 0122f0cc:		0000: c0012d00 0004020a 88888888
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_COLOR_DEST_MASK: 0xffffffff
 0122f0d8:		0000: c0012d00 00040326 ffffffff
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 0122f0e4:		0000: c0012d00 0004031b 0003c000
-t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
+		opcode: CP_SET_CONSTANT (2d) (4 dwords)
 			SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 }
 			SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 }
 0122f0f0:		0000: c0022d00 00040183 00000000 00000000
-t3		opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords)
+		opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords)
 0122f100:		0000: c0004b00 00000000
-t3		opcode: CP_WAIT_REG_EQ (52) (5 dwords)
+		opcode: CP_WAIT_REG_EQ (52) (5 dwords)
 0122f108:		0000: c0035200 000005d0 00000000 5f601000 00000001
-t0		write SQ_INST_STORE_MANAGMENT (0d02)
+		write SQ_INST_STORE_MANAGMENT (0d02)
 			SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 }
 0122f11c:		0000: 00000d02 00000180
-t3		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
+		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
 0122f124:		0000: c0003b00 00000300
-t3		opcode: CP_SET_SHADER_BASES (4a) (2 dwords)
+		opcode: CP_SET_SHADER_BASES (4a) (2 dwords)
 0122f12c:		0000: c0004a00 80000180
-t3		opcode: CP_SET_CONSTANT (2d) (14 dwords)
+		opcode: CP_SET_CONSTANT (2d) (14 dwords)
 0122f13c:			0.000000 0.000000 0.000000 0.000000 20000.000000 1.000000 0.500000 0.000000
 0122f15c:			2.000000 0.750000 0.375000 0.250000
 0122f134:		0000: c00c2d00 00000000 00000000 00000000 00000000 00000000 469c4000 3f800000
 0122f154:		0020: 3f000000 00000000 40000000 3f400000 3ec00000 3e800000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 0122f16c:		0000: c0012d00 00040104 0000000f
-t3		opcode: CP_SET_CONSTANT (2d) (6 dwords)
+		opcode: CP_SET_CONSTANT (2d) (6 dwords)
 			RB_BLEND_RED: 0
 			RB_BLEND_GREEN: 0
 			RB_BLEND_BLUE: 0
 			RB_BLEND_ALPHA: 0xff
 0122f178:		0000: c0042d00 00040105 00000000 00000000 00000000 000000ff
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT }
 0122f190:		0000: c0012d00 00040206 0000043f
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 }
 0122f19c:		0000: c0012d00 00040000 00000020
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | LINEAR | ENDIAN = 0 | SWAP = 1 | BASE = 0x1266000 }
 0122f1a8:		0000: c0012d00 00040001 01266245
-t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
+		opcode: CP_SET_CONSTANT (2d) (4 dwords)
 			PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 }
 			PA_SC_SCREEN_SCISSOR_BR: { X = 16 | Y = 32 }
 0122f1b4:		0000: c0022d00 0004000e 80000000 00200010
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
 0122f1c4:		0000: c0012d00 00040080 00000000
-t0		write CP_SCRATCH_REG6 (057e)
+		write CP_SCRATCH_REG6 (057e)
 			CP_SCRATCH_REG6: 113
 			:0,0,113,104
 0122f1d0:		0000: 0000057e 00000071
-t3		opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
+		opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
 		ibaddr:0122e000
 		ibsize:000000b6
-t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
+			opcode: CP_SET_CONSTANT (2d) (6 dwords)
 			set shader const 0078
 0122e000:			0000: c0042d00 00010078 0112d6c7 00100000 0112d6c7 00100000
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				PA_SC_AA_MASK: 0xffff
 0122e018:			0000: c0012d00 00040312 0000ffff
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
 0122e024:			0000: c0012d00 00040200 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (5 dwords)
+			opcode: CP_SET_CONSTANT (2d) (5 dwords)
 				RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
 				RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
 				RB_ALPHA_REF: 0
 0122e030:			0000: c0032d00 0004010c 00000000 00000000 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
+			opcode: CP_SET_CONSTANT (2d) (4 dwords)
 				PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
 				PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST }
 0122e044:			0000: c0022d00 00040204 00000000 00090244
-t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
+			opcode: CP_SET_CONSTANT (2d) (6 dwords)
 				PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 }
 				PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 }
 				PA_SU_LINE_CNTL: { WIDTH = 0.000000 }
 				PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER }
 0122e054:			0000: c0042d00 00040280 00000000 00000000 00000000 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (7 dwords)
+			opcode: CP_SET_CONSTANT (2d) (7 dwords)
 				PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH }
 				PA_CL_GB_VERT_CLIP_ADJ: 1.000000
 				PA_CL_GB_VERT_DISC_ADJ: 1.000000
 				PA_CL_GB_HORZ_CLIP_ADJ: 1.000000
 				PA_CL_GB_HORZ_DISC_ADJ: 1.000000
 0122e06c:			0000: c0052d00 00040302 00000001 3f800000 3f800000 3f800000 3f800000
-t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
+			opcode: CP_SET_CONSTANT (2d) (4 dwords)
 				PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
 				PA_SC_WINDOW_SCISSOR_BR: { X = 16 | Y = 32 }
 0122e088:			0000: c0022d00 00040081 00000000 00200010
-t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
+			opcode: CP_SET_CONSTANT (2d) (8 dwords)
 				PA_CL_VPORT_XSCALE: 8.000000
 				PA_CL_VPORT_XOFFSET: 8.000000
 				PA_CL_VPORT_YSCALE: 16.000000
@@ -6231,11 +6231,11 @@ t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
 				PA_CL_VPORT_ZSCALE: 0.000000
 				PA_CL_VPORT_ZOFFSET: 0.000000
 0122e098:			0000: c0062d00 0004010f 41000000 41000000 41800000 41800000 00000000 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (10 dwords)
+			opcode: CP_SET_CONSTANT (2d) (10 dwords)
 0122e0c0:				8.000000 16.000000 0.000000 0.000000 8.000000 16.000000 0.000000 0.000000
 0122e0b8:			0000: c0082d00 00000184 41000000 41800000 00000000 00000000 41000000 41800000
 *
-t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords)
+			opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords)
 			vertex shader, start=0000, size=0015
 					    2003 0007 1000            	EXEC ADDR(0x3) CNT(0x2)
 					03: 19481000 00262688 00000020	   (S)FETCH:	VERTEX	R1.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) CONST(20, 0)
@@ -6250,7 +6250,7 @@ t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords)
 0122e0e0:			0000: c0162b00 00000000 00000015 00072003 00001000 c2000000 00021005 00001000
 0122e100:			0020: c4000000 00001006 00002000 00000000 19481000 00262688 00000020 13480000
 0122e120:			0040: 40262688 00001020 000f803e 00000000 c2010100 000f8000 00000000 c2000000
-t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
+			opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
 			fragment shader, start=0000, size=000c
 					    1002 0003 1000            	EXEC ADDR(0x2) CNT(0x1)
 					02: 90000001 1ffff688 00000002	   (S)FETCH:	SAMPLE	R0.xyzw = R0.xyz CONST(0) LOCATION(CENTER)
@@ -6260,31 +6260,31 @@ t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
 					    0000 0000 0000            	NOP
 0122e140:			0000: c00d2b00 00000001 0000000c 00031002 00001000 c4000000 00021003 00002000
 0122e160:			0020: 00000000 90000001 1ffff688 00000002 000f8000 00000000 c2000000
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 }
 0122e17c:			0000: c0012d00 00040181 00000106
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
 0122e188:			0000: c0012d00 00040180 10030002
-t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
+			opcode: CP_SET_CONSTANT (2d) (6 dwords)
 0122e19c:				0.000000 0.000000 0.000000 0.000000
 0122e194:			0000: c0042d00 00000080 00000000 00000000 00000000 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
 0122e1ac:			0000: c0012d00 00040202 00000c20
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
 0122e1b8:			0000: c0012d00 00040201 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 0122e1c4:			0000: c0012d00 00040104 0000000f
-t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
+			opcode: CP_SET_CONSTANT (2d) (6 dwords)
 				RB_BLEND_RED: 0
 				RB_BLEND_GREEN: 0
 				RB_BLEND_BLUE: 0
 				RB_BLEND_ALPHA: 0
 0122e1d0:			0000: c0042d00 00040105 00000000 00000000 00000000 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
+			opcode: CP_SET_CONSTANT (2d) (8 dwords)
 			set texture const 0000
 				clamp x/y/z: clamp-last-texel/clamp-last-texel/clamp-last-texel
 				filter min/mag: point/point
@@ -6292,23 +6292,23 @@ t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
 				addr=0108a000 (flags=806), size=256x256, pitch=16640, format=FMT_8_8_8_8
 				mipaddr=00000000 (flags=200)
 0122e1e8:			0000: c0062d00 00010000 82024800 0108a806 001fe0ff 00000c14 00000000 00000200
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				VGT_INDX_OFFSET: 0
 0122e208:			0000: c0012d00 00040102 00000000
-t0			write TC_CNTL_STATUS (0e00)
+			write TC_CNTL_STATUS (0e00)
 				TC_CNTL_STATUS: { L2_INVALIDATE }
 0122e214:			0000: 00000e00 00000001
-t3			opcode: CP_WAIT_REG_EQ (52) (5 dwords)
+			opcode: CP_WAIT_REG_EQ (52) (5 dwords)
 0122e21c:			0000: c0035200 000005d0 00000000 00001000 00000001
-t3			opcode: CP_DRAW_INDX_BIN (34) (7 dwords)
+			opcode: CP_DRAW_INDX_BIN (34) (7 dwords)
 0122e230:			0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 109
 				:0,0,113,109
 0122e24c:			0000: 0000057f 0000006d
-t3			opcode: CP_NOP (10) (2 dwords)
+			opcode: CP_NOP (10) (2 dwords)
 0122e254:			0000: c0001000 00000000
-t3			opcode: CP_DRAW_INDX (22) (3 dwords)
+			opcode: CP_DRAW_INDX (22) (3 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRIFAN | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x40000 }
 			draw:          0
@@ -6384,220 +6384,220 @@ t3			opcode: CP_DRAW_INDX (22) (3 dwords)
  +	0003c000			RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
  +	ffffffff			RB_COLOR_DEST_MASK: 0xffffffff
 0122e25c:			0000: c0012200 00000000 00040085
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 110
 				:0,0,113,110
 0122e268:			0000: 0000057f 0000006e
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 0122e270:			0000: c0002600 00000000
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e278:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e280:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e288:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e290:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e298:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2a0:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2a8:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2b0:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2b8:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2c0:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2c8:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2d0:			0000: c0004600 00000006
 0122f1d8:		0000: c0013700 0122e000 000000b6
-t2		nop
+		nop
 ############################################################
 vertices: 0
 cmd: deqp-gles2/185: fence=1265
 ############################################################
 cmdstream[15]: 124 dwords
-t0		write RB_BC_CONTROL (0f01)
+		write RB_BC_CONTROL (0f01)
 			RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 }
 0110c000:		0000: 00000f01 1c004046
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 }
 0110c008:		0000: c0012d00 00040293 00000020
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
 0110c014:		0000: c0012d00 00040316 00000002
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 }
 0110c020:		0000: c0012d00 00040317 00000002
-t0		write CP_PERFMON_CNTL (0444)
+		write CP_PERFMON_CNTL (0444)
 			CP_PERFMON_CNTL: 0
 0110c02c:		0000: 00000444 00000000
-t0		write RBBM_PM_OVERRIDE1 (039c)
+		write RBBM_PM_OVERRIDE1 (039c)
 			RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
 			RBBM_PM_OVERRIDE2: 0xfff
 0110c034:		0000: 0001039c ffffffff 00000fff
-t0		write TP0_CHICKEN (0e1e)
+		write TP0_CHICKEN (0e1e)
 			TP0_CHICKEN: 0x2
 0110c040:		0000: 00000e1e 00000002
-t3		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
+		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
 0110c048:		0000: c0003b00 00007fff
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			SQ_VS_CONST: { BASE = 32 | SIZE = 256 }
 0110c050:		0000: c0012d00 00040307 00100020
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			SQ_PS_CONST: { BASE = 288 | SIZE = 224 }
 0110c05c:		0000: c0012d00 00040308 000e0120
-t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
+		opcode: CP_SET_CONSTANT (2d) (4 dwords)
 			VGT_MAX_VTX_INDX: 0xffffffff
 			VGT_MIN_VTX_INDX: 0
 0110c068:		0000: c0022d00 00040100 ffffffff 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			VGT_INDX_OFFSET: 0
 0110c078:		0000: c0012d00 00040102 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			SQ_CONTEXT_MISC: { SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 }
 0110c084:		0000: c0012d00 00040181 00000004
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 }
 0110c090:		0000: c0012d00 00040182 ffffffff
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
 0110c09c:		0000: c0012d00 00040301 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_LINE_CNTL: { BRES_CNTL = 0 }
 0110c0a8:		0000: c0012d00 00040300 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
 0110c0b4:		0000: c0012d00 00040080 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
 0110c0c0:		0000: c0012d00 00040208 00000004
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_SAMPLE_POS: 0x88888888
 0110c0cc:		0000: c0012d00 0004020a 88888888
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_COLOR_DEST_MASK: 0xffffffff
 0110c0d8:		0000: c0012d00 00040326 ffffffff
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 0110c0e4:		0000: c0012d00 0004031b 0003c000
-t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
+		opcode: CP_SET_CONSTANT (2d) (4 dwords)
 			SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 }
 			SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 }
 0110c0f0:		0000: c0022d00 00040183 00000000 00000000
-t3		opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords)
+		opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords)
 0110c100:		0000: c0004b00 00000000
-t3		opcode: CP_WAIT_REG_EQ (52) (5 dwords)
+		opcode: CP_WAIT_REG_EQ (52) (5 dwords)
 0110c108:		0000: c0035200 000005d0 00000000 5f601000 00000001
-t0		write SQ_INST_STORE_MANAGMENT (0d02)
+		write SQ_INST_STORE_MANAGMENT (0d02)
 			SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 }
 0110c11c:		0000: 00000d02 00000180
-t3		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
+		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
 0110c124:		0000: c0003b00 00000300
-t3		opcode: CP_SET_SHADER_BASES (4a) (2 dwords)
+		opcode: CP_SET_SHADER_BASES (4a) (2 dwords)
 0110c12c:		0000: c0004a00 80000180
-t3		opcode: CP_SET_CONSTANT (2d) (14 dwords)
+		opcode: CP_SET_CONSTANT (2d) (14 dwords)
 0110c13c:			0.000000 0.000000 0.000000 0.000000 20000.000000 1.000000 0.500000 0.000000
 0110c15c:			2.000000 0.750000 0.375000 0.250000
 0110c134:		0000: c00c2d00 00000000 00000000 00000000 00000000 00000000 469c4000 3f800000
 0110c154:		0020: 3f000000 00000000 40000000 3f400000 3ec00000 3e800000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 0110c16c:		0000: c0012d00 00040104 0000000f
-t3		opcode: CP_SET_CONSTANT (2d) (6 dwords)
+		opcode: CP_SET_CONSTANT (2d) (6 dwords)
 			RB_BLEND_RED: 0
 			RB_BLEND_GREEN: 0
 			RB_BLEND_BLUE: 0
 			RB_BLEND_ALPHA: 0xff
 0110c178:		0000: c0042d00 00040105 00000000 00000000 00000000 000000ff
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT }
 0110c190:		0000: c0012d00 00040206 0000043f
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_SURFACE_INFO: { SURFACE_PITCH = 256 | MSAA_SAMPLES = 0 }
 0110c19c:		0000: c0012d00 00040000 00000100
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 1 | BASE = 0x108a000 }
 0110c1a8:		0000: c0012d00 00040001 0108a205
-t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
+		opcode: CP_SET_CONSTANT (2d) (4 dwords)
 			PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 }
 			PA_SC_SCREEN_SCISSOR_BR: { X = 256 | Y = 256 }
 0110c1b4:		0000: c0022d00 0004000e 80000000 01000100
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
 0110c1c4:		0000: c0012d00 00040080 00000000
-t0		write CP_SCRATCH_REG6 (057e)
+		write CP_SCRATCH_REG6 (057e)
 			CP_SCRATCH_REG6: 119
 			:0,0,119,110
 0110c1d0:		0000: 0000057e 00000077
-t3		opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
+		opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
 		ibaddr:0110b000
 		ibsize:000000b8
-t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
+			opcode: CP_SET_CONSTANT (2d) (6 dwords)
 			set shader const 0078
 0110b000:			0000: c0042d00 00010078 0112d747 00100000 0112d787 00100000
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				PA_SC_AA_MASK: 0xffff
 0110b018:			0000: c0012d00 00040312 0000ffff
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
 0110b024:			0000: c0012d00 00040200 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (5 dwords)
+			opcode: CP_SET_CONSTANT (2d) (5 dwords)
 				RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
 				RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
 				RB_ALPHA_REF: 0
 0110b030:			0000: c0032d00 0004010c 00000000 00000000 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
+			opcode: CP_SET_CONSTANT (2d) (4 dwords)
 				PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
 				PA_SU_SC_MODE_CNTL: { POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST }
 0110b044:			0000: c0022d00 00040204 00000000 00090240
-t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
+			opcode: CP_SET_CONSTANT (2d) (6 dwords)
 				PA_SU_POINT_SIZE: { HEIGHT = 0.500000 | WIDTH = 0.500000 }
 				PA_SU_POINT_MINMAX: { MIN = 0.500000 | MAX = 0.500000 }
 				PA_SU_LINE_CNTL: { WIDTH = 0.500000 }
 				PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER }
 0110b054:			0000: c0042d00 00040280 00080008 00080008 00000008 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (7 dwords)
+			opcode: CP_SET_CONSTANT (2d) (7 dwords)
 				PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH }
 				PA_CL_GB_VERT_CLIP_ADJ: 1.000000
 				PA_CL_GB_VERT_DISC_ADJ: 1.000000
 				PA_CL_GB_HORZ_CLIP_ADJ: 1.000000
 				PA_CL_GB_HORZ_DISC_ADJ: 1.000000
 0110b06c:			0000: c0052d00 00040302 00000001 3f800000 3f800000 3f800000 3f800000
-t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
+			opcode: CP_SET_CONSTANT (2d) (4 dwords)
 				PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
 				PA_SC_WINDOW_SCISSOR_BR: { X = 256 | Y = 256 }
 0110b088:			0000: c0022d00 00040081 00000000 01000100
-t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
+			opcode: CP_SET_CONSTANT (2d) (8 dwords)
 				PA_CL_VPORT_XSCALE: 128.000000
 				PA_CL_VPORT_XOFFSET: 128.000000
 				PA_CL_VPORT_YSCALE: -128.000000
@@ -6605,11 +6605,11 @@ t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
 				PA_CL_VPORT_ZSCALE: 0.500000
 				PA_CL_VPORT_ZOFFSET: 0.500000
 0110b098:			0000: c0062d00 0004010f 43000000 43000000 c3000000 43000000 3f000000 3f000000
-t3			opcode: CP_SET_CONSTANT (2d) (10 dwords)
+			opcode: CP_SET_CONSTANT (2d) (10 dwords)
 0110b0c0:				128.000000 128.000000 0.500000 0.000000 128.000000 -128.000000 0.500000 0.000000
 0110b0b8:			0000: c0082d00 00000184 43000000 43000000 3f000000 00000000 43000000 c3000000
 0110b0d8:			0020: 3f000000 00000000
-t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords)
+			opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords)
 			vertex shader, start=0000, size=0015
 					    2003 0007 1000            	EXEC ADDR(0x3) CNT(0x2)
 					03: 19481000 00262688 00000010	   (S)FETCH:	VERTEX	R1.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(16) CONST(20, 0)
@@ -6624,7 +6624,7 @@ t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords)
 0110b0e0:			0000: c0162b00 00000000 00000015 00072003 00001000 c2000000 00021005 00001000
 0110b100:			0020: c4000000 00001006 00002000 00000000 19481000 00262688 00000010 13480000
 0110b120:			0040: 40252fc8 00000008 000f803e 00000000 c2010100 00038000 00000000 c2000000
-t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
+			opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
 			fragment shader, start=0000, size=000c
 					    1002 0003 1000            	EXEC ADDR(0x2) CNT(0x1)
 					02: 90000001 1ffff688 00000002	   (S)FETCH:	SAMPLE	R0.xyzw = R0.xyz CONST(0) LOCATION(CENTER)
@@ -6634,31 +6634,31 @@ t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
 					    0000 0000 0000            	NOP
 0110b140:			0000: c00d2b00 00000001 0000000c 00031002 00001000 c4000000 00021003 00002000
 0110b160:			0020: 00000000 90000001 1ffff688 00000002 000f8000 00000000 c2000000
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 }
 0110b17c:			0000: c0012d00 00040181 00000106
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
 0110b188:			0000: c0012d00 00040180 10030002
-t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
+			opcode: CP_SET_CONSTANT (2d) (6 dwords)
 0110b19c:				0.000000 0.000000 0.000000 0.000000
 0110b194:			0000: c0042d00 00000080 00000000 00000000 00000000 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_ALWAYS | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
 0110b1ac:			0000: c0012d00 00040202 00001c20
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
 0110b1b8:			0000: c0012d00 00040201 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 0110b1c4:			0000: c0012d00 00040104 0000000f
-t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
+			opcode: CP_SET_CONSTANT (2d) (6 dwords)
 				RB_BLEND_RED: 0
 				RB_BLEND_GREEN: 0
 				RB_BLEND_BLUE: 0
 				RB_BLEND_ALPHA: 0
 0110b1d0:			0000: c0042d00 00040105 00000000 00000000 00000000 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
+			opcode: CP_SET_CONSTANT (2d) (8 dwords)
 			set texture const 0000
 				clamp x/y/z: clamp-last-texel/clamp-last-texel/wrap
 				filter min/mag: point/point
@@ -6666,23 +6666,23 @@ t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
 				addr=01230000 (flags=820), size=64x128, pitch=16448, format=FMT_1_REVERSE
 				mipaddr=01240000 (flags=200)
 0110b1e8:			0000: c0062d00 00010000 80804800 01230820 000fe03f 00000d11 000001c0 01240200
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				VGT_INDX_OFFSET: 0
 0110b208:			0000: c0012d00 00040102 00000000
-t0			write TC_CNTL_STATUS (0e00)
+			write TC_CNTL_STATUS (0e00)
 				TC_CNTL_STATUS: { L2_INVALIDATE }
 0110b214:			0000: 00000e00 00000001
-t3			opcode: CP_WAIT_REG_EQ (52) (5 dwords)
+			opcode: CP_WAIT_REG_EQ (52) (5 dwords)
 0110b21c:			0000: c0035200 000005d0 00000000 00001000 00000001
-t3			opcode: CP_DRAW_INDX_BIN (34) (7 dwords)
+			opcode: CP_DRAW_INDX_BIN (34) (7 dwords)
 0110b230:			0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 115
 				:0,0,119,115
 0110b24c:			0000: 0000057f 00000073
-t3			opcode: CP_NOP (10) (2 dwords)
+			opcode: CP_NOP (10) (2 dwords)
 0110b254:			0000: c0001000 00000000
-t3			opcode: CP_DRAW_INDX (22) (5 dwords)
+			opcode: CP_DRAW_INDX (22) (5 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x60000 }
 				{ NUM_INDICES = 18012068 }
@@ -6760,220 +6760,220 @@ t3			opcode: CP_DRAW_INDX (22) (5 dwords)
  +	0003c000			RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
  +	ffffffff			RB_COLOR_DEST_MASK: 0xffffffff
 0110b25c:			0000: c0032200 00000000 00060004 0112d7a4 0000000c
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 116
 				:0,0,119,116
 0110b270:			0000: 0000057f 00000074
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 0110b278:			0000: c0002600 00000000
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0110b280:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0110b288:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0110b290:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0110b298:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0110b2a0:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0110b2a8:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0110b2b0:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0110b2b8:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0110b2c0:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0110b2c8:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0110b2d0:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0110b2d8:			0000: c0004600 00000006
 0110c1d8:		0000: c0013700 0110b000 000000b8
-t2		nop
+		nop
 ############################################################
 vertices: 0
 cmd: deqp-gles2/185: fence=1266
 ############################################################
 cmdstream[16]: 124 dwords
-t0		write RB_BC_CONTROL (0f01)
+		write RB_BC_CONTROL (0f01)
 			RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 }
 0122d000:		0000: 00000f01 1c004046
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 }
 0122d008:		0000: c0012d00 00040293 00000020
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
 0122d014:		0000: c0012d00 00040316 00000002
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 }
 0122d020:		0000: c0012d00 00040317 00000002
-t0		write CP_PERFMON_CNTL (0444)
+		write CP_PERFMON_CNTL (0444)
 			CP_PERFMON_CNTL: 0
 0122d02c:		0000: 00000444 00000000
-t0		write RBBM_PM_OVERRIDE1 (039c)
+		write RBBM_PM_OVERRIDE1 (039c)
 			RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
 			RBBM_PM_OVERRIDE2: 0xfff
 0122d034:		0000: 0001039c ffffffff 00000fff
-t0		write TP0_CHICKEN (0e1e)
+		write TP0_CHICKEN (0e1e)
 			TP0_CHICKEN: 0x2
 0122d040:		0000: 00000e1e 00000002
-t3		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
+		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
 0122d048:		0000: c0003b00 00007fff
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			SQ_VS_CONST: { BASE = 32 | SIZE = 256 }
 0122d050:		0000: c0012d00 00040307 00100020
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			SQ_PS_CONST: { BASE = 288 | SIZE = 224 }
 0122d05c:		0000: c0012d00 00040308 000e0120
-t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
+		opcode: CP_SET_CONSTANT (2d) (4 dwords)
 			VGT_MAX_VTX_INDX: 0xffffffff
 			VGT_MIN_VTX_INDX: 0
 0122d068:		0000: c0022d00 00040100 ffffffff 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			VGT_INDX_OFFSET: 0
 0122d078:		0000: c0012d00 00040102 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			SQ_CONTEXT_MISC: { SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 }
 0122d084:		0000: c0012d00 00040181 00000004
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 }
 0122d090:		0000: c0012d00 00040182 ffffffff
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
 0122d09c:		0000: c0012d00 00040301 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_LINE_CNTL: { BRES_CNTL = 0 }
 0122d0a8:		0000: c0012d00 00040300 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
 0122d0b4:		0000: c0012d00 00040080 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
 0122d0c0:		0000: c0012d00 00040208 00000004
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_SAMPLE_POS: 0x88888888
 0122d0cc:		0000: c0012d00 0004020a 88888888
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_COLOR_DEST_MASK: 0xffffffff
 0122d0d8:		0000: c0012d00 00040326 ffffffff
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 0122d0e4:		0000: c0012d00 0004031b 0003c000
-t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
+		opcode: CP_SET_CONSTANT (2d) (4 dwords)
 			SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 }
 			SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 }
 0122d0f0:		0000: c0022d00 00040183 00000000 00000000
-t3		opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords)
+		opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords)
 0122d100:		0000: c0004b00 00000000
-t3		opcode: CP_WAIT_REG_EQ (52) (5 dwords)
+		opcode: CP_WAIT_REG_EQ (52) (5 dwords)
 0122d108:		0000: c0035200 000005d0 00000000 5f601000 00000001
-t0		write SQ_INST_STORE_MANAGMENT (0d02)
+		write SQ_INST_STORE_MANAGMENT (0d02)
 			SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 }
 0122d11c:		0000: 00000d02 00000180
-t3		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
+		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
 0122d124:		0000: c0003b00 00000300
-t3		opcode: CP_SET_SHADER_BASES (4a) (2 dwords)
+		opcode: CP_SET_SHADER_BASES (4a) (2 dwords)
 0122d12c:		0000: c0004a00 80000180
-t3		opcode: CP_SET_CONSTANT (2d) (14 dwords)
+		opcode: CP_SET_CONSTANT (2d) (14 dwords)
 0122d13c:			0.000000 0.000000 0.000000 0.000000 20000.000000 1.000000 0.500000 0.000000
 0122d15c:			2.000000 0.750000 0.375000 0.250000
 0122d134:		0000: c00c2d00 00000000 00000000 00000000 00000000 00000000 469c4000 3f800000
 0122d154:		0020: 3f000000 00000000 40000000 3f400000 3ec00000 3e800000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 0122d16c:		0000: c0012d00 00040104 0000000f
-t3		opcode: CP_SET_CONSTANT (2d) (6 dwords)
+		opcode: CP_SET_CONSTANT (2d) (6 dwords)
 			RB_BLEND_RED: 0
 			RB_BLEND_GREEN: 0
 			RB_BLEND_BLUE: 0
 			RB_BLEND_ALPHA: 0xff
 0122d178:		0000: c0042d00 00040105 00000000 00000000 00000000 000000ff
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT }
 0122d190:		0000: c0012d00 00040206 0000043f
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 }
 0122d19c:		0000: c0012d00 00040000 00000020
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | LINEAR | ENDIAN = 0 | SWAP = 1 | BASE = 0x1266000 }
 0122d1a8:		0000: c0012d00 00040001 01266245
-t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
+		opcode: CP_SET_CONSTANT (2d) (4 dwords)
 			PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 }
 			PA_SC_SCREEN_SCISSOR_BR: { X = 8 | Y = 16 }
 0122d1b4:		0000: c0022d00 0004000e 80000000 00100008
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
 0122d1c4:		0000: c0012d00 00040080 00000000
-t0		write CP_SCRATCH_REG6 (057e)
+		write CP_SCRATCH_REG6 (057e)
 			CP_SCRATCH_REG6: 125
 			:0,0,125,116
 0122d1d0:		0000: 0000057e 0000007d
-t3		opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
+		opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
 		ibaddr:0122e000
 		ibsize:000000b6
-t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
+			opcode: CP_SET_CONSTANT (2d) (6 dwords)
 			set shader const 0078
 0122e000:			0000: c0042d00 00010078 0112d7b3 00100000 0112d7b3 00100000
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				PA_SC_AA_MASK: 0xffff
 0122e018:			0000: c0012d00 00040312 0000ffff
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
 0122e024:			0000: c0012d00 00040200 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (5 dwords)
+			opcode: CP_SET_CONSTANT (2d) (5 dwords)
 				RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
 				RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
 				RB_ALPHA_REF: 0
 0122e030:			0000: c0032d00 0004010c 00000000 00000000 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
+			opcode: CP_SET_CONSTANT (2d) (4 dwords)
 				PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
 				PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST }
 0122e044:			0000: c0022d00 00040204 00000000 00090244
-t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
+			opcode: CP_SET_CONSTANT (2d) (6 dwords)
 				PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 }
 				PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 }
 				PA_SU_LINE_CNTL: { WIDTH = 0.000000 }
 				PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER }
 0122e054:			0000: c0042d00 00040280 00000000 00000000 00000000 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (7 dwords)
+			opcode: CP_SET_CONSTANT (2d) (7 dwords)
 				PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH }
 				PA_CL_GB_VERT_CLIP_ADJ: 1.000000
 				PA_CL_GB_VERT_DISC_ADJ: 1.000000
 				PA_CL_GB_HORZ_CLIP_ADJ: 1.000000
 				PA_CL_GB_HORZ_DISC_ADJ: 1.000000
 0122e06c:			0000: c0052d00 00040302 00000001 3f800000 3f800000 3f800000 3f800000
-t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
+			opcode: CP_SET_CONSTANT (2d) (4 dwords)
 				PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
 				PA_SC_WINDOW_SCISSOR_BR: { X = 8 | Y = 16 }
 0122e088:			0000: c0022d00 00040081 00000000 00100008
-t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
+			opcode: CP_SET_CONSTANT (2d) (8 dwords)
 				PA_CL_VPORT_XSCALE: 4.000000
 				PA_CL_VPORT_XOFFSET: 4.000000
 				PA_CL_VPORT_YSCALE: 8.000000
@@ -6981,11 +6981,11 @@ t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
 				PA_CL_VPORT_ZSCALE: 0.000000
 				PA_CL_VPORT_ZOFFSET: 0.000000
 0122e098:			0000: c0062d00 0004010f 40800000 40800000 41000000 41000000 00000000 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (10 dwords)
+			opcode: CP_SET_CONSTANT (2d) (10 dwords)
 0122e0c0:				4.000000 8.000000 0.000000 0.000000 4.000000 8.000000 0.000000 0.000000
 0122e0b8:			0000: c0082d00 00000184 40800000 41000000 00000000 00000000 40800000 41000000
 *
-t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords)
+			opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords)
 			vertex shader, start=0000, size=0015
 					    2003 0007 1000            	EXEC ADDR(0x3) CNT(0x2)
 					03: 19481000 00262688 00000020	   (S)FETCH:	VERTEX	R1.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) CONST(20, 0)
@@ -7000,7 +7000,7 @@ t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords)
 0122e0e0:			0000: c0162b00 00000000 00000015 00072003 00001000 c2000000 00021005 00001000
 0122e100:			0020: c4000000 00001006 00002000 00000000 19481000 00262688 00000020 13480000
 0122e120:			0040: 40262688 00001020 000f803e 00000000 c2010100 000f8000 00000000 c2000000
-t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
+			opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
 			fragment shader, start=0000, size=000c
 					    1002 0003 1000            	EXEC ADDR(0x2) CNT(0x1)
 					02: 90000001 1ffff688 00000002	   (S)FETCH:	SAMPLE	R0.xyzw = R0.xyz CONST(0) LOCATION(CENTER)
@@ -7010,31 +7010,31 @@ t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
 					    0000 0000 0000            	NOP
 0122e140:			0000: c00d2b00 00000001 0000000c 00031002 00001000 c4000000 00021003 00002000
 0122e160:			0020: 00000000 90000001 1ffff688 00000002 000f8000 00000000 c2000000
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 }
 0122e17c:			0000: c0012d00 00040181 00000106
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
 0122e188:			0000: c0012d00 00040180 10030002
-t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
+			opcode: CP_SET_CONSTANT (2d) (6 dwords)
 0122e19c:				0.000000 0.000000 0.000000 0.000000
 0122e194:			0000: c0042d00 00000080 00000000 00000000 00000000 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
 0122e1ac:			0000: c0012d00 00040202 00000c20
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
 0122e1b8:			0000: c0012d00 00040201 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 0122e1c4:			0000: c0012d00 00040104 0000000f
-t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
+			opcode: CP_SET_CONSTANT (2d) (6 dwords)
 				RB_BLEND_RED: 0
 				RB_BLEND_GREEN: 0
 				RB_BLEND_BLUE: 0
 				RB_BLEND_ALPHA: 0
 0122e1d0:			0000: c0042d00 00040105 00000000 00000000 00000000 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
+			opcode: CP_SET_CONSTANT (2d) (8 dwords)
 			set texture const 0000
 				clamp x/y/z: clamp-last-texel/clamp-last-texel/clamp-last-texel
 				filter min/mag: point/point
@@ -7042,23 +7042,23 @@ t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
 				addr=0108a000 (flags=806), size=256x256, pitch=16640, format=FMT_8_8_8_8
 				mipaddr=00000000 (flags=200)
 0122e1e8:			0000: c0062d00 00010000 82024800 0108a806 001fe0ff 00000c14 00000000 00000200
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				VGT_INDX_OFFSET: 0
 0122e208:			0000: c0012d00 00040102 00000000
-t0			write TC_CNTL_STATUS (0e00)
+			write TC_CNTL_STATUS (0e00)
 				TC_CNTL_STATUS: { L2_INVALIDATE }
 0122e214:			0000: 00000e00 00000001
-t3			opcode: CP_WAIT_REG_EQ (52) (5 dwords)
+			opcode: CP_WAIT_REG_EQ (52) (5 dwords)
 0122e21c:			0000: c0035200 000005d0 00000000 00001000 00000001
-t3			opcode: CP_DRAW_INDX_BIN (34) (7 dwords)
+			opcode: CP_DRAW_INDX_BIN (34) (7 dwords)
 0122e230:			0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 121
 				:0,0,125,121
 0122e24c:			0000: 0000057f 00000079
-t3			opcode: CP_NOP (10) (2 dwords)
+			opcode: CP_NOP (10) (2 dwords)
 0122e254:			0000: c0001000 00000000
-t3			opcode: CP_DRAW_INDX (22) (3 dwords)
+			opcode: CP_DRAW_INDX (22) (3 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRIFAN | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x40000 }
 			draw:          0
@@ -7134,220 +7134,220 @@ t3			opcode: CP_DRAW_INDX (22) (3 dwords)
  +	0003c000			RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
  +	ffffffff			RB_COLOR_DEST_MASK: 0xffffffff
 0122e25c:			0000: c0012200 00000000 00040085
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 122
 				:0,0,125,122
 0122e268:			0000: 0000057f 0000007a
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 0122e270:			0000: c0002600 00000000
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e278:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e280:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e288:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e290:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e298:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2a0:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2a8:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2b0:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2b8:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2c0:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2c8:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2d0:			0000: c0004600 00000006
 0122d1d8:		0000: c0013700 0122e000 000000b6
-t2		nop
+		nop
 ############################################################
 vertices: 0
 cmd: deqp-gles2/185: fence=1267
 ############################################################
 cmdstream[17]: 124 dwords
-t0		write RB_BC_CONTROL (0f01)
+		write RB_BC_CONTROL (0f01)
 			RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 }
 0110a000:		0000: 00000f01 1c004046
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 }
 0110a008:		0000: c0012d00 00040293 00000020
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
 0110a014:		0000: c0012d00 00040316 00000002
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 }
 0110a020:		0000: c0012d00 00040317 00000002
-t0		write CP_PERFMON_CNTL (0444)
+		write CP_PERFMON_CNTL (0444)
 			CP_PERFMON_CNTL: 0
 0110a02c:		0000: 00000444 00000000
-t0		write RBBM_PM_OVERRIDE1 (039c)
+		write RBBM_PM_OVERRIDE1 (039c)
 			RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
 			RBBM_PM_OVERRIDE2: 0xfff
 0110a034:		0000: 0001039c ffffffff 00000fff
-t0		write TP0_CHICKEN (0e1e)
+		write TP0_CHICKEN (0e1e)
 			TP0_CHICKEN: 0x2
 0110a040:		0000: 00000e1e 00000002
-t3		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
+		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
 0110a048:		0000: c0003b00 00007fff
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			SQ_VS_CONST: { BASE = 32 | SIZE = 256 }
 0110a050:		0000: c0012d00 00040307 00100020
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			SQ_PS_CONST: { BASE = 288 | SIZE = 224 }
 0110a05c:		0000: c0012d00 00040308 000e0120
-t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
+		opcode: CP_SET_CONSTANT (2d) (4 dwords)
 			VGT_MAX_VTX_INDX: 0xffffffff
 			VGT_MIN_VTX_INDX: 0
 0110a068:		0000: c0022d00 00040100 ffffffff 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			VGT_INDX_OFFSET: 0
 0110a078:		0000: c0012d00 00040102 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			SQ_CONTEXT_MISC: { SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 }
 0110a084:		0000: c0012d00 00040181 00000004
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 }
 0110a090:		0000: c0012d00 00040182 ffffffff
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
 0110a09c:		0000: c0012d00 00040301 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_LINE_CNTL: { BRES_CNTL = 0 }
 0110a0a8:		0000: c0012d00 00040300 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
 0110a0b4:		0000: c0012d00 00040080 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
 0110a0c0:		0000: c0012d00 00040208 00000004
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_SAMPLE_POS: 0x88888888
 0110a0cc:		0000: c0012d00 0004020a 88888888
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_COLOR_DEST_MASK: 0xffffffff
 0110a0d8:		0000: c0012d00 00040326 ffffffff
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 0110a0e4:		0000: c0012d00 0004031b 0003c000
-t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
+		opcode: CP_SET_CONSTANT (2d) (4 dwords)
 			SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 }
 			SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 }
 0110a0f0:		0000: c0022d00 00040183 00000000 00000000
-t3		opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords)
+		opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords)
 0110a100:		0000: c0004b00 00000000
-t3		opcode: CP_WAIT_REG_EQ (52) (5 dwords)
+		opcode: CP_WAIT_REG_EQ (52) (5 dwords)
 0110a108:		0000: c0035200 000005d0 00000000 5f601000 00000001
-t0		write SQ_INST_STORE_MANAGMENT (0d02)
+		write SQ_INST_STORE_MANAGMENT (0d02)
 			SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 }
 0110a11c:		0000: 00000d02 00000180
-t3		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
+		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
 0110a124:		0000: c0003b00 00000300
-t3		opcode: CP_SET_SHADER_BASES (4a) (2 dwords)
+		opcode: CP_SET_SHADER_BASES (4a) (2 dwords)
 0110a12c:		0000: c0004a00 80000180
-t3		opcode: CP_SET_CONSTANT (2d) (14 dwords)
+		opcode: CP_SET_CONSTANT (2d) (14 dwords)
 0110a13c:			0.000000 0.000000 0.000000 0.000000 20000.000000 1.000000 0.500000 0.000000
 0110a15c:			2.000000 0.750000 0.375000 0.250000
 0110a134:		0000: c00c2d00 00000000 00000000 00000000 00000000 00000000 469c4000 3f800000
 0110a154:		0020: 3f000000 00000000 40000000 3f400000 3ec00000 3e800000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 0110a16c:		0000: c0012d00 00040104 0000000f
-t3		opcode: CP_SET_CONSTANT (2d) (6 dwords)
+		opcode: CP_SET_CONSTANT (2d) (6 dwords)
 			RB_BLEND_RED: 0
 			RB_BLEND_GREEN: 0
 			RB_BLEND_BLUE: 0
 			RB_BLEND_ALPHA: 0xff
 0110a178:		0000: c0042d00 00040105 00000000 00000000 00000000 000000ff
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT }
 0110a190:		0000: c0012d00 00040206 0000043f
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_SURFACE_INFO: { SURFACE_PITCH = 256 | MSAA_SAMPLES = 0 }
 0110a19c:		0000: c0012d00 00040000 00000100
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 1 | BASE = 0x108a000 }
 0110a1a8:		0000: c0012d00 00040001 0108a205
-t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
+		opcode: CP_SET_CONSTANT (2d) (4 dwords)
 			PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 }
 			PA_SC_SCREEN_SCISSOR_BR: { X = 256 | Y = 256 }
 0110a1b4:		0000: c0022d00 0004000e 80000000 01000100
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
 0110a1c4:		0000: c0012d00 00040080 00000000
-t0		write CP_SCRATCH_REG6 (057e)
+		write CP_SCRATCH_REG6 (057e)
 			CP_SCRATCH_REG6: 131
 			:0,0,131,122
 0110a1d0:		0000: 0000057e 00000083
-t3		opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
+		opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
 		ibaddr:0110b000
 		ibsize:000000b8
-t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
+			opcode: CP_SET_CONSTANT (2d) (6 dwords)
 			set shader const 0078
 0110b000:			0000: c0042d00 00010078 0112d833 00100000 0112d873 00100000
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				PA_SC_AA_MASK: 0xffff
 0110b018:			0000: c0012d00 00040312 0000ffff
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
 0110b024:			0000: c0012d00 00040200 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (5 dwords)
+			opcode: CP_SET_CONSTANT (2d) (5 dwords)
 				RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
 				RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
 				RB_ALPHA_REF: 0
 0110b030:			0000: c0032d00 0004010c 00000000 00000000 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
+			opcode: CP_SET_CONSTANT (2d) (4 dwords)
 				PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
 				PA_SU_SC_MODE_CNTL: { POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST }
 0110b044:			0000: c0022d00 00040204 00000000 00090240
-t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
+			opcode: CP_SET_CONSTANT (2d) (6 dwords)
 				PA_SU_POINT_SIZE: { HEIGHT = 0.500000 | WIDTH = 0.500000 }
 				PA_SU_POINT_MINMAX: { MIN = 0.500000 | MAX = 0.500000 }
 				PA_SU_LINE_CNTL: { WIDTH = 0.500000 }
 				PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER }
 0110b054:			0000: c0042d00 00040280 00080008 00080008 00000008 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (7 dwords)
+			opcode: CP_SET_CONSTANT (2d) (7 dwords)
 				PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH }
 				PA_CL_GB_VERT_CLIP_ADJ: 1.000000
 				PA_CL_GB_VERT_DISC_ADJ: 1.000000
 				PA_CL_GB_HORZ_CLIP_ADJ: 1.000000
 				PA_CL_GB_HORZ_DISC_ADJ: 1.000000
 0110b06c:			0000: c0052d00 00040302 00000001 3f800000 3f800000 3f800000 3f800000
-t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
+			opcode: CP_SET_CONSTANT (2d) (4 dwords)
 				PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
 				PA_SC_WINDOW_SCISSOR_BR: { X = 256 | Y = 256 }
 0110b088:			0000: c0022d00 00040081 00000000 01000100
-t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
+			opcode: CP_SET_CONSTANT (2d) (8 dwords)
 				PA_CL_VPORT_XSCALE: 128.000000
 				PA_CL_VPORT_XOFFSET: 128.000000
 				PA_CL_VPORT_YSCALE: -128.000000
@@ -7355,11 +7355,11 @@ t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
 				PA_CL_VPORT_ZSCALE: 0.500000
 				PA_CL_VPORT_ZOFFSET: 0.500000
 0110b098:			0000: c0062d00 0004010f 43000000 43000000 c3000000 43000000 3f000000 3f000000
-t3			opcode: CP_SET_CONSTANT (2d) (10 dwords)
+			opcode: CP_SET_CONSTANT (2d) (10 dwords)
 0110b0c0:				128.000000 128.000000 0.500000 0.000000 128.000000 -128.000000 0.500000 0.000000
 0110b0b8:			0000: c0082d00 00000184 43000000 43000000 3f000000 00000000 43000000 c3000000
 0110b0d8:			0020: 3f000000 00000000
-t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords)
+			opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords)
 			vertex shader, start=0000, size=0015
 					    2003 0007 1000            	EXEC ADDR(0x3) CNT(0x2)
 					03: 19481000 00262688 00000010	   (S)FETCH:	VERTEX	R1.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(16) CONST(20, 0)
@@ -7374,7 +7374,7 @@ t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords)
 0110b0e0:			0000: c0162b00 00000000 00000015 00072003 00001000 c2000000 00021005 00001000
 0110b100:			0020: c4000000 00001006 00002000 00000000 19481000 00262688 00000010 13480000
 0110b120:			0040: 40252fc8 00000008 000f803e 00000000 c2010100 00038000 00000000 c2000000
-t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
+			opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
 			fragment shader, start=0000, size=000c
 					    1002 0003 1000            	EXEC ADDR(0x2) CNT(0x1)
 					02: 90000001 1ffff688 00000002	   (S)FETCH:	SAMPLE	R0.xyzw = R0.xyz CONST(0) LOCATION(CENTER)
@@ -7384,31 +7384,31 @@ t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
 					    0000 0000 0000            	NOP
 0110b140:			0000: c00d2b00 00000001 0000000c 00031002 00001000 c4000000 00021003 00002000
 0110b160:			0020: 00000000 90000001 1ffff688 00000002 000f8000 00000000 c2000000
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 }
 0110b17c:			0000: c0012d00 00040181 00000106
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
 0110b188:			0000: c0012d00 00040180 10030002
-t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
+			opcode: CP_SET_CONSTANT (2d) (6 dwords)
 0110b19c:				0.000000 0.000000 0.000000 0.000000
 0110b194:			0000: c0042d00 00000080 00000000 00000000 00000000 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_ALWAYS | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
 0110b1ac:			0000: c0012d00 00040202 00001c20
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
 0110b1b8:			0000: c0012d00 00040201 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 0110b1c4:			0000: c0012d00 00040104 0000000f
-t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
+			opcode: CP_SET_CONSTANT (2d) (6 dwords)
 				RB_BLEND_RED: 0
 				RB_BLEND_GREEN: 0
 				RB_BLEND_BLUE: 0
 				RB_BLEND_ALPHA: 0
 0110b1d0:			0000: c0042d00 00040105 00000000 00000000 00000000 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
+			opcode: CP_SET_CONSTANT (2d) (8 dwords)
 			set texture const 0000
 				clamp x/y/z: clamp-last-texel/clamp-last-texel/wrap
 				filter min/mag: point/point
@@ -7416,23 +7416,23 @@ t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
 				addr=01230000 (flags=820), size=64x128, pitch=16448, format=FMT_1_REVERSE
 				mipaddr=01240000 (flags=200)
 0110b1e8:			0000: c0062d00 00010000 80804800 01230820 000fe03f 00000d11 000001c0 01240200
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				VGT_INDX_OFFSET: 0
 0110b208:			0000: c0012d00 00040102 00000000
-t0			write TC_CNTL_STATUS (0e00)
+			write TC_CNTL_STATUS (0e00)
 				TC_CNTL_STATUS: { L2_INVALIDATE }
 0110b214:			0000: 00000e00 00000001
-t3			opcode: CP_WAIT_REG_EQ (52) (5 dwords)
+			opcode: CP_WAIT_REG_EQ (52) (5 dwords)
 0110b21c:			0000: c0035200 000005d0 00000000 00001000 00000001
-t3			opcode: CP_DRAW_INDX_BIN (34) (7 dwords)
+			opcode: CP_DRAW_INDX_BIN (34) (7 dwords)
 0110b230:			0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 127
 				:0,0,131,127
 0110b24c:			0000: 0000057f 0000007f
-t3			opcode: CP_NOP (10) (2 dwords)
+			opcode: CP_NOP (10) (2 dwords)
 0110b254:			0000: c0001000 00000000
-t3			opcode: CP_DRAW_INDX (22) (5 dwords)
+			opcode: CP_DRAW_INDX (22) (5 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x60000 }
 				{ NUM_INDICES = 18012304 }
@@ -7510,220 +7510,220 @@ t3			opcode: CP_DRAW_INDX (22) (5 dwords)
  +	0003c000			RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
  +	ffffffff			RB_COLOR_DEST_MASK: 0xffffffff
 0110b25c:			0000: c0032200 00000000 00060004 0112d890 0000000c
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 128
 				:0,0,131,128
 0110b270:			0000: 0000057f 00000080
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 0110b278:			0000: c0002600 00000000
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0110b280:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0110b288:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0110b290:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0110b298:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0110b2a0:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0110b2a8:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0110b2b0:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0110b2b8:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0110b2c0:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0110b2c8:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0110b2d0:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0110b2d8:			0000: c0004600 00000006
 0110a1d8:		0000: c0013700 0110b000 000000b8
-t2		nop
+		nop
 ############################################################
 vertices: 0
 cmd: deqp-gles2/185: fence=1268
 ############################################################
 cmdstream[18]: 124 dwords
-t0		write RB_BC_CONTROL (0f01)
+		write RB_BC_CONTROL (0f01)
 			RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 }
 0122f000:		0000: 00000f01 1c004046
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 }
 0122f008:		0000: c0012d00 00040293 00000020
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
 0122f014:		0000: c0012d00 00040316 00000002
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 }
 0122f020:		0000: c0012d00 00040317 00000002
-t0		write CP_PERFMON_CNTL (0444)
+		write CP_PERFMON_CNTL (0444)
 			CP_PERFMON_CNTL: 0
 0122f02c:		0000: 00000444 00000000
-t0		write RBBM_PM_OVERRIDE1 (039c)
+		write RBBM_PM_OVERRIDE1 (039c)
 			RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
 			RBBM_PM_OVERRIDE2: 0xfff
 0122f034:		0000: 0001039c ffffffff 00000fff
-t0		write TP0_CHICKEN (0e1e)
+		write TP0_CHICKEN (0e1e)
 			TP0_CHICKEN: 0x2
 0122f040:		0000: 00000e1e 00000002
-t3		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
+		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
 0122f048:		0000: c0003b00 00007fff
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			SQ_VS_CONST: { BASE = 32 | SIZE = 256 }
 0122f050:		0000: c0012d00 00040307 00100020
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			SQ_PS_CONST: { BASE = 288 | SIZE = 224 }
 0122f05c:		0000: c0012d00 00040308 000e0120
-t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
+		opcode: CP_SET_CONSTANT (2d) (4 dwords)
 			VGT_MAX_VTX_INDX: 0xffffffff
 			VGT_MIN_VTX_INDX: 0
 0122f068:		0000: c0022d00 00040100 ffffffff 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			VGT_INDX_OFFSET: 0
 0122f078:		0000: c0012d00 00040102 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			SQ_CONTEXT_MISC: { SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 }
 0122f084:		0000: c0012d00 00040181 00000004
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 }
 0122f090:		0000: c0012d00 00040182 ffffffff
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
 0122f09c:		0000: c0012d00 00040301 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_LINE_CNTL: { BRES_CNTL = 0 }
 0122f0a8:		0000: c0012d00 00040300 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
 0122f0b4:		0000: c0012d00 00040080 00000000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
 0122f0c0:		0000: c0012d00 00040208 00000004
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_SAMPLE_POS: 0x88888888
 0122f0cc:		0000: c0012d00 0004020a 88888888
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_COLOR_DEST_MASK: 0xffffffff
 0122f0d8:		0000: c0012d00 00040326 ffffffff
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 0122f0e4:		0000: c0012d00 0004031b 0003c000
-t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
+		opcode: CP_SET_CONSTANT (2d) (4 dwords)
 			SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 }
 			SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 }
 0122f0f0:		0000: c0022d00 00040183 00000000 00000000
-t3		opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords)
+		opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords)
 0122f100:		0000: c0004b00 00000000
-t3		opcode: CP_WAIT_REG_EQ (52) (5 dwords)
+		opcode: CP_WAIT_REG_EQ (52) (5 dwords)
 0122f108:		0000: c0035200 000005d0 00000000 5f601000 00000001
-t0		write SQ_INST_STORE_MANAGMENT (0d02)
+		write SQ_INST_STORE_MANAGMENT (0d02)
 			SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 }
 0122f11c:		0000: 00000d02 00000180
-t3		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
+		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
 0122f124:		0000: c0003b00 00000300
-t3		opcode: CP_SET_SHADER_BASES (4a) (2 dwords)
+		opcode: CP_SET_SHADER_BASES (4a) (2 dwords)
 0122f12c:		0000: c0004a00 80000180
-t3		opcode: CP_SET_CONSTANT (2d) (14 dwords)
+		opcode: CP_SET_CONSTANT (2d) (14 dwords)
 0122f13c:			0.000000 0.000000 0.000000 0.000000 20000.000000 1.000000 0.500000 0.000000
 0122f15c:			2.000000 0.750000 0.375000 0.250000
 0122f134:		0000: c00c2d00 00000000 00000000 00000000 00000000 00000000 469c4000 3f800000
 0122f154:		0020: 3f000000 00000000 40000000 3f400000 3ec00000 3e800000
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 0122f16c:		0000: c0012d00 00040104 0000000f
-t3		opcode: CP_SET_CONSTANT (2d) (6 dwords)
+		opcode: CP_SET_CONSTANT (2d) (6 dwords)
 			RB_BLEND_RED: 0
 			RB_BLEND_GREEN: 0
 			RB_BLEND_BLUE: 0
 			RB_BLEND_ALPHA: 0xff
 0122f178:		0000: c0042d00 00040105 00000000 00000000 00000000 000000ff
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT }
 0122f190:		0000: c0012d00 00040206 0000043f
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 }
 0122f19c:		0000: c0012d00 00040000 00000020
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | LINEAR | ENDIAN = 0 | SWAP = 1 | BASE = 0x1266000 }
 0122f1a8:		0000: c0012d00 00040001 01266245
-t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
+		opcode: CP_SET_CONSTANT (2d) (4 dwords)
 			PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 }
 			PA_SC_SCREEN_SCISSOR_BR: { X = 4 | Y = 8 }
 0122f1b4:		0000: c0022d00 0004000e 80000000 00080004
-t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
+		opcode: CP_SET_CONSTANT (2d) (3 dwords)
 			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
 0122f1c4:		0000: c0012d00 00040080 00000000
-t0		write CP_SCRATCH_REG6 (057e)
+		write CP_SCRATCH_REG6 (057e)
 			CP_SCRATCH_REG6: 137
 			:0,0,137,128
 0122f1d0:		0000: 0000057e 00000089
-t3		opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
+		opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
 		ibaddr:0122e000
 		ibsize:000000b6
-t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
+			opcode: CP_SET_CONSTANT (2d) (6 dwords)
 			set shader const 0078
 0122e000:			0000: c0042d00 00010078 0112d89f 00100000 0112d89f 00100000
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				PA_SC_AA_MASK: 0xffff
 0122e018:			0000: c0012d00 00040312 0000ffff
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
 0122e024:			0000: c0012d00 00040200 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (5 dwords)
+			opcode: CP_SET_CONSTANT (2d) (5 dwords)
 				RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
 				RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
 				RB_ALPHA_REF: 0
 0122e030:			0000: c0032d00 0004010c 00000000 00000000 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
+			opcode: CP_SET_CONSTANT (2d) (4 dwords)
 				PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
 				PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST }
 0122e044:			0000: c0022d00 00040204 00000000 00090244
-t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
+			opcode: CP_SET_CONSTANT (2d) (6 dwords)
 				PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 }
 				PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 }
 				PA_SU_LINE_CNTL: { WIDTH = 0.000000 }
 				PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER }
 0122e054:			0000: c0042d00 00040280 00000000 00000000 00000000 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (7 dwords)
+			opcode: CP_SET_CONSTANT (2d) (7 dwords)
 				PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH }
 				PA_CL_GB_VERT_CLIP_ADJ: 1.000000
 				PA_CL_GB_VERT_DISC_ADJ: 1.000000
 				PA_CL_GB_HORZ_CLIP_ADJ: 1.000000
 				PA_CL_GB_HORZ_DISC_ADJ: 1.000000
 0122e06c:			0000: c0052d00 00040302 00000001 3f800000 3f800000 3f800000 3f800000
-t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
+			opcode: CP_SET_CONSTANT (2d) (4 dwords)
 				PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
 				PA_SC_WINDOW_SCISSOR_BR: { X = 4 | Y = 8 }
 0122e088:			0000: c0022d00 00040081 00000000 00080004
-t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
+			opcode: CP_SET_CONSTANT (2d) (8 dwords)
 				PA_CL_VPORT_XSCALE: 2.000000
 				PA_CL_VPORT_XOFFSET: 2.000000
 				PA_CL_VPORT_YSCALE: 4.000000
@@ -7731,11 +7731,11 @@ t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
 				PA_CL_VPORT_ZSCALE: 0.000000
 				PA_CL_VPORT_ZOFFSET: 0.000000
 0122e098:			0000: c0062d00 0004010f 40000000 40000000 40800000 40800000 00000000 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (10 dwords)
+			opcode: CP_SET_CONSTANT (2d) (10 dwords)
 0122e0c0:				2.000000 4.000000 0.000000 0.000000 2.000000 4.000000 0.000000 0.000000
 0122e0b8:			0000: c0082d00 00000184 40000000 40800000 00000000 00000000 40000000 40800000
 *
-t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords)
+			opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords)
 			vertex shader, start=0000, size=0015
 					    2003 0007 1000            	EXEC ADDR(0x3) CNT(0x2)
 					03: 19481000 00262688 00000020	   (S)FETCH:	VERTEX	R1.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) CONST(20, 0)
@@ -7750,7 +7750,7 @@ t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords)
 0122e0e0:			0000: c0162b00 00000000 00000015 00072003 00001000 c2000000 00021005 00001000
 0122e100:			0020: c4000000 00001006 00002000 00000000 19481000 00262688 00000020 13480000
 0122e120:			0040: 40262688 00001020 000f803e 00000000 c2010100 000f8000 00000000 c2000000
-t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
+			opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
 			fragment shader, start=0000, size=000c
 					    1002 0003 1000            	EXEC ADDR(0x2) CNT(0x1)
 					02: 90000001 1ffff688 00000002	   (S)FETCH:	SAMPLE	R0.xyzw = R0.xyz CONST(0) LOCATION(CENTER)
@@ -7760,31 +7760,31 @@ t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
 					    0000 0000 0000            	NOP
 0122e140:			0000: c00d2b00 00000001 0000000c 00031002 00001000 c4000000 00021003 00002000
 0122e160:			0020: 00000000 90000001 1ffff688 00000002 000f8000 00000000 c2000000
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 }
 0122e17c:			0000: c0012d00 00040181 00000106
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
 0122e188:			0000: c0012d00 00040180 10030002
-t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
+			opcode: CP_SET_CONSTANT (2d) (6 dwords)
 0122e19c:				0.000000 0.000000 0.000000 0.000000
 0122e194:			0000: c0042d00 00000080 00000000 00000000 00000000 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
 0122e1ac:			0000: c0012d00 00040202 00000c20
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
 0122e1b8:			0000: c0012d00 00040201 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 0122e1c4:			0000: c0012d00 00040104 0000000f
-t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
+			opcode: CP_SET_CONSTANT (2d) (6 dwords)
 				RB_BLEND_RED: 0
 				RB_BLEND_GREEN: 0
 				RB_BLEND_BLUE: 0
 				RB_BLEND_ALPHA: 0
 0122e1d0:			0000: c0042d00 00040105 00000000 00000000 00000000 00000000
-t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
+			opcode: CP_SET_CONSTANT (2d) (8 dwords)
 			set texture const 0000
 				clamp x/y/z: clamp-last-texel/clamp-last-texel/clamp-last-texel
 				filter min/mag: point/point
@@ -7792,23 +7792,23 @@ t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
 				addr=0108a000 (flags=806), size=256x256, pitch=16640, format=FMT_8_8_8_8
 				mipaddr=00000000 (flags=200)
 0122e1e8:			0000: c0062d00 00010000 82024800 0108a806 001fe0ff 00000c14 00000000 00000200
-t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
+			opcode: CP_SET_CONSTANT (2d) (3 dwords)
 				VGT_INDX_OFFSET: 0
 0122e208:			0000: c0012d00 00040102 00000000
-t0			write TC_CNTL_STATUS (0e00)
+			write TC_CNTL_STATUS (0e00)
 				TC_CNTL_STATUS: { L2_INVALIDATE }
 0122e214:			0000: 00000e00 00000001
-t3			opcode: CP_WAIT_REG_EQ (52) (5 dwords)
+			opcode: CP_WAIT_REG_EQ (52) (5 dwords)
 0122e21c:			0000: c0035200 000005d0 00000000 00001000 00000001
-t3			opcode: CP_DRAW_INDX_BIN (34) (7 dwords)
+			opcode: CP_DRAW_INDX_BIN (34) (7 dwords)
 0122e230:			0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 133
 				:0,0,137,133
 0122e24c:			0000: 0000057f 00000085
-t3			opcode: CP_NOP (10) (2 dwords)
+			opcode: CP_NOP (10) (2 dwords)
 0122e254:			0000: c0001000 00000000
-t3			opcode: CP_DRAW_INDX (22) (3 dwords)
+			opcode: CP_DRAW_INDX (22) (3 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRIFAN | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x40000 }
 			draw:          0
@@ -7884,62 +7884,62 @@ t3			opcode: CP_DRAW_INDX (22) (3 dwords)
  +	0003c000			RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
  +	ffffffff			RB_COLOR_DEST_MASK: 0xffffffff
 0122e25c:			0000: c0012200 00000000 00040085
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 134
 				:0,0,137,134
 0122e268:			0000: 0000057f 00000086
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 0122e270:			0000: c0002600 00000000
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e278:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e280:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e288:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e290:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e298:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2a0:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2a8:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2b0:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2b8:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2c0:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2c8:			0000: c0004600 00000006
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = CACHE_FLUSH }
 			event CACHE_FLUSH
 0122e2d0:			0000: c0004600 00000006
 0122f1d8:		0000: c0013700 0122e000 000000b6
-t2		nop
+		nop
 ############################################################
 vertices: 0
diff --git a/src/freedreno/.gitlab-ci/reference/dEQP-VK.draw.indirect_draw.indexed.indirect_draw_count.triangle_list.log b/src/freedreno/.gitlab-ci/reference/dEQP-VK.draw.indirect_draw.indexed.indirect_draw_count.triangle_list.log
index b3ca7d2ed2a..33eef780071 100644
--- a/src/freedreno/.gitlab-ci/reference/dEQP-VK.draw.indirect_draw.indexed.indirect_draw_count.triangle_list.log
+++ b/src/freedreno/.gitlab-ci/reference/dEQP-VK.draw.indirect_draw.indexed.indirect_draw_count.triangle_list.log
@@ -1,277 +1,277 @@
 gpu_id: 640
 cmd: deqp-vk/74711: fence=247337
 ############################################################
-cmdstream: 265 dwords
-t7		opcode: CP_EVENT_WRITE (46) (2 dwords)
+cmdstream[0]: 265 dwords
+		opcode: CP_EVENT_WRITE (46) (2 dwords)
 			{ EVENT = CACHE_INVALIDATE }
 		event CACHE_INVALIDATE
 0000000001058000:		0000: 70460001 00000031
-t4		write HLSQ_INVALIDATE_CMD (bb08)
+		write HLSQ_INVALIDATE_CMD (bb08)
 			HLSQ_INVALIDATE_CMD: { VS_STATE | HS_STATE | DS_STATE | GS_STATE | FS_STATE | CS_STATE | CS_IBO | GFX_IBO | CS_SHARED_CONST | GFX_SHARED_CONST | CS_BINDLESS = 0x1f | GFX_BINDLESS = 0x1f }
 0000000001058008:		0000: 40bb0801 000fffff
-t7		opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
+		opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
 0000000001058010:		0000: 70268000
-t4		write RB_CCU_CNTL (8e07)
+		write RB_CCU_CNTL (8e07)
 			RB_CCU_CNTL: { COLOR_OFFSET = 0x20000 | DEPTH_OFFSET = 0 }
 0000000001058014:		0000: 408e0701 10000000
-t4		write RB_DBG_ECO_CNTL (8e04)
+		write RB_DBG_ECO_CNTL (8e04)
 			RB_DBG_ECO_CNTL: 0x100000
 000000000105801c:		0000: 408e0401 00100000
-t4		write SP_FLOAT_CNTL (ae04)
+		write SP_FLOAT_CNTL (ae04)
 			SP_FLOAT_CNTL: { F16_NO_INF }
 0000000001058024:		0000: 48ae0401 00000008
-t4		write SP_DBG_ECO_CNTL (ae00)
+		write SP_DBG_ECO_CNTL (ae00)
 			SP_DBG_ECO_CNTL: 0
 000000000105802c:		0000: 40ae0001 00000000
-t4		write SP_PERFCTR_ENABLE (ae0f)
+		write SP_PERFCTR_ENABLE (ae0f)
 			SP_PERFCTR_ENABLE: { VS | HS | DS | GS | FS | CS }
 0000000001058034:		0000: 40ae0f01 0000003f
-t4		write TPL1_UNKNOWN_B605 (b605)
+		write TPL1_UNKNOWN_B605 (b605)
 			TPL1_UNKNOWN_B605: 68
 000000000105803c:		0000: 40b60501 00000044
-t4		write TPL1_DBG_ECO_CNTL (b600)
+		write TPL1_DBG_ECO_CNTL (b600)
 			TPL1_DBG_ECO_CNTL: 0x100000
 0000000001058044:		0000: 40b60001 00100000
-t4		write HLSQ_UNKNOWN_BE00 (be00)
+		write HLSQ_UNKNOWN_BE00 (be00)
 			HLSQ_UNKNOWN_BE00: 0x80
 000000000105804c:		0000: 48be0001 00000080
-t4		write HLSQ_UNKNOWN_BE01 (be01)
+		write HLSQ_UNKNOWN_BE01 (be01)
 			HLSQ_UNKNOWN_BE01: 0
 0000000001058054:		0000: 40be0101 00000000
-t4		write VPC_DBG_ECO_CNTL (9600)
+		write VPC_DBG_ECO_CNTL (9600)
 			VPC_DBG_ECO_CNTL: 0
 000000000105805c:		0000: 48960001 00000000
-t4		write GRAS_DBG_ECO_CNTL (8600)
+		write GRAS_DBG_ECO_CNTL (8600)
 			GRAS_DBG_ECO_CNTL: { UNK7 | LRZCACHELOCKDIS }
 0000000001058064:		0000: 40860001 00000880
-t4		write HLSQ_DBG_ECO_CNTL (be04)
+		write HLSQ_DBG_ECO_CNTL (be04)
 			HLSQ_DBG_ECO_CNTL: 0
 000000000105806c:		0000: 40be0401 00000000
-t4		write SP_CHICKEN_BITS (ae03)
+		write SP_CHICKEN_BITS (ae03)
 			SP_CHICKEN_BITS: 0x410
 0000000001058074:		0000: 40ae0301 00000410
-t4		write SP_IBO_COUNT (ab20)
+		write SP_IBO_COUNT (ab20)
 			SP_IBO_COUNT: 0
 000000000105807c:		0000: 48ab2001 00000000
-t4		write SP_UNKNOWN_B182 (b182)
+		write SP_UNKNOWN_B182 (b182)
 			SP_UNKNOWN_B182: 0
 0000000001058084:		0000: 48b18201 00000000
-t4		write HLSQ_SHARED_CONSTS (bb11)
+		write HLSQ_SHARED_CONSTS (bb11)
 			HLSQ_SHARED_CONSTS: { 0 }
 000000000105808c:		0000: 48bb1101 00000000
-t4		write UCHE_UNKNOWN_0E12 (0e12)
+		write UCHE_UNKNOWN_0E12 (0e12)
 			UCHE_UNKNOWN_0E12: 0x3200000
 0000000001058094:		0000: 400e1201 03200000
-t4		write UCHE_CLIENT_PF (0e19)
+		write UCHE_CLIENT_PF (0e19)
 			UCHE_CLIENT_PF: { PERFSEL = 0x4 }
 000000000105809c:		0000: 480e1901 00000004
-t4		write RB_UNKNOWN_8E01 (8e01)
+		write RB_UNKNOWN_8E01 (8e01)
 			RB_UNKNOWN_8E01: 0
 00000000010580a4:		0000: 408e0101 00000000
-t4		write SP_FS_OBJ_FIRST_EXEC_OFFSET (a982)
+		write SP_FS_OBJ_FIRST_EXEC_OFFSET (a982)
 			SP_FS_OBJ_FIRST_EXEC_OFFSET: 0
 00000000010580ac:		0000: 48a98201 00000000
-t4		write SP_UNKNOWN_A9A8 (a9a8)
+		write SP_UNKNOWN_A9A8 (a9a8)
 			SP_UNKNOWN_A9A8: 0
 00000000010580b4:		0000: 40a9a801 00000000
-t4		write SP_MODE_CONTROL (ab00)
+		write SP_MODE_CONTROL (ab00)
 			SP_MODE_CONTROL: { CONSTANT_DEMOTION_ENABLE | ISAMMODE = ISAMMODE_GL }
 00000000010580bc:		0000: 40ab0001 00000005
-t4		write VFD_ADD_OFFSET (a009)
+		write VFD_ADD_OFFSET (a009)
 			VFD_ADD_OFFSET: { VERTEX }
 00000000010580c4:		0000: 48a00901 00000001
-t4		write RB_UNKNOWN_8811 (8811)
+		write RB_UNKNOWN_8811 (8811)
 			RB_UNKNOWN_8811: 0x1
 00000000010580cc:		0000: 48881101 00000010
-t4		write PC_MODE_CNTL (9804)
+		write PC_MODE_CNTL (9804)
 			PC_MODE_CNTL: 0x1f
 00000000010580d4:		0000: 48980401 0000001f
-t4		write RB_SRGB_CNTL (880f)
+		write RB_SRGB_CNTL (880f)
 			RB_SRGB_CNTL: { 0 }
 00000000010580dc:		0000: 48880f01 00000000
-t4		write GRAS_UNKNOWN_8110 (8110)
+		write GRAS_UNKNOWN_8110 (8110)
 			GRAS_UNKNOWN_8110: 0
 00000000010580e4:		0000: 40811001 00000000
-t4		write RB_RENDER_CONTROL0 (8809)
+		write RB_RENDER_CONTROL0 (8809)
 			RB_RENDER_CONTROL0: { IJ_PERSP_PIXEL | COORD_MASK = 0 | UNK10 }
 00000000010580ec:		0000: 48880901 00000401
-t4		write RB_RENDER_CONTROL1 (880a)
+		write RB_RENDER_CONTROL1 (880a)
 			RB_RENDER_CONTROL1: { FRAGCOORDSAMPLEMODE = FRAGCOORD_CENTER }
 00000000010580f4:		0000: 48880a01 00000000
-t4		write RB_FS_OUTPUT_CNTL0 (880b)
+		write RB_FS_OUTPUT_CNTL0 (880b)
 			RB_FS_OUTPUT_CNTL0: { 0 }
 00000000010580fc:		0000: 40880b01 00000000
-t4		write RB_UNKNOWN_8818 (8818)
+		write RB_UNKNOWN_8818 (8818)
 			RB_UNKNOWN_8818: 0
 0000000001058104:		0000: 48881801 00000000
-t4		write RB_UNKNOWN_8819 (8819)
+		write RB_UNKNOWN_8819 (8819)
 			RB_UNKNOWN_8819: 0
 000000000105810c:		0000: 40881901 00000000
-t4		write RB_UNKNOWN_881A (881a)
+		write RB_UNKNOWN_881A (881a)
 			RB_UNKNOWN_881A: 0
 0000000001058114:		0000: 40881a01 00000000
-t4		write RB_UNKNOWN_881B (881b)
+		write RB_UNKNOWN_881B (881b)
 			RB_UNKNOWN_881B: 0
 000000000105811c:		0000: 48881b01 00000000
-t4		write RB_UNKNOWN_881C (881c)
+		write RB_UNKNOWN_881C (881c)
 			RB_UNKNOWN_881C: 0
 0000000001058124:		0000: 40881c01 00000000
-t4		write RB_UNKNOWN_881D (881d)
+		write RB_UNKNOWN_881D (881d)
 			RB_UNKNOWN_881D: 0
 000000000105812c:		0000: 48881d01 00000000
-t4		write RB_UNKNOWN_881E (881e)
+		write RB_UNKNOWN_881E (881e)
 			RB_UNKNOWN_881E: 0
 0000000001058134:		0000: 48881e01 00000000
-t4		write RB_UNKNOWN_88F0 (88f0)
+		write RB_UNKNOWN_88F0 (88f0)
 			RB_UNKNOWN_88F0: 0
 000000000105813c:		0000: 4888f001 00000000
-t4		write VPC_UNKNOWN_9107 (9107)
+		write VPC_UNKNOWN_9107 (9107)
 			VPC_UNKNOWN_9107: { 0 }
 0000000001058144:		0000: 48910701 00000000
-t4		write VPC_POINT_COORD_INVERT (9236)
+		write VPC_POINT_COORD_INVERT (9236)
 			VPC_POINT_COORD_INVERT: { 0 }
 000000000105814c:		0000: 40923601 00000000
-t4		write VPC_UNKNOWN_9300 (9300)
+		write VPC_UNKNOWN_9300 (9300)
 			VPC_UNKNOWN_9300: 0
 0000000001058154:		0000: 48930001 00000000
-t4		write VPC_SO_DISABLE (9306)
+		write VPC_SO_DISABLE (9306)
 			VPC_SO_DISABLE: { DISABLE }
 000000000105815c:		0000: 48930601 00000001
-t4		write PC_RASTER_CNTL (9980)
+		write PC_RASTER_CNTL (9980)
 			PC_RASTER_CNTL: { STREAM = 0 }
 0000000001058164:		0000: 40998001 00000000
-t4		write PC_PRIMITIVE_CNTL_6 (9b06)
+		write PC_PRIMITIVE_CNTL_6 (9b06)
 			PC_PRIMITIVE_CNTL_6: { STRIDE_IN_VPC = 0 }
 000000000105816c:		0000: 409b0601 00000000
-t4		write PC_MULTIVIEW_CNTL (9b07)
+		write PC_MULTIVIEW_CNTL (9b07)
 			PC_MULTIVIEW_CNTL: { VIEWS = 0 }
 0000000001058174:		0000: 489b0701 00000000
-t4		write SP_VS_OBJ_FIRST_EXEC_OFFSET (a81b)
+		write SP_VS_OBJ_FIRST_EXEC_OFFSET (a81b)
 			SP_VS_OBJ_FIRST_EXEC_OFFSET: 0
 000000000105817c:		0000: 40a81b01 00000000
-t4		write SP_UNKNOWN_B183 (b183)
+		write SP_UNKNOWN_B183 (b183)
 			SP_UNKNOWN_B183: 0
 0000000001058184:		0000: 40b18301 00000000
-t4		write GRAS_SU_CONSERVATIVE_RAS_CNTL (8099)
+		write GRAS_SU_CONSERVATIVE_RAS_CNTL (8099)
 			GRAS_SU_CONSERVATIVE_RAS_CNTL: { SHIFTAMOUNT = 0 }
 000000000105818c:		0000: 40809901 00000000
-t4		write GRAS_SC_CNTL (80a0)
+		write GRAS_SC_CNTL (80a0)
 			GRAS_SC_CNTL: { CCUSINGLECACHELINESIZE = 0x2 | SINGLE_PRIM_MODE = NO_FLUSH | RASTER_MODE = TYPE_TILED | RASTER_DIRECTION = LR_TB | SEQUENCED_THREAD_DISTRIBUTION = DIST_SCREEN_COORD }
 0000000001058194:		0000: 4080a001 00000002
-t4		write GRAS_UNKNOWN_80AF (80af)
+		write GRAS_UNKNOWN_80AF (80af)
 			GRAS_UNKNOWN_80AF: FALSE
 000000000105819c:		0000: 4080af01 00000000
-t4		write VPC_UNKNOWN_9210 (9210)
+		write VPC_UNKNOWN_9210 (9210)
 			VPC_UNKNOWN_9210: 0
 00000000010581a4:		0000: 48921001 00000000
-t4		write VPC_UNKNOWN_9211 (9211)
+		write VPC_UNKNOWN_9211 (9211)
 			VPC_UNKNOWN_9211: 0
 00000000010581ac:		0000: 40921101 00000000
-t4		write VPC_UNKNOWN_9602 (9602)
+		write VPC_UNKNOWN_9602 (9602)
 			VPC_UNKNOWN_9602: FALSE
 00000000010581b4:		0000: 40960201 00000000
-t4		write PC_UNKNOWN_9E72 (9e72)
+		write PC_UNKNOWN_9E72 (9e72)
 			PC_UNKNOWN_9E72: 0
 00000000010581bc:		0000: 409e7201 00000000
-t4		write SP_TP_MODE_CNTL (b309)
+		write SP_TP_MODE_CNTL (b309)
 			SP_TP_MODE_CNTL: { ISAMMODE = ISAMMODE_GL | UNK3 = 0x28 }
 00000000010581c4:		0000: 40b30901 000000a2
-t4		write HLSQ_CONTROL_5_REG (b986)
+		write HLSQ_CONTROL_5_REG (b986)
 			HLSQ_CONTROL_5_REG: { LINELENGTHREGID = r63.x | FOVEATIONQUALITYREGID = r0.x }
 00000000010581cc:		0000: 48b98601 000000fc
-t4		write VFD_MODE_CNTL (a007)
+		write VFD_MODE_CNTL (a007)
 			VFD_MODE_CNTL: { RENDER_MODE = RENDERING_PASS }
 00000000010581d4:		0000: 40a00701 00000000
-t4		write VFD_MULTIVIEW_CNTL (a008)
+		write VFD_MULTIVIEW_CNTL (a008)
 			VFD_MULTIVIEW_CNTL: { VIEWS = 0 }
 00000000010581dc:		0000: 40a00801 00000000
-t4		write PC_MODE_CNTL (9804)
+		write PC_MODE_CNTL (9804)
 			PC_MODE_CNTL: 0x1f
 00000000010581e4:		0000: 48980401 0000001f
-t7		opcode: CP_SET_DRAW_STATE (43) (4 dwords)
+		opcode: CP_SET_DRAW_STATE (43) (4 dwords)
 			{ COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 }
 			{ ADDR_LO = 0 }
 			{ ADDR_HI = 0 }
 00000000010581ec:		0000: 70438003 00040000 00000000 00000000
-t4		write SP_HS_CTRL_REG0 (a830)
+		write SP_HS_CTRL_REG0 (a830)
 			SP_HS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 0 | BRANCHSTACK = 0 }
 00000000010581fc:		0000: 40a83001 00000000
-t4		write SP_GS_CTRL_REG0 (a870)
+		write SP_GS_CTRL_REG0 (a870)
 			SP_GS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 0 | BRANCHSTACK = 0 }
 0000000001058204:		0000: 48a87001 00000000
-t4		write GRAS_LRZ_CNTL (8100)
+		write GRAS_LRZ_CNTL (8100)
 			GRAS_LRZ_CNTL: { DIR = 0 }
 000000000105820c:		0000: 48810001 00000000
-t4		write RB_LRZ_CNTL (8898)
+		write RB_LRZ_CNTL (8898)
 			RB_LRZ_CNTL: { 0 }
 0000000001058214:		0000: 40889801 00000000
-t4		write SP_TP_BORDER_COLOR_BASE_ADDR (b302)
+		write SP_TP_BORDER_COLOR_BASE_ADDR (b302)
 			SP_TP_BORDER_COLOR_BASE_ADDR: 0x1011000
 			SP_TP_BORDER_COLOR_BASE_ADDR_HI: 0
 000000000105821c:		0000: 48b30202 01011000 00000000
-t4		write SP_PS_TP_BORDER_COLOR_BASE_ADDR (b180)
+		write SP_PS_TP_BORDER_COLOR_BASE_ADDR (b180)
 			SP_PS_TP_BORDER_COLOR_BASE_ADDR: 0x1011000
 			SP_PS_TP_BORDER_COLOR_BASE_ADDR_HI: 0
 0000000001058228:		0000: 40b18002 01011000 00000000
-t4		write VSC_DRAW_STRM_SIZE_ADDRESS (0c03)
+		write VSC_DRAW_STRM_SIZE_ADDRESS (0c03)
 			VSC_DRAW_STRM_SIZE_ADDRESS: 0x10fd000
 			VSC_DRAW_STRM_SIZE_ADDRESS_HI: 0
 0000000001058234:		0000: 480c0302 010fd000 00000000
-t4		write VSC_PRIM_STRM_ADDRESS (0c30)
+		write VSC_PRIM_STRM_ADDRESS (0c30)
 			VSC_PRIM_STRM_ADDRESS: 0x105c000
 			VSC_PRIM_STRM_ADDRESS_HI: 0
 0000000001058240:		0000: 480c3002 0105c000 00000000
-t4		write VSC_DRAW_STRM_ADDRESS (0c34)
+		write VSC_DRAW_STRM_ADDRESS (0c34)
 			VSC_DRAW_STRM_ADDRESS: 0x10dc800
 			VSC_DRAW_STRM_ADDRESS_HI: 0
 000000000105824c:		0000: 400c3402 010dc800 00000000
-t7		opcode: CP_EVENT_WRITE (46) (5 dwords)
+		opcode: CP_EVENT_WRITE (46) (5 dwords)
 			{ EVENT = PC_CCU_FLUSH_COLOR_TS }
 			{ ADDR_0_LO = 0x1011880 }
 			{ ADDR_0_HI = 0 }
 			{ 3 = 0 }
 		event PC_CCU_FLUSH_COLOR_TS
 0000000001058258:		0000: 70460004 0000001d 01011880 00000000 00000000
-t7		opcode: CP_EVENT_WRITE (46) (2 dwords)
+		opcode: CP_EVENT_WRITE (46) (2 dwords)
 			{ EVENT = PC_CCU_INVALIDATE_COLOR }
 		event PC_CCU_INVALIDATE_COLOR
 000000000105826c:		0000: 70460001 00000019
-t7		opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
+		opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
 0000000001058274:		0000: 70268000
-t4		write RB_2D_UNKNOWN_8C01 (8c01)
+		write RB_2D_UNKNOWN_8C01 (8c01)
 			RB_2D_UNKNOWN_8C01: 0
 0000000001058278:		0000: 488c0101 00000000
-t4		write RB_2D_BLIT_CNTL (8c00)
+		write RB_2D_BLIT_CNTL (8c00)
 			RB_2D_BLIT_CNTL: { ROTATE = ROTATE_0 | SOLID_COLOR | COLOR_FORMAT = FMT6_8_8_8_8_UNORM | MASK = 0xf | IFMT = R2D_UNORM8 | RASTER_MODE = TYPE_TILED }
 0000000001058280:		0000: 408c0001 10f03080
-t4		write GRAS_2D_BLIT_CNTL (8400)
+		write GRAS_2D_BLIT_CNTL (8400)
 			GRAS_2D_BLIT_CNTL: { ROTATE = ROTATE_0 | SOLID_COLOR | COLOR_FORMAT = FMT6_8_8_8_8_UNORM | MASK = 0xf | IFMT = R2D_UNORM8 | RASTER_MODE = TYPE_TILED }
 0000000001058288:		0000: 48840001 10f03080
-t4		write SP_2D_DST_FORMAT (acc0)
+		write SP_2D_DST_FORMAT (acc0)
 			SP_2D_DST_FORMAT: { COLOR_FORMAT = FMT6_8_8_8_8_UNORM | MASK = 0xf }
 0000000001058290:		0000: 48acc001 0000f180
-t4		write RB_2D_SRC_SOLID_C0 (8c2c)
+		write RB_2D_SRC_SOLID_C0 (8c2c)
 			RB_2D_SRC_SOLID_C0: 0
 			RB_2D_SRC_SOLID_C1: 0
 			RB_2D_SRC_SOLID_C2: 0
 			RB_2D_SRC_SOLID_C3: 0xff
 0000000001058298:		0000: 488c2c04 00000000 00000000 00000000 000000ff
-t4		write GRAS_2D_DST_TL (8405)
+		write GRAS_2D_DST_TL (8405)
 			GRAS_2D_DST_TL: { X = 0 | Y = 0 }
 			GRAS_2D_DST_BR: { X = 255 | Y = 255 }
 00000000010582ac:		0000: 48840502 00000000 00ff00ff
-t4		write RB_2D_DST_INFO (8c17)
+		write RB_2D_DST_INFO (8c17)
 			RB_2D_DST_INFO: { COLOR_FORMAT = FMT6_8_8_8_8_UNORM | TILE_MODE = TILE6_3 | COLOR_SWAP = WZYX | FLAGS | SAMPLES = MSAA_ONE }
 			RB_2D_DST: 0x1013000
 			RB_2D_DST_HI: 0
 			RB_2D_DST_PITCH: 1024
 00000000010582b8:		0000: 408c1704 00001330 01013000 00000000 00000010
-t4		write RB_2D_DST_FLAGS (8c20)
+		write RB_2D_DST_FLAGS (8c20)
 			RB_2D_DST_FLAGS: 0x1012000
 			RB_2D_DST_FLAGS_HI: 0
 			RB_2D_DST_FLAGS_PITCH: 64 | 0x4000
 00000000010582cc:		0000: 488c2083 01012000 00000000 00004001
-t7		opcode: CP_BLIT (2c) (2 dwords)
+		opcode: CP_BLIT (2c) (2 dwords)
 			{ OP = BLIT_OP_SCALE }
 		mode: (null)
 		skip_ib2: g=0, l=0
@@ -367,116 +367,116 @@ t7		opcode: CP_BLIT (2c) (2 dwords)
  +	00000000		HLSQ_UNKNOWN_BE01: 0
  +	00000000		HLSQ_DBG_ECO_CNTL: 0
 00000000010582dc:		0000: 702c0001 00000003
-t7		opcode: CP_EVENT_WRITE (46) (2 dwords)
+		opcode: CP_EVENT_WRITE (46) (2 dwords)
 			{ EVENT = LRZ_FLUSH }
 		event LRZ_FLUSH
 00000000010582e4:		0000: 70460001 00000026
-t7		opcode: CP_SKIP_IB2_ENABLE_GLOBAL (1d) (2 dwords)
+		opcode: CP_SKIP_IB2_ENABLE_GLOBAL (1d) (2 dwords)
 00000000010582ec:		0000: 709d0001 00000000
-t7		opcode: CP_EVENT_WRITE (46) (5 dwords)
+		opcode: CP_EVENT_WRITE (46) (5 dwords)
 			{ EVENT = PC_CCU_FLUSH_COLOR_TS }
 			{ ADDR_0_LO = 0x1011880 }
 			{ ADDR_0_HI = 0 }
 			{ 3 = 0 }
 		event PC_CCU_FLUSH_COLOR_TS
 00000000010582f4:		0000: 70460004 0000001d 01011880 00000000 00000000
-t7		opcode: CP_EVENT_WRITE (46) (5 dwords)
+		opcode: CP_EVENT_WRITE (46) (5 dwords)
 			{ EVENT = PC_CCU_FLUSH_DEPTH_TS }
 			{ ADDR_0_LO = 0x1011880 }
 			{ ADDR_0_HI = 0 }
 			{ 3 = 0 }
 		event PC_CCU_FLUSH_DEPTH_TS
 0000000001058308:		0000: 70460004 0000001c 01011880 00000000 00000000
-t7		opcode: CP_EVENT_WRITE (46) (2 dwords)
+		opcode: CP_EVENT_WRITE (46) (2 dwords)
 			{ EVENT = PC_CCU_INVALIDATE_COLOR }
 		event PC_CCU_INVALIDATE_COLOR
 000000000105831c:		0000: 70460001 00000019
-t7		opcode: CP_EVENT_WRITE (46) (2 dwords)
+		opcode: CP_EVENT_WRITE (46) (2 dwords)
 			{ EVENT = PC_CCU_INVALIDATE_DEPTH }
 		event PC_CCU_INVALIDATE_DEPTH
 0000000001058324:		0000: 70460001 00000018
-t7		opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
+		opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
 000000000105832c:		0000: 70268000
-t4		write RB_CCU_CNTL (8e07)
+		write RB_CCU_CNTL (8e07)
 			RB_CCU_CNTL: { COLOR_OFFSET = 0xf8000 | DEPTH_OFFSET = 0 | GMEM }
 0000000001058330:		0000: 408e0701 7c400000
-t4		write VPC_SO_DISABLE (9306)
+		write VPC_SO_DISABLE (9306)
 			VPC_SO_DISABLE: { 0 }
 0000000001058338:		0000: 48930601 00000000
-t4		write GRAS_BIN_CONTROL (80a1)
+		write GRAS_BIN_CONTROL (80a1)
 			GRAS_BIN_CONTROL: { BINW = 256 | BINH = 256 | RENDER_MODE = RENDERING_PASS | BUFFERS_LOCATION = BUFFERS_IN_GMEM | LRZ_FEEDBACK_ZMODE_MASK = 0x6 }
 0000000001058340:		0000: 4880a101 06001008
-t4		write RB_BIN_CONTROL (8800)
+		write RB_BIN_CONTROL (8800)
 			RB_BIN_CONTROL: { BINW = 256 | BINH = 256 | RENDER_MODE = RENDERING_PASS | BUFFERS_LOCATION = BUFFERS_IN_GMEM | LRZ_FEEDBACK_ZMODE_MASK = 0x6 }
 0000000001058348:		0000: 48880001 06001008
-t4		write RB_BIN_CONTROL2 (88d3)
+		write RB_BIN_CONTROL2 (88d3)
 			RB_BIN_CONTROL2: { BINW = 256 | BINH = 256 }
 0000000001058350:		0000: 4088d301 00001008
-t7		opcode: CP_SET_MARKER (65) (2 dwords)
+		opcode: CP_SET_MARKER (65) (2 dwords)
 			{ MODE = RM6_YIELD | MARKER = RM6_YIELD }
 0000000001058358:		0000: 70e50001 00000007
-t7		opcode: CP_SET_MARKER (65) (2 dwords)
+		opcode: CP_SET_MARKER (65) (2 dwords)
 			{ MODE = RM6_GMEM | MARKER = RM6_GMEM }
 0000000001058360:		0000: 70e50001 00000004
-t4		write GRAS_SC_WINDOW_SCISSOR_TL (80f0)
+		write GRAS_SC_WINDOW_SCISSOR_TL (80f0)
 			GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
 			GRAS_SC_WINDOW_SCISSOR_BR: { X = 255 | Y = 255 }
 0000000001058368:		0000: 4080f002 00000000 00ff00ff
-t4		write GRAS_2D_RESOLVE_CNTL_1 (840a)
+		write GRAS_2D_RESOLVE_CNTL_1 (840a)
 			GRAS_2D_RESOLVE_CNTL_1: { X = 0 | Y = 0 }
 			GRAS_2D_RESOLVE_CNTL_2: { X = 255 | Y = 255 }
 0000000001058374:		0000: 48840a02 00000000 00ff00ff
-t4		write RB_WINDOW_OFFSET (8890)
+		write RB_WINDOW_OFFSET (8890)
 			RB_WINDOW_OFFSET: { X = 0 | Y = 0 }
 0000000001058380:		0000: 48889001 00000000
-t4		write RB_WINDOW_OFFSET2 (88d4)
+		write RB_WINDOW_OFFSET2 (88d4)
 			RB_WINDOW_OFFSET2: { X = 0 | Y = 0 }
 0000000001058388:		0000: 4888d401 00000000
-t4		write SP_WINDOW_OFFSET (b4d1)
+		write SP_WINDOW_OFFSET (b4d1)
 			SP_WINDOW_OFFSET: { X = 0 | Y = 0 }
 0000000001058390:		0000: 48b4d101 00000000
-t4		write SP_TP_WINDOW_OFFSET (b307)
+		write SP_TP_WINDOW_OFFSET (b307)
 			SP_TP_WINDOW_OFFSET: { X = 0 | Y = 0 }
 0000000001058398:		0000: 48b30701 00000000
-t4		write VPC_SO_DISABLE (9306)
+		write VPC_SO_DISABLE (9306)
 			VPC_SO_DISABLE: { 0 }
 00000000010583a0:		0000: 48930601 00000000
-t7		opcode: CP_SET_VISIBILITY_OVERRIDE (64) (2 dwords)
+		opcode: CP_SET_VISIBILITY_OVERRIDE (64) (2 dwords)
 00000000010583a8:		0000: 70640001 00000001
-t7		opcode: CP_SET_MODE (63) (2 dwords)
+		opcode: CP_SET_MODE (63) (2 dwords)
 00000000010583b0:		0000: 70e30001 00000000
-t7		opcode: CP_INDIRECT_BUFFER (3f) (4 dwords)
+		opcode: CP_INDIRECT_BUFFER (3f) (4 dwords)
 		ibaddr:000000000115e000
 		ibsize:000000f1
-t7			opcode: CP_COND_REG_EXEC (47) (3 dwords)
+			opcode: CP_COND_REG_EXEC (47) (3 dwords)
 				{ REG0 = 0 | GMEM | MODE = RENDER_MODE }
 				{ DWORDS = 23 }
 000000000115e000:			0000: 70c70002 34000000 00000017
-t4			write RB_BLIT_SCISSOR_TL (88d1)
+			write RB_BLIT_SCISSOR_TL (88d1)
 				RB_BLIT_SCISSOR_TL: { X = 0 | Y = 0 }
 				RB_BLIT_SCISSOR_BR: { X = 255 | Y = 255 }
 000000000115e00c:			0000: 4888d102 00000000 00ff00ff
-t4			write RB_BLIT_GMEM_MSAA_CNTL (88d5)
+			write RB_BLIT_GMEM_MSAA_CNTL (88d5)
 				RB_BLIT_GMEM_MSAA_CNTL: { SAMPLES = MSAA_ONE }
 000000000115e018:			0000: 4088d501 00000000
-t4			write RB_BLIT_INFO (88e3)
+			write RB_BLIT_INFO (88e3)
 				RB_BLIT_INFO: { UNK0 | GMEM | CLEAR_MASK = 0 | LAST = 0 | BUFFER_ID = 0 }
 000000000115e020:			0000: 4088e301 00000003
-t4			write RB_BLIT_DST_INFO (88d7)
+			write RB_BLIT_DST_INFO (88d7)
 				RB_BLIT_DST_INFO: { TILE_MODE = TILE6_3 | FLAGS | SAMPLES = MSAA_ONE | COLOR_SWAP = WZYX | COLOR_FORMAT = FMT6_8_8_8_8_UNORM }
 				RB_BLIT_DST: 0x1013000
 				RB_BLIT_DST_HI: 0
 				RB_BLIT_DST_PITCH: 1024
 000000000115e028:			0000: 4888d704 00001807 01013000 00000000 00000010
-t4			write RB_BLIT_FLAG_DST (88dc)
+			write RB_BLIT_FLAG_DST (88dc)
 				RB_BLIT_FLAG_DST: 0x1012000
 				RB_BLIT_FLAG_DST_HI: 0
 				RB_BLIT_FLAG_DST_PITCH: { PITCH = 64 | ARRAY_PITCH = 1024 }
 000000000115e03c:			0000: 4088dc83 01012000 00000000 00004001
-t4			write RB_BLIT_BASE_GMEM (88d6)
+			write RB_BLIT_BASE_GMEM (88d6)
 				RB_BLIT_BASE_GMEM: 0
 000000000115e04c:			0000: 4088d601 00000000
-t7			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = BLIT }
 			event BLIT
 			mode: RM6_GMEM
@@ -508,15 +508,15 @@ t7			opcode: CP_EVENT_WRITE (46) (2 dwords)
  +	00000000			SP_TP_WINDOW_OFFSET: { X = 0 | Y = 0 }
  +	00000000			SP_WINDOW_OFFSET: { X = 0 | Y = 0 }
 000000000115e054:			0000: 70460001 0000001e
-t4			write RB_BLIT_SCISSOR_TL (88d1)
+			write RB_BLIT_SCISSOR_TL (88d1)
 				RB_BLIT_SCISSOR_TL: { X = 0 | Y = 0 }
 				RB_BLIT_SCISSOR_BR: { X = 255 | Y = 255 }
 000000000115e05c:			0000: 4888d102 00000000 00ff00ff
-t7			opcode: CP_COND_REG_EXEC (47) (3 dwords)
+			opcode: CP_COND_REG_EXEC (47) (3 dwords)
 				{ REG0 = 0 | SYSMEM | MODE = RENDER_MODE }
 				{ DWORDS = 0 }
 000000000115e068:			0000: 70c70002 38000000 00000000
-t4			write RB_DEPTH_BUFFER_INFO (8872)
+			write RB_DEPTH_BUFFER_INFO (8872)
 				RB_DEPTH_BUFFER_INFO: { DEPTH_FORMAT = DEPTH6_NONE }
 				RB_DEPTH_BUFFER_PITCH: 0
 				RB_DEPTH_BUFFER_ARRAY_PITCH: 0
@@ -524,20 +524,20 @@ t4			write RB_DEPTH_BUFFER_INFO (8872)
 				RB_DEPTH_BUFFER_BASE_HI: 0
 				RB_DEPTH_BUFFER_BASE_GMEM: 0
 000000000115e074:			0000: 48887286 00000000 00000000 00000000 00000000 00000000 00000000
-t4			write GRAS_SU_DEPTH_BUFFER_INFO (8098)
+			write GRAS_SU_DEPTH_BUFFER_INFO (8098)
 				GRAS_SU_DEPTH_BUFFER_INFO: { DEPTH_FORMAT = DEPTH6_NONE }
 000000000115e090:			0000: 48809801 00000000
-t4			write GRAS_LRZ_BUFFER_BASE (8103)
+			write GRAS_LRZ_BUFFER_BASE (8103)
 				GRAS_LRZ_BUFFER_BASE: 0
 				GRAS_LRZ_BUFFER_BASE_HI: 0
 				GRAS_LRZ_BUFFER_PITCH: { PITCH = 0 | ARRAY_PITCH = 0 }
 				GRAS_LRZ_FAST_CLEAR_BUFFER_BASE: 0
 				GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI: 0
 000000000115e098:			0000: 48810385 00000000 00000000 00000000 00000000 00000000
-t4			write RB_STENCIL_INFO (8881)
+			write RB_STENCIL_INFO (8881)
 				RB_STENCIL_INFO: { 0 }
 000000000115e0b0:			0000: 48888101 00000000
-t4			write RB_MRT[0].BUF_INFO (8822)
+			write RB_MRT[0].BUF_INFO (8822)
 				RB_MRT[0].BUF_INFO: { COLOR_FORMAT = FMT6_8_8_8_8_UNORM | COLOR_TILE_MODE = TILE6_3 | COLOR_SWAP = WZYX }
 				RB_MRT[0].PITCH: 1024
 				RB_MRT[0].ARRAY_PITCH: 262144
@@ -545,47 +545,47 @@ t4			write RB_MRT[0].BUF_INFO (8822)
 				RB_MRT[0].BASE_HI: 0
 				RB_MRT[0].BASE_GMEM: 0
 000000000115e0b8:			0000: 48882286 00000330 00000010 00001000 01013000 00000000 00000000
-t4			write SP_FS_MRT[0].REG (a996)
+			write SP_FS_MRT[0].REG (a996)
 				SP_FS_MRT[0].REG: { COLOR_FORMAT = FMT6_8_8_8_8_UNORM }
 000000000115e0d4:			0000: 48a99601 00000030
-t4			write RB_MRT_FLAG_BUFFER[0].ADDR (8903)
+			write RB_MRT_FLAG_BUFFER[0].ADDR (8903)
 				RB_MRT_FLAG_BUFFER[0].ADDR: 0x1012000
 				RB_MRT_FLAG_BUFFER[0].ADDR_HI: 0
 				RB_MRT_FLAG_BUFFER[0].PITCH: { PITCH = 64 | ARRAY_PITCH = 1024 }
 000000000115e0dc:			0000: 40890383 01012000 00000000 00004001
-t4			write RB_SRGB_CNTL (880f)
+			write RB_SRGB_CNTL (880f)
 				RB_SRGB_CNTL: { 0 }
 000000000115e0ec:			0000: 48880f01 00000000
-t4			write SP_SRGB_CNTL (a98a)
+			write SP_SRGB_CNTL (a98a)
 				SP_SRGB_CNTL: { 0 }
 000000000115e0f4:			0000: 40a98a01 00000000
-t4			write GRAS_MAX_LAYER_INDEX (8004)
+			write GRAS_MAX_LAYER_INDEX (8004)
 				GRAS_MAX_LAYER_INDEX: 0
 000000000115e0fc:			0000: 48800401 00000000
-t4			write SP_TP_RAS_MSAA_CNTL (b300)
+			write SP_TP_RAS_MSAA_CNTL (b300)
 				SP_TP_RAS_MSAA_CNTL: { SAMPLES = MSAA_ONE }
 				SP_TP_DEST_MSAA_CNTL: { SAMPLES = MSAA_ONE | MSAA_DISABLE }
 000000000115e104:			0000: 40b30002 00000000 00000004
-t4			write GRAS_RAS_MSAA_CNTL (80a2)
+			write GRAS_RAS_MSAA_CNTL (80a2)
 				GRAS_RAS_MSAA_CNTL: { SAMPLES = MSAA_ONE }
 				GRAS_DEST_MSAA_CNTL: { SAMPLES = MSAA_ONE | MSAA_DISABLE }
 000000000115e110:			0000: 4880a202 00000000 00000004
-t4			write RB_RAS_MSAA_CNTL (8802)
+			write RB_RAS_MSAA_CNTL (8802)
 				RB_RAS_MSAA_CNTL: { SAMPLES = MSAA_ONE }
 				RB_DEST_MSAA_CNTL: { SAMPLES = MSAA_ONE | MSAA_DISABLE }
 000000000115e11c:			0000: 40880202 00000000 00000004
-t4			write RB_BLIT_GMEM_MSAA_CNTL (88d5)
+			write RB_BLIT_GMEM_MSAA_CNTL (88d5)
 				RB_BLIT_GMEM_MSAA_CNTL: { SAMPLES = MSAA_ONE }
 000000000115e128:			0000: 4088d501 00000000
-t7			opcode: CP_COND_REG_EXEC (47) (3 dwords)
+			opcode: CP_COND_REG_EXEC (47) (3 dwords)
 				{ REG0 = 0 | GMEM | SYSMEM | MODE = RENDER_MODE }
 				{ DWORDS = 4 }
 000000000115e130:			0000: 70c70002 3c000000 00000004
-t7			opcode: CP_REG_WRITE (6d) (4 dwords)
+			opcode: CP_REG_WRITE (6d) (4 dwords)
 				{ TRACKER = TRACK_RENDER_CNTL }
 				RB_RENDER_CNTL: { CCUSINGLECACHELINESIZE = 0x2 | RASTER_MODE = TYPE_TILED | RASTER_DIRECTION = LR_TB | FLAG_MRTS = 0x1 }
 000000000115e13c:			0000: 706d8003 00000002 00008801 00010010
-t7			opcode: CP_SET_DRAW_STATE (43) (7 dwords)
+			opcode: CP_SET_DRAW_STATE (43) (7 dwords)
 				{ COUNT = 0 | DISABLE | GMEM | GROUP_ID = 17 }
 				{ ADDR_LO = 0 }
 				{ ADDR_HI = 0 }
@@ -593,7 +593,7 @@ t7			opcode: CP_SET_DRAW_STATE (43) (7 dwords)
 				{ ADDR_LO = 0 }
 				{ ADDR_HI = 0 }
 000000000115e14c:			0000: 70438006 11220000 00000000 00000000 12420000 00000000 00000000
-t7			opcode: CP_SET_DRAW_STATE (43) (52 dwords)
+			opcode: CP_SET_DRAW_STATE (43) (52 dwords)
 				{ COUNT = 157 | GMEM | SYSMEM | GROUP_ID = 0 }
 				{ ADDR_LO = 0x1054180 }
 				{ ADDR_HI = 0 }
@@ -652,15 +652,15 @@ t7			opcode: CP_SET_DRAW_STATE (43) (52 dwords)
 000000000115e1e8:			0080: 01054738 00000000 17700005 010547a0 00000000 18700003 01054760 00000000
 000000000115e208:			00a0: 19700002 0105476c 00000000 1a700002 01054774 00000000 1b700002 0105477c
 000000000115e228:			00c0: 00000000 1c700006 010547b4 00000000
-t4			write PC_RESTART_INDEX (9803)
+			write PC_RESTART_INDEX (9803)
 				PC_RESTART_INDEX: 4294967295
 000000000115e238:			0000: 40980301 ffffffff
-t7			opcode: CP_WAIT_FOR_ME (13) (1 dwords)
+			opcode: CP_WAIT_FOR_ME (13) (1 dwords)
 000000000115e240:			0000: 70138000
-t4			write PC_PRIMITIVE_CNTL_0 (9b00)
+			write PC_PRIMITIVE_CNTL_0 (9b00)
 				PC_PRIMITIVE_CNTL_0: { 0 }
 000000000115e244:			0000: 409b0001 00000000
-t7			opcode: CP_SET_DRAW_STATE (43) (82 dwords)
+			opcode: CP_SET_DRAW_STATE (43) (82 dwords)
 				{ COUNT = 157 | GMEM | SYSMEM | GROUP_ID = 0 }
 				{ ADDR_LO = 0x1054180 }
 				{ ADDR_HI = 0 }
@@ -778,20 +778,20 @@ t7			opcode: CP_SET_DRAW_STATE (43) (82 dwords)
 00000000010543a0:				0220: 00000001 48a98e08 00000002 000000fc 000000fc 000000fc 000000fc 000000fc
 00000000010543c0:				0240: 000000fc 000000fc 48a98b01 0000000f 40880b02 00000000 00000001 40880d01
 00000000010543e0:				0260: 0000000f 48809401 00000000 40887001 00000000
-t4					write HLSQ_INVALIDATE_CMD (bb08)
+					write HLSQ_INVALIDATE_CMD (bb08)
 						HLSQ_INVALIDATE_CMD: { VS_STATE | HS_STATE | DS_STATE | GS_STATE | FS_STATE | GFX_IBO | CS_BINDLESS = 0 | GFX_BINDLESS = 0 }
 0000000001054180:					0000: 40bb0801 0000009f
-t4					write SP_VS_CTRL_REG0 (a800)
+					write SP_VS_CTRL_REG0 (a800)
 						SP_VS_CTRL_REG0: { MERGEDREGS | THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 3 | BRANCHSTACK = 0 | 0x80000000 }
 0000000001054188:					0000: 40a80001 80100180
-t4					write SP_VS_CONFIG (a823)
+					write SP_VS_CONFIG (a823)
 						SP_VS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 }
 						SP_VS_INSTRLEN: 1
 0000000001054190:					0000: 48a82302 00000100 00000001
-t4					write HLSQ_VS_CNTL (b800)
+					write HLSQ_VS_CNTL (b800)
 						HLSQ_VS_CNTL: { CONSTLEN = 4 | ENABLED }
 000000000105419c:					0000: 48b80001 00000101
-t4					write SP_VS_OBJ_START (a81c)
+					write SP_VS_OBJ_START (a81c)
 						SP_VS_OBJ_START: 0x1054000		base=1054000, offset=0, size=12288
 0000000001054000:							0000: 00080009 42bc080b 10040004 64858008 10050005 64858009 10050006 6485800a
 0000000001054020:							0020: 10040007 6485800b 00000000 03000000 00000000 00000000 00000000 00000000
@@ -816,7 +816,7 @@ t4					write SP_VS_OBJ_START (a81c)
 							- shaderdb: 0 sstall, 0 (ss), 0 (sy)
 						SP_VS_OBJ_START_HI: 0
 00000000010541a4:					0000: 48a81c02 01054000 00000000
-t7					opcode: CP_LOAD_STATE6_GEOM (32) (4 dwords)
+					opcode: CP_LOAD_STATE6_GEOM (32) (4 dwords)
 						{ DST_OFF = 0 | STATE_TYPE = ST6_SHADER | STATE_SRC = SS6_INDIRECT | STATE_BLOCK = SB6_VS_SHADER | NUM_UNIT = 1 }
 						{ EXT_SRC_ADDR = 0x1054000 }
 						{ EXT_SRC_ADDR_HI = 0 }
@@ -836,42 +836,42 @@ t7					opcode: CP_LOAD_STATE6_GEOM (32) (4 dwords)
 						- shaderdb: 8 cat0, 0 cat1, 1 cat2, 4 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7
 						- shaderdb: 0 sstall, 0 (ss), 0 (sy)
 00000000010541b0:					0000: 70328003 00620000 01054000 00000000
-t7					opcode: CP_LOAD_STATE6_GEOM (32) (8 dwords)
+					opcode: CP_LOAD_STATE6_GEOM (32) (8 dwords)
 						{ DST_OFF = 1 | STATE_TYPE = ST6_CONSTANTS | STATE_SRC = SS6_DIRECT | STATE_BLOCK = SB6_VS_SHADER | NUM_UNIT = 1 }
 						{ EXT_SRC_ADDR = 0 }
 						{ EXT_SRC_ADDR_HI = 0 }
 00000000010541d0:						1.000000 0.000000 -28026765312.000000 -28026765312.000000
 00000000010541d0:						0000: 3f800000 00000000 d0d0d0d0 d0d0d0d0
 00000000010541c0:					0000: 70320007 00604001 00000000 00000000 3f800000 00000000 d0d0d0d0 d0d0d0d0
-t4					write SP_HS_CONFIG (a83b)
+					write SP_HS_CONFIG (a83b)
 						SP_HS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 }
 00000000010541e0:					0000: 48a83b01 00000000
-t4					write HLSQ_HS_CNTL (b801)
+					write HLSQ_HS_CNTL (b801)
 						HLSQ_HS_CNTL: { CONSTLEN = 0 }
 00000000010541e8:					0000: 40b80101 00000000
-t4					write SP_DS_CONFIG (a863)
+					write SP_DS_CONFIG (a863)
 						SP_DS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 }
 00000000010541f0:					0000: 40a86301 00000000
-t4					write HLSQ_DS_CNTL (b802)
+					write HLSQ_DS_CNTL (b802)
 						HLSQ_DS_CNTL: { CONSTLEN = 0 }
 00000000010541f8:					0000: 40b80201 00000000
-t4					write SP_GS_CONFIG (a894)
+					write SP_GS_CONFIG (a894)
 						SP_GS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 }
 0000000001054200:					0000: 48a89401 00000000
-t4					write HLSQ_GS_CNTL (b803)
+					write HLSQ_GS_CNTL (b803)
 						HLSQ_GS_CNTL: { CONSTLEN = 0 }
 0000000001054208:					0000: 48b80301 00000000
-t4					write SP_FS_CTRL_REG0 (a980)
+					write SP_FS_CTRL_REG0 (a980)
 						SP_FS_CTRL_REG0: { THREADSIZE = THREAD128 | VARYING | UNK24 | MERGEDREGS | THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 2 | BRANCHSTACK = 0 }
 0000000001054210:					0000: 40a98001 81500100
-t4					write SP_FS_CONFIG (ab04)
+					write SP_FS_CONFIG (ab04)
 						SP_FS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 }
 						SP_FS_INSTRLEN: 1
 0000000001054218:					0000: 48ab0402 00000100 00000001
-t4					write HLSQ_FS_CNTL (bb10)
+					write HLSQ_FS_CNTL (bb10)
 						HLSQ_FS_CNTL: { CONSTLEN = 0 | ENABLED }
 0000000001054224:					0000: 40bb1001 00000100
-t4					write SP_FS_OBJ_START (a983)
+					write SP_FS_OBJ_START (a983)
 						SP_FS_OBJ_START: 0x1054080		base=1054000, offset=128, size=12288
 0000000001054080:							0000: 00002000 47300002 00002001 47300003 00002002 47300004 00002003 47308005
 00000000010540a0:							0020: 00000000 03000000 00000000 00000000 00000000 00000000 00000000 00000000
@@ -894,7 +894,7 @@ t4					write SP_FS_OBJ_START (a983)
 							- shaderdb: 0 sstall, 0 (ss), 0 (sy)
 						SP_FS_OBJ_START_HI: 0
 000000000105422c:					0000: 40a98302 01054080 00000000
-t7					opcode: CP_LOAD_STATE6_FRAG (34) (4 dwords)
+					opcode: CP_LOAD_STATE6_FRAG (34) (4 dwords)
 						{ DST_OFF = 0 | STATE_TYPE = ST6_SHADER | STATE_SRC = SS6_INDIRECT | STATE_BLOCK = SB6_FS_SHADER | NUM_UNIT = 1 }
 						{ EXT_SRC_ADDR = 0x1054080 }
 						{ EXT_SRC_ADDR_HI = 0 }
@@ -913,16 +913,16 @@ t7					opcode: CP_LOAD_STATE6_FRAG (34) (4 dwords)
 						- shaderdb: 5 cat0, 0 cat1, 4 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7
 						- shaderdb: 0 sstall, 0 (ss), 0 (sy)
 0000000001054238:					0000: 70348003 00720000 01054080 00000000
-t4					write SP_CS_CONFIG (a9bb)
+					write SP_CS_CONFIG (a9bb)
 						SP_CS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 }
 0000000001054248:					0000: 48a9bb01 00000000
-t4					write HLSQ_CS_CNTL (b987)
+					write HLSQ_CS_CNTL (b987)
 						HLSQ_CS_CNTL: { CONSTLEN = 0 }
 0000000001054250:					0000: 40b98701 00000000
-t4					write SP_HS_WAVE_INPUT_SIZE (a831)
+					write SP_HS_WAVE_INPUT_SIZE (a831)
 						SP_HS_WAVE_INPUT_SIZE: 0
 0000000001054258:					0000: 48a83101 00000000
-t4					write VFD_CONTROL_1 (a001)
+					write VFD_CONTROL_1 (a001)
 						VFD_CONTROL_1: { REGID4VTX = r2.y | REGID4INST = r63.x | REGID4PRIMID = r63.x | REGID4VIEWID = r63.x }
 						VFD_CONTROL_2: { REGID_HSRELPATCHID = r63.x | REGID_INVOCATIONID = r63.x }
 						VFD_CONTROL_3: { REGID_DSPRIMID = r63.x | REGID_DSRELPATCHID = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x }
@@ -930,50 +930,50 @@ t4					write VFD_CONTROL_1 (a001)
 						VFD_CONTROL_5: { REGID_GSHEADER = r63.x | UNK8 = r63.x }
 						VFD_CONTROL_6: { 0 }
 0000000001054260:					0000: 40a00186 fcfcfc09 0000fcfc fcfcfcfc 000000fc 0000fcfc 00000000
-t4					write VPC_VAR[0].DISABLE (9212)
+					write VPC_VAR[0].DISABLE (9212)
 						VPC_VAR[0].DISABLE: 0xfffffff0
 						VPC_VAR[0x1].DISABLE: 0xffffffff
 						VPC_VAR[0x2].DISABLE: 0xffffffff
 						VPC_VAR[0x3].DISABLE: 0xffffffff
 000000000105427c:					0000: 40921204 fffffff0 ffffffff ffffffff ffffffff
-t7					opcode: CP_CONTEXT_REG_BUNCH (5c) (5 dwords)
+					opcode: CP_CONTEXT_REG_BUNCH (5c) (5 dwords)
 						VPC_SO_CNTL: { ADDR = 0 }
 						VPC_SO_STREAM_CNTL: { BUF0_STREAM = 0 | BUF1_STREAM = 0 | BUF2_STREAM = 0 | BUF3_STREAM = 0 | STREAM_ENABLE = 0 }
 0000000001054290:					0000: 70dc0004 00009216 00000000 00009305 00000000
-t4					write SP_VS_OUT[0].REG (a803)
+					write SP_VS_OUT[0].REG (a803)
 						SP_VS_OUT[0].REG: { A_REGID = r2.x | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0xf }
 00000000010542a4:					0000: 40a80301 0f000f08
-t4					write SP_VS_VPC_DST[0].REG (a813)
+					write SP_VS_VPC_DST[0].REG (a813)
 						SP_VS_VPC_DST[0].REG: { OUTLOC0 = 0 | OUTLOC1 = 4 | OUTLOC2 = 0 | OUTLOC3 = 0 }
 00000000010542ac:					0000: 48a81301 00000400
-t4					write VPC_VS_PACK (9301)
+					write VPC_VS_PACK (9301)
 						VPC_VS_PACK: { STRIDE_IN_VPC = 8 | POSITIONLOC = 4 | PSIZELOC = 255 | EXTRAPOS = 0 }
 00000000010542b4:					0000: 40930101 00ff0408
-t4					write VPC_VS_CLIP_CNTL (9101)
+					write VPC_VS_CLIP_CNTL (9101)
 						VPC_VS_CLIP_CNTL: { CLIP_MASK = 0 | CLIP_DIST_03_LOC = 255 | CLIP_DIST_47_LOC = 255 }
 00000000010542bc:					0000: 48910101 00ffff00
-t4					write GRAS_VS_CL_CNTL (8001)
+					write GRAS_VS_CL_CNTL (8001)
 						GRAS_VS_CL_CNTL: { CLIP_MASK = 0 | CULL_MASK = 0 }
 00000000010542c4:					0000: 48800101 00000000
-t4					write PC_VS_OUT_CNTL (9b01)
+					write PC_VS_OUT_CNTL (9b01)
 						PC_VS_OUT_CNTL: { STRIDE_IN_VPC = 8 | CLIP_MASK = 0 }
 00000000010542cc:					0000: 489b0101 00000008
-t4					write SP_VS_PRIMITIVE_CNTL (a802)
+					write SP_VS_PRIMITIVE_CNTL (a802)
 						SP_VS_PRIMITIVE_CNTL: { OUT = 2 | FLAGS_REGID = r0.x }
 00000000010542d4:					0000: 48a80201 00000002
-t4					write VPC_VS_LAYER_CNTL (9104)
+					write VPC_VS_LAYER_CNTL (9104)
 						VPC_VS_LAYER_CNTL: { LAYERLOC = 255 | VIEWLOC = 255 }
 00000000010542dc:					0000: 48910401 0000ffff
-t4					write GRAS_VS_LAYER_CNTL (809b)
+					write GRAS_VS_LAYER_CNTL (809b)
 						GRAS_VS_LAYER_CNTL: { 0 }
 00000000010542e4:					0000: 48809b01 00000000
-t4					write PC_PRIMID_PASSTHRU (9806)
+					write PC_PRIMID_PASSTHRU (9806)
 						PC_PRIMID_PASSTHRU: FALSE
 00000000010542ec:					0000: 40980601 00000000
-t4					write VPC_CNTL_0 (9304)
+					write VPC_CNTL_0 (9304)
 						VPC_CNTL_0: { NUMNONPOSVAR = 4 | PRIMIDLOC = 255 | VARYING | VIEWIDLOC = 255 }
 00000000010542f4:					0000: 40930401 ff01ff04
-t4					write VPC_VARYING_INTERP[0].MODE (9200)
+					write VPC_VARYING_INTERP[0].MODE (9200)
 						VPC_VARYING_INTERP[0].MODE: 0
 						VPC_VARYING_INTERP[0x1].MODE: 0
 						VPC_VARYING_INTERP[0x2].MODE: 0
@@ -984,7 +984,7 @@ t4					write VPC_VARYING_INTERP[0].MODE (9200)
 						VPC_VARYING_INTERP[0x7].MODE: 0
 00000000010542fc:					0000: 40920008 00000000 00000000 00000000 00000000 00000000 00000000 00000000
 *
-t4					write VPC_VARYING_PS_REPL[0].MODE (9208)
+					write VPC_VARYING_PS_REPL[0].MODE (9208)
 						VPC_VARYING_PS_REPL[0].MODE: 0
 						VPC_VARYING_PS_REPL[0x1].MODE: 0
 						VPC_VARYING_PS_REPL[0x2].MODE: 0
@@ -995,40 +995,40 @@ t4					write VPC_VARYING_PS_REPL[0].MODE (9208)
 						VPC_VARYING_PS_REPL[0x7].MODE: 0
 0000000001054320:					0000: 48920808 00000000 00000000 00000000 00000000 00000000 00000000 00000000
 *
-t4					write SP_FS_PREFETCH_CNTL (a99e)
+					write SP_FS_PREFETCH_CNTL (a99e)
 						SP_FS_PREFETCH_CNTL: { COUNT = 0 | UNK6 = 0x1ff }
 0000000001054344:					0000: 40a99e01 00007fc0
-t4					write HLSQ_CONTROL_1_REG (b982)
+					write HLSQ_CONTROL_1_REG (b982)
 						HLSQ_CONTROL_1_REG: 0x7
 						HLSQ_CONTROL_2_REG: { FACEREGID = r63.x | SAMPLEID = r63.x | SAMPLEMASK = r63.x | CENTERRHW = r63.x }
 						HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x }
 						HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | XYCOORDREGID = r63.x | ZWCOORDREGID = r63.x }
 						HLSQ_CONTROL_5_REG: { LINELENGTHREGID = r63.x | FOVEATIONQUALITYREGID = r0.x }
 000000000105434c:					0000: 40b98285 00000007 fcfcfcfc fcfcfc00 fcfcfcfc 000000fc
-t4					write HLSQ_FS_CNTL_0 (b980)
+					write HLSQ_FS_CNTL_0 (b980)
 						HLSQ_FS_CNTL_0: { THREADSIZE = THREAD128 | VARYINGS }
 0000000001054364:					0000: 48b98001 00000003
-t4					write GRAS_CNTL (8005)
+					write GRAS_CNTL (8005)
 						GRAS_CNTL: { IJ_PERSP_PIXEL | COORD_MASK = 0 }
 000000000105436c:					0000: 40800501 00000001
-t4					write RB_RENDER_CONTROL0 (8809)
+					write RB_RENDER_CONTROL0 (8809)
 						RB_RENDER_CONTROL0: { IJ_PERSP_PIXEL | COORD_MASK = 0 | UNK10 }
 						RB_RENDER_CONTROL1: { FRAGCOORDSAMPLEMODE = FRAGCOORD_CENTER }
 0000000001054374:					0000: 48880902 00000401 00000000
-t4					write RB_SAMPLE_CNTL (8810)
+					write RB_SAMPLE_CNTL (8810)
 						RB_SAMPLE_CNTL: { 0 }
 0000000001054380:					0000: 40881001 00000000
-t4					write GRAS_LRZ_PS_INPUT_CNTL (8101)
+					write GRAS_LRZ_PS_INPUT_CNTL (8101)
 						GRAS_LRZ_PS_INPUT_CNTL: { FRAGCOORDSAMPLEMODE = FRAGCOORD_CENTER }
 0000000001054388:					0000: 40810101 00000000
-t4					write GRAS_SAMPLE_CNTL (8109)
+					write GRAS_SAMPLE_CNTL (8109)
 						GRAS_SAMPLE_CNTL: { 0 }
 0000000001054390:					0000: 48810901 00000000
-t4					write SP_FS_OUTPUT_CNTL0 (a98c)
+					write SP_FS_OUTPUT_CNTL0 (a98c)
 						SP_FS_OUTPUT_CNTL0: { DEPTH_REGID = r63.x | SAMPMASK_REGID = r63.x | STENCILREF_REGID = r63.x }
 						SP_FS_OUTPUT_CNTL1: { MRT = 1 }
 0000000001054398:					0000: 40a98c02 fcfcfc00 00000001
-t4					write SP_FS_OUTPUT[0].REG (a98e)
+					write SP_FS_OUTPUT[0].REG (a98e)
 						SP_FS_OUTPUT[0].REG: { REGID = r0.z }
 						SP_FS_OUTPUT[0x1].REG: { REGID = r63.x }
 						SP_FS_OUTPUT[0x2].REG: { REGID = r63.x }
@@ -1039,20 +1039,20 @@ t4					write SP_FS_OUTPUT[0].REG (a98e)
 						SP_FS_OUTPUT[0x7].REG: { REGID = r63.x }
 00000000010543a4:					0000: 48a98e08 00000002 000000fc 000000fc 000000fc 000000fc 000000fc 000000fc
 00000000010543c4:					0020: 000000fc
-t4					write SP_FS_RENDER_COMPONENTS (a98b)
+					write SP_FS_RENDER_COMPONENTS (a98b)
 						SP_FS_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 }
 00000000010543c8:					0000: 48a98b01 0000000f
-t4					write RB_FS_OUTPUT_CNTL0 (880b)
+					write RB_FS_OUTPUT_CNTL0 (880b)
 						RB_FS_OUTPUT_CNTL0: { 0 }
 						RB_FS_OUTPUT_CNTL1: { MRT = 1 }
 00000000010543d0:					0000: 40880b02 00000000 00000001
-t4					write RB_RENDER_COMPONENTS (880d)
+					write RB_RENDER_COMPONENTS (880d)
 						RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 }
 00000000010543dc:					0000: 40880d01 0000000f
-t4					write GRAS_SU_DEPTH_PLANE_CNTL (8094)
+					write GRAS_SU_DEPTH_PLANE_CNTL (8094)
 						GRAS_SU_DEPTH_PLANE_CNTL: { Z_MODE = A6XX_EARLY_Z }
 00000000010543e4:					0000: 48809401 00000000
-t4					write RB_DEPTH_PLANE_CNTL (8870)
+					write RB_DEPTH_PLANE_CNTL (8870)
 						RB_DEPTH_PLANE_CNTL: { Z_MODE = A6XX_EARLY_Z }
 00000000010543ec:					0000: 40887001 00000000
 			group_id: 1
@@ -1068,7 +1068,7 @@ t4					write RB_DEPTH_PLANE_CNTL (8870)
 			flags: 0
 			enable_mask: 0x7
 000000000115c070:				0000: 40a01083 01053000 00000000 00000318
-t4					write VFD_FETCH[0].BASE (a010)
+					write VFD_FETCH[0].BASE (a010)
 						VFD_FETCH[0].BASE: 0x1053000
 						VFD_FETCH[0].BASE_HI: 0
 						VFD_FETCH[0].SIZE: 792
@@ -1081,31 +1081,31 @@ t4					write VFD_FETCH[0].BASE (a010)
 0000000001054620:				0000: 40a01301 00000024 48a09002 c8200000 00000001 40a0d001 0000000f 40a09202
 0000000001054640:				0020: c8200200 00000001 48a0d101 0000004f 40a09402 44c00400 00000001 48a0d201
 0000000001054660:				0040: 00000081 48a00001 00000303
-t4					write VFD_FETCH[0].STRIDE (a013)
+					write VFD_FETCH[0].STRIDE (a013)
 						VFD_FETCH[0].STRIDE: 36
 0000000001054620:					0000: 40a01301 00000024
-t4					write VFD_DECODE[0].INSTR (a090)
+					write VFD_DECODE[0].INSTR (a090)
 						VFD_DECODE[0].INSTR: { IDX = 0 | OFFSET = 0 | FORMAT = FMT6_32_32_32_32_FLOAT | SWAP = WZYX | UNK30 | FLOAT }
 						VFD_DECODE[0].STEP_RATE: 1
 0000000001054628:					0000: 48a09002 c8200000 00000001
-t4					write VFD_DEST_CNTL[0].INSTR (a0d0)
+					write VFD_DEST_CNTL[0].INSTR (a0d0)
 						VFD_DEST_CNTL[0].INSTR: { WRITEMASK = 0xf | REGID = r0.x }
 0000000001054634:					0000: 40a0d001 0000000f
-t4					write VFD_DECODE[0x1].INSTR (a092)
+					write VFD_DECODE[0x1].INSTR (a092)
 						VFD_DECODE[0x1].INSTR: { IDX = 0 | OFFSET = 0x10 | FORMAT = FMT6_32_32_32_32_FLOAT | SWAP = WZYX | UNK30 | FLOAT }
 						VFD_DECODE[0x1].STEP_RATE: 1
 000000000105463c:					0000: 40a09202 c8200200 00000001
-t4					write VFD_DEST_CNTL[0x1].INSTR (a0d1)
+					write VFD_DEST_CNTL[0x1].INSTR (a0d1)
 						VFD_DEST_CNTL[0x1].INSTR: { WRITEMASK = 0xf | REGID = r1.x }
 0000000001054648:					0000: 48a0d101 0000004f
-t4					write VFD_DECODE[0x2].INSTR (a094)
+					write VFD_DECODE[0x2].INSTR (a094)
 						VFD_DECODE[0x2].INSTR: { IDX = 0 | OFFSET = 0x20 | FORMAT = FMT6_32_SINT | SWAP = WZYX | UNK30 }
 						VFD_DECODE[0x2].STEP_RATE: 1
 0000000001054650:					0000: 40a09402 44c00400 00000001
-t4					write VFD_DEST_CNTL[0x2].INSTR (a0d2)
+					write VFD_DEST_CNTL[0x2].INSTR (a0d2)
 						VFD_DEST_CNTL[0x2].INSTR: { WRITEMASK = 0x1 | REGID = r2.x }
 000000000105465c:					0000: 48a0d201 00000081
-t4					write VFD_CONTROL_0 (a000)
+					write VFD_CONTROL_0 (a000)
 						VFD_CONTROL_0: { FETCH_CNT = 3 | DECODE_CNT = 3 }
 0000000001054664:					0000: 48a00001 00000303
 			group_id: 5
@@ -1122,16 +1122,16 @@ t4					write VFD_CONTROL_0 (a000)
 			enable_mask: 0x7
 000000000105470c:				0000: 40800001 000000c0 48910801 00000003 48998101 00000003 48809102 ffc00001
 000000000105472c:				0020: 00000010
-t4					write GRAS_CL_CNTL (8000)
+					write GRAS_CL_CNTL (8000)
 						GRAS_CL_CNTL: { ZERO_GB_SCALE_Z | VP_CLIP_CODE_IGNORE }
 000000000105470c:					0000: 40800001 000000c0
-t4					write VPC_POLYGON_MODE (9108)
+					write VPC_POLYGON_MODE (9108)
 						VPC_POLYGON_MODE: { MODE = POLYMODE6_TRIANGLES }
 0000000001054714:					0000: 48910801 00000003
-t4					write PC_POLYGON_MODE (9981)
+					write PC_POLYGON_MODE (9981)
 						PC_POLYGON_MODE: { MODE = POLYMODE6_TRIANGLES }
 000000000105471c:					0000: 48998101 00000003
-t4					write GRAS_SU_POINT_MINMAX (8091)
+					write GRAS_SU_POINT_MINMAX (8091)
 						GRAS_SU_POINT_MINMAX: { MIN = 0.062500 | MAX = 4092.000000 }
 						GRAS_SU_POINT_SIZE: 1.000000
 0000000001054724:					0000: 48809102 ffc00001 00000010
@@ -1141,13 +1141,13 @@ t4					write GRAS_SU_POINT_MINMAX (8091)
 			flags: 0
 			enable_mask: 0x7
 0000000001054748:				0000: 40886401 00000000 48887101 00000000 40888001 00000000
-t4					write RB_ALPHA_CONTROL (8864)
+					write RB_ALPHA_CONTROL (8864)
 						RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_NEVER }
 0000000001054748:					0000: 40886401 00000000
-t4					write RB_DEPTH_CNTL (8871)
+					write RB_DEPTH_CNTL (8871)
 						RB_DEPTH_CNTL: { ZFUNC = FUNC_NEVER }
 0000000001054750:					0000: 48887101 00000000
-t4					write RB_STENCIL_CONTROL (8880)
+					write RB_STENCIL_CONTROL (8880)
 						RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP }
 0000000001054758:					0000: 40888001 00000000
 			group_id: 8
@@ -1156,14 +1156,14 @@ t4					write RB_STENCIL_CONTROL (8880)
 			flags: 0
 			enable_mask: 0x7
 0000000001054784:				0000: 40882002 00000780 08040804 40a98901 00000100 48886501 ffff0100
-t4					write RB_MRT[0].CONTROL (8820)
+					write RB_MRT[0].CONTROL (8820)
 						RB_MRT[0].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0xf }
 						RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_SRC_COLOR | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_DST_COLOR | ALPHA_SRC_FACTOR = FACTOR_SRC_COLOR | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_DST_COLOR }
 0000000001054784:					0000: 40882002 00000780 08040804
-t4					write SP_BLEND_CNTL (a989)
+					write SP_BLEND_CNTL (a989)
 						SP_BLEND_CNTL: { ENABLE_BLEND = 0 | UNK8 }
 0000000001054790:					0000: 40a98901 00000100
-t4					write RB_BLEND_CNTL (8865)
+					write RB_BLEND_CNTL (8865)
 						RB_BLEND_CNTL: { ENABLE_BLEND = 0 | INDEPENDENT_BLEND | SAMPLE_MASK = 0xffff }
 0000000001054798:					0000: 48886501 ffff0100
 			group_id: 19
@@ -1174,7 +1174,7 @@ t4					write RB_BLEND_CNTL (8865)
 00000000010546b8:				0000: 48801086 43000000 43000000 43000000 43000000 00000000 3f800000 4880d002
 00000000010546d8:				0020: 00000000 00ff00ff 40800601 0007fdff 48807002 00000000 3f800000 4888c002
 00000000010546f8:				0040: 00000000 3f800000
-t4					write GRAS_CL_VPORT[0].XOFFSET (8010)
+					write GRAS_CL_VPORT[0].XOFFSET (8010)
 						GRAS_CL_VPORT[0].XOFFSET: 128.000000
 						GRAS_CL_VPORT[0].XSCALE: 128.000000
 						GRAS_CL_VPORT[0].YOFFSET: 128.000000
@@ -1182,18 +1182,18 @@ t4					write GRAS_CL_VPORT[0].XOFFSET (8010)
 						GRAS_CL_VPORT[0].ZOFFSET: 0.000000
 						GRAS_CL_VPORT[0].ZSCALE: 1.000000
 00000000010546b8:					0000: 48801086 43000000 43000000 43000000 43000000 00000000 3f800000
-t4					write GRAS_SC_VIEWPORT_SCISSOR[0].TL (80d0)
+					write GRAS_SC_VIEWPORT_SCISSOR[0].TL (80d0)
 						GRAS_SC_VIEWPORT_SCISSOR[0].TL: { X = 0 | Y = 0 }
 						GRAS_SC_VIEWPORT_SCISSOR[0].BR: { X = 255 | Y = 255 }
 00000000010546d4:					0000: 4880d002 00000000 00ff00ff
-t4					write GRAS_CL_GUARDBAND_CLIP_ADJ (8006)
+					write GRAS_CL_GUARDBAND_CLIP_ADJ (8006)
 						GRAS_CL_GUARDBAND_CLIP_ADJ: { HORZ = 511 | VERT = 511 }
 00000000010546e0:					0000: 40800601 0007fdff
-t4					write GRAS_CL_Z_CLAMP[0].MIN (8070)
+					write GRAS_CL_Z_CLAMP[0].MIN (8070)
 						GRAS_CL_Z_CLAMP[0].MIN: 0.000000
 						GRAS_CL_Z_CLAMP[0].MAX: 1.000000
 00000000010546e8:					0000: 48807002 00000000 3f800000
-t4					write RB_Z_CLAMP_MIN (88c0)
+					write RB_Z_CLAMP_MIN (88c0)
 						RB_Z_CLAMP_MIN: 0.000000
 						RB_Z_CLAMP_MAX: 1.000000
 00000000010546f4:					0000: 4888c002 00000000 3f800000
@@ -1203,7 +1203,7 @@ t4					write RB_Z_CLAMP_MIN (88c0)
 			flags: 0
 			enable_mask: 0x7
 0000000001054700:				0000: 4880b002 00000000 00ff00ff
-t4					write GRAS_SC_SCREEN_SCISSOR[0].TL (80b0)
+					write GRAS_SC_SCREEN_SCISSOR[0].TL (80b0)
 						GRAS_SC_SCREEN_SCISSOR[0].TL: { X = 0 | Y = 0 }
 						GRAS_SC_SCREEN_SCISSOR[0].BR: { X = 255 | Y = 255 }
 0000000001054700:					0000: 4880b002 00000000 00ff00ff
@@ -1213,7 +1213,7 @@ t4					write GRAS_SC_SCREEN_SCISSOR[0].TL (80b0)
 			flags: 0
 			enable_mask: 0x7
 0000000001054730:				0000: 40809001 00000814
-t4					write GRAS_SU_CNTL (8090)
+					write GRAS_SU_CNTL (8090)
 						GRAS_SU_CNTL: { FRONT_CW | LINEHALFWIDTH = 0.500000 | POLY_OFFSET | LINE_MODE = BRESENHAM }
 0000000001054730:					0000: 40809001 00000814
 			group_id: 22
@@ -1222,7 +1222,7 @@ t4					write GRAS_SU_CNTL (8090)
 			flags: 0
 			enable_mask: 0x7
 0000000001054738:				0000: 40809583 00000000 00000000 00000000
-t4					write GRAS_SU_POLY_OFFSET_SCALE (8095)
+					write GRAS_SU_POLY_OFFSET_SCALE (8095)
 						GRAS_SU_POLY_OFFSET_SCALE: 0.000000
 						GRAS_SU_POLY_OFFSET_OFFSET: 0.000000
 						GRAS_SU_POLY_OFFSET_OFFSET_CLAMP: 0.000000
@@ -1233,7 +1233,7 @@ t4					write GRAS_SU_POLY_OFFSET_SCALE (8095)
 			flags: 0
 			enable_mask: 0x7
 00000000010547a0:				0000: 48886004 dffe8440 0000ffff dffe8678 0000ffff
-t4					write RB_BLEND_RED_F32 (8860)
+					write RB_BLEND_RED_F32 (8860)
 						RB_BLEND_RED_F32: -36679707902607360000.000000
 						RB_BLEND_GREEN_F32: 0.000000
 						RB_BLEND_BLUE_F32: -36680956947816513536.000000
@@ -1245,7 +1245,7 @@ t4					write RB_BLEND_RED_F32 (8860)
 			flags: 0
 			enable_mask: 0x7
 0000000001054760:				0000: 48887802 00000000 00000000
-t4					write RB_Z_BOUNDS_MIN (8878)
+					write RB_Z_BOUNDS_MIN (8878)
 						RB_Z_BOUNDS_MIN: 0.000000
 						RB_Z_BOUNDS_MAX: 0.000000
 0000000001054760:					0000: 48887802 00000000 00000000
@@ -1255,7 +1255,7 @@ t4					write RB_Z_BOUNDS_MIN (8878)
 			flags: 0
 			enable_mask: 0x7
 000000000105476c:				0000: 48888801 00000000
-t4					write RB_STENCILMASK (8888)
+					write RB_STENCILMASK (8888)
 						RB_STENCILMASK: { MASK = 0 | BFMASK = 0 }
 000000000105476c:					0000: 48888801 00000000
 			group_id: 26
@@ -1264,7 +1264,7 @@ t4					write RB_STENCILMASK (8888)
 			flags: 0
 			enable_mask: 0x7
 0000000001054774:				0000: 40888901 00000000
-t4					write RB_STENCILWRMASK (8889)
+					write RB_STENCILWRMASK (8889)
 						RB_STENCILWRMASK: { WRMASK = 0 | BFWRMASK = 0 }
 0000000001054774:					0000: 40888901 00000000
 			group_id: 27
@@ -1273,7 +1273,7 @@ t4					write RB_STENCILWRMASK (8889)
 			flags: 0
 			enable_mask: 0x7
 000000000105477c:				0000: 48888701 00000000
-t4					write RB_STENCILREF (8887)
+					write RB_STENCILREF (8887)
 						RB_STENCILREF: { REF = 0 | BFREF = 0 }
 000000000105477c:					0000: 48888701 00000000
 			group_id: 28
@@ -1282,16 +1282,16 @@ t4					write RB_STENCILREF (8887)
 			flags: 0
 			enable_mask: 0x7
 00000000010547b4:				0000: 4880a401 00000000 40880401 00000000 48b30401 00000000
-t4					write GRAS_SAMPLE_CONFIG (80a4)
+					write GRAS_SAMPLE_CONFIG (80a4)
 						GRAS_SAMPLE_CONFIG: { 0 }
 00000000010547b4:					0000: 4880a401 00000000
-t4					write RB_SAMPLE_CONFIG (8804)
+					write RB_SAMPLE_CONFIG (8804)
 						RB_SAMPLE_CONFIG: { 0 }
 00000000010547bc:					0000: 40880401 00000000
-t4					write SP_TP_SAMPLE_CONFIG (b304)
+					write SP_TP_SAMPLE_CONFIG (b304)
 						SP_TP_SAMPLE_CONFIG: { 0 }
 00000000010547c4:					0000: 48b30401 00000000
-t7			opcode: CP_DRAW_INDIRECT_MULTI (2a) (12 dwords)
+			opcode: CP_DRAW_INDIRECT_MULTI (2a) (12 dwords)
 				{ PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = USE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS }
 				{ OPCODE = INDIRECT_OP_INDIRECT_COUNT_INDEXED | DST_OFF = 0 }
 				{ DRAW_COUNT = 3 }
@@ -1538,44 +1538,44 @@ t7			opcode: CP_DRAW_INDIRECT_MULTI (2a) (12 dwords)
 000000000115e394:			0000: 702a000b 00000904 00000007 00000003 01057000 00000000 00000009 01162008
 000000000115e3b4:			0020: 00000000 0116300c 00000000 00000028
 00000000010583b8:		0000: 70bf8003 0115e000 00000000 000000f1
-t7		opcode: CP_INDIRECT_BUFFER (3f) (4 dwords)
+		opcode: CP_INDIRECT_BUFFER (3f) (4 dwords)
 		ibaddr:000000000115c000
 		ibsize:0000001c
-t7			opcode: CP_SET_DRAW_STATE (43) (4 dwords)
+			opcode: CP_SET_DRAW_STATE (43) (4 dwords)
 				{ COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 }
 				{ ADDR_LO = 0 }
 				{ ADDR_HI = 0 }
 000000000115c000:			0000: 70438003 00040000 00000000 00000000
-t7			opcode: CP_SKIP_IB2_ENABLE_GLOBAL (1d) (2 dwords)
+			opcode: CP_SKIP_IB2_ENABLE_GLOBAL (1d) (2 dwords)
 000000000115c010:			0000: 709d0001 00000000
-t7			opcode: CP_SET_MARKER (65) (2 dwords)
+			opcode: CP_SET_MARKER (65) (2 dwords)
 				{ MODE = RM6_RESOLVE | MARKER = RM6_RESOLVE }
 000000000115c018:			0000: 70e50001 00000006
-t4			write RB_BLIT_SCISSOR_TL (88d1)
+			write RB_BLIT_SCISSOR_TL (88d1)
 				RB_BLIT_SCISSOR_TL: { X = 0 | Y = 0 }
 				RB_BLIT_SCISSOR_BR: { X = 255 | Y = 255 }
 000000000115c020:			0000: 4888d102 00000000 00ff00ff
-t4			write RB_BLIT_GMEM_MSAA_CNTL (88d5)
+			write RB_BLIT_GMEM_MSAA_CNTL (88d5)
 				RB_BLIT_GMEM_MSAA_CNTL: { SAMPLES = MSAA_ONE }
 000000000115c02c:			0000: 4088d501 00000000
-t4			write RB_BLIT_INFO (88e3)
+			write RB_BLIT_INFO (88e3)
 				RB_BLIT_INFO: { CLEAR_MASK = 0 | LAST = 0 | BUFFER_ID = 0 }
 000000000115c034:			0000: 4088e301 00000000
-t4			write RB_BLIT_DST_INFO (88d7)
+			write RB_BLIT_DST_INFO (88d7)
 				RB_BLIT_DST_INFO: { TILE_MODE = TILE6_3 | FLAGS | SAMPLES = MSAA_ONE | COLOR_SWAP = WZYX | COLOR_FORMAT = FMT6_8_8_8_8_UNORM }
 				RB_BLIT_DST: 0x1013000
 				RB_BLIT_DST_HI: 0
 				RB_BLIT_DST_PITCH: 1024
 000000000115c03c:			0000: 4888d704 00001807 01013000 00000000 00000010
-t4			write RB_BLIT_FLAG_DST (88dc)
+			write RB_BLIT_FLAG_DST (88dc)
 				RB_BLIT_FLAG_DST: 0x1012000
 				RB_BLIT_FLAG_DST_HI: 0
 				RB_BLIT_FLAG_DST_PITCH: { PITCH = 64 | ARRAY_PITCH = 1024 }
 000000000115c050:			0000: 4088dc83 01012000 00000000 00004001
-t4			write RB_BLIT_BASE_GMEM (88d6)
+			write RB_BLIT_BASE_GMEM (88d6)
 				RB_BLIT_BASE_GMEM: 0
 000000000115c060:			0000: 4088d601 00000000
-t7			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = BLIT }
 			event BLIT
 			mode: RM6_RESOLVE
@@ -1595,28 +1595,28 @@ t7			opcode: CP_EVENT_WRITE (46) (2 dwords)
 !+	00000000			RB_BLIT_INFO: { CLEAR_MASK = 0 | LAST = 0 | BUFFER_ID = 0 }
 000000000115c068:			0000: 70460001 0000001e
 00000000010583c8:		0000: 70bf8003 0115c000 00000000 0000001c
-t4		write GRAS_LRZ_CNTL (8100)
+		write GRAS_LRZ_CNTL (8100)
 			GRAS_LRZ_CNTL: { DIR = 0 }
 00000000010583d8:		0000: 48810001 00000000
-t7		opcode: CP_EVENT_WRITE (46) (2 dwords)
+		opcode: CP_EVENT_WRITE (46) (2 dwords)
 			{ EVENT = LRZ_FLUSH }
 		event LRZ_FLUSH
 00000000010583e0:		0000: 70460001 00000026
-t7		opcode: CP_EVENT_WRITE (46) (5 dwords)
+		opcode: CP_EVENT_WRITE (46) (5 dwords)
 			{ EVENT = PC_CCU_RESOLVE_TS }
 			{ ADDR_0_LO = 0x1011880 }
 			{ ADDR_0_HI = 0 }
 			{ 3 = 0 }
 		event PC_CCU_RESOLVE_TS
 00000000010583e8:		0000: 70460004 0000001a 01011880 00000000 00000000
-t7		opcode: CP_EVENT_WRITE (46) (5 dwords)
+		opcode: CP_EVENT_WRITE (46) (5 dwords)
 			{ EVENT = PC_CCU_FLUSH_COLOR_TS }
 			{ ADDR_0_LO = 0x1011880 }
 			{ ADDR_0_HI = 0 }
 			{ 3 = 0 }
 		event PC_CCU_FLUSH_COLOR_TS
 00000000010583fc:		0000: 70460004 0000001d 01011880 00000000 00000000
-t7		opcode: CP_EVENT_WRITE (46) (5 dwords)
+		opcode: CP_EVENT_WRITE (46) (5 dwords)
 			{ EVENT = PC_CCU_FLUSH_DEPTH_TS }
 			{ ADDR_0_LO = 0x1011880 }
 			{ ADDR_0_HI = 0 }
diff --git a/src/freedreno/.gitlab-ci/reference/es2gears-a320.log b/src/freedreno/.gitlab-ci/reference/es2gears-a320.log
index a34bd7bd743..752bb40094a 100644
--- a/src/freedreno/.gitlab-ci/reference/es2gears-a320.log
+++ b/src/freedreno/.gitlab-ci/reference/es2gears-a320.log
@@ -2,129 +2,129 @@ gpu_id: 330
 cmd: es2gears/628: fence=276
 ############################################################
 cmdstream[0]: 488 dwords
-t3		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
+		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
 11848658:		0000: c0003b00 00007fff
-t0		write SP_VS_PVT_MEM_PARAM_REG (22d6)
+		write SP_VS_PVT_MEM_PARAM_REG (22d6)
 			SP_VS_PVT_MEM_PARAM_REG: { MEMSIZEPERITEM = 1 | HWSTACKOFFSET = 0 | HWSTACKSIZEPERTHREAD = 8 }
 			SP_VS_PVT_MEM_ADDR_REG: { BURSTLEN = 0 | SHADERSTARTADDRESS = 0x127f4000 }
 			SP_VS_PVT_MEM_SIZE_REG: 0
 11848660:		0000: 000222d6 08000001 127f4000 00000000
-t0		write SP_FS_PVT_MEM_PARAM_REG (22e4)
+		write SP_FS_PVT_MEM_PARAM_REG (22e4)
 			SP_FS_PVT_MEM_PARAM_REG: { MEMSIZEPERITEM = 1 | HWSTACKOFFSET = 0 | HWSTACKSIZEPERTHREAD = 8 }
 			SP_FS_PVT_MEM_ADDR_REG: { BURSTLEN = 0 | SHADERSTARTADDRESS = 0x127f6000 }
 			SP_FS_PVT_MEM_SIZE_REG: 0
 11848670:		0000: 000222e4 08000001 127f6000 00000000
-t0		write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+		write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 			PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11848680:		0000: 000021ea 0000000b
-t0		write GRAS_SC_CONTROL (2072)
+		write GRAS_SC_CONTROL (2072)
 			GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = MSAA_ONE | RASTER_MODE = 0 }
 11848688:		0000: 00002072 00000000
-t0		write RB_MSAA_CONTROL (20c2)
+		write RB_MSAA_CONTROL (20c2)
 			RB_MSAA_CONTROL: { DISABLE | SAMPLES = MSAA_ONE | SAMPLE_MASK = 0xffff }
 			RB_ALPHA_REF: { UINT = 0 | FLOAT = 0.000000 }
 11848690:		0000: 000120c2 ffff0400 00000000
-t0		write GRAS_CL_GB_CLIP_ADJ (2044)
+		write GRAS_CL_GB_CLIP_ADJ (2044)
 			GRAS_CL_GB_CLIP_ADJ: { HORZ = 0 | VERT = 0 }
 1184869c:		0000: 00002044 00000000
-t0		write GRAS_TSE_DEBUG_ECO (0c81)
+		write GRAS_TSE_DEBUG_ECO (0c81)
 			GRAS_TSE_DEBUG_ECO: 0x1
 118486a4:		0000: 00000c81 00000001
-t0		write TPL1_TP_VS_TEX_OFFSET (2340)
+		write TPL1_TP_VS_TEX_OFFSET (2340)
 			TPL1_TP_VS_TEX_OFFSET: { SAMPLEROFFSET = 0 | MEMOBJOFFSET = 0 | BASETABLEPTR = 0 }
 118486ac:		0000: 00002340 00000000
-t0		write TPL1_TP_FS_TEX_OFFSET (2342)
+		write TPL1_TP_FS_TEX_OFFSET (2342)
 			TPL1_TP_FS_TEX_OFFSET: { SAMPLEROFFSET = 16 | MEMOBJOFFSET = 16 | BASETABLEPTR = 224 }
 118486b4:		0000: 00002342 00e01010
-t0		write VPC_VARY_CYLWRAP_ENABLE_0 (228a)
+		write VPC_VARY_CYLWRAP_ENABLE_0 (228a)
 			VPC_VARY_CYLWRAP_ENABLE_0: 0
 			VPC_VARY_CYLWRAP_ENABLE_1: 0
 118486bc:		0000: 0001228a 00000000 00000000
-t0		write UNKNOWN_0E43 (0e43)
+		write UNKNOWN_0E43 (0e43)
 			UNKNOWN_0E43: 0x1
 118486c8:		0000: 00000e43 00000001
-t0		write UNKNOWN_0F03 (0f03)
+		write UNKNOWN_0F03 (0f03)
 			UNKNOWN_0F03: 0x1
 118486d0:		0000: 00000f03 00000001
-t0		write UNKNOWN_0EE0 (0ee0)
+		write UNKNOWN_0EE0 (0ee0)
 			UNKNOWN_0EE0: 0x3
 118486d8:		0000: 00000ee0 00000003
-t0		write UNKNOWN_0C3D (0c3d)
+		write UNKNOWN_0C3D (0c3d)
 			UNKNOWN_0C3D: 0x1
 118486e0:		0000: 00000c3d 00000001
-t0		write HLSQ_PERFCOUNTER0_SELECT (0e00)
+		write HLSQ_PERFCOUNTER0_SELECT (0e00)
 			HLSQ_PERFCOUNTER0_SELECT: HLSQ_PERF_SP_VS_CONSTANT
 118486e8:		0000: 00000e00 00000000
-t0		write HLSQ_CONST_VSPRESV_RANGE_REG (2206)
+		write HLSQ_CONST_VSPRESV_RANGE_REG (2206)
 			HLSQ_CONST_VSPRESV_RANGE_REG: { STARTENTRY = 0 | ENDENTRY = 0 }
 			HLSQ_CONST_FSPRESV_RANGE_REG: { STARTENTRY = 0 | ENDENTRY = 0 }
 118486f0:		0000: 00012206 00000000 00000000
-t0		write UCHE_CACHE_MODE_CONTROL_REG (0e82)
+		write UCHE_CACHE_MODE_CONTROL_REG (0e82)
 			UCHE_CACHE_MODE_CONTROL_REG: 0x1
 118486fc:		0000: 00000e82 00000001
-t0		write VSC_SIZE_ADDRESS (0c02)
+		write VSC_SIZE_ADDRESS (0c02)
 			VSC_SIZE_ADDRESS: 0x127f8000
 11848704:		0000: 00000c02 127f8000
-t0		write GRAS_CL_CLIP_CNTL (2040)
+		write GRAS_CL_CLIP_CNTL (2040)
 			GRAS_CL_CLIP_CNTL: { NUM_USER_CLIP_PLANES = 0 }
 1184870c:		0000: 00002040 00000000
-t0		write GRAS_SU_POINT_MINMAX (2068)
+		write GRAS_SU_POINT_MINMAX (2068)
 			GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 4092.000000 }
 			GRAS_SU_POINT_SIZE: 0.500000
 11848714:		0000: 00012068 ffc00010 00000008
-t0		write PC_RESTART_INDEX (21ed)
+		write PC_RESTART_INDEX (21ed)
 			PC_RESTART_INDEX: 0xffffffff
 11848720:		0000: 000021ed ffffffff
-t0		write RB_WINDOW_OFFSET (210e)
+		write RB_WINDOW_OFFSET (210e)
 			RB_WINDOW_OFFSET: { X = 0 | Y = 0 }
 11848728:		0000: 0000210e 00000000
-t0		write RB_BLEND_RED (20e4)
+		write RB_BLEND_RED (20e4)
 			RB_BLEND_RED: { UINT = 0 | FLOAT = 0.000000 }
 			RB_BLEND_GREEN: { UINT = 0 | FLOAT = 0.000000 }
 			RB_BLEND_BLUE: { UINT = 0 | FLOAT = 0.000000 }
 			RB_BLEND_ALPHA: { UINT = 0xff | FLOAT = 1.000000 }
 11848730:		0000: 000320e4 00000000 00000000 00000000 3c0000ff
-t0		write GRAS_CL_USER_PLANE[0].X (0ca0)
+		write GRAS_CL_USER_PLANE[0].X (0ca0)
 			GRAS_CL_USER_PLANE[0].X: 0
 			GRAS_CL_USER_PLANE[0].Y: 0
 			GRAS_CL_USER_PLANE[0].Z: 0
 			GRAS_CL_USER_PLANE[0].W: 0
 11848744:		0000: 00030ca0 00000000 00000000 00000000 00000000
-t0		write GRAS_CL_USER_PLANE[0x1].X (0ca4)
+		write GRAS_CL_USER_PLANE[0x1].X (0ca4)
 			GRAS_CL_USER_PLANE[0x1].X: 0
 			GRAS_CL_USER_PLANE[0x1].Y: 0
 			GRAS_CL_USER_PLANE[0x1].Z: 0
 			GRAS_CL_USER_PLANE[0x1].W: 0
 11848758:		0000: 00030ca4 00000000 00000000 00000000 00000000
-t0		write GRAS_CL_USER_PLANE[0x2].X (0ca8)
+		write GRAS_CL_USER_PLANE[0x2].X (0ca8)
 			GRAS_CL_USER_PLANE[0x2].X: 0
 			GRAS_CL_USER_PLANE[0x2].Y: 0
 			GRAS_CL_USER_PLANE[0x2].Z: 0
 			GRAS_CL_USER_PLANE[0x2].W: 0
 1184876c:		0000: 00030ca8 00000000 00000000 00000000 00000000
-t0		write GRAS_CL_USER_PLANE[0x3].X (0cac)
+		write GRAS_CL_USER_PLANE[0x3].X (0cac)
 			GRAS_CL_USER_PLANE[0x3].X: 0
 			GRAS_CL_USER_PLANE[0x3].Y: 0
 			GRAS_CL_USER_PLANE[0x3].Z: 0
 			GRAS_CL_USER_PLANE[0x3].W: 0
 11848780:		0000: 00030cac 00000000 00000000 00000000 00000000
-t0		write GRAS_CL_USER_PLANE[0x4].X (0cb0)
+		write GRAS_CL_USER_PLANE[0x4].X (0cb0)
 			GRAS_CL_USER_PLANE[0x4].X: 0
 			GRAS_CL_USER_PLANE[0x4].Y: 0
 			GRAS_CL_USER_PLANE[0x4].Z: 0
 			GRAS_CL_USER_PLANE[0x4].W: 0
 11848794:		0000: 00030cb0 00000000 00000000 00000000 00000000
-t0		write GRAS_CL_USER_PLANE[0x5].X (0cb4)
+		write GRAS_CL_USER_PLANE[0x5].X (0cb4)
 			GRAS_CL_USER_PLANE[0x5].X: 0
 			GRAS_CL_USER_PLANE[0x5].Y: 0
 			GRAS_CL_USER_PLANE[0x5].Z: 0
 			GRAS_CL_USER_PLANE[0x5].W: 0
 118487a8:		0000: 00030cb4 00000000 00000000 00000000 00000000
-t3		opcode: CP_EVENT_WRITE (46) (2 dwords)
+		opcode: CP_EVENT_WRITE (46) (2 dwords)
 			{ EVENT = CACHE_FLUSH }
 		event CACHE_FLUSH
 118487bc:		0000: c0004600 00000006
-t3		opcode: CP_DRAW_INDX (22) (4 dwords)
+		opcode: CP_DRAW_INDX (22) (4 dwords)
 			{ VIZ_QUERY = 0 }
 			{ PRIM_TYPE = DI_PT_POINTLIST_PSIZE | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 			{ NUM_INDICES = 0 }
@@ -133,122 +133,122 @@ t3		opcode: CP_DRAW_INDX (22) (4 dwords)
 		source_select: DI_SRC_SEL_AUTO_INDEX (2)
 		num_indices:   0
 118487c4:		0000: c0022200 00000000 00004081 00000000
-t3		opcode: CP_NOP (10) (5 dwords)
+		opcode: CP_NOP (10) (5 dwords)
 118487d4:		0000: c0031000 00000000 00000000 00000000 00000000
-t3		opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+		opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 118487e8:		0000: c0002600 00000000
-t0		write VSC_BIN_SIZE (0c01)
+		write VSC_BIN_SIZE (0c01)
 			VSC_BIN_SIZE: { WIDTH = 160 | HEIGHT = 320 }
 118487f0:		0000: 00000c01 00000145
-t0		write VSC_PIPE[0].CONFIG (0c06)
+		write VSC_PIPE[0].CONFIG (0c06)
 			VSC_PIPE[0].CONFIG: { X = 0 | Y = 0 | W = 2 | H = 1 }
 			VSC_PIPE[0].DATA_ADDRESS: 0x127f9000
 			VSC_PIPE[0].DATA_LENGTH: 0x3ffe0
 118487f8:		0000: 00020c06 01200000 127f9000 0003ffe0
-t0		write VSC_PIPE[0x1].CONFIG (0c09)
+		write VSC_PIPE[0x1].CONFIG (0c09)
 			VSC_PIPE[0x1].CONFIG: { X = 0 | Y = 0 | W = 0 | H = 0 }
 			VSC_PIPE[0x1].DATA_ADDRESS: 0
 			VSC_PIPE[0x1].DATA_LENGTH: 0
 11848808:		0000: 00020c09 00000000 00000000 00000000
-t0		write VSC_PIPE[0x2].CONFIG (0c0c)
+		write VSC_PIPE[0x2].CONFIG (0c0c)
 			VSC_PIPE[0x2].CONFIG: { X = 0 | Y = 0 | W = 0 | H = 0 }
 			VSC_PIPE[0x2].DATA_ADDRESS: 0
 			VSC_PIPE[0x2].DATA_LENGTH: 0
 11848818:		0000: 00020c0c 00000000 00000000 00000000
-t0		write VSC_PIPE[0x3].CONFIG (0c0f)
+		write VSC_PIPE[0x3].CONFIG (0c0f)
 			VSC_PIPE[0x3].CONFIG: { X = 0 | Y = 0 | W = 0 | H = 0 }
 			VSC_PIPE[0x3].DATA_ADDRESS: 0
 			VSC_PIPE[0x3].DATA_LENGTH: 0
 11848828:		0000: 00020c0f 00000000 00000000 00000000
-t0		write VSC_PIPE[0x4].CONFIG (0c12)
+		write VSC_PIPE[0x4].CONFIG (0c12)
 			VSC_PIPE[0x4].CONFIG: { X = 0 | Y = 0 | W = 0 | H = 0 }
 			VSC_PIPE[0x4].DATA_ADDRESS: 0
 			VSC_PIPE[0x4].DATA_LENGTH: 0
 11848838:		0000: 00020c12 00000000 00000000 00000000
-t0		write VSC_PIPE[0x5].CONFIG (0c15)
+		write VSC_PIPE[0x5].CONFIG (0c15)
 			VSC_PIPE[0x5].CONFIG: { X = 0 | Y = 0 | W = 0 | H = 0 }
 			VSC_PIPE[0x5].DATA_ADDRESS: 0
 			VSC_PIPE[0x5].DATA_LENGTH: 0
 11848848:		0000: 00020c15 00000000 00000000 00000000
-t0		write VSC_PIPE[0x6].CONFIG (0c18)
+		write VSC_PIPE[0x6].CONFIG (0c18)
 			VSC_PIPE[0x6].CONFIG: { X = 0 | Y = 0 | W = 0 | H = 0 }
 			VSC_PIPE[0x6].DATA_ADDRESS: 0
 			VSC_PIPE[0x6].DATA_LENGTH: 0
 11848858:		0000: 00020c18 00000000 00000000 00000000
-t0		write VSC_PIPE[0x7].CONFIG (0c1b)
+		write VSC_PIPE[0x7].CONFIG (0c1b)
 			VSC_PIPE[0x7].CONFIG: { X = 0 | Y = 0 | W = 0 | H = 0 }
 			VSC_PIPE[0x7].DATA_ADDRESS: 0
 			VSC_PIPE[0x7].DATA_LENGTH: 0
 11848868:		0000: 00020c1b 00000000 00000000 00000000
-t0		write RB_DEPTH_INFO (2102)
+		write RB_DEPTH_INFO (2102)
 			RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTHX_16 | DEPTH_BASE = 0x40000 }
 			RB_DEPTH_PITCH: 320
 11848878:		0000: 00012102 00020000 00000028
-t0		write RB_FRAME_BUFFER_DIMENSION (0ce0)
+		write RB_FRAME_BUFFER_DIMENSION (0ce0)
 			RB_FRAME_BUFFER_DIMENSION: { WIDTH = 300 | HEIGHT = 300 }
 11848884:		0000: 00000ce0 004b012c
-t0		write RB_MODE_CONTROL (20c0)
+		write RB_MODE_CONTROL (20c0)
 			RB_MODE_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MRT = 0 | MARB_CACHE_SPLIT_MODE }
 1184888c:		0000: 000020c0 00008000
-t3		opcode: (null) (4c) (4 dwords)
+		opcode: (null) (4c) (4 dwords)
 11848894:		0000: c0024c00 00000000 00000000 012b009f
-t0		write RB_MRT[0].BUF_INFO (20c5)
+		write RB_MRT[0].BUF_INFO (20c5)
 			RB_MRT[0].BUF_INFO: { COLOR_FORMAT = RB_R8G8B8A8_UNORM | COLOR_TILE_MODE = TILE_32X32 | COLOR_SWAP = WXYZ | COLOR_BUF_PITCH = 640 }
 			RB_MRT[0].BUF_BASE: { COLOR_BUF_BASE = 0 }
 118488a4:		0000: 000120c5 00280488 00000000
-t0		write SP_FS_IMAGE_OUTPUT[0].REG (22f4)
+		write SP_FS_IMAGE_OUTPUT[0].REG (22f4)
 			SP_FS_IMAGE_OUTPUT[0].REG: { MRTFORMAT = RB_R8G8B8A8_UNORM }
 118488b0:		0000: 000022f4 00000008
-t0		write RB_MRT[0x1].BUF_INFO (20c9)
+		write RB_MRT[0x1].BUF_INFO (20c9)
 			RB_MRT[0x1].BUF_INFO: { COLOR_FORMAT = RB_R5G6B5_UNORM | COLOR_TILE_MODE = TILE_32X32 | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 0 }
 			RB_MRT[0x1].BUF_BASE: { COLOR_BUF_BASE = 0 }
 118488b8:		0000: 000120c9 00000080 00000000
-t0		write SP_FS_IMAGE_OUTPUT[0x1].REG (22f5)
+		write SP_FS_IMAGE_OUTPUT[0x1].REG (22f5)
 			SP_FS_IMAGE_OUTPUT[0x1].REG: { MRTFORMAT = RB_R5G6B5_UNORM }
 118488c4:		0000: 000022f5 00000000
-t0		write RB_MRT[0x2].BUF_INFO (20cd)
+		write RB_MRT[0x2].BUF_INFO (20cd)
 			RB_MRT[0x2].BUF_INFO: { COLOR_FORMAT = RB_R5G6B5_UNORM | COLOR_TILE_MODE = TILE_32X32 | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 0 }
 			RB_MRT[0x2].BUF_BASE: { COLOR_BUF_BASE = 0 }
 118488cc:		0000: 000120cd 00000080 00000000
-t0		write SP_FS_IMAGE_OUTPUT[0x2].REG (22f6)
+		write SP_FS_IMAGE_OUTPUT[0x2].REG (22f6)
 			SP_FS_IMAGE_OUTPUT[0x2].REG: { MRTFORMAT = RB_R5G6B5_UNORM }
 118488d8:		0000: 000022f6 00000000
-t0		write RB_MRT[0x3].BUF_INFO (20d1)
+		write RB_MRT[0x3].BUF_INFO (20d1)
 			RB_MRT[0x3].BUF_INFO: { COLOR_FORMAT = RB_R5G6B5_UNORM | COLOR_TILE_MODE = TILE_32X32 | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 0 }
 			RB_MRT[0x3].BUF_BASE: { COLOR_BUF_BASE = 0 }
 118488e0:		0000: 000120d1 00000080 00000000
-t0		write SP_FS_IMAGE_OUTPUT[0x3].REG (22f7)
+		write SP_FS_IMAGE_OUTPUT[0x3].REG (22f7)
 			SP_FS_IMAGE_OUTPUT[0x3].REG: { MRTFORMAT = RB_R5G6B5_UNORM }
 118488ec:		0000: 000022f7 00000000
-t3		opcode: CP_REG_RMW (21) (4 dwords)
+		opcode: CP_REG_RMW (21) (4 dwords)
 			{ DST_REG = 0x20c1 | ROTATE = 0 }
 			{ SRC0 = 4294955023 }
 			{ SRC1 = 8272 }
 		rmw (RB_RENDER_CONTROL & 0xffffd00f) | 0x00002050)
 118488f4:		0000: c0022100 000020c1 ffffd00f 00002050
-t0		write RB_WINDOW_OFFSET (210e)
+		write RB_WINDOW_OFFSET (210e)
 			RB_WINDOW_OFFSET: { X = 0 | Y = 0 }
 11848904:		0000: 0000210e 00000000
-t0		write GRAS_SC_SCREEN_SCISSOR_TL (2074)
+		write GRAS_SC_SCREEN_SCISSOR_TL (2074)
 			GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 }
 			GRAS_SC_SCREEN_SCISSOR_BR: { X = 159 | Y = 299 }
 1184890c:		0000: 00012074 00000000 012b009f
-t0		write CP_SCRATCH_REG6 (057e)
+		write CP_SCRATCH_REG6 (057e)
 			CP_SCRATCH_REG6: 12814
 			:0,0,12814,0
 11848918:		0000: 0000057e 0000320e
-t3		opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
+		opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
 		ibaddr:11842370
 		ibsize:000018ba
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 				CP_SCRATCH_REG5: 11971
 				:0,11971,12814,0
 11842370:			0000: 0000057d 00002ec3
-t0			write GRAS_SC_WINDOW_SCISSOR_TL (2079)
+			write GRAS_SC_WINDOW_SCISSOR_TL (2079)
 				GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
 				GRAS_SC_WINDOW_SCISSOR_BR: { X = 299 | Y = 299 }
 11842378:			0000: 00012079 00000000 012b012b
-t0			write GRAS_CL_VPORT_XOFFSET (2048)
+			write GRAS_CL_VPORT_XOFFSET (2048)
 				GRAS_CL_VPORT_XOFFSET: 149.500000
 				GRAS_CL_VPORT_XSCALE: 150.000000
 				GRAS_CL_VPORT_YOFFSET: 149.500000
@@ -256,57 +256,57 @@ t0			write GRAS_CL_VPORT_XOFFSET (2048)
 				GRAS_CL_VPORT_ZOFFSET: 0.500000
 				GRAS_CL_VPORT_ZSCALE: 0.500000
 11842384:			0000: 00052048 43158000 43160000 43158000 c3160000 3f000000 3f000000
-t0			write RB_BLEND_ALPHA (20e7)
+			write RB_BLEND_ALPHA (20e7)
 				RB_BLEND_ALPHA: { UINT = 0xff | FLOAT = 1.000000 }
 118423a0:			0000: 000020e7 3c0000ff
-t3			opcode: CP_REG_RMW (21) (4 dwords)
+			opcode: CP_REG_RMW (21) (4 dwords)
 				{ DST_REG = 0x20c1 | ROTATE = 0 }
 				{ SRC0 = 12272 }
 				{ SRC1 = 0 }
 			rmw (RB_RENDER_CONTROL & 0x00002ff0) | 0x00000000)
 118423a8:			0000: c0022100 000020c1 00002ff0 00000000
-t0			write RB_DEPTH_CONTROL (2100)
+			write RB_DEPTH_CONTROL (2100)
 				RB_DEPTH_CONTROL: { Z_TEST_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_ALWAYS }
 118423b8:			0000: 00002100 00000076
-t0			write GRAS_CL_VPORT_ZOFFSET (204c)
+			write GRAS_CL_VPORT_ZOFFSET (204c)
 				GRAS_CL_VPORT_ZOFFSET: 0.000000
 				GRAS_CL_VPORT_ZSCALE: 1.000000
 118423c0:			0000: 0001204c 00000000 3f800000
-t0			write RB_STENCILREFMASK (2108)
+			write RB_STENCILREFMASK (2108)
 				RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
 				RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
 118423cc:			0000: 00012108 00000000 00000000
-t0			write RB_STENCIL_CONTROL (2104)
+			write RB_STENCIL_CONTROL (2104)
 				RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP }
 118423d8:			0000: 00002104 00000000
-t0			write RB_MRT[0].CONTROL (20c4)
+			write RB_MRT[0].CONTROL (20c4)
 				RB_MRT[0].CONTROL: { ROP_CODE = ROP_COPY | DITHER_MODE = DITHER_ALWAYS | COMPONENT_ENABLE = 0xf }
 118423e0:			0000: 000020c4 0f001c00
-t0			write RB_MRT[0].BLEND_CONTROL (20c7)
+			write RB_MRT[0].BLEND_CONTROL (20c7)
 				RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ONE | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ONE | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO | CLAMP_ENABLE }
 118423e8:			0000: 000020c7 20010001
-t0			write RB_MRT[0x1].CONTROL (20c8)
+			write RB_MRT[0x1].CONTROL (20c8)
 				RB_MRT[0x1].CONTROL: { ROP_CODE = ROP_COPY | DITHER_MODE = DITHER_ALWAYS | COMPONENT_ENABLE = 0xf }
 118423f0:			0000: 000020c8 0f001c00
-t0			write RB_MRT[0x1].BLEND_CONTROL (20cb)
+			write RB_MRT[0x1].BLEND_CONTROL (20cb)
 				RB_MRT[0x1].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ONE | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ONE | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO | CLAMP_ENABLE }
 118423f8:			0000: 000020cb 20010001
-t0			write RB_MRT[0x2].CONTROL (20cc)
+			write RB_MRT[0x2].CONTROL (20cc)
 				RB_MRT[0x2].CONTROL: { ROP_CODE = ROP_COPY | DITHER_MODE = DITHER_ALWAYS | COMPONENT_ENABLE = 0xf }
 11842400:			0000: 000020cc 0f001c00
-t0			write RB_MRT[0x2].BLEND_CONTROL (20cf)
+			write RB_MRT[0x2].BLEND_CONTROL (20cf)
 				RB_MRT[0x2].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ONE | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ONE | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO | CLAMP_ENABLE }
 11842408:			0000: 000020cf 20010001
-t0			write RB_MRT[0x3].CONTROL (20d0)
+			write RB_MRT[0x3].CONTROL (20d0)
 				RB_MRT[0x3].CONTROL: { ROP_CODE = ROP_COPY | DITHER_MODE = DITHER_ALWAYS | COMPONENT_ENABLE = 0xf }
 11842410:			0000: 000020d0 0f001c00
-t0			write RB_MRT[0x3].BLEND_CONTROL (20d3)
+			write RB_MRT[0x3].BLEND_CONTROL (20d3)
 				RB_MRT[0x3].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ONE | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ONE | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO | CLAMP_ENABLE }
 11842418:			0000: 000020d3 20010001
-t0			write GRAS_SU_MODE_CONTROL (2070)
+			write GRAS_SU_MODE_CONTROL (2070)
 				GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 }
 11842420:			0000: 00002070 00000000
-t0			write HLSQ_CONTROL_0_REG (2200)
+			write HLSQ_CONTROL_0_REG (2200)
 				HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | SPSHADERRESTART | CYCLETIMEOUTLIMITVPC = 0 | CONSTMODE = 0 | SPCONSTFULLUPDATE }
 				HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | FRAGCOORDXYREGID = r0.x | FRAGCOORDZWREGID = r0.x }
 				HLSQ_CONTROL_2_REG: { FACENESSREGID = r0.x | COVVALUEREGID = r0.x | PRIMALLOCTHRESHOLD = 31 }
@@ -314,112 +314,112 @@ t0			write HLSQ_CONTROL_0_REG (2200)
 				HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTSTARTOFFSET = 0 | INSTRLENGTH = 1 }
 				HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 1 | CONSTSTARTOFFSET = 128 | INSTRLENGTH = 1 }
 11842428:			0000: 00052200 20000210 00000100 7c000000 00000000 01000000 01080001
-t0			write SP_SP_CTRL_REG (22c0)
+			write SP_SP_CTRL_REG (22c0)
 				SP_SP_CTRL_REG: { CONSTMODE = 0 | SLEEPMODE = 1 | L0MODE = 1 }
 11842444:			0000: 000022c0 00500000
-t0			write SP_VS_LENGTH_REG (22df)
+			write SP_VS_LENGTH_REG (22df)
 				SP_VS_LENGTH_REG: { SHADERLENGTH = 1 }
 1184244c:			0000: 000022df 00000001
-t0			write SP_VS_CTRL_REG0 (22c4)
+			write SP_VS_CTRL_REG0 (22c4)
 				SP_VS_CTRL_REG0: { THREADMODE = MULTI | INSTRBUFFERMODE = BUFFER | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE | LENGTH = 1 }
 				SP_VS_CTRL_REG1: { CONSTLENGTH = 0 | CONSTFOOTPRINT = 0 | INITIALOUTSTANDING = 4 }
 				SP_VS_PARAM_REG: { POSREGID = r0.x | PSIZEREGID = r63.x | TOTALVSOUTVAR = 0 }
 11842454:			0000: 000222c4 01200402 04000000 0000fc00
-t0			write SP_FS_LENGTH_REG (22ff)
+			write SP_FS_LENGTH_REG (22ff)
 				SP_FS_LENGTH_REG: { SHADERLENGTH = 1 }
 11842464:			0000: 000022ff 00000001
-t0			write SP_FS_CTRL_REG0 (22e0)
+			write SP_FS_CTRL_REG0 (22e0)
 				SP_FS_CTRL_REG0: { THREADMODE = MULTI | INSTRBUFFERMODE = BUFFER | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 0 | INOUTREGOVERLAP | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE | LENGTH = 1 }
 				SP_FS_CTRL_REG1: { CONSTLENGTH = 1 | CONSTFOOTPRINT = 0 | INITIALOUTSTANDING = 0 | HALFPRECVAROFFSET = 63 }
 1184246c:			0000: 000122e0 01340012 3f000001
-t0			write SP_FS_FLAT_SHAD_MODE_REG_0 (22e8)
+			write SP_FS_FLAT_SHAD_MODE_REG_0 (22e8)
 				SP_FS_FLAT_SHAD_MODE_REG_0: 0
 				SP_FS_FLAT_SHAD_MODE_REG_1: 0
 11842478:			0000: 000122e8 00000000 00000000
-t0			write SP_FS_OUTPUT_REG (22ec)
+			write SP_FS_OUTPUT_REG (22ec)
 				SP_FS_OUTPUT_REG: { MRT = 0 | DEPTH_REGID = r0.x }
 11842484:			0000: 000022ec 00000000
-t0			write SP_FS_MRT[0].REG (22f0)
+			write SP_FS_MRT[0].REG (22f0)
 				SP_FS_MRT[0].REG: { REGID = r0.x | HALF_PRECISION }
 				SP_FS_MRT[0x1].REG: { REGID = r0.x }
 				SP_FS_MRT[0x2].REG: { REGID = r0.x }
 				SP_FS_MRT[0x3].REG: { REGID = r0.x }
 1184248c:			0000: 000322f0 00000100 00000000 00000000 00000000
-t0			write VPC_ATTR (2280)
+			write VPC_ATTR (2280)
 				VPC_ATTR: { TOTALATTR = 0 | THRDASSIGN = 1 | LMSIZE = 1 }
 				VPC_PACK: { NUMFPNONPOSVAR = 0 | NUMNONPOSVSVAR = 0 }
 118424a0:			0000: 00012280 10001000 00000000
-t0			write VPC_VARYING_INTERP[0].MODE (2282)
+			write VPC_VARYING_INTERP[0].MODE (2282)
 				VPC_VARYING_INTERP[0].MODE: { C0 = SMOOTH | C1 = SMOOTH | C2 = SMOOTH | C3 = SMOOTH | C4 = SMOOTH | C5 = SMOOTH | C6 = SMOOTH | C7 = SMOOTH | C8 = SMOOTH | C9 = SMOOTH | CA = SMOOTH | CB = SMOOTH | CC = SMOOTH | CD = SMOOTH | CE = SMOOTH | CF = SMOOTH }
 				VPC_VARYING_INTERP[0x1].MODE: { C0 = SMOOTH | C1 = SMOOTH | C2 = SMOOTH | C3 = SMOOTH | C4 = SMOOTH | C5 = SMOOTH | C6 = SMOOTH | C7 = SMOOTH | C8 = SMOOTH | C9 = SMOOTH | CA = SMOOTH | CB = SMOOTH | CC = SMOOTH | CD = SMOOTH | CE = SMOOTH | CF = SMOOTH }
 				VPC_VARYING_INTERP[0x2].MODE: { C0 = SMOOTH | C1 = SMOOTH | C2 = SMOOTH | C3 = SMOOTH | C4 = SMOOTH | C5 = SMOOTH | C6 = SMOOTH | C7 = SMOOTH | C8 = SMOOTH | C9 = SMOOTH | CA = SMOOTH | CB = SMOOTH | CC = SMOOTH | CD = SMOOTH | CE = SMOOTH | CF = SMOOTH }
 				VPC_VARYING_INTERP[0x3].MODE: { C0 = SMOOTH | C1 = SMOOTH | C2 = SMOOTH | C3 = SMOOTH | C4 = SMOOTH | C5 = SMOOTH | C6 = SMOOTH | C7 = SMOOTH | C8 = SMOOTH | C9 = SMOOTH | CA = SMOOTH | CB = SMOOTH | CC = SMOOTH | CD = SMOOTH | CE = SMOOTH | CF = SMOOTH }
 118424ac:			0000: 00032282 00000000 00000000 00000000 00000000
-t0			write VPC_VARYING_PS_REPL[0].MODE (2286)
+			write VPC_VARYING_PS_REPL[0].MODE (2286)
 				VPC_VARYING_PS_REPL[0].MODE: { C0 = 0 | C1 = 0 | C2 = 0 | C3 = 0 | C4 = 0 | C5 = 0 | C6 = 0 | C7 = 0 | C8 = 0 | C9 = 0 | CA = 0 | CB = 0 | CC = 0 | CD = 0 | CE = 0 | CF = 0 }
 				VPC_VARYING_PS_REPL[0x1].MODE: { C0 = 0 | C1 = 0 | C2 = 0 | C3 = 0 | C4 = 0 | C5 = 0 | C6 = 0 | C7 = 0 | C8 = 0 | C9 = 0 | CA = 0 | CB = 0 | CC = 0 | CD = 0 | CE = 0 | CF = 0 }
 				VPC_VARYING_PS_REPL[0x2].MODE: { C0 = 0 | C1 = 0 | C2 = 0 | C3 = 0 | C4 = 0 | C5 = 0 | C6 = 0 | C7 = 0 | C8 = 0 | C9 = 0 | CA = 0 | CB = 0 | CC = 0 | CD = 0 | CE = 0 | CF = 0 }
 				VPC_VARYING_PS_REPL[0x3].MODE: { C0 = 0 | C1 = 0 | C2 = 0 | C3 = 0 | C4 = 0 | C5 = 0 | C6 = 0 | C7 = 0 | C8 = 0 | C9 = 0 | CA = 0 | CB = 0 | CC = 0 | CD = 0 | CE = 0 | CF = 0 }
 118424c0:			0000: 00032286 00000000 00000000 00000000 00000000
-t0			write VFD_VS_THREADING_THRESHOLD (227e)
+			write VFD_VS_THREADING_THRESHOLD (227e)
 				VFD_VS_THREADING_THRESHOLD: { REGID_THRESHOLD = 15 | REGID_VTXCNT = r63.x }
 118424d4:			0000: 0000227e 0000fc0f
-t3			opcode: CP_LOAD_STATE (30) (3 dwords)
+			opcode: CP_LOAD_STATE (30) (3 dwords)
 				{ DST_OFF = 0 | STATE_SRC = SS_INDIRECT | STATE_BLOCK = SB_VERT_SHADER | NUM_UNIT = 1 }
 				{ STATE_TYPE = ST_SHADER | EXT_SRC_ADDR = 0x117e2000 }
 118424dc:			0000: c0013000 00640000 117e2000
-t0			write VFD_PERFCOUNTER0_SELECT (0e44)
+			write VFD_PERFCOUNTER0_SELECT (0e44)
 				VFD_PERFCOUNTER0_SELECT: VFD_PERF_UCHE_BYTE_FETCHED
 118424e8:			0000: 00000e44 00000000
-t3			opcode: CP_LOAD_STATE (30) (3 dwords)
+			opcode: CP_LOAD_STATE (30) (3 dwords)
 				{ DST_OFF = 0 | STATE_SRC = SS_INDIRECT | STATE_BLOCK = SB_FRAG_SHADER | NUM_UNIT = 1 }
 				{ STATE_TYPE = ST_SHADER | EXT_SRC_ADDR = 0x117e1000 }
 118424f0:			0000: c0013000 00740000 117e1000
-t0			write VFD_PERFCOUNTER0_SELECT (0e44)
+			write VFD_PERFCOUNTER0_SELECT (0e44)
 				VFD_PERFCOUNTER0_SELECT: VFD_PERF_UCHE_BYTE_FETCHED
 118424fc:			0000: 00000e44 00000000
-t0			write VFD_CONTROL_0 (2240)
+			write VFD_CONTROL_0 (2240)
 				VFD_CONTROL_0: { TOTALATTRTOVS = 4 | PACKETSIZE = 2 | STRMDECINSTRCNT = 1 | STRMFETCHINSTRCNT = 1 }
 				VFD_CONTROL_1: { MAXSTORAGE = 1 | MAXTHRESHOLD = 0 | MINTHRESHOLD = 0 | REGID4VTX = r63.x | REGID4INST = r63.x }
 11842504:			0000: 00012240 08480004 fcfc0001
-t0			write VFD_FETCH[0].INSTR_0 (2246)
+			write VFD_FETCH[0].INSTR_0 (2246)
 				VFD_FETCH[0].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 12 | INDEXCODE = 0 | STEPRATE = 1 }
 				VFD_FETCH[0].INSTR_1: 0x127e9000
 11842510:			0000: 00012246 0100060b 127e9000
-t0			write VFD_DECODE[0].INSTR (2266)
+			write VFD_DECODE[0].INSTR (2266)
 				VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID }
 1184251c:			0000: 00002266 2c00009f
-t0			write UCHE_CACHE_INVALIDATE0_REG (0ea0)
+			write UCHE_CACHE_INVALIDATE0_REG (0ea0)
 				UCHE_CACHE_INVALIDATE0_REG: { ADDR = 0 }
 				UCHE_CACHE_INVALIDATE1_REG: { ADDR = 0 | OPCODE = INVALIDATE | ENTIRE_CACHE }
 11842524:			0000: 00010ea0 00000000 90000000
-t3			opcode: CP_LOAD_STATE (30) (7 dwords)
+			opcode: CP_LOAD_STATE (30) (7 dwords)
 				{ DST_OFF = 0 | STATE_SRC = SS_DIRECT | STATE_BLOCK = SB_FRAG_SHADER | NUM_UNIT = 2 }
 				{ STATE_TYPE = ST_CONSTANTS | EXT_SRC_ADDR = 0 }
 1184253c:				0.000000 0.000000 0.000000 1.000000
 1184253c:				0000: 00000000 00000000 00000000 3f800000
 11842530:			0000: c0053000 00b00000 00000001 00000000 00000000 00000000 3f800000
-t0			write PC_PRIM_VTX_CNTL (21ec)
+			write PC_PRIM_VTX_CNTL (21ec)
 				PC_PRIM_VTX_CNTL: { STRIDE_IN_VPC = 0 | POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES | PROVOKING_VTX_LAST }
 1184254c:			0000: 000021ec 02000240
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 0
 				VFD_INDEX_MAX: 2
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 0
 11842554:			0000: 00032242 00000000 00000002 00000000 00000000
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11842568:			0000: 000021ed ffffffff
-t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = PERFCOUNTER_STOP }
 			event PERFCOUNTER_STOP
 11842570:			0000: c0004600 00000018
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 11972
 				:0,11971,12814,11972
 11842578:			0000: 0000057f 00002ec4
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 2 }
@@ -603,57 +603,57 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			TPL1_TP_VS_TEX_OFFSET: { SAMPLEROFFSET = 0 | MEMOBJOFFSET = 0 | BASETABLEPTR = 0 }
 !+	00e01010			TPL1_TP_FS_TEX_OFFSET: { SAMPLEROFFSET = 16 | MEMOBJOFFSET = 16 | BASETABLEPTR = 224 }
 11842580:			0000: c0022200 00000000 00004088 00000002
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 11973
 				:0,11971,12814,11973
 11842590:			0000: 0000057f 00002ec5
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11842598:			0000: c0002600 00000000
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 				CP_SCRATCH_REG5: 11974
 				:0,11974,12814,11973
 118425a0:			0000: 0000057d 00002ec6
-t0			write RB_MSAA_CONTROL (20c2)
+			write RB_MSAA_CONTROL (20c2)
 				RB_MSAA_CONTROL: { DISABLE | SAMPLES = MSAA_ONE | SAMPLE_MASK = 0xffff }
 118425a8:			0000: 000020c2 ffff0400
-t3			opcode: CP_REG_RMW (21) (4 dwords)
+			opcode: CP_REG_RMW (21) (4 dwords)
 				{ DST_REG = 0x20c1 | ROTATE = 0 }
 				{ SRC0 = 12272 }
 				{ SRC1 = 0 }
 			rmw (RB_RENDER_CONTROL & 0x00002ff0) | 0x00000000)
 118425b0:			0000: c0022100 000020c1 00002ff0 00000000
-t0			write RB_ALPHA_REF (20c3)
+			write RB_ALPHA_REF (20c3)
 				RB_ALPHA_REF: { UINT = 0 | FLOAT = 0.000000 }
 118425c0:			0000: 000020c3 00000000
-t0			write RB_DEPTH_CONTROL (2100)
+			write RB_DEPTH_CONTROL (2100)
 				RB_DEPTH_CONTROL: { Z_TEST_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_READ_ENABLE }
 118425c8:			0000: 00002100 80000016
-t0			write RB_STENCIL_CONTROL (2104)
+			write RB_STENCIL_CONTROL (2104)
 				RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP }
 118425d0:			0000: 00002104 00000000
-t0			write RB_STENCILREFMASK (2108)
+			write RB_STENCILREFMASK (2108)
 				RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
 				RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
 118425d8:			0000: 00012108 00000000 00000000
-t0			write GRAS_SU_MODE_CONTROL (2070)
+			write GRAS_SU_MODE_CONTROL (2070)
 				GRAS_SU_MODE_CONTROL: { CULL_BACK | LINEHALFWIDTH = 0.500000 }
 118425e4:			0000: 00002070 00000012
-t0			write GRAS_SU_POINT_MINMAX (2068)
+			write GRAS_SU_POINT_MINMAX (2068)
 				GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 4092.000000 }
 				GRAS_SU_POINT_SIZE: 0.500000
 118425ec:			0000: 00012068 ffc00010 00000008
-t0			write GRAS_SU_POLY_OFFSET_SCALE (206c)
+			write GRAS_SU_POLY_OFFSET_SCALE (206c)
 				GRAS_SU_POLY_OFFSET_SCALE: { VAL = 0.000000 }
 				GRAS_SU_POLY_OFFSET_OFFSET: 0.000000
 118425f8:			0000: 0001206c 00000000 00000000
-t0			write GRAS_CL_CLIP_CNTL (2040)
+			write GRAS_CL_CLIP_CNTL (2040)
 				GRAS_CL_CLIP_CNTL: { IJ_PERSP_CENTER | NUM_USER_CLIP_PLANES = 0 }
 11842604:			0000: 00002040 00001000
-t0			write PC_PRIM_VTX_CNTL (21ec)
+			write PC_PRIM_VTX_CNTL (21ec)
 				PC_PRIM_VTX_CNTL: { STRIDE_IN_VPC = 2 | POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES | PROVOKING_VTX_LAST }
 1184260c:			0000: 000021ec 02000242
-t0			write GRAS_CL_VPORT_XOFFSET (2048)
+			write GRAS_CL_VPORT_XOFFSET (2048)
 				GRAS_CL_VPORT_XOFFSET: 149.500000
 				GRAS_CL_VPORT_XSCALE: 150.000000
 				GRAS_CL_VPORT_YOFFSET: 149.500000
@@ -661,7 +661,7 @@ t0			write GRAS_CL_VPORT_XOFFSET (2048)
 				GRAS_CL_VPORT_ZOFFSET: 0.500000
 				GRAS_CL_VPORT_ZSCALE: 0.500000
 11842614:			0000: 00052048 43158000 43160000 43158000 c3160000 3f000000 3f000000
-t0			write HLSQ_CONTROL_0_REG (2200)
+			write HLSQ_CONTROL_0_REG (2200)
 				HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | SPSHADERRESTART | CYCLETIMEOUTLIMITVPC = 0 | CONSTMODE = 0 | SPCONSTFULLUPDATE }
 				HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | FRAGCOORDXYREGID = r0.x | FRAGCOORDZWREGID = r0.x }
 				HLSQ_CONTROL_2_REG: { FACENESSREGID = r0.x | COVVALUEREGID = r0.x | PRIMALLOCTHRESHOLD = 31 }
@@ -669,85 +669,85 @@ t0			write HLSQ_CONTROL_0_REG (2200)
 				HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 11 | CONSTSTARTOFFSET = 0 | INSTRLENGTH = 36 }
 				HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTSTARTOFFSET = 128 | INSTRLENGTH = 4 }
 11842630:			0000: 00052200 20000210 00000100 7c000000 00000000 2400000b 04080000
-t0			write SP_SP_CTRL_REG (22c0)
+			write SP_SP_CTRL_REG (22c0)
 				SP_SP_CTRL_REG: { CONSTMODE = 0 | SLEEPMODE = 1 | L0MODE = 1 }
 1184264c:			0000: 000022c0 00500000
-t0			write SP_VS_LENGTH_REG (22df)
+			write SP_VS_LENGTH_REG (22df)
 				SP_VS_LENGTH_REG: { SHADERLENGTH = 36 }
 11842654:			0000: 000022df 00000024
-t0			write SP_VS_CTRL_REG0 (22c4)
+			write SP_VS_CTRL_REG0 (22c4)
 				SP_VS_CTRL_REG0: { THREADMODE = MULTI | INSTRBUFFERMODE = BUFFER | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 8 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE | LENGTH = 36 }
 				SP_VS_CTRL_REG1: { CONSTLENGTH = 11 | CONSTFOOTPRINT = 10 | INITIALOUTSTANDING = 8 }
 				SP_VS_PARAM_REG: { POSREGID = r2.x | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 }
 1184265c:			0000: 000222c4 24202002 0800280b 0010fc08
-t0			write SP_VS_OUT[0].REG (22c7)
+			write SP_VS_OUT[0].REG (22c7)
 				SP_VS_OUT[0].REG: { A_REGID = r3.x | A_COMPMASK = 0xf | B_REGID = r2.x | B_COMPMASK = 0 }
 1184266c:			0000: 000022c7 00081e0c
-t0			write SP_VS_VPC_DST[0].REG (22d0)
+			write SP_VS_VPC_DST[0].REG (22d0)
 				SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 }
 11842674:			0000: 000022d0 00000008
-t0			write SP_FS_LENGTH_REG (22ff)
+			write SP_FS_LENGTH_REG (22ff)
 				SP_FS_LENGTH_REG: { SHADERLENGTH = 4 }
 1184267c:			0000: 000022ff 00000004
-t0			write SP_FS_CTRL_REG0 (22e0)
+			write SP_FS_CTRL_REG0 (22e0)
 				SP_FS_CTRL_REG0: { THREADMODE = MULTI | INSTRBUFFERMODE = BUFFER | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE | LENGTH = 4 }
 				SP_FS_CTRL_REG1: { CONSTLENGTH = 0 | CONSTFOOTPRINT = 0 | INITIALOUTSTANDING = 4 | HALFPRECVAROFFSET = 63 }
 11842684:			0000: 000122e0 04340c02 3f400000
-t0			write SP_FS_FLAT_SHAD_MODE_REG_0 (22e8)
+			write SP_FS_FLAT_SHAD_MODE_REG_0 (22e8)
 				SP_FS_FLAT_SHAD_MODE_REG_0: 0
 				SP_FS_FLAT_SHAD_MODE_REG_1: 0
 11842690:			0000: 000122e8 00000000 00000000
-t0			write SP_FS_OUTPUT_REG (22ec)
+			write SP_FS_OUTPUT_REG (22ec)
 				SP_FS_OUTPUT_REG: { MRT = 0 | DEPTH_REGID = r0.x }
 1184269c:			0000: 000022ec 00000000
-t0			write SP_FS_MRT[0].REG (22f0)
+			write SP_FS_MRT[0].REG (22f0)
 				SP_FS_MRT[0].REG: { REGID = r2.x }
 				SP_FS_MRT[0x1].REG: { REGID = r0.x }
 				SP_FS_MRT[0x2].REG: { REGID = r0.x }
 				SP_FS_MRT[0x3].REG: { REGID = r0.x }
 118426a4:			0000: 000322f0 00000008 00000000 00000000 00000000
-t0			write VPC_ATTR (2280)
+			write VPC_ATTR (2280)
 				VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | LMSIZE = 1 }
 				VPC_PACK: { NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 }
 118426b8:			0000: 00012280 10001004 00040400
-t0			write VPC_VARYING_INTERP[0].MODE (2282)
+			write VPC_VARYING_INTERP[0].MODE (2282)
 				VPC_VARYING_INTERP[0].MODE: { C0 = SMOOTH | C1 = SMOOTH | C2 = SMOOTH | C3 = SMOOTH | C4 = SMOOTH | C5 = SMOOTH | C6 = SMOOTH | C7 = SMOOTH | C8 = SMOOTH | C9 = SMOOTH | CA = SMOOTH | CB = SMOOTH | CC = SMOOTH | CD = SMOOTH | CE = SMOOTH | CF = SMOOTH }
 				VPC_VARYING_INTERP[0x1].MODE: { C0 = SMOOTH | C1 = SMOOTH | C2 = SMOOTH | C3 = SMOOTH | C4 = SMOOTH | C5 = SMOOTH | C6 = SMOOTH | C7 = SMOOTH | C8 = SMOOTH | C9 = SMOOTH | CA = SMOOTH | CB = SMOOTH | CC = SMOOTH | CD = SMOOTH | CE = SMOOTH | CF = SMOOTH }
 				VPC_VARYING_INTERP[0x2].MODE: { C0 = SMOOTH | C1 = SMOOTH | C2 = SMOOTH | C3 = SMOOTH | C4 = SMOOTH | C5 = SMOOTH | C6 = SMOOTH | C7 = SMOOTH | C8 = SMOOTH | C9 = SMOOTH | CA = SMOOTH | CB = SMOOTH | CC = SMOOTH | CD = SMOOTH | CE = SMOOTH | CF = SMOOTH }
 				VPC_VARYING_INTERP[0x3].MODE: { C0 = SMOOTH | C1 = SMOOTH | C2 = SMOOTH | C3 = SMOOTH | C4 = SMOOTH | C5 = SMOOTH | C6 = SMOOTH | C7 = SMOOTH | C8 = SMOOTH | C9 = SMOOTH | CA = SMOOTH | CB = SMOOTH | CC = SMOOTH | CD = SMOOTH | CE = SMOOTH | CF = SMOOTH }
 118426c4:			0000: 00032282 00000000 00000000 00000000 00000000
-t0			write VPC_VARYING_PS_REPL[0].MODE (2286)
+			write VPC_VARYING_PS_REPL[0].MODE (2286)
 				VPC_VARYING_PS_REPL[0].MODE: { C0 = 0 | C1 = 0 | C2 = 0 | C3 = 0 | C4 = 0 | C5 = 0 | C6 = 0 | C7 = 0 | C8 = 0 | C9 = 0 | CA = 0 | CB = 0 | CC = 0 | CD = 0 | CE = 0 | CF = 0 }
 				VPC_VARYING_PS_REPL[0x1].MODE: { C0 = 0 | C1 = 0 | C2 = 0 | C3 = 0 | C4 = 0 | C5 = 0 | C6 = 0 | C7 = 0 | C8 = 0 | C9 = 0 | CA = 0 | CB = 0 | CC = 0 | CD = 0 | CE = 0 | CF = 0 }
 				VPC_VARYING_PS_REPL[0x2].MODE: { C0 = 0 | C1 = 0 | C2 = 0 | C3 = 0 | C4 = 0 | C5 = 0 | C6 = 0 | C7 = 0 | C8 = 0 | C9 = 0 | CA = 0 | CB = 0 | CC = 0 | CD = 0 | CE = 0 | CF = 0 }
 				VPC_VARYING_PS_REPL[0x3].MODE: { C0 = 0 | C1 = 0 | C2 = 0 | C3 = 0 | C4 = 0 | C5 = 0 | C6 = 0 | C7 = 0 | C8 = 0 | C9 = 0 | CA = 0 | CB = 0 | CC = 0 | CD = 0 | CE = 0 | CF = 0 }
 118426d8:			0000: 00032286 00000000 00000000 00000000 00000000
-t0			write VFD_VS_THREADING_THRESHOLD (227e)
+			write VFD_VS_THREADING_THRESHOLD (227e)
 				VFD_VS_THREADING_THRESHOLD: { REGID_THRESHOLD = 15 | REGID_VTXCNT = r63.x }
 118426ec:			0000: 0000227e 0000fc0f
-t3			opcode: CP_LOAD_STATE (30) (3 dwords)
+			opcode: CP_LOAD_STATE (30) (3 dwords)
 				{ DST_OFF = 0 | STATE_SRC = SS_INDIRECT | STATE_BLOCK = SB_VERT_SHADER | NUM_UNIT = 36 }
 				{ STATE_TYPE = ST_SHADER | EXT_SRC_ADDR = 0x127f3000 }
 118426f4:			0000: c0013000 09240000 127f3000
-t0			write VFD_PERFCOUNTER0_SELECT (0e44)
+			write VFD_PERFCOUNTER0_SELECT (0e44)
 				VFD_PERFCOUNTER0_SELECT: VFD_PERF_UCHE_BYTE_FETCHED
 11842700:			0000: 00000e44 00000000
-t3			opcode: CP_LOAD_STATE (30) (3 dwords)
+			opcode: CP_LOAD_STATE (30) (3 dwords)
 				{ DST_OFF = 0 | STATE_SRC = SS_INDIRECT | STATE_BLOCK = SB_FRAG_SHADER | NUM_UNIT = 4 }
 				{ STATE_TYPE = ST_SHADER | EXT_SRC_ADDR = 0x127f2000 }
 11842708:			0000: c0013000 01340000 127f2000
-t0			write VFD_PERFCOUNTER0_SELECT (0e44)
+			write VFD_PERFCOUNTER0_SELECT (0e44)
 				VFD_PERFCOUNTER0_SELECT: VFD_PERF_UCHE_BYTE_FETCHED
 11842714:			0000: 00000e44 00000000
-t0			write VFD_CONTROL_0 (2240)
+			write VFD_CONTROL_0 (2240)
 				VFD_CONTROL_0: { TOTALATTRTOVS = 8 | PACKETSIZE = 2 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 }
 				VFD_CONTROL_1: { MAXSTORAGE = 1 | MAXTHRESHOLD = 0 | MINTHRESHOLD = 0 | REGID4VTX = r63.x | REGID4INST = r63.x }
 1184271c:			0000: 00012240 10880008 fcfc0001
-t0			write UCHE_CACHE_INVALIDATE0_REG (0ea0)
+			write UCHE_CACHE_INVALIDATE0_REG (0ea0)
 				UCHE_CACHE_INVALIDATE0_REG: { ADDR = 0 }
 				UCHE_CACHE_INVALIDATE1_REG: { ADDR = 0 | OPCODE = INVALIDATE | ENTIRE_CACHE }
 11842728:			0000: 00010ea0 00000000 90000000
-t3			opcode: CP_LOAD_STATE (30) (43 dwords)
+			opcode: CP_LOAD_STATE (30) (43 dwords)
 				{ DST_OFF = 0 | STATE_SRC = SS_DIRECT | STATE_BLOCK = SB_VERT_SHADER | NUM_UNIT = 20 }
 				{ STATE_TYPE = ST_CONSTANTS | EXT_SRC_ADDR = 0 }
 11842740:				1.499184 0.349716 0.459207 0.458311 -0.049471 1.616941 -0.358029 -0.357330
@@ -766,73 +766,73 @@ t3			opcode: CP_LOAD_STATE (30) (43 dwords)
 11842794:			0060: 3f6efc91 3eb6f3f3 4110bebf 3f000000 be97a747 3f50550b 41823527 00000000
 118427b4:			0080: 00000000 00000000 3f800000 40a00000 40a00000 41200000 3f800000 3f4ccccd
 118427d4:			00a0: 3dcccccd 00000000 3f800000
-t0			write UCHE_CACHE_INVALIDATE0_REG (0ea0)
+			write UCHE_CACHE_INVALIDATE0_REG (0ea0)
 				UCHE_CACHE_INVALIDATE0_REG: { ADDR = 0 }
 				UCHE_CACHE_INVALIDATE1_REG: { ADDR = 0 | OPCODE = INVALIDATE | ENTIRE_CACHE }
 118427e0:			0000: 00010ea0 00000000 90000000
-t3			opcode: CP_LOAD_STATE (30) (7 dwords)
+			opcode: CP_LOAD_STATE (30) (7 dwords)
 				{ DST_OFF = 20 | STATE_SRC = SS_DIRECT | STATE_BLOCK = SB_VERT_SHADER | NUM_UNIT = 2 }
 				{ STATE_TYPE = ST_CONSTANTS | EXT_SRC_ADDR = 0 }
 118427f8:				0.000000 0.000000 0.000000 0.000000
 118427f8:				0000: 00000000 00000000 00000000 00000000
 118427ec:			0000: c0053000 00a00014 00000001 00000000 00000000 00000000 00000000
-t0			write RB_MRT[0].CONTROL (20c4)
+			write RB_MRT[0].CONTROL (20c4)
 				RB_MRT[0].CONTROL: { ROP_CODE = ROP_COPY | DITHER_MODE = DITHER_ALWAYS | COMPONENT_ENABLE = 0xf }
 11842808:			0000: 000020c4 0f001c00
-t0			write RB_MRT[0].BLEND_CONTROL (20c7)
+			write RB_MRT[0].BLEND_CONTROL (20c7)
 				RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO | CLAMP_ENABLE }
 11842810:			0000: 000020c7 20000000
-t0			write RB_MRT[0x1].CONTROL (20c8)
+			write RB_MRT[0x1].CONTROL (20c8)
 				RB_MRT[0x1].CONTROL: { ROP_CODE = ROP_COPY | DITHER_MODE = DITHER_ALWAYS | COMPONENT_ENABLE = 0 }
 11842818:			0000: 000020c8 00001c00
-t0			write RB_MRT[0x1].BLEND_CONTROL (20cb)
+			write RB_MRT[0x1].BLEND_CONTROL (20cb)
 				RB_MRT[0x1].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO | CLAMP_ENABLE }
 11842820:			0000: 000020cb 20000000
-t0			write RB_MRT[0x2].CONTROL (20cc)
+			write RB_MRT[0x2].CONTROL (20cc)
 				RB_MRT[0x2].CONTROL: { ROP_CODE = ROP_COPY | DITHER_MODE = DITHER_ALWAYS | COMPONENT_ENABLE = 0 }
 11842828:			0000: 000020cc 00001c00
-t0			write RB_MRT[0x2].BLEND_CONTROL (20cf)
+			write RB_MRT[0x2].BLEND_CONTROL (20cf)
 				RB_MRT[0x2].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO | CLAMP_ENABLE }
 11842830:			0000: 000020cf 20000000
-t0			write RB_MRT[0x3].CONTROL (20d0)
+			write RB_MRT[0x3].CONTROL (20d0)
 				RB_MRT[0x3].CONTROL: { ROP_CODE = ROP_COPY | DITHER_MODE = DITHER_ALWAYS | COMPONENT_ENABLE = 0 }
 11842838:			0000: 000020d0 00001c00
-t0			write RB_MRT[0x3].BLEND_CONTROL (20d3)
+			write RB_MRT[0x3].BLEND_CONTROL (20d3)
 				RB_MRT[0x3].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO | CLAMP_ENABLE }
 11842840:			0000: 000020d3 20000000
-t0			write VFD_FETCH[0].INSTR_0 (2246)
+			write VFD_FETCH[0].INSTR_0 (2246)
 				VFD_FETCH[0].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 24 | SWITCHNEXT | INDEXCODE = 0 | STEPRATE = 1 }
 				VFD_FETCH[0].INSTR_1: 0x127ea000
 11842848:			0000: 00012246 01020c0b 127ea000
-t0			write VFD_DECODE[0].INSTR (2266)
+			write VFD_DECODE[0].INSTR (2266)
 				VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID | SWITCHNEXT }
 11842854:			0000: 00002266 6c00009f
-t0			write VFD_FETCH[0x1].INSTR_0 (2248)
+			write VFD_FETCH[0x1].INSTR_0 (2248)
 				VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 24 | INDEXCODE = 1 | STEPRATE = 1 }
 				VFD_FETCH[0x1].INSTR_1: 0x127ea00c
 1184285c:			0000: 00012248 01040c0b 127ea00c
-t0			write VFD_DECODE[0x1].INSTR (2267)
+			write VFD_DECODE[0x1].INSTR (2267)
 				VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT_32_32_32_FLOAT | REGID = r1.x | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID }
 11842868:			0000: 00002267 2c00409f
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11842870:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11842878:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 0
 				VFD_INDEX_MAX: 6
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 0
 11842880:			0000: 00032242 00000000 00000006 00000000 00000000
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11842894:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 11975
 				:0,11974,12814,11975
 1184289c:			0000: 0000057f 00002ec7
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 7 }
@@ -925,35 +925,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			SP_FS_MRT[0x3].REG: { REGID = r0.x }
 !+	00000004			SP_FS_LENGTH_REG: { SHADERLENGTH = 4 }
 118428a4:			0000: c0022200 00000000 00004086 00000007
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 11976
 				:0,11974,12814,11976
 118428b4:			0000: 0000057f 00002ec8
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 11977
 				:0,11977,12814,11976
 118428bc:			0000: 0000057d 00002ec9
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 118428c4:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 118428cc:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 7
 				VFD_INDEX_MAX: 10
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 7
 118428d4:			0000: 00032242 00000007 0000000a 00000000 00000007
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 118428e8:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 11978
 				:0,11977,12814,11978
 118428f0:			0000: 0000057f 00002eca
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -973,35 +973,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000007			VFD_INDEX_OFFSET: 7
 118428f8:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 11979
 				:0,11977,12814,11979
 11842908:			0000: 0000057f 00002ecb
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 11980
 				:0,11980,12814,11979
 11842910:			0000: 0000057d 00002ecc
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11842918:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11842920:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 11
 				VFD_INDEX_MAX: 17
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 11
 11842928:			0000: 00032242 0000000b 00000011 00000000 0000000b
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 1184293c:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 11981
 				:0,11980,12814,11981
 11842944:			0000: 0000057f 00002ecd
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 7 }
@@ -1021,35 +1021,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	0000000b			VFD_INDEX_OFFSET: 11
 1184294c:			0000: c0022200 00000000 00004086 00000007
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 11982
 				:0,11980,12814,11982
 1184295c:			0000: 0000057f 00002ece
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 11983
 				:0,11983,12814,11982
 11842964:			0000: 0000057d 00002ecf
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 1184296c:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11842974:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 18
 				VFD_INDEX_MAX: 21
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 18
 1184297c:			0000: 00032242 00000012 00000015 00000000 00000012
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11842990:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 11984
 				:0,11983,12814,11984
 11842998:			0000: 0000057f 00002ed0
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -1069,35 +1069,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000012			VFD_INDEX_OFFSET: 18
 118429a0:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 11985
 				:0,11983,12814,11985
 118429b0:			0000: 0000057f 00002ed1
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 11986
 				:0,11986,12814,11985
 118429b8:			0000: 0000057d 00002ed2
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 118429c0:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 118429c8:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 22
 				VFD_INDEX_MAX: 25
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 22
 118429d0:			0000: 00032242 00000016 00000019 00000000 00000016
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 118429e4:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 11987
 				:0,11986,12814,11987
 118429ec:			0000: 0000057f 00002ed3
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -1117,35 +1117,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000016			VFD_INDEX_OFFSET: 22
 118429f4:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 11988
 				:0,11986,12814,11988
 11842a04:			0000: 0000057f 00002ed4
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 11989
 				:0,11989,12814,11988
 11842a0c:			0000: 0000057d 00002ed5
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11842a14:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11842a1c:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 26
 				VFD_INDEX_MAX: 29
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 26
 11842a24:			0000: 00032242 0000001a 0000001d 00000000 0000001a
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11842a38:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 11990
 				:0,11989,12814,11990
 11842a40:			0000: 0000057f 00002ed6
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -1165,35 +1165,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	0000001a			VFD_INDEX_OFFSET: 26
 11842a48:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 11991
 				:0,11989,12814,11991
 11842a58:			0000: 0000057f 00002ed7
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 11992
 				:0,11992,12814,11991
 11842a60:			0000: 0000057d 00002ed8
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11842a68:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11842a70:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 30
 				VFD_INDEX_MAX: 33
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 30
 11842a78:			0000: 00032242 0000001e 00000021 00000000 0000001e
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11842a8c:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 11993
 				:0,11992,12814,11993
 11842a94:			0000: 0000057f 00002ed9
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -1213,35 +1213,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	0000001e			VFD_INDEX_OFFSET: 30
 11842a9c:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 11994
 				:0,11992,12814,11994
 11842aac:			0000: 0000057f 00002eda
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 11995
 				:0,11995,12814,11994
 11842ab4:			0000: 0000057d 00002edb
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11842abc:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11842ac4:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 34
 				VFD_INDEX_MAX: 40
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 34
 11842acc:			0000: 00032242 00000022 00000028 00000000 00000022
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11842ae0:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 11996
 				:0,11995,12814,11996
 11842ae8:			0000: 0000057f 00002edc
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 7 }
@@ -1261,35 +1261,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000022			VFD_INDEX_OFFSET: 34
 11842af0:			0000: c0022200 00000000 00004086 00000007
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 11997
 				:0,11995,12814,11997
 11842b00:			0000: 0000057f 00002edd
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 11998
 				:0,11998,12814,11997
 11842b08:			0000: 0000057d 00002ede
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11842b10:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11842b18:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 41
 				VFD_INDEX_MAX: 44
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 41
 11842b20:			0000: 00032242 00000029 0000002c 00000000 00000029
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11842b34:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 11999
 				:0,11998,12814,11999
 11842b3c:			0000: 0000057f 00002edf
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -1309,35 +1309,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000029			VFD_INDEX_OFFSET: 41
 11842b44:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12000
 				:0,11998,12814,12000
 11842b54:			0000: 0000057f 00002ee0
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12001
 				:0,12001,12814,12000
 11842b5c:			0000: 0000057d 00002ee1
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11842b64:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11842b6c:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 45
 				VFD_INDEX_MAX: 51
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 45
 11842b74:			0000: 00032242 0000002d 00000033 00000000 0000002d
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11842b88:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12002
 				:0,12001,12814,12002
 11842b90:			0000: 0000057f 00002ee2
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 7 }
@@ -1357,35 +1357,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	0000002d			VFD_INDEX_OFFSET: 45
 11842b98:			0000: c0022200 00000000 00004086 00000007
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12003
 				:0,12001,12814,12003
 11842ba8:			0000: 0000057f 00002ee3
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12004
 				:0,12004,12814,12003
 11842bb0:			0000: 0000057d 00002ee4
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11842bb8:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11842bc0:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 52
 				VFD_INDEX_MAX: 55
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 52
 11842bc8:			0000: 00032242 00000034 00000037 00000000 00000034
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11842bdc:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12005
 				:0,12004,12814,12005
 11842be4:			0000: 0000057f 00002ee5
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -1405,35 +1405,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000034			VFD_INDEX_OFFSET: 52
 11842bec:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12006
 				:0,12004,12814,12006
 11842bfc:			0000: 0000057f 00002ee6
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12007
 				:0,12007,12814,12006
 11842c04:			0000: 0000057d 00002ee7
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11842c0c:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11842c14:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 56
 				VFD_INDEX_MAX: 59
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 56
 11842c1c:			0000: 00032242 00000038 0000003b 00000000 00000038
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11842c30:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12008
 				:0,12007,12814,12008
 11842c38:			0000: 0000057f 00002ee8
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -1453,35 +1453,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000038			VFD_INDEX_OFFSET: 56
 11842c40:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12009
 				:0,12007,12814,12009
 11842c50:			0000: 0000057f 00002ee9
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12010
 				:0,12010,12814,12009
 11842c58:			0000: 0000057d 00002eea
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11842c60:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11842c68:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 60
 				VFD_INDEX_MAX: 63
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 60
 11842c70:			0000: 00032242 0000003c 0000003f 00000000 0000003c
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11842c84:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12011
 				:0,12010,12814,12011
 11842c8c:			0000: 0000057f 00002eeb
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -1501,35 +1501,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	0000003c			VFD_INDEX_OFFSET: 60
 11842c94:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12012
 				:0,12010,12814,12012
 11842ca4:			0000: 0000057f 00002eec
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12013
 				:0,12013,12814,12012
 11842cac:			0000: 0000057d 00002eed
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11842cb4:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11842cbc:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 64
 				VFD_INDEX_MAX: 67
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 64
 11842cc4:			0000: 00032242 00000040 00000043 00000000 00000040
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11842cd8:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12014
 				:0,12013,12814,12014
 11842ce0:			0000: 0000057f 00002eee
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -1549,35 +1549,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000040			VFD_INDEX_OFFSET: 64
 11842ce8:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12015
 				:0,12013,12814,12015
 11842cf8:			0000: 0000057f 00002eef
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12016
 				:0,12016,12814,12015
 11842d00:			0000: 0000057d 00002ef0
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11842d08:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11842d10:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 68
 				VFD_INDEX_MAX: 74
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 68
 11842d18:			0000: 00032242 00000044 0000004a 00000000 00000044
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11842d2c:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12017
 				:0,12016,12814,12017
 11842d34:			0000: 0000057f 00002ef1
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 7 }
@@ -1597,35 +1597,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000044			VFD_INDEX_OFFSET: 68
 11842d3c:			0000: c0022200 00000000 00004086 00000007
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12018
 				:0,12016,12814,12018
 11842d4c:			0000: 0000057f 00002ef2
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12019
 				:0,12019,12814,12018
 11842d54:			0000: 0000057d 00002ef3
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11842d5c:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11842d64:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 75
 				VFD_INDEX_MAX: 78
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 75
 11842d6c:			0000: 00032242 0000004b 0000004e 00000000 0000004b
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11842d80:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12020
 				:0,12019,12814,12020
 11842d88:			0000: 0000057f 00002ef4
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -1645,35 +1645,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	0000004b			VFD_INDEX_OFFSET: 75
 11842d90:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12021
 				:0,12019,12814,12021
 11842da0:			0000: 0000057f 00002ef5
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12022
 				:0,12022,12814,12021
 11842da8:			0000: 0000057d 00002ef6
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11842db0:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11842db8:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 79
 				VFD_INDEX_MAX: 85
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 79
 11842dc0:			0000: 00032242 0000004f 00000055 00000000 0000004f
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11842dd4:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12023
 				:0,12022,12814,12023
 11842ddc:			0000: 0000057f 00002ef7
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 7 }
@@ -1693,35 +1693,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	0000004f			VFD_INDEX_OFFSET: 79
 11842de4:			0000: c0022200 00000000 00004086 00000007
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12024
 				:0,12022,12814,12024
 11842df4:			0000: 0000057f 00002ef8
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12025
 				:0,12025,12814,12024
 11842dfc:			0000: 0000057d 00002ef9
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11842e04:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11842e0c:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 86
 				VFD_INDEX_MAX: 89
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 86
 11842e14:			0000: 00032242 00000056 00000059 00000000 00000056
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11842e28:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12026
 				:0,12025,12814,12026
 11842e30:			0000: 0000057f 00002efa
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -1741,35 +1741,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000056			VFD_INDEX_OFFSET: 86
 11842e38:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12027
 				:0,12025,12814,12027
 11842e48:			0000: 0000057f 00002efb
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12028
 				:0,12028,12814,12027
 11842e50:			0000: 0000057d 00002efc
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11842e58:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11842e60:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 90
 				VFD_INDEX_MAX: 93
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 90
 11842e68:			0000: 00032242 0000005a 0000005d 00000000 0000005a
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11842e7c:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12029
 				:0,12028,12814,12029
 11842e84:			0000: 0000057f 00002efd
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -1789,35 +1789,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	0000005a			VFD_INDEX_OFFSET: 90
 11842e8c:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12030
 				:0,12028,12814,12030
 11842e9c:			0000: 0000057f 00002efe
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12031
 				:0,12031,12814,12030
 11842ea4:			0000: 0000057d 00002eff
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11842eac:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11842eb4:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 94
 				VFD_INDEX_MAX: 97
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 94
 11842ebc:			0000: 00032242 0000005e 00000061 00000000 0000005e
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11842ed0:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12032
 				:0,12031,12814,12032
 11842ed8:			0000: 0000057f 00002f00
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -1837,35 +1837,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	0000005e			VFD_INDEX_OFFSET: 94
 11842ee0:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12033
 				:0,12031,12814,12033
 11842ef0:			0000: 0000057f 00002f01
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12034
 				:0,12034,12814,12033
 11842ef8:			0000: 0000057d 00002f02
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11842f00:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11842f08:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 98
 				VFD_INDEX_MAX: 101
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 98
 11842f10:			0000: 00032242 00000062 00000065 00000000 00000062
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11842f24:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12035
 				:0,12034,12814,12035
 11842f2c:			0000: 0000057f 00002f03
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -1885,35 +1885,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000062			VFD_INDEX_OFFSET: 98
 11842f34:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12036
 				:0,12034,12814,12036
 11842f44:			0000: 0000057f 00002f04
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12037
 				:0,12037,12814,12036
 11842f4c:			0000: 0000057d 00002f05
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11842f54:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11842f5c:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 102
 				VFD_INDEX_MAX: 108
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 102
 11842f64:			0000: 00032242 00000066 0000006c 00000000 00000066
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11842f78:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12038
 				:0,12037,12814,12038
 11842f80:			0000: 0000057f 00002f06
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 7 }
@@ -1933,35 +1933,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000066			VFD_INDEX_OFFSET: 102
 11842f88:			0000: c0022200 00000000 00004086 00000007
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12039
 				:0,12037,12814,12039
 11842f98:			0000: 0000057f 00002f07
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12040
 				:0,12040,12814,12039
 11842fa0:			0000: 0000057d 00002f08
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11842fa8:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11842fb0:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 109
 				VFD_INDEX_MAX: 112
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 109
 11842fb8:			0000: 00032242 0000006d 00000070 00000000 0000006d
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11842fcc:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12041
 				:0,12040,12814,12041
 11842fd4:			0000: 0000057f 00002f09
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -1981,35 +1981,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	0000006d			VFD_INDEX_OFFSET: 109
 11842fdc:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12042
 				:0,12040,12814,12042
 11842fec:			0000: 0000057f 00002f0a
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12043
 				:0,12043,12814,12042
 11842ff4:			0000: 0000057d 00002f0b
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11842ffc:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11843004:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 113
 				VFD_INDEX_MAX: 119
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 113
 1184300c:			0000: 00032242 00000071 00000077 00000000 00000071
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11843020:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12044
 				:0,12043,12814,12044
 11843028:			0000: 0000057f 00002f0c
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 7 }
@@ -2029,35 +2029,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000071			VFD_INDEX_OFFSET: 113
 11843030:			0000: c0022200 00000000 00004086 00000007
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12045
 				:0,12043,12814,12045
 11843040:			0000: 0000057f 00002f0d
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12046
 				:0,12046,12814,12045
 11843048:			0000: 0000057d 00002f0e
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11843050:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11843058:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 120
 				VFD_INDEX_MAX: 123
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 120
 11843060:			0000: 00032242 00000078 0000007b 00000000 00000078
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11843074:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12047
 				:0,12046,12814,12047
 1184307c:			0000: 0000057f 00002f0f
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -2077,35 +2077,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000078			VFD_INDEX_OFFSET: 120
 11843084:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12048
 				:0,12046,12814,12048
 11843094:			0000: 0000057f 00002f10
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12049
 				:0,12049,12814,12048
 1184309c:			0000: 0000057d 00002f11
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 118430a4:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 118430ac:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 124
 				VFD_INDEX_MAX: 127
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 124
 118430b4:			0000: 00032242 0000007c 0000007f 00000000 0000007c
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 118430c8:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12050
 				:0,12049,12814,12050
 118430d0:			0000: 0000057f 00002f12
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -2125,35 +2125,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	0000007c			VFD_INDEX_OFFSET: 124
 118430d8:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12051
 				:0,12049,12814,12051
 118430e8:			0000: 0000057f 00002f13
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12052
 				:0,12052,12814,12051
 118430f0:			0000: 0000057d 00002f14
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 118430f8:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11843100:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 128
 				VFD_INDEX_MAX: 131
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 128
 11843108:			0000: 00032242 00000080 00000083 00000000 00000080
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 1184311c:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12053
 				:0,12052,12814,12053
 11843124:			0000: 0000057f 00002f15
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -2173,35 +2173,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000080			VFD_INDEX_OFFSET: 128
 1184312c:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12054
 				:0,12052,12814,12054
 1184313c:			0000: 0000057f 00002f16
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12055
 				:0,12055,12814,12054
 11843144:			0000: 0000057d 00002f17
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 1184314c:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11843154:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 132
 				VFD_INDEX_MAX: 135
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 132
 1184315c:			0000: 00032242 00000084 00000087 00000000 00000084
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11843170:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12056
 				:0,12055,12814,12056
 11843178:			0000: 0000057f 00002f18
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -2221,35 +2221,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000084			VFD_INDEX_OFFSET: 132
 11843180:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12057
 				:0,12055,12814,12057
 11843190:			0000: 0000057f 00002f19
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12058
 				:0,12058,12814,12057
 11843198:			0000: 0000057d 00002f1a
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 118431a0:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 118431a8:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 136
 				VFD_INDEX_MAX: 142
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 136
 118431b0:			0000: 00032242 00000088 0000008e 00000000 00000088
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 118431c4:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12059
 				:0,12058,12814,12059
 118431cc:			0000: 0000057f 00002f1b
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 7 }
@@ -2269,35 +2269,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000088			VFD_INDEX_OFFSET: 136
 118431d4:			0000: c0022200 00000000 00004086 00000007
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12060
 				:0,12058,12814,12060
 118431e4:			0000: 0000057f 00002f1c
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12061
 				:0,12061,12814,12060
 118431ec:			0000: 0000057d 00002f1d
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 118431f4:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 118431fc:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 143
 				VFD_INDEX_MAX: 146
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 143
 11843204:			0000: 00032242 0000008f 00000092 00000000 0000008f
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11843218:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12062
 				:0,12061,12814,12062
 11843220:			0000: 0000057f 00002f1e
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -2317,35 +2317,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	0000008f			VFD_INDEX_OFFSET: 143
 11843228:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12063
 				:0,12061,12814,12063
 11843238:			0000: 0000057f 00002f1f
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12064
 				:0,12064,12814,12063
 11843240:			0000: 0000057d 00002f20
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11843248:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11843250:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 147
 				VFD_INDEX_MAX: 153
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 147
 11843258:			0000: 00032242 00000093 00000099 00000000 00000093
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 1184326c:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12065
 				:0,12064,12814,12065
 11843274:			0000: 0000057f 00002f21
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 7 }
@@ -2365,35 +2365,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000093			VFD_INDEX_OFFSET: 147
 1184327c:			0000: c0022200 00000000 00004086 00000007
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12066
 				:0,12064,12814,12066
 1184328c:			0000: 0000057f 00002f22
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12067
 				:0,12067,12814,12066
 11843294:			0000: 0000057d 00002f23
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 1184329c:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 118432a4:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 154
 				VFD_INDEX_MAX: 157
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 154
 118432ac:			0000: 00032242 0000009a 0000009d 00000000 0000009a
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 118432c0:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12068
 				:0,12067,12814,12068
 118432c8:			0000: 0000057f 00002f24
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -2413,35 +2413,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	0000009a			VFD_INDEX_OFFSET: 154
 118432d0:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12069
 				:0,12067,12814,12069
 118432e0:			0000: 0000057f 00002f25
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12070
 				:0,12070,12814,12069
 118432e8:			0000: 0000057d 00002f26
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 118432f0:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 118432f8:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 158
 				VFD_INDEX_MAX: 161
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 158
 11843300:			0000: 00032242 0000009e 000000a1 00000000 0000009e
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11843314:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12071
 				:0,12070,12814,12071
 1184331c:			0000: 0000057f 00002f27
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -2461,35 +2461,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	0000009e			VFD_INDEX_OFFSET: 158
 11843324:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12072
 				:0,12070,12814,12072
 11843334:			0000: 0000057f 00002f28
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12073
 				:0,12073,12814,12072
 1184333c:			0000: 0000057d 00002f29
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11843344:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 1184334c:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 162
 				VFD_INDEX_MAX: 165
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 162
 11843354:			0000: 00032242 000000a2 000000a5 00000000 000000a2
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11843368:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12074
 				:0,12073,12814,12074
 11843370:			0000: 0000057f 00002f2a
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -2509,35 +2509,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	000000a2			VFD_INDEX_OFFSET: 162
 11843378:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12075
 				:0,12073,12814,12075
 11843388:			0000: 0000057f 00002f2b
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12076
 				:0,12076,12814,12075
 11843390:			0000: 0000057d 00002f2c
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11843398:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 118433a0:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 166
 				VFD_INDEX_MAX: 169
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 166
 118433a8:			0000: 00032242 000000a6 000000a9 00000000 000000a6
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 118433bc:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12077
 				:0,12076,12814,12077
 118433c4:			0000: 0000057f 00002f2d
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -2557,35 +2557,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	000000a6			VFD_INDEX_OFFSET: 166
 118433cc:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12078
 				:0,12076,12814,12078
 118433dc:			0000: 0000057f 00002f2e
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12079
 				:0,12079,12814,12078
 118433e4:			0000: 0000057d 00002f2f
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 118433ec:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 118433f4:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 170
 				VFD_INDEX_MAX: 176
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 170
 118433fc:			0000: 00032242 000000aa 000000b0 00000000 000000aa
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11843410:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12080
 				:0,12079,12814,12080
 11843418:			0000: 0000057f 00002f30
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 7 }
@@ -2605,35 +2605,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	000000aa			VFD_INDEX_OFFSET: 170
 11843420:			0000: c0022200 00000000 00004086 00000007
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12081
 				:0,12079,12814,12081
 11843430:			0000: 0000057f 00002f31
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12082
 				:0,12082,12814,12081
 11843438:			0000: 0000057d 00002f32
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11843440:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11843448:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 177
 				VFD_INDEX_MAX: 180
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 177
 11843450:			0000: 00032242 000000b1 000000b4 00000000 000000b1
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11843464:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12083
 				:0,12082,12814,12083
 1184346c:			0000: 0000057f 00002f33
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -2653,35 +2653,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	000000b1			VFD_INDEX_OFFSET: 177
 11843474:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12084
 				:0,12082,12814,12084
 11843484:			0000: 0000057f 00002f34
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12085
 				:0,12085,12814,12084
 1184348c:			0000: 0000057d 00002f35
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11843494:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 1184349c:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 181
 				VFD_INDEX_MAX: 187
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 181
 118434a4:			0000: 00032242 000000b5 000000bb 00000000 000000b5
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 118434b8:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12086
 				:0,12085,12814,12086
 118434c0:			0000: 0000057f 00002f36
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 7 }
@@ -2701,35 +2701,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	000000b5			VFD_INDEX_OFFSET: 181
 118434c8:			0000: c0022200 00000000 00004086 00000007
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12087
 				:0,12085,12814,12087
 118434d8:			0000: 0000057f 00002f37
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12088
 				:0,12088,12814,12087
 118434e0:			0000: 0000057d 00002f38
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 118434e8:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 118434f0:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 188
 				VFD_INDEX_MAX: 191
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 188
 118434f8:			0000: 00032242 000000bc 000000bf 00000000 000000bc
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 1184350c:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12089
 				:0,12088,12814,12089
 11843514:			0000: 0000057f 00002f39
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -2749,35 +2749,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	000000bc			VFD_INDEX_OFFSET: 188
 1184351c:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12090
 				:0,12088,12814,12090
 1184352c:			0000: 0000057f 00002f3a
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12091
 				:0,12091,12814,12090
 11843534:			0000: 0000057d 00002f3b
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 1184353c:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11843544:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 192
 				VFD_INDEX_MAX: 195
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 192
 1184354c:			0000: 00032242 000000c0 000000c3 00000000 000000c0
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11843560:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12092
 				:0,12091,12814,12092
 11843568:			0000: 0000057f 00002f3c
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -2797,35 +2797,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	000000c0			VFD_INDEX_OFFSET: 192
 11843570:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12093
 				:0,12091,12814,12093
 11843580:			0000: 0000057f 00002f3d
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12094
 				:0,12094,12814,12093
 11843588:			0000: 0000057d 00002f3e
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11843590:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11843598:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 196
 				VFD_INDEX_MAX: 199
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 196
 118435a0:			0000: 00032242 000000c4 000000c7 00000000 000000c4
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 118435b4:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12095
 				:0,12094,12814,12095
 118435bc:			0000: 0000057f 00002f3f
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -2845,35 +2845,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	000000c4			VFD_INDEX_OFFSET: 196
 118435c4:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12096
 				:0,12094,12814,12096
 118435d4:			0000: 0000057f 00002f40
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12097
 				:0,12097,12814,12096
 118435dc:			0000: 0000057d 00002f41
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 118435e4:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 118435ec:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 200
 				VFD_INDEX_MAX: 203
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 200
 118435f4:			0000: 00032242 000000c8 000000cb 00000000 000000c8
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11843608:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12098
 				:0,12097,12814,12098
 11843610:			0000: 0000057f 00002f42
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -2893,35 +2893,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	000000c8			VFD_INDEX_OFFSET: 200
 11843618:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12099
 				:0,12097,12814,12099
 11843628:			0000: 0000057f 00002f43
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12100
 				:0,12100,12814,12099
 11843630:			0000: 0000057d 00002f44
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11843638:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11843640:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 204
 				VFD_INDEX_MAX: 210
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 204
 11843648:			0000: 00032242 000000cc 000000d2 00000000 000000cc
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 1184365c:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12101
 				:0,12100,12814,12101
 11843664:			0000: 0000057f 00002f45
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 7 }
@@ -2941,35 +2941,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	000000cc			VFD_INDEX_OFFSET: 204
 1184366c:			0000: c0022200 00000000 00004086 00000007
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12102
 				:0,12100,12814,12102
 1184367c:			0000: 0000057f 00002f46
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12103
 				:0,12103,12814,12102
 11843684:			0000: 0000057d 00002f47
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 1184368c:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11843694:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 211
 				VFD_INDEX_MAX: 214
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 211
 1184369c:			0000: 00032242 000000d3 000000d6 00000000 000000d3
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 118436b0:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12104
 				:0,12103,12814,12104
 118436b8:			0000: 0000057f 00002f48
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -2989,35 +2989,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	000000d3			VFD_INDEX_OFFSET: 211
 118436c0:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12105
 				:0,12103,12814,12105
 118436d0:			0000: 0000057f 00002f49
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12106
 				:0,12106,12814,12105
 118436d8:			0000: 0000057d 00002f4a
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 118436e0:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 118436e8:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 215
 				VFD_INDEX_MAX: 221
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 215
 118436f0:			0000: 00032242 000000d7 000000dd 00000000 000000d7
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11843704:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12107
 				:0,12106,12814,12107
 1184370c:			0000: 0000057f 00002f4b
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 7 }
@@ -3037,35 +3037,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	000000d7			VFD_INDEX_OFFSET: 215
 11843714:			0000: c0022200 00000000 00004086 00000007
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12108
 				:0,12106,12814,12108
 11843724:			0000: 0000057f 00002f4c
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12109
 				:0,12109,12814,12108
 1184372c:			0000: 0000057d 00002f4d
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11843734:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 1184373c:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 222
 				VFD_INDEX_MAX: 225
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 222
 11843744:			0000: 00032242 000000de 000000e1 00000000 000000de
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11843758:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12110
 				:0,12109,12814,12110
 11843760:			0000: 0000057f 00002f4e
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -3085,35 +3085,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	000000de			VFD_INDEX_OFFSET: 222
 11843768:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12111
 				:0,12109,12814,12111
 11843778:			0000: 0000057f 00002f4f
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12112
 				:0,12112,12814,12111
 11843780:			0000: 0000057d 00002f50
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11843788:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11843790:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 226
 				VFD_INDEX_MAX: 229
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 226
 11843798:			0000: 00032242 000000e2 000000e5 00000000 000000e2
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 118437ac:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12113
 				:0,12112,12814,12113
 118437b4:			0000: 0000057f 00002f51
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -3133,35 +3133,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	000000e2			VFD_INDEX_OFFSET: 226
 118437bc:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12114
 				:0,12112,12814,12114
 118437cc:			0000: 0000057f 00002f52
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12115
 				:0,12115,12814,12114
 118437d4:			0000: 0000057d 00002f53
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 118437dc:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 118437e4:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 230
 				VFD_INDEX_MAX: 233
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 230
 118437ec:			0000: 00032242 000000e6 000000e9 00000000 000000e6
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11843800:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12116
 				:0,12115,12814,12116
 11843808:			0000: 0000057f 00002f54
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -3181,35 +3181,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	000000e6			VFD_INDEX_OFFSET: 230
 11843810:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12117
 				:0,12115,12814,12117
 11843820:			0000: 0000057f 00002f55
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12118
 				:0,12118,12814,12117
 11843828:			0000: 0000057d 00002f56
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11843830:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11843838:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 234
 				VFD_INDEX_MAX: 237
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 234
 11843840:			0000: 00032242 000000ea 000000ed 00000000 000000ea
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11843854:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12119
 				:0,12118,12814,12119
 1184385c:			0000: 0000057f 00002f57
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -3229,35 +3229,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	000000ea			VFD_INDEX_OFFSET: 234
 11843864:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12120
 				:0,12118,12814,12120
 11843874:			0000: 0000057f 00002f58
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12121
 				:0,12121,12814,12120
 1184387c:			0000: 0000057d 00002f59
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11843884:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 1184388c:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 238
 				VFD_INDEX_MAX: 244
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 238
 11843894:			0000: 00032242 000000ee 000000f4 00000000 000000ee
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 118438a8:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12122
 				:0,12121,12814,12122
 118438b0:			0000: 0000057f 00002f5a
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 7 }
@@ -3277,35 +3277,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	000000ee			VFD_INDEX_OFFSET: 238
 118438b8:			0000: c0022200 00000000 00004086 00000007
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12123
 				:0,12121,12814,12123
 118438c8:			0000: 0000057f 00002f5b
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12124
 				:0,12124,12814,12123
 118438d0:			0000: 0000057d 00002f5c
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 118438d8:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 118438e0:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 245
 				VFD_INDEX_MAX: 248
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 245
 118438e8:			0000: 00032242 000000f5 000000f8 00000000 000000f5
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 118438fc:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12125
 				:0,12124,12814,12125
 11843904:			0000: 0000057f 00002f5d
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -3325,35 +3325,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	000000f5			VFD_INDEX_OFFSET: 245
 1184390c:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12126
 				:0,12124,12814,12126
 1184391c:			0000: 0000057f 00002f5e
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12127
 				:0,12127,12814,12126
 11843924:			0000: 0000057d 00002f5f
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 1184392c:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11843934:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 249
 				VFD_INDEX_MAX: 255
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 249
 1184393c:			0000: 00032242 000000f9 000000ff 00000000 000000f9
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11843950:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12128
 				:0,12127,12814,12128
 11843958:			0000: 0000057f 00002f60
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 7 }
@@ -3373,35 +3373,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	000000f9			VFD_INDEX_OFFSET: 249
 11843960:			0000: c0022200 00000000 00004086 00000007
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12129
 				:0,12127,12814,12129
 11843970:			0000: 0000057f 00002f61
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12130
 				:0,12130,12814,12129
 11843978:			0000: 0000057d 00002f62
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11843980:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11843988:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 256
 				VFD_INDEX_MAX: 259
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 256
 11843990:			0000: 00032242 00000100 00000103 00000000 00000100
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 118439a4:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12131
 				:0,12130,12814,12131
 118439ac:			0000: 0000057f 00002f63
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -3421,35 +3421,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000100			VFD_INDEX_OFFSET: 256
 118439b4:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12132
 				:0,12130,12814,12132
 118439c4:			0000: 0000057f 00002f64
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12133
 				:0,12133,12814,12132
 118439cc:			0000: 0000057d 00002f65
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 118439d4:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 118439dc:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 260
 				VFD_INDEX_MAX: 263
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 260
 118439e4:			0000: 00032242 00000104 00000107 00000000 00000104
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 118439f8:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12134
 				:0,12133,12814,12134
 11843a00:			0000: 0000057f 00002f66
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -3469,35 +3469,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000104			VFD_INDEX_OFFSET: 260
 11843a08:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12135
 				:0,12133,12814,12135
 11843a18:			0000: 0000057f 00002f67
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12136
 				:0,12136,12814,12135
 11843a20:			0000: 0000057d 00002f68
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11843a28:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11843a30:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 264
 				VFD_INDEX_MAX: 267
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 264
 11843a38:			0000: 00032242 00000108 0000010b 00000000 00000108
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11843a4c:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12137
 				:0,12136,12814,12137
 11843a54:			0000: 0000057f 00002f69
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -3517,35 +3517,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000108			VFD_INDEX_OFFSET: 264
 11843a5c:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12138
 				:0,12136,12814,12138
 11843a6c:			0000: 0000057f 00002f6a
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12139
 				:0,12139,12814,12138
 11843a74:			0000: 0000057d 00002f6b
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11843a7c:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11843a84:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 268
 				VFD_INDEX_MAX: 271
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 268
 11843a8c:			0000: 00032242 0000010c 0000010f 00000000 0000010c
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11843aa0:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12140
 				:0,12139,12814,12140
 11843aa8:			0000: 0000057f 00002f6c
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -3565,35 +3565,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	0000010c			VFD_INDEX_OFFSET: 268
 11843ab0:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12141
 				:0,12139,12814,12141
 11843ac0:			0000: 0000057f 00002f6d
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12142
 				:0,12142,12814,12141
 11843ac8:			0000: 0000057d 00002f6e
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11843ad0:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11843ad8:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 272
 				VFD_INDEX_MAX: 278
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 272
 11843ae0:			0000: 00032242 00000110 00000116 00000000 00000110
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11843af4:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12143
 				:0,12142,12814,12143
 11843afc:			0000: 0000057f 00002f6f
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 7 }
@@ -3613,35 +3613,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000110			VFD_INDEX_OFFSET: 272
 11843b04:			0000: c0022200 00000000 00004086 00000007
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12144
 				:0,12142,12814,12144
 11843b14:			0000: 0000057f 00002f70
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12145
 				:0,12145,12814,12144
 11843b1c:			0000: 0000057d 00002f71
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11843b24:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11843b2c:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 279
 				VFD_INDEX_MAX: 282
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 279
 11843b34:			0000: 00032242 00000117 0000011a 00000000 00000117
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11843b48:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12146
 				:0,12145,12814,12146
 11843b50:			0000: 0000057f 00002f72
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -3661,35 +3661,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000117			VFD_INDEX_OFFSET: 279
 11843b58:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12147
 				:0,12145,12814,12147
 11843b68:			0000: 0000057f 00002f73
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12148
 				:0,12148,12814,12147
 11843b70:			0000: 0000057d 00002f74
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11843b78:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11843b80:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 283
 				VFD_INDEX_MAX: 289
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 283
 11843b88:			0000: 00032242 0000011b 00000121 00000000 0000011b
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11843b9c:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12149
 				:0,12148,12814,12149
 11843ba4:			0000: 0000057f 00002f75
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 7 }
@@ -3709,35 +3709,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	0000011b			VFD_INDEX_OFFSET: 283
 11843bac:			0000: c0022200 00000000 00004086 00000007
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12150
 				:0,12148,12814,12150
 11843bbc:			0000: 0000057f 00002f76
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12151
 				:0,12151,12814,12150
 11843bc4:			0000: 0000057d 00002f77
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11843bcc:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11843bd4:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 290
 				VFD_INDEX_MAX: 293
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 290
 11843bdc:			0000: 00032242 00000122 00000125 00000000 00000122
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11843bf0:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12152
 				:0,12151,12814,12152
 11843bf8:			0000: 0000057f 00002f78
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -3757,35 +3757,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000122			VFD_INDEX_OFFSET: 290
 11843c00:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12153
 				:0,12151,12814,12153
 11843c10:			0000: 0000057f 00002f79
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12154
 				:0,12154,12814,12153
 11843c18:			0000: 0000057d 00002f7a
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11843c20:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11843c28:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 294
 				VFD_INDEX_MAX: 297
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 294
 11843c30:			0000: 00032242 00000126 00000129 00000000 00000126
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11843c44:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12155
 				:0,12154,12814,12155
 11843c4c:			0000: 0000057f 00002f7b
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -3805,35 +3805,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000126			VFD_INDEX_OFFSET: 294
 11843c54:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12156
 				:0,12154,12814,12156
 11843c64:			0000: 0000057f 00002f7c
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12157
 				:0,12157,12814,12156
 11843c6c:			0000: 0000057d 00002f7d
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11843c74:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11843c7c:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 298
 				VFD_INDEX_MAX: 301
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 298
 11843c84:			0000: 00032242 0000012a 0000012d 00000000 0000012a
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11843c98:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12158
 				:0,12157,12814,12158
 11843ca0:			0000: 0000057f 00002f7e
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -3853,35 +3853,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	0000012a			VFD_INDEX_OFFSET: 298
 11843ca8:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12159
 				:0,12157,12814,12159
 11843cb8:			0000: 0000057f 00002f7f
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12160
 				:0,12160,12814,12159
 11843cc0:			0000: 0000057d 00002f80
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11843cc8:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11843cd0:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 302
 				VFD_INDEX_MAX: 305
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 302
 11843cd8:			0000: 00032242 0000012e 00000131 00000000 0000012e
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11843cec:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12161
 				:0,12160,12814,12161
 11843cf4:			0000: 0000057f 00002f81
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -3901,35 +3901,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	0000012e			VFD_INDEX_OFFSET: 302
 11843cfc:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12162
 				:0,12160,12814,12162
 11843d0c:			0000: 0000057f 00002f82
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12163
 				:0,12163,12814,12162
 11843d14:			0000: 0000057d 00002f83
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11843d1c:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11843d24:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 306
 				VFD_INDEX_MAX: 312
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 306
 11843d2c:			0000: 00032242 00000132 00000138 00000000 00000132
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11843d40:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12164
 				:0,12163,12814,12164
 11843d48:			0000: 0000057f 00002f84
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 7 }
@@ -3949,35 +3949,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000132			VFD_INDEX_OFFSET: 306
 11843d50:			0000: c0022200 00000000 00004086 00000007
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12165
 				:0,12163,12814,12165
 11843d60:			0000: 0000057f 00002f85
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12166
 				:0,12166,12814,12165
 11843d68:			0000: 0000057d 00002f86
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11843d70:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11843d78:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 313
 				VFD_INDEX_MAX: 316
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 313
 11843d80:			0000: 00032242 00000139 0000013c 00000000 00000139
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11843d94:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12167
 				:0,12166,12814,12167
 11843d9c:			0000: 0000057f 00002f87
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -3997,35 +3997,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000139			VFD_INDEX_OFFSET: 313
 11843da4:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12168
 				:0,12166,12814,12168
 11843db4:			0000: 0000057f 00002f88
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12169
 				:0,12169,12814,12168
 11843dbc:			0000: 0000057d 00002f89
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11843dc4:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11843dcc:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 317
 				VFD_INDEX_MAX: 323
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 317
 11843dd4:			0000: 00032242 0000013d 00000143 00000000 0000013d
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11843de8:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12170
 				:0,12169,12814,12170
 11843df0:			0000: 0000057f 00002f8a
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 7 }
@@ -4045,35 +4045,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	0000013d			VFD_INDEX_OFFSET: 317
 11843df8:			0000: c0022200 00000000 00004086 00000007
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12171
 				:0,12169,12814,12171
 11843e08:			0000: 0000057f 00002f8b
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12172
 				:0,12172,12814,12171
 11843e10:			0000: 0000057d 00002f8c
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11843e18:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11843e20:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 324
 				VFD_INDEX_MAX: 327
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 324
 11843e28:			0000: 00032242 00000144 00000147 00000000 00000144
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11843e3c:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12173
 				:0,12172,12814,12173
 11843e44:			0000: 0000057f 00002f8d
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -4093,35 +4093,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000144			VFD_INDEX_OFFSET: 324
 11843e4c:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12174
 				:0,12172,12814,12174
 11843e5c:			0000: 0000057f 00002f8e
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12175
 				:0,12175,12814,12174
 11843e64:			0000: 0000057d 00002f8f
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11843e6c:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11843e74:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 328
 				VFD_INDEX_MAX: 331
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 328
 11843e7c:			0000: 00032242 00000148 0000014b 00000000 00000148
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11843e90:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12176
 				:0,12175,12814,12176
 11843e98:			0000: 0000057f 00002f90
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -4141,35 +4141,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000148			VFD_INDEX_OFFSET: 328
 11843ea0:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12177
 				:0,12175,12814,12177
 11843eb0:			0000: 0000057f 00002f91
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12178
 				:0,12178,12814,12177
 11843eb8:			0000: 0000057d 00002f92
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11843ec0:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11843ec8:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 332
 				VFD_INDEX_MAX: 335
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 332
 11843ed0:			0000: 00032242 0000014c 0000014f 00000000 0000014c
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11843ee4:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12179
 				:0,12178,12814,12179
 11843eec:			0000: 0000057f 00002f93
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -4189,35 +4189,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	0000014c			VFD_INDEX_OFFSET: 332
 11843ef4:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12180
 				:0,12178,12814,12180
 11843f04:			0000: 0000057f 00002f94
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12181
 				:0,12181,12814,12180
 11843f0c:			0000: 0000057d 00002f95
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11843f14:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11843f1c:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 336
 				VFD_INDEX_MAX: 339
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 336
 11843f24:			0000: 00032242 00000150 00000153 00000000 00000150
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11843f38:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12182
 				:0,12181,12814,12182
 11843f40:			0000: 0000057f 00002f96
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -4237,35 +4237,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000150			VFD_INDEX_OFFSET: 336
 11843f48:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12183
 				:0,12181,12814,12183
 11843f58:			0000: 0000057f 00002f97
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12184
 				:0,12184,12814,12183
 11843f60:			0000: 0000057d 00002f98
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11843f68:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11843f70:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 340
 				VFD_INDEX_MAX: 346
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 340
 11843f78:			0000: 00032242 00000154 0000015a 00000000 00000154
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11843f8c:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12185
 				:0,12184,12814,12185
 11843f94:			0000: 0000057f 00002f99
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 7 }
@@ -4285,35 +4285,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000154			VFD_INDEX_OFFSET: 340
 11843f9c:			0000: c0022200 00000000 00004086 00000007
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12186
 				:0,12184,12814,12186
 11843fac:			0000: 0000057f 00002f9a
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12187
 				:0,12187,12814,12186
 11843fb4:			0000: 0000057d 00002f9b
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11843fbc:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11843fc4:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 347
 				VFD_INDEX_MAX: 350
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 347
 11843fcc:			0000: 00032242 0000015b 0000015e 00000000 0000015b
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11843fe0:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12188
 				:0,12187,12814,12188
 11843fe8:			0000: 0000057f 00002f9c
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -4333,35 +4333,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	0000015b			VFD_INDEX_OFFSET: 347
 11843ff0:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12189
 				:0,12187,12814,12189
 11844000:			0000: 0000057f 00002f9d
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12190
 				:0,12190,12814,12189
 11844008:			0000: 0000057d 00002f9e
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11844010:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11844018:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 351
 				VFD_INDEX_MAX: 357
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 351
 11844020:			0000: 00032242 0000015f 00000165 00000000 0000015f
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11844034:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12191
 				:0,12190,12814,12191
 1184403c:			0000: 0000057f 00002f9f
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 7 }
@@ -4381,35 +4381,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	0000015f			VFD_INDEX_OFFSET: 351
 11844044:			0000: c0022200 00000000 00004086 00000007
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12192
 				:0,12190,12814,12192
 11844054:			0000: 0000057f 00002fa0
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12193
 				:0,12193,12814,12192
 1184405c:			0000: 0000057d 00002fa1
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11844064:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 1184406c:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 358
 				VFD_INDEX_MAX: 361
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 358
 11844074:			0000: 00032242 00000166 00000169 00000000 00000166
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11844088:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12194
 				:0,12193,12814,12194
 11844090:			0000: 0000057f 00002fa2
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -4429,35 +4429,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000166			VFD_INDEX_OFFSET: 358
 11844098:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12195
 				:0,12193,12814,12195
 118440a8:			0000: 0000057f 00002fa3
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12196
 				:0,12196,12814,12195
 118440b0:			0000: 0000057d 00002fa4
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 118440b8:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 118440c0:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 362
 				VFD_INDEX_MAX: 365
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 362
 118440c8:			0000: 00032242 0000016a 0000016d 00000000 0000016a
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 118440dc:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12197
 				:0,12196,12814,12197
 118440e4:			0000: 0000057f 00002fa5
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -4477,35 +4477,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	0000016a			VFD_INDEX_OFFSET: 362
 118440ec:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12198
 				:0,12196,12814,12198
 118440fc:			0000: 0000057f 00002fa6
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12199
 				:0,12199,12814,12198
 11844104:			0000: 0000057d 00002fa7
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 1184410c:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11844114:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 366
 				VFD_INDEX_MAX: 369
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 366
 1184411c:			0000: 00032242 0000016e 00000171 00000000 0000016e
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11844130:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12200
 				:0,12199,12814,12200
 11844138:			0000: 0000057f 00002fa8
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -4525,35 +4525,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	0000016e			VFD_INDEX_OFFSET: 366
 11844140:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12201
 				:0,12199,12814,12201
 11844150:			0000: 0000057f 00002fa9
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12202
 				:0,12202,12814,12201
 11844158:			0000: 0000057d 00002faa
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11844160:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11844168:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 370
 				VFD_INDEX_MAX: 373
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 370
 11844170:			0000: 00032242 00000172 00000175 00000000 00000172
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11844184:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12203
 				:0,12202,12814,12203
 1184418c:			0000: 0000057f 00002fab
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -4573,35 +4573,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000172			VFD_INDEX_OFFSET: 370
 11844194:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12204
 				:0,12202,12814,12204
 118441a4:			0000: 0000057f 00002fac
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12205
 				:0,12205,12814,12204
 118441ac:			0000: 0000057d 00002fad
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 118441b4:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 118441bc:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 374
 				VFD_INDEX_MAX: 380
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 374
 118441c4:			0000: 00032242 00000176 0000017c 00000000 00000176
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 118441d8:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12206
 				:0,12205,12814,12206
 118441e0:			0000: 0000057f 00002fae
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 7 }
@@ -4621,35 +4621,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000176			VFD_INDEX_OFFSET: 374
 118441e8:			0000: c0022200 00000000 00004086 00000007
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12207
 				:0,12205,12814,12207
 118441f8:			0000: 0000057f 00002faf
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12208
 				:0,12208,12814,12207
 11844200:			0000: 0000057d 00002fb0
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11844208:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11844210:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 381
 				VFD_INDEX_MAX: 384
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 381
 11844218:			0000: 00032242 0000017d 00000180 00000000 0000017d
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 1184422c:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12209
 				:0,12208,12814,12209
 11844234:			0000: 0000057f 00002fb1
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -4669,35 +4669,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	0000017d			VFD_INDEX_OFFSET: 381
 1184423c:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12210
 				:0,12208,12814,12210
 1184424c:			0000: 0000057f 00002fb2
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12211
 				:0,12211,12814,12210
 11844254:			0000: 0000057d 00002fb3
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 1184425c:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11844264:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 385
 				VFD_INDEX_MAX: 391
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 385
 1184426c:			0000: 00032242 00000181 00000187 00000000 00000181
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11844280:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12212
 				:0,12211,12814,12212
 11844288:			0000: 0000057f 00002fb4
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 7 }
@@ -4717,35 +4717,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000181			VFD_INDEX_OFFSET: 385
 11844290:			0000: c0022200 00000000 00004086 00000007
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12213
 				:0,12211,12814,12213
 118442a0:			0000: 0000057f 00002fb5
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12214
 				:0,12214,12814,12213
 118442a8:			0000: 0000057d 00002fb6
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 118442b0:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 118442b8:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 392
 				VFD_INDEX_MAX: 395
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 392
 118442c0:			0000: 00032242 00000188 0000018b 00000000 00000188
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 118442d4:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12215
 				:0,12214,12814,12215
 118442dc:			0000: 0000057f 00002fb7
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -4765,35 +4765,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000188			VFD_INDEX_OFFSET: 392
 118442e4:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12216
 				:0,12214,12814,12216
 118442f4:			0000: 0000057f 00002fb8
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12217
 				:0,12217,12814,12216
 118442fc:			0000: 0000057d 00002fb9
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11844304:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 1184430c:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 396
 				VFD_INDEX_MAX: 399
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 396
 11844314:			0000: 00032242 0000018c 0000018f 00000000 0000018c
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11844328:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12218
 				:0,12217,12814,12218
 11844330:			0000: 0000057f 00002fba
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -4813,35 +4813,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	0000018c			VFD_INDEX_OFFSET: 396
 11844338:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12219
 				:0,12217,12814,12219
 11844348:			0000: 0000057f 00002fbb
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12220
 				:0,12220,12814,12219
 11844350:			0000: 0000057d 00002fbc
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11844358:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11844360:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 400
 				VFD_INDEX_MAX: 403
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 400
 11844368:			0000: 00032242 00000190 00000193 00000000 00000190
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 1184437c:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12221
 				:0,12220,12814,12221
 11844384:			0000: 0000057f 00002fbd
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -4861,35 +4861,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000190			VFD_INDEX_OFFSET: 400
 1184438c:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12222
 				:0,12220,12814,12222
 1184439c:			0000: 0000057f 00002fbe
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12223
 				:0,12223,12814,12222
 118443a4:			0000: 0000057d 00002fbf
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 118443ac:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 118443b4:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 404
 				VFD_INDEX_MAX: 407
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 404
 118443bc:			0000: 00032242 00000194 00000197 00000000 00000194
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 118443d0:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12224
 				:0,12223,12814,12224
 118443d8:			0000: 0000057f 00002fc0
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -4909,35 +4909,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000194			VFD_INDEX_OFFSET: 404
 118443e0:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12225
 				:0,12223,12814,12225
 118443f0:			0000: 0000057f 00002fc1
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12226
 				:0,12226,12814,12225
 118443f8:			0000: 0000057d 00002fc2
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11844400:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11844408:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 408
 				VFD_INDEX_MAX: 414
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 408
 11844410:			0000: 00032242 00000198 0000019e 00000000 00000198
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11844424:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12227
 				:0,12226,12814,12227
 1184442c:			0000: 0000057f 00002fc3
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 7 }
@@ -4957,35 +4957,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000198			VFD_INDEX_OFFSET: 408
 11844434:			0000: c0022200 00000000 00004086 00000007
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12228
 				:0,12226,12814,12228
 11844444:			0000: 0000057f 00002fc4
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12229
 				:0,12229,12814,12228
 1184444c:			0000: 0000057d 00002fc5
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11844454:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 1184445c:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 415
 				VFD_INDEX_MAX: 418
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 415
 11844464:			0000: 00032242 0000019f 000001a2 00000000 0000019f
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11844478:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12230
 				:0,12229,12814,12230
 11844480:			0000: 0000057f 00002fc6
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -5005,35 +5005,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	0000019f			VFD_INDEX_OFFSET: 415
 11844488:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12231
 				:0,12229,12814,12231
 11844498:			0000: 0000057f 00002fc7
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12232
 				:0,12232,12814,12231
 118444a0:			0000: 0000057d 00002fc8
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 118444a8:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 118444b0:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 419
 				VFD_INDEX_MAX: 425
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 419
 118444b8:			0000: 00032242 000001a3 000001a9 00000000 000001a3
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 118444cc:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12233
 				:0,12232,12814,12233
 118444d4:			0000: 0000057f 00002fc9
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 7 }
@@ -5053,35 +5053,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	000001a3			VFD_INDEX_OFFSET: 419
 118444dc:			0000: c0022200 00000000 00004086 00000007
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12234
 				:0,12232,12814,12234
 118444ec:			0000: 0000057f 00002fca
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12235
 				:0,12235,12814,12234
 118444f4:			0000: 0000057d 00002fcb
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 118444fc:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11844504:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 426
 				VFD_INDEX_MAX: 429
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 426
 1184450c:			0000: 00032242 000001aa 000001ad 00000000 000001aa
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11844520:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12236
 				:0,12235,12814,12236
 11844528:			0000: 0000057f 00002fcc
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -5101,35 +5101,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	000001aa			VFD_INDEX_OFFSET: 426
 11844530:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12237
 				:0,12235,12814,12237
 11844540:			0000: 0000057f 00002fcd
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12238
 				:0,12238,12814,12237
 11844548:			0000: 0000057d 00002fce
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11844550:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11844558:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 430
 				VFD_INDEX_MAX: 433
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 430
 11844560:			0000: 00032242 000001ae 000001b1 00000000 000001ae
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11844574:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12239
 				:0,12238,12814,12239
 1184457c:			0000: 0000057f 00002fcf
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -5149,35 +5149,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	000001ae			VFD_INDEX_OFFSET: 430
 11844584:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12240
 				:0,12238,12814,12240
 11844594:			0000: 0000057f 00002fd0
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12241
 				:0,12241,12814,12240
 1184459c:			0000: 0000057d 00002fd1
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 118445a4:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 118445ac:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 434
 				VFD_INDEX_MAX: 437
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 434
 118445b4:			0000: 00032242 000001b2 000001b5 00000000 000001b2
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 118445c8:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12242
 				:0,12241,12814,12242
 118445d0:			0000: 0000057f 00002fd2
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -5197,35 +5197,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	000001b2			VFD_INDEX_OFFSET: 434
 118445d8:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12243
 				:0,12241,12814,12243
 118445e8:			0000: 0000057f 00002fd3
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12244
 				:0,12244,12814,12243
 118445f0:			0000: 0000057d 00002fd4
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 118445f8:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11844600:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 438
 				VFD_INDEX_MAX: 441
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 438
 11844608:			0000: 00032242 000001b6 000001b9 00000000 000001b6
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 1184461c:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12245
 				:0,12244,12814,12245
 11844624:			0000: 0000057f 00002fd5
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -5245,35 +5245,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	000001b6			VFD_INDEX_OFFSET: 438
 1184462c:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12246
 				:0,12244,12814,12246
 1184463c:			0000: 0000057f 00002fd6
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12247
 				:0,12247,12814,12246
 11844644:			0000: 0000057d 00002fd7
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 1184464c:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11844654:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 442
 				VFD_INDEX_MAX: 448
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 442
 1184465c:			0000: 00032242 000001ba 000001c0 00000000 000001ba
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11844670:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12248
 				:0,12247,12814,12248
 11844678:			0000: 0000057f 00002fd8
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 7 }
@@ -5293,35 +5293,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	000001ba			VFD_INDEX_OFFSET: 442
 11844680:			0000: c0022200 00000000 00004086 00000007
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12249
 				:0,12247,12814,12249
 11844690:			0000: 0000057f 00002fd9
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12250
 				:0,12250,12814,12249
 11844698:			0000: 0000057d 00002fda
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 118446a0:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 118446a8:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 449
 				VFD_INDEX_MAX: 452
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 449
 118446b0:			0000: 00032242 000001c1 000001c4 00000000 000001c1
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 118446c4:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12251
 				:0,12250,12814,12251
 118446cc:			0000: 0000057f 00002fdb
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -5341,35 +5341,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	000001c1			VFD_INDEX_OFFSET: 449
 118446d4:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12252
 				:0,12250,12814,12252
 118446e4:			0000: 0000057f 00002fdc
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12253
 				:0,12253,12814,12252
 118446ec:			0000: 0000057d 00002fdd
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 118446f4:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 118446fc:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 453
 				VFD_INDEX_MAX: 459
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 453
 11844704:			0000: 00032242 000001c5 000001cb 00000000 000001c5
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11844718:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12254
 				:0,12253,12814,12254
 11844720:			0000: 0000057f 00002fde
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 7 }
@@ -5389,35 +5389,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	000001c5			VFD_INDEX_OFFSET: 453
 11844728:			0000: c0022200 00000000 00004086 00000007
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12255
 				:0,12253,12814,12255
 11844738:			0000: 0000057f 00002fdf
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12256
 				:0,12256,12814,12255
 11844740:			0000: 0000057d 00002fe0
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11844748:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11844750:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 460
 				VFD_INDEX_MAX: 463
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 460
 11844758:			0000: 00032242 000001cc 000001cf 00000000 000001cc
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 1184476c:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12257
 				:0,12256,12814,12257
 11844774:			0000: 0000057f 00002fe1
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -5437,35 +5437,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	000001cc			VFD_INDEX_OFFSET: 460
 1184477c:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12258
 				:0,12256,12814,12258
 1184478c:			0000: 0000057f 00002fe2
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12259
 				:0,12259,12814,12258
 11844794:			0000: 0000057d 00002fe3
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 1184479c:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 118447a4:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 464
 				VFD_INDEX_MAX: 467
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 464
 118447ac:			0000: 00032242 000001d0 000001d3 00000000 000001d0
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 118447c0:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12260
 				:0,12259,12814,12260
 118447c8:			0000: 0000057f 00002fe4
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -5485,35 +5485,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	000001d0			VFD_INDEX_OFFSET: 464
 118447d0:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12261
 				:0,12259,12814,12261
 118447e0:			0000: 0000057f 00002fe5
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12262
 				:0,12262,12814,12261
 118447e8:			0000: 0000057d 00002fe6
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 118447f0:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 118447f8:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 468
 				VFD_INDEX_MAX: 471
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 468
 11844800:			0000: 00032242 000001d4 000001d7 00000000 000001d4
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11844814:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12263
 				:0,12262,12814,12263
 1184481c:			0000: 0000057f 00002fe7
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -5533,35 +5533,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	000001d4			VFD_INDEX_OFFSET: 468
 11844824:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12264
 				:0,12262,12814,12264
 11844834:			0000: 0000057f 00002fe8
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12265
 				:0,12265,12814,12264
 1184483c:			0000: 0000057d 00002fe9
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11844844:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 1184484c:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 472
 				VFD_INDEX_MAX: 475
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 472
 11844854:			0000: 00032242 000001d8 000001db 00000000 000001d8
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11844868:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12266
 				:0,12265,12814,12266
 11844870:			0000: 0000057f 00002fea
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -5581,35 +5581,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	000001d8			VFD_INDEX_OFFSET: 472
 11844878:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12267
 				:0,12265,12814,12267
 11844888:			0000: 0000057f 00002feb
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12268
 				:0,12268,12814,12267
 11844890:			0000: 0000057d 00002fec
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11844898:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 118448a0:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 476
 				VFD_INDEX_MAX: 482
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 476
 118448a8:			0000: 00032242 000001dc 000001e2 00000000 000001dc
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 118448bc:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12269
 				:0,12268,12814,12269
 118448c4:			0000: 0000057f 00002fed
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 7 }
@@ -5629,35 +5629,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	000001dc			VFD_INDEX_OFFSET: 476
 118448cc:			0000: c0022200 00000000 00004086 00000007
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12270
 				:0,12268,12814,12270
 118448dc:			0000: 0000057f 00002fee
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12271
 				:0,12271,12814,12270
 118448e4:			0000: 0000057d 00002fef
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 118448ec:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 118448f4:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 483
 				VFD_INDEX_MAX: 486
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 483
 118448fc:			0000: 00032242 000001e3 000001e6 00000000 000001e3
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11844910:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12272
 				:0,12271,12814,12272
 11844918:			0000: 0000057f 00002ff0
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -5677,35 +5677,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	000001e3			VFD_INDEX_OFFSET: 483
 11844920:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12273
 				:0,12271,12814,12273
 11844930:			0000: 0000057f 00002ff1
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12274
 				:0,12274,12814,12273
 11844938:			0000: 0000057d 00002ff2
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11844940:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11844948:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 487
 				VFD_INDEX_MAX: 493
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 487
 11844950:			0000: 00032242 000001e7 000001ed 00000000 000001e7
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11844964:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12275
 				:0,12274,12814,12275
 1184496c:			0000: 0000057f 00002ff3
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 7 }
@@ -5725,35 +5725,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	000001e7			VFD_INDEX_OFFSET: 487
 11844974:			0000: c0022200 00000000 00004086 00000007
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12276
 				:0,12274,12814,12276
 11844984:			0000: 0000057f 00002ff4
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12277
 				:0,12277,12814,12276
 1184498c:			0000: 0000057d 00002ff5
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11844994:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 1184499c:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 494
 				VFD_INDEX_MAX: 497
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 494
 118449a4:			0000: 00032242 000001ee 000001f1 00000000 000001ee
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 118449b8:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12278
 				:0,12277,12814,12278
 118449c0:			0000: 0000057f 00002ff6
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -5773,35 +5773,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	000001ee			VFD_INDEX_OFFSET: 494
 118449c8:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12279
 				:0,12277,12814,12279
 118449d8:			0000: 0000057f 00002ff7
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12280
 				:0,12280,12814,12279
 118449e0:			0000: 0000057d 00002ff8
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 118449e8:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 118449f0:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 498
 				VFD_INDEX_MAX: 501
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 498
 118449f8:			0000: 00032242 000001f2 000001f5 00000000 000001f2
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11844a0c:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12281
 				:0,12280,12814,12281
 11844a14:			0000: 0000057f 00002ff9
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -5821,35 +5821,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	000001f2			VFD_INDEX_OFFSET: 498
 11844a1c:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12282
 				:0,12280,12814,12282
 11844a2c:			0000: 0000057f 00002ffa
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12283
 				:0,12283,12814,12282
 11844a34:			0000: 0000057d 00002ffb
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11844a3c:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11844a44:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 502
 				VFD_INDEX_MAX: 505
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 502
 11844a4c:			0000: 00032242 000001f6 000001f9 00000000 000001f6
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11844a60:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12284
 				:0,12283,12814,12284
 11844a68:			0000: 0000057f 00002ffc
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -5869,35 +5869,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	000001f6			VFD_INDEX_OFFSET: 502
 11844a70:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12285
 				:0,12283,12814,12285
 11844a80:			0000: 0000057f 00002ffd
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12286
 				:0,12286,12814,12285
 11844a88:			0000: 0000057d 00002ffe
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11844a90:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11844a98:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 506
 				VFD_INDEX_MAX: 509
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 506
 11844aa0:			0000: 00032242 000001fa 000001fd 00000000 000001fa
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11844ab4:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12287
 				:0,12286,12814,12287
 11844abc:			0000: 0000057f 00002fff
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -5917,35 +5917,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	000001fa			VFD_INDEX_OFFSET: 506
 11844ac4:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12288
 				:0,12286,12814,12288
 11844ad4:			0000: 0000057f 00003000
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12289
 				:0,12289,12814,12288
 11844adc:			0000: 0000057d 00003001
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11844ae4:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11844aec:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 510
 				VFD_INDEX_MAX: 516
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 510
 11844af4:			0000: 00032242 000001fe 00000204 00000000 000001fe
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11844b08:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12290
 				:0,12289,12814,12290
 11844b10:			0000: 0000057f 00003002
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 7 }
@@ -5965,35 +5965,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	000001fe			VFD_INDEX_OFFSET: 510
 11844b18:			0000: c0022200 00000000 00004086 00000007
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12291
 				:0,12289,12814,12291
 11844b28:			0000: 0000057f 00003003
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12292
 				:0,12292,12814,12291
 11844b30:			0000: 0000057d 00003004
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11844b38:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11844b40:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 517
 				VFD_INDEX_MAX: 520
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 517
 11844b48:			0000: 00032242 00000205 00000208 00000000 00000205
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11844b5c:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12293
 				:0,12292,12814,12293
 11844b64:			0000: 0000057f 00003005
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -6013,35 +6013,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000205			VFD_INDEX_OFFSET: 517
 11844b6c:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12294
 				:0,12292,12814,12294
 11844b7c:			0000: 0000057f 00003006
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12295
 				:0,12295,12814,12294
 11844b84:			0000: 0000057d 00003007
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11844b8c:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11844b94:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 521
 				VFD_INDEX_MAX: 527
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 521
 11844b9c:			0000: 00032242 00000209 0000020f 00000000 00000209
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11844bb0:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12296
 				:0,12295,12814,12296
 11844bb8:			0000: 0000057f 00003008
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 7 }
@@ -6061,35 +6061,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000209			VFD_INDEX_OFFSET: 521
 11844bc0:			0000: c0022200 00000000 00004086 00000007
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12297
 				:0,12295,12814,12297
 11844bd0:			0000: 0000057f 00003009
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12298
 				:0,12298,12814,12297
 11844bd8:			0000: 0000057d 0000300a
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11844be0:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11844be8:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 528
 				VFD_INDEX_MAX: 531
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 528
 11844bf0:			0000: 00032242 00000210 00000213 00000000 00000210
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11844c04:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12299
 				:0,12298,12814,12299
 11844c0c:			0000: 0000057f 0000300b
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -6109,35 +6109,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000210			VFD_INDEX_OFFSET: 528
 11844c14:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12300
 				:0,12298,12814,12300
 11844c24:			0000: 0000057f 0000300c
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12301
 				:0,12301,12814,12300
 11844c2c:			0000: 0000057d 0000300d
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11844c34:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11844c3c:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 532
 				VFD_INDEX_MAX: 535
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 532
 11844c44:			0000: 00032242 00000214 00000217 00000000 00000214
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11844c58:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12302
 				:0,12301,12814,12302
 11844c60:			0000: 0000057f 0000300e
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -6157,35 +6157,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000214			VFD_INDEX_OFFSET: 532
 11844c68:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12303
 				:0,12301,12814,12303
 11844c78:			0000: 0000057f 0000300f
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12304
 				:0,12304,12814,12303
 11844c80:			0000: 0000057d 00003010
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11844c88:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11844c90:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 536
 				VFD_INDEX_MAX: 539
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 536
 11844c98:			0000: 00032242 00000218 0000021b 00000000 00000218
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11844cac:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12305
 				:0,12304,12814,12305
 11844cb4:			0000: 0000057f 00003011
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -6205,35 +6205,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000218			VFD_INDEX_OFFSET: 536
 11844cbc:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12306
 				:0,12304,12814,12306
 11844ccc:			0000: 0000057f 00003012
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12307
 				:0,12307,12814,12306
 11844cd4:			0000: 0000057d 00003013
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11844cdc:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11844ce4:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 540
 				VFD_INDEX_MAX: 543
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 540
 11844cec:			0000: 00032242 0000021c 0000021f 00000000 0000021c
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11844d00:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12308
 				:0,12307,12814,12308
 11844d08:			0000: 0000057f 00003014
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -6253,35 +6253,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	0000021c			VFD_INDEX_OFFSET: 540
 11844d10:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12309
 				:0,12307,12814,12309
 11844d20:			0000: 0000057f 00003015
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12310
 				:0,12310,12814,12309
 11844d28:			0000: 0000057d 00003016
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11844d30:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11844d38:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 544
 				VFD_INDEX_MAX: 550
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 544
 11844d40:			0000: 00032242 00000220 00000226 00000000 00000220
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11844d54:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12311
 				:0,12310,12814,12311
 11844d5c:			0000: 0000057f 00003017
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 7 }
@@ -6301,35 +6301,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000220			VFD_INDEX_OFFSET: 544
 11844d64:			0000: c0022200 00000000 00004086 00000007
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12312
 				:0,12310,12814,12312
 11844d74:			0000: 0000057f 00003018
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12313
 				:0,12313,12814,12312
 11844d7c:			0000: 0000057d 00003019
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11844d84:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11844d8c:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 551
 				VFD_INDEX_MAX: 554
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 551
 11844d94:			0000: 00032242 00000227 0000022a 00000000 00000227
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11844da8:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12314
 				:0,12313,12814,12314
 11844db0:			0000: 0000057f 0000301a
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -6349,35 +6349,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000227			VFD_INDEX_OFFSET: 551
 11844db8:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12315
 				:0,12313,12814,12315
 11844dc8:			0000: 0000057f 0000301b
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12316
 				:0,12316,12814,12315
 11844dd0:			0000: 0000057d 0000301c
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11844dd8:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11844de0:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 555
 				VFD_INDEX_MAX: 561
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 555
 11844de8:			0000: 00032242 0000022b 00000231 00000000 0000022b
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11844dfc:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12317
 				:0,12316,12814,12317
 11844e04:			0000: 0000057f 0000301d
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 7 }
@@ -6397,35 +6397,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	0000022b			VFD_INDEX_OFFSET: 555
 11844e0c:			0000: c0022200 00000000 00004086 00000007
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12318
 				:0,12316,12814,12318
 11844e1c:			0000: 0000057f 0000301e
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12319
 				:0,12319,12814,12318
 11844e24:			0000: 0000057d 0000301f
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11844e2c:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11844e34:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 562
 				VFD_INDEX_MAX: 565
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 562
 11844e3c:			0000: 00032242 00000232 00000235 00000000 00000232
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11844e50:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12320
 				:0,12319,12814,12320
 11844e58:			0000: 0000057f 00003020
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -6445,35 +6445,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000232			VFD_INDEX_OFFSET: 562
 11844e60:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12321
 				:0,12319,12814,12321
 11844e70:			0000: 0000057f 00003021
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12322
 				:0,12322,12814,12321
 11844e78:			0000: 0000057d 00003022
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11844e80:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11844e88:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 566
 				VFD_INDEX_MAX: 569
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 566
 11844e90:			0000: 00032242 00000236 00000239 00000000 00000236
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11844ea4:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12323
 				:0,12322,12814,12323
 11844eac:			0000: 0000057f 00003023
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -6493,35 +6493,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000236			VFD_INDEX_OFFSET: 566
 11844eb4:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12324
 				:0,12322,12814,12324
 11844ec4:			0000: 0000057f 00003024
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12325
 				:0,12325,12814,12324
 11844ecc:			0000: 0000057d 00003025
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11844ed4:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11844edc:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 570
 				VFD_INDEX_MAX: 573
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 570
 11844ee4:			0000: 00032242 0000023a 0000023d 00000000 0000023a
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11844ef8:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12326
 				:0,12325,12814,12326
 11844f00:			0000: 0000057f 00003026
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -6541,35 +6541,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	0000023a			VFD_INDEX_OFFSET: 570
 11844f08:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12327
 				:0,12325,12814,12327
 11844f18:			0000: 0000057f 00003027
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12328
 				:0,12328,12814,12327
 11844f20:			0000: 0000057d 00003028
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11844f28:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11844f30:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 574
 				VFD_INDEX_MAX: 577
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 574
 11844f38:			0000: 00032242 0000023e 00000241 00000000 0000023e
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11844f4c:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12329
 				:0,12328,12814,12329
 11844f54:			0000: 0000057f 00003029
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -6589,35 +6589,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	0000023e			VFD_INDEX_OFFSET: 574
 11844f5c:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12330
 				:0,12328,12814,12330
 11844f6c:			0000: 0000057f 0000302a
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12331
 				:0,12331,12814,12330
 11844f74:			0000: 0000057d 0000302b
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11844f7c:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11844f84:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 578
 				VFD_INDEX_MAX: 584
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 578
 11844f8c:			0000: 00032242 00000242 00000248 00000000 00000242
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11844fa0:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12332
 				:0,12331,12814,12332
 11844fa8:			0000: 0000057f 0000302c
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 7 }
@@ -6637,35 +6637,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000242			VFD_INDEX_OFFSET: 578
 11844fb0:			0000: c0022200 00000000 00004086 00000007
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12333
 				:0,12331,12814,12333
 11844fc0:			0000: 0000057f 0000302d
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12334
 				:0,12334,12814,12333
 11844fc8:			0000: 0000057d 0000302e
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11844fd0:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11844fd8:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 585
 				VFD_INDEX_MAX: 588
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 585
 11844fe0:			0000: 00032242 00000249 0000024c 00000000 00000249
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11844ff4:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12335
 				:0,12334,12814,12335
 11844ffc:			0000: 0000057f 0000302f
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -6685,35 +6685,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000249			VFD_INDEX_OFFSET: 585
 11845004:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12336
 				:0,12334,12814,12336
 11845014:			0000: 0000057f 00003030
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12337
 				:0,12337,12814,12336
 1184501c:			0000: 0000057d 00003031
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11845024:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 1184502c:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 589
 				VFD_INDEX_MAX: 595
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 589
 11845034:			0000: 00032242 0000024d 00000253 00000000 0000024d
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11845048:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12338
 				:0,12337,12814,12338
 11845050:			0000: 0000057f 00003032
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 7 }
@@ -6733,35 +6733,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	0000024d			VFD_INDEX_OFFSET: 589
 11845058:			0000: c0022200 00000000 00004086 00000007
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12339
 				:0,12337,12814,12339
 11845068:			0000: 0000057f 00003033
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12340
 				:0,12340,12814,12339
 11845070:			0000: 0000057d 00003034
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11845078:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11845080:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 596
 				VFD_INDEX_MAX: 599
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 596
 11845088:			0000: 00032242 00000254 00000257 00000000 00000254
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 1184509c:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12341
 				:0,12340,12814,12341
 118450a4:			0000: 0000057f 00003035
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -6781,35 +6781,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000254			VFD_INDEX_OFFSET: 596
 118450ac:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12342
 				:0,12340,12814,12342
 118450bc:			0000: 0000057f 00003036
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12343
 				:0,12343,12814,12342
 118450c4:			0000: 0000057d 00003037
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 118450cc:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 118450d4:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 600
 				VFD_INDEX_MAX: 603
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 600
 118450dc:			0000: 00032242 00000258 0000025b 00000000 00000258
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 118450f0:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12344
 				:0,12343,12814,12344
 118450f8:			0000: 0000057f 00003038
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -6829,35 +6829,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000258			VFD_INDEX_OFFSET: 600
 11845100:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12345
 				:0,12343,12814,12345
 11845110:			0000: 0000057f 00003039
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12346
 				:0,12346,12814,12345
 11845118:			0000: 0000057d 0000303a
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11845120:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11845128:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 604
 				VFD_INDEX_MAX: 607
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 604
 11845130:			0000: 00032242 0000025c 0000025f 00000000 0000025c
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11845144:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12347
 				:0,12346,12814,12347
 1184514c:			0000: 0000057f 0000303b
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -6877,35 +6877,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	0000025c			VFD_INDEX_OFFSET: 604
 11845154:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12348
 				:0,12346,12814,12348
 11845164:			0000: 0000057f 0000303c
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12349
 				:0,12349,12814,12348
 1184516c:			0000: 0000057d 0000303d
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11845174:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 1184517c:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 608
 				VFD_INDEX_MAX: 611
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 608
 11845184:			0000: 00032242 00000260 00000263 00000000 00000260
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11845198:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12350
 				:0,12349,12814,12350
 118451a0:			0000: 0000057f 0000303e
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -6925,35 +6925,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000260			VFD_INDEX_OFFSET: 608
 118451a8:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12351
 				:0,12349,12814,12351
 118451b8:			0000: 0000057f 0000303f
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12352
 				:0,12352,12814,12351
 118451c0:			0000: 0000057d 00003040
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 118451c8:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 118451d0:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 612
 				VFD_INDEX_MAX: 618
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 612
 118451d8:			0000: 00032242 00000264 0000026a 00000000 00000264
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 118451ec:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12353
 				:0,12352,12814,12353
 118451f4:			0000: 0000057f 00003041
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 7 }
@@ -6973,35 +6973,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000264			VFD_INDEX_OFFSET: 612
 118451fc:			0000: c0022200 00000000 00004086 00000007
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12354
 				:0,12352,12814,12354
 1184520c:			0000: 0000057f 00003042
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12355
 				:0,12355,12814,12354
 11845214:			0000: 0000057d 00003043
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 1184521c:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11845224:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 619
 				VFD_INDEX_MAX: 622
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 619
 1184522c:			0000: 00032242 0000026b 0000026e 00000000 0000026b
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11845240:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12356
 				:0,12355,12814,12356
 11845248:			0000: 0000057f 00003044
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -7021,35 +7021,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	0000026b			VFD_INDEX_OFFSET: 619
 11845250:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12357
 				:0,12355,12814,12357
 11845260:			0000: 0000057f 00003045
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12358
 				:0,12358,12814,12357
 11845268:			0000: 0000057d 00003046
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11845270:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11845278:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 623
 				VFD_INDEX_MAX: 629
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 623
 11845280:			0000: 00032242 0000026f 00000275 00000000 0000026f
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11845294:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12359
 				:0,12358,12814,12359
 1184529c:			0000: 0000057f 00003047
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 7 }
@@ -7069,35 +7069,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	0000026f			VFD_INDEX_OFFSET: 623
 118452a4:			0000: c0022200 00000000 00004086 00000007
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12360
 				:0,12358,12814,12360
 118452b4:			0000: 0000057f 00003048
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12361
 				:0,12361,12814,12360
 118452bc:			0000: 0000057d 00003049
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 118452c4:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 118452cc:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 630
 				VFD_INDEX_MAX: 633
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 630
 118452d4:			0000: 00032242 00000276 00000279 00000000 00000276
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 118452e8:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12362
 				:0,12361,12814,12362
 118452f0:			0000: 0000057f 0000304a
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -7117,35 +7117,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000276			VFD_INDEX_OFFSET: 630
 118452f8:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12363
 				:0,12361,12814,12363
 11845308:			0000: 0000057f 0000304b
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12364
 				:0,12364,12814,12363
 11845310:			0000: 0000057d 0000304c
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11845318:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11845320:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 634
 				VFD_INDEX_MAX: 637
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 634
 11845328:			0000: 00032242 0000027a 0000027d 00000000 0000027a
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 1184533c:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12365
 				:0,12364,12814,12365
 11845344:			0000: 0000057f 0000304d
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -7165,35 +7165,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	0000027a			VFD_INDEX_OFFSET: 634
 1184534c:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12366
 				:0,12364,12814,12366
 1184535c:			0000: 0000057f 0000304e
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12367
 				:0,12367,12814,12366
 11845364:			0000: 0000057d 0000304f
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 1184536c:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11845374:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 638
 				VFD_INDEX_MAX: 641
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 638
 1184537c:			0000: 00032242 0000027e 00000281 00000000 0000027e
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11845390:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12368
 				:0,12367,12814,12368
 11845398:			0000: 0000057f 00003050
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -7213,35 +7213,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	0000027e			VFD_INDEX_OFFSET: 638
 118453a0:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12369
 				:0,12367,12814,12369
 118453b0:			0000: 0000057f 00003051
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12370
 				:0,12370,12814,12369
 118453b8:			0000: 0000057d 00003052
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 118453c0:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 118453c8:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 642
 				VFD_INDEX_MAX: 645
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 642
 118453d0:			0000: 00032242 00000282 00000285 00000000 00000282
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 118453e4:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12371
 				:0,12370,12814,12371
 118453ec:			0000: 0000057f 00003053
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -7261,35 +7261,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000282			VFD_INDEX_OFFSET: 642
 118453f4:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12372
 				:0,12370,12814,12372
 11845404:			0000: 0000057f 00003054
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12373
 				:0,12373,12814,12372
 1184540c:			0000: 0000057d 00003055
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11845414:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 1184541c:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 646
 				VFD_INDEX_MAX: 652
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 646
 11845424:			0000: 00032242 00000286 0000028c 00000000 00000286
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11845438:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12374
 				:0,12373,12814,12374
 11845440:			0000: 0000057f 00003056
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 7 }
@@ -7309,35 +7309,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000286			VFD_INDEX_OFFSET: 646
 11845448:			0000: c0022200 00000000 00004086 00000007
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12375
 				:0,12373,12814,12375
 11845458:			0000: 0000057f 00003057
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12376
 				:0,12376,12814,12375
 11845460:			0000: 0000057d 00003058
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11845468:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11845470:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 653
 				VFD_INDEX_MAX: 656
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 653
 11845478:			0000: 00032242 0000028d 00000290 00000000 0000028d
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 1184548c:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12377
 				:0,12376,12814,12377
 11845494:			0000: 0000057f 00003059
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -7357,35 +7357,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	0000028d			VFD_INDEX_OFFSET: 653
 1184549c:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12378
 				:0,12376,12814,12378
 118454ac:			0000: 0000057f 0000305a
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12379
 				:0,12379,12814,12378
 118454b4:			0000: 0000057d 0000305b
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 118454bc:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 118454c4:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 657
 				VFD_INDEX_MAX: 663
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 657
 118454cc:			0000: 00032242 00000291 00000297 00000000 00000291
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 118454e0:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12380
 				:0,12379,12814,12380
 118454e8:			0000: 0000057f 0000305c
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 7 }
@@ -7405,35 +7405,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000291			VFD_INDEX_OFFSET: 657
 118454f0:			0000: c0022200 00000000 00004086 00000007
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12381
 				:0,12379,12814,12381
 11845500:			0000: 0000057f 0000305d
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12382
 				:0,12382,12814,12381
 11845508:			0000: 0000057d 0000305e
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11845510:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11845518:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 664
 				VFD_INDEX_MAX: 667
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 664
 11845520:			0000: 00032242 00000298 0000029b 00000000 00000298
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11845534:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12383
 				:0,12382,12814,12383
 1184553c:			0000: 0000057f 0000305f
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -7453,35 +7453,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000298			VFD_INDEX_OFFSET: 664
 11845544:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12384
 				:0,12382,12814,12384
 11845554:			0000: 0000057f 00003060
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12385
 				:0,12385,12814,12384
 1184555c:			0000: 0000057d 00003061
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11845564:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 1184556c:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 668
 				VFD_INDEX_MAX: 671
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 668
 11845574:			0000: 00032242 0000029c 0000029f 00000000 0000029c
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11845588:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12386
 				:0,12385,12814,12386
 11845590:			0000: 0000057f 00003062
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -7501,35 +7501,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	0000029c			VFD_INDEX_OFFSET: 668
 11845598:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12387
 				:0,12385,12814,12387
 118455a8:			0000: 0000057f 00003063
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12388
 				:0,12388,12814,12387
 118455b0:			0000: 0000057d 00003064
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 118455b8:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 118455c0:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 672
 				VFD_INDEX_MAX: 675
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 672
 118455c8:			0000: 00032242 000002a0 000002a3 00000000 000002a0
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 118455dc:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12389
 				:0,12388,12814,12389
 118455e4:			0000: 0000057f 00003065
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -7549,35 +7549,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	000002a0			VFD_INDEX_OFFSET: 672
 118455ec:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12390
 				:0,12388,12814,12390
 118455fc:			0000: 0000057f 00003066
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12391
 				:0,12391,12814,12390
 11845604:			0000: 0000057d 00003067
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 1184560c:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11845614:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 676
 				VFD_INDEX_MAX: 679
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 676
 1184561c:			0000: 00032242 000002a4 000002a7 00000000 000002a4
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11845630:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12392
 				:0,12391,12814,12392
 11845638:			0000: 0000057f 00003068
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -7597,23 +7597,23 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	000002a4			VFD_INDEX_OFFSET: 676
 11845640:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12393
 				:0,12391,12814,12393
 11845650:			0000: 0000057f 00003069
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12394
 				:0,12394,12814,12393
 11845658:			0000: 0000057d 0000306a
-t0			write UCHE_CACHE_INVALIDATE0_REG (0ea0)
+			write UCHE_CACHE_INVALIDATE0_REG (0ea0)
 NEEDS WFI: UCHE_CACHE_INVALIDATE0_REG (ea0)
 				UCHE_CACHE_INVALIDATE0_REG: { ADDR = 0 }
 NEEDS WFI: UCHE_CACHE_INVALIDATE1_REG (ea1)
 				UCHE_CACHE_INVALIDATE1_REG: { ADDR = 0 | OPCODE = INVALIDATE | ENTIRE_CACHE }
 11845660:			0000: 00010ea0 00000000 90000000
-t3			opcode: CP_LOAD_STATE (30) (43 dwords)
+			opcode: CP_LOAD_STATE (30) (43 dwords)
 				{ DST_OFF = 0 | STATE_SRC = SS_DIRECT | STATE_BLOCK = SB_VERT_SHADER | NUM_UNIT = 20 }
 				{ STATE_TYPE = ST_CONSTANTS | EXT_SRC_ADDR = 0 }
 11845678:				1.462840 -0.071177 0.534908 0.533864 0.331812 1.652796 -0.230062 -0.229613
@@ -7632,51 +7632,51 @@ t3			opcode: CP_LOAD_STATE (30) (43 dwords)
 118456cc:			0060: 3f744935 3e6b1fc2 40bb6c57 3f000000 be97a747 3f50550b 41823527 00000000
 118456ec:			0080: 00000000 00000000 3f800000 40a00000 40a00000 41200000 3f800000 00000000
 1184570c:			00a0: 3f4ccccd 3e4ccccd 3f800000
-t0			write UCHE_CACHE_INVALIDATE0_REG (0ea0)
+			write UCHE_CACHE_INVALIDATE0_REG (0ea0)
 NEEDS WFI: UCHE_CACHE_INVALIDATE0_REG (ea0)
 				UCHE_CACHE_INVALIDATE0_REG: { ADDR = 0 }
 NEEDS WFI: UCHE_CACHE_INVALIDATE1_REG (ea1)
 				UCHE_CACHE_INVALIDATE1_REG: { ADDR = 0 | OPCODE = INVALIDATE | ENTIRE_CACHE }
 11845718:			0000: 00010ea0 00000000 90000000
-t3			opcode: CP_LOAD_STATE (30) (7 dwords)
+			opcode: CP_LOAD_STATE (30) (7 dwords)
 				{ DST_OFF = 20 | STATE_SRC = SS_DIRECT | STATE_BLOCK = SB_VERT_SHADER | NUM_UNIT = 2 }
 				{ STATE_TYPE = ST_CONSTANTS | EXT_SRC_ADDR = 0 }
 11845730:				0.000000 0.000000 0.000000 0.000000
 11845730:				0000: 00000000 00000000 00000000 00000000
 11845724:			0000: c0053000 00a00014 00000001 00000000 00000000 00000000 00000000
-t0			write VFD_FETCH[0].INSTR_0 (2246)
+			write VFD_FETCH[0].INSTR_0 (2246)
 				VFD_FETCH[0].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 24 | SWITCHNEXT | INDEXCODE = 0 | STEPRATE = 1 }
 				VFD_FETCH[0].INSTR_1: 0x127ee000
 11845740:			0000: 00012246 01020c0b 127ee000
-t0			write VFD_DECODE[0].INSTR (2266)
+			write VFD_DECODE[0].INSTR (2266)
 				VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID | SWITCHNEXT }
 1184574c:			0000: 00002266 6c00009f
-t0			write VFD_FETCH[0x1].INSTR_0 (2248)
+			write VFD_FETCH[0x1].INSTR_0 (2248)
 				VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 24 | INDEXCODE = 1 | STEPRATE = 1 }
 				VFD_FETCH[0x1].INSTR_1: 0x127ee00c
 11845754:			0000: 00012248 01040c0b 127ee00c
-t0			write VFD_DECODE[0x1].INSTR (2267)
+			write VFD_DECODE[0x1].INSTR (2267)
 				VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT_32_32_32_FLOAT | REGID = r1.x | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID }
 11845760:			0000: 00002267 2c00409f
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11845768:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11845770:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 0
 				VFD_INDEX_MAX: 6
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 0
 11845778:			0000: 00032242 00000000 00000006 00000000 00000000
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 1184578c:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12395
 				:0,12394,12814,12395
 11845794:			0000: 0000057f 0000306b
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 7 }
@@ -7704,35 +7704,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	6c00009f			VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID | SWITCHNEXT }
  +	2c00409f			VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT_32_32_32_FLOAT | REGID = r1.x | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID }
 1184579c:			0000: c0022200 00000000 00004086 00000007
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12396
 				:0,12394,12814,12396
 118457ac:			0000: 0000057f 0000306c
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12397
 				:0,12397,12814,12396
 118457b4:			0000: 0000057d 0000306d
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 118457bc:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 118457c4:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 7
 				VFD_INDEX_MAX: 10
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 7
 118457cc:			0000: 00032242 00000007 0000000a 00000000 00000007
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 118457e0:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12398
 				:0,12397,12814,12398
 118457e8:			0000: 0000057f 0000306e
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -7752,35 +7752,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000007			VFD_INDEX_OFFSET: 7
 118457f0:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12399
 				:0,12397,12814,12399
 11845800:			0000: 0000057f 0000306f
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12400
 				:0,12400,12814,12399
 11845808:			0000: 0000057d 00003070
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11845810:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11845818:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 11
 				VFD_INDEX_MAX: 17
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 11
 11845820:			0000: 00032242 0000000b 00000011 00000000 0000000b
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11845834:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12401
 				:0,12400,12814,12401
 1184583c:			0000: 0000057f 00003071
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 7 }
@@ -7800,35 +7800,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	0000000b			VFD_INDEX_OFFSET: 11
 11845844:			0000: c0022200 00000000 00004086 00000007
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12402
 				:0,12400,12814,12402
 11845854:			0000: 0000057f 00003072
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12403
 				:0,12403,12814,12402
 1184585c:			0000: 0000057d 00003073
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11845864:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 1184586c:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 18
 				VFD_INDEX_MAX: 21
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 18
 11845874:			0000: 00032242 00000012 00000015 00000000 00000012
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11845888:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12404
 				:0,12403,12814,12404
 11845890:			0000: 0000057f 00003074
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -7848,35 +7848,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000012			VFD_INDEX_OFFSET: 18
 11845898:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12405
 				:0,12403,12814,12405
 118458a8:			0000: 0000057f 00003075
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12406
 				:0,12406,12814,12405
 118458b0:			0000: 0000057d 00003076
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 118458b8:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 118458c0:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 22
 				VFD_INDEX_MAX: 25
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 22
 118458c8:			0000: 00032242 00000016 00000019 00000000 00000016
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 118458dc:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12407
 				:0,12406,12814,12407
 118458e4:			0000: 0000057f 00003077
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -7896,35 +7896,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000016			VFD_INDEX_OFFSET: 22
 118458ec:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12408
 				:0,12406,12814,12408
 118458fc:			0000: 0000057f 00003078
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12409
 				:0,12409,12814,12408
 11845904:			0000: 0000057d 00003079
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 1184590c:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11845914:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 26
 				VFD_INDEX_MAX: 29
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 26
 1184591c:			0000: 00032242 0000001a 0000001d 00000000 0000001a
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11845930:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12410
 				:0,12409,12814,12410
 11845938:			0000: 0000057f 0000307a
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -7944,35 +7944,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	0000001a			VFD_INDEX_OFFSET: 26
 11845940:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12411
 				:0,12409,12814,12411
 11845950:			0000: 0000057f 0000307b
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12412
 				:0,12412,12814,12411
 11845958:			0000: 0000057d 0000307c
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11845960:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11845968:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 30
 				VFD_INDEX_MAX: 33
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 30
 11845970:			0000: 00032242 0000001e 00000021 00000000 0000001e
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11845984:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12413
 				:0,12412,12814,12413
 1184598c:			0000: 0000057f 0000307d
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -7992,35 +7992,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	0000001e			VFD_INDEX_OFFSET: 30
 11845994:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12414
 				:0,12412,12814,12414
 118459a4:			0000: 0000057f 0000307e
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12415
 				:0,12415,12814,12414
 118459ac:			0000: 0000057d 0000307f
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 118459b4:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 118459bc:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 34
 				VFD_INDEX_MAX: 40
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 34
 118459c4:			0000: 00032242 00000022 00000028 00000000 00000022
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 118459d8:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12416
 				:0,12415,12814,12416
 118459e0:			0000: 0000057f 00003080
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 7 }
@@ -8040,35 +8040,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000022			VFD_INDEX_OFFSET: 34
 118459e8:			0000: c0022200 00000000 00004086 00000007
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12417
 				:0,12415,12814,12417
 118459f8:			0000: 0000057f 00003081
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12418
 				:0,12418,12814,12417
 11845a00:			0000: 0000057d 00003082
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11845a08:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11845a10:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 41
 				VFD_INDEX_MAX: 44
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 41
 11845a18:			0000: 00032242 00000029 0000002c 00000000 00000029
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11845a2c:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12419
 				:0,12418,12814,12419
 11845a34:			0000: 0000057f 00003083
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -8088,35 +8088,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000029			VFD_INDEX_OFFSET: 41
 11845a3c:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12420
 				:0,12418,12814,12420
 11845a4c:			0000: 0000057f 00003084
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12421
 				:0,12421,12814,12420
 11845a54:			0000: 0000057d 00003085
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11845a5c:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11845a64:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 45
 				VFD_INDEX_MAX: 51
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 45
 11845a6c:			0000: 00032242 0000002d 00000033 00000000 0000002d
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11845a80:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12422
 				:0,12421,12814,12422
 11845a88:			0000: 0000057f 00003086
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 7 }
@@ -8136,35 +8136,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	0000002d			VFD_INDEX_OFFSET: 45
 11845a90:			0000: c0022200 00000000 00004086 00000007
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12423
 				:0,12421,12814,12423
 11845aa0:			0000: 0000057f 00003087
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12424
 				:0,12424,12814,12423
 11845aa8:			0000: 0000057d 00003088
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11845ab0:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11845ab8:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 52
 				VFD_INDEX_MAX: 55
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 52
 11845ac0:			0000: 00032242 00000034 00000037 00000000 00000034
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11845ad4:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12425
 				:0,12424,12814,12425
 11845adc:			0000: 0000057f 00003089
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -8184,35 +8184,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000034			VFD_INDEX_OFFSET: 52
 11845ae4:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12426
 				:0,12424,12814,12426
 11845af4:			0000: 0000057f 0000308a
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12427
 				:0,12427,12814,12426
 11845afc:			0000: 0000057d 0000308b
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11845b04:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11845b0c:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 56
 				VFD_INDEX_MAX: 59
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 56
 11845b14:			0000: 00032242 00000038 0000003b 00000000 00000038
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11845b28:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12428
 				:0,12427,12814,12428
 11845b30:			0000: 0000057f 0000308c
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -8232,35 +8232,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000038			VFD_INDEX_OFFSET: 56
 11845b38:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12429
 				:0,12427,12814,12429
 11845b48:			0000: 0000057f 0000308d
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12430
 				:0,12430,12814,12429
 11845b50:			0000: 0000057d 0000308e
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11845b58:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11845b60:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 60
 				VFD_INDEX_MAX: 63
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 60
 11845b68:			0000: 00032242 0000003c 0000003f 00000000 0000003c
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11845b7c:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12431
 				:0,12430,12814,12431
 11845b84:			0000: 0000057f 0000308f
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -8280,35 +8280,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	0000003c			VFD_INDEX_OFFSET: 60
 11845b8c:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12432
 				:0,12430,12814,12432
 11845b9c:			0000: 0000057f 00003090
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12433
 				:0,12433,12814,12432
 11845ba4:			0000: 0000057d 00003091
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11845bac:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11845bb4:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 64
 				VFD_INDEX_MAX: 67
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 64
 11845bbc:			0000: 00032242 00000040 00000043 00000000 00000040
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11845bd0:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12434
 				:0,12433,12814,12434
 11845bd8:			0000: 0000057f 00003092
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -8328,35 +8328,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000040			VFD_INDEX_OFFSET: 64
 11845be0:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12435
 				:0,12433,12814,12435
 11845bf0:			0000: 0000057f 00003093
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12436
 				:0,12436,12814,12435
 11845bf8:			0000: 0000057d 00003094
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11845c00:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11845c08:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 68
 				VFD_INDEX_MAX: 74
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 68
 11845c10:			0000: 00032242 00000044 0000004a 00000000 00000044
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11845c24:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12437
 				:0,12436,12814,12437
 11845c2c:			0000: 0000057f 00003095
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 7 }
@@ -8376,35 +8376,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000044			VFD_INDEX_OFFSET: 68
 11845c34:			0000: c0022200 00000000 00004086 00000007
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12438
 				:0,12436,12814,12438
 11845c44:			0000: 0000057f 00003096
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12439
 				:0,12439,12814,12438
 11845c4c:			0000: 0000057d 00003097
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11845c54:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11845c5c:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 75
 				VFD_INDEX_MAX: 78
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 75
 11845c64:			0000: 00032242 0000004b 0000004e 00000000 0000004b
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11845c78:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12440
 				:0,12439,12814,12440
 11845c80:			0000: 0000057f 00003098
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -8424,35 +8424,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	0000004b			VFD_INDEX_OFFSET: 75
 11845c88:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12441
 				:0,12439,12814,12441
 11845c98:			0000: 0000057f 00003099
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12442
 				:0,12442,12814,12441
 11845ca0:			0000: 0000057d 0000309a
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11845ca8:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11845cb0:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 79
 				VFD_INDEX_MAX: 85
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 79
 11845cb8:			0000: 00032242 0000004f 00000055 00000000 0000004f
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11845ccc:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12443
 				:0,12442,12814,12443
 11845cd4:			0000: 0000057f 0000309b
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 7 }
@@ -8472,35 +8472,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	0000004f			VFD_INDEX_OFFSET: 79
 11845cdc:			0000: c0022200 00000000 00004086 00000007
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12444
 				:0,12442,12814,12444
 11845cec:			0000: 0000057f 0000309c
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12445
 				:0,12445,12814,12444
 11845cf4:			0000: 0000057d 0000309d
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11845cfc:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11845d04:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 86
 				VFD_INDEX_MAX: 89
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 86
 11845d0c:			0000: 00032242 00000056 00000059 00000000 00000056
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11845d20:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12446
 				:0,12445,12814,12446
 11845d28:			0000: 0000057f 0000309e
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -8520,35 +8520,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000056			VFD_INDEX_OFFSET: 86
 11845d30:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12447
 				:0,12445,12814,12447
 11845d40:			0000: 0000057f 0000309f
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12448
 				:0,12448,12814,12447
 11845d48:			0000: 0000057d 000030a0
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11845d50:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11845d58:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 90
 				VFD_INDEX_MAX: 93
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 90
 11845d60:			0000: 00032242 0000005a 0000005d 00000000 0000005a
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11845d74:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12449
 				:0,12448,12814,12449
 11845d7c:			0000: 0000057f 000030a1
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -8568,35 +8568,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	0000005a			VFD_INDEX_OFFSET: 90
 11845d84:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12450
 				:0,12448,12814,12450
 11845d94:			0000: 0000057f 000030a2
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12451
 				:0,12451,12814,12450
 11845d9c:			0000: 0000057d 000030a3
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11845da4:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11845dac:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 94
 				VFD_INDEX_MAX: 97
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 94
 11845db4:			0000: 00032242 0000005e 00000061 00000000 0000005e
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11845dc8:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12452
 				:0,12451,12814,12452
 11845dd0:			0000: 0000057f 000030a4
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -8616,35 +8616,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	0000005e			VFD_INDEX_OFFSET: 94
 11845dd8:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12453
 				:0,12451,12814,12453
 11845de8:			0000: 0000057f 000030a5
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12454
 				:0,12454,12814,12453
 11845df0:			0000: 0000057d 000030a6
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11845df8:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11845e00:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 98
 				VFD_INDEX_MAX: 101
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 98
 11845e08:			0000: 00032242 00000062 00000065 00000000 00000062
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11845e1c:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12455
 				:0,12454,12814,12455
 11845e24:			0000: 0000057f 000030a7
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -8664,35 +8664,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000062			VFD_INDEX_OFFSET: 98
 11845e2c:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12456
 				:0,12454,12814,12456
 11845e3c:			0000: 0000057f 000030a8
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12457
 				:0,12457,12814,12456
 11845e44:			0000: 0000057d 000030a9
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11845e4c:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11845e54:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 102
 				VFD_INDEX_MAX: 108
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 102
 11845e5c:			0000: 00032242 00000066 0000006c 00000000 00000066
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11845e70:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12458
 				:0,12457,12814,12458
 11845e78:			0000: 0000057f 000030aa
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 7 }
@@ -8712,35 +8712,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000066			VFD_INDEX_OFFSET: 102
 11845e80:			0000: c0022200 00000000 00004086 00000007
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12459
 				:0,12457,12814,12459
 11845e90:			0000: 0000057f 000030ab
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12460
 				:0,12460,12814,12459
 11845e98:			0000: 0000057d 000030ac
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11845ea0:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11845ea8:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 109
 				VFD_INDEX_MAX: 112
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 109
 11845eb0:			0000: 00032242 0000006d 00000070 00000000 0000006d
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11845ec4:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12461
 				:0,12460,12814,12461
 11845ecc:			0000: 0000057f 000030ad
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -8760,35 +8760,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	0000006d			VFD_INDEX_OFFSET: 109
 11845ed4:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12462
 				:0,12460,12814,12462
 11845ee4:			0000: 0000057f 000030ae
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12463
 				:0,12463,12814,12462
 11845eec:			0000: 0000057d 000030af
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11845ef4:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11845efc:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 113
 				VFD_INDEX_MAX: 119
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 113
 11845f04:			0000: 00032242 00000071 00000077 00000000 00000071
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11845f18:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12464
 				:0,12463,12814,12464
 11845f20:			0000: 0000057f 000030b0
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 7 }
@@ -8808,35 +8808,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000071			VFD_INDEX_OFFSET: 113
 11845f28:			0000: c0022200 00000000 00004086 00000007
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12465
 				:0,12463,12814,12465
 11845f38:			0000: 0000057f 000030b1
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12466
 				:0,12466,12814,12465
 11845f40:			0000: 0000057d 000030b2
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11845f48:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11845f50:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 120
 				VFD_INDEX_MAX: 123
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 120
 11845f58:			0000: 00032242 00000078 0000007b 00000000 00000078
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11845f6c:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12467
 				:0,12466,12814,12467
 11845f74:			0000: 0000057f 000030b3
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -8856,35 +8856,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000078			VFD_INDEX_OFFSET: 120
 11845f7c:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12468
 				:0,12466,12814,12468
 11845f8c:			0000: 0000057f 000030b4
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12469
 				:0,12469,12814,12468
 11845f94:			0000: 0000057d 000030b5
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11845f9c:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11845fa4:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 124
 				VFD_INDEX_MAX: 127
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 124
 11845fac:			0000: 00032242 0000007c 0000007f 00000000 0000007c
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11845fc0:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12470
 				:0,12469,12814,12470
 11845fc8:			0000: 0000057f 000030b6
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -8904,35 +8904,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	0000007c			VFD_INDEX_OFFSET: 124
 11845fd0:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12471
 				:0,12469,12814,12471
 11845fe0:			0000: 0000057f 000030b7
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12472
 				:0,12472,12814,12471
 11845fe8:			0000: 0000057d 000030b8
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11845ff0:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11845ff8:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 128
 				VFD_INDEX_MAX: 131
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 128
 11846000:			0000: 00032242 00000080 00000083 00000000 00000080
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11846014:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12473
 				:0,12472,12814,12473
 1184601c:			0000: 0000057f 000030b9
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -8952,35 +8952,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000080			VFD_INDEX_OFFSET: 128
 11846024:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12474
 				:0,12472,12814,12474
 11846034:			0000: 0000057f 000030ba
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12475
 				:0,12475,12814,12474
 1184603c:			0000: 0000057d 000030bb
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11846044:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 1184604c:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 132
 				VFD_INDEX_MAX: 135
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 132
 11846054:			0000: 00032242 00000084 00000087 00000000 00000084
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11846068:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12476
 				:0,12475,12814,12476
 11846070:			0000: 0000057f 000030bc
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -9000,35 +9000,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000084			VFD_INDEX_OFFSET: 132
 11846078:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12477
 				:0,12475,12814,12477
 11846088:			0000: 0000057f 000030bd
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12478
 				:0,12478,12814,12477
 11846090:			0000: 0000057d 000030be
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11846098:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 118460a0:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 136
 				VFD_INDEX_MAX: 142
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 136
 118460a8:			0000: 00032242 00000088 0000008e 00000000 00000088
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 118460bc:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12479
 				:0,12478,12814,12479
 118460c4:			0000: 0000057f 000030bf
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 7 }
@@ -9048,35 +9048,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000088			VFD_INDEX_OFFSET: 136
 118460cc:			0000: c0022200 00000000 00004086 00000007
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12480
 				:0,12478,12814,12480
 118460dc:			0000: 0000057f 000030c0
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12481
 				:0,12481,12814,12480
 118460e4:			0000: 0000057d 000030c1
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 118460ec:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 118460f4:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 143
 				VFD_INDEX_MAX: 146
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 143
 118460fc:			0000: 00032242 0000008f 00000092 00000000 0000008f
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11846110:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12482
 				:0,12481,12814,12482
 11846118:			0000: 0000057f 000030c2
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -9096,35 +9096,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	0000008f			VFD_INDEX_OFFSET: 143
 11846120:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12483
 				:0,12481,12814,12483
 11846130:			0000: 0000057f 000030c3
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12484
 				:0,12484,12814,12483
 11846138:			0000: 0000057d 000030c4
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11846140:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11846148:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 147
 				VFD_INDEX_MAX: 153
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 147
 11846150:			0000: 00032242 00000093 00000099 00000000 00000093
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11846164:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12485
 				:0,12484,12814,12485
 1184616c:			0000: 0000057f 000030c5
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 7 }
@@ -9144,35 +9144,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000093			VFD_INDEX_OFFSET: 147
 11846174:			0000: c0022200 00000000 00004086 00000007
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12486
 				:0,12484,12814,12486
 11846184:			0000: 0000057f 000030c6
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12487
 				:0,12487,12814,12486
 1184618c:			0000: 0000057d 000030c7
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11846194:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 1184619c:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 154
 				VFD_INDEX_MAX: 157
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 154
 118461a4:			0000: 00032242 0000009a 0000009d 00000000 0000009a
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 118461b8:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12488
 				:0,12487,12814,12488
 118461c0:			0000: 0000057f 000030c8
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -9192,35 +9192,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	0000009a			VFD_INDEX_OFFSET: 154
 118461c8:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12489
 				:0,12487,12814,12489
 118461d8:			0000: 0000057f 000030c9
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12490
 				:0,12490,12814,12489
 118461e0:			0000: 0000057d 000030ca
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 118461e8:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 118461f0:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 158
 				VFD_INDEX_MAX: 161
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 158
 118461f8:			0000: 00032242 0000009e 000000a1 00000000 0000009e
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 1184620c:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12491
 				:0,12490,12814,12491
 11846214:			0000: 0000057f 000030cb
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -9240,35 +9240,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	0000009e			VFD_INDEX_OFFSET: 158
 1184621c:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12492
 				:0,12490,12814,12492
 1184622c:			0000: 0000057f 000030cc
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12493
 				:0,12493,12814,12492
 11846234:			0000: 0000057d 000030cd
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 1184623c:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11846244:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 162
 				VFD_INDEX_MAX: 165
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 162
 1184624c:			0000: 00032242 000000a2 000000a5 00000000 000000a2
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11846260:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12494
 				:0,12493,12814,12494
 11846268:			0000: 0000057f 000030ce
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -9288,35 +9288,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	000000a2			VFD_INDEX_OFFSET: 162
 11846270:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12495
 				:0,12493,12814,12495
 11846280:			0000: 0000057f 000030cf
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12496
 				:0,12496,12814,12495
 11846288:			0000: 0000057d 000030d0
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11846290:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11846298:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 166
 				VFD_INDEX_MAX: 169
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 166
 118462a0:			0000: 00032242 000000a6 000000a9 00000000 000000a6
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 118462b4:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12497
 				:0,12496,12814,12497
 118462bc:			0000: 0000057f 000030d1
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -9336,35 +9336,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	000000a6			VFD_INDEX_OFFSET: 166
 118462c4:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12498
 				:0,12496,12814,12498
 118462d4:			0000: 0000057f 000030d2
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12499
 				:0,12499,12814,12498
 118462dc:			0000: 0000057d 000030d3
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 118462e4:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 118462ec:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 170
 				VFD_INDEX_MAX: 176
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 170
 118462f4:			0000: 00032242 000000aa 000000b0 00000000 000000aa
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11846308:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12500
 				:0,12499,12814,12500
 11846310:			0000: 0000057f 000030d4
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 7 }
@@ -9384,35 +9384,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	000000aa			VFD_INDEX_OFFSET: 170
 11846318:			0000: c0022200 00000000 00004086 00000007
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12501
 				:0,12499,12814,12501
 11846328:			0000: 0000057f 000030d5
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12502
 				:0,12502,12814,12501
 11846330:			0000: 0000057d 000030d6
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11846338:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11846340:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 177
 				VFD_INDEX_MAX: 180
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 177
 11846348:			0000: 00032242 000000b1 000000b4 00000000 000000b1
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 1184635c:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12503
 				:0,12502,12814,12503
 11846364:			0000: 0000057f 000030d7
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -9432,35 +9432,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	000000b1			VFD_INDEX_OFFSET: 177
 1184636c:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12504
 				:0,12502,12814,12504
 1184637c:			0000: 0000057f 000030d8
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12505
 				:0,12505,12814,12504
 11846384:			0000: 0000057d 000030d9
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 1184638c:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11846394:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 181
 				VFD_INDEX_MAX: 187
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 181
 1184639c:			0000: 00032242 000000b5 000000bb 00000000 000000b5
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 118463b0:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12506
 				:0,12505,12814,12506
 118463b8:			0000: 0000057f 000030da
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 7 }
@@ -9480,35 +9480,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	000000b5			VFD_INDEX_OFFSET: 181
 118463c0:			0000: c0022200 00000000 00004086 00000007
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12507
 				:0,12505,12814,12507
 118463d0:			0000: 0000057f 000030db
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12508
 				:0,12508,12814,12507
 118463d8:			0000: 0000057d 000030dc
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 118463e0:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 118463e8:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 188
 				VFD_INDEX_MAX: 191
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 188
 118463f0:			0000: 00032242 000000bc 000000bf 00000000 000000bc
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11846404:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12509
 				:0,12508,12814,12509
 1184640c:			0000: 0000057f 000030dd
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -9528,35 +9528,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	000000bc			VFD_INDEX_OFFSET: 188
 11846414:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12510
 				:0,12508,12814,12510
 11846424:			0000: 0000057f 000030de
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12511
 				:0,12511,12814,12510
 1184642c:			0000: 0000057d 000030df
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11846434:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 1184643c:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 192
 				VFD_INDEX_MAX: 195
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 192
 11846444:			0000: 00032242 000000c0 000000c3 00000000 000000c0
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11846458:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12512
 				:0,12511,12814,12512
 11846460:			0000: 0000057f 000030e0
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -9576,35 +9576,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	000000c0			VFD_INDEX_OFFSET: 192
 11846468:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12513
 				:0,12511,12814,12513
 11846478:			0000: 0000057f 000030e1
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12514
 				:0,12514,12814,12513
 11846480:			0000: 0000057d 000030e2
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11846488:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11846490:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 196
 				VFD_INDEX_MAX: 199
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 196
 11846498:			0000: 00032242 000000c4 000000c7 00000000 000000c4
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 118464ac:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12515
 				:0,12514,12814,12515
 118464b4:			0000: 0000057f 000030e3
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -9624,35 +9624,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	000000c4			VFD_INDEX_OFFSET: 196
 118464bc:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12516
 				:0,12514,12814,12516
 118464cc:			0000: 0000057f 000030e4
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12517
 				:0,12517,12814,12516
 118464d4:			0000: 0000057d 000030e5
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 118464dc:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 118464e4:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 200
 				VFD_INDEX_MAX: 203
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 200
 118464ec:			0000: 00032242 000000c8 000000cb 00000000 000000c8
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11846500:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12518
 				:0,12517,12814,12518
 11846508:			0000: 0000057f 000030e6
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -9672,35 +9672,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	000000c8			VFD_INDEX_OFFSET: 200
 11846510:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12519
 				:0,12517,12814,12519
 11846520:			0000: 0000057f 000030e7
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12520
 				:0,12520,12814,12519
 11846528:			0000: 0000057d 000030e8
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11846530:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11846538:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 204
 				VFD_INDEX_MAX: 210
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 204
 11846540:			0000: 00032242 000000cc 000000d2 00000000 000000cc
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11846554:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12521
 				:0,12520,12814,12521
 1184655c:			0000: 0000057f 000030e9
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 7 }
@@ -9720,35 +9720,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	000000cc			VFD_INDEX_OFFSET: 204
 11846564:			0000: c0022200 00000000 00004086 00000007
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12522
 				:0,12520,12814,12522
 11846574:			0000: 0000057f 000030ea
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12523
 				:0,12523,12814,12522
 1184657c:			0000: 0000057d 000030eb
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11846584:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 1184658c:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 211
 				VFD_INDEX_MAX: 214
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 211
 11846594:			0000: 00032242 000000d3 000000d6 00000000 000000d3
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 118465a8:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12524
 				:0,12523,12814,12524
 118465b0:			0000: 0000057f 000030ec
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -9768,35 +9768,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	000000d3			VFD_INDEX_OFFSET: 211
 118465b8:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12525
 				:0,12523,12814,12525
 118465c8:			0000: 0000057f 000030ed
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12526
 				:0,12526,12814,12525
 118465d0:			0000: 0000057d 000030ee
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 118465d8:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 118465e0:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 215
 				VFD_INDEX_MAX: 221
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 215
 118465e8:			0000: 00032242 000000d7 000000dd 00000000 000000d7
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 118465fc:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12527
 				:0,12526,12814,12527
 11846604:			0000: 0000057f 000030ef
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 7 }
@@ -9816,35 +9816,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	000000d7			VFD_INDEX_OFFSET: 215
 1184660c:			0000: c0022200 00000000 00004086 00000007
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12528
 				:0,12526,12814,12528
 1184661c:			0000: 0000057f 000030f0
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12529
 				:0,12529,12814,12528
 11846624:			0000: 0000057d 000030f1
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 1184662c:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11846634:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 222
 				VFD_INDEX_MAX: 225
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 222
 1184663c:			0000: 00032242 000000de 000000e1 00000000 000000de
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11846650:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12530
 				:0,12529,12814,12530
 11846658:			0000: 0000057f 000030f2
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -9864,35 +9864,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	000000de			VFD_INDEX_OFFSET: 222
 11846660:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12531
 				:0,12529,12814,12531
 11846670:			0000: 0000057f 000030f3
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12532
 				:0,12532,12814,12531
 11846678:			0000: 0000057d 000030f4
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11846680:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11846688:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 226
 				VFD_INDEX_MAX: 229
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 226
 11846690:			0000: 00032242 000000e2 000000e5 00000000 000000e2
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 118466a4:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12533
 				:0,12532,12814,12533
 118466ac:			0000: 0000057f 000030f5
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -9912,35 +9912,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	000000e2			VFD_INDEX_OFFSET: 226
 118466b4:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12534
 				:0,12532,12814,12534
 118466c4:			0000: 0000057f 000030f6
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12535
 				:0,12535,12814,12534
 118466cc:			0000: 0000057d 000030f7
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 118466d4:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 118466dc:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 230
 				VFD_INDEX_MAX: 233
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 230
 118466e4:			0000: 00032242 000000e6 000000e9 00000000 000000e6
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 118466f8:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12536
 				:0,12535,12814,12536
 11846700:			0000: 0000057f 000030f8
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -9960,35 +9960,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	000000e6			VFD_INDEX_OFFSET: 230
 11846708:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12537
 				:0,12535,12814,12537
 11846718:			0000: 0000057f 000030f9
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12538
 				:0,12538,12814,12537
 11846720:			0000: 0000057d 000030fa
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11846728:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11846730:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 234
 				VFD_INDEX_MAX: 237
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 234
 11846738:			0000: 00032242 000000ea 000000ed 00000000 000000ea
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 1184674c:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12539
 				:0,12538,12814,12539
 11846754:			0000: 0000057f 000030fb
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -10008,35 +10008,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	000000ea			VFD_INDEX_OFFSET: 234
 1184675c:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12540
 				:0,12538,12814,12540
 1184676c:			0000: 0000057f 000030fc
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12541
 				:0,12541,12814,12540
 11846774:			0000: 0000057d 000030fd
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 1184677c:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11846784:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 238
 				VFD_INDEX_MAX: 244
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 238
 1184678c:			0000: 00032242 000000ee 000000f4 00000000 000000ee
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 118467a0:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12542
 				:0,12541,12814,12542
 118467a8:			0000: 0000057f 000030fe
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 7 }
@@ -10056,35 +10056,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	000000ee			VFD_INDEX_OFFSET: 238
 118467b0:			0000: c0022200 00000000 00004086 00000007
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12543
 				:0,12541,12814,12543
 118467c0:			0000: 0000057f 000030ff
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12544
 				:0,12544,12814,12543
 118467c8:			0000: 0000057d 00003100
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 118467d0:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 118467d8:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 245
 				VFD_INDEX_MAX: 248
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 245
 118467e0:			0000: 00032242 000000f5 000000f8 00000000 000000f5
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 118467f4:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12545
 				:0,12544,12814,12545
 118467fc:			0000: 0000057f 00003101
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -10104,35 +10104,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	000000f5			VFD_INDEX_OFFSET: 245
 11846804:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12546
 				:0,12544,12814,12546
 11846814:			0000: 0000057f 00003102
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12547
 				:0,12547,12814,12546
 1184681c:			0000: 0000057d 00003103
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11846824:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 1184682c:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 249
 				VFD_INDEX_MAX: 255
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 249
 11846834:			0000: 00032242 000000f9 000000ff 00000000 000000f9
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11846848:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12548
 				:0,12547,12814,12548
 11846850:			0000: 0000057f 00003104
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 7 }
@@ -10152,35 +10152,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	000000f9			VFD_INDEX_OFFSET: 249
 11846858:			0000: c0022200 00000000 00004086 00000007
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12549
 				:0,12547,12814,12549
 11846868:			0000: 0000057f 00003105
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12550
 				:0,12550,12814,12549
 11846870:			0000: 0000057d 00003106
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11846878:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11846880:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 256
 				VFD_INDEX_MAX: 259
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 256
 11846888:			0000: 00032242 00000100 00000103 00000000 00000100
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 1184689c:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12551
 				:0,12550,12814,12551
 118468a4:			0000: 0000057f 00003107
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -10200,35 +10200,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000100			VFD_INDEX_OFFSET: 256
 118468ac:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12552
 				:0,12550,12814,12552
 118468bc:			0000: 0000057f 00003108
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12553
 				:0,12553,12814,12552
 118468c4:			0000: 0000057d 00003109
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 118468cc:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 118468d4:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 260
 				VFD_INDEX_MAX: 263
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 260
 118468dc:			0000: 00032242 00000104 00000107 00000000 00000104
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 118468f0:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12554
 				:0,12553,12814,12554
 118468f8:			0000: 0000057f 0000310a
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -10248,35 +10248,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000104			VFD_INDEX_OFFSET: 260
 11846900:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12555
 				:0,12553,12814,12555
 11846910:			0000: 0000057f 0000310b
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12556
 				:0,12556,12814,12555
 11846918:			0000: 0000057d 0000310c
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11846920:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11846928:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 264
 				VFD_INDEX_MAX: 267
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 264
 11846930:			0000: 00032242 00000108 0000010b 00000000 00000108
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11846944:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12557
 				:0,12556,12814,12557
 1184694c:			0000: 0000057f 0000310d
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -10296,35 +10296,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000108			VFD_INDEX_OFFSET: 264
 11846954:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12558
 				:0,12556,12814,12558
 11846964:			0000: 0000057f 0000310e
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12559
 				:0,12559,12814,12558
 1184696c:			0000: 0000057d 0000310f
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11846974:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 1184697c:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 268
 				VFD_INDEX_MAX: 271
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 268
 11846984:			0000: 00032242 0000010c 0000010f 00000000 0000010c
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11846998:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12560
 				:0,12559,12814,12560
 118469a0:			0000: 0000057f 00003110
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -10344,35 +10344,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	0000010c			VFD_INDEX_OFFSET: 268
 118469a8:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12561
 				:0,12559,12814,12561
 118469b8:			0000: 0000057f 00003111
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12562
 				:0,12562,12814,12561
 118469c0:			0000: 0000057d 00003112
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 118469c8:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 118469d0:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 272
 				VFD_INDEX_MAX: 278
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 272
 118469d8:			0000: 00032242 00000110 00000116 00000000 00000110
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 118469ec:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12563
 				:0,12562,12814,12563
 118469f4:			0000: 0000057f 00003113
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 7 }
@@ -10392,35 +10392,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000110			VFD_INDEX_OFFSET: 272
 118469fc:			0000: c0022200 00000000 00004086 00000007
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12564
 				:0,12562,12814,12564
 11846a0c:			0000: 0000057f 00003114
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12565
 				:0,12565,12814,12564
 11846a14:			0000: 0000057d 00003115
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11846a1c:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11846a24:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 279
 				VFD_INDEX_MAX: 282
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 279
 11846a2c:			0000: 00032242 00000117 0000011a 00000000 00000117
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11846a40:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12566
 				:0,12565,12814,12566
 11846a48:			0000: 0000057f 00003116
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -10440,35 +10440,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000117			VFD_INDEX_OFFSET: 279
 11846a50:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12567
 				:0,12565,12814,12567
 11846a60:			0000: 0000057f 00003117
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12568
 				:0,12568,12814,12567
 11846a68:			0000: 0000057d 00003118
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11846a70:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11846a78:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 283
 				VFD_INDEX_MAX: 289
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 283
 11846a80:			0000: 00032242 0000011b 00000121 00000000 0000011b
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11846a94:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12569
 				:0,12568,12814,12569
 11846a9c:			0000: 0000057f 00003119
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 7 }
@@ -10488,35 +10488,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	0000011b			VFD_INDEX_OFFSET: 283
 11846aa4:			0000: c0022200 00000000 00004086 00000007
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12570
 				:0,12568,12814,12570
 11846ab4:			0000: 0000057f 0000311a
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12571
 				:0,12571,12814,12570
 11846abc:			0000: 0000057d 0000311b
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11846ac4:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11846acc:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 290
 				VFD_INDEX_MAX: 293
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 290
 11846ad4:			0000: 00032242 00000122 00000125 00000000 00000122
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11846ae8:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12572
 				:0,12571,12814,12572
 11846af0:			0000: 0000057f 0000311c
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -10536,35 +10536,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000122			VFD_INDEX_OFFSET: 290
 11846af8:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12573
 				:0,12571,12814,12573
 11846b08:			0000: 0000057f 0000311d
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12574
 				:0,12574,12814,12573
 11846b10:			0000: 0000057d 0000311e
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11846b18:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11846b20:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 294
 				VFD_INDEX_MAX: 297
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 294
 11846b28:			0000: 00032242 00000126 00000129 00000000 00000126
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11846b3c:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12575
 				:0,12574,12814,12575
 11846b44:			0000: 0000057f 0000311f
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -10584,35 +10584,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000126			VFD_INDEX_OFFSET: 294
 11846b4c:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12576
 				:0,12574,12814,12576
 11846b5c:			0000: 0000057f 00003120
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12577
 				:0,12577,12814,12576
 11846b64:			0000: 0000057d 00003121
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11846b6c:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11846b74:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 298
 				VFD_INDEX_MAX: 301
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 298
 11846b7c:			0000: 00032242 0000012a 0000012d 00000000 0000012a
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11846b90:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12578
 				:0,12577,12814,12578
 11846b98:			0000: 0000057f 00003122
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -10632,35 +10632,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	0000012a			VFD_INDEX_OFFSET: 298
 11846ba0:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12579
 				:0,12577,12814,12579
 11846bb0:			0000: 0000057f 00003123
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12580
 				:0,12580,12814,12579
 11846bb8:			0000: 0000057d 00003124
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11846bc0:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11846bc8:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 302
 				VFD_INDEX_MAX: 305
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 302
 11846bd0:			0000: 00032242 0000012e 00000131 00000000 0000012e
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11846be4:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12581
 				:0,12580,12814,12581
 11846bec:			0000: 0000057f 00003125
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -10680,35 +10680,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	0000012e			VFD_INDEX_OFFSET: 302
 11846bf4:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12582
 				:0,12580,12814,12582
 11846c04:			0000: 0000057f 00003126
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12583
 				:0,12583,12814,12582
 11846c0c:			0000: 0000057d 00003127
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11846c14:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11846c1c:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 306
 				VFD_INDEX_MAX: 312
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 306
 11846c24:			0000: 00032242 00000132 00000138 00000000 00000132
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11846c38:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12584
 				:0,12583,12814,12584
 11846c40:			0000: 0000057f 00003128
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 7 }
@@ -10728,35 +10728,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000132			VFD_INDEX_OFFSET: 306
 11846c48:			0000: c0022200 00000000 00004086 00000007
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12585
 				:0,12583,12814,12585
 11846c58:			0000: 0000057f 00003129
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12586
 				:0,12586,12814,12585
 11846c60:			0000: 0000057d 0000312a
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11846c68:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11846c70:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 313
 				VFD_INDEX_MAX: 316
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 313
 11846c78:			0000: 00032242 00000139 0000013c 00000000 00000139
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11846c8c:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12587
 				:0,12586,12814,12587
 11846c94:			0000: 0000057f 0000312b
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -10776,35 +10776,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000139			VFD_INDEX_OFFSET: 313
 11846c9c:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12588
 				:0,12586,12814,12588
 11846cac:			0000: 0000057f 0000312c
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12589
 				:0,12589,12814,12588
 11846cb4:			0000: 0000057d 0000312d
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11846cbc:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11846cc4:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 317
 				VFD_INDEX_MAX: 323
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 317
 11846ccc:			0000: 00032242 0000013d 00000143 00000000 0000013d
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11846ce0:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12590
 				:0,12589,12814,12590
 11846ce8:			0000: 0000057f 0000312e
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 7 }
@@ -10824,35 +10824,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	0000013d			VFD_INDEX_OFFSET: 317
 11846cf0:			0000: c0022200 00000000 00004086 00000007
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12591
 				:0,12589,12814,12591
 11846d00:			0000: 0000057f 0000312f
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12592
 				:0,12592,12814,12591
 11846d08:			0000: 0000057d 00003130
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11846d10:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11846d18:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 324
 				VFD_INDEX_MAX: 327
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 324
 11846d20:			0000: 00032242 00000144 00000147 00000000 00000144
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11846d34:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12593
 				:0,12592,12814,12593
 11846d3c:			0000: 0000057f 00003131
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -10872,35 +10872,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000144			VFD_INDEX_OFFSET: 324
 11846d44:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12594
 				:0,12592,12814,12594
 11846d54:			0000: 0000057f 00003132
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12595
 				:0,12595,12814,12594
 11846d5c:			0000: 0000057d 00003133
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11846d64:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11846d6c:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 328
 				VFD_INDEX_MAX: 331
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 328
 11846d74:			0000: 00032242 00000148 0000014b 00000000 00000148
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11846d88:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12596
 				:0,12595,12814,12596
 11846d90:			0000: 0000057f 00003134
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -10920,35 +10920,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000148			VFD_INDEX_OFFSET: 328
 11846d98:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12597
 				:0,12595,12814,12597
 11846da8:			0000: 0000057f 00003135
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12598
 				:0,12598,12814,12597
 11846db0:			0000: 0000057d 00003136
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11846db8:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11846dc0:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 332
 				VFD_INDEX_MAX: 335
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 332
 11846dc8:			0000: 00032242 0000014c 0000014f 00000000 0000014c
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11846ddc:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12599
 				:0,12598,12814,12599
 11846de4:			0000: 0000057f 00003137
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -10968,35 +10968,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	0000014c			VFD_INDEX_OFFSET: 332
 11846dec:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12600
 				:0,12598,12814,12600
 11846dfc:			0000: 0000057f 00003138
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12601
 				:0,12601,12814,12600
 11846e04:			0000: 0000057d 00003139
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11846e0c:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11846e14:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 336
 				VFD_INDEX_MAX: 339
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 336
 11846e1c:			0000: 00032242 00000150 00000153 00000000 00000150
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11846e30:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12602
 				:0,12601,12814,12602
 11846e38:			0000: 0000057f 0000313a
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -11016,23 +11016,23 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000150			VFD_INDEX_OFFSET: 336
 11846e40:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12603
 				:0,12601,12814,12603
 11846e50:			0000: 0000057f 0000313b
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12604
 				:0,12604,12814,12603
 11846e58:			0000: 0000057d 0000313c
-t0			write UCHE_CACHE_INVALIDATE0_REG (0ea0)
+			write UCHE_CACHE_INVALIDATE0_REG (0ea0)
 NEEDS WFI: UCHE_CACHE_INVALIDATE0_REG (ea0)
 				UCHE_CACHE_INVALIDATE0_REG: { ADDR = 0 }
 NEEDS WFI: UCHE_CACHE_INVALIDATE1_REG (ea1)
 				UCHE_CACHE_INVALIDATE1_REG: { ADDR = 0 | OPCODE = INVALIDATE | ENTIRE_CACHE }
 11846e60:			0000: 00010ea0 00000000 90000000
-t3			opcode: CP_LOAD_STATE (30) (43 dwords)
+			opcode: CP_LOAD_STATE (30) (43 dwords)
 				{ DST_OFF = 0 | STATE_SRC = SS_DIRECT | STATE_BLOCK = SB_VERT_SHADER | NUM_UNIT = 20 }
 				{ STATE_TYPE = ST_CONSTANTS | EXT_SRC_ADDR = 0 }
 11846e78:				1.314712 -0.523992 0.577600 0.576473 0.722172 1.569150 -0.073709 -0.073566
@@ -11051,51 +11051,51 @@ t3			opcode: CP_LOAD_STATE (30) (43 dwords)
 11846ecc:			0060: 3f67ec4c 3d96a98c bf37a732 3f000000 be97a747 3f50550b 41823527 00000000
 11846eec:			0080: 00000000 00000000 3f800000 40a00000 40a00000 41200000 3f800000 3e4ccccd
 11846f0c:			00a0: 3e4ccccd 3f800000 3f800000
-t0			write UCHE_CACHE_INVALIDATE0_REG (0ea0)
+			write UCHE_CACHE_INVALIDATE0_REG (0ea0)
 NEEDS WFI: UCHE_CACHE_INVALIDATE0_REG (ea0)
 				UCHE_CACHE_INVALIDATE0_REG: { ADDR = 0 }
 NEEDS WFI: UCHE_CACHE_INVALIDATE1_REG (ea1)
 				UCHE_CACHE_INVALIDATE1_REG: { ADDR = 0 | OPCODE = INVALIDATE | ENTIRE_CACHE }
 11846f18:			0000: 00010ea0 00000000 90000000
-t3			opcode: CP_LOAD_STATE (30) (7 dwords)
+			opcode: CP_LOAD_STATE (30) (7 dwords)
 				{ DST_OFF = 20 | STATE_SRC = SS_DIRECT | STATE_BLOCK = SB_VERT_SHADER | NUM_UNIT = 2 }
 				{ STATE_TYPE = ST_CONSTANTS | EXT_SRC_ADDR = 0 }
 11846f30:				0.000000 0.000000 0.000000 0.000000
 11846f30:				0000: 00000000 00000000 00000000 00000000
 11846f24:			0000: c0053000 00a00014 00000001 00000000 00000000 00000000 00000000
-t0			write VFD_FETCH[0].INSTR_0 (2246)
+			write VFD_FETCH[0].INSTR_0 (2246)
 				VFD_FETCH[0].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 24 | SWITCHNEXT | INDEXCODE = 0 | STEPRATE = 1 }
 				VFD_FETCH[0].INSTR_1: 0x127f0000
 11846f40:			0000: 00012246 01020c0b 127f0000
-t0			write VFD_DECODE[0].INSTR (2266)
+			write VFD_DECODE[0].INSTR (2266)
 				VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID | SWITCHNEXT }
 11846f4c:			0000: 00002266 6c00009f
-t0			write VFD_FETCH[0x1].INSTR_0 (2248)
+			write VFD_FETCH[0x1].INSTR_0 (2248)
 				VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 24 | INDEXCODE = 1 | STEPRATE = 1 }
 				VFD_FETCH[0x1].INSTR_1: 0x127f000c
 11846f54:			0000: 00012248 01040c0b 127f000c
-t0			write VFD_DECODE[0x1].INSTR (2267)
+			write VFD_DECODE[0x1].INSTR (2267)
 				VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT_32_32_32_FLOAT | REGID = r1.x | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID }
 11846f60:			0000: 00002267 2c00409f
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11846f68:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11846f70:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 0
 				VFD_INDEX_MAX: 6
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 0
 11846f78:			0000: 00032242 00000000 00000006 00000000 00000000
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11846f8c:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12605
 				:0,12604,12814,12605
 11846f94:			0000: 0000057f 0000313d
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 7 }
@@ -11123,35 +11123,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	6c00009f			VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID | SWITCHNEXT }
  +	2c00409f			VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT_32_32_32_FLOAT | REGID = r1.x | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID }
 11846f9c:			0000: c0022200 00000000 00004086 00000007
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12606
 				:0,12604,12814,12606
 11846fac:			0000: 0000057f 0000313e
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12607
 				:0,12607,12814,12606
 11846fb4:			0000: 0000057d 0000313f
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11846fbc:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11846fc4:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 7
 				VFD_INDEX_MAX: 10
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 7
 11846fcc:			0000: 00032242 00000007 0000000a 00000000 00000007
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11846fe0:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12608
 				:0,12607,12814,12608
 11846fe8:			0000: 0000057f 00003140
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -11171,35 +11171,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000007			VFD_INDEX_OFFSET: 7
 11846ff0:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12609
 				:0,12607,12814,12609
 11847000:			0000: 0000057f 00003141
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12610
 				:0,12610,12814,12609
 11847008:			0000: 0000057d 00003142
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11847010:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11847018:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 11
 				VFD_INDEX_MAX: 17
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 11
 11847020:			0000: 00032242 0000000b 00000011 00000000 0000000b
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11847034:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12611
 				:0,12610,12814,12611
 1184703c:			0000: 0000057f 00003143
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 7 }
@@ -11219,35 +11219,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	0000000b			VFD_INDEX_OFFSET: 11
 11847044:			0000: c0022200 00000000 00004086 00000007
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12612
 				:0,12610,12814,12612
 11847054:			0000: 0000057f 00003144
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12613
 				:0,12613,12814,12612
 1184705c:			0000: 0000057d 00003145
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11847064:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 1184706c:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 18
 				VFD_INDEX_MAX: 21
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 18
 11847074:			0000: 00032242 00000012 00000015 00000000 00000012
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11847088:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12614
 				:0,12613,12814,12614
 11847090:			0000: 0000057f 00003146
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -11267,35 +11267,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000012			VFD_INDEX_OFFSET: 18
 11847098:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12615
 				:0,12613,12814,12615
 118470a8:			0000: 0000057f 00003147
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12616
 				:0,12616,12814,12615
 118470b0:			0000: 0000057d 00003148
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 118470b8:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 118470c0:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 22
 				VFD_INDEX_MAX: 25
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 22
 118470c8:			0000: 00032242 00000016 00000019 00000000 00000016
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 118470dc:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12617
 				:0,12616,12814,12617
 118470e4:			0000: 0000057f 00003149
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -11315,35 +11315,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000016			VFD_INDEX_OFFSET: 22
 118470ec:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12618
 				:0,12616,12814,12618
 118470fc:			0000: 0000057f 0000314a
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12619
 				:0,12619,12814,12618
 11847104:			0000: 0000057d 0000314b
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 1184710c:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11847114:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 26
 				VFD_INDEX_MAX: 29
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 26
 1184711c:			0000: 00032242 0000001a 0000001d 00000000 0000001a
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11847130:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12620
 				:0,12619,12814,12620
 11847138:			0000: 0000057f 0000314c
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -11363,35 +11363,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	0000001a			VFD_INDEX_OFFSET: 26
 11847140:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12621
 				:0,12619,12814,12621
 11847150:			0000: 0000057f 0000314d
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12622
 				:0,12622,12814,12621
 11847158:			0000: 0000057d 0000314e
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11847160:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11847168:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 30
 				VFD_INDEX_MAX: 33
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 30
 11847170:			0000: 00032242 0000001e 00000021 00000000 0000001e
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11847184:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12623
 				:0,12622,12814,12623
 1184718c:			0000: 0000057f 0000314f
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -11411,35 +11411,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	0000001e			VFD_INDEX_OFFSET: 30
 11847194:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12624
 				:0,12622,12814,12624
 118471a4:			0000: 0000057f 00003150
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12625
 				:0,12625,12814,12624
 118471ac:			0000: 0000057d 00003151
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 118471b4:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 118471bc:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 34
 				VFD_INDEX_MAX: 40
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 34
 118471c4:			0000: 00032242 00000022 00000028 00000000 00000022
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 118471d8:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12626
 				:0,12625,12814,12626
 118471e0:			0000: 0000057f 00003152
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 7 }
@@ -11459,35 +11459,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000022			VFD_INDEX_OFFSET: 34
 118471e8:			0000: c0022200 00000000 00004086 00000007
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12627
 				:0,12625,12814,12627
 118471f8:			0000: 0000057f 00003153
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12628
 				:0,12628,12814,12627
 11847200:			0000: 0000057d 00003154
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11847208:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11847210:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 41
 				VFD_INDEX_MAX: 44
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 41
 11847218:			0000: 00032242 00000029 0000002c 00000000 00000029
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 1184722c:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12629
 				:0,12628,12814,12629
 11847234:			0000: 0000057f 00003155
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -11507,35 +11507,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000029			VFD_INDEX_OFFSET: 41
 1184723c:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12630
 				:0,12628,12814,12630
 1184724c:			0000: 0000057f 00003156
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12631
 				:0,12631,12814,12630
 11847254:			0000: 0000057d 00003157
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 1184725c:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11847264:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 45
 				VFD_INDEX_MAX: 51
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 45
 1184726c:			0000: 00032242 0000002d 00000033 00000000 0000002d
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11847280:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12632
 				:0,12631,12814,12632
 11847288:			0000: 0000057f 00003158
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 7 }
@@ -11555,35 +11555,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	0000002d			VFD_INDEX_OFFSET: 45
 11847290:			0000: c0022200 00000000 00004086 00000007
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12633
 				:0,12631,12814,12633
 118472a0:			0000: 0000057f 00003159
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12634
 				:0,12634,12814,12633
 118472a8:			0000: 0000057d 0000315a
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 118472b0:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 118472b8:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 52
 				VFD_INDEX_MAX: 55
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 52
 118472c0:			0000: 00032242 00000034 00000037 00000000 00000034
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 118472d4:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12635
 				:0,12634,12814,12635
 118472dc:			0000: 0000057f 0000315b
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -11603,35 +11603,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000034			VFD_INDEX_OFFSET: 52
 118472e4:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12636
 				:0,12634,12814,12636
 118472f4:			0000: 0000057f 0000315c
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12637
 				:0,12637,12814,12636
 118472fc:			0000: 0000057d 0000315d
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11847304:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 1184730c:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 56
 				VFD_INDEX_MAX: 59
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 56
 11847314:			0000: 00032242 00000038 0000003b 00000000 00000038
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11847328:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12638
 				:0,12637,12814,12638
 11847330:			0000: 0000057f 0000315e
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -11651,35 +11651,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000038			VFD_INDEX_OFFSET: 56
 11847338:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12639
 				:0,12637,12814,12639
 11847348:			0000: 0000057f 0000315f
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12640
 				:0,12640,12814,12639
 11847350:			0000: 0000057d 00003160
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11847358:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11847360:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 60
 				VFD_INDEX_MAX: 63
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 60
 11847368:			0000: 00032242 0000003c 0000003f 00000000 0000003c
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 1184737c:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12641
 				:0,12640,12814,12641
 11847384:			0000: 0000057f 00003161
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -11699,35 +11699,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	0000003c			VFD_INDEX_OFFSET: 60
 1184738c:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12642
 				:0,12640,12814,12642
 1184739c:			0000: 0000057f 00003162
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12643
 				:0,12643,12814,12642
 118473a4:			0000: 0000057d 00003163
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 118473ac:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 118473b4:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 64
 				VFD_INDEX_MAX: 67
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 64
 118473bc:			0000: 00032242 00000040 00000043 00000000 00000040
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 118473d0:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12644
 				:0,12643,12814,12644
 118473d8:			0000: 0000057f 00003164
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -11747,35 +11747,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000040			VFD_INDEX_OFFSET: 64
 118473e0:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12645
 				:0,12643,12814,12645
 118473f0:			0000: 0000057f 00003165
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12646
 				:0,12646,12814,12645
 118473f8:			0000: 0000057d 00003166
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11847400:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11847408:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 68
 				VFD_INDEX_MAX: 74
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 68
 11847410:			0000: 00032242 00000044 0000004a 00000000 00000044
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11847424:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12647
 				:0,12646,12814,12647
 1184742c:			0000: 0000057f 00003167
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 7 }
@@ -11795,35 +11795,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000044			VFD_INDEX_OFFSET: 68
 11847434:			0000: c0022200 00000000 00004086 00000007
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12648
 				:0,12646,12814,12648
 11847444:			0000: 0000057f 00003168
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12649
 				:0,12649,12814,12648
 1184744c:			0000: 0000057d 00003169
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11847454:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 1184745c:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 75
 				VFD_INDEX_MAX: 78
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 75
 11847464:			0000: 00032242 0000004b 0000004e 00000000 0000004b
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11847478:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12650
 				:0,12649,12814,12650
 11847480:			0000: 0000057f 0000316a
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -11843,35 +11843,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	0000004b			VFD_INDEX_OFFSET: 75
 11847488:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12651
 				:0,12649,12814,12651
 11847498:			0000: 0000057f 0000316b
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12652
 				:0,12652,12814,12651
 118474a0:			0000: 0000057d 0000316c
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 118474a8:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 118474b0:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 79
 				VFD_INDEX_MAX: 85
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 79
 118474b8:			0000: 00032242 0000004f 00000055 00000000 0000004f
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 118474cc:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12653
 				:0,12652,12814,12653
 118474d4:			0000: 0000057f 0000316d
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 7 }
@@ -11891,35 +11891,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	0000004f			VFD_INDEX_OFFSET: 79
 118474dc:			0000: c0022200 00000000 00004086 00000007
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12654
 				:0,12652,12814,12654
 118474ec:			0000: 0000057f 0000316e
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12655
 				:0,12655,12814,12654
 118474f4:			0000: 0000057d 0000316f
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 118474fc:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11847504:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 86
 				VFD_INDEX_MAX: 89
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 86
 1184750c:			0000: 00032242 00000056 00000059 00000000 00000056
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11847520:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12656
 				:0,12655,12814,12656
 11847528:			0000: 0000057f 00003170
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -11939,35 +11939,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000056			VFD_INDEX_OFFSET: 86
 11847530:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12657
 				:0,12655,12814,12657
 11847540:			0000: 0000057f 00003171
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12658
 				:0,12658,12814,12657
 11847548:			0000: 0000057d 00003172
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11847550:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11847558:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 90
 				VFD_INDEX_MAX: 93
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 90
 11847560:			0000: 00032242 0000005a 0000005d 00000000 0000005a
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11847574:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12659
 				:0,12658,12814,12659
 1184757c:			0000: 0000057f 00003173
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -11987,35 +11987,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	0000005a			VFD_INDEX_OFFSET: 90
 11847584:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12660
 				:0,12658,12814,12660
 11847594:			0000: 0000057f 00003174
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12661
 				:0,12661,12814,12660
 1184759c:			0000: 0000057d 00003175
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 118475a4:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 118475ac:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 94
 				VFD_INDEX_MAX: 97
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 94
 118475b4:			0000: 00032242 0000005e 00000061 00000000 0000005e
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 118475c8:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12662
 				:0,12661,12814,12662
 118475d0:			0000: 0000057f 00003176
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -12035,35 +12035,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	0000005e			VFD_INDEX_OFFSET: 94
 118475d8:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12663
 				:0,12661,12814,12663
 118475e8:			0000: 0000057f 00003177
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12664
 				:0,12664,12814,12663
 118475f0:			0000: 0000057d 00003178
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 118475f8:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11847600:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 98
 				VFD_INDEX_MAX: 101
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 98
 11847608:			0000: 00032242 00000062 00000065 00000000 00000062
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 1184761c:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12665
 				:0,12664,12814,12665
 11847624:			0000: 0000057f 00003179
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -12083,35 +12083,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000062			VFD_INDEX_OFFSET: 98
 1184762c:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12666
 				:0,12664,12814,12666
 1184763c:			0000: 0000057f 0000317a
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12667
 				:0,12667,12814,12666
 11847644:			0000: 0000057d 0000317b
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 1184764c:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11847654:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 102
 				VFD_INDEX_MAX: 108
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 102
 1184765c:			0000: 00032242 00000066 0000006c 00000000 00000066
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11847670:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12668
 				:0,12667,12814,12668
 11847678:			0000: 0000057f 0000317c
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 7 }
@@ -12131,35 +12131,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000066			VFD_INDEX_OFFSET: 102
 11847680:			0000: c0022200 00000000 00004086 00000007
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12669
 				:0,12667,12814,12669
 11847690:			0000: 0000057f 0000317d
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12670
 				:0,12670,12814,12669
 11847698:			0000: 0000057d 0000317e
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 118476a0:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 118476a8:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 109
 				VFD_INDEX_MAX: 112
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 109
 118476b0:			0000: 00032242 0000006d 00000070 00000000 0000006d
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 118476c4:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12671
 				:0,12670,12814,12671
 118476cc:			0000: 0000057f 0000317f
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -12179,35 +12179,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	0000006d			VFD_INDEX_OFFSET: 109
 118476d4:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12672
 				:0,12670,12814,12672
 118476e4:			0000: 0000057f 00003180
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12673
 				:0,12673,12814,12672
 118476ec:			0000: 0000057d 00003181
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 118476f4:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 118476fc:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 113
 				VFD_INDEX_MAX: 119
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 113
 11847704:			0000: 00032242 00000071 00000077 00000000 00000071
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11847718:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12674
 				:0,12673,12814,12674
 11847720:			0000: 0000057f 00003182
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 7 }
@@ -12227,35 +12227,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000071			VFD_INDEX_OFFSET: 113
 11847728:			0000: c0022200 00000000 00004086 00000007
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12675
 				:0,12673,12814,12675
 11847738:			0000: 0000057f 00003183
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12676
 				:0,12676,12814,12675
 11847740:			0000: 0000057d 00003184
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11847748:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11847750:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 120
 				VFD_INDEX_MAX: 123
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 120
 11847758:			0000: 00032242 00000078 0000007b 00000000 00000078
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 1184776c:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12677
 				:0,12676,12814,12677
 11847774:			0000: 0000057f 00003185
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -12275,35 +12275,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000078			VFD_INDEX_OFFSET: 120
 1184777c:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12678
 				:0,12676,12814,12678
 1184778c:			0000: 0000057f 00003186
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12679
 				:0,12679,12814,12678
 11847794:			0000: 0000057d 00003187
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 1184779c:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 118477a4:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 124
 				VFD_INDEX_MAX: 127
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 124
 118477ac:			0000: 00032242 0000007c 0000007f 00000000 0000007c
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 118477c0:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12680
 				:0,12679,12814,12680
 118477c8:			0000: 0000057f 00003188
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -12323,35 +12323,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	0000007c			VFD_INDEX_OFFSET: 124
 118477d0:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12681
 				:0,12679,12814,12681
 118477e0:			0000: 0000057f 00003189
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12682
 				:0,12682,12814,12681
 118477e8:			0000: 0000057d 0000318a
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 118477f0:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 118477f8:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 128
 				VFD_INDEX_MAX: 131
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 128
 11847800:			0000: 00032242 00000080 00000083 00000000 00000080
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11847814:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12683
 				:0,12682,12814,12683
 1184781c:			0000: 0000057f 0000318b
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -12371,35 +12371,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000080			VFD_INDEX_OFFSET: 128
 11847824:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12684
 				:0,12682,12814,12684
 11847834:			0000: 0000057f 0000318c
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12685
 				:0,12685,12814,12684
 1184783c:			0000: 0000057d 0000318d
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11847844:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 1184784c:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 132
 				VFD_INDEX_MAX: 135
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 132
 11847854:			0000: 00032242 00000084 00000087 00000000 00000084
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11847868:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12686
 				:0,12685,12814,12686
 11847870:			0000: 0000057f 0000318e
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -12419,35 +12419,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000084			VFD_INDEX_OFFSET: 132
 11847878:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12687
 				:0,12685,12814,12687
 11847888:			0000: 0000057f 0000318f
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12688
 				:0,12688,12814,12687
 11847890:			0000: 0000057d 00003190
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11847898:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 118478a0:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 136
 				VFD_INDEX_MAX: 142
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 136
 118478a8:			0000: 00032242 00000088 0000008e 00000000 00000088
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 118478bc:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12689
 				:0,12688,12814,12689
 118478c4:			0000: 0000057f 00003191
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 7 }
@@ -12467,35 +12467,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000088			VFD_INDEX_OFFSET: 136
 118478cc:			0000: c0022200 00000000 00004086 00000007
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12690
 				:0,12688,12814,12690
 118478dc:			0000: 0000057f 00003192
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12691
 				:0,12691,12814,12690
 118478e4:			0000: 0000057d 00003193
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 118478ec:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 118478f4:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 143
 				VFD_INDEX_MAX: 146
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 143
 118478fc:			0000: 00032242 0000008f 00000092 00000000 0000008f
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11847910:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12692
 				:0,12691,12814,12692
 11847918:			0000: 0000057f 00003194
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -12515,35 +12515,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	0000008f			VFD_INDEX_OFFSET: 143
 11847920:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12693
 				:0,12691,12814,12693
 11847930:			0000: 0000057f 00003195
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12694
 				:0,12694,12814,12693
 11847938:			0000: 0000057d 00003196
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11847940:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11847948:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 147
 				VFD_INDEX_MAX: 153
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 147
 11847950:			0000: 00032242 00000093 00000099 00000000 00000093
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11847964:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12695
 				:0,12694,12814,12695
 1184796c:			0000: 0000057f 00003197
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 7 }
@@ -12563,35 +12563,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000093			VFD_INDEX_OFFSET: 147
 11847974:			0000: c0022200 00000000 00004086 00000007
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12696
 				:0,12694,12814,12696
 11847984:			0000: 0000057f 00003198
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12697
 				:0,12697,12814,12696
 1184798c:			0000: 0000057d 00003199
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11847994:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 1184799c:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 154
 				VFD_INDEX_MAX: 157
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 154
 118479a4:			0000: 00032242 0000009a 0000009d 00000000 0000009a
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 118479b8:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12698
 				:0,12697,12814,12698
 118479c0:			0000: 0000057f 0000319a
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -12611,35 +12611,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	0000009a			VFD_INDEX_OFFSET: 154
 118479c8:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12699
 				:0,12697,12814,12699
 118479d8:			0000: 0000057f 0000319b
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12700
 				:0,12700,12814,12699
 118479e0:			0000: 0000057d 0000319c
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 118479e8:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 118479f0:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 158
 				VFD_INDEX_MAX: 161
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 158
 118479f8:			0000: 00032242 0000009e 000000a1 00000000 0000009e
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11847a0c:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12701
 				:0,12700,12814,12701
 11847a14:			0000: 0000057f 0000319d
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -12659,35 +12659,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	0000009e			VFD_INDEX_OFFSET: 158
 11847a1c:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12702
 				:0,12700,12814,12702
 11847a2c:			0000: 0000057f 0000319e
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12703
 				:0,12703,12814,12702
 11847a34:			0000: 0000057d 0000319f
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11847a3c:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11847a44:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 162
 				VFD_INDEX_MAX: 165
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 162
 11847a4c:			0000: 00032242 000000a2 000000a5 00000000 000000a2
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11847a60:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12704
 				:0,12703,12814,12704
 11847a68:			0000: 0000057f 000031a0
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -12707,35 +12707,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	000000a2			VFD_INDEX_OFFSET: 162
 11847a70:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12705
 				:0,12703,12814,12705
 11847a80:			0000: 0000057f 000031a1
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12706
 				:0,12706,12814,12705
 11847a88:			0000: 0000057d 000031a2
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11847a90:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11847a98:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 166
 				VFD_INDEX_MAX: 169
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 166
 11847aa0:			0000: 00032242 000000a6 000000a9 00000000 000000a6
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11847ab4:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12707
 				:0,12706,12814,12707
 11847abc:			0000: 0000057f 000031a3
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -12755,35 +12755,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	000000a6			VFD_INDEX_OFFSET: 166
 11847ac4:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12708
 				:0,12706,12814,12708
 11847ad4:			0000: 0000057f 000031a4
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12709
 				:0,12709,12814,12708
 11847adc:			0000: 0000057d 000031a5
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11847ae4:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11847aec:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 170
 				VFD_INDEX_MAX: 176
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 170
 11847af4:			0000: 00032242 000000aa 000000b0 00000000 000000aa
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11847b08:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12710
 				:0,12709,12814,12710
 11847b10:			0000: 0000057f 000031a6
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 7 }
@@ -12803,35 +12803,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	000000aa			VFD_INDEX_OFFSET: 170
 11847b18:			0000: c0022200 00000000 00004086 00000007
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12711
 				:0,12709,12814,12711
 11847b28:			0000: 0000057f 000031a7
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12712
 				:0,12712,12814,12711
 11847b30:			0000: 0000057d 000031a8
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11847b38:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11847b40:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 177
 				VFD_INDEX_MAX: 180
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 177
 11847b48:			0000: 00032242 000000b1 000000b4 00000000 000000b1
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11847b5c:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12713
 				:0,12712,12814,12713
 11847b64:			0000: 0000057f 000031a9
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -12851,35 +12851,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	000000b1			VFD_INDEX_OFFSET: 177
 11847b6c:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12714
 				:0,12712,12814,12714
 11847b7c:			0000: 0000057f 000031aa
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12715
 				:0,12715,12814,12714
 11847b84:			0000: 0000057d 000031ab
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11847b8c:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11847b94:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 181
 				VFD_INDEX_MAX: 187
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 181
 11847b9c:			0000: 00032242 000000b5 000000bb 00000000 000000b5
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11847bb0:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12716
 				:0,12715,12814,12716
 11847bb8:			0000: 0000057f 000031ac
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 7 }
@@ -12899,35 +12899,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	000000b5			VFD_INDEX_OFFSET: 181
 11847bc0:			0000: c0022200 00000000 00004086 00000007
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12717
 				:0,12715,12814,12717
 11847bd0:			0000: 0000057f 000031ad
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12718
 				:0,12718,12814,12717
 11847bd8:			0000: 0000057d 000031ae
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11847be0:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11847be8:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 188
 				VFD_INDEX_MAX: 191
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 188
 11847bf0:			0000: 00032242 000000bc 000000bf 00000000 000000bc
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11847c04:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12719
 				:0,12718,12814,12719
 11847c0c:			0000: 0000057f 000031af
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -12947,35 +12947,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	000000bc			VFD_INDEX_OFFSET: 188
 11847c14:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12720
 				:0,12718,12814,12720
 11847c24:			0000: 0000057f 000031b0
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12721
 				:0,12721,12814,12720
 11847c2c:			0000: 0000057d 000031b1
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11847c34:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11847c3c:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 192
 				VFD_INDEX_MAX: 195
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 192
 11847c44:			0000: 00032242 000000c0 000000c3 00000000 000000c0
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11847c58:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12722
 				:0,12721,12814,12722
 11847c60:			0000: 0000057f 000031b2
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -12995,35 +12995,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	000000c0			VFD_INDEX_OFFSET: 192
 11847c68:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12723
 				:0,12721,12814,12723
 11847c78:			0000: 0000057f 000031b3
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12724
 				:0,12724,12814,12723
 11847c80:			0000: 0000057d 000031b4
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11847c88:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11847c90:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 196
 				VFD_INDEX_MAX: 199
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 196
 11847c98:			0000: 00032242 000000c4 000000c7 00000000 000000c4
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11847cac:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12725
 				:0,12724,12814,12725
 11847cb4:			0000: 0000057f 000031b5
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -13043,35 +13043,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	000000c4			VFD_INDEX_OFFSET: 196
 11847cbc:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12726
 				:0,12724,12814,12726
 11847ccc:			0000: 0000057f 000031b6
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12727
 				:0,12727,12814,12726
 11847cd4:			0000: 0000057d 000031b7
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11847cdc:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11847ce4:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 200
 				VFD_INDEX_MAX: 203
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 200
 11847cec:			0000: 00032242 000000c8 000000cb 00000000 000000c8
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11847d00:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12728
 				:0,12727,12814,12728
 11847d08:			0000: 0000057f 000031b8
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -13091,35 +13091,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	000000c8			VFD_INDEX_OFFSET: 200
 11847d10:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12729
 				:0,12727,12814,12729
 11847d20:			0000: 0000057f 000031b9
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12730
 				:0,12730,12814,12729
 11847d28:			0000: 0000057d 000031ba
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11847d30:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11847d38:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 204
 				VFD_INDEX_MAX: 210
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 204
 11847d40:			0000: 00032242 000000cc 000000d2 00000000 000000cc
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11847d54:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12731
 				:0,12730,12814,12731
 11847d5c:			0000: 0000057f 000031bb
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 7 }
@@ -13139,35 +13139,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	000000cc			VFD_INDEX_OFFSET: 204
 11847d64:			0000: c0022200 00000000 00004086 00000007
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12732
 				:0,12730,12814,12732
 11847d74:			0000: 0000057f 000031bc
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12733
 				:0,12733,12814,12732
 11847d7c:			0000: 0000057d 000031bd
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11847d84:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11847d8c:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 211
 				VFD_INDEX_MAX: 214
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 211
 11847d94:			0000: 00032242 000000d3 000000d6 00000000 000000d3
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11847da8:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12734
 				:0,12733,12814,12734
 11847db0:			0000: 0000057f 000031be
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -13187,35 +13187,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	000000d3			VFD_INDEX_OFFSET: 211
 11847db8:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12735
 				:0,12733,12814,12735
 11847dc8:			0000: 0000057f 000031bf
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12736
 				:0,12736,12814,12735
 11847dd0:			0000: 0000057d 000031c0
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11847dd8:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11847de0:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 215
 				VFD_INDEX_MAX: 221
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 215
 11847de8:			0000: 00032242 000000d7 000000dd 00000000 000000d7
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11847dfc:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12737
 				:0,12736,12814,12737
 11847e04:			0000: 0000057f 000031c1
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 7 }
@@ -13235,35 +13235,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	000000d7			VFD_INDEX_OFFSET: 215
 11847e0c:			0000: c0022200 00000000 00004086 00000007
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12738
 				:0,12736,12814,12738
 11847e1c:			0000: 0000057f 000031c2
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12739
 				:0,12739,12814,12738
 11847e24:			0000: 0000057d 000031c3
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11847e2c:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11847e34:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 222
 				VFD_INDEX_MAX: 225
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 222
 11847e3c:			0000: 00032242 000000de 000000e1 00000000 000000de
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11847e50:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12740
 				:0,12739,12814,12740
 11847e58:			0000: 0000057f 000031c4
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -13283,35 +13283,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	000000de			VFD_INDEX_OFFSET: 222
 11847e60:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12741
 				:0,12739,12814,12741
 11847e70:			0000: 0000057f 000031c5
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12742
 				:0,12742,12814,12741
 11847e78:			0000: 0000057d 000031c6
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11847e80:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11847e88:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 226
 				VFD_INDEX_MAX: 229
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 226
 11847e90:			0000: 00032242 000000e2 000000e5 00000000 000000e2
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11847ea4:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12743
 				:0,12742,12814,12743
 11847eac:			0000: 0000057f 000031c7
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -13331,35 +13331,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	000000e2			VFD_INDEX_OFFSET: 226
 11847eb4:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12744
 				:0,12742,12814,12744
 11847ec4:			0000: 0000057f 000031c8
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12745
 				:0,12745,12814,12744
 11847ecc:			0000: 0000057d 000031c9
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11847ed4:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11847edc:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 230
 				VFD_INDEX_MAX: 233
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 230
 11847ee4:			0000: 00032242 000000e6 000000e9 00000000 000000e6
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11847ef8:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12746
 				:0,12745,12814,12746
 11847f00:			0000: 0000057f 000031ca
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -13379,35 +13379,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	000000e6			VFD_INDEX_OFFSET: 230
 11847f08:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12747
 				:0,12745,12814,12747
 11847f18:			0000: 0000057f 000031cb
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12748
 				:0,12748,12814,12747
 11847f20:			0000: 0000057d 000031cc
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11847f28:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11847f30:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 234
 				VFD_INDEX_MAX: 237
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 234
 11847f38:			0000: 00032242 000000ea 000000ed 00000000 000000ea
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11847f4c:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12749
 				:0,12748,12814,12749
 11847f54:			0000: 0000057f 000031cd
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -13427,35 +13427,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	000000ea			VFD_INDEX_OFFSET: 234
 11847f5c:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12750
 				:0,12748,12814,12750
 11847f6c:			0000: 0000057f 000031ce
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12751
 				:0,12751,12814,12750
 11847f74:			0000: 0000057d 000031cf
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11847f7c:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11847f84:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 238
 				VFD_INDEX_MAX: 244
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 238
 11847f8c:			0000: 00032242 000000ee 000000f4 00000000 000000ee
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11847fa0:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12752
 				:0,12751,12814,12752
 11847fa8:			0000: 0000057f 000031d0
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 7 }
@@ -13475,35 +13475,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	000000ee			VFD_INDEX_OFFSET: 238
 11847fb0:			0000: c0022200 00000000 00004086 00000007
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12753
 				:0,12751,12814,12753
 11847fc0:			0000: 0000057f 000031d1
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12754
 				:0,12754,12814,12753
 11847fc8:			0000: 0000057d 000031d2
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11847fd0:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11847fd8:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 245
 				VFD_INDEX_MAX: 248
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 245
 11847fe0:			0000: 00032242 000000f5 000000f8 00000000 000000f5
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11847ff4:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12755
 				:0,12754,12814,12755
 11847ffc:			0000: 0000057f 000031d3
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -13523,35 +13523,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	000000f5			VFD_INDEX_OFFSET: 245
 11848004:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12756
 				:0,12754,12814,12756
 11848014:			0000: 0000057f 000031d4
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12757
 				:0,12757,12814,12756
 1184801c:			0000: 0000057d 000031d5
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11848024:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 1184802c:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 249
 				VFD_INDEX_MAX: 255
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 249
 11848034:			0000: 00032242 000000f9 000000ff 00000000 000000f9
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11848048:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12758
 				:0,12757,12814,12758
 11848050:			0000: 0000057f 000031d6
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 7 }
@@ -13571,35 +13571,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	000000f9			VFD_INDEX_OFFSET: 249
 11848058:			0000: c0022200 00000000 00004086 00000007
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12759
 				:0,12757,12814,12759
 11848068:			0000: 0000057f 000031d7
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12760
 				:0,12760,12814,12759
 11848070:			0000: 0000057d 000031d8
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11848078:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11848080:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 256
 				VFD_INDEX_MAX: 259
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 256
 11848088:			0000: 00032242 00000100 00000103 00000000 00000100
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 1184809c:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12761
 				:0,12760,12814,12761
 118480a4:			0000: 0000057f 000031d9
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -13619,35 +13619,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000100			VFD_INDEX_OFFSET: 256
 118480ac:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12762
 				:0,12760,12814,12762
 118480bc:			0000: 0000057f 000031da
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12763
 				:0,12763,12814,12762
 118480c4:			0000: 0000057d 000031db
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 118480cc:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 118480d4:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 260
 				VFD_INDEX_MAX: 263
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 260
 118480dc:			0000: 00032242 00000104 00000107 00000000 00000104
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 118480f0:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12764
 				:0,12763,12814,12764
 118480f8:			0000: 0000057f 000031dc
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -13667,35 +13667,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000104			VFD_INDEX_OFFSET: 260
 11848100:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12765
 				:0,12763,12814,12765
 11848110:			0000: 0000057f 000031dd
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12766
 				:0,12766,12814,12765
 11848118:			0000: 0000057d 000031de
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11848120:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11848128:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 264
 				VFD_INDEX_MAX: 267
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 264
 11848130:			0000: 00032242 00000108 0000010b 00000000 00000108
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11848144:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12767
 				:0,12766,12814,12767
 1184814c:			0000: 0000057f 000031df
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -13715,35 +13715,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000108			VFD_INDEX_OFFSET: 264
 11848154:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12768
 				:0,12766,12814,12768
 11848164:			0000: 0000057f 000031e0
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12769
 				:0,12769,12814,12768
 1184816c:			0000: 0000057d 000031e1
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11848174:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 1184817c:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 268
 				VFD_INDEX_MAX: 271
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 268
 11848184:			0000: 00032242 0000010c 0000010f 00000000 0000010c
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11848198:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12770
 				:0,12769,12814,12770
 118481a0:			0000: 0000057f 000031e2
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -13763,35 +13763,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	0000010c			VFD_INDEX_OFFSET: 268
 118481a8:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12771
 				:0,12769,12814,12771
 118481b8:			0000: 0000057f 000031e3
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12772
 				:0,12772,12814,12771
 118481c0:			0000: 0000057d 000031e4
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 118481c8:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 118481d0:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 272
 				VFD_INDEX_MAX: 278
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 272
 118481d8:			0000: 00032242 00000110 00000116 00000000 00000110
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 118481ec:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12773
 				:0,12772,12814,12773
 118481f4:			0000: 0000057f 000031e5
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 7 }
@@ -13811,35 +13811,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000110			VFD_INDEX_OFFSET: 272
 118481fc:			0000: c0022200 00000000 00004086 00000007
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12774
 				:0,12772,12814,12774
 1184820c:			0000: 0000057f 000031e6
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12775
 				:0,12775,12814,12774
 11848214:			0000: 0000057d 000031e7
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 1184821c:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11848224:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 279
 				VFD_INDEX_MAX: 282
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 279
 1184822c:			0000: 00032242 00000117 0000011a 00000000 00000117
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11848240:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12776
 				:0,12775,12814,12776
 11848248:			0000: 0000057f 000031e8
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -13859,35 +13859,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000117			VFD_INDEX_OFFSET: 279
 11848250:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12777
 				:0,12775,12814,12777
 11848260:			0000: 0000057f 000031e9
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12778
 				:0,12778,12814,12777
 11848268:			0000: 0000057d 000031ea
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11848270:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11848278:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 283
 				VFD_INDEX_MAX: 289
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 283
 11848280:			0000: 00032242 0000011b 00000121 00000000 0000011b
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11848294:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12779
 				:0,12778,12814,12779
 1184829c:			0000: 0000057f 000031eb
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 7 }
@@ -13907,35 +13907,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	0000011b			VFD_INDEX_OFFSET: 283
 118482a4:			0000: c0022200 00000000 00004086 00000007
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12780
 				:0,12778,12814,12780
 118482b4:			0000: 0000057f 000031ec
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12781
 				:0,12781,12814,12780
 118482bc:			0000: 0000057d 000031ed
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 118482c4:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 118482cc:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 290
 				VFD_INDEX_MAX: 293
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 290
 118482d4:			0000: 00032242 00000122 00000125 00000000 00000122
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 118482e8:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12782
 				:0,12781,12814,12782
 118482f0:			0000: 0000057f 000031ee
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -13955,35 +13955,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000122			VFD_INDEX_OFFSET: 290
 118482f8:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12783
 				:0,12781,12814,12783
 11848308:			0000: 0000057f 000031ef
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12784
 				:0,12784,12814,12783
 11848310:			0000: 0000057d 000031f0
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11848318:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11848320:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 294
 				VFD_INDEX_MAX: 297
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 294
 11848328:			0000: 00032242 00000126 00000129 00000000 00000126
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 1184833c:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12785
 				:0,12784,12814,12785
 11848344:			0000: 0000057f 000031f1
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -14003,35 +14003,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000126			VFD_INDEX_OFFSET: 294
 1184834c:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12786
 				:0,12784,12814,12786
 1184835c:			0000: 0000057f 000031f2
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12787
 				:0,12787,12814,12786
 11848364:			0000: 0000057d 000031f3
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 1184836c:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11848374:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 298
 				VFD_INDEX_MAX: 301
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 298
 1184837c:			0000: 00032242 0000012a 0000012d 00000000 0000012a
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11848390:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12788
 				:0,12787,12814,12788
 11848398:			0000: 0000057f 000031f4
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -14051,35 +14051,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	0000012a			VFD_INDEX_OFFSET: 298
 118483a0:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12789
 				:0,12787,12814,12789
 118483b0:			0000: 0000057f 000031f5
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12790
 				:0,12790,12814,12789
 118483b8:			0000: 0000057d 000031f6
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 118483c0:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 118483c8:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 302
 				VFD_INDEX_MAX: 305
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 302
 118483d0:			0000: 00032242 0000012e 00000131 00000000 0000012e
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 118483e4:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12791
 				:0,12790,12814,12791
 118483ec:			0000: 0000057f 000031f7
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -14099,35 +14099,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	0000012e			VFD_INDEX_OFFSET: 302
 118483f4:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12792
 				:0,12790,12814,12792
 11848404:			0000: 0000057f 000031f8
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12793
 				:0,12793,12814,12792
 1184840c:			0000: 0000057d 000031f9
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11848414:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 1184841c:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 306
 				VFD_INDEX_MAX: 312
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 306
 11848424:			0000: 00032242 00000132 00000138 00000000 00000132
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11848438:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12794
 				:0,12793,12814,12794
 11848440:			0000: 0000057f 000031fa
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 7 }
@@ -14147,35 +14147,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000132			VFD_INDEX_OFFSET: 306
 11848448:			0000: c0022200 00000000 00004086 00000007
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12795
 				:0,12793,12814,12795
 11848458:			0000: 0000057f 000031fb
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12796
 				:0,12796,12814,12795
 11848460:			0000: 0000057d 000031fc
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11848468:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11848470:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 313
 				VFD_INDEX_MAX: 316
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 313
 11848478:			0000: 00032242 00000139 0000013c 00000000 00000139
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 1184848c:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12797
 				:0,12796,12814,12797
 11848494:			0000: 0000057f 000031fd
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -14195,35 +14195,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000139			VFD_INDEX_OFFSET: 313
 1184849c:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12798
 				:0,12796,12814,12798
 118484ac:			0000: 0000057f 000031fe
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12799
 				:0,12799,12814,12798
 118484b4:			0000: 0000057d 000031ff
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 118484bc:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 118484c4:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 317
 				VFD_INDEX_MAX: 323
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 317
 118484cc:			0000: 00032242 0000013d 00000143 00000000 0000013d
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 118484e0:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12800
 				:0,12799,12814,12800
 118484e8:			0000: 0000057f 00003200
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 7 }
@@ -14243,35 +14243,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	0000013d			VFD_INDEX_OFFSET: 317
 118484f0:			0000: c0022200 00000000 00004086 00000007
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12801
 				:0,12799,12814,12801
 11848500:			0000: 0000057f 00003201
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12802
 				:0,12802,12814,12801
 11848508:			0000: 0000057d 00003202
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11848510:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11848518:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 324
 				VFD_INDEX_MAX: 327
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 324
 11848520:			0000: 00032242 00000144 00000147 00000000 00000144
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11848534:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12803
 				:0,12802,12814,12803
 1184853c:			0000: 0000057f 00003203
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -14291,35 +14291,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000144			VFD_INDEX_OFFSET: 324
 11848544:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12804
 				:0,12802,12814,12804
 11848554:			0000: 0000057f 00003204
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12805
 				:0,12805,12814,12804
 1184855c:			0000: 0000057d 00003205
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 11848564:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 1184856c:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 328
 				VFD_INDEX_MAX: 331
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 328
 11848574:			0000: 00032242 00000148 0000014b 00000000 00000148
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11848588:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12806
 				:0,12805,12814,12806
 11848590:			0000: 0000057f 00003206
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -14339,35 +14339,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000148			VFD_INDEX_OFFSET: 328
 11848598:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12807
 				:0,12805,12814,12807
 118485a8:			0000: 0000057f 00003207
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12808
 				:0,12808,12814,12807
 118485b0:			0000: 0000057d 00003208
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 118485b8:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 118485c0:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 332
 				VFD_INDEX_MAX: 335
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 332
 118485c8:			0000: 00032242 0000014c 0000014f 00000000 0000014c
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 118485dc:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12809
 				:0,12808,12814,12809
 118485e4:			0000: 0000057f 00003209
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -14387,35 +14387,35 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	0000014c			VFD_INDEX_OFFSET: 332
 118485ec:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12810
 				:0,12808,12814,12810
 118485fc:			0000: 0000057f 0000320a
-t0			write CP_SCRATCH_REG5 (057d)
+			write CP_SCRATCH_REG5 (057d)
 NEEDS WFI: CP_SCRATCH_REG5 (57d)
 				CP_SCRATCH_REG5: 12811
 				:0,12811,12814,12810
 11848604:			0000: 0000057d 0000320b
-t0			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
+			write PC_VERTEX_REUSE_BLOCK_CNTL (21ea)
 				PC_VERTEX_REUSE_BLOCK_CNTL: 0xb
 1184860c:			0000: 000021ea 0000000b
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 11848614:			0000: c0002600 00000000
-t0			write VFD_INDEX_MIN (2242)
+			write VFD_INDEX_MIN (2242)
 				VFD_INDEX_MIN: 336
 				VFD_INDEX_MAX: 339
 				VFD_INSTANCEID_OFFSET: 0
 				VFD_INDEX_OFFSET: 336
 1184861c:			0000: 00032242 00000150 00000153 00000000 00000150
-t0			write PC_RESTART_INDEX (21ed)
+			write PC_RESTART_INDEX (21ed)
 				PC_RESTART_INDEX: 0xffffffff
 11848630:			0000: 000021ed ffffffff
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 				CP_SCRATCH_REG7: 12812
 				:0,12811,12814,12812
 11848638:			0000: 0000057f 0000320c
-t3			opcode: CP_DRAW_INDX (22) (4 dwords)
+			opcode: CP_DRAW_INDX (22) (4 dwords)
 				{ VIZ_QUERY = 0 }
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 				{ NUM_INDICES = 4 }
@@ -14435,34 +14435,34 @@ t3			opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000			VFD_INSTANCEID_OFFSET: 0
 !+	00000150			VFD_INDEX_OFFSET: 336
 11848640:			0000: c0022200 00000000 00004086 00000004
-t0			write CP_SCRATCH_REG7 (057f)
+			write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 				CP_SCRATCH_REG7: 12813
 				:0,12811,12814,12813
 11848650:			0000: 0000057f 0000320d
 11848920:		0000: c0013700 11842370 000018ba
-t0		write CP_SCRATCH_REG6 (057e)
+		write CP_SCRATCH_REG6 (057e)
 NEEDS WFI: CP_SCRATCH_REG6 (57e)
 			CP_SCRATCH_REG6: 12815
 			:0,12811,12815,12813
 1184892c:		0000: 0000057e 0000320f
-t0		write RB_DEPTH_CONTROL (2100)
+		write RB_DEPTH_CONTROL (2100)
 			RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER }
 11848934:		0000: 00002100 00000000
-t0		write RB_STENCIL_CONTROL (2104)
+		write RB_STENCIL_CONTROL (2104)
 			RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP }
 1184893c:		0000: 00002104 00000000
-t0		write RB_STENCILREFMASK (2108)
+		write RB_STENCILREFMASK (2108)
 			RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0xff | 0xff000000 }
 			RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0xff | 0xff000000 }
 11848944:		0000: 00012108 ffff0000 ffff0000
-t0		write GRAS_SU_MODE_CONTROL (2070)
+		write GRAS_SU_MODE_CONTROL (2070)
 			GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 }
 11848950:		0000: 00002070 00000000
-t0		write GRAS_CL_CLIP_CNTL (2040)
+		write GRAS_CL_CLIP_CNTL (2040)
 			GRAS_CL_CLIP_CNTL: { NUM_USER_CLIP_PLANES = 0 }
 11848958:		0000: 00002040 00000000
-t0		write GRAS_CL_VPORT_XOFFSET (2048)
+		write GRAS_CL_VPORT_XOFFSET (2048)
 			GRAS_CL_VPORT_XOFFSET: 149.500000
 			GRAS_CL_VPORT_XSCALE: 150.000000
 			GRAS_CL_VPORT_YOFFSET: 149.500000
@@ -14470,33 +14470,33 @@ t0		write GRAS_CL_VPORT_XOFFSET (2048)
 			GRAS_CL_VPORT_ZOFFSET: 0.000000
 			GRAS_CL_VPORT_ZSCALE: 1.000000
 11848960:		0000: 00052048 43158000 43160000 43158000 c3160000 00000000 3f800000
-t0		write RB_MODE_CONTROL (20c0)
+		write RB_MODE_CONTROL (20c0)
 			RB_MODE_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MRT = 0 | MARB_CACHE_SPLIT_MODE }
 1184897c:		0000: 000020c0 00008200
-t3		opcode: CP_REG_RMW (21) (4 dwords)
+		opcode: CP_REG_RMW (21) (4 dwords)
 			{ DST_REG = 0x20c1 | ROTATE = 0 }
 			{ SRC0 = 12272 }
 			{ SRC1 = 4096 }
 		rmw (RB_RENDER_CONTROL & 0x00002ff0) | 0x00001000)
 NEEDS WFI: rmw (RB_RENDER_CONTROL & 0x00002ff0) | 0x00001000)
 11848984:		0000: c0022100 000020c1 00002ff0 00001000
-t0		write GRAS_SC_CONTROL (2072)
+		write GRAS_SC_CONTROL (2072)
 			GRAS_SC_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MSAA_SAMPLES = MSAA_ONE | RASTER_MODE = 0x1 }
 11848994:		0000: 00002072 00001020
-t0		write PC_PRIM_VTX_CNTL (21ec)
+		write PC_PRIM_VTX_CNTL (21ec)
 			PC_PRIM_VTX_CNTL: { STRIDE_IN_VPC = 0 | POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES | PROVOKING_VTX_LAST }
 1184899c:		0000: 000021ec 02000240
-t0		write GRAS_SC_WINDOW_SCISSOR_TL (2079)
+		write GRAS_SC_WINDOW_SCISSOR_TL (2079)
 			GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
 			GRAS_SC_WINDOW_SCISSOR_BR: { X = 299 | Y = 299 }
 118489a4:		0000: 00012079 00000000 012b012b
-t0		write VFD_INDEX_MIN (2242)
+		write VFD_INDEX_MIN (2242)
 			VFD_INDEX_MIN: 0
 			VFD_INDEX_MAX: 2
 			VFD_INSTANCEID_OFFSET: 0
 			VFD_INDEX_OFFSET: 0
 118489b0:		0000: 00032242 00000000 00000002 00000000 00000000
-t0		write HLSQ_CONTROL_0_REG (2200)
+		write HLSQ_CONTROL_0_REG (2200)
 			HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | SPSHADERRESTART | CYCLETIMEOUTLIMITVPC = 0 | CONSTMODE = 0 | SPCONSTFULLUPDATE }
 			HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | FRAGCOORDXYREGID = r0.x | FRAGCOORDZWREGID = r0.x }
 			HLSQ_CONTROL_2_REG: { FACENESSREGID = r0.x | COVVALUEREGID = r0.x | PRIMALLOCTHRESHOLD = 31 }
@@ -14504,95 +14504,95 @@ t0		write HLSQ_CONTROL_0_REG (2200)
 			HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTSTARTOFFSET = 0 | INSTRLENGTH = 1 }
 			HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 1 | CONSTSTARTOFFSET = 128 | INSTRLENGTH = 1 }
 118489c4:		0000: 00052200 20000210 00000100 7c000000 00000000 01000000 01080001
-t0		write SP_SP_CTRL_REG (22c0)
+		write SP_SP_CTRL_REG (22c0)
 			SP_SP_CTRL_REG: { CONSTMODE = 0 | SLEEPMODE = 1 | L0MODE = 1 }
 118489e0:		0000: 000022c0 00500000
-t0		write SP_VS_LENGTH_REG (22df)
+		write SP_VS_LENGTH_REG (22df)
 			SP_VS_LENGTH_REG: { SHADERLENGTH = 1 }
 118489e8:		0000: 000022df 00000001
-t0		write SP_VS_CTRL_REG0 (22c4)
+		write SP_VS_CTRL_REG0 (22c4)
 			SP_VS_CTRL_REG0: { THREADMODE = MULTI | INSTRBUFFERMODE = BUFFER | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE | LENGTH = 1 }
 			SP_VS_CTRL_REG1: { CONSTLENGTH = 0 | CONSTFOOTPRINT = 0 | INITIALOUTSTANDING = 4 }
 			SP_VS_PARAM_REG: { POSREGID = r0.x | PSIZEREGID = r63.x | TOTALVSOUTVAR = 0 }
 118489f0:		0000: 000222c4 01200402 04000000 0000fc00
-t0		write SP_FS_LENGTH_REG (22ff)
+		write SP_FS_LENGTH_REG (22ff)
 			SP_FS_LENGTH_REG: { SHADERLENGTH = 1 }
 11848a00:		0000: 000022ff 00000001
-t0		write SP_FS_CTRL_REG0 (22e0)
+		write SP_FS_CTRL_REG0 (22e0)
 			SP_FS_CTRL_REG0: { THREADMODE = MULTI | INSTRBUFFERMODE = BUFFER | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 0 | INOUTREGOVERLAP | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE | LENGTH = 1 }
 			SP_FS_CTRL_REG1: { CONSTLENGTH = 1 | CONSTFOOTPRINT = 0 | INITIALOUTSTANDING = 0 | HALFPRECVAROFFSET = 63 }
 11848a08:		0000: 000122e0 01340012 3f000001
-t0		write SP_FS_FLAT_SHAD_MODE_REG_0 (22e8)
+		write SP_FS_FLAT_SHAD_MODE_REG_0 (22e8)
 			SP_FS_FLAT_SHAD_MODE_REG_0: 0
 			SP_FS_FLAT_SHAD_MODE_REG_1: 0
 11848a14:		0000: 000122e8 00000000 00000000
-t0		write SP_FS_OUTPUT_REG (22ec)
+		write SP_FS_OUTPUT_REG (22ec)
 			SP_FS_OUTPUT_REG: { MRT = 0 | DEPTH_REGID = r0.x }
 11848a20:		0000: 000022ec 00000000
-t0		write SP_FS_MRT[0].REG (22f0)
+		write SP_FS_MRT[0].REG (22f0)
 			SP_FS_MRT[0].REG: { REGID = r0.x | HALF_PRECISION }
 			SP_FS_MRT[0x1].REG: { REGID = r0.x }
 			SP_FS_MRT[0x2].REG: { REGID = r0.x }
 			SP_FS_MRT[0x3].REG: { REGID = r0.x }
 11848a28:		0000: 000322f0 00000100 00000000 00000000 00000000
-t0		write VPC_ATTR (2280)
+		write VPC_ATTR (2280)
 			VPC_ATTR: { TOTALATTR = 0 | THRDASSIGN = 1 | LMSIZE = 1 }
 			VPC_PACK: { NUMFPNONPOSVAR = 0 | NUMNONPOSVSVAR = 0 }
 11848a3c:		0000: 00012280 10001000 00000000
-t0		write VPC_VARYING_INTERP[0].MODE (2282)
+		write VPC_VARYING_INTERP[0].MODE (2282)
 			VPC_VARYING_INTERP[0].MODE: { C0 = SMOOTH | C1 = SMOOTH | C2 = SMOOTH | C3 = SMOOTH | C4 = SMOOTH | C5 = SMOOTH | C6 = SMOOTH | C7 = SMOOTH | C8 = SMOOTH | C9 = SMOOTH | CA = SMOOTH | CB = SMOOTH | CC = SMOOTH | CD = SMOOTH | CE = SMOOTH | CF = SMOOTH }
 			VPC_VARYING_INTERP[0x1].MODE: { C0 = SMOOTH | C1 = SMOOTH | C2 = SMOOTH | C3 = SMOOTH | C4 = SMOOTH | C5 = SMOOTH | C6 = SMOOTH | C7 = SMOOTH | C8 = SMOOTH | C9 = SMOOTH | CA = SMOOTH | CB = SMOOTH | CC = SMOOTH | CD = SMOOTH | CE = SMOOTH | CF = SMOOTH }
 			VPC_VARYING_INTERP[0x2].MODE: { C0 = SMOOTH | C1 = SMOOTH | C2 = SMOOTH | C3 = SMOOTH | C4 = SMOOTH | C5 = SMOOTH | C6 = SMOOTH | C7 = SMOOTH | C8 = SMOOTH | C9 = SMOOTH | CA = SMOOTH | CB = SMOOTH | CC = SMOOTH | CD = SMOOTH | CE = SMOOTH | CF = SMOOTH }
 			VPC_VARYING_INTERP[0x3].MODE: { C0 = SMOOTH | C1 = SMOOTH | C2 = SMOOTH | C3 = SMOOTH | C4 = SMOOTH | C5 = SMOOTH | C6 = SMOOTH | C7 = SMOOTH | C8 = SMOOTH | C9 = SMOOTH | CA = SMOOTH | CB = SMOOTH | CC = SMOOTH | CD = SMOOTH | CE = SMOOTH | CF = SMOOTH }
 11848a48:		0000: 00032282 00000000 00000000 00000000 00000000
-t0		write VPC_VARYING_PS_REPL[0].MODE (2286)
+		write VPC_VARYING_PS_REPL[0].MODE (2286)
 			VPC_VARYING_PS_REPL[0].MODE: { C0 = 0 | C1 = 0 | C2 = 0 | C3 = 0 | C4 = 0 | C5 = 0 | C6 = 0 | C7 = 0 | C8 = 0 | C9 = 0 | CA = 0 | CB = 0 | CC = 0 | CD = 0 | CE = 0 | CF = 0 }
 			VPC_VARYING_PS_REPL[0x1].MODE: { C0 = 0 | C1 = 0 | C2 = 0 | C3 = 0 | C4 = 0 | C5 = 0 | C6 = 0 | C7 = 0 | C8 = 0 | C9 = 0 | CA = 0 | CB = 0 | CC = 0 | CD = 0 | CE = 0 | CF = 0 }
 			VPC_VARYING_PS_REPL[0x2].MODE: { C0 = 0 | C1 = 0 | C2 = 0 | C3 = 0 | C4 = 0 | C5 = 0 | C6 = 0 | C7 = 0 | C8 = 0 | C9 = 0 | CA = 0 | CB = 0 | CC = 0 | CD = 0 | CE = 0 | CF = 0 }
 			VPC_VARYING_PS_REPL[0x3].MODE: { C0 = 0 | C1 = 0 | C2 = 0 | C3 = 0 | C4 = 0 | C5 = 0 | C6 = 0 | C7 = 0 | C8 = 0 | C9 = 0 | CA = 0 | CB = 0 | CC = 0 | CD = 0 | CE = 0 | CF = 0 }
 11848a5c:		0000: 00032286 00000000 00000000 00000000 00000000
-t0		write VFD_VS_THREADING_THRESHOLD (227e)
+		write VFD_VS_THREADING_THRESHOLD (227e)
 			VFD_VS_THREADING_THRESHOLD: { REGID_THRESHOLD = 15 | REGID_VTXCNT = r63.x }
 11848a70:		0000: 0000227e 0000fc0f
-t3		opcode: CP_LOAD_STATE (30) (3 dwords)
+		opcode: CP_LOAD_STATE (30) (3 dwords)
 			{ DST_OFF = 0 | STATE_SRC = SS_INDIRECT | STATE_BLOCK = SB_VERT_SHADER | NUM_UNIT = 1 }
 			{ STATE_TYPE = ST_SHADER | EXT_SRC_ADDR = 0x117e2000 }
 11848a78:		0000: c0013000 00640000 117e2000
-t0		write VFD_PERFCOUNTER0_SELECT (0e44)
+		write VFD_PERFCOUNTER0_SELECT (0e44)
 NEEDS WFI: VFD_PERFCOUNTER0_SELECT (e44)
 			VFD_PERFCOUNTER0_SELECT: VFD_PERF_UCHE_BYTE_FETCHED
 11848a84:		0000: 00000e44 00000000
-t3		opcode: CP_LOAD_STATE (30) (3 dwords)
+		opcode: CP_LOAD_STATE (30) (3 dwords)
 			{ DST_OFF = 0 | STATE_SRC = SS_INDIRECT | STATE_BLOCK = SB_FRAG_SHADER | NUM_UNIT = 1 }
 			{ STATE_TYPE = ST_SHADER | EXT_SRC_ADDR = 0x117e1000 }
 11848a8c:		0000: c0013000 00740000 117e1000
-t0		write VFD_PERFCOUNTER0_SELECT (0e44)
+		write VFD_PERFCOUNTER0_SELECT (0e44)
 NEEDS WFI: VFD_PERFCOUNTER0_SELECT (e44)
 			VFD_PERFCOUNTER0_SELECT: VFD_PERF_UCHE_BYTE_FETCHED
 11848a98:		0000: 00000e44 00000000
-t0		write VFD_CONTROL_0 (2240)
+		write VFD_CONTROL_0 (2240)
 			VFD_CONTROL_0: { TOTALATTRTOVS = 4 | PACKETSIZE = 2 | STRMDECINSTRCNT = 1 | STRMFETCHINSTRCNT = 1 }
 			VFD_CONTROL_1: { MAXSTORAGE = 1 | MAXTHRESHOLD = 0 | MINTHRESHOLD = 0 | REGID4VTX = r63.x | REGID4INST = r63.x }
 11848aa0:		0000: 00012240 08480004 fcfc0001
-t0		write VFD_FETCH[0].INSTR_0 (2246)
+		write VFD_FETCH[0].INSTR_0 (2246)
 			VFD_FETCH[0].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 12 | INDEXCODE = 0 | STEPRATE = 1 }
 			VFD_FETCH[0].INSTR_1: 0x127e9000
 11848aac:		0000: 00012246 0100060b 127e9000
-t0		write VFD_DECODE[0].INSTR (2266)
+		write VFD_DECODE[0].INSTR (2266)
 			VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID }
 11848ab8:		0000: 00002266 2c00009f
-t0		write RB_COPY_CONTROL (20ec)
+		write RB_COPY_CONTROL (20ec)
 			RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_ONE | MODE = RB_COPY_DEPTH_STENCIL | FASTCLEAR = 0 | GMEM_BASE = 0x40000 }
 			RB_COPY_DEST_BASE: { BASE = 0x12839000 }
 			RB_COPY_DEST_PITCH: { PITCH = 640 }
 			RB_COPY_DEST_INFO: { TILE = LINEAR | FORMAT = RB_R8G8_UNORM | SWAP = WZYX | DITHER_MODE = DITHER_DISABLE | COMPONENT_ENABLE = 0xf | ENDIAN = ENDIAN_NONE }
 11848ac0:		0000: 000320ec 00040050 0941c800 00000014 0003c030
-t0		write CP_SCRATCH_REG7 (057f)
+		write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 			CP_SCRATCH_REG7: 12816
 			:0,12811,12815,12816
 11848ad4:		0000: 0000057f 00003210
-t3		opcode: CP_DRAW_INDX (22) (4 dwords)
+		opcode: CP_DRAW_INDX (22) (4 dwords)
 			{ VIZ_QUERY = 0 }
 			{ PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 			{ NUM_INDICES = 2 }
@@ -14670,23 +14670,23 @@ t3		opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000		SP_FS_MRT[0x3].REG: { REGID = r0.x }
 !+	00000001		SP_FS_LENGTH_REG: { SHADERLENGTH = 1 }
 11848adc:		0000: c0022200 00000000 00004088 00000002
-t0		write CP_SCRATCH_REG7 (057f)
+		write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 			CP_SCRATCH_REG7: 12817
 			:0,12811,12815,12817
 11848aec:		0000: 0000057f 00003211
-t0		write RB_COPY_CONTROL (20ec)
+		write RB_COPY_CONTROL (20ec)
 			RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_ONE | MODE = RB_COPY_RESOLVE | FASTCLEAR = 0 | GMEM_BASE = 0 }
 			RB_COPY_DEST_BASE: { BASE = 0x12869000 }
 			RB_COPY_DEST_PITCH: { PITCH = 1280 }
 			RB_COPY_DEST_INFO: { TILE = LINEAR | FORMAT = RB_R8G8B8A8_UNORM | SWAP = WXYZ | DITHER_MODE = DITHER_DISABLE | COMPONENT_ENABLE = 0xf | ENDIAN = ENDIAN_NONE }
 11848af4:		0000: 000320ec 00000010 09434800 00000028 0003c120
-t0		write CP_SCRATCH_REG7 (057f)
+		write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 			CP_SCRATCH_REG7: 12818
 			:0,12811,12815,12818
 11848b08:		0000: 0000057f 00003212
-t3		opcode: CP_DRAW_INDX (22) (4 dwords)
+		opcode: CP_DRAW_INDX (22) (4 dwords)
 			{ VIZ_QUERY = 0 }
 			{ PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 			{ NUM_INDICES = 2 }
@@ -14702,103 +14702,103 @@ t3		opcode: CP_DRAW_INDX (22) (4 dwords)
 !+	00000028		RB_COPY_DEST_PITCH: { PITCH = 1280 }
 !+	0003c120		RB_COPY_DEST_INFO: { TILE = LINEAR | FORMAT = RB_R8G8B8A8_UNORM | SWAP = WXYZ | DITHER_MODE = DITHER_DISABLE | COMPONENT_ENABLE = 0xf | ENDIAN = ENDIAN_NONE }
 11848b10:		0000: c0022200 00000000 00004088 00000002
-t0		write CP_SCRATCH_REG7 (057f)
+		write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 			CP_SCRATCH_REG7: 12819
 			:0,12811,12815,12819
 11848b20:		0000: 0000057f 00003213
-t0		write RB_MODE_CONTROL (20c0)
+		write RB_MODE_CONTROL (20c0)
 			RB_MODE_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MRT = 0 | MARB_CACHE_SPLIT_MODE }
 11848b28:		0000: 000020c0 00008000
-t0		write GRAS_SC_CONTROL (2072)
+		write GRAS_SC_CONTROL (2072)
 			GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = MSAA_ONE | RASTER_MODE = 0 }
 11848b30:		0000: 00002072 00000000
-t0		write RB_DEPTH_INFO (2102)
+		write RB_DEPTH_INFO (2102)
 			RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTHX_16 | DEPTH_BASE = 0x40000 }
 			RB_DEPTH_PITCH: 320
 11848b38:		0000: 00012102 00020000 00000028
-t0		write RB_FRAME_BUFFER_DIMENSION (0ce0)
+		write RB_FRAME_BUFFER_DIMENSION (0ce0)
 NEEDS WFI: RB_FRAME_BUFFER_DIMENSION (ce0)
 			RB_FRAME_BUFFER_DIMENSION: { WIDTH = 300 | HEIGHT = 300 }
 11848b44:		0000: 00000ce0 004b012c
-t0		write RB_MODE_CONTROL (20c0)
+		write RB_MODE_CONTROL (20c0)
 			RB_MODE_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MRT = 0 | MARB_CACHE_SPLIT_MODE }
 11848b4c:		0000: 000020c0 00008000
-t3		opcode: (null) (4c) (4 dwords)
+		opcode: (null) (4c) (4 dwords)
 11848b54:		0000: c0024c00 00000000 000000a0 012b012b
-t0		write RB_MRT[0].BUF_INFO (20c5)
+		write RB_MRT[0].BUF_INFO (20c5)
 			RB_MRT[0].BUF_INFO: { COLOR_FORMAT = RB_R8G8B8A8_UNORM | COLOR_TILE_MODE = TILE_32X32 | COLOR_SWAP = WXYZ | COLOR_BUF_PITCH = 640 }
 			RB_MRT[0].BUF_BASE: { COLOR_BUF_BASE = 0 }
 11848b64:		0000: 000120c5 00280488 00000000
-t0		write SP_FS_IMAGE_OUTPUT[0].REG (22f4)
+		write SP_FS_IMAGE_OUTPUT[0].REG (22f4)
 			SP_FS_IMAGE_OUTPUT[0].REG: { MRTFORMAT = RB_R8G8B8A8_UNORM }
 11848b70:		0000: 000022f4 00000008
-t0		write RB_MRT[0x1].BUF_INFO (20c9)
+		write RB_MRT[0x1].BUF_INFO (20c9)
 			RB_MRT[0x1].BUF_INFO: { COLOR_FORMAT = RB_R5G6B5_UNORM | COLOR_TILE_MODE = TILE_32X32 | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 0 }
 			RB_MRT[0x1].BUF_BASE: { COLOR_BUF_BASE = 0 }
 11848b78:		0000: 000120c9 00000080 00000000
-t0		write SP_FS_IMAGE_OUTPUT[0x1].REG (22f5)
+		write SP_FS_IMAGE_OUTPUT[0x1].REG (22f5)
 			SP_FS_IMAGE_OUTPUT[0x1].REG: { MRTFORMAT = RB_R5G6B5_UNORM }
 11848b84:		0000: 000022f5 00000000
-t0		write RB_MRT[0x2].BUF_INFO (20cd)
+		write RB_MRT[0x2].BUF_INFO (20cd)
 			RB_MRT[0x2].BUF_INFO: { COLOR_FORMAT = RB_R5G6B5_UNORM | COLOR_TILE_MODE = TILE_32X32 | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 0 }
 			RB_MRT[0x2].BUF_BASE: { COLOR_BUF_BASE = 0 }
 11848b8c:		0000: 000120cd 00000080 00000000
-t0		write SP_FS_IMAGE_OUTPUT[0x2].REG (22f6)
+		write SP_FS_IMAGE_OUTPUT[0x2].REG (22f6)
 			SP_FS_IMAGE_OUTPUT[0x2].REG: { MRTFORMAT = RB_R5G6B5_UNORM }
 11848b98:		0000: 000022f6 00000000
-t0		write RB_MRT[0x3].BUF_INFO (20d1)
+		write RB_MRT[0x3].BUF_INFO (20d1)
 			RB_MRT[0x3].BUF_INFO: { COLOR_FORMAT = RB_R5G6B5_UNORM | COLOR_TILE_MODE = TILE_32X32 | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 0 }
 			RB_MRT[0x3].BUF_BASE: { COLOR_BUF_BASE = 0 }
 11848ba0:		0000: 000120d1 00000080 00000000
-t0		write SP_FS_IMAGE_OUTPUT[0x3].REG (22f7)
+		write SP_FS_IMAGE_OUTPUT[0x3].REG (22f7)
 			SP_FS_IMAGE_OUTPUT[0x3].REG: { MRTFORMAT = RB_R5G6B5_UNORM }
 11848bac:		0000: 000022f7 00000000
-t3		opcode: CP_REG_RMW (21) (4 dwords)
+		opcode: CP_REG_RMW (21) (4 dwords)
 			{ DST_REG = 0x20c1 | ROTATE = 0 }
 			{ SRC0 = 4294955023 }
 			{ SRC1 = 8272 }
 		rmw (RB_RENDER_CONTROL & 0xffffd00f) | 0x00002050)
 NEEDS WFI: rmw (RB_RENDER_CONTROL & 0xffffd00f) | 0x00002050)
 11848bb4:		0000: c0022100 000020c1 ffffd00f 00002050
-t0		write RB_WINDOW_OFFSET (210e)
+		write RB_WINDOW_OFFSET (210e)
 			RB_WINDOW_OFFSET: { X = 160 | Y = 0 }
 11848bc4:		0000: 0000210e 000000a0
-t0		write GRAS_SC_SCREEN_SCISSOR_TL (2074)
+		write GRAS_SC_SCREEN_SCISSOR_TL (2074)
 			GRAS_SC_SCREEN_SCISSOR_TL: { X = 160 | Y = 0 }
 			GRAS_SC_SCREEN_SCISSOR_BR: { X = 299 | Y = 299 }
 11848bcc:		0000: 00012074 000000a0 012b012b
-t0		write CP_SCRATCH_REG6 (057e)
+		write CP_SCRATCH_REG6 (057e)
 NEEDS WFI: CP_SCRATCH_REG6 (57e)
 			CP_SCRATCH_REG6: 12820
 			:0,12811,12820,12819
 11848bd8:		0000: 0000057e 00003214
-t3		opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
+		opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
 		ibaddr:11842370
 		ibsize:000018ba
 11848be0:		0000: c0013700 11842370 000018ba
-t0		write CP_SCRATCH_REG6 (057e)
+		write CP_SCRATCH_REG6 (057e)
 NEEDS WFI: CP_SCRATCH_REG6 (57e)
 			CP_SCRATCH_REG6: 12821
 			:0,12811,12821,12819
 11848bec:		0000: 0000057e 00003215
-t0		write RB_DEPTH_CONTROL (2100)
+		write RB_DEPTH_CONTROL (2100)
 			RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER }
 11848bf4:		0000: 00002100 00000000
-t0		write RB_STENCIL_CONTROL (2104)
+		write RB_STENCIL_CONTROL (2104)
 			RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP }
 11848bfc:		0000: 00002104 00000000
-t0		write RB_STENCILREFMASK (2108)
+		write RB_STENCILREFMASK (2108)
 			RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0xff | 0xff000000 }
 			RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0xff | 0xff000000 }
 11848c04:		0000: 00012108 ffff0000 ffff0000
-t0		write GRAS_SU_MODE_CONTROL (2070)
+		write GRAS_SU_MODE_CONTROL (2070)
 			GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 }
 11848c10:		0000: 00002070 00000000
-t0		write GRAS_CL_CLIP_CNTL (2040)
+		write GRAS_CL_CLIP_CNTL (2040)
 			GRAS_CL_CLIP_CNTL: { NUM_USER_CLIP_PLANES = 0 }
 11848c18:		0000: 00002040 00000000
-t0		write GRAS_CL_VPORT_XOFFSET (2048)
+		write GRAS_CL_VPORT_XOFFSET (2048)
 			GRAS_CL_VPORT_XOFFSET: 149.500000
 			GRAS_CL_VPORT_XSCALE: 150.000000
 			GRAS_CL_VPORT_YOFFSET: 149.500000
@@ -14806,33 +14806,33 @@ t0		write GRAS_CL_VPORT_XOFFSET (2048)
 			GRAS_CL_VPORT_ZOFFSET: 0.000000
 			GRAS_CL_VPORT_ZSCALE: 1.000000
 11848c20:		0000: 00052048 43158000 43160000 43158000 c3160000 00000000 3f800000
-t0		write RB_MODE_CONTROL (20c0)
+		write RB_MODE_CONTROL (20c0)
 			RB_MODE_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MRT = 0 | MARB_CACHE_SPLIT_MODE }
 11848c3c:		0000: 000020c0 00008200
-t3		opcode: CP_REG_RMW (21) (4 dwords)
+		opcode: CP_REG_RMW (21) (4 dwords)
 			{ DST_REG = 0x20c1 | ROTATE = 0 }
 			{ SRC0 = 12272 }
 			{ SRC1 = 4096 }
 		rmw (RB_RENDER_CONTROL & 0x00002ff0) | 0x00001000)
 NEEDS WFI: rmw (RB_RENDER_CONTROL & 0x00002ff0) | 0x00001000)
 11848c44:		0000: c0022100 000020c1 00002ff0 00001000
-t0		write GRAS_SC_CONTROL (2072)
+		write GRAS_SC_CONTROL (2072)
 			GRAS_SC_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MSAA_SAMPLES = MSAA_ONE | RASTER_MODE = 0x1 }
 11848c54:		0000: 00002072 00001020
-t0		write PC_PRIM_VTX_CNTL (21ec)
+		write PC_PRIM_VTX_CNTL (21ec)
 			PC_PRIM_VTX_CNTL: { STRIDE_IN_VPC = 0 | POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES | PROVOKING_VTX_LAST }
 11848c5c:		0000: 000021ec 02000240
-t0		write GRAS_SC_WINDOW_SCISSOR_TL (2079)
+		write GRAS_SC_WINDOW_SCISSOR_TL (2079)
 			GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
 			GRAS_SC_WINDOW_SCISSOR_BR: { X = 299 | Y = 299 }
 11848c64:		0000: 00012079 00000000 012b012b
-t0		write VFD_INDEX_MIN (2242)
+		write VFD_INDEX_MIN (2242)
 			VFD_INDEX_MIN: 0
 			VFD_INDEX_MAX: 2
 			VFD_INSTANCEID_OFFSET: 0
 			VFD_INDEX_OFFSET: 0
 11848c70:		0000: 00032242 00000000 00000002 00000000 00000000
-t0		write HLSQ_CONTROL_0_REG (2200)
+		write HLSQ_CONTROL_0_REG (2200)
 			HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | SPSHADERRESTART | CYCLETIMEOUTLIMITVPC = 0 | CONSTMODE = 0 | SPCONSTFULLUPDATE }
 			HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | FRAGCOORDXYREGID = r0.x | FRAGCOORDZWREGID = r0.x }
 			HLSQ_CONTROL_2_REG: { FACENESSREGID = r0.x | COVVALUEREGID = r0.x | PRIMALLOCTHRESHOLD = 31 }
@@ -14840,95 +14840,95 @@ t0		write HLSQ_CONTROL_0_REG (2200)
 			HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTSTARTOFFSET = 0 | INSTRLENGTH = 1 }
 			HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 1 | CONSTSTARTOFFSET = 128 | INSTRLENGTH = 1 }
 11848c84:		0000: 00052200 20000210 00000100 7c000000 00000000 01000000 01080001
-t0		write SP_SP_CTRL_REG (22c0)
+		write SP_SP_CTRL_REG (22c0)
 			SP_SP_CTRL_REG: { CONSTMODE = 0 | SLEEPMODE = 1 | L0MODE = 1 }
 11848ca0:		0000: 000022c0 00500000
-t0		write SP_VS_LENGTH_REG (22df)
+		write SP_VS_LENGTH_REG (22df)
 			SP_VS_LENGTH_REG: { SHADERLENGTH = 1 }
 11848ca8:		0000: 000022df 00000001
-t0		write SP_VS_CTRL_REG0 (22c4)
+		write SP_VS_CTRL_REG0 (22c4)
 			SP_VS_CTRL_REG0: { THREADMODE = MULTI | INSTRBUFFERMODE = BUFFER | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE | LENGTH = 1 }
 			SP_VS_CTRL_REG1: { CONSTLENGTH = 0 | CONSTFOOTPRINT = 0 | INITIALOUTSTANDING = 4 }
 			SP_VS_PARAM_REG: { POSREGID = r0.x | PSIZEREGID = r63.x | TOTALVSOUTVAR = 0 }
 11848cb0:		0000: 000222c4 01200402 04000000 0000fc00
-t0		write SP_FS_LENGTH_REG (22ff)
+		write SP_FS_LENGTH_REG (22ff)
 			SP_FS_LENGTH_REG: { SHADERLENGTH = 1 }
 11848cc0:		0000: 000022ff 00000001
-t0		write SP_FS_CTRL_REG0 (22e0)
+		write SP_FS_CTRL_REG0 (22e0)
 			SP_FS_CTRL_REG0: { THREADMODE = MULTI | INSTRBUFFERMODE = BUFFER | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 0 | INOUTREGOVERLAP | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE | LENGTH = 1 }
 			SP_FS_CTRL_REG1: { CONSTLENGTH = 1 | CONSTFOOTPRINT = 0 | INITIALOUTSTANDING = 0 | HALFPRECVAROFFSET = 63 }
 11848cc8:		0000: 000122e0 01340012 3f000001
-t0		write SP_FS_FLAT_SHAD_MODE_REG_0 (22e8)
+		write SP_FS_FLAT_SHAD_MODE_REG_0 (22e8)
 			SP_FS_FLAT_SHAD_MODE_REG_0: 0
 			SP_FS_FLAT_SHAD_MODE_REG_1: 0
 11848cd4:		0000: 000122e8 00000000 00000000
-t0		write SP_FS_OUTPUT_REG (22ec)
+		write SP_FS_OUTPUT_REG (22ec)
 			SP_FS_OUTPUT_REG: { MRT = 0 | DEPTH_REGID = r0.x }
 11848ce0:		0000: 000022ec 00000000
-t0		write SP_FS_MRT[0].REG (22f0)
+		write SP_FS_MRT[0].REG (22f0)
 			SP_FS_MRT[0].REG: { REGID = r0.x | HALF_PRECISION }
 			SP_FS_MRT[0x1].REG: { REGID = r0.x }
 			SP_FS_MRT[0x2].REG: { REGID = r0.x }
 			SP_FS_MRT[0x3].REG: { REGID = r0.x }
 11848ce8:		0000: 000322f0 00000100 00000000 00000000 00000000
-t0		write VPC_ATTR (2280)
+		write VPC_ATTR (2280)
 			VPC_ATTR: { TOTALATTR = 0 | THRDASSIGN = 1 | LMSIZE = 1 }
 			VPC_PACK: { NUMFPNONPOSVAR = 0 | NUMNONPOSVSVAR = 0 }
 11848cfc:		0000: 00012280 10001000 00000000
-t0		write VPC_VARYING_INTERP[0].MODE (2282)
+		write VPC_VARYING_INTERP[0].MODE (2282)
 			VPC_VARYING_INTERP[0].MODE: { C0 = SMOOTH | C1 = SMOOTH | C2 = SMOOTH | C3 = SMOOTH | C4 = SMOOTH | C5 = SMOOTH | C6 = SMOOTH | C7 = SMOOTH | C8 = SMOOTH | C9 = SMOOTH | CA = SMOOTH | CB = SMOOTH | CC = SMOOTH | CD = SMOOTH | CE = SMOOTH | CF = SMOOTH }
 			VPC_VARYING_INTERP[0x1].MODE: { C0 = SMOOTH | C1 = SMOOTH | C2 = SMOOTH | C3 = SMOOTH | C4 = SMOOTH | C5 = SMOOTH | C6 = SMOOTH | C7 = SMOOTH | C8 = SMOOTH | C9 = SMOOTH | CA = SMOOTH | CB = SMOOTH | CC = SMOOTH | CD = SMOOTH | CE = SMOOTH | CF = SMOOTH }
 			VPC_VARYING_INTERP[0x2].MODE: { C0 = SMOOTH | C1 = SMOOTH | C2 = SMOOTH | C3 = SMOOTH | C4 = SMOOTH | C5 = SMOOTH | C6 = SMOOTH | C7 = SMOOTH | C8 = SMOOTH | C9 = SMOOTH | CA = SMOOTH | CB = SMOOTH | CC = SMOOTH | CD = SMOOTH | CE = SMOOTH | CF = SMOOTH }
 			VPC_VARYING_INTERP[0x3].MODE: { C0 = SMOOTH | C1 = SMOOTH | C2 = SMOOTH | C3 = SMOOTH | C4 = SMOOTH | C5 = SMOOTH | C6 = SMOOTH | C7 = SMOOTH | C8 = SMOOTH | C9 = SMOOTH | CA = SMOOTH | CB = SMOOTH | CC = SMOOTH | CD = SMOOTH | CE = SMOOTH | CF = SMOOTH }
 11848d08:		0000: 00032282 00000000 00000000 00000000 00000000
-t0		write VPC_VARYING_PS_REPL[0].MODE (2286)
+		write VPC_VARYING_PS_REPL[0].MODE (2286)
 			VPC_VARYING_PS_REPL[0].MODE: { C0 = 0 | C1 = 0 | C2 = 0 | C3 = 0 | C4 = 0 | C5 = 0 | C6 = 0 | C7 = 0 | C8 = 0 | C9 = 0 | CA = 0 | CB = 0 | CC = 0 | CD = 0 | CE = 0 | CF = 0 }
 			VPC_VARYING_PS_REPL[0x1].MODE: { C0 = 0 | C1 = 0 | C2 = 0 | C3 = 0 | C4 = 0 | C5 = 0 | C6 = 0 | C7 = 0 | C8 = 0 | C9 = 0 | CA = 0 | CB = 0 | CC = 0 | CD = 0 | CE = 0 | CF = 0 }
 			VPC_VARYING_PS_REPL[0x2].MODE: { C0 = 0 | C1 = 0 | C2 = 0 | C3 = 0 | C4 = 0 | C5 = 0 | C6 = 0 | C7 = 0 | C8 = 0 | C9 = 0 | CA = 0 | CB = 0 | CC = 0 | CD = 0 | CE = 0 | CF = 0 }
 			VPC_VARYING_PS_REPL[0x3].MODE: { C0 = 0 | C1 = 0 | C2 = 0 | C3 = 0 | C4 = 0 | C5 = 0 | C6 = 0 | C7 = 0 | C8 = 0 | C9 = 0 | CA = 0 | CB = 0 | CC = 0 | CD = 0 | CE = 0 | CF = 0 }
 11848d1c:		0000: 00032286 00000000 00000000 00000000 00000000
-t0		write VFD_VS_THREADING_THRESHOLD (227e)
+		write VFD_VS_THREADING_THRESHOLD (227e)
 			VFD_VS_THREADING_THRESHOLD: { REGID_THRESHOLD = 15 | REGID_VTXCNT = r63.x }
 11848d30:		0000: 0000227e 0000fc0f
-t3		opcode: CP_LOAD_STATE (30) (3 dwords)
+		opcode: CP_LOAD_STATE (30) (3 dwords)
 			{ DST_OFF = 0 | STATE_SRC = SS_INDIRECT | STATE_BLOCK = SB_VERT_SHADER | NUM_UNIT = 1 }
 			{ STATE_TYPE = ST_SHADER | EXT_SRC_ADDR = 0x117e2000 }
 11848d38:		0000: c0013000 00640000 117e2000
-t0		write VFD_PERFCOUNTER0_SELECT (0e44)
+		write VFD_PERFCOUNTER0_SELECT (0e44)
 NEEDS WFI: VFD_PERFCOUNTER0_SELECT (e44)
 			VFD_PERFCOUNTER0_SELECT: VFD_PERF_UCHE_BYTE_FETCHED
 11848d44:		0000: 00000e44 00000000
-t3		opcode: CP_LOAD_STATE (30) (3 dwords)
+		opcode: CP_LOAD_STATE (30) (3 dwords)
 			{ DST_OFF = 0 | STATE_SRC = SS_INDIRECT | STATE_BLOCK = SB_FRAG_SHADER | NUM_UNIT = 1 }
 			{ STATE_TYPE = ST_SHADER | EXT_SRC_ADDR = 0x117e1000 }
 11848d4c:		0000: c0013000 00740000 117e1000
-t0		write VFD_PERFCOUNTER0_SELECT (0e44)
+		write VFD_PERFCOUNTER0_SELECT (0e44)
 NEEDS WFI: VFD_PERFCOUNTER0_SELECT (e44)
 			VFD_PERFCOUNTER0_SELECT: VFD_PERF_UCHE_BYTE_FETCHED
 11848d58:		0000: 00000e44 00000000
-t0		write VFD_CONTROL_0 (2240)
+		write VFD_CONTROL_0 (2240)
 			VFD_CONTROL_0: { TOTALATTRTOVS = 4 | PACKETSIZE = 2 | STRMDECINSTRCNT = 1 | STRMFETCHINSTRCNT = 1 }
 			VFD_CONTROL_1: { MAXSTORAGE = 1 | MAXTHRESHOLD = 0 | MINTHRESHOLD = 0 | REGID4VTX = r63.x | REGID4INST = r63.x }
 11848d60:		0000: 00012240 08480004 fcfc0001
-t0		write VFD_FETCH[0].INSTR_0 (2246)
+		write VFD_FETCH[0].INSTR_0 (2246)
 			VFD_FETCH[0].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 12 | INDEXCODE = 0 | STEPRATE = 1 }
 			VFD_FETCH[0].INSTR_1: 0x127e9000
 11848d6c:		0000: 00012246 0100060b 127e9000
-t0		write VFD_DECODE[0].INSTR (2266)
+		write VFD_DECODE[0].INSTR (2266)
 			VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID }
 11848d78:		0000: 00002266 2c00009f
-t0		write RB_COPY_CONTROL (20ec)
+		write RB_COPY_CONTROL (20ec)
 			RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_ONE | MODE = RB_COPY_DEPTH_STENCIL | FASTCLEAR = 0 | GMEM_BASE = 0x40000 }
 			RB_COPY_DEST_BASE: { BASE = 0x12839000 }
 			RB_COPY_DEST_PITCH: { PITCH = 640 }
 			RB_COPY_DEST_INFO: { TILE = LINEAR | FORMAT = RB_R8G8_UNORM | SWAP = WZYX | DITHER_MODE = DITHER_DISABLE | COMPONENT_ENABLE = 0xf | ENDIAN = ENDIAN_NONE }
 11848d80:		0000: 000320ec 00040050 0941c800 00000014 0003c030
-t0		write CP_SCRATCH_REG7 (057f)
+		write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 			CP_SCRATCH_REG7: 12822
 			:0,12811,12821,12822
 11848d94:		0000: 0000057f 00003216
-t3		opcode: CP_DRAW_INDX (22) (4 dwords)
+		opcode: CP_DRAW_INDX (22) (4 dwords)
 			{ VIZ_QUERY = 0 }
 			{ PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 			{ NUM_INDICES = 2 }
@@ -15024,23 +15024,23 @@ t3		opcode: CP_DRAW_INDX (22) (4 dwords)
  +	00000000		SP_FS_IMAGE_OUTPUT[0x3].REG: { MRTFORMAT = RB_R5G6B5_UNORM }
  +	00000001		SP_FS_LENGTH_REG: { SHADERLENGTH = 1 }
 11848d9c:		0000: c0022200 00000000 00004088 00000002
-t0		write CP_SCRATCH_REG7 (057f)
+		write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 			CP_SCRATCH_REG7: 12823
 			:0,12811,12821,12823
 11848dac:		0000: 0000057f 00003217
-t0		write RB_COPY_CONTROL (20ec)
+		write RB_COPY_CONTROL (20ec)
 			RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_ONE | MODE = RB_COPY_RESOLVE | FASTCLEAR = 0 | GMEM_BASE = 0 }
 			RB_COPY_DEST_BASE: { BASE = 0x12869000 }
 			RB_COPY_DEST_PITCH: { PITCH = 1280 }
 			RB_COPY_DEST_INFO: { TILE = LINEAR | FORMAT = RB_R8G8B8A8_UNORM | SWAP = WXYZ | DITHER_MODE = DITHER_DISABLE | COMPONENT_ENABLE = 0xf | ENDIAN = ENDIAN_NONE }
 11848db4:		0000: 000320ec 00000010 09434800 00000028 0003c120
-t0		write CP_SCRATCH_REG7 (057f)
+		write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 			CP_SCRATCH_REG7: 12824
 			:0,12811,12821,12824
 11848dc8:		0000: 0000057f 00003218
-t3		opcode: CP_DRAW_INDX (22) (4 dwords)
+		opcode: CP_DRAW_INDX (22) (4 dwords)
 			{ VIZ_QUERY = 0 }
 			{ PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 }
 			{ NUM_INDICES = 2 }
@@ -15056,15 +15056,15 @@ t3		opcode: CP_DRAW_INDX (22) (4 dwords)
 !+	00000028		RB_COPY_DEST_PITCH: { PITCH = 1280 }
 !+	0003c120		RB_COPY_DEST_INFO: { TILE = LINEAR | FORMAT = RB_R8G8B8A8_UNORM | SWAP = WXYZ | DITHER_MODE = DITHER_DISABLE | COMPONENT_ENABLE = 0xf | ENDIAN = ENDIAN_NONE }
 11848dd0:		0000: c0022200 00000000 00004088 00000002
-t0		write CP_SCRATCH_REG7 (057f)
+		write CP_SCRATCH_REG7 (057f)
 NEEDS WFI: CP_SCRATCH_REG7 (57f)
 			CP_SCRATCH_REG7: 12825
 			:0,12811,12821,12825
 11848de0:		0000: 0000057f 00003219
-t0		write RB_MODE_CONTROL (20c0)
+		write RB_MODE_CONTROL (20c0)
 			RB_MODE_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MRT = 0 | MARB_CACHE_SPLIT_MODE }
 11848de8:		0000: 000020c0 00008000
-t0		write GRAS_SC_CONTROL (2072)
+		write GRAS_SC_CONTROL (2072)
 			GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = MSAA_ONE | RASTER_MODE = 0 }
 11848df0:		0000: 00002072 00000000
 ############################################################
diff --git a/src/freedreno/.gitlab-ci/reference/fd-clouds.log b/src/freedreno/.gitlab-ci/reference/fd-clouds.log
index 8121d238cb6..3f18ad0289b 100644
--- a/src/freedreno/.gitlab-ci/reference/fd-clouds.log
+++ b/src/freedreno/.gitlab-ci/reference/fd-clouds.log
@@ -1,253 +1,253 @@
 gpu_id: 630
 cmd: null_platform_t/2995: fence=1855
 ############################################################
-cmdstream: 1023 dwords
-t7		opcode: CP_EVENT_WRITE (46) (2 dwords)
+cmdstream[0]: 1023 dwords
+		opcode: CP_EVENT_WRITE (46) (2 dwords)
 			{ EVENT = CACHE_INVALIDATE }
 		event CACHE_INVALIDATE
 0000000001d91000:		0000: 70460001 00000031
-t4		write HLSQ_INVALIDATE_CMD (bb08)
+		write HLSQ_INVALIDATE_CMD (bb08)
 			HLSQ_INVALIDATE_CMD: { VS_STATE | HS_STATE | DS_STATE | GS_STATE | FS_STATE | CS_STATE | CS_IBO | GFX_IBO | CS_SHARED_CONST | GFX_SHARED_CONST | CS_BINDLESS = 0x1f | GFX_BINDLESS = 0x1f }
 0000000001d91008:		0000: 40bb0801 000fffff
-t7		opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
+		opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
 0000000001d91010:		0000: 70268000
-t4		write RB_DBG_ECO_CNTL (8e04)
+		write RB_DBG_ECO_CNTL (8e04)
 			RB_DBG_ECO_CNTL: 0
 0000000001d91014:		0000: 408e0401 00000000
-t4		write SP_FLOAT_CNTL (ae04)
+		write SP_FLOAT_CNTL (ae04)
 			SP_FLOAT_CNTL: { F16_NO_INF }
 0000000001d9101c:		0000: 48ae0401 00000008
-t4		write SP_DBG_ECO_CNTL (ae00)
+		write SP_DBG_ECO_CNTL (ae00)
 			SP_DBG_ECO_CNTL: 0
 0000000001d91024:		0000: 40ae0001 00000000
-t4		write SP_PERFCTR_ENABLE (ae0f)
+		write SP_PERFCTR_ENABLE (ae0f)
 			SP_PERFCTR_ENABLE: { VS | HS | DS | GS | FS | CS }
 0000000001d9102c:		0000: 40ae0f01 0000003f
-t4		write TPL1_UNKNOWN_B605 (b605)
+		write TPL1_UNKNOWN_B605 (b605)
 			TPL1_UNKNOWN_B605: 68
 0000000001d91034:		0000: 40b60501 00000044
-t4		write TPL1_DBG_ECO_CNTL (b600)
+		write TPL1_DBG_ECO_CNTL (b600)
 			TPL1_DBG_ECO_CNTL: 0x100000
 0000000001d9103c:		0000: 40b60001 00100000
-t4		write HLSQ_UNKNOWN_BE00 (be00)
+		write HLSQ_UNKNOWN_BE00 (be00)
 			HLSQ_UNKNOWN_BE00: 0x80
 0000000001d91044:		0000: 48be0001 00000080
-t4		write HLSQ_UNKNOWN_BE01 (be01)
+		write HLSQ_UNKNOWN_BE01 (be01)
 			HLSQ_UNKNOWN_BE01: 0
 0000000001d9104c:		0000: 40be0101 00000000
-t4		write VPC_DBG_ECO_CNTL (9600)
+		write VPC_DBG_ECO_CNTL (9600)
 			VPC_DBG_ECO_CNTL: 0
 0000000001d91054:		0000: 48960001 00000000
-t4		write GRAS_DBG_ECO_CNTL (8600)
+		write GRAS_DBG_ECO_CNTL (8600)
 			GRAS_DBG_ECO_CNTL: { UNK7 | LRZCACHELOCKDIS }
 0000000001d9105c:		0000: 40860001 00000880
-t4		write HLSQ_DBG_ECO_CNTL (be04)
+		write HLSQ_DBG_ECO_CNTL (be04)
 			HLSQ_DBG_ECO_CNTL: 0x80000
 0000000001d91064:		0000: 40be0401 00080000
-t4		write SP_CHICKEN_BITS (ae03)
+		write SP_CHICKEN_BITS (ae03)
 			SP_CHICKEN_BITS: 0x1430
 0000000001d9106c:		0000: 40ae0301 00001430
-t4		write SP_IBO_COUNT (ab20)
+		write SP_IBO_COUNT (ab20)
 			SP_IBO_COUNT: 0
 0000000001d91074:		0000: 48ab2001 00000000
-t4		write SP_UNKNOWN_B182 (b182)
+		write SP_UNKNOWN_B182 (b182)
 			SP_UNKNOWN_B182: 0
 0000000001d9107c:		0000: 48b18201 00000000
-t4		write HLSQ_SHARED_CONSTS (bb11)
+		write HLSQ_SHARED_CONSTS (bb11)
 			HLSQ_SHARED_CONSTS: { 0 }
 0000000001d91084:		0000: 48bb1101 00000000
-t4		write UCHE_UNKNOWN_0E12 (0e12)
+		write UCHE_UNKNOWN_0E12 (0e12)
 			UCHE_UNKNOWN_0E12: 0x3200000
 0000000001d9108c:		0000: 400e1201 03200000
-t4		write UCHE_CLIENT_PF (0e19)
+		write UCHE_CLIENT_PF (0e19)
 			UCHE_CLIENT_PF: { PERFSEL = 0x4 }
 0000000001d91094:		0000: 480e1901 00000004
-t4		write RB_UNKNOWN_8E01 (8e01)
+		write RB_UNKNOWN_8E01 (8e01)
 			RB_UNKNOWN_8E01: 0x1
 0000000001d9109c:		0000: 408e0101 00000001
-t4		write SP_MODE_CONTROL (ab00)
+		write SP_MODE_CONTROL (ab00)
 			SP_MODE_CONTROL: { CONSTANT_DEMOTION_ENABLE | ISAMMODE = ISAMMODE_GL }
 0000000001d910a4:		0000: 40ab0001 00000005
-t4		write VFD_ADD_OFFSET (a009)
+		write VFD_ADD_OFFSET (a009)
 			VFD_ADD_OFFSET: { VERTEX }
 0000000001d910ac:		0000: 48a00901 00000001
-t4		write RB_UNKNOWN_8811 (8811)
+		write RB_UNKNOWN_8811 (8811)
 			RB_UNKNOWN_8811: 0x1
 0000000001d910b4:		0000: 48881101 00000010
-t4		write PC_MODE_CNTL (9804)
+		write PC_MODE_CNTL (9804)
 			PC_MODE_CNTL: 0x1f
 0000000001d910bc:		0000: 48980401 0000001f
-t4		write RB_SRGB_CNTL (880f)
+		write RB_SRGB_CNTL (880f)
 			RB_SRGB_CNTL: { 0 }
 0000000001d910c4:		0000: 48880f01 00000000
-t4		write GRAS_LRZ_PS_INPUT_CNTL (8101)
+		write GRAS_LRZ_PS_INPUT_CNTL (8101)
 			GRAS_LRZ_PS_INPUT_CNTL: { FRAGCOORDSAMPLEMODE = FRAGCOORD_CENTER }
 0000000001d910cc:		0000: 40810101 00000000
-t4		write GRAS_SAMPLE_CNTL (8109)
+		write GRAS_SAMPLE_CNTL (8109)
 			GRAS_SAMPLE_CNTL: { 0 }
 0000000001d910d4:		0000: 48810901 00000000
-t4		write GRAS_UNKNOWN_8110 (8110)
+		write GRAS_UNKNOWN_8110 (8110)
 			GRAS_UNKNOWN_8110: 0x2
 0000000001d910dc:		0000: 40811001 00000002
-t4		write RB_UNKNOWN_8818 (8818)
+		write RB_UNKNOWN_8818 (8818)
 			RB_UNKNOWN_8818: 0
 0000000001d910e4:		0000: 48881801 00000000
-t4		write RB_UNKNOWN_8819 (8819)
+		write RB_UNKNOWN_8819 (8819)
 			RB_UNKNOWN_8819: 0
 0000000001d910ec:		0000: 40881901 00000000
-t4		write RB_UNKNOWN_881A (881a)
+		write RB_UNKNOWN_881A (881a)
 			RB_UNKNOWN_881A: 0
 0000000001d910f4:		0000: 40881a01 00000000
-t4		write RB_UNKNOWN_881B (881b)
+		write RB_UNKNOWN_881B (881b)
 			RB_UNKNOWN_881B: 0
 0000000001d910fc:		0000: 48881b01 00000000
-t4		write RB_UNKNOWN_881C (881c)
+		write RB_UNKNOWN_881C (881c)
 			RB_UNKNOWN_881C: 0
 0000000001d91104:		0000: 40881c01 00000000
-t4		write RB_UNKNOWN_881D (881d)
+		write RB_UNKNOWN_881D (881d)
 			RB_UNKNOWN_881D: 0
 0000000001d9110c:		0000: 48881d01 00000000
-t4		write RB_UNKNOWN_881E (881e)
+		write RB_UNKNOWN_881E (881e)
 			RB_UNKNOWN_881E: 0
 0000000001d91114:		0000: 48881e01 00000000
-t4		write RB_UNKNOWN_88F0 (88f0)
+		write RB_UNKNOWN_88F0 (88f0)
 			RB_UNKNOWN_88F0: 0
 0000000001d9111c:		0000: 4888f001 00000000
-t4		write VPC_POINT_COORD_INVERT (9236)
+		write VPC_POINT_COORD_INVERT (9236)
 			VPC_POINT_COORD_INVERT: { 0 }
 0000000001d91124:		0000: 40923601 00000000
-t4		write VPC_UNKNOWN_9300 (9300)
+		write VPC_UNKNOWN_9300 (9300)
 			VPC_UNKNOWN_9300: 0
 0000000001d9112c:		0000: 48930001 00000000
-t4		write VPC_SO_DISABLE (9306)
+		write VPC_SO_DISABLE (9306)
 			VPC_SO_DISABLE: { DISABLE }
 0000000001d91134:		0000: 48930601 00000001
-t4		write PC_PRIMID_PASSTHRU (9806)
+		write PC_PRIMID_PASSTHRU (9806)
 			PC_PRIMID_PASSTHRU: FALSE
 0000000001d9113c:		0000: 40980601 00000000
-t4		write 0x9990 (9990)
+		write 0x9990 (9990)
 			0x9990: 00000000
 0000000001d91144:		0000: 48999001 00000000
-t4		write PC_RASTER_CNTL (9980)
+		write PC_RASTER_CNTL (9980)
 			PC_RASTER_CNTL: { STREAM = 0 }
 0000000001d9114c:		0000: 40998001 00000000
-t4		write PC_MULTIVIEW_CNTL (9b07)
+		write PC_MULTIVIEW_CNTL (9b07)
 			PC_MULTIVIEW_CNTL: { VIEWS = 0 }
 0000000001d91154:		0000: 489b0701 00000000
-t4		write SP_VS_OBJ_FIRST_EXEC_OFFSET (a81b)
+		write SP_VS_OBJ_FIRST_EXEC_OFFSET (a81b)
 			SP_VS_OBJ_FIRST_EXEC_OFFSET: 0
 0000000001d9115c:		0000: 40a81b01 00000000
-t4		write SP_UNKNOWN_B183 (b183)
+		write SP_UNKNOWN_B183 (b183)
 			SP_UNKNOWN_B183: 0
 0000000001d91164:		0000: 40b18301 00000000
-t4		write GRAS_SU_CONSERVATIVE_RAS_CNTL (8099)
+		write GRAS_SU_CONSERVATIVE_RAS_CNTL (8099)
 			GRAS_SU_CONSERVATIVE_RAS_CNTL: { SHIFTAMOUNT = 0 }
 0000000001d9116c:		0000: 40809901 00000000
-t4		write GRAS_VS_LAYER_CNTL (809b)
+		write GRAS_VS_LAYER_CNTL (809b)
 			GRAS_VS_LAYER_CNTL: { 0 }
 0000000001d91174:		0000: 48809b01 00000000
-t4		write GRAS_SC_CNTL (80a0)
+		write GRAS_SC_CNTL (80a0)
 			GRAS_SC_CNTL: { CCUSINGLECACHELINESIZE = 0x2 | SINGLE_PRIM_MODE = NO_FLUSH | RASTER_MODE = TYPE_TILED | RASTER_DIRECTION = LR_TB | SEQUENCED_THREAD_DISTRIBUTION = DIST_SCREEN_COORD }
 0000000001d9117c:		0000: 4080a001 00000002
-t4		write GRAS_UNKNOWN_80AF (80af)
+		write GRAS_UNKNOWN_80AF (80af)
 			GRAS_UNKNOWN_80AF: FALSE
 0000000001d91184:		0000: 4080af01 00000000
-t4		write VPC_UNKNOWN_9210 (9210)
+		write VPC_UNKNOWN_9210 (9210)
 			VPC_UNKNOWN_9210: 0
 0000000001d9118c:		0000: 48921001 00000000
-t4		write VPC_UNKNOWN_9211 (9211)
+		write VPC_UNKNOWN_9211 (9211)
 			VPC_UNKNOWN_9211: 0
 0000000001d91194:		0000: 40921101 00000000
-t4		write VPC_UNKNOWN_9602 (9602)
+		write VPC_UNKNOWN_9602 (9602)
 			VPC_UNKNOWN_9602: FALSE
 0000000001d9119c:		0000: 40960201 00000000
-t4		write PC_POLYGON_MODE (9981)
+		write PC_POLYGON_MODE (9981)
 			PC_POLYGON_MODE: { MODE = POLYMODE6_TRIANGLES }
 0000000001d911a4:		0000: 48998101 00000003
-t4		write PC_UNKNOWN_9E72 (9e72)
+		write PC_UNKNOWN_9E72 (9e72)
 			PC_UNKNOWN_9E72: 0
 0000000001d911ac:		0000: 409e7201 00000000
-t4		write VPC_POLYGON_MODE (9108)
+		write VPC_POLYGON_MODE (9108)
 			VPC_POLYGON_MODE: { MODE = POLYMODE6_TRIANGLES }
 0000000001d911b4:		0000: 48910801 00000003
-t4		write SP_TP_SAMPLE_CONFIG (b304)
+		write SP_TP_SAMPLE_CONFIG (b304)
 			SP_TP_SAMPLE_CONFIG: { 0 }
 0000000001d911bc:		0000: 48b30401 00000000
-t4		write SP_TP_MODE_CNTL (b309)
+		write SP_TP_MODE_CNTL (b309)
 			SP_TP_MODE_CNTL: { ISAMMODE = ISAMMODE_GL | UNK3 = 0x28 }
 0000000001d911c4:		0000: 40b30901 000000a2
-t4		write RB_SAMPLE_CONFIG (8804)
+		write RB_SAMPLE_CONFIG (8804)
 			RB_SAMPLE_CONFIG: { 0 }
 0000000001d911cc:		0000: 40880401 00000000
-t4		write GRAS_SAMPLE_CONFIG (80a4)
+		write GRAS_SAMPLE_CONFIG (80a4)
 			GRAS_SAMPLE_CONFIG: { 0 }
 0000000001d911d4:		0000: 4880a401 00000000
-t4		write GRAS_SAMPLE_LOCATION_0 (80a5)
+		write GRAS_SAMPLE_LOCATION_0 (80a5)
 			GRAS_SAMPLE_LOCATION_0: { SAMPLE_0_X = 0.000000 | SAMPLE_0_Y = 0.000000 | SAMPLE_1_X = 0.000000 | SAMPLE_1_Y = 0.000000 | SAMPLE_2_X = 0.000000 | SAMPLE_2_Y = 0.000000 | SAMPLE_3_X = 0.000000 | SAMPLE_3_Y = 0.000000 }
 0000000001d911dc:		0000: 4080a501 00000000
-t4		write GRAS_SAMPLE_LOCATION_1 (80a6)
+		write GRAS_SAMPLE_LOCATION_1 (80a6)
 			GRAS_SAMPLE_LOCATION_1: { SAMPLE_0_X = 0.000000 | SAMPLE_0_Y = 0.000000 | SAMPLE_1_X = 0.000000 | SAMPLE_1_Y = 0.000000 | SAMPLE_2_X = 0.000000 | SAMPLE_2_Y = 0.000000 | SAMPLE_3_X = 0.000000 | SAMPLE_3_Y = 0.000000 }
 0000000001d911e4:		0000: 4080a601 00000000
-t4		write RB_SAMPLE_LOCATION_0 (8805)
+		write RB_SAMPLE_LOCATION_0 (8805)
 			RB_SAMPLE_LOCATION_0: { SAMPLE_0_X = 0.000000 | SAMPLE_0_Y = 0.000000 | SAMPLE_1_X = 0.000000 | SAMPLE_1_Y = 0.000000 | SAMPLE_2_X = 0.000000 | SAMPLE_2_Y = 0.000000 | SAMPLE_3_X = 0.000000 | SAMPLE_3_Y = 0.000000 }
 0000000001d911ec:		0000: 48880501 00000000
-t4		write RB_SAMPLE_LOCATION_1 (8806)
+		write RB_SAMPLE_LOCATION_1 (8806)
 			RB_SAMPLE_LOCATION_1: { SAMPLE_0_X = 0.000000 | SAMPLE_0_Y = 0.000000 | SAMPLE_1_X = 0.000000 | SAMPLE_1_Y = 0.000000 | SAMPLE_2_X = 0.000000 | SAMPLE_2_Y = 0.000000 | SAMPLE_3_X = 0.000000 | SAMPLE_3_Y = 0.000000 }
 0000000001d911f4:		0000: 48880601 00000000
-t4		write RB_Z_BOUNDS_MIN (8878)
+		write RB_Z_BOUNDS_MIN (8878)
 			RB_Z_BOUNDS_MIN: 0.000000
 0000000001d911fc:		0000: 48887801 00000000
-t4		write RB_Z_BOUNDS_MAX (8879)
+		write RB_Z_BOUNDS_MAX (8879)
 			RB_Z_BOUNDS_MAX: 0.000000
 0000000001d91204:		0000: 40887901 00000000
-t4		write HLSQ_CONTROL_5_REG (b986)
+		write HLSQ_CONTROL_5_REG (b986)
 			HLSQ_CONTROL_5_REG: { LINELENGTHREGID = r63.x | FOVEATIONQUALITYREGID = r0.x }
 0000000001d9120c:		0000: 48b98601 000000fc
-t7		opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
+		opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
 0000000001d91214:		0000: 70268000
-t4		write CP_SCRATCH[0x7].REG (088a)
+		write CP_SCRATCH[0x7].REG (088a)
 			CP_SCRATCH[0x7].REG: 4
 			:0,0,0,4
 0000000001d91218:		0000: 48088a01 00000004
-t4		write VFD_MODE_CNTL (a007)
+		write VFD_MODE_CNTL (a007)
 			VFD_MODE_CNTL: { RENDER_MODE = RENDERING_PASS }
 0000000001d91220:		0000: 40a00701 00000000
-t4		write VFD_MULTIVIEW_CNTL (a008)
+		write VFD_MULTIVIEW_CNTL (a008)
 			VFD_MULTIVIEW_CNTL: { VIEWS = 0 }
 0000000001d91228:		0000: 40a00801 00000000
-t4		write PC_MODE_CNTL (9804)
+		write PC_MODE_CNTL (9804)
 			PC_MODE_CNTL: 0x1f
 0000000001d91230:		0000: 48980401 0000001f
-t7		opcode: CP_SET_DRAW_STATE (43) (4 dwords)
+		opcode: CP_SET_DRAW_STATE (43) (4 dwords)
 			{ COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 }
 			{ ADDR_LO = 0 }
 			{ ADDR_HI = 0 }
 0000000001d91238:		0000: 70438003 00040000 00000000 00000000
-t4		write VPC_SO_STREAM_CNTL (9305)
+		write VPC_SO_STREAM_CNTL (9305)
 			VPC_SO_STREAM_CNTL: { BUF0_STREAM = 0 | BUF1_STREAM = 0 | BUF2_STREAM = 0 | BUF3_STREAM = 0 | STREAM_ENABLE = 0 }
 0000000001d91248:		0000: 48930501 00000000
-t4		write GRAS_LRZ_CNTL (8100)
+		write GRAS_LRZ_CNTL (8100)
 			GRAS_LRZ_CNTL: { DIR = 0 }
 0000000001d91250:		0000: 48810001 00000000
-t4		write RB_LRZ_CNTL (8898)
+		write RB_LRZ_CNTL (8898)
 			RB_LRZ_CNTL: { 0 }
 0000000001d91258:		0000: 40889801 00000000
-t7		opcode: CP_EVENT_WRITE (46) (2 dwords)
+		opcode: CP_EVENT_WRITE (46) (2 dwords)
 			{ EVENT = LRZ_FLUSH }
 		event LRZ_FLUSH
 0000000001d91260:		0000: 70460001 00000026
-t7		opcode: CP_EVENT_WRITE (46) (2 dwords)
+		opcode: CP_EVENT_WRITE (46) (2 dwords)
 			{ EVENT = CACHE_INVALIDATE }
 		event CACHE_INVALIDATE
 0000000001d91268:		0000: 70460001 00000031
-t7		opcode: CP_SKIP_IB2_ENABLE_GLOBAL (1d) (2 dwords)
+		opcode: CP_SKIP_IB2_ENABLE_GLOBAL (1d) (2 dwords)
 0000000001d91270:		0000: 709d0001 00000000
-t7		opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
+		opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
 0000000001d91278:		0000: 70268000
-t4		write RB_CCU_CNTL (8e07)
+		write RB_CCU_CNTL (8e07)
 			RB_CCU_CNTL: { COLOR_OFFSET = 0xf8000 | DEPTH_OFFSET = 0 | GMEM | CONCURRENT_RESOLVE }
 0000000001d9127c:		0000: 408e0701 7c400004
-t4		write RB_DEPTH_BUFFER_INFO (8872)
+		write RB_DEPTH_BUFFER_INFO (8872)
 			RB_DEPTH_BUFFER_INFO: { DEPTH_FORMAT = DEPTH6_NONE }
 			RB_DEPTH_BUFFER_PITCH: 0
 			RB_DEPTH_BUFFER_ARRAY_PITCH: 0
@@ -255,20 +255,20 @@ t4		write RB_DEPTH_BUFFER_INFO (8872)
 			RB_DEPTH_BUFFER_BASE_HI: 0
 			RB_DEPTH_BUFFER_BASE_GMEM: 0
 0000000001d91284:		0000: 48887286 00000000 00000000 00000000 00000000 00000000 00000000
-t4		write GRAS_SU_DEPTH_BUFFER_INFO (8098)
+		write GRAS_SU_DEPTH_BUFFER_INFO (8098)
 			GRAS_SU_DEPTH_BUFFER_INFO: { DEPTH_FORMAT = DEPTH6_NONE }
 0000000001d912a0:		0000: 48809801 00000000
-t4		write GRAS_LRZ_BUFFER_BASE (8103)
+		write GRAS_LRZ_BUFFER_BASE (8103)
 			GRAS_LRZ_BUFFER_BASE: 0
 			GRAS_LRZ_BUFFER_BASE_HI: 0
 			GRAS_LRZ_BUFFER_PITCH: { PITCH = 0 | ARRAY_PITCH = 0 }
 			GRAS_LRZ_FAST_CLEAR_BUFFER_BASE: 0
 			GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI: 0
 0000000001d912a8:		0000: 48810385 00000000 00000000 00000000 00000000 00000000
-t4		write RB_STENCIL_INFO (8881)
+		write RB_STENCIL_INFO (8881)
 			RB_STENCIL_INFO: { 0 }
 0000000001d912c0:		0000: 48888101 00000000
-t4		write RB_MRT[0].BUF_INFO (8822)
+		write RB_MRT[0].BUF_INFO (8822)
 			RB_MRT[0].BUF_INFO: { COLOR_FORMAT = FMT6_8_8_8_X8_UNORM | COLOR_TILE_MODE = TILE6_LINEAR | COLOR_SWAP = WXYZ }
 			RB_MRT[0].PITCH: 8704
 			RB_MRT[0].ARRAY_PITCH: 12533760
@@ -276,101 +276,101 @@ t4		write RB_MRT[0].BUF_INFO (8822)
 			RB_MRT[0].BASE_HI: 0
 			RB_MRT[0].BASE_GMEM: 0
 0000000001d912c8:		0000: 48882286 00002031 00000088 0002fd00 01125000 00000000 00000000
-t4		write SP_FS_MRT[0].REG (a996)
+		write SP_FS_MRT[0].REG (a996)
 			SP_FS_MRT[0].REG: { COLOR_FORMAT = FMT6_8_8_8_X8_UNORM }
 0000000001d912e4:		0000: 48a99601 00000031
-t4		write RB_MRT_FLAG_BUFFER[0].ADDR (8903)
+		write RB_MRT_FLAG_BUFFER[0].ADDR (8903)
 			RB_MRT_FLAG_BUFFER[0].ADDR: 0
 			RB_MRT_FLAG_BUFFER[0].ADDR_HI: 0
 			RB_MRT_FLAG_BUFFER[0].PITCH: { PITCH = 0 | ARRAY_PITCH = 0 }
 0000000001d912ec:		0000: 40890383 00000000 00000000 00000000
-t4		write RB_SRGB_CNTL (880f)
+		write RB_SRGB_CNTL (880f)
 			RB_SRGB_CNTL: { 0 }
 0000000001d912fc:		0000: 48880f01 00000000
-t4		write SP_SRGB_CNTL (a98a)
+		write SP_SRGB_CNTL (a98a)
 			SP_SRGB_CNTL: { 0 }
 0000000001d91304:		0000: 40a98a01 00000000
-t4		write RB_RENDER_COMPONENTS (880d)
+		write RB_RENDER_COMPONENTS (880d)
 			RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 }
 0000000001d9130c:		0000: 40880d01 0000000f
-t4		write SP_FS_RENDER_COMPONENTS (a98b)
+		write SP_FS_RENDER_COMPONENTS (a98b)
 			SP_FS_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 }
 0000000001d91314:		0000: 48a98b01 0000000f
-t4		write GRAS_MAX_LAYER_INDEX (8004)
+		write GRAS_MAX_LAYER_INDEX (8004)
 			GRAS_MAX_LAYER_INDEX: 0
 0000000001d9131c:		0000: 48800401 00000000
-t4		write SP_TP_RAS_MSAA_CNTL (b300)
+		write SP_TP_RAS_MSAA_CNTL (b300)
 			SP_TP_RAS_MSAA_CNTL: { SAMPLES = MSAA_ONE }
 			SP_TP_DEST_MSAA_CNTL: { SAMPLES = MSAA_ONE | MSAA_DISABLE }
 0000000001d91324:		0000: 40b30002 00000000 00000004
-t4		write GRAS_RAS_MSAA_CNTL (80a2)
+		write GRAS_RAS_MSAA_CNTL (80a2)
 			GRAS_RAS_MSAA_CNTL: { SAMPLES = MSAA_ONE }
 			GRAS_DEST_MSAA_CNTL: { SAMPLES = MSAA_ONE | MSAA_DISABLE }
 0000000001d91330:		0000: 4880a202 00000000 00000004
-t4		write RB_RAS_MSAA_CNTL (8802)
+		write RB_RAS_MSAA_CNTL (8802)
 			RB_RAS_MSAA_CNTL: { SAMPLES = MSAA_ONE }
 			RB_DEST_MSAA_CNTL: { SAMPLES = MSAA_ONE | MSAA_DISABLE }
 0000000001d9133c:		0000: 40880202 00000000 00000004
-t4		write RB_BLIT_GMEM_MSAA_CNTL (88d5)
+		write RB_BLIT_GMEM_MSAA_CNTL (88d5)
 			RB_BLIT_GMEM_MSAA_CNTL: { SAMPLES = MSAA_ONE }
 0000000001d91348:		0000: 4088d501 00000000
-t4		write VPC_SO_DISABLE (9306)
+		write VPC_SO_DISABLE (9306)
 			VPC_SO_DISABLE: { 0 }
 0000000001d91350:		0000: 48930601 00000000
-t4		write GRAS_BIN_CONTROL (80a1)
+		write GRAS_BIN_CONTROL (80a1)
 			GRAS_BIN_CONTROL: { BINW = 544 | BINH = 480 | RENDER_MODE = BINNING_PASS | BUFFERS_LOCATION = BUFFERS_IN_GMEM | LRZ_FEEDBACK_ZMODE_MASK = 0x6 }
 0000000001d91358:		0000: 4880a101 06041e11
-t4		write RB_BIN_CONTROL (8800)
+		write RB_BIN_CONTROL (8800)
 			RB_BIN_CONTROL: { BINW = 544 | BINH = 480 | RENDER_MODE = BINNING_PASS | BUFFERS_LOCATION = BUFFERS_IN_GMEM | LRZ_FEEDBACK_ZMODE_MASK = 0x6 }
 0000000001d91360:		0000: 48880001 06041e11
-t4		write RB_BIN_CONTROL2 (88d3)
+		write RB_BIN_CONTROL2 (88d3)
 			RB_BIN_CONTROL2: { BINW = 544 | BINH = 480 }
 0000000001d91368:		0000: 4088d301 00001e11
-t7		opcode: CP_REG_WRITE (6d) (4 dwords)
+		opcode: CP_REG_WRITE (6d) (4 dwords)
 			{ TRACKER = TRACK_RENDER_CNTL }
 			RB_RENDER_CNTL: { CCUSINGLECACHELINESIZE = 0x2 | BINNING | RASTER_MODE = TYPE_TILED | RASTER_DIRECTION = LR_TB | FLAG_MRTS = 0 }
 0000000001d91370:		0000: 706d8003 00000002 00008801 00000090
-t4		write GRAS_SC_WINDOW_SCISSOR_TL (80f0)
+		write GRAS_SC_WINDOW_SCISSOR_TL (80f0)
 			GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
 			GRAS_SC_WINDOW_SCISSOR_BR: { X = 2159 | Y = 1439 }
 0000000001d91380:		0000: 4080f002 00000000 059f086f
-t4		write GRAS_2D_RESOLVE_CNTL_1 (840a)
+		write GRAS_2D_RESOLVE_CNTL_1 (840a)
 			GRAS_2D_RESOLVE_CNTL_1: { X = 0 | Y = 0 }
 			GRAS_2D_RESOLVE_CNTL_2: { X = 2159 | Y = 1439 }
 0000000001d9138c:		0000: 48840a02 00000000 059f086f
-t7		opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
+		opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
 0000000001d91398:		0000: 70268000
-t4		write CP_SCRATCH[0x7].REG (088a)
+		write CP_SCRATCH[0x7].REG (088a)
 			CP_SCRATCH[0x7].REG: 9
 			:0,0,0,9
 0000000001d9139c:		0000: 48088a01 00000009
-t7		opcode: CP_SET_MARKER (65) (2 dwords)
+		opcode: CP_SET_MARKER (65) (2 dwords)
 			{ MODE = RM6_BINNING | MARKER = RM6_BINNING }
 0000000001d913a4:		0000: 70e50001 00000002
-t7		opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
+		opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
 0000000001d913ac:		0000: 70268000
-t4		write CP_SCRATCH[0x7].REG (088a)
+		write CP_SCRATCH[0x7].REG (088a)
 			CP_SCRATCH[0x7].REG: 10
 			:0,0,0,10
 0000000001d913b0:		0000: 48088a01 0000000a
-t7		opcode: CP_SET_VISIBILITY_OVERRIDE (64) (2 dwords)
+		opcode: CP_SET_VISIBILITY_OVERRIDE (64) (2 dwords)
 0000000001d913b8:		0000: 70640001 00000001
-t7		opcode: CP_SET_MODE (63) (2 dwords)
+		opcode: CP_SET_MODE (63) (2 dwords)
 0000000001d913c0:		0000: 70e30001 00000001
-t7		opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
+		opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
 0000000001d913c8:		0000: 70268000
-t4		write VFD_MODE_CNTL (a007)
+		write VFD_MODE_CNTL (a007)
 			VFD_MODE_CNTL: { RENDER_MODE = BINNING_PASS }
 0000000001d913cc:		0000: 40a00701 00000001
-t4		write VSC_BIN_SIZE (0c02)
+		write VSC_BIN_SIZE (0c02)
 			VSC_BIN_SIZE: { WIDTH = 544 | HEIGHT = 480 }
 			VSC_DRAW_STRM_SIZE_ADDRESS: 0x1d65800
 			VSC_DRAW_STRM_SIZE_ADDRESS_HI: 0
 0000000001d913d4:		0000: 400c0283 00001e11 01d65800 00000000
-t4		write VSC_BIN_COUNT (0c06)
+		write VSC_BIN_COUNT (0c06)
 			VSC_BIN_COUNT: { NX = 4 | NY = 3 }
 0000000001d913e4:		0000: 480c0601 00001808
-t4		write VSC_PIPE_CONFIG[0].REG (0c10)
+		write VSC_PIPE_CONFIG[0].REG (0c10)
 			VSC_PIPE_CONFIG[0].REG: { X = 0 | Y = 0 | W = 1 | H = 1 }
 			VSC_PIPE_CONFIG[0x1].REG: { X = 1 | Y = 0 | W = 1 | H = 1 }
 			VSC_PIPE_CONFIG[0x2].REG: { X = 2 | Y = 0 | W = 1 | H = 1 }
@@ -406,66 +406,66 @@ t4		write VSC_PIPE_CONFIG[0].REG (0c10)
 0000000001d913ec:		0000: 400c1020 04100000 04100001 04100002 04100003 04100400 04100401 04100402
 0000000001d9140c:		0020: 04100403 04100800 04100801 04100802 04100803 00000000 00000000 00000000
 *
-t4		write VSC_PRIM_STRM_ADDRESS (0c30)
+		write VSC_PRIM_STRM_ADDRESS (0c30)
 			VSC_PRIM_STRM_ADDRESS: 0x1d67000
 			VSC_PRIM_STRM_ADDRESS_HI: 0
 			VSC_PRIM_STRM_PITCH: 0x1040
 			VSC_PRIM_STRM_LIMIT: 0x28000
 0000000001d91470:		0000: 480c3004 01d67000 00000000 00001040 00028000
-t4		write VSC_DRAW_STRM_ADDRESS (0c34)
+		write VSC_DRAW_STRM_ADDRESS (0c34)
 			VSC_DRAW_STRM_ADDRESS: 0x1d5d000
 			VSC_DRAW_STRM_ADDRESS_HI: 0
 			VSC_DRAW_STRM_PITCH: 0x440
 			VSC_DRAW_STRM_LIMIT: 0xa000
 0000000001d91484:		0000: 400c3404 01d5d000 00000000 00000440 0000a000
-t4		write PC_POWER_CNTL (9805)
+		write PC_POWER_CNTL (9805)
 			PC_POWER_CNTL: 0x1
 0000000001d91498:		0000: 40980501 00000001
-t4		write VFD_POWER_CNTL (a0f8)
+		write VFD_POWER_CNTL (a0f8)
 			VFD_POWER_CNTL: 0x1
 0000000001d914a0:		0000: 40a0f801 00000001
-t7		opcode: CP_EVENT_WRITE (46) (2 dwords)
+		opcode: CP_EVENT_WRITE (46) (2 dwords)
 			{ EVENT = UNK_2C }
 		event UNK_2C
 0000000001d914a8:		0000: 70460001 0000002c
-t4		write RB_WINDOW_OFFSET (8890)
+		write RB_WINDOW_OFFSET (8890)
 			RB_WINDOW_OFFSET: { X = 0 | Y = 0 }
 0000000001d914b0:		0000: 48889001 00000000
-t4		write SP_TP_WINDOW_OFFSET (b307)
+		write SP_TP_WINDOW_OFFSET (b307)
 			SP_TP_WINDOW_OFFSET: { X = 0 | Y = 0 }
 0000000001d914b8:		0000: 48b30701 00000000
-t7		opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
+		opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
 0000000001d914c0:		0000: 70268000
-t4		write CP_SCRATCH[0x6].REG (0889)
+		write CP_SCRATCH[0x6].REG (0889)
 			CP_SCRATCH[0x6].REG: 11
 			:0,0,11,10
 0000000001d914c4:		0000: 48088901 0000000b
-t7		opcode: CP_INDIRECT_BUFFER (3f) (4 dwords)
+		opcode: CP_INDIRECT_BUFFER (3f) (4 dwords)
 		ibaddr:0000000001d8f000
 		ibsize:00000053
-t4			write VFD_INDEX_OFFSET (a00e)
+			write VFD_INDEX_OFFSET (a00e)
 				VFD_INDEX_OFFSET: 0
 0000000001d8f000:			0000: 40a00e01 00000000
-t4			write VFD_INSTANCE_START_OFFSET (a00f)
+			write VFD_INSTANCE_START_OFFSET (a00f)
 				VFD_INSTANCE_START_OFFSET: 0
 0000000001d8f008:			0000: 48a00f01 00000000
-t4			write PC_RESTART_INDEX (9803)
+			write PC_RESTART_INDEX (9803)
 				PC_RESTART_INDEX: 4294967295
 0000000001d8f010:			0000: 40980301 ffffffff
-t7			opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
 0000000001d8f018:			0000: 70268000
-t4			write CP_SCRATCH[0x5].REG (0888)
+			write CP_SCRATCH[0x5].REG (0888)
 				CP_SCRATCH[0x5].REG: 1
 				:0,1,11,10
 0000000001d8f01c:			0000: 40088801 00000001
-t4			write RB_STENCILREF (8887)
+			write RB_STENCILREF (8887)
 				RB_STENCILREF: { REF = 0 | BFREF = 0 }
 0000000001d8f024:			0000: 48888701 00000000
-t4			write GRAS_SC_SCREEN_SCISSOR[0].TL (80b0)
+			write GRAS_SC_SCREEN_SCISSOR[0].TL (80b0)
 				GRAS_SC_SCREEN_SCISSOR[0].TL: { X = 0 | Y = 0 }
 				GRAS_SC_SCREEN_SCISSOR[0].BR: { X = 2159 | Y = 1439 }
 0000000001d8f02c:			0000: 4880b002 00000000 059f086f
-t4			write GRAS_CL_VPORT[0].XOFFSET (8010)
+			write GRAS_CL_VPORT[0].XOFFSET (8010)
 				GRAS_CL_VPORT[0].XOFFSET: 1080.000000
 				GRAS_CL_VPORT[0].XSCALE: 1080.000000
 				GRAS_CL_VPORT[0].YOFFSET: 720.000000
@@ -473,23 +473,23 @@ t4			write GRAS_CL_VPORT[0].XOFFSET (8010)
 				GRAS_CL_VPORT[0].ZOFFSET: 0.500000
 				GRAS_CL_VPORT[0].ZSCALE: 0.500000
 0000000001d8f038:			0000: 48801086 44870000 44870000 44340000 44340000 3f000000 3f000000
-t4			write GRAS_SC_VIEWPORT_SCISSOR[0].TL (80d0)
+			write GRAS_SC_VIEWPORT_SCISSOR[0].TL (80d0)
 				GRAS_SC_VIEWPORT_SCISSOR[0].TL: { X = 0 | Y = 0 }
 				GRAS_SC_VIEWPORT_SCISSOR[0].BR: { X = 2159 | Y = 1439 }
 0000000001d8f054:			0000: 4880d002 00000000 059f086f
-t4			write GRAS_CL_GUARDBAND_CLIP_ADJ (8006)
+			write GRAS_CL_GUARDBAND_CLIP_ADJ (8006)
 				GRAS_CL_GUARDBAND_CLIP_ADJ: { HORZ = 311 | VERT = 349 }
 0000000001d8f060:			0000: 40800601 00057537
-t4			write RB_BLEND_CNTL (8865)
+			write RB_BLEND_CNTL (8865)
 				RB_BLEND_CNTL: { ENABLE_BLEND = 0 | SAMPLE_MASK = 0xffff }
 0000000001d8f068:			0000: 48886501 ffff0000
-t4			write RB_BLEND_RED_F32 (8860)
+			write RB_BLEND_RED_F32 (8860)
 				RB_BLEND_RED_F32: 0.000000
 				RB_BLEND_GREEN_F32: 0.000000
 				RB_BLEND_BLUE_F32: 0.000000
 				RB_BLEND_ALPHA_F32: 0.000000
 0000000001d8f070:			0000: 48886004 00000000 00000000 00000000 00000000
-t7			opcode: CP_SET_DRAW_STATE (43) (40 dwords)
+			opcode: CP_SET_DRAW_STATE (43) (40 dwords)
 				{ COUNT = 12 | BINNING | GMEM | SYSMEM | GROUP_ID = 7 }
 				{ ADDR_LO = 0x1116000 }
 				{ ADDR_HI = 0 }
@@ -534,9 +534,9 @@ t7			opcode: CP_SET_DRAW_STATE (43) (40 dwords)
 0000000001d8f0c4:			0040: 03600012 01122000 00000000 1570000e 01123000 00000000 04600005 01116030
 0000000001d8f0e4:			0060: 00000000 08720000 00000000 00000000 0c600014 01116050 00000000 0d720000
 0000000001d8f104:			0080: 00000000 00000000 17600024 01124000 00000000 14600009 011160a0 00000000
-t7			opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
 0000000001d8f124:			0000: 70268000
-t4			write CP_SCRATCH[0x7].REG (088a)
+			write CP_SCRATCH[0x7].REG (088a)
 				CP_SCRATCH[0x7].REG: 2
 				:0,1,11,2
 0000000001d8f128:			0000: 48088a01 00000002
@@ -548,34 +548,34 @@ t4			write CP_SCRATCH[0x7].REG (088a)
 000000000111f000:				0000: 40bb0801 000000ff 48b80004 00000100 00000000 00000000 00000000 40bb1001
 000000000111f020:				0020: 00000108 48a82301 00000100 48a83b01 00000000 40a86301 00000000 48a89401
 000000000111f040:				0040: 00000000 48ab0401 00000100 48ab2001 00000000
-t4					write HLSQ_INVALIDATE_CMD (bb08)
+					write HLSQ_INVALIDATE_CMD (bb08)
 						HLSQ_INVALIDATE_CMD: { VS_STATE | HS_STATE | DS_STATE | GS_STATE | FS_STATE | CS_STATE | CS_IBO | GFX_IBO | CS_BINDLESS = 0 | GFX_BINDLESS = 0 }
 000000000111f000:					0000: 40bb0801 000000ff
-t4					write HLSQ_VS_CNTL (b800)
+					write HLSQ_VS_CNTL (b800)
 						HLSQ_VS_CNTL: { CONSTLEN = 0 | ENABLED }
 						HLSQ_HS_CNTL: { CONSTLEN = 0 }
 						HLSQ_DS_CNTL: { CONSTLEN = 0 }
 						HLSQ_GS_CNTL: { CONSTLEN = 0 }
 000000000111f008:					0000: 48b80004 00000100 00000000 00000000 00000000
-t4					write HLSQ_FS_CNTL (bb10)
+					write HLSQ_FS_CNTL (bb10)
 						HLSQ_FS_CNTL: { CONSTLEN = 32 | ENABLED }
 000000000111f01c:					0000: 40bb1001 00000108
-t4					write SP_VS_CONFIG (a823)
+					write SP_VS_CONFIG (a823)
 						SP_VS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 }
 000000000111f024:					0000: 48a82301 00000100
-t4					write SP_HS_CONFIG (a83b)
+					write SP_HS_CONFIG (a83b)
 						SP_HS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 }
 000000000111f02c:					0000: 48a83b01 00000000
-t4					write SP_DS_CONFIG (a863)
+					write SP_DS_CONFIG (a863)
 						SP_DS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 }
 000000000111f034:					0000: 40a86301 00000000
-t4					write SP_GS_CONFIG (a894)
+					write SP_GS_CONFIG (a894)
 						SP_GS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 }
 000000000111f03c:					0000: 48a89401 00000000
-t4					write SP_FS_CONFIG (ab04)
+					write SP_FS_CONFIG (ab04)
 						SP_FS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 }
 000000000111f044:					0000: 48ab0401 00000100
-t4					write SP_IBO_COUNT (ab20)
+					write SP_IBO_COUNT (ab20)
 						SP_IBO_COUNT: 0
 000000000111f04c:					0000: 48ab2001 00000000
 			group_id: 1
@@ -602,28 +602,28 @@ t4					write SP_IBO_COUNT (ab20)
 0000000001121120:				0120: 000000fc 000000fc 40930101 00ff0004 409b0601 00000000 40a87101 00000000
 0000000001121140:				0140: 48910101 00ffff00 48910701 00000000 40a00186 fcfcfcfc 0000fcfc fcfcfcfc
 0000000001121160:				0160: 000000fc 0000fcfc 00000000 40887001 00000000 48809401 00000000
-t4					write SP_HS_OBJ_FIRST_EXEC_OFFSET (a833)
+					write SP_HS_OBJ_FIRST_EXEC_OFFSET (a833)
 						SP_HS_OBJ_FIRST_EXEC_OFFSET: 0
 0000000001121000:					0000: 40a83301 00000000
-t4					write SP_FS_PREFETCH_CNTL (a99e)
+					write SP_FS_PREFETCH_CNTL (a99e)
 						SP_FS_PREFETCH_CNTL: { COUNT = 0 | UNK6 = 0x1ff }
 0000000001121008:					0000: 40a99e01 00007fc0
-t4					write SP_UNKNOWN_A9A8 (a9a8)
+					write SP_UNKNOWN_A9A8 (a9a8)
 						SP_UNKNOWN_A9A8: 0
 0000000001121010:					0000: 40a9a801 00000000
-t4					write SP_MODE_CONTROL (ab00)
+					write SP_MODE_CONTROL (ab00)
 						SP_MODE_CONTROL: { CONSTANT_DEMOTION_ENABLE | ISAMMODE = ISAMMODE_GL }
 0000000001121018:					0000: 40ab0001 00000005
-t4					write SP_FS_OUTPUT_CNTL0 (a98c)
+					write SP_FS_OUTPUT_CNTL0 (a98c)
 						SP_FS_OUTPUT_CNTL0: { DEPTH_REGID = r63.x | SAMPMASK_REGID = r63.x | STENCILREF_REGID = r63.x }
 0000000001121020:					0000: 40a98c01 fcfcfc00
-t4					write SP_VS_CTRL_REG0 (a800)
+					write SP_VS_CTRL_REG0 (a800)
 						SP_VS_CTRL_REG0: { MERGEDREGS | THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | BRANCHSTACK = 0 | 0x80000000 }
 0000000001121028:					0000: 40a80001 80100080
-t4					write SP_VS_INSTRLEN (a824)
+					write SP_VS_INSTRLEN (a824)
 						SP_VS_INSTRLEN: 1
 0000000001121030:					0000: 40a82401 00000001
-t4					write SP_VS_OBJ_START (a81c)
+					write SP_VS_OBJ_START (a81c)
 						SP_VS_OBJ_START: 0x1011000		base=1011000, offset=0, size=128
 0000000001011000:							0000: 00000000 03000000 00000000 00000000 00000000 00000000 00000000 00000000
 *
@@ -639,7 +639,7 @@ t4					write SP_VS_OBJ_START (a81c)
 							- shaderdb: 0 sstall, 0 (ss), 0 (sy)
 						SP_VS_OBJ_START_HI: 0
 0000000001121038:					0000: 48a81c02 01011000 00000000
-t7					opcode: CP_LOAD_STATE6_GEOM (32) (4 dwords)
+					opcode: CP_LOAD_STATE6_GEOM (32) (4 dwords)
 						{ DST_OFF = 0 | STATE_TYPE = ST6_SHADER | STATE_SRC = SS6_INDIRECT | STATE_BLOCK = SB6_VS_SHADER | NUM_UNIT = 1 }
 						{ EXT_SRC_ADDR = 0x1011000 }
 						{ EXT_SRC_ADDR_HI = 0 }
@@ -654,69 +654,69 @@ t7					opcode: CP_LOAD_STATE6_GEOM (32) (4 dwords)
 						- shaderdb: 5 cat0, 0 cat1, 0 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7
 						- shaderdb: 0 sstall, 0 (ss), 0 (sy)
 0000000001121044:					0000: 70328003 00620000 01011000 00000000
-t4					write VPC_VAR[0].DISABLE (9212)
+					write VPC_VAR[0].DISABLE (9212)
 						VPC_VAR[0].DISABLE: 0xffffffff
 						VPC_VAR[0x1].DISABLE: 0xffffffff
 						VPC_VAR[0x2].DISABLE: 0xffffffff
 						VPC_VAR[0x3].DISABLE: 0xffffffff
 0000000001121054:					0000: 40921204 ffffffff ffffffff ffffffff ffffffff
-t4					write SP_VS_OUT[0].REG (a803)
+					write SP_VS_OUT[0].REG (a803)
 						SP_VS_OUT[0].REG: { A_REGID = r0.x | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 }
 0000000001121068:					0000: 40a80301 00000f00
-t4					write SP_VS_VPC_DST[0].REG (a813)
+					write SP_VS_VPC_DST[0].REG (a813)
 						SP_VS_VPC_DST[0].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 }
 0000000001121070:					0000: 48a81301 00000000
-t4					write SP_HS_WAVE_INPUT_SIZE (a831)
+					write SP_HS_WAVE_INPUT_SIZE (a831)
 						SP_HS_WAVE_INPUT_SIZE: 0
 0000000001121078:					0000: 48a83101 00000000
-t4					write SP_VS_PRIMITIVE_CNTL (a802)
+					write SP_VS_PRIMITIVE_CNTL (a802)
 						SP_VS_PRIMITIVE_CNTL: { OUT = 1 | FLAGS_REGID = r0.x }
 0000000001121080:					0000: 48a80201 00000001
-t4					write VPC_CNTL_0 (9304)
+					write VPC_CNTL_0 (9304)
 						VPC_CNTL_0: { NUMNONPOSVAR = 0 | PRIMIDLOC = 255 | VIEWIDLOC = 255 }
 0000000001121088:					0000: 40930401 ff00ff00
-t4					write PC_VS_OUT_CNTL (9b01)
+					write PC_VS_OUT_CNTL (9b01)
 						PC_VS_OUT_CNTL: { STRIDE_IN_VPC = 4 | CLIP_MASK = 0 }
 0000000001121090:					0000: 489b0101 00000004
-t4					write PC_HS_OUT_CNTL (9b03)
+					write PC_HS_OUT_CNTL (9b03)
 						PC_HS_OUT_CNTL: { STRIDE_IN_VPC = 0 | CLIP_MASK = 0 }
 0000000001121098:					0000: 409b0301 00000000
-t4					write HLSQ_CONTROL_1_REG (b982)
+					write HLSQ_CONTROL_1_REG (b982)
 						HLSQ_CONTROL_1_REG: 0x7
 						HLSQ_CONTROL_2_REG: { FACEREGID = r63.x | SAMPLEID = r63.x | SAMPLEMASK = r63.x | CENTERRHW = r63.x }
 						HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r63.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x }
 						HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | XYCOORDREGID = r63.x | ZWCOORDREGID = r63.x }
 						HLSQ_CONTROL_5_REG: { LINELENGTHREGID = r63.x | FOVEATIONQUALITYREGID = r0.x }
 00000000011210a0:					0000: 40b98285 00000007 fcfcfcfc fcfcfcfc fcfcfcfc 000000fc
-t4					write HLSQ_FS_CNTL_0 (b980)
+					write HLSQ_FS_CNTL_0 (b980)
 						HLSQ_FS_CNTL_0: { THREADSIZE = THREAD128 }
 00000000011210b8:					0000: 48b98001 00000001
-t4					write SP_FS_CTRL_REG0 (a980)
+					write SP_FS_CTRL_REG0 (a980)
 						SP_FS_CTRL_REG0: { THREADSIZE = THREAD128 | UNK24 | MERGEDREGS | THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | BRANCHSTACK = 0 }
 00000000011210c0:					0000: 40a98001 81100080
-t4					write SP_FS_OBJ_FIRST_EXEC_OFFSET (a982)
+					write SP_FS_OBJ_FIRST_EXEC_OFFSET (a982)
 						SP_FS_OBJ_FIRST_EXEC_OFFSET: 0
 00000000011210c8:					0000: 48a98201 00000000
-t4					write VPC_VS_LAYER_CNTL (9104)
+					write VPC_VS_LAYER_CNTL (9104)
 						VPC_VS_LAYER_CNTL: { LAYERLOC = 255 | VIEWLOC = 255 }
 00000000011210d0:					0000: 48910401 0000ffff
-t4					write GRAS_CNTL (8005)
+					write GRAS_CNTL (8005)
 						GRAS_CNTL: { COORD_MASK = 0 }
 00000000011210d8:					0000: 40800501 00000000
-t4					write RB_RENDER_CONTROL0 (8809)
+					write RB_RENDER_CONTROL0 (8809)
 						RB_RENDER_CONTROL0: { COORD_MASK = 0 }
 						RB_RENDER_CONTROL1: { FRAGCOORDSAMPLEMODE = FRAGCOORD_CENTER }
 00000000011210e0:					0000: 48880902 00000000 00000000
-t4					write RB_SAMPLE_CNTL (8810)
+					write RB_SAMPLE_CNTL (8810)
 						RB_SAMPLE_CNTL: { 0 }
 00000000011210ec:					0000: 40881001 00000000
-t4					write GRAS_LRZ_PS_INPUT_CNTL (8101)
+					write GRAS_LRZ_PS_INPUT_CNTL (8101)
 						GRAS_LRZ_PS_INPUT_CNTL: { FRAGCOORDSAMPLEMODE = FRAGCOORD_CENTER }
 00000000011210f4:					0000: 40810101 00000000
-t4					write GRAS_SAMPLE_CNTL (8109)
+					write GRAS_SAMPLE_CNTL (8109)
 						GRAS_SAMPLE_CNTL: { 0 }
 00000000011210fc:					0000: 48810901 00000000
-t4					write SP_FS_OUTPUT[0].REG (a98e)
+					write SP_FS_OUTPUT[0].REG (a98e)
 						SP_FS_OUTPUT[0].REG: { REGID = r63.x }
 						SP_FS_OUTPUT[0x1].REG: { REGID = r63.x }
 						SP_FS_OUTPUT[0x2].REG: { REGID = r63.x }
@@ -727,22 +727,22 @@ t4					write SP_FS_OUTPUT[0].REG (a98e)
 						SP_FS_OUTPUT[0x7].REG: { REGID = r63.x }
 0000000001121104:					0000: 48a98e08 000000fc 000000fc 000000fc 000000fc 000000fc 000000fc 000000fc
 0000000001121124:					0020: 000000fc
-t4					write VPC_VS_PACK (9301)
+					write VPC_VS_PACK (9301)
 						VPC_VS_PACK: { STRIDE_IN_VPC = 4 | POSITIONLOC = 0 | PSIZELOC = 255 | EXTRAPOS = 0 }
 0000000001121128:					0000: 40930101 00ff0004
-t4					write PC_PRIMITIVE_CNTL_6 (9b06)
+					write PC_PRIMITIVE_CNTL_6 (9b06)
 						PC_PRIMITIVE_CNTL_6: { STRIDE_IN_VPC = 0 }
 0000000001121130:					0000: 409b0601 00000000
-t4					write SP_GS_PRIM_SIZE (a871)
+					write SP_GS_PRIM_SIZE (a871)
 						SP_GS_PRIM_SIZE: 0
 0000000001121138:					0000: 40a87101 00000000
-t4					write VPC_VS_CLIP_CNTL (9101)
+					write VPC_VS_CLIP_CNTL (9101)
 						VPC_VS_CLIP_CNTL: { CLIP_MASK = 0 | CLIP_DIST_03_LOC = 255 | CLIP_DIST_47_LOC = 255 }
 0000000001121140:					0000: 48910101 00ffff00
-t4					write VPC_UNKNOWN_9107 (9107)
+					write VPC_UNKNOWN_9107 (9107)
 						VPC_UNKNOWN_9107: { 0 }
 0000000001121148:					0000: 48910701 00000000
-t4					write VFD_CONTROL_1 (a001)
+					write VFD_CONTROL_1 (a001)
 						VFD_CONTROL_1: { REGID4VTX = r63.x | REGID4INST = r63.x | REGID4PRIMID = r63.x | REGID4VIEWID = r63.x }
 						VFD_CONTROL_2: { REGID_HSRELPATCHID = r63.x | REGID_INVOCATIONID = r63.x }
 						VFD_CONTROL_3: { REGID_DSPRIMID = r63.x | REGID_DSRELPATCHID = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x }
@@ -750,10 +750,10 @@ t4					write VFD_CONTROL_1 (a001)
 						VFD_CONTROL_5: { REGID_GSHEADER = r63.x | UNK8 = r63.x }
 						VFD_CONTROL_6: { 0 }
 0000000001121150:					0000: 40a00186 fcfcfcfc 0000fcfc fcfcfcfc 000000fc 0000fcfc 00000000
-t4					write RB_DEPTH_PLANE_CNTL (8870)
+					write RB_DEPTH_PLANE_CNTL (8870)
 						RB_DEPTH_PLANE_CNTL: { Z_MODE = A6XX_EARLY_Z }
 000000000112116c:					0000: 40887001 00000000
-t4					write GRAS_SU_DEPTH_PLANE_CNTL (8094)
+					write GRAS_SU_DEPTH_PLANE_CNTL (8094)
 						GRAS_SU_DEPTH_PLANE_CNTL: { Z_MODE = A6XX_EARLY_Z }
 0000000001121174:					0000: 48809401 00000000
 			group_id: 3
@@ -777,20 +777,20 @@ t4					write GRAS_SU_DEPTH_PLANE_CNTL (8094)
 			enable_mask: 0x7
 0000000001116000:				0000: 40a01004 01016000 00000000 00100000 0000000c 48a09002 c7400000 00000001
 0000000001116020:				0020: 40a0d001 0000000f 48a00001 00000101
-t4					write VFD_FETCH[0].BASE (a010)
+					write VFD_FETCH[0].BASE (a010)
 						VFD_FETCH[0].BASE: 0x1016000
 						VFD_FETCH[0].BASE_HI: 0
 						VFD_FETCH[0].SIZE: 1048576
 						VFD_FETCH[0].STRIDE: 12
 0000000001116000:					0000: 40a01004 01016000 00000000 00100000 0000000c
-t4					write VFD_DECODE[0].INSTR (a090)
+					write VFD_DECODE[0].INSTR (a090)
 						VFD_DECODE[0].INSTR: { IDX = 0 | OFFSET = 0 | FORMAT = FMT6_32_32_32_FLOAT | SWAP = WZYX | UNK30 | FLOAT }
 						VFD_DECODE[0].STEP_RATE: 1
 0000000001116014:					0000: 48a09002 c7400000 00000001
-t4					write VFD_DEST_CNTL[0].INSTR (a0d0)
+					write VFD_DEST_CNTL[0].INSTR (a0d0)
 						VFD_DEST_CNTL[0].INSTR: { WRITEMASK = 0xf | REGID = r0.x }
 0000000001116020:					0000: 40a0d001 0000000f
-t4					write VFD_CONTROL_0 (a000)
+					write VFD_CONTROL_0 (a000)
 						VFD_CONTROL_0: { FETCH_CNT = 1 | DECODE_CNT = 1 }
 0000000001116028:					0000: 48a00001 00000101
 			group_id: 12
@@ -814,23 +814,23 @@ t4					write VFD_CONTROL_0 (a000)
 			enable_mask: 0x7
 0000000001123000:				0000: 40800002 00000080 00000000 40809001 00000014 48809102 00100010 00000010
 0000000001123020:				0020: 40809583 00000000 00000000 00000000 409b0001 00000002
-t4					write GRAS_CL_CNTL (8000)
+					write GRAS_CL_CNTL (8000)
 						GRAS_CL_CNTL: { VP_CLIP_CODE_IGNORE }
 						GRAS_VS_CL_CNTL: { CLIP_MASK = 0 | CULL_MASK = 0 }
 0000000001123000:					0000: 40800002 00000080 00000000
-t4					write GRAS_SU_CNTL (8090)
+					write GRAS_SU_CNTL (8090)
 						GRAS_SU_CNTL: { FRONT_CW | LINEHALFWIDTH = 0.500000 | LINE_MODE = BRESENHAM }
 000000000112300c:					0000: 40809001 00000014
-t4					write GRAS_SU_POINT_MINMAX (8091)
+					write GRAS_SU_POINT_MINMAX (8091)
 						GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 1.000000 }
 						GRAS_SU_POINT_SIZE: 1.000000
 0000000001123014:					0000: 48809102 00100010 00000010
-t4					write GRAS_SU_POLY_OFFSET_SCALE (8095)
+					write GRAS_SU_POLY_OFFSET_SCALE (8095)
 						GRAS_SU_POLY_OFFSET_SCALE: 0.000000
 						GRAS_SU_POLY_OFFSET_OFFSET: 0.000000
 						GRAS_SU_POLY_OFFSET_OFFSET_CLAMP: 0.000000
 0000000001123020:					0000: 40809583 00000000 00000000 00000000
-t4					write PC_PRIMITIVE_CNTL_0 (9b00)
+					write PC_PRIMITIVE_CNTL_0 (9b00)
 						PC_PRIMITIVE_CNTL_0: { PROVOKING_VTX_LAST }
 0000000001123030:					0000: 409b0001 00000002
 			group_id: 22
@@ -840,16 +840,16 @@ t4					write PC_PRIMITIVE_CNTL_0 (9b00)
 			enable_mask: 0x7
 000000000111e000:				0000: 40886401 00000000 40888001 00000000 48887101 00000000 48888802 00000000
 *
-t4					write RB_ALPHA_CONTROL (8864)
+					write RB_ALPHA_CONTROL (8864)
 						RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_NEVER }
 000000000111e000:					0000: 40886401 00000000
-t4					write RB_STENCIL_CONTROL (8880)
+					write RB_STENCIL_CONTROL (8880)
 						RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP }
 000000000111e008:					0000: 40888001 00000000
-t4					write RB_DEPTH_CNTL (8871)
+					write RB_DEPTH_CNTL (8871)
 						RB_DEPTH_CNTL: { ZFUNC = FUNC_NEVER }
 000000000111e010:					0000: 48887101 00000000
-t4					write RB_STENCILMASK (8888)
+					write RB_STENCILMASK (8888)
 						RB_STENCILMASK: { MASK = 0 | BFMASK = 0 }
 						RB_STENCILWRMASK: { WRMASK = 0 | BFWRMASK = 0 }
 000000000111e018:					0000: 48888802 00000000 00000000
@@ -860,7 +860,7 @@ t4					write RB_STENCILMASK (8888)
 			enable_mask: 0x6
 				skipped!
 
-t7			opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords)
+			opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords)
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = USE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_8_BIT | PATCH_TYPE = TESS_QUADS }
 				{ NUM_INSTANCES = 1 }
 				{ NUM_INDICES = 4 }
@@ -1151,40 +1151,40 @@ t7			opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords)
  +	00000000			HLSQ_UNKNOWN_BE01: 0
 !+	00080000			HLSQ_DBG_ECO_CNTL: 0x80000
 0000000001d8f130:			0000: 70388003 00000186 00000001 00000004
-t7			opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
 0000000001d8f140:			0000: 70268000
-t4			write CP_SCRATCH[0x7].REG (088a)
+			write CP_SCRATCH[0x7].REG (088a)
 				CP_SCRATCH[0x7].REG: 3
 				:0,1,11,3
 0000000001d8f144:			0000: 48088a01 00000003
 0000000001d914cc:		0000: 70bf8003 01d8f000 00000000 00000053
-t7		opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
+		opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
 0000000001d914dc:		0000: 70268000
-t4		write CP_SCRATCH[0x6].REG (0889)
+		write CP_SCRATCH[0x6].REG (0889)
 			CP_SCRATCH[0x6].REG: 12
 			:0,1,12,3
 0000000001d914e0:		0000: 48088901 0000000c
-t7		opcode: CP_SET_DRAW_STATE (43) (4 dwords)
+		opcode: CP_SET_DRAW_STATE (43) (4 dwords)
 			{ COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 }
 			{ ADDR_LO = 0 }
 			{ ADDR_HI = 0 }
 0000000001d914e8:		0000: 70438003 00040000 00000000 00000000
-t7		opcode: CP_EVENT_WRITE (46) (2 dwords)
+		opcode: CP_EVENT_WRITE (46) (2 dwords)
 			{ EVENT = UNK_2D }
 		event UNK_2D
 0000000001d914f8:		0000: 70460001 0000002d
-t7		opcode: CP_EVENT_WRITE (46) (2 dwords)
+		opcode: CP_EVENT_WRITE (46) (2 dwords)
 			{ EVENT = CACHE_INVALIDATE }
 		event CACHE_INVALIDATE
 0000000001d91500:		0000: 70460001 00000031
-t7		opcode: CP_EVENT_WRITE (46) (5 dwords)
+		opcode: CP_EVENT_WRITE (46) (5 dwords)
 			{ EVENT = RB_DONE_TS }
 			{ ADDR_0_LO = 0x1d90000 }
 			{ ADDR_0_HI = 0 }
 			{ 3 = 0x1 }
 		event RB_DONE_TS
 0000000001d91508:		0000: 70460004 00000016 01d90000 00000000 00000001
-t7		opcode: CP_WAIT_REG_MEM (3c) (7 dwords)
+		opcode: CP_WAIT_REG_MEM (3c) (7 dwords)
 			{ FUNCTION = WRITE_EQ | POLL_MEMORY }
 			{ POLL_ADDR_LO = 0x1d90000 }
 			{ POLL_ADDR_HI = 0 }
@@ -1192,30 +1192,30 @@ t7		opcode: CP_WAIT_REG_MEM (3c) (7 dwords)
 			{ MASK = 0xffffffff }
 			{ DELAY_LOOP_CYCLES = 0x10 }
 0000000001d9151c:		0000: 70bc8006 00000013 01d90000 00000000 00000001 ffffffff 00000010
-t7		opcode: CP_EVENT_WRITE (46) (5 dwords)
+		opcode: CP_EVENT_WRITE (46) (5 dwords)
 			{ EVENT = CACHE_FLUSH_TS }
 			{ ADDR_0_LO = 0x1d90000 }
 			{ ADDR_0_HI = 0 }
 			{ 3 = 0x2 }
 		event CACHE_FLUSH_TS
 0000000001d91538:		0000: 70460004 00000004 01d90000 00000000 00000002
-t7		opcode: CP_WAIT_MEM_GTE (14) (5 dwords)
+		opcode: CP_WAIT_MEM_GTE (14) (5 dwords)
 			{ RESERVED = 0 }
 			{ POLL_ADDR_LO = 0x1d90000 }
 			{ POLL_ADDR_HI = 0 }
 			{ REF = 0x2 }
 0000000001d9154c:		0000: 70940004 00000000 01d90000 00000000 00000002
-t7		opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
+		opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
 0000000001d91560:		0000: 70268000
-t7		opcode: CP_WAIT_FOR_ME (13) (1 dwords)
+		opcode: CP_WAIT_FOR_ME (13) (1 dwords)
 0000000001d91564:		0000: 70138000
-t7		opcode: CP_MEM_WRITE (3d) (4 dwords)
+		opcode: CP_MEM_WRITE (3d) (4 dwords)
 			{ ADDR_LO = 0x1d90010 }
 			{ ADDR_HI = 0 }
 		gpuaddr:0000000001d90010
 0000000001d91574:			0000: 00000000
 0000000001d91568:		0000: 703d8003 01d90010 00000000 00000000
-t7		opcode: CP_COND_WRITE5 (45) (9 dwords)
+		opcode: CP_COND_WRITE5 (45) (9 dwords)
 			{ FUNCTION = WRITE_GE | WRITE_MEMORY }
 			{ POLL_ADDR_LO = 0xc78 }
 			{ POLL_ADDR_HI = 0 }
@@ -1226,7 +1226,7 @@ t7		opcode: CP_COND_WRITE5 (45) (9 dwords)
 			{ WRITE_DATA = 0x441 }
 0000000001d91578:		0000: 70450008 00000105 00000c78 00000000 00000440 ffffffff 01d90010 00000000
 0000000001d91598:		0020: 00000441
-t7		opcode: CP_COND_WRITE5 (45) (9 dwords)
+		opcode: CP_COND_WRITE5 (45) (9 dwords)
 			{ FUNCTION = WRITE_GE | WRITE_MEMORY }
 			{ POLL_ADDR_LO = 0xc58 }
 			{ POLL_ADDR_HI = 0 }
@@ -1237,7 +1237,7 @@ t7		opcode: CP_COND_WRITE5 (45) (9 dwords)
 			{ WRITE_DATA = 0x1043 }
 0000000001d9159c:		0000: 70450008 00000105 00000c58 00000000 00001040 ffffffff 01d90010 00000000
 0000000001d915bc:		0020: 00001043
-t7		opcode: CP_COND_WRITE5 (45) (9 dwords)
+		opcode: CP_COND_WRITE5 (45) (9 dwords)
 			{ FUNCTION = WRITE_GE | WRITE_MEMORY }
 			{ POLL_ADDR_LO = 0xc79 }
 			{ POLL_ADDR_HI = 0 }
@@ -1248,7 +1248,7 @@ t7		opcode: CP_COND_WRITE5 (45) (9 dwords)
 			{ WRITE_DATA = 0x441 }
 0000000001d915c0:		0000: 70450008 00000105 00000c79 00000000 00000440 ffffffff 01d90010 00000000
 0000000001d915e0:		0020: 00000441
-t7		opcode: CP_COND_WRITE5 (45) (9 dwords)
+		opcode: CP_COND_WRITE5 (45) (9 dwords)
 			{ FUNCTION = WRITE_GE | WRITE_MEMORY }
 			{ POLL_ADDR_LO = 0xc59 }
 			{ POLL_ADDR_HI = 0 }
@@ -1259,7 +1259,7 @@ t7		opcode: CP_COND_WRITE5 (45) (9 dwords)
 			{ WRITE_DATA = 0x1043 }
 0000000001d915e4:		0000: 70450008 00000105 00000c59 00000000 00001040 ffffffff 01d90010 00000000
 0000000001d91604:		0020: 00001043
-t7		opcode: CP_COND_WRITE5 (45) (9 dwords)
+		opcode: CP_COND_WRITE5 (45) (9 dwords)
 			{ FUNCTION = WRITE_GE | WRITE_MEMORY }
 			{ POLL_ADDR_LO = 0xc7a }
 			{ POLL_ADDR_HI = 0 }
@@ -1270,7 +1270,7 @@ t7		opcode: CP_COND_WRITE5 (45) (9 dwords)
 			{ WRITE_DATA = 0x441 }
 0000000001d91608:		0000: 70450008 00000105 00000c7a 00000000 00000440 ffffffff 01d90010 00000000
 0000000001d91628:		0020: 00000441
-t7		opcode: CP_COND_WRITE5 (45) (9 dwords)
+		opcode: CP_COND_WRITE5 (45) (9 dwords)
 			{ FUNCTION = WRITE_GE | WRITE_MEMORY }
 			{ POLL_ADDR_LO = 0xc5a }
 			{ POLL_ADDR_HI = 0 }
@@ -1281,7 +1281,7 @@ t7		opcode: CP_COND_WRITE5 (45) (9 dwords)
 			{ WRITE_DATA = 0x1043 }
 0000000001d9162c:		0000: 70450008 00000105 00000c5a 00000000 00001040 ffffffff 01d90010 00000000
 0000000001d9164c:		0020: 00001043
-t7		opcode: CP_COND_WRITE5 (45) (9 dwords)
+		opcode: CP_COND_WRITE5 (45) (9 dwords)
 			{ FUNCTION = WRITE_GE | WRITE_MEMORY }
 			{ POLL_ADDR_LO = 0xc7b }
 			{ POLL_ADDR_HI = 0 }
@@ -1292,7 +1292,7 @@ t7		opcode: CP_COND_WRITE5 (45) (9 dwords)
 			{ WRITE_DATA = 0x441 }
 0000000001d91650:		0000: 70450008 00000105 00000c7b 00000000 00000440 ffffffff 01d90010 00000000
 0000000001d91670:		0020: 00000441
-t7		opcode: CP_COND_WRITE5 (45) (9 dwords)
+		opcode: CP_COND_WRITE5 (45) (9 dwords)
 			{ FUNCTION = WRITE_GE | WRITE_MEMORY }
 			{ POLL_ADDR_LO = 0xc5b }
 			{ POLL_ADDR_HI = 0 }
@@ -1303,7 +1303,7 @@ t7		opcode: CP_COND_WRITE5 (45) (9 dwords)
 			{ WRITE_DATA = 0x1043 }
 0000000001d91674:		0000: 70450008 00000105 00000c5b 00000000 00001040 ffffffff 01d90010 00000000
 0000000001d91694:		0020: 00001043
-t7		opcode: CP_COND_WRITE5 (45) (9 dwords)
+		opcode: CP_COND_WRITE5 (45) (9 dwords)
 			{ FUNCTION = WRITE_GE | WRITE_MEMORY }
 			{ POLL_ADDR_LO = 0xc7c }
 			{ POLL_ADDR_HI = 0 }
@@ -1314,7 +1314,7 @@ t7		opcode: CP_COND_WRITE5 (45) (9 dwords)
 			{ WRITE_DATA = 0x441 }
 0000000001d91698:		0000: 70450008 00000105 00000c7c 00000000 00000440 ffffffff 01d90010 00000000
 0000000001d916b8:		0020: 00000441
-t7		opcode: CP_COND_WRITE5 (45) (9 dwords)
+		opcode: CP_COND_WRITE5 (45) (9 dwords)
 			{ FUNCTION = WRITE_GE | WRITE_MEMORY }
 			{ POLL_ADDR_LO = 0xc5c }
 			{ POLL_ADDR_HI = 0 }
@@ -1325,7 +1325,7 @@ t7		opcode: CP_COND_WRITE5 (45) (9 dwords)
 			{ WRITE_DATA = 0x1043 }
 0000000001d916bc:		0000: 70450008 00000105 00000c5c 00000000 00001040 ffffffff 01d90010 00000000
 0000000001d916dc:		0020: 00001043
-t7		opcode: CP_COND_WRITE5 (45) (9 dwords)
+		opcode: CP_COND_WRITE5 (45) (9 dwords)
 			{ FUNCTION = WRITE_GE | WRITE_MEMORY }
 			{ POLL_ADDR_LO = 0xc7d }
 			{ POLL_ADDR_HI = 0 }
@@ -1336,7 +1336,7 @@ t7		opcode: CP_COND_WRITE5 (45) (9 dwords)
 			{ WRITE_DATA = 0x441 }
 0000000001d916e0:		0000: 70450008 00000105 00000c7d 00000000 00000440 ffffffff 01d90010 00000000
 0000000001d91700:		0020: 00000441
-t7		opcode: CP_COND_WRITE5 (45) (9 dwords)
+		opcode: CP_COND_WRITE5 (45) (9 dwords)
 			{ FUNCTION = WRITE_GE | WRITE_MEMORY }
 			{ POLL_ADDR_LO = 0xc5d }
 			{ POLL_ADDR_HI = 0 }
@@ -1347,7 +1347,7 @@ t7		opcode: CP_COND_WRITE5 (45) (9 dwords)
 			{ WRITE_DATA = 0x1043 }
 0000000001d91704:		0000: 70450008 00000105 00000c5d 00000000 00001040 ffffffff 01d90010 00000000
 0000000001d91724:		0020: 00001043
-t7		opcode: CP_COND_WRITE5 (45) (9 dwords)
+		opcode: CP_COND_WRITE5 (45) (9 dwords)
 			{ FUNCTION = WRITE_GE | WRITE_MEMORY }
 			{ POLL_ADDR_LO = 0xc7e }
 			{ POLL_ADDR_HI = 0 }
@@ -1358,7 +1358,7 @@ t7		opcode: CP_COND_WRITE5 (45) (9 dwords)
 			{ WRITE_DATA = 0x441 }
 0000000001d91728:		0000: 70450008 00000105 00000c7e 00000000 00000440 ffffffff 01d90010 00000000
 0000000001d91748:		0020: 00000441
-t7		opcode: CP_COND_WRITE5 (45) (9 dwords)
+		opcode: CP_COND_WRITE5 (45) (9 dwords)
 			{ FUNCTION = WRITE_GE | WRITE_MEMORY }
 			{ POLL_ADDR_LO = 0xc5e }
 			{ POLL_ADDR_HI = 0 }
@@ -1369,7 +1369,7 @@ t7		opcode: CP_COND_WRITE5 (45) (9 dwords)
 			{ WRITE_DATA = 0x1043 }
 0000000001d9174c:		0000: 70450008 00000105 00000c5e 00000000 00001040 ffffffff 01d90010 00000000
 0000000001d9176c:		0020: 00001043
-t7		opcode: CP_COND_WRITE5 (45) (9 dwords)
+		opcode: CP_COND_WRITE5 (45) (9 dwords)
 			{ FUNCTION = WRITE_GE | WRITE_MEMORY }
 			{ POLL_ADDR_LO = 0xc7f }
 			{ POLL_ADDR_HI = 0 }
@@ -1380,7 +1380,7 @@ t7		opcode: CP_COND_WRITE5 (45) (9 dwords)
 			{ WRITE_DATA = 0x441 }
 0000000001d91770:		0000: 70450008 00000105 00000c7f 00000000 00000440 ffffffff 01d90010 00000000
 0000000001d91790:		0020: 00000441
-t7		opcode: CP_COND_WRITE5 (45) (9 dwords)
+		opcode: CP_COND_WRITE5 (45) (9 dwords)
 			{ FUNCTION = WRITE_GE | WRITE_MEMORY }
 			{ POLL_ADDR_LO = 0xc5f }
 			{ POLL_ADDR_HI = 0 }
@@ -1391,7 +1391,7 @@ t7		opcode: CP_COND_WRITE5 (45) (9 dwords)
 			{ WRITE_DATA = 0x1043 }
 0000000001d91794:		0000: 70450008 00000105 00000c5f 00000000 00001040 ffffffff 01d90010 00000000
 0000000001d917b4:		0020: 00001043
-t7		opcode: CP_COND_WRITE5 (45) (9 dwords)
+		opcode: CP_COND_WRITE5 (45) (9 dwords)
 			{ FUNCTION = WRITE_GE | WRITE_MEMORY }
 			{ POLL_ADDR_LO = 0xc80 }
 			{ POLL_ADDR_HI = 0 }
@@ -1402,7 +1402,7 @@ t7		opcode: CP_COND_WRITE5 (45) (9 dwords)
 			{ WRITE_DATA = 0x441 }
 0000000001d917b8:		0000: 70450008 00000105 00000c80 00000000 00000440 ffffffff 01d90010 00000000
 0000000001d917d8:		0020: 00000441
-t7		opcode: CP_COND_WRITE5 (45) (9 dwords)
+		opcode: CP_COND_WRITE5 (45) (9 dwords)
 			{ FUNCTION = WRITE_GE | WRITE_MEMORY }
 			{ POLL_ADDR_LO = 0xc60 }
 			{ POLL_ADDR_HI = 0 }
@@ -1413,7 +1413,7 @@ t7		opcode: CP_COND_WRITE5 (45) (9 dwords)
 			{ WRITE_DATA = 0x1043 }
 0000000001d917dc:		0000: 70450008 00000105 00000c60 00000000 00001040 ffffffff 01d90010 00000000
 0000000001d917fc:		0020: 00001043
-t7		opcode: CP_COND_WRITE5 (45) (9 dwords)
+		opcode: CP_COND_WRITE5 (45) (9 dwords)
 			{ FUNCTION = WRITE_GE | WRITE_MEMORY }
 			{ POLL_ADDR_LO = 0xc81 }
 			{ POLL_ADDR_HI = 0 }
@@ -1424,7 +1424,7 @@ t7		opcode: CP_COND_WRITE5 (45) (9 dwords)
 			{ WRITE_DATA = 0x441 }
 0000000001d91800:		0000: 70450008 00000105 00000c81 00000000 00000440 ffffffff 01d90010 00000000
 0000000001d91820:		0020: 00000441
-t7		opcode: CP_COND_WRITE5 (45) (9 dwords)
+		opcode: CP_COND_WRITE5 (45) (9 dwords)
 			{ FUNCTION = WRITE_GE | WRITE_MEMORY }
 			{ POLL_ADDR_LO = 0xc61 }
 			{ POLL_ADDR_HI = 0 }
@@ -1435,7 +1435,7 @@ t7		opcode: CP_COND_WRITE5 (45) (9 dwords)
 			{ WRITE_DATA = 0x1043 }
 0000000001d91824:		0000: 70450008 00000105 00000c61 00000000 00001040 ffffffff 01d90010 00000000
 0000000001d91844:		0020: 00001043
-t7		opcode: CP_COND_WRITE5 (45) (9 dwords)
+		opcode: CP_COND_WRITE5 (45) (9 dwords)
 			{ FUNCTION = WRITE_GE | WRITE_MEMORY }
 			{ POLL_ADDR_LO = 0xc82 }
 			{ POLL_ADDR_HI = 0 }
@@ -1446,7 +1446,7 @@ t7		opcode: CP_COND_WRITE5 (45) (9 dwords)
 			{ WRITE_DATA = 0x441 }
 0000000001d91848:		0000: 70450008 00000105 00000c82 00000000 00000440 ffffffff 01d90010 00000000
 0000000001d91868:		0020: 00000441
-t7		opcode: CP_COND_WRITE5 (45) (9 dwords)
+		opcode: CP_COND_WRITE5 (45) (9 dwords)
 			{ FUNCTION = WRITE_GE | WRITE_MEMORY }
 			{ POLL_ADDR_LO = 0xc62 }
 			{ POLL_ADDR_HI = 0 }
@@ -1457,7 +1457,7 @@ t7		opcode: CP_COND_WRITE5 (45) (9 dwords)
 			{ WRITE_DATA = 0x1043 }
 0000000001d9186c:		0000: 70450008 00000105 00000c62 00000000 00001040 ffffffff 01d90010 00000000
 0000000001d9188c:		0020: 00001043
-t7		opcode: CP_COND_WRITE5 (45) (9 dwords)
+		opcode: CP_COND_WRITE5 (45) (9 dwords)
 			{ FUNCTION = WRITE_GE | WRITE_MEMORY }
 			{ POLL_ADDR_LO = 0xc83 }
 			{ POLL_ADDR_HI = 0 }
@@ -1468,7 +1468,7 @@ t7		opcode: CP_COND_WRITE5 (45) (9 dwords)
 			{ WRITE_DATA = 0x441 }
 0000000001d91890:		0000: 70450008 00000105 00000c83 00000000 00000440 ffffffff 01d90010 00000000
 0000000001d918b0:		0020: 00000441
-t7		opcode: CP_COND_WRITE5 (45) (9 dwords)
+		opcode: CP_COND_WRITE5 (45) (9 dwords)
 			{ FUNCTION = WRITE_GE | WRITE_MEMORY }
 			{ POLL_ADDR_LO = 0xc63 }
 			{ POLL_ADDR_HI = 0 }
@@ -1479,107 +1479,107 @@ t7		opcode: CP_COND_WRITE5 (45) (9 dwords)
 			{ WRITE_DATA = 0x1043 }
 0000000001d918b4:		0000: 70450008 00000105 00000c63 00000000 00001040 ffffffff 01d90010 00000000
 0000000001d918d4:		0020: 00001043
-t7		opcode: CP_WAIT_MEM_WRITES (12) (1 dwords)
+		opcode: CP_WAIT_MEM_WRITES (12) (1 dwords)
 0000000001d918d8:		0000: 70928000
-t7		opcode: CP_WAIT_FOR_ME (13) (1 dwords)
+		opcode: CP_WAIT_FOR_ME (13) (1 dwords)
 0000000001d918dc:		0000: 70138000
-t7		opcode: CP_MEM_TO_REG (42) (4 dwords)
+		opcode: CP_MEM_TO_REG (42) (4 dwords)
 			{ REG = 0x883 | CNT = 0 }
 			{ SRC = 0x1d90010 }
 			{ SRC_HI = 0 }
 		base register: CP_SCRATCH[0].REG
 		gpuaddr:0000000001d90010
 0000000001d918e0:		0000: 70c28003 00000883 01d90010 00000000
-t7		opcode: CP_REG_TEST (39) (2 dwords)
+		opcode: CP_REG_TEST (39) (2 dwords)
 			{ REG = 0x883 | BIT = 0 | WAIT_FOR_ME }
 0000000001d918f0:		0000: 70b90001 02000883
-t7		opcode: CP_COND_REG_EXEC (47) (3 dwords)
+		opcode: CP_COND_REG_EXEC (47) (3 dwords)
 			{ REG0 = 0 | MODE = PRED_TEST }
 			{ DWORDS = 7 }
 0000000001d918f8:		0000: 70c70002 10000000 00000007
-t7		opcode: CP_REG_TO_MEM (3e) (4 dwords)
+		opcode: CP_REG_TO_MEM (3e) (4 dwords)
 			{ REG = 0x883 | CNT = 0 }
 			{ DEST = 0x1d90008 }
 			{ DEST_HI = 0 }
 		base register: CP_SCRATCH[0].REG
 		gpuaddr:0000000001d90008
 0000000001d91904:		0000: 703e8003 00000883 01d90008 00000000
-t4		write CP_SCRATCH[0].REG (0883)
+		write CP_SCRATCH[0].REG (0883)
 			CP_SCRATCH[0].REG: 0
 0000000001d91914:		0000: 48088301 00000000
-t7		opcode: CP_NOP (10) (3 dwords)
+		opcode: CP_NOP (10) (3 dwords)
 0000000001d9191c:		0000: 70100002 48088301 00000001
-t7		opcode: CP_SET_VISIBILITY_OVERRIDE (64) (2 dwords)
+		opcode: CP_SET_VISIBILITY_OVERRIDE (64) (2 dwords)
 0000000001d91928:		0000: 70640001 00000000
-t7		opcode: CP_SET_MODE (63) (2 dwords)
+		opcode: CP_SET_MODE (63) (2 dwords)
 0000000001d91930:		0000: 70e30001 00000000
-t7		opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
+		opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
 0000000001d91938:		0000: 70268000
-t4		write RB_CCU_CNTL (8e07)
+		write RB_CCU_CNTL (8e07)
 			RB_CCU_CNTL: { COLOR_OFFSET = 0xf8000 | DEPTH_OFFSET = 0 | GMEM | CONCURRENT_RESOLVE }
 0000000001d9193c:		0000: 408e0701 7c400004
-t4		write VPC_SO_DISABLE (9306)
+		write VPC_SO_DISABLE (9306)
 			VPC_SO_DISABLE: { DISABLE }
 0000000001d91944:		0000: 48930601 00000001
-t4		write GRAS_BIN_CONTROL (80a1)
+		write GRAS_BIN_CONTROL (80a1)
 			GRAS_BIN_CONTROL: { BINW = 544 | BINH = 480 | RENDER_MODE = RENDERING_PASS | FORCE_LRZ_WRITE_DIS | BUFFERS_LOCATION = BUFFERS_IN_GMEM | LRZ_FEEDBACK_ZMODE_MASK = 0x6 }
 0000000001d9194c:		0000: 4880a101 06201e11
-t4		write RB_BIN_CONTROL (8800)
+		write RB_BIN_CONTROL (8800)
 			RB_BIN_CONTROL: { BINW = 544 | BINH = 480 | RENDER_MODE = RENDERING_PASS | FORCE_LRZ_WRITE_DIS | BUFFERS_LOCATION = BUFFERS_IN_GMEM | LRZ_FEEDBACK_ZMODE_MASK = 0x6 }
 0000000001d91954:		0000: 48880001 06201e11
-t4		write RB_BIN_CONTROL2 (88d3)
+		write RB_BIN_CONTROL2 (88d3)
 			RB_BIN_CONTROL2: { BINW = 544 | BINH = 480 }
 0000000001d9195c:		0000: 4088d301 00001e11
-t4		write VFD_MODE_CNTL (a007)
+		write VFD_MODE_CNTL (a007)
 			VFD_MODE_CNTL: { RENDER_MODE = RENDERING_PASS }
 0000000001d91964:		0000: 40a00701 00000000
-t4		write PC_POWER_CNTL (9805)
+		write PC_POWER_CNTL (9805)
 			PC_POWER_CNTL: 0x1
 0000000001d9196c:		0000: 40980501 00000001
-t4		write VFD_POWER_CNTL (a0f8)
+		write VFD_POWER_CNTL (a0f8)
 			VFD_POWER_CNTL: 0x1
 0000000001d91974:		0000: 40a0f801 00000001
-t7		opcode: CP_SKIP_IB2_ENABLE_GLOBAL (1d) (2 dwords)
+		opcode: CP_SKIP_IB2_ENABLE_GLOBAL (1d) (2 dwords)
 0000000001d9197c:		0000: 709d0001 00000001
-t7		opcode: CP_REG_WRITE (6d) (4 dwords)
+		opcode: CP_REG_WRITE (6d) (4 dwords)
 			{ TRACKER = TRACK_RENDER_CNTL }
 			RB_RENDER_CNTL: { CCUSINGLECACHELINESIZE = 0x2 | RASTER_MODE = TYPE_TILED | RASTER_DIRECTION = LR_TB | FLAG_MRTS = 0 }
 0000000001d91984:		0000: 706d8003 00000002 00008801 00000010
-t7		opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
+		opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
 0000000001d91994:		0000: 70268000
-t4		write CP_SCRATCH[0x7].REG (088a)
+		write CP_SCRATCH[0x7].REG (088a)
 			CP_SCRATCH[0x7].REG: 13
 			:0,1,12,13
 0000000001d91998:		0000: 48088a01 0000000d
-t7		opcode: CP_SET_MARKER (65) (2 dwords)
+		opcode: CP_SET_MARKER (65) (2 dwords)
 			{ MODE = 0x14 | MARKER = RM6_GMEM }
 0000000001d919a0:		0000: 70e50001 00000014
-t7		opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
+		opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
 0000000001d919a8:		0000: 70268000
-t4		write CP_SCRATCH[0x7].REG (088a)
+		write CP_SCRATCH[0x7].REG (088a)
 			CP_SCRATCH[0x7].REG: 14
 			:0,1,12,14
 0000000001d919ac:		0000: 48088a01 0000000e
-t4		write GRAS_SC_WINDOW_SCISSOR_TL (80f0)
+		write GRAS_SC_WINDOW_SCISSOR_TL (80f0)
 			GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
 			GRAS_SC_WINDOW_SCISSOR_BR: { X = 543 | Y = 479 }
 0000000001d919b4:		0000: 4080f002 00000000 01df021f
-t4		write GRAS_2D_RESOLVE_CNTL_1 (840a)
+		write GRAS_2D_RESOLVE_CNTL_1 (840a)
 			GRAS_2D_RESOLVE_CNTL_1: { X = 0 | Y = 0 }
 			GRAS_2D_RESOLVE_CNTL_2: { X = 543 | Y = 479 }
 0000000001d919c0:		0000: 48840a02 00000000 01df021f
-t7		opcode: CP_WAIT_FOR_ME (13) (1 dwords)
+		opcode: CP_WAIT_FOR_ME (13) (1 dwords)
 0000000001d919cc:		0000: 70138000
-t7		opcode: CP_SET_MODE (63) (2 dwords)
+		opcode: CP_SET_MODE (63) (2 dwords)
 0000000001d919d0:		0000: 70e30001 00000000
-t7		opcode: CP_REG_TEST (39) (2 dwords)
+		opcode: CP_REG_TEST (39) (2 dwords)
 			{ REG = 0x883 | BIT = 0 | WAIT_FOR_ME }
 0000000001d919d8:		0000: 70b90001 02000883
-t7		opcode: CP_COND_REG_EXEC (47) (3 dwords)
+		opcode: CP_COND_REG_EXEC (47) (3 dwords)
 			{ REG0 = 0 | MODE = PRED_TEST }
 			{ DWORDS = 11 }
 0000000001d919e0:		0000: 70c70002 10000000 0000000b
-t7		opcode: CP_SET_BIN_DATA5 (2f) (8 dwords)
+		opcode: CP_SET_BIN_DATA5 (2f) (8 dwords)
 			{ VSC_SIZE = 1 | VSC_N = 0 }
 			{ BIN_DATA_ADDR_LO = 0x1d5d000 }
 			{ BIN_DATA_ADDR_HI = 0 }
@@ -1588,80 +1588,80 @@ t7		opcode: CP_SET_BIN_DATA5 (2f) (8 dwords)
 			{ BIN_PRIM_STRM_LO = 0x1d67000 }
 			{ BIN_PRIM_STRM_HI = 0 }
 0000000001d919ec:		0000: 702f0007 00010000 01d5d000 00000000 01d65800 00000000 01d67000 00000000
-t7		opcode: CP_SET_VISIBILITY_OVERRIDE (64) (2 dwords)
+		opcode: CP_SET_VISIBILITY_OVERRIDE (64) (2 dwords)
 0000000001d91a0c:		0000: 70640001 00000000
-t7		opcode: CP_NOP (10) (3 dwords)
+		opcode: CP_NOP (10) (3 dwords)
 0000000001d91a14:		0000: 70100002 70640001 00000001
-t4		write RB_WINDOW_OFFSET (8890)
+		write RB_WINDOW_OFFSET (8890)
 			RB_WINDOW_OFFSET: { X = 0 | Y = 0 }
 0000000001d91a20:		0000: 48889001 00000000
-t4		write RB_WINDOW_OFFSET2 (88d4)
+		write RB_WINDOW_OFFSET2 (88d4)
 			RB_WINDOW_OFFSET2: { X = 0 | Y = 0 }
 0000000001d91a28:		0000: 4888d401 00000000
-t4		write SP_WINDOW_OFFSET (b4d1)
+		write SP_WINDOW_OFFSET (b4d1)
 			SP_WINDOW_OFFSET: { X = 0 | Y = 0 }
 0000000001d91a30:		0000: 48b4d101 00000000
-t4		write SP_TP_WINDOW_OFFSET (b307)
+		write SP_TP_WINDOW_OFFSET (b307)
 			SP_TP_WINDOW_OFFSET: { X = 0 | Y = 0 }
 0000000001d91a38:		0000: 48b30701 00000000
-t4		write GRAS_BIN_CONTROL (80a1)
+		write GRAS_BIN_CONTROL (80a1)
 			GRAS_BIN_CONTROL: { BINW = 544 | BINH = 480 | RENDER_MODE = RENDERING_PASS | BUFFERS_LOCATION = BUFFERS_IN_GMEM | LRZ_FEEDBACK_ZMODE_MASK = 0x6 }
 0000000001d91a40:		0000: 4880a101 06001e11
-t4		write RB_BIN_CONTROL (8800)
+		write RB_BIN_CONTROL (8800)
 			RB_BIN_CONTROL: { BINW = 544 | BINH = 480 | RENDER_MODE = RENDERING_PASS | BUFFERS_LOCATION = BUFFERS_IN_GMEM | LRZ_FEEDBACK_ZMODE_MASK = 0x6 }
 0000000001d91a48:		0000: 48880001 06001e11
-t4		write RB_BIN_CONTROL2 (88d3)
+		write RB_BIN_CONTROL2 (88d3)
 			RB_BIN_CONTROL2: { BINW = 544 | BINH = 480 }
 0000000001d91a50:		0000: 4088d301 00001e11
-t7		opcode: CP_SET_MODE (63) (2 dwords)
+		opcode: CP_SET_MODE (63) (2 dwords)
 0000000001d91a58:		0000: 70e30001 00000000
-t4		write RB_SAMPLE_CONFIG (8804)
+		write RB_SAMPLE_CONFIG (8804)
 			RB_SAMPLE_CONFIG: { 0 }
 0000000001d91a60:		0000: 40880401 00000000
-t4		write SP_TP_SAMPLE_CONFIG (b304)
+		write SP_TP_SAMPLE_CONFIG (b304)
 			SP_TP_SAMPLE_CONFIG: { 0 }
 0000000001d91a68:		0000: 48b30401 00000000
-t4		write GRAS_SAMPLE_CONFIG (80a4)
+		write GRAS_SAMPLE_CONFIG (80a4)
 			GRAS_SAMPLE_CONFIG: { 0 }
 0000000001d91a70:		0000: 4880a401 00000000
-t7		opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
+		opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
 0000000001d91a78:		0000: 70268000
-t4		write CP_SCRATCH[0x6].REG (0889)
+		write CP_SCRATCH[0x6].REG (0889)
 			CP_SCRATCH[0x6].REG: 15
 			:0,1,15,14
 0000000001d91a7c:		0000: 48088901 0000000f
-t7		opcode: CP_INDIRECT_BUFFER (3f) (4 dwords)
+		opcode: CP_INDIRECT_BUFFER (3f) (4 dwords)
 		ibaddr:00000000011160d0
 		ibsize:00000018
-t4			write RB_BLIT_SCISSOR_TL (88d1)
+			write RB_BLIT_SCISSOR_TL (88d1)
 				RB_BLIT_SCISSOR_TL: { X = 0 | Y = 0 }
 				RB_BLIT_SCISSOR_BR: { X = 2175 | Y = 1439 }
 00000000011160d0:			0000: 4888d102 00000000 059f087f
-t4			write RB_BLIT_DST_INFO (88d7)
+			write RB_BLIT_DST_INFO (88d7)
 				RB_BLIT_DST_INFO: { TILE_MODE = TILE6_LINEAR | SAMPLES = MSAA_ONE | COLOR_SWAP = WZYX | COLOR_FORMAT = FMT6_8_8_8_X8_UNORM }
 00000000011160dc:			0000: 4888d701 00001880
-t4			write RB_BLIT_INFO (88e3)
+			write RB_BLIT_INFO (88e3)
 				RB_BLIT_INFO: { GMEM | CLEAR_MASK = 0xf | LAST = 0 | BUFFER_ID = 0 }
 00000000011160e4:			0000: 4088e301 000000f2
-t4			write RB_BLIT_BASE_GMEM (88d6)
+			write RB_BLIT_BASE_GMEM (88d6)
 				RB_BLIT_BASE_GMEM: 0
 00000000011160ec:			0000: 4088d601 00000000
-t4			write RB_UNKNOWN_88D0 (88d0)
+			write RB_UNKNOWN_88D0 (88d0)
 				RB_UNKNOWN_88D0: { 0 }
 00000000011160f4:			0000: 4088d001 00000000
-t4			write RB_BLIT_CLEAR_COLOR_DW0 (88df)
+			write RB_BLIT_CLEAR_COLOR_DW0 (88df)
 				RB_BLIT_CLEAR_COLOR_DW0: 0
 				RB_BLIT_CLEAR_COLOR_DW1: 0
 				RB_BLIT_CLEAR_COLOR_DW2: 0
 				RB_BLIT_CLEAR_COLOR_DW3: 0
 00000000011160fc:			0000: 4088df04 00000000 00000000 00000000 00000000
-t7			opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
 0000000001116110:			0000: 70268000
-t4			write CP_SCRATCH[0x7].REG (088a)
+			write CP_SCRATCH[0x7].REG (088a)
 				CP_SCRATCH[0x7].REG: 5
 				:0,1,15,5
 0000000001116114:			0000: 48088a01 00000005
-t7			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = BLIT }
 			event BLIT
 			mode: RM6_GMEM
@@ -1703,58 +1703,58 @@ t7			opcode: CP_EVENT_WRITE (46) (2 dwords)
  +	00000000			SP_TP_WINDOW_OFFSET: { X = 0 | Y = 0 }
  +	00000000			SP_WINDOW_OFFSET: { X = 0 | Y = 0 }
 000000000111611c:			0000: 70460001 0000001e
-t7			opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
 0000000001116124:			0000: 70268000
-t4			write CP_SCRATCH[0x7].REG (088a)
+			write CP_SCRATCH[0x7].REG (088a)
 				CP_SCRATCH[0x7].REG: 6
 				:0,1,15,6
 0000000001116128:			0000: 48088a01 00000006
 0000000001d91a84:		0000: 70bf8003 011160d0 00000000 00000018
-t7		opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
+		opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
 0000000001d91a94:		0000: 70268000
-t4		write CP_SCRATCH[0x6].REG (0889)
+		write CP_SCRATCH[0x6].REG (0889)
 			CP_SCRATCH[0x6].REG: 16
 			:0,1,16,6
 0000000001d91a98:		0000: 48088901 00000010
-t7		opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
+		opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
 0000000001d91aa0:		0000: 70268000
-t4		write CP_SCRATCH[0x6].REG (0889)
+		write CP_SCRATCH[0x6].REG (0889)
 			CP_SCRATCH[0x6].REG: 17
 			:0,1,17,6
 0000000001d91aa4:		0000: 48088901 00000011
-t7		opcode: CP_REG_TEST (39) (2 dwords)
+		opcode: CP_REG_TEST (39) (2 dwords)
 			{ REG = 0xc38 | BIT = 0 | WAIT_FOR_ME }
 0000000001d91aac:		0000: 70b90001 02000c38
-t7		opcode: CP_COND_REG_EXEC (47) (3 dwords)
+		opcode: CP_COND_REG_EXEC (47) (3 dwords)
 			{ REG0 = 0 | MODE = PRED_TEST }
 			{ DWORDS = 4 }
 0000000001d91ab4:		0000: 70c70002 10000000 00000004
-t7		opcode: CP_INDIRECT_BUFFER (3f) (4 dwords)
+		opcode: CP_INDIRECT_BUFFER (3f) (4 dwords)
 		ibaddr:0000000001d8f000
 		ibsize:00000053
-t4			write VFD_INDEX_OFFSET (a00e)
+			write VFD_INDEX_OFFSET (a00e)
 				VFD_INDEX_OFFSET: 0
 0000000001d8f000:			0000: 40a00e01 00000000
-t4			write VFD_INSTANCE_START_OFFSET (a00f)
+			write VFD_INSTANCE_START_OFFSET (a00f)
 				VFD_INSTANCE_START_OFFSET: 0
 0000000001d8f008:			0000: 48a00f01 00000000
-t4			write PC_RESTART_INDEX (9803)
+			write PC_RESTART_INDEX (9803)
 				PC_RESTART_INDEX: 4294967295
 0000000001d8f010:			0000: 40980301 ffffffff
-t7			opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
 0000000001d8f018:			0000: 70268000
-t4			write CP_SCRATCH[0x5].REG (0888)
+			write CP_SCRATCH[0x5].REG (0888)
 				CP_SCRATCH[0x5].REG: 1
 				:0,1,17,6
 0000000001d8f01c:			0000: 40088801 00000001
-t4			write RB_STENCILREF (8887)
+			write RB_STENCILREF (8887)
 				RB_STENCILREF: { REF = 0 | BFREF = 0 }
 0000000001d8f024:			0000: 48888701 00000000
-t4			write GRAS_SC_SCREEN_SCISSOR[0].TL (80b0)
+			write GRAS_SC_SCREEN_SCISSOR[0].TL (80b0)
 				GRAS_SC_SCREEN_SCISSOR[0].TL: { X = 0 | Y = 0 }
 				GRAS_SC_SCREEN_SCISSOR[0].BR: { X = 2159 | Y = 1439 }
 0000000001d8f02c:			0000: 4880b002 00000000 059f086f
-t4			write GRAS_CL_VPORT[0].XOFFSET (8010)
+			write GRAS_CL_VPORT[0].XOFFSET (8010)
 				GRAS_CL_VPORT[0].XOFFSET: 1080.000000
 				GRAS_CL_VPORT[0].XSCALE: 1080.000000
 				GRAS_CL_VPORT[0].YOFFSET: 720.000000
@@ -1762,23 +1762,23 @@ t4			write GRAS_CL_VPORT[0].XOFFSET (8010)
 				GRAS_CL_VPORT[0].ZOFFSET: 0.500000
 				GRAS_CL_VPORT[0].ZSCALE: 0.500000
 0000000001d8f038:			0000: 48801086 44870000 44870000 44340000 44340000 3f000000 3f000000
-t4			write GRAS_SC_VIEWPORT_SCISSOR[0].TL (80d0)
+			write GRAS_SC_VIEWPORT_SCISSOR[0].TL (80d0)
 				GRAS_SC_VIEWPORT_SCISSOR[0].TL: { X = 0 | Y = 0 }
 				GRAS_SC_VIEWPORT_SCISSOR[0].BR: { X = 2159 | Y = 1439 }
 0000000001d8f054:			0000: 4880d002 00000000 059f086f
-t4			write GRAS_CL_GUARDBAND_CLIP_ADJ (8006)
+			write GRAS_CL_GUARDBAND_CLIP_ADJ (8006)
 				GRAS_CL_GUARDBAND_CLIP_ADJ: { HORZ = 311 | VERT = 349 }
 0000000001d8f060:			0000: 40800601 00057537
-t4			write RB_BLEND_CNTL (8865)
+			write RB_BLEND_CNTL (8865)
 				RB_BLEND_CNTL: { ENABLE_BLEND = 0 | SAMPLE_MASK = 0xffff }
 0000000001d8f068:			0000: 48886501 ffff0000
-t4			write RB_BLEND_RED_F32 (8860)
+			write RB_BLEND_RED_F32 (8860)
 				RB_BLEND_RED_F32: 0.000000
 				RB_BLEND_GREEN_F32: 0.000000
 				RB_BLEND_BLUE_F32: 0.000000
 				RB_BLEND_ALPHA_F32: 0.000000
 0000000001d8f070:			0000: 48886004 00000000 00000000 00000000 00000000
-t7			opcode: CP_SET_DRAW_STATE (43) (40 dwords)
+			opcode: CP_SET_DRAW_STATE (43) (40 dwords)
 				{ COUNT = 12 | BINNING | GMEM | SYSMEM | GROUP_ID = 7 }
 				{ ADDR_LO = 0x1116000 }
 				{ ADDR_HI = 0 }
@@ -1823,9 +1823,9 @@ t7			opcode: CP_SET_DRAW_STATE (43) (40 dwords)
 0000000001d8f0c4:			0040: 03600012 01122000 00000000 1570000e 01123000 00000000 04600005 01116030
 0000000001d8f0e4:			0060: 00000000 08720000 00000000 00000000 0c600014 01116050 00000000 0d720000
 0000000001d8f104:			0080: 00000000 00000000 17600024 01124000 00000000 14600009 011160a0 00000000
-t7			opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
 0000000001d8f124:			0000: 70268000
-t4			write CP_SCRATCH[0x7].REG (088a)
+			write CP_SCRATCH[0x7].REG (088a)
 				CP_SCRATCH[0x7].REG: 2
 				:0,1,17,2
 0000000001d8f128:			0000: 48088a01 00000002
@@ -1837,34 +1837,34 @@ t4			write CP_SCRATCH[0x7].REG (088a)
 000000000111f000:				0000: 40bb0801 000000ff 48b80004 00000100 00000000 00000000 00000000 40bb1001
 000000000111f020:				0020: 00000108 48a82301 00000100 48a83b01 00000000 40a86301 00000000 48a89401
 000000000111f040:				0040: 00000000 48ab0401 00000100 48ab2001 00000000
-t4					write HLSQ_INVALIDATE_CMD (bb08)
+					write HLSQ_INVALIDATE_CMD (bb08)
 						HLSQ_INVALIDATE_CMD: { VS_STATE | HS_STATE | DS_STATE | GS_STATE | FS_STATE | CS_STATE | CS_IBO | GFX_IBO | CS_BINDLESS = 0 | GFX_BINDLESS = 0 }
 000000000111f000:					0000: 40bb0801 000000ff
-t4					write HLSQ_VS_CNTL (b800)
+					write HLSQ_VS_CNTL (b800)
 						HLSQ_VS_CNTL: { CONSTLEN = 0 | ENABLED }
 						HLSQ_HS_CNTL: { CONSTLEN = 0 }
 						HLSQ_DS_CNTL: { CONSTLEN = 0 }
 						HLSQ_GS_CNTL: { CONSTLEN = 0 }
 000000000111f008:					0000: 48b80004 00000100 00000000 00000000 00000000
-t4					write HLSQ_FS_CNTL (bb10)
+					write HLSQ_FS_CNTL (bb10)
 						HLSQ_FS_CNTL: { CONSTLEN = 32 | ENABLED }
 000000000111f01c:					0000: 40bb1001 00000108
-t4					write SP_VS_CONFIG (a823)
+					write SP_VS_CONFIG (a823)
 						SP_VS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 }
 000000000111f024:					0000: 48a82301 00000100
-t4					write SP_HS_CONFIG (a83b)
+					write SP_HS_CONFIG (a83b)
 						SP_HS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 }
 000000000111f02c:					0000: 48a83b01 00000000
-t4					write SP_DS_CONFIG (a863)
+					write SP_DS_CONFIG (a863)
 						SP_DS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 }
 000000000111f034:					0000: 40a86301 00000000
-t4					write SP_GS_CONFIG (a894)
+					write SP_GS_CONFIG (a894)
 						SP_GS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 }
 000000000111f03c:					0000: 48a89401 00000000
-t4					write SP_FS_CONFIG (ab04)
+					write SP_FS_CONFIG (ab04)
 						SP_FS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 }
 000000000111f044:					0000: 48ab0401 00000100
-t4					write SP_IBO_COUNT (ab20)
+					write SP_IBO_COUNT (ab20)
 						SP_IBO_COUNT: 0
 000000000111f04c:					0000: 48ab2001 00000000
 			group_id: 1
@@ -1896,28 +1896,28 @@ t4					write SP_IBO_COUNT (ab20)
 00000000011202a0:				02a0: 3dd70a3e 3d3851ec 40d9999a 3d4ac083 3ba3d70a 3de147ae 358637bd 33d6bf95
 00000000011202c0:				02c0: 3f0ccccd 41800000 45070000 44b40000 3df5c28f 3f333333 3f266666 3f7851ec
 00000000011202e0:				02e0: 3f19999a 3f666666 3f7d70a4 40100000 00000000 3db851ec 00000000 07ee25f4
-t4					write SP_HS_OBJ_FIRST_EXEC_OFFSET (a833)
+					write SP_HS_OBJ_FIRST_EXEC_OFFSET (a833)
 						SP_HS_OBJ_FIRST_EXEC_OFFSET: 0
 0000000001120000:					0000: 40a83301 00000000
-t4					write SP_FS_PREFETCH_CNTL (a99e)
+					write SP_FS_PREFETCH_CNTL (a99e)
 						SP_FS_PREFETCH_CNTL: { COUNT = 0 | UNK6 = 0x1ff }
 0000000001120008:					0000: 40a99e01 00007fc0
-t4					write SP_UNKNOWN_A9A8 (a9a8)
+					write SP_UNKNOWN_A9A8 (a9a8)
 						SP_UNKNOWN_A9A8: 0
 0000000001120010:					0000: 40a9a801 00000000
-t4					write SP_MODE_CONTROL (ab00)
+					write SP_MODE_CONTROL (ab00)
 						SP_MODE_CONTROL: { CONSTANT_DEMOTION_ENABLE | ISAMMODE = ISAMMODE_GL }
 0000000001120018:					0000: 40ab0001 00000005
-t4					write SP_FS_OUTPUT_CNTL0 (a98c)
+					write SP_FS_OUTPUT_CNTL0 (a98c)
 						SP_FS_OUTPUT_CNTL0: { DEPTH_REGID = r63.x | SAMPMASK_REGID = r63.x | STENCILREF_REGID = r63.x }
 0000000001120020:					0000: 40a98c01 fcfcfc00
-t4					write SP_VS_CTRL_REG0 (a800)
+					write SP_VS_CTRL_REG0 (a800)
 						SP_VS_CTRL_REG0: { MERGEDREGS | THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | BRANCHSTACK = 0 | 0x80000000 }
 0000000001120028:					0000: 40a80001 80100080
-t4					write SP_VS_INSTRLEN (a824)
+					write SP_VS_INSTRLEN (a824)
 						SP_VS_INSTRLEN: 1
 0000000001120030:					0000: 40a82401 00000001
-t4					write SP_VS_OBJ_START (a81c)
+					write SP_VS_OBJ_START (a81c)
 						SP_VS_OBJ_START: 0x1012000		base=1012000, offset=0, size=128
 0000000001012000:							0000: 00000000 03000000 00000000 00000000 00000000 00000000 00000000 00000000
 *
@@ -1933,7 +1933,7 @@ t4					write SP_VS_OBJ_START (a81c)
 							- shaderdb: 0 sstall, 0 (ss), 0 (sy)
 						SP_VS_OBJ_START_HI: 0
 0000000001120038:					0000: 48a81c02 01012000 00000000
-t7					opcode: CP_LOAD_STATE6_GEOM (32) (4 dwords)
+					opcode: CP_LOAD_STATE6_GEOM (32) (4 dwords)
 						{ DST_OFF = 0 | STATE_TYPE = ST6_SHADER | STATE_SRC = SS6_INDIRECT | STATE_BLOCK = SB6_VS_SHADER | NUM_UNIT = 1 }
 						{ EXT_SRC_ADDR = 0x1012000 }
 						{ EXT_SRC_ADDR_HI = 0 }
@@ -1948,69 +1948,69 @@ t7					opcode: CP_LOAD_STATE6_GEOM (32) (4 dwords)
 						- shaderdb: 5 cat0, 0 cat1, 0 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7
 						- shaderdb: 0 sstall, 0 (ss), 0 (sy)
 0000000001120044:					0000: 70328003 00620000 01012000 00000000
-t4					write VPC_VAR[0].DISABLE (9212)
+					write VPC_VAR[0].DISABLE (9212)
 						VPC_VAR[0].DISABLE: 0xffffffff
 						VPC_VAR[0x1].DISABLE: 0xffffffff
 						VPC_VAR[0x2].DISABLE: 0xffffffff
 						VPC_VAR[0x3].DISABLE: 0xffffffff
 0000000001120054:					0000: 40921204 ffffffff ffffffff ffffffff ffffffff
-t4					write SP_VS_OUT[0].REG (a803)
+					write SP_VS_OUT[0].REG (a803)
 						SP_VS_OUT[0].REG: { A_REGID = r0.x | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 }
 0000000001120068:					0000: 40a80301 00000f00
-t4					write SP_VS_VPC_DST[0].REG (a813)
+					write SP_VS_VPC_DST[0].REG (a813)
 						SP_VS_VPC_DST[0].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 }
 0000000001120070:					0000: 48a81301 00000000
-t4					write SP_HS_WAVE_INPUT_SIZE (a831)
+					write SP_HS_WAVE_INPUT_SIZE (a831)
 						SP_HS_WAVE_INPUT_SIZE: 0
 0000000001120078:					0000: 48a83101 00000000
-t4					write SP_VS_PRIMITIVE_CNTL (a802)
+					write SP_VS_PRIMITIVE_CNTL (a802)
 						SP_VS_PRIMITIVE_CNTL: { OUT = 1 | FLAGS_REGID = r0.x }
 0000000001120080:					0000: 48a80201 00000001
-t4					write VPC_CNTL_0 (9304)
+					write VPC_CNTL_0 (9304)
 						VPC_CNTL_0: { NUMNONPOSVAR = 0 | PRIMIDLOC = 255 | VIEWIDLOC = 255 }
 0000000001120088:					0000: 40930401 ff00ff00
-t4					write PC_VS_OUT_CNTL (9b01)
+					write PC_VS_OUT_CNTL (9b01)
 						PC_VS_OUT_CNTL: { STRIDE_IN_VPC = 4 | CLIP_MASK = 0 }
 0000000001120090:					0000: 489b0101 00000004
-t4					write PC_HS_OUT_CNTL (9b03)
+					write PC_HS_OUT_CNTL (9b03)
 						PC_HS_OUT_CNTL: { STRIDE_IN_VPC = 0 | CLIP_MASK = 0 }
 0000000001120098:					0000: 409b0301 00000000
-t4					write HLSQ_CONTROL_1_REG (b982)
+					write HLSQ_CONTROL_1_REG (b982)
 						HLSQ_CONTROL_1_REG: 0x7
 						HLSQ_CONTROL_2_REG: { FACEREGID = r63.x | SAMPLEID = r63.x | SAMPLEMASK = r63.x | CENTERRHW = r63.x }
 						HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r63.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x }
 						HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | XYCOORDREGID = r4.w | ZWCOORDREGID = r5.y }
 						HLSQ_CONTROL_5_REG: { LINELENGTHREGID = r63.x | FOVEATIONQUALITYREGID = r0.x }
 00000000011200a0:					0000: 40b98285 00000007 fcfcfcfc fcfcfcfc 1513fcfc 000000fc
-t4					write HLSQ_FS_CNTL_0 (b980)
+					write HLSQ_FS_CNTL_0 (b980)
 						HLSQ_FS_CNTL_0: { THREADSIZE = THREAD128 }
 00000000011200b8:					0000: 48b98001 00000001
-t4					write SP_FS_CTRL_REG0 (a980)
+					write SP_FS_CTRL_REG0 (a980)
 						SP_FS_CTRL_REG0: { THREADSIZE = THREAD128 | VARYING | UNK24 | MERGEDREGS | THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 19 | BRANCHSTACK = 2 }
 00000000011200c0:					0000: 40a98001 81508980
-t4					write SP_FS_OBJ_FIRST_EXEC_OFFSET (a982)
+					write SP_FS_OBJ_FIRST_EXEC_OFFSET (a982)
 						SP_FS_OBJ_FIRST_EXEC_OFFSET: 0
 00000000011200c8:					0000: 48a98201 00000000
-t4					write VPC_VS_LAYER_CNTL (9104)
+					write VPC_VS_LAYER_CNTL (9104)
 						VPC_VS_LAYER_CNTL: { LAYERLOC = 255 | VIEWLOC = 255 }
 00000000011200d0:					0000: 48910401 0000ffff
-t4					write GRAS_CNTL (8005)
+					write GRAS_CNTL (8005)
 						GRAS_CNTL: { IJ_LINEAR_PIXEL | COORD_MASK = 0xf }
 00000000011200d8:					0000: 40800501 000003c8
-t4					write RB_RENDER_CONTROL0 (8809)
+					write RB_RENDER_CONTROL0 (8809)
 						RB_RENDER_CONTROL0: { IJ_LINEAR_PIXEL | COORD_MASK = 0xf }
 						RB_RENDER_CONTROL1: { FRAGCOORDSAMPLEMODE = FRAGCOORD_CENTER }
 00000000011200e0:					0000: 48880902 000003c8 00000000
-t4					write RB_SAMPLE_CNTL (8810)
+					write RB_SAMPLE_CNTL (8810)
 						RB_SAMPLE_CNTL: { 0 }
 00000000011200ec:					0000: 40881001 00000000
-t4					write GRAS_LRZ_PS_INPUT_CNTL (8101)
+					write GRAS_LRZ_PS_INPUT_CNTL (8101)
 						GRAS_LRZ_PS_INPUT_CNTL: { FRAGCOORDSAMPLEMODE = FRAGCOORD_CENTER }
 00000000011200f4:					0000: 40810101 00000000
-t4					write GRAS_SAMPLE_CNTL (8109)
+					write GRAS_SAMPLE_CNTL (8109)
 						GRAS_SAMPLE_CNTL: { 0 }
 00000000011200fc:					0000: 48810901 00000000
-t4					write SP_FS_OUTPUT[0].REG (a98e)
+					write SP_FS_OUTPUT[0].REG (a98e)
 						SP_FS_OUTPUT[0].REG: { REGID = r1.x }
 						SP_FS_OUTPUT[0x1].REG: { REGID = r1.x }
 						SP_FS_OUTPUT[0x2].REG: { REGID = r1.x }
@@ -2021,25 +2021,25 @@ t4					write SP_FS_OUTPUT[0].REG (a98e)
 						SP_FS_OUTPUT[0x7].REG: { REGID = r1.x }
 0000000001120104:					0000: 48a98e08 00000004 00000004 00000004 00000004 00000004 00000004 00000004
 0000000001120124:					0020: 00000004
-t4					write VPC_VS_PACK (9301)
+					write VPC_VS_PACK (9301)
 						VPC_VS_PACK: { STRIDE_IN_VPC = 4 | POSITIONLOC = 0 | PSIZELOC = 255 | EXTRAPOS = 0 }
 0000000001120128:					0000: 40930101 00ff0004
-t4					write PC_PRIMITIVE_CNTL_6 (9b06)
+					write PC_PRIMITIVE_CNTL_6 (9b06)
 						PC_PRIMITIVE_CNTL_6: { STRIDE_IN_VPC = 0 }
 0000000001120130:					0000: 409b0601 00000000
-t4					write SP_GS_PRIM_SIZE (a871)
+					write SP_GS_PRIM_SIZE (a871)
 						SP_GS_PRIM_SIZE: 0
 0000000001120138:					0000: 40a87101 00000000
-t4					write VPC_VS_CLIP_CNTL (9101)
+					write VPC_VS_CLIP_CNTL (9101)
 						VPC_VS_CLIP_CNTL: { CLIP_MASK = 0 | CLIP_DIST_03_LOC = 255 | CLIP_DIST_47_LOC = 255 }
 0000000001120140:					0000: 48910101 00ffff00
-t4					write VPC_UNKNOWN_9107 (9107)
+					write VPC_UNKNOWN_9107 (9107)
 						VPC_UNKNOWN_9107: { 0 }
 0000000001120148:					0000: 48910701 00000000
-t4					write SP_FS_INSTRLEN (ab05)
+					write SP_FS_INSTRLEN (ab05)
 						SP_FS_INSTRLEN: 88
 0000000001120150:					0000: 40ab0501 00000058
-t4					write SP_FS_OBJ_START (a983)
+					write SP_FS_OBJ_START (a983)
 						SP_FS_OBJ_START: 0x1013000		base=1013000, offset=0, size=11264
 0000000001013000:							0000: 40400000 204cc000 00000000 204cc006 3e99999a 204cc004 20080014 42700008
 0000000001013020:							0020: 10331003 6380000c 00000006 200cc00d 00041003 40700004 00000000 20244014
@@ -3466,7 +3466,7 @@ t4					write SP_FS_OBJ_START (a983)
 							- shaderdb: 1326 sstall, 140 (ss), 0 (sy)
 						SP_FS_OBJ_START_HI: 0
 0000000001120158:					0000: 40a98302 01013000 00000000
-t7					opcode: CP_LOAD_STATE6_FRAG (34) (4 dwords)
+					opcode: CP_LOAD_STATE6_FRAG (34) (4 dwords)
 						{ DST_OFF = 0 | STATE_TYPE = ST6_SHADER | STATE_SRC = SS6_INDIRECT | STATE_BLOCK = SB6_FS_SHADER | NUM_UNIT = 88 }
 						{ EXT_SRC_ADDR = 0x1013000 }
 						{ EXT_SRC_ADDR_HI = 0 }
@@ -4886,7 +4886,7 @@ t7					opcode: CP_LOAD_STATE6_FRAG (34) (4 dwords)
 						- shaderdb: 1120 cat0, 48 cat1, 551 cat2, 512 cat3, 183 cat4, 0 cat5, 0 cat6, 0 cat7
 						- shaderdb: 1326 sstall, 140 (ss), 0 (sy)
 0000000001120164:					0000: 70348003 16320000 01013000 00000000
-t4					write VFD_CONTROL_1 (a001)
+					write VFD_CONTROL_1 (a001)
 						VFD_CONTROL_1: { REGID4VTX = r63.x | REGID4INST = r63.x | REGID4PRIMID = r63.x | REGID4VIEWID = r63.x }
 						VFD_CONTROL_2: { REGID_HSRELPATCHID = r63.x | REGID_INVOCATIONID = r63.x }
 						VFD_CONTROL_3: { REGID_DSPRIMID = r63.x | REGID_DSRELPATCHID = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x }
@@ -4894,13 +4894,13 @@ t4					write VFD_CONTROL_1 (a001)
 						VFD_CONTROL_5: { REGID_GSHEADER = r63.x | UNK8 = r63.x }
 						VFD_CONTROL_6: { 0 }
 0000000001120174:					0000: 40a00186 fcfcfcfc 0000fcfc fcfcfcfc 000000fc 0000fcfc 00000000
-t4					write RB_DEPTH_PLANE_CNTL (8870)
+					write RB_DEPTH_PLANE_CNTL (8870)
 						RB_DEPTH_PLANE_CNTL: { Z_MODE = A6XX_EARLY_Z }
 0000000001120190:					0000: 40887001 00000000
-t4					write GRAS_SU_DEPTH_PLANE_CNTL (8094)
+					write GRAS_SU_DEPTH_PLANE_CNTL (8094)
 						GRAS_SU_DEPTH_PLANE_CNTL: { Z_MODE = A6XX_EARLY_Z }
 0000000001120198:					0000: 48809401 00000000
-t7					opcode: CP_LOAD_STATE6_FRAG (34) (88 dwords)
+					opcode: CP_LOAD_STATE6_FRAG (34) (88 dwords)
 						{ DST_OFF = 8 | STATE_TYPE = ST6_CONSTANTS | STATE_SRC = SS6_DIRECT | STATE_BLOCK = SB6_FS_SHADER | NUM_UNIT = 21 }
 						{ EXT_SRC_ADDR = 0 }
 						{ EXT_SRC_ADDR_HI = 0 }
@@ -4952,7 +4952,7 @@ t7					opcode: CP_LOAD_STATE6_FRAG (34) (88 dwords)
 0000000001122000:				0000: 40920008 00000000 00000000 00000000 00000000 00000000 00000000 00000000
 0000000001122020:				0020: 00000000 48920808 00000000 00000000 00000000 00000000 00000000 00000000
 *
-t4					write VPC_VARYING_INTERP[0].MODE (9200)
+					write VPC_VARYING_INTERP[0].MODE (9200)
 						VPC_VARYING_INTERP[0].MODE: 0
 						VPC_VARYING_INTERP[0x1].MODE: 0
 						VPC_VARYING_INTERP[0x2].MODE: 0
@@ -4963,7 +4963,7 @@ t4					write VPC_VARYING_INTERP[0].MODE (9200)
 						VPC_VARYING_INTERP[0x7].MODE: 0
 0000000001122000:					0000: 40920008 00000000 00000000 00000000 00000000 00000000 00000000 00000000
 *
-t4					write VPC_VARYING_PS_REPL[0].MODE (9208)
+					write VPC_VARYING_PS_REPL[0].MODE (9208)
 						VPC_VARYING_PS_REPL[0].MODE: 0
 						VPC_VARYING_PS_REPL[0x1].MODE: 0
 						VPC_VARYING_PS_REPL[0x2].MODE: 0
@@ -4980,11 +4980,11 @@ t4					write VPC_VARYING_PS_REPL[0].MODE (9208)
 			flags: 0
 			enable_mask: 0x6
 0000000001116030:				0000: 40880b02 00000000 00000001 48a98d01 00000001
-t4					write RB_FS_OUTPUT_CNTL0 (880b)
+					write RB_FS_OUTPUT_CNTL0 (880b)
 						RB_FS_OUTPUT_CNTL0: { 0 }
 						RB_FS_OUTPUT_CNTL1: { MRT = 1 }
 0000000001116030:					0000: 40880b02 00000000 00000001
-t4					write SP_FS_OUTPUT_CNTL1 (a98d)
+					write SP_FS_OUTPUT_CNTL1 (a98d)
 						SP_FS_OUTPUT_CNTL1: { MRT = 1 }
 000000000111603c:					0000: 48a98d01 00000001
 			group_id: 7
@@ -4994,20 +4994,20 @@ t4					write SP_FS_OUTPUT_CNTL1 (a98d)
 			enable_mask: 0x7
 0000000001116000:				0000: 40a01004 01016000 00000000 00100000 0000000c 48a09002 c7400000 00000001
 0000000001116020:				0020: 40a0d001 0000000f 48a00001 00000101
-t4					write VFD_FETCH[0].BASE (a010)
+					write VFD_FETCH[0].BASE (a010)
 						VFD_FETCH[0].BASE: 0x1016000
 						VFD_FETCH[0].BASE_HI: 0
 						VFD_FETCH[0].SIZE: 1048576
 						VFD_FETCH[0].STRIDE: 12
 0000000001116000:					0000: 40a01004 01016000 00000000 00100000 0000000c
-t4					write VFD_DECODE[0].INSTR (a090)
+					write VFD_DECODE[0].INSTR (a090)
 						VFD_DECODE[0].INSTR: { IDX = 0 | OFFSET = 0 | FORMAT = FMT6_32_32_32_FLOAT | SWAP = WZYX | UNK30 | FLOAT }
 						VFD_DECODE[0].STEP_RATE: 1
 0000000001116014:					0000: 48a09002 c7400000 00000001
-t4					write VFD_DEST_CNTL[0].INSTR (a0d0)
+					write VFD_DEST_CNTL[0].INSTR (a0d0)
 						VFD_DEST_CNTL[0].INSTR: { WRITEMASK = 0xf | REGID = r0.x }
 0000000001116020:					0000: 40a0d001 0000000f
-t4					write VFD_CONTROL_0 (a000)
+					write VFD_CONTROL_0 (a000)
 						VFD_CONTROL_0: { FETCH_CNT = 1 | DECODE_CNT = 1 }
 0000000001116028:					0000: 48a00001 00000101
 			group_id: 12
@@ -5018,7 +5018,7 @@ t4					write VFD_CONTROL_0 (a000)
 0000000001116050:				0000: 70340013 01304000 00000000 00000000 44800000 44400000 00000000 00000000
 0000000001116070:				0020: 00000000 00000000 00000000 00000000 3f800000 00000000 bf800000 44b40000
 0000000001116090:				0040: 07e56cc8 07dd3ebc 00000000 00000000
-t7					opcode: CP_LOAD_STATE6_FRAG (34) (20 dwords)
+					opcode: CP_LOAD_STATE6_FRAG (34) (20 dwords)
 						{ DST_OFF = 0 | STATE_TYPE = ST6_CONSTANTS | STATE_SRC = SS6_DIRECT | STATE_BLOCK = SB6_FS_SHADER | NUM_UNIT = 4 }
 						{ EXT_SRC_ADDR = 0 }
 						{ EXT_SRC_ADDR_HI = 0 }
@@ -5036,16 +5036,16 @@ t7					opcode: CP_LOAD_STATE6_FRAG (34) (20 dwords)
 			enable_mask: 0x6
 00000000011160a0:				0000: 70b68003 003a0000 011160a0 00000000 48ab1a02 011160a0 00000000 48ab2001
 *
-t7					opcode: CP_LOAD_STATE6 (36) (4 dwords)
+					opcode: CP_LOAD_STATE6 (36) (4 dwords)
 						{ DST_OFF = 0 | STATE_TYPE = ST6_SHADER | STATE_SRC = SS6_INDIRECT | STATE_BLOCK = SB6_IBO | NUM_UNIT = 0 }
 						{ EXT_SRC_ADDR = 0x11160a0 }
 						{ EXT_SRC_ADDR_HI = 0 }
 00000000011160a0:					0000: 70b68003 003a0000 011160a0 00000000
-t4					write SP_IBO (ab1a)
+					write SP_IBO (ab1a)
 						SP_IBO: 0x11160a0		base=1116000, offset=160, size=388
 						SP_IBO_HI: 0
 00000000011160b0:					0000: 48ab1a02 011160a0 00000000
-t4					write SP_IBO_COUNT (ab20)
+					write SP_IBO_COUNT (ab20)
 						SP_IBO_COUNT: 0
 00000000011160bc:					0000: 48ab2001 00000000
 			group_id: 21
@@ -5055,23 +5055,23 @@ t4					write SP_IBO_COUNT (ab20)
 			enable_mask: 0x7
 0000000001123000:				0000: 40800002 00000080 00000000 40809001 00000014 48809102 00100010 00000010
 0000000001123020:				0020: 40809583 00000000 00000000 00000000 409b0001 00000002
-t4					write GRAS_CL_CNTL (8000)
+					write GRAS_CL_CNTL (8000)
 						GRAS_CL_CNTL: { VP_CLIP_CODE_IGNORE }
 						GRAS_VS_CL_CNTL: { CLIP_MASK = 0 | CULL_MASK = 0 }
 0000000001123000:					0000: 40800002 00000080 00000000
-t4					write GRAS_SU_CNTL (8090)
+					write GRAS_SU_CNTL (8090)
 						GRAS_SU_CNTL: { FRONT_CW | LINEHALFWIDTH = 0.500000 | LINE_MODE = BRESENHAM }
 000000000112300c:					0000: 40809001 00000014
-t4					write GRAS_SU_POINT_MINMAX (8091)
+					write GRAS_SU_POINT_MINMAX (8091)
 						GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 1.000000 }
 						GRAS_SU_POINT_SIZE: 1.000000
 0000000001123014:					0000: 48809102 00100010 00000010
-t4					write GRAS_SU_POLY_OFFSET_SCALE (8095)
+					write GRAS_SU_POLY_OFFSET_SCALE (8095)
 						GRAS_SU_POLY_OFFSET_SCALE: 0.000000
 						GRAS_SU_POLY_OFFSET_OFFSET: 0.000000
 						GRAS_SU_POLY_OFFSET_OFFSET_CLAMP: 0.000000
 0000000001123020:					0000: 40809583 00000000 00000000 00000000
-t4					write PC_PRIMITIVE_CNTL_0 (9b00)
+					write PC_PRIMITIVE_CNTL_0 (9b00)
 						PC_PRIMITIVE_CNTL_0: { PROVOKING_VTX_LAST }
 0000000001123030:					0000: 409b0001 00000002
 			group_id: 22
@@ -5081,16 +5081,16 @@ t4					write PC_PRIMITIVE_CNTL_0 (9b00)
 			enable_mask: 0x7
 000000000111e000:				0000: 40886401 00000000 40888001 00000000 48887101 00000000 48888802 00000000
 *
-t4					write RB_ALPHA_CONTROL (8864)
+					write RB_ALPHA_CONTROL (8864)
 						RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_NEVER }
 000000000111e000:					0000: 40886401 00000000
-t4					write RB_STENCIL_CONTROL (8880)
+					write RB_STENCIL_CONTROL (8880)
 						RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP }
 000000000111e008:					0000: 40888001 00000000
-t4					write RB_DEPTH_CNTL (8871)
+					write RB_DEPTH_CNTL (8871)
 						RB_DEPTH_CNTL: { ZFUNC = FUNC_NEVER }
 000000000111e010:					0000: 48887101 00000000
-t4					write RB_STENCILMASK (8888)
+					write RB_STENCILMASK (8888)
 						RB_STENCILMASK: { MASK = 0 | BFMASK = 0 }
 						RB_STENCILWRMASK: { WRMASK = 0 | BFWRMASK = 0 }
 000000000111e018:					0000: 48888802 00000000 00000000
@@ -5104,61 +5104,61 @@ t4					write RB_STENCILMASK (8888)
 0000000001124040:				0040: 48884101 00000000 40884001 000007e0 40884901 00000000 48884801 000007e0
 0000000001124060:				0060: 40885101 00000000 48885001 000007e0 48885901 00000000 40885801 000007e0
 0000000001124080:				0080: 40880e01 00005555 40a98901 00000100
-t4					write RB_MRT[0].BLEND_CONTROL (8821)
+					write RB_MRT[0].BLEND_CONTROL (8821)
 						RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO }
 0000000001124000:					0000: 48882101 00000000
-t4					write RB_MRT[0].CONTROL (8820)
+					write RB_MRT[0].CONTROL (8820)
 						RB_MRT[0].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0xf }
 0000000001124008:					0000: 40882001 000007e0
-t4					write RB_MRT[0x1].BLEND_CONTROL (8829)
+					write RB_MRT[0x1].BLEND_CONTROL (8829)
 						RB_MRT[0x1].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO }
 0000000001124010:					0000: 40882901 00000000
-t4					write RB_MRT[0x1].CONTROL (8828)
+					write RB_MRT[0x1].CONTROL (8828)
 						RB_MRT[0x1].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0xf }
 0000000001124018:					0000: 48882801 000007e0
-t4					write RB_MRT[0x2].BLEND_CONTROL (8831)
+					write RB_MRT[0x2].BLEND_CONTROL (8831)
 						RB_MRT[0x2].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO }
 0000000001124020:					0000: 40883101 00000000
-t4					write RB_MRT[0x2].CONTROL (8830)
+					write RB_MRT[0x2].CONTROL (8830)
 						RB_MRT[0x2].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0xf }
 0000000001124028:					0000: 48883001 000007e0
-t4					write RB_MRT[0x3].BLEND_CONTROL (8839)
+					write RB_MRT[0x3].BLEND_CONTROL (8839)
 						RB_MRT[0x3].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO }
 0000000001124030:					0000: 48883901 00000000
-t4					write RB_MRT[0x3].CONTROL (8838)
+					write RB_MRT[0x3].CONTROL (8838)
 						RB_MRT[0x3].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0xf }
 0000000001124038:					0000: 40883801 000007e0
-t4					write RB_MRT[0x4].BLEND_CONTROL (8841)
+					write RB_MRT[0x4].BLEND_CONTROL (8841)
 						RB_MRT[0x4].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO }
 0000000001124040:					0000: 48884101 00000000
-t4					write RB_MRT[0x4].CONTROL (8840)
+					write RB_MRT[0x4].CONTROL (8840)
 						RB_MRT[0x4].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0xf }
 0000000001124048:					0000: 40884001 000007e0
-t4					write RB_MRT[0x5].BLEND_CONTROL (8849)
+					write RB_MRT[0x5].BLEND_CONTROL (8849)
 						RB_MRT[0x5].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO }
 0000000001124050:					0000: 40884901 00000000
-t4					write RB_MRT[0x5].CONTROL (8848)
+					write RB_MRT[0x5].CONTROL (8848)
 						RB_MRT[0x5].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0xf }
 0000000001124058:					0000: 48884801 000007e0
-t4					write RB_MRT[0x6].BLEND_CONTROL (8851)
+					write RB_MRT[0x6].BLEND_CONTROL (8851)
 						RB_MRT[0x6].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO }
 0000000001124060:					0000: 40885101 00000000
-t4					write RB_MRT[0x6].CONTROL (8850)
+					write RB_MRT[0x6].CONTROL (8850)
 						RB_MRT[0x6].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0xf }
 0000000001124068:					0000: 48885001 000007e0
-t4					write RB_MRT[0x7].BLEND_CONTROL (8859)
+					write RB_MRT[0x7].BLEND_CONTROL (8859)
 						RB_MRT[0x7].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO }
 0000000001124070:					0000: 48885901 00000000
-t4					write RB_MRT[0x7].CONTROL (8858)
+					write RB_MRT[0x7].CONTROL (8858)
 						RB_MRT[0x7].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0xf }
 0000000001124078:					0000: 40885801 000007e0
-t4					write RB_DITHER_CNTL (880e)
+					write RB_DITHER_CNTL (880e)
 						RB_DITHER_CNTL: { DITHER_MODE_MRT0 = DITHER_ALWAYS | DITHER_MODE_MRT1 = DITHER_ALWAYS | DITHER_MODE_MRT2 = DITHER_ALWAYS | DITHER_MODE_MRT3 = DITHER_ALWAYS | DITHER_MODE_MRT4 = DITHER_ALWAYS | DITHER_MODE_MRT5 = DITHER_ALWAYS | DITHER_MODE_MRT6 = DITHER_ALWAYS | DITHER_MODE_MRT7 = DITHER_ALWAYS }
 0000000001124080:					0000: 40880e01 00005555
-t4					write SP_BLEND_CNTL (a989)
+					write SP_BLEND_CNTL (a989)
 						SP_BLEND_CNTL: { ENABLE_BLEND = 0 | UNK8 }
 0000000001124088:					0000: 40a98901 00000100
-t7			opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords)
+			opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords)
 				{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = USE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_8_BIT | PATCH_TYPE = TESS_QUADS }
 				{ NUM_INSTANCES = 1 }
 				{ NUM_INDICES = 4 }
@@ -6759,84 +6759,84 @@ t7			opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords)
  +	000000ff			HLSQ_INVALIDATE_CMD: { VS_STATE | HS_STATE | DS_STATE | GS_STATE | FS_STATE | CS_STATE | CS_IBO | GFX_IBO | CS_BINDLESS = 0 | GFX_BINDLESS = 0 }
  +	00000108			HLSQ_FS_CNTL: { CONSTLEN = 32 | ENABLED }
 0000000001d8f130:			0000: 70388003 00000186 00000001 00000004
-t7			opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
 0000000001d8f140:			0000: 70268000
-t4			write CP_SCRATCH[0x7].REG (088a)
+			write CP_SCRATCH[0x7].REG (088a)
 				CP_SCRATCH[0x7].REG: 3
 				:0,1,17,3
 0000000001d8f144:			0000: 48088a01 00000003
 0000000001d91ac0:		0000: 70bf8003 01d8f000 00000000 00000053
-t7		opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
+		opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
 0000000001d91ad0:		0000: 70268000
-t4		write CP_SCRATCH[0x6].REG (0889)
+		write CP_SCRATCH[0x6].REG (0889)
 			CP_SCRATCH[0x6].REG: 18
 			:0,1,18,3
 0000000001d91ad4:		0000: 48088901 00000012
-t7		opcode: CP_REG_TEST (39) (2 dwords)
+		opcode: CP_REG_TEST (39) (2 dwords)
 			{ REG = 0x883 | BIT = 0 | WAIT_FOR_ME }
 0000000001d91adc:		0000: 70b90001 02000883
-t7		opcode: CP_COND_REG_EXEC (47) (3 dwords)
+		opcode: CP_COND_REG_EXEC (47) (3 dwords)
 			{ REG0 = 0 | MODE = PRED_TEST }
 			{ DWORDS = 2 }
 0000000001d91ae4:		0000: 70c70002 10000000 00000002
-t7		opcode: CP_SET_MARKER (65) (2 dwords)
+		opcode: CP_SET_MARKER (65) (2 dwords)
 			{ MODE = 0x15 | MARKER = RM6_ENDVIS }
 0000000001d91af0:		0000: 70e50001 00000015
-t7		opcode: CP_SET_DRAW_STATE (43) (4 dwords)
+		opcode: CP_SET_DRAW_STATE (43) (4 dwords)
 			{ COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 }
 			{ ADDR_LO = 0 }
 			{ ADDR_HI = 0 }
 0000000001d91af8:		0000: 70438003 00040000 00000000 00000000
-t7		opcode: CP_SKIP_IB2_ENABLE_LOCAL (23) (2 dwords)
+		opcode: CP_SKIP_IB2_ENABLE_LOCAL (23) (2 dwords)
 0000000001d91b08:		0000: 70230001 00000000
-t7		opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
+		opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
 0000000001d91b10:		0000: 70268000
-t4		write CP_SCRATCH[0x7].REG (088a)
+		write CP_SCRATCH[0x7].REG (088a)
 			CP_SCRATCH[0x7].REG: 19
 			:0,1,18,19
 0000000001d91b14:		0000: 48088a01 00000013
-t7		opcode: CP_SET_MARKER (65) (2 dwords)
+		opcode: CP_SET_MARKER (65) (2 dwords)
 			{ MODE = 0x16 | MARKER = RM6_RESOLVE }
 0000000001d91b1c:		0000: 70e50001 00000016
-t7		opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
+		opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
 0000000001d91b24:		0000: 70268000
-t4		write CP_SCRATCH[0x7].REG (088a)
+		write CP_SCRATCH[0x7].REG (088a)
 			CP_SCRATCH[0x7].REG: 20
 			:0,1,18,20
 0000000001d91b28:		0000: 48088a01 00000014
-t7		opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
+		opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
 0000000001d91b30:		0000: 70268000
-t4		write CP_SCRATCH[0x6].REG (0889)
+		write CP_SCRATCH[0x6].REG (0889)
 			CP_SCRATCH[0x6].REG: 21
 			:0,1,21,20
 0000000001d91b34:		0000: 48088901 00000015
-t7		opcode: CP_INDIRECT_BUFFER (3f) (4 dwords)
+		opcode: CP_INDIRECT_BUFFER (3f) (4 dwords)
 		ibaddr:0000000001116130
 		ibsize:00000015
-t4			write RB_BLIT_SCISSOR_TL (88d1)
+			write RB_BLIT_SCISSOR_TL (88d1)
 				RB_BLIT_SCISSOR_TL: { X = 0 | Y = 0 }
 				RB_BLIT_SCISSOR_BR: { X = 2175 | Y = 1439 }
 0000000001116130:			0000: 4888d102 00000000 059f087f
-t4			write RB_BLIT_INFO (88e3)
+			write RB_BLIT_INFO (88e3)
 				RB_BLIT_INFO: { CLEAR_MASK = 0 | LAST = 0 | BUFFER_ID = 0 }
 000000000111613c:			0000: 4088e301 00000000
-t4			write RB_BLIT_DST_INFO (88d7)
+			write RB_BLIT_DST_INFO (88d7)
 				RB_BLIT_DST_INFO: { TILE_MODE = TILE6_LINEAR | SAMPLES = MSAA_ONE | COLOR_SWAP = WXYZ | COLOR_FORMAT = FMT6_8_8_8_X8_UNORM }
 				RB_BLIT_DST: 0x1125000
 				RB_BLIT_DST_HI: 0
 				RB_BLIT_DST_PITCH: 8704
 				RB_BLIT_DST_ARRAY_PITCH: 12533760
 0000000001116144:			0000: 4888d785 000018a0 01125000 00000000 00000088 0002fd00
-t4			write RB_BLIT_BASE_GMEM (88d6)
+			write RB_BLIT_BASE_GMEM (88d6)
 				RB_BLIT_BASE_GMEM: 0
 000000000111615c:			0000: 4088d601 00000000
-t7			opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
 0000000001116164:			0000: 70268000
-t4			write CP_SCRATCH[0x7].REG (088a)
+			write CP_SCRATCH[0x7].REG (088a)
 				CP_SCRATCH[0x7].REG: 7
 				:0,1,21,7
 0000000001116168:			0000: 48088a01 00000007
-t7			opcode: CP_EVENT_WRITE (46) (2 dwords)
+			opcode: CP_EVENT_WRITE (46) (2 dwords)
 				{ EVENT = BLIT }
 			event BLIT
 			mode: RM6_RESOLVE
@@ -6856,57 +6856,57 @@ t7			opcode: CP_EVENT_WRITE (46) (2 dwords)
 !+	0002fd00			RB_BLIT_DST_ARRAY_PITCH: 12533760
 !+	00000000			RB_BLIT_INFO: { CLEAR_MASK = 0 | LAST = 0 | BUFFER_ID = 0 }
 0000000001116170:			0000: 70460001 0000001e
-t7			opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
 0000000001116178:			0000: 70268000
-t4			write CP_SCRATCH[0x7].REG (088a)
+			write CP_SCRATCH[0x7].REG (088a)
 				CP_SCRATCH[0x7].REG: 8
 				:0,1,21,8
 000000000111617c:			0000: 48088a01 00000008
 0000000001d91b3c:		0000: 70bf8003 01116130 00000000 00000015
-t7		opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
+		opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
 0000000001d91b4c:		0000: 70268000
-t4		write CP_SCRATCH[0x6].REG (0889)
+		write CP_SCRATCH[0x6].REG (0889)
 			CP_SCRATCH[0x6].REG: 22
 			:0,1,22,8
 0000000001d91b50:		0000: 48088901 00000016
-t7		opcode: CP_SET_MARKER (65) (2 dwords)
+		opcode: CP_SET_MARKER (65) (2 dwords)
 			{ MODE = RM6_YIELD | MARKER = RM6_YIELD }
 0000000001d91b58:		0000: 70e50001 00000007
-t7		opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
+		opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
 0000000001d91b60:		0000: 70268000
-t4		write CP_SCRATCH[0x7].REG (088a)
+		write CP_SCRATCH[0x7].REG (088a)
 			CP_SCRATCH[0x7].REG: 23
 			:0,1,22,23
 0000000001d91b64:		0000: 48088a01 00000017
-t7		opcode: CP_SET_MARKER (65) (2 dwords)
+		opcode: CP_SET_MARKER (65) (2 dwords)
 			{ MODE = 0x14 | MARKER = RM6_GMEM }
 0000000001d91b6c:		0000: 70e50001 00000014
-t7		opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
+		opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
 0000000001d91b74:		0000: 70268000
-t4		write CP_SCRATCH[0x7].REG (088a)
+		write CP_SCRATCH[0x7].REG (088a)
 			CP_SCRATCH[0x7].REG: 24
 			:0,1,22,24
 0000000001d91b78:		0000: 48088a01 00000018
-t4		write GRAS_SC_WINDOW_SCISSOR_TL (80f0)
+		write GRAS_SC_WINDOW_SCISSOR_TL (80f0)
 			GRAS_SC_WINDOW_SCISSOR_TL: { X = 544 | Y = 0 }
 			GRAS_SC_WINDOW_SCISSOR_BR: { X = 1087 | Y = 479 }
 0000000001d91b80:		0000: 4080f002 00000220 01df043f
-t4		write GRAS_2D_RESOLVE_CNTL_1 (840a)
+		write GRAS_2D_RESOLVE_CNTL_1 (840a)
 			GRAS_2D_RESOLVE_CNTL_1: { X = 544 | Y = 0 }
 			GRAS_2D_RESOLVE_CNTL_2: { X = 1087 | Y = 479 }
 0000000001d91b8c:		0000: 48840a02 00000220 01df043f
-t7		opcode: CP_WAIT_FOR_ME (13) (1 dwords)
+		opcode: CP_WAIT_FOR_ME (13) (1 dwords)
 0000000001d91b98:		0000: 70138000
-t7		opcode: CP_SET_MODE (63) (2 dwords)
+		opcode: CP_SET_MODE (63) (2 dwords)
 0000000001d91b9c:		0000: 70e30001 00000000
-t7		opcode: CP_REG_TEST (39) (2 dwords)
+		opcode: CP_REG_TEST (39) (2 dwords)
 			{ REG = 0x883 | BIT = 0 | WAIT_FOR_ME }
 0000000001d91ba4:		0000: 70b90001 02000883
-t7		opcode: CP_COND_REG_EXEC (47) (3 dwords)
+		opcode: CP_COND_REG_EXEC (47) (3 dwords)
 			{ REG0 = 0 | MODE = PRED_TEST }
 			{ DWORDS = 11 }
 0000000001d91bac:		0000: 70c70002 10000000 0000000b
-t7		opcode: CP_SET_BIN_DATA5 (2f) (8 dwords)
+		opcode: CP_SET_BIN_DATA5 (2f) (8 dwords)
 			{ VSC_SIZE = 1 | VSC_N = 0 }
 			{ BIN_DATA_ADDR_LO = 0x1d5d440 }
 			{ BIN_DATA_ADDR_HI = 0 }
@@ -6915,167 +6915,167 @@ t7		opcode: CP_SET_BIN_DATA5 (2f) (8 dwords)
 			{ BIN_PRIM_STRM_LO = 0x1d68040 }
 			{ BIN_PRIM_STRM_HI = 0 }
 0000000001d91bb8:		0000: 702f0007 00010000 01d5d440 00000000 01d65804 00000000 01d68040 00000000
-t7		opcode: CP_SET_VISIBILITY_OVERRIDE (64) (2 dwords)
+		opcode: CP_SET_VISIBILITY_OVERRIDE (64) (2 dwords)
 0000000001d91bd8:		0000: 70640001 00000000
-t7		opcode: CP_NOP (10) (3 dwords)
+		opcode: CP_NOP (10) (3 dwords)
 0000000001d91be0:		0000: 70100002 70640001 00000001
-t4		write RB_WINDOW_OFFSET (8890)
+		write RB_WINDOW_OFFSET (8890)
 			RB_WINDOW_OFFSET: { X = 544 | Y = 0 }
 0000000001d91bec:		0000: 48889001 00000220
-t4		write RB_WINDOW_OFFSET2 (88d4)
+		write RB_WINDOW_OFFSET2 (88d4)
 			RB_WINDOW_OFFSET2: { X = 544 | Y = 0 }
 0000000001d91bf4:		0000: 4888d401 00000220
-t4		write SP_WINDOW_OFFSET (b4d1)
+		write SP_WINDOW_OFFSET (b4d1)
 			SP_WINDOW_OFFSET: { X = 544 | Y = 0 }
 0000000001d91bfc:		0000: 48b4d101 00000220
-t4		write SP_TP_WINDOW_OFFSET (b307)
+		write SP_TP_WINDOW_OFFSET (b307)
 			SP_TP_WINDOW_OFFSET: { X = 544 | Y = 0 }
 0000000001d91c04:		0000: 48b30701 00000220
-t4		write GRAS_BIN_CONTROL (80a1)
+		write GRAS_BIN_CONTROL (80a1)
 			GRAS_BIN_CONTROL: { BINW = 544 | BINH = 480 | RENDER_MODE = RENDERING_PASS | BUFFERS_LOCATION = BUFFERS_IN_GMEM | LRZ_FEEDBACK_ZMODE_MASK = 0x6 }
 0000000001d91c0c:		0000: 4880a101 06001e11
-t4		write RB_BIN_CONTROL (8800)
+		write RB_BIN_CONTROL (8800)
 			RB_BIN_CONTROL: { BINW = 544 | BINH = 480 | RENDER_MODE = RENDERING_PASS | BUFFERS_LOCATION = BUFFERS_IN_GMEM | LRZ_FEEDBACK_ZMODE_MASK = 0x6 }
 0000000001d91c14:		0000: 48880001 06001e11
-t4		write RB_BIN_CONTROL2 (88d3)
+		write RB_BIN_CONTROL2 (88d3)
 			RB_BIN_CONTROL2: { BINW = 544 | BINH = 480 }
 0000000001d91c1c:		0000: 4088d301 00001e11
-t7		opcode: CP_SET_MODE (63) (2 dwords)
+		opcode: CP_SET_MODE (63) (2 dwords)
 0000000001d91c24:		0000: 70e30001 00000000
-t4		write RB_SAMPLE_CONFIG (8804)
+		write RB_SAMPLE_CONFIG (8804)
 			RB_SAMPLE_CONFIG: { 0 }
 0000000001d91c2c:		0000: 40880401 00000000
-t4		write SP_TP_SAMPLE_CONFIG (b304)
+		write SP_TP_SAMPLE_CONFIG (b304)
 			SP_TP_SAMPLE_CONFIG: { 0 }
 0000000001d91c34:		0000: 48b30401 00000000
-t4		write GRAS_SAMPLE_CONFIG (80a4)
+		write GRAS_SAMPLE_CONFIG (80a4)
 			GRAS_SAMPLE_CONFIG: { 0 }
 0000000001d91c3c:		0000: 4880a401 00000000
-t7		opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
+		opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
 0000000001d91c44:		0000: 70268000
-t4		write CP_SCRATCH[0x6].REG (0889)
+		write CP_SCRATCH[0x6].REG (0889)
 			CP_SCRATCH[0x6].REG: 25
 			:0,1,25,24
 0000000001d91c48:		0000: 48088901 00000019
-t7		opcode: CP_INDIRECT_BUFFER (3f) (4 dwords)
+		opcode: CP_INDIRECT_BUFFER (3f) (4 dwords)
 		ibaddr:00000000011160d0
 		ibsize:00000018
 0000000001d91c50:		0000: 70bf8003 011160d0 00000000 00000018
-t7		opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
+		opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
 0000000001d91c60:		0000: 70268000
-t4		write CP_SCRATCH[0x6].REG (0889)
+		write CP_SCRATCH[0x6].REG (0889)
 			CP_SCRATCH[0x6].REG: 26
 			:0,1,26,24
 0000000001d91c64:		0000: 48088901 0000001a
-t7		opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
+		opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
 0000000001d91c6c:		0000: 70268000
-t4		write CP_SCRATCH[0x6].REG (0889)
+		write CP_SCRATCH[0x6].REG (0889)
 			CP_SCRATCH[0x6].REG: 27
 			:0,1,27,24
 0000000001d91c70:		0000: 48088901 0000001b
-t7		opcode: CP_REG_TEST (39) (2 dwords)
+		opcode: CP_REG_TEST (39) (2 dwords)
 			{ REG = 0xc39 | BIT = 0 | WAIT_FOR_ME }
 0000000001d91c78:		0000: 70b90001 02000c39
-t7		opcode: CP_COND_REG_EXEC (47) (3 dwords)
+		opcode: CP_COND_REG_EXEC (47) (3 dwords)
 			{ REG0 = 0 | MODE = PRED_TEST }
 			{ DWORDS = 4 }
 0000000001d91c80:		0000: 70c70002 10000000 00000004
-t7		opcode: CP_INDIRECT_BUFFER (3f) (4 dwords)
+		opcode: CP_INDIRECT_BUFFER (3f) (4 dwords)
 		ibaddr:0000000001d8f000
 		ibsize:00000053
 0000000001d91c8c:		0000: 70bf8003 01d8f000 00000000 00000053
-t7		opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
+		opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
 0000000001d91c9c:		0000: 70268000
-t4		write CP_SCRATCH[0x6].REG (0889)
+		write CP_SCRATCH[0x6].REG (0889)
 			CP_SCRATCH[0x6].REG: 28
 			:0,1,28,24
 0000000001d91ca0:		0000: 48088901 0000001c
-t7		opcode: CP_REG_TEST (39) (2 dwords)
+		opcode: CP_REG_TEST (39) (2 dwords)
 			{ REG = 0x883 | BIT = 0 | WAIT_FOR_ME }
 0000000001d91ca8:		0000: 70b90001 02000883
-t7		opcode: CP_COND_REG_EXEC (47) (3 dwords)
+		opcode: CP_COND_REG_EXEC (47) (3 dwords)
 			{ REG0 = 0 | MODE = PRED_TEST }
 			{ DWORDS = 2 }
 0000000001d91cb0:		0000: 70c70002 10000000 00000002
-t7		opcode: CP_SET_MARKER (65) (2 dwords)
+		opcode: CP_SET_MARKER (65) (2 dwords)
 			{ MODE = 0x15 | MARKER = RM6_ENDVIS }
 0000000001d91cbc:		0000: 70e50001 00000015
-t7		opcode: CP_SET_DRAW_STATE (43) (4 dwords)
+		opcode: CP_SET_DRAW_STATE (43) (4 dwords)
 			{ COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 }
 			{ ADDR_LO = 0 }
 			{ ADDR_HI = 0 }
 0000000001d91cc4:		0000: 70438003 00040000 00000000 00000000
-t7		opcode: CP_SKIP_IB2_ENABLE_LOCAL (23) (2 dwords)
+		opcode: CP_SKIP_IB2_ENABLE_LOCAL (23) (2 dwords)
 0000000001d91cd4:		0000: 70230001 00000000
-t7		opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
+		opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
 0000000001d91cdc:		0000: 70268000
-t4		write CP_SCRATCH[0x7].REG (088a)
+		write CP_SCRATCH[0x7].REG (088a)
 			CP_SCRATCH[0x7].REG: 29
 			:0,1,28,29
 0000000001d91ce0:		0000: 48088a01 0000001d
-t7		opcode: CP_SET_MARKER (65) (2 dwords)
+		opcode: CP_SET_MARKER (65) (2 dwords)
 			{ MODE = 0x16 | MARKER = RM6_RESOLVE }
 0000000001d91ce8:		0000: 70e50001 00000016
-t7		opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
+		opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
 0000000001d91cf0:		0000: 70268000
-t4		write CP_SCRATCH[0x7].REG (088a)
+		write CP_SCRATCH[0x7].REG (088a)
 			CP_SCRATCH[0x7].REG: 30
 			:0,1,28,30
 0000000001d91cf4:		0000: 48088a01 0000001e
-t7		opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
+		opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
 0000000001d91cfc:		0000: 70268000
-t4		write CP_SCRATCH[0x6].REG (0889)
+		write CP_SCRATCH[0x6].REG (0889)
 			CP_SCRATCH[0x6].REG: 31
 			:0,1,31,30
 0000000001d91d00:		0000: 48088901 0000001f
-t7		opcode: CP_INDIRECT_BUFFER (3f) (4 dwords)
+		opcode: CP_INDIRECT_BUFFER (3f) (4 dwords)
 		ibaddr:0000000001116130
 		ibsize:00000015
 0000000001d91d08:		0000: 70bf8003 01116130 00000000 00000015
-t7		opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
+		opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
 0000000001d91d18:		0000: 70268000
-t4		write CP_SCRATCH[0x6].REG (0889)
+		write CP_SCRATCH[0x6].REG (0889)
 			CP_SCRATCH[0x6].REG: 32
 			:0,1,32,30
 0000000001d91d1c:		0000: 48088901 00000020
-t7		opcode: CP_SET_MARKER (65) (2 dwords)
+		opcode: CP_SET_MARKER (65) (2 dwords)
 			{ MODE = RM6_YIELD | MARKER = RM6_YIELD }
 0000000001d91d24:		0000: 70e50001 00000007
-t7		opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
+		opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
 0000000001d91d2c:		0000: 70268000
-t4		write CP_SCRATCH[0x7].REG (088a)
+		write CP_SCRATCH[0x7].REG (088a)
 			CP_SCRATCH[0x7].REG: 33
 			:0,1,32,33
 0000000001d91d30:		0000: 48088a01 00000021
-t7		opcode: CP_SET_MARKER (65) (2 dwords)
+		opcode: CP_SET_MARKER (65) (2 dwords)
 			{ MODE = 0x14 | MARKER = RM6_GMEM }
 0000000001d91d38:		0000: 70e50001 00000014
-t7		opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
+		opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
 0000000001d91d40:		0000: 70268000
-t4		write CP_SCRATCH[0x7].REG (088a)
+		write CP_SCRATCH[0x7].REG (088a)
 			CP_SCRATCH[0x7].REG: 34
 			:0,1,32,34
 0000000001d91d44:		0000: 48088a01 00000022
-t4		write GRAS_SC_WINDOW_SCISSOR_TL (80f0)
+		write GRAS_SC_WINDOW_SCISSOR_TL (80f0)
 			GRAS_SC_WINDOW_SCISSOR_TL: { X = 1088 | Y = 0 }
 			GRAS_SC_WINDOW_SCISSOR_BR: { X = 1631 | Y = 479 }
 0000000001d91d4c:		0000: 4080f002 00000440 01df065f
-t4		write GRAS_2D_RESOLVE_CNTL_1 (840a)
+		write GRAS_2D_RESOLVE_CNTL_1 (840a)
 			GRAS_2D_RESOLVE_CNTL_1: { X = 1088 | Y = 0 }
 			GRAS_2D_RESOLVE_CNTL_2: { X = 1631 | Y = 479 }
 0000000001d91d58:		0000: 48840a02 00000440 01df065f
-t7		opcode: CP_WAIT_FOR_ME (13) (1 dwords)
+		opcode: CP_WAIT_FOR_ME (13) (1 dwords)
 0000000001d91d64:		0000: 70138000
-t7		opcode: CP_SET_MODE (63) (2 dwords)
+		opcode: CP_SET_MODE (63) (2 dwords)
 0000000001d91d68:		0000: 70e30001 00000000
-t7		opcode: CP_REG_TEST (39) (2 dwords)
+		opcode: CP_REG_TEST (39) (2 dwords)
 			{ REG = 0x883 | BIT = 0 | WAIT_FOR_ME }
 0000000001d91d70:		0000: 70b90001 02000883
-t7		opcode: CP_COND_REG_EXEC (47) (3 dwords)
+		opcode: CP_COND_REG_EXEC (47) (3 dwords)
 			{ REG0 = 0 | MODE = PRED_TEST }
 			{ DWORDS = 11 }
 0000000001d91d78:		0000: 70c70002 10000000 0000000b
-t7		opcode: CP_SET_BIN_DATA5 (2f) (8 dwords)
+		opcode: CP_SET_BIN_DATA5 (2f) (8 dwords)
 			{ VSC_SIZE = 1 | VSC_N = 0 }
 			{ BIN_DATA_ADDR_LO = 0x1d5d880 }
 			{ BIN_DATA_ADDR_HI = 0 }
@@ -7084,167 +7084,167 @@ t7		opcode: CP_SET_BIN_DATA5 (2f) (8 dwords)
 			{ BIN_PRIM_STRM_LO = 0x1d69080 }
 			{ BIN_PRIM_STRM_HI = 0 }
 0000000001d91d84:		0000: 702f0007 00010000 01d5d880 00000000 01d65808 00000000 01d69080 00000000
-t7		opcode: CP_SET_VISIBILITY_OVERRIDE (64) (2 dwords)
+		opcode: CP_SET_VISIBILITY_OVERRIDE (64) (2 dwords)
 0000000001d91da4:		0000: 70640001 00000000
-t7		opcode: CP_NOP (10) (3 dwords)
+		opcode: CP_NOP (10) (3 dwords)
 0000000001d91dac:		0000: 70100002 70640001 00000001
-t4		write RB_WINDOW_OFFSET (8890)
+		write RB_WINDOW_OFFSET (8890)
 			RB_WINDOW_OFFSET: { X = 1088 | Y = 0 }
 0000000001d91db8:		0000: 48889001 00000440
-t4		write RB_WINDOW_OFFSET2 (88d4)
+		write RB_WINDOW_OFFSET2 (88d4)
 			RB_WINDOW_OFFSET2: { X = 1088 | Y = 0 }
 0000000001d91dc0:		0000: 4888d401 00000440
-t4		write SP_WINDOW_OFFSET (b4d1)
+		write SP_WINDOW_OFFSET (b4d1)
 			SP_WINDOW_OFFSET: { X = 1088 | Y = 0 }
 0000000001d91dc8:		0000: 48b4d101 00000440
-t4		write SP_TP_WINDOW_OFFSET (b307)
+		write SP_TP_WINDOW_OFFSET (b307)
 			SP_TP_WINDOW_OFFSET: { X = 1088 | Y = 0 }
 0000000001d91dd0:		0000: 48b30701 00000440
-t4		write GRAS_BIN_CONTROL (80a1)
+		write GRAS_BIN_CONTROL (80a1)
 			GRAS_BIN_CONTROL: { BINW = 544 | BINH = 480 | RENDER_MODE = RENDERING_PASS | BUFFERS_LOCATION = BUFFERS_IN_GMEM | LRZ_FEEDBACK_ZMODE_MASK = 0x6 }
 0000000001d91dd8:		0000: 4880a101 06001e11
-t4		write RB_BIN_CONTROL (8800)
+		write RB_BIN_CONTROL (8800)
 			RB_BIN_CONTROL: { BINW = 544 | BINH = 480 | RENDER_MODE = RENDERING_PASS | BUFFERS_LOCATION = BUFFERS_IN_GMEM | LRZ_FEEDBACK_ZMODE_MASK = 0x6 }
 0000000001d91de0:		0000: 48880001 06001e11
-t4		write RB_BIN_CONTROL2 (88d3)
+		write RB_BIN_CONTROL2 (88d3)
 			RB_BIN_CONTROL2: { BINW = 544 | BINH = 480 }
 0000000001d91de8:		0000: 4088d301 00001e11
-t7		opcode: CP_SET_MODE (63) (2 dwords)
+		opcode: CP_SET_MODE (63) (2 dwords)
 0000000001d91df0:		0000: 70e30001 00000000
-t4		write RB_SAMPLE_CONFIG (8804)
+		write RB_SAMPLE_CONFIG (8804)
 			RB_SAMPLE_CONFIG: { 0 }
 0000000001d91df8:		0000: 40880401 00000000
-t4		write SP_TP_SAMPLE_CONFIG (b304)
+		write SP_TP_SAMPLE_CONFIG (b304)
 			SP_TP_SAMPLE_CONFIG: { 0 }
 0000000001d91e00:		0000: 48b30401 00000000
-t4		write GRAS_SAMPLE_CONFIG (80a4)
+		write GRAS_SAMPLE_CONFIG (80a4)
 			GRAS_SAMPLE_CONFIG: { 0 }
 0000000001d91e08:		0000: 4880a401 00000000
-t7		opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
+		opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
 0000000001d91e10:		0000: 70268000
-t4		write CP_SCRATCH[0x6].REG (0889)
+		write CP_SCRATCH[0x6].REG (0889)
 			CP_SCRATCH[0x6].REG: 35
 			:0,1,35,34
 0000000001d91e14:		0000: 48088901 00000023
-t7		opcode: CP_INDIRECT_BUFFER (3f) (4 dwords)
+		opcode: CP_INDIRECT_BUFFER (3f) (4 dwords)
 		ibaddr:00000000011160d0
 		ibsize:00000018
 0000000001d91e1c:		0000: 70bf8003 011160d0 00000000 00000018
-t7		opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
+		opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
 0000000001d91e2c:		0000: 70268000
-t4		write CP_SCRATCH[0x6].REG (0889)
+		write CP_SCRATCH[0x6].REG (0889)
 			CP_SCRATCH[0x6].REG: 36
 			:0,1,36,34
 0000000001d91e30:		0000: 48088901 00000024
-t7		opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
+		opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
 0000000001d91e38:		0000: 70268000
-t4		write CP_SCRATCH[0x6].REG (0889)
+		write CP_SCRATCH[0x6].REG (0889)
 			CP_SCRATCH[0x6].REG: 37
 			:0,1,37,34
 0000000001d91e3c:		0000: 48088901 00000025
-t7		opcode: CP_REG_TEST (39) (2 dwords)
+		opcode: CP_REG_TEST (39) (2 dwords)
 			{ REG = 0xc3a | BIT = 0 | WAIT_FOR_ME }
 0000000001d91e44:		0000: 70b90001 02000c3a
-t7		opcode: CP_COND_REG_EXEC (47) (3 dwords)
+		opcode: CP_COND_REG_EXEC (47) (3 dwords)
 			{ REG0 = 0 | MODE = PRED_TEST }
 			{ DWORDS = 4 }
 0000000001d91e4c:		0000: 70c70002 10000000 00000004
-t7		opcode: CP_INDIRECT_BUFFER (3f) (4 dwords)
+		opcode: CP_INDIRECT_BUFFER (3f) (4 dwords)
 		ibaddr:0000000001d8f000
 		ibsize:00000053
 0000000001d91e58:		0000: 70bf8003 01d8f000 00000000 00000053
-t7		opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
+		opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
 0000000001d91e68:		0000: 70268000
-t4		write CP_SCRATCH[0x6].REG (0889)
+		write CP_SCRATCH[0x6].REG (0889)
 			CP_SCRATCH[0x6].REG: 38
 			:0,1,38,34
 0000000001d91e6c:		0000: 48088901 00000026
-t7		opcode: CP_REG_TEST (39) (2 dwords)
+		opcode: CP_REG_TEST (39) (2 dwords)
 			{ REG = 0x883 | BIT = 0 | WAIT_FOR_ME }
 0000000001d91e74:		0000: 70b90001 02000883
-t7		opcode: CP_COND_REG_EXEC (47) (3 dwords)
+		opcode: CP_COND_REG_EXEC (47) (3 dwords)
 			{ REG0 = 0 | MODE = PRED_TEST }
 			{ DWORDS = 2 }
 0000000001d91e7c:		0000: 70c70002 10000000 00000002
-t7		opcode: CP_SET_MARKER (65) (2 dwords)
+		opcode: CP_SET_MARKER (65) (2 dwords)
 			{ MODE = 0x15 | MARKER = RM6_ENDVIS }
 0000000001d91e88:		0000: 70e50001 00000015
-t7		opcode: CP_SET_DRAW_STATE (43) (4 dwords)
+		opcode: CP_SET_DRAW_STATE (43) (4 dwords)
 			{ COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 }
 			{ ADDR_LO = 0 }
 			{ ADDR_HI = 0 }
 0000000001d91e90:		0000: 70438003 00040000 00000000 00000000
-t7		opcode: CP_SKIP_IB2_ENABLE_LOCAL (23) (2 dwords)
+		opcode: CP_SKIP_IB2_ENABLE_LOCAL (23) (2 dwords)
 0000000001d91ea0:		0000: 70230001 00000000
-t7		opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
+		opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
 0000000001d91ea8:		0000: 70268000
-t4		write CP_SCRATCH[0x7].REG (088a)
+		write CP_SCRATCH[0x7].REG (088a)
 			CP_SCRATCH[0x7].REG: 39
 			:0,1,38,39
 0000000001d91eac:		0000: 48088a01 00000027
-t7		opcode: CP_SET_MARKER (65) (2 dwords)
+		opcode: CP_SET_MARKER (65) (2 dwords)
 			{ MODE = 0x16 | MARKER = RM6_RESOLVE }
 0000000001d91eb4:		0000: 70e50001 00000016
-t7		opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
+		opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
 0000000001d91ebc:		0000: 70268000
-t4		write CP_SCRATCH[0x7].REG (088a)
+		write CP_SCRATCH[0x7].REG (088a)
 			CP_SCRATCH[0x7].REG: 40
 			:0,1,38,40
 0000000001d91ec0:		0000: 48088a01 00000028
-t7		opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
+		opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
 0000000001d91ec8:		0000: 70268000
-t4		write CP_SCRATCH[0x6].REG (0889)
+		write CP_SCRATCH[0x6].REG (0889)
 			CP_SCRATCH[0x6].REG: 41
 			:0,1,41,40
 0000000001d91ecc:		0000: 48088901 00000029
-t7		opcode: CP_INDIRECT_BUFFER (3f) (4 dwords)
+		opcode: CP_INDIRECT_BUFFER (3f) (4 dwords)
 		ibaddr:0000000001116130
 		ibsize:00000015
 0000000001d91ed4:		0000: 70bf8003 01116130 00000000 00000015
-t7		opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
+		opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
 0000000001d91ee4:		0000: 70268000
-t4		write CP_SCRATCH[0x6].REG (0889)
+		write CP_SCRATCH[0x6].REG (0889)
 			CP_SCRATCH[0x6].REG: 42
 			:0,1,42,40
 0000000001d91ee8:		0000: 48088901 0000002a
-t7		opcode: CP_SET_MARKER (65) (2 dwords)
+		opcode: CP_SET_MARKER (65) (2 dwords)
 			{ MODE = RM6_YIELD | MARKER = RM6_YIELD }
 0000000001d91ef0:		0000: 70e50001 00000007
-t7		opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
+		opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
 0000000001d91ef8:		0000: 70268000
-t4		write CP_SCRATCH[0x7].REG (088a)
+		write CP_SCRATCH[0x7].REG (088a)
 			CP_SCRATCH[0x7].REG: 43
 			:0,1,42,43
 0000000001d91efc:		0000: 48088a01 0000002b
-t7		opcode: CP_SET_MARKER (65) (2 dwords)
+		opcode: CP_SET_MARKER (65) (2 dwords)
 			{ MODE = 0x14 | MARKER = RM6_GMEM }
 0000000001d91f04:		0000: 70e50001 00000014
-t7		opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
+		opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
 0000000001d91f0c:		0000: 70268000
-t4		write CP_SCRATCH[0x7].REG (088a)
+		write CP_SCRATCH[0x7].REG (088a)
 			CP_SCRATCH[0x7].REG: 44
 			:0,1,42,44
 0000000001d91f10:		0000: 48088a01 0000002c
-t4		write GRAS_SC_WINDOW_SCISSOR_TL (80f0)
+		write GRAS_SC_WINDOW_SCISSOR_TL (80f0)
 			GRAS_SC_WINDOW_SCISSOR_TL: { X = 1632 | Y = 0 }
 			GRAS_SC_WINDOW_SCISSOR_BR: { X = 2159 | Y = 479 }
 0000000001d91f18:		0000: 4080f002 00000660 01df086f
-t4		write GRAS_2D_RESOLVE_CNTL_1 (840a)
+		write GRAS_2D_RESOLVE_CNTL_1 (840a)
 			GRAS_2D_RESOLVE_CNTL_1: { X = 1632 | Y = 0 }
 			GRAS_2D_RESOLVE_CNTL_2: { X = 2159 | Y = 479 }
 0000000001d91f24:		0000: 48840a02 00000660 01df086f
-t7		opcode: CP_WAIT_FOR_ME (13) (1 dwords)
+		opcode: CP_WAIT_FOR_ME (13) (1 dwords)
 0000000001d91f30:		0000: 70138000
-t7		opcode: CP_SET_MODE (63) (2 dwords)
+		opcode: CP_SET_MODE (63) (2 dwords)
 0000000001d91f34:		0000: 70e30001 00000000
-t7		opcode: CP_REG_TEST (39) (2 dwords)
+		opcode: CP_REG_TEST (39) (2 dwords)
 			{ REG = 0x883 | BIT = 0 | WAIT_FOR_ME }
 0000000001d91f3c:		0000: 70b90001 02000883
-t7		opcode: CP_COND_REG_EXEC (47) (3 dwords)
+		opcode: CP_COND_REG_EXEC (47) (3 dwords)
 			{ REG0 = 0 | MODE = PRED_TEST }
 			{ DWORDS = 11 }
 0000000001d91f44:		0000: 70c70002 10000000 0000000b
-t7		opcode: CP_SET_BIN_DATA5 (2f) (8 dwords)
+		opcode: CP_SET_BIN_DATA5 (2f) (8 dwords)
 			{ VSC_SIZE = 1 | VSC_N = 0 }
 			{ BIN_DATA_ADDR_LO = 0x1d5dcc0 }
 			{ BIN_DATA_ADDR_HI = 0 }
@@ -7253,53 +7253,53 @@ t7		opcode: CP_SET_BIN_DATA5 (2f) (8 dwords)
 			{ BIN_PRIM_STRM_LO = 0x1d6a0c0 }
 			{ BIN_PRIM_STRM_HI = 0 }
 0000000001d91f50:		0000: 702f0007 00010000 01d5dcc0 00000000 01d6580c 00000000 01d6a0c0 00000000
-t7		opcode: CP_SET_VISIBILITY_OVERRIDE (64) (2 dwords)
+		opcode: CP_SET_VISIBILITY_OVERRIDE (64) (2 dwords)
 0000000001d91f70:		0000: 70640001 00000000
-t7		opcode: CP_NOP (10) (3 dwords)
+		opcode: CP_NOP (10) (3 dwords)
 0000000001d91f78:		0000: 70100002 70640001 00000001
-t4		write RB_WINDOW_OFFSET (8890)
+		write RB_WINDOW_OFFSET (8890)
 			RB_WINDOW_OFFSET: { X = 1632 | Y = 0 }
 0000000001d91f84:		0000: 48889001 00000660
-t4		write RB_WINDOW_OFFSET2 (88d4)
+		write RB_WINDOW_OFFSET2 (88d4)
 			RB_WINDOW_OFFSET2: { X = 1632 | Y = 0 }
 0000000001d91f8c:		0000: 4888d401 00000660
-t4		write SP_WINDOW_OFFSET (b4d1)
+		write SP_WINDOW_OFFSET (b4d1)
 			SP_WINDOW_OFFSET: { X = 1632 | Y = 0 }
 0000000001d91f94:		0000: 48b4d101 00000660
-t4		write SP_TP_WINDOW_OFFSET (b307)
+		write SP_TP_WINDOW_OFFSET (b307)
 			SP_TP_WINDOW_OFFSET: { X = 1632 | Y = 0 }
 0000000001d91f9c:		0000: 48b30701 00000660
-t4		write GRAS_BIN_CONTROL (80a1)
+		write GRAS_BIN_CONTROL (80a1)
 			GRAS_BIN_CONTROL: { BINW = 544 | BINH = 480 | RENDER_MODE = RENDERING_PASS | BUFFERS_LOCATION = BUFFERS_IN_GMEM | LRZ_FEEDBACK_ZMODE_MASK = 0x6 }
 0000000001d91fa4:		0000: 4880a101 06001e11
-t4		write RB_BIN_CONTROL (8800)
+		write RB_BIN_CONTROL (8800)
 			RB_BIN_CONTROL: { BINW = 544 | BINH = 480 | RENDER_MODE = RENDERING_PASS | BUFFERS_LOCATION = BUFFERS_IN_GMEM | LRZ_FEEDBACK_ZMODE_MASK = 0x6 }
 0000000001d91fac:		0000: 48880001 06001e11
-t4		write RB_BIN_CONTROL2 (88d3)
+		write RB_BIN_CONTROL2 (88d3)
 			RB_BIN_CONTROL2: { BINW = 544 | BINH = 480 }
 0000000001d91fb4:		0000: 4088d301 00001e11
-t7		opcode: CP_SET_MODE (63) (2 dwords)
+		opcode: CP_SET_MODE (63) (2 dwords)
 0000000001d91fbc:		0000: 70e30001 00000000
-t4		write RB_SAMPLE_CONFIG (8804)
+		write RB_SAMPLE_CONFIG (8804)
 			RB_SAMPLE_CONFIG: { 0 }
 0000000001d91fc4:		0000: 40880401 00000000
-t4		write SP_TP_SAMPLE_CONFIG (b304)
+		write SP_TP_SAMPLE_CONFIG (b304)
 			SP_TP_SAMPLE_CONFIG: { 0 }
 0000000001d91fcc:		0000: 48b30401 00000000
-t4		write GRAS_SAMPLE_CONFIG (80a4)
+		write GRAS_SAMPLE_CONFIG (80a4)
 			GRAS_SAMPLE_CONFIG: { 0 }
 0000000001d91fd4:		0000: 4880a401 00000000
-t7		opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
+		opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
 0000000001d91fdc:		0000: 70268000
-t4		write CP_SCRATCH[0x6].REG (0889)
+		write CP_SCRATCH[0x6].REG (0889)
 			CP_SCRATCH[0x6].REG: 45
 			:0,1,45,44
 0000000001d91fe0:		0000: 48088901 0000002d
-t7		opcode: CP_INDIRECT_BUFFER (3f) (4 dwords)
+		opcode: CP_INDIRECT_BUFFER (3f) (4 dwords)
 		ibaddr:00000000011160d0
 		ibsize:00000018
 0000000001d91fe8:		0000: 70bf8003 011160d0 00000000 00000018
-t7		opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
+		opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
 0000000001d91ff8:		0000: 70268000
 ############################################################
 vertices: 0
diff --git a/src/freedreno/.gitlab-ci/reference/glxgears-a420.log b/src/freedreno/.gitlab-ci/reference/glxgears-a420.log
index ca341567540..b547de29387 100644
--- a/src/freedreno/.gitlab-ci/reference/glxgears-a420.log
+++ b/src/freedreno/.gitlab-ci/reference/glxgears-a420.log
@@ -3,139 +3,139 @@ cmd: X/23360: fence=1029603
 cmd: glxgears/23375: fence=1029604
 ############################################################
 cmdstream[1]: 414 dwords
-t0		write RBBM_PERFCTR_CTL (0170)
+		write RBBM_PERFCTR_CTL (0170)
 			RBBM_PERFCTR_CTL: 0x1
 108ce000:		0000: 00000170 00000001
-t0		write GRAS_DEBUG_ECO_CONTROL (0c81)
+		write GRAS_DEBUG_ECO_CONTROL (0c81)
 			GRAS_DEBUG_ECO_CONTROL: 0
 108ce008:		0000: 00000c81 00000000
-t0		write SP_MODE_CONTROL (0ec3)
+		write SP_MODE_CONTROL (0ec3)
 			SP_MODE_CONTROL: 0x6
 108ce010:		0000: 00000ec3 00000006
-t0		write TPL1_TP_MODE_CONTROL (0f03)
+		write TPL1_TP_MODE_CONTROL (0f03)
 			TPL1_TP_MODE_CONTROL: 0x3a
 108ce018:		0000: 00000f03 0000003a
-t0		write UNKNOWN_0D01 (0d01)
+		write UNKNOWN_0D01 (0d01)
 			UNKNOWN_0D01: 0x1
 108ce020:		0000: 00000d01 00000001
-t0		write UNKNOWN_0E42 (0e42)
+		write UNKNOWN_0E42 (0e42)
 			UNKNOWN_0E42: 0
 108ce028:		0000: 00000e42 00000000
-t0		write UCHE_CACHE_WAYS_VFD (0e8c)
+		write UCHE_CACHE_WAYS_VFD (0e8c)
 			UCHE_CACHE_WAYS_VFD: 0x7
 108ce030:		0000: 00000e8c 00000007
-t0		write UCHE_CACHE_MODE_CONTROL (0e80)
+		write UCHE_CACHE_MODE_CONTROL (0e80)
 			UCHE_CACHE_MODE_CONTROL: 0
 108ce038:		0000: 00000e80 00000000
-t0		write UCHE_INVALIDATE0 (0e8a)
+		write UCHE_INVALIDATE0 (0e8a)
 			UCHE_INVALIDATE0: 0
 			UCHE_INVALIDATE1: 0x12
 108ce040:		0000: 00010e8a 00000000 00000012
-t0		write HLSQ_MODE_CONTROL (0e05)
+		write HLSQ_MODE_CONTROL (0e05)
 			HLSQ_MODE_CONTROL: 0
 108ce04c:		0000: 00000e05 00000000
-t0		write UNKNOWN_0CC5 (0cc5)
+		write UNKNOWN_0CC5 (0cc5)
 			UNKNOWN_0CC5: 0x6
 108ce054:		0000: 00000cc5 00000006
-t0		write UNKNOWN_0CC6 (0cc6)
+		write UNKNOWN_0CC6 (0cc6)
 			UNKNOWN_0CC6: 0
 108ce05c:		0000: 00000cc6 00000000
-t0		write UNKNOWN_0EC2 (0ec2)
+		write UNKNOWN_0EC2 (0ec2)
 			UNKNOWN_0EC2: 0x40000
 108ce064:		0000: 00000ec2 00040000
-t0		write UNKNOWN_2001 (2001)
+		write UNKNOWN_2001 (2001)
 			UNKNOWN_2001: 0
 108ce06c:		0000: 00002001 00000000
-t3		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
+		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
 108ce074:		0000: c0003b00 00001000
-t0		write UNKNOWN_20EF (20ef)
+		write UNKNOWN_20EF (20ef)
 			UNKNOWN_20EF: 0
 108ce07c:		0000: 000020ef 00000000
-t0		write RB_BLEND_RED (20f0)
+		write RB_BLEND_RED (20f0)
 			RB_BLEND_RED: { UINT = 0 | SINT = 0 | FLOAT = 0.000000 }
 			RB_BLEND_RED_F32: 0.000000
 			RB_BLEND_GREEN: { UINT = 0 | SINT = 0 | FLOAT = 0.000000 }
 			RB_BLEND_GREEN_F32: 0.007813
 108ce084:		0000: 000320f0 00000000 00000000 00000000 3c0000ff
-t0		write UNKNOWN_2152 (2152)
+		write UNKNOWN_2152 (2152)
 			UNKNOWN_2152: 0
 108ce098:		0000: 00002152 00000000
-t0		write UNKNOWN_2153 (2153)
+		write UNKNOWN_2153 (2153)
 			UNKNOWN_2153: 0
 108ce0a0:		0000: 00002153 00000000
-t0		write UNKNOWN_2154 (2154)
+		write UNKNOWN_2154 (2154)
 			UNKNOWN_2154: 0
 108ce0a8:		0000: 00002154 00000000
-t0		write UNKNOWN_2155 (2155)
+		write UNKNOWN_2155 (2155)
 			UNKNOWN_2155: 0
 108ce0b0:		0000: 00002155 00000000
-t0		write UNKNOWN_2156 (2156)
+		write UNKNOWN_2156 (2156)
 			UNKNOWN_2156: 0
 108ce0b8:		0000: 00002156 00000000
-t0		write UNKNOWN_2157 (2157)
+		write UNKNOWN_2157 (2157)
 			UNKNOWN_2157: 0
 108ce0c0:		0000: 00002157 00000000
-t0		write UNKNOWN_21C3 (21c3)
+		write UNKNOWN_21C3 (21c3)
 			UNKNOWN_21C3: 0x1d
 108ce0c8:		0000: 000021c3 0000001d
-t0		write PC_GS_PARAM (21e5)
+		write PC_GS_PARAM (21e5)
 			PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS }
 108ce0d0:		0000: 000021e5 00000000
-t0		write UNKNOWN_21E6 (21e6)
+		write UNKNOWN_21E6 (21e6)
 			UNKNOWN_21E6: 0x1
 108ce0d8:		0000: 000021e6 00000001
-t0		write PC_HS_PARAM (21e7)
+		write PC_HS_PARAM (21e7)
 			PC_HS_PARAM: { VERTICES_OUT = 0 | SPACING = EQUAL_SPACING }
 108ce0e0:		0000: 000021e7 00000000
-t0		write UNKNOWN_22D7 (22d7)
+		write UNKNOWN_22D7 (22d7)
 			UNKNOWN_22D7: 0
 108ce0e8:		0000: 000022d7 00000000
-t0		write TPL1_TP_TEX_OFFSET (2380)
+		write TPL1_TP_TEX_OFFSET (2380)
 			TPL1_TP_TEX_OFFSET: 0
 108ce0f0:		0000: 00002380 00000000
-t0		write TPL1_TP_TEX_COUNT (2381)
+		write TPL1_TP_TEX_COUNT (2381)
 			TPL1_TP_TEX_COUNT: { VS = 16 | HS = 0 | DS = 0 | GS = 0 }
 108ce0f8:		0000: 00002381 00000010
-t0		write TPL1_TP_FS_TEX_COUNT (23a0)
+		write TPL1_TP_FS_TEX_COUNT (23a0)
 			TPL1_TP_FS_TEX_COUNT: { FS = 16 | CS = 0 }
 108ce100:		0000: 000023a0 00000010
-t3		opcode: CP_SET_DRAW_STATE (43) (3 dwords)
+		opcode: CP_SET_DRAW_STATE (43) (3 dwords)
 			{ COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 }
 			{ ADDR_LO = 0 }
 108ce108:		0000: c0014300 00040000 00000000
-t0		write SP_VS_PVT_MEM_PARAM (22e2)
+		write SP_VS_PVT_MEM_PARAM (22e2)
 			SP_VS_PVT_MEM_PARAM: 0x8000001
 			SP_VS_PVT_MEM_ADDR: 0x10cd7000
 108ce114:		0000: 000122e2 08000001 10cd7000
-t0		write SP_FS_PVT_MEM_PARAM (22ec)
+		write SP_FS_PVT_MEM_PARAM (22ec)
 			SP_FS_PVT_MEM_PARAM: 0x8000001
 			SP_FS_PVT_MEM_ADDR: 0x10cd9000
 108ce120:		0000: 000122ec 08000001 10cd9000
-t0		write GRAS_SC_CONTROL (207b)
+		write GRAS_SC_CONTROL (207b)
 			GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = 0 | MSAA_DISABLE | RASTER_MODE = 0 }
 108ce12c:		0000: 0000207b 00000800
-t0		write RB_MSAA_CONTROL (20a2)
+		write RB_MSAA_CONTROL (20a2)
 			RB_MSAA_CONTROL: { DISABLE | SAMPLES = 0 }
 108ce134:		0000: 000020a2 00001000
-t0		write GRAS_CL_GB_CLIP_ADJ (2004)
+		write GRAS_CL_GB_CLIP_ADJ (2004)
 			GRAS_CL_GB_CLIP_ADJ: { HORZ = 0 | VERT = 0 }
 108ce13c:		0000: 00002004 00000000
-t0		write RB_ALPHA_CONTROL (20f8)
+		write RB_ALPHA_CONTROL (20f8)
 			RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS }
 108ce144:		0000: 000020f8 00000e00
-t0		write RB_FS_OUTPUT (20f9)
+		write RB_FS_OUTPUT (20f9)
 			RB_FS_OUTPUT: { ENABLE_BLEND = 0 | SAMPLE_MASK = 0xffff }
 108ce14c:		0000: 000020f9 ffff0000
-t0		write GRAS_ALPHA_CONTROL (2073)
+		write GRAS_ALPHA_CONTROL (2073)
 			GRAS_ALPHA_CONTROL: { 0 }
 108ce154:		0000: 00002073 00000000
-t0		write VSC_BIN_SIZE (0c00)
+		write VSC_BIN_SIZE (0c00)
 			VSC_BIN_SIZE: { WIDTH = 320 | HEIGHT = 320 }
 108ce15c:		0000: 00000c00 0000014a
-t0		write VSC_SIZE_ADDRESS (0c01)
+		write VSC_SIZE_ADDRESS (0c01)
 			VSC_SIZE_ADDRESS: 0x10cdb000
 108ce164:		0000: 00000c01 10cdb000
-t0		write VSC_PIPE_CONFIG[0].REG (0c08)
+		write VSC_PIPE_CONFIG[0].REG (0c08)
 			VSC_PIPE_CONFIG[0].REG: { X = 0 | Y = 0 | W = 1 | H = 1 }
 			VSC_PIPE_CONFIG[0x1].REG: { X = 0 | Y = 0 | W = 0 | H = 0 }
 			VSC_PIPE_CONFIG[0x2].REG: { X = 0 | Y = 0 | W = 0 | H = 0 }
@@ -146,7 +146,7 @@ t0		write VSC_PIPE_CONFIG[0].REG (0c08)
 			VSC_PIPE_CONFIG[0x7].REG: { X = 0 | Y = 0 | W = 0 | H = 0 }
 108ce16c:		0000: 00070c08 01100000 00000000 00000000 00000000 00000000 00000000 00000000
 *
-t0		write VSC_PIPE_DATA_ADDRESS[0].REG (0c10)
+		write VSC_PIPE_DATA_ADDRESS[0].REG (0c10)
 			VSC_PIPE_DATA_ADDRESS[0].REG: 0x10cdc000
 			VSC_PIPE_DATA_ADDRESS[0x1].REG: 0x10d1c000
 			VSC_PIPE_DATA_ADDRESS[0x2].REG: 0x10d5c000
@@ -157,7 +157,7 @@ t0		write VSC_PIPE_DATA_ADDRESS[0].REG (0c10)
 			VSC_PIPE_DATA_ADDRESS[0x7].REG: 0x10e9c000
 108ce190:		0000: 00070c10 10cdc000 10d1c000 10d5c000 10d9c000 10ddc000 10e1c000 10e5c000
 108ce1b0:		0020: 10e9c000
-t0		write VSC_PIPE_DATA_LENGTH[0].REG (0c18)
+		write VSC_PIPE_DATA_LENGTH[0].REG (0c18)
 			VSC_PIPE_DATA_LENGTH[0].REG: 0x3ffe0
 			VSC_PIPE_DATA_LENGTH[0x1].REG: 0x3ffe0
 			VSC_PIPE_DATA_LENGTH[0x2].REG: 0x3ffe0
@@ -168,138 +168,138 @@ t0		write VSC_PIPE_DATA_LENGTH[0].REG (0c18)
 			VSC_PIPE_DATA_LENGTH[0x7].REG: 0x3ffe0
 108ce1b4:		0000: 00070c18 0003ffe0 0003ffe0 0003ffe0 0003ffe0 0003ffe0 0003ffe0 0003ffe0
 108ce1d4:		0020: 0003ffe0
-t3		opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+		opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 108ce1d8:		0000: c0002600 00000000
-t0		write RB_FRAME_BUFFER_DIMENSION (0ce0)
+		write RB_FRAME_BUFFER_DIMENSION (0ce0)
 			RB_FRAME_BUFFER_DIMENSION: { WIDTH = 300 | HEIGHT = 300 }
 108ce1e0:		0000: 00000ce0 012c012c
-t0		write RB_MODE_CONTROL (20a0)
+		write RB_MODE_CONTROL (20a0)
 			RB_MODE_CONTROL: { WIDTH = 320 | HEIGHT = 320 | ENABLE_GMEM }
 108ce1e8:		0000: 000020a0 00010a0a
-t0		write RB_DEPTH_INFO (2103)
+		write RB_DEPTH_INFO (2103)
 			RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTH4_24_8 | DEPTH_BASE = 0x64000 }
 			RB_DEPTH_PITCH: 1280
 			RB_DEPTH_PITCH2: 1280
 108ce1f0:		0000: 00022103 00064002 00000028 00000028
-t0		write RB_STENCIL_INFO (2108)
+		write RB_STENCIL_INFO (2108)
 			RB_STENCIL_INFO: { STENCIL_BASE = 0 }
 			RB_STENCIL_PITCH: 0
 108ce200:		0000: 00012108 00000000 00000000
-t0		write GRAS_DEPTH_CONTROL (2077)
+		write GRAS_DEPTH_CONTROL (2077)
 			GRAS_DEPTH_CONTROL: { FORMAT = DEPTH4_24_8 }
 108ce20c:		0000: 00002077 00000002
-t0		write PC_VSTREAM_CONTROL (21c2)
+		write PC_VSTREAM_CONTROL (21c2)
 			PC_VSTREAM_CONTROL: { SIZE = 0 | N = 0 }
 108ce214:		0000: 000021c2 00000000
-t3		opcode: (null) (4c) (4 dwords)
+		opcode: (null) (4c) (4 dwords)
 108ce21c:		0000: c0024c00 00000000 00000000 012b012b
-t0		write RB_MRT[0].BUF_INFO (20a5)
+		write RB_MRT[0].BUF_INFO (20a5)
 			RB_MRT[0].BUF_INFO: { COLOR_FORMAT = RB4_R8G8B8A8_UNORM | COLOR_TILE_MODE = TILE4_2 | DITHER_MODE = DITHER_DISABLE | COLOR_SWAP = WXYZ | COLOR_BUF_PITCH = 1280 }
 			RB_MRT[0].BASE: 0
 			RB_MRT[0].CONTROL3: { STRIDE = 1280 }
 108ce22c:		0000: 000220a5 0014089a 00000000 00002800
-t0		write RB_MRT[0x1].BUF_INFO (20aa)
+		write RB_MRT[0x1].BUF_INFO (20aa)
 			RB_MRT[0x1].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE4_2 | DITHER_MODE = DITHER_DISABLE | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 0 }
 			RB_MRT[0x1].BASE: 0
 			RB_MRT[0x1].CONTROL3: { STRIDE = 0 }
 108ce23c:		0000: 000220aa 00000080 00000000 00000000
-t0		write RB_MRT[0x2].BUF_INFO (20af)
+		write RB_MRT[0x2].BUF_INFO (20af)
 			RB_MRT[0x2].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE4_2 | DITHER_MODE = DITHER_DISABLE | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 0 }
 			RB_MRT[0x2].BASE: 0
 			RB_MRT[0x2].CONTROL3: { STRIDE = 0 }
 108ce24c:		0000: 000220af 00000080 00000000 00000000
-t0		write RB_MRT[0x3].BUF_INFO (20b4)
+		write RB_MRT[0x3].BUF_INFO (20b4)
 			RB_MRT[0x3].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE4_2 | DITHER_MODE = DITHER_DISABLE | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 0 }
 			RB_MRT[0x3].BASE: 0
 			RB_MRT[0x3].CONTROL3: { STRIDE = 0 }
 108ce25c:		0000: 000220b4 00000080 00000000 00000000
-t0		write RB_MRT[0x4].BUF_INFO (20b9)
+		write RB_MRT[0x4].BUF_INFO (20b9)
 			RB_MRT[0x4].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE4_2 | DITHER_MODE = DITHER_DISABLE | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 0 }
 			RB_MRT[0x4].BASE: 0
 			RB_MRT[0x4].CONTROL3: { STRIDE = 0 }
 108ce26c:		0000: 000220b9 00000080 00000000 00000000
-t0		write RB_MRT[0x5].BUF_INFO (20be)
+		write RB_MRT[0x5].BUF_INFO (20be)
 			RB_MRT[0x5].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE4_2 | DITHER_MODE = DITHER_DISABLE | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 0 }
 			RB_MRT[0x5].BASE: 0
 			RB_MRT[0x5].CONTROL3: { STRIDE = 0 }
 108ce27c:		0000: 000220be 00000080 00000000 00000000
-t0		write RB_MRT[0x6].BUF_INFO (20c3)
+		write RB_MRT[0x6].BUF_INFO (20c3)
 			RB_MRT[0x6].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE4_2 | DITHER_MODE = DITHER_DISABLE | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 0 }
 			RB_MRT[0x6].BASE: 0
 			RB_MRT[0x6].CONTROL3: { STRIDE = 0 }
 108ce28c:		0000: 000220c3 00000080 00000000 00000000
-t0		write RB_MRT[0x7].BUF_INFO (20c8)
+		write RB_MRT[0x7].BUF_INFO (20c8)
 			RB_MRT[0x7].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE4_2 | DITHER_MODE = DITHER_DISABLE | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 0 }
 			RB_MRT[0x7].BASE: 0
 			RB_MRT[0x7].CONTROL3: { STRIDE = 0 }
 108ce29c:		0000: 000220c8 00000080 00000000 00000000
-t0		write RB_BIN_OFFSET (210d)
+		write RB_BIN_OFFSET (210d)
 			RB_BIN_OFFSET: { X = 0 | Y = 0 }
 108ce2ac:		0000: 0000210d 00000000
-t0		write GRAS_SC_SCREEN_SCISSOR_TL (207c)
+		write GRAS_SC_SCREEN_SCISSOR_TL (207c)
 			GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 }
 			GRAS_SC_SCREEN_SCISSOR_BR: { X = 299 | Y = 299 }
 108ce2b4:		0000: 0001207c 00000000 012b012b
-t0		write RB_RENDER_CONTROL (20a1)
+		write RB_RENDER_CONTROL (20a1)
 			RB_RENDER_CONTROL: { 0x8 }
 108ce2c0:		0000: 000020a1 00000008
-t0		write CP_SCRATCH[0x6].REG (057e)
+		write CP_SCRATCH[0x6].REG (057e)
 			CP_SCRATCH[0x6].REG: 0x73
 			:0,0,115,0
 108ce2c8:		0000: 0000057e 00000073
-t3		opcode: CP_INDIRECT_BUFFER (3f) (3 dwords)
+		opcode: CP_INDIRECT_BUFFER (3f) (3 dwords)
 		ibaddr:109ce000
 		ibsize:00000f2e
-t0			write CP_SCRATCH[0x5].REG (057d)
+			write CP_SCRATCH[0x5].REG (057d)
 				CP_SCRATCH[0x5].REG: 0x1
 				:0,1,115,0
 109ce000:			0000: 0000057d 00000001
-t0			write RB_RENDER_COMPONENTS (20fb)
+			write RB_RENDER_COMPONENTS (20fb)
 				RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 }
 109ce008:			0000: 000020fb 0000000f
-t0			write RB_ALPHA_CONTROL (20f8)
+			write RB_ALPHA_CONTROL (20f8)
 				RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_NEVER }
 109ce010:			0000: 000020f8 00000000
-t0			write RB_STENCIL_CONTROL (2106)
+			write RB_STENCIL_CONTROL (2106)
 				RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP }
 				RB_STENCIL_CONTROL2: { 0 }
 109ce018:			0000: 00012106 00000000 00000000
-t0			write RB_STENCILREFMASK (210b)
+			write RB_STENCILREFMASK (210b)
 				RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
 				RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
 109ce024:			0000: 0001210b 00000000 00000000
-t0			write RB_DEPTH_CONTROL (2101)
+			write RB_DEPTH_CONTROL (2101)
 				RB_DEPTH_CONTROL: { Z_TEST_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_ALWAYS | Z_READ_ENABLE }
 109ce030:			0000: 00002101 80000076
-t0			write GRAS_ALPHA_CONTROL (2073)
+			write GRAS_ALPHA_CONTROL (2073)
 				GRAS_ALPHA_CONTROL: { 0 }
 109ce038:			0000: 00002073 00000000
-t0			write GRAS_SU_MODE_CONTROL (2078)
+			write GRAS_SU_MODE_CONTROL (2078)
 				GRAS_SU_MODE_CONTROL: { FRONT_CW | LINEHALFWIDTH = 0.000000 | RENDERING_PASS }
 109ce040:			0000: 00002078 00100004
-t0			write GRAS_SU_POINT_MINMAX (2070)
+			write GRAS_SU_POINT_MINMAX (2070)
 				GRAS_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 }
 				GRAS_SU_POINT_SIZE: 0.000000
 109ce048:			0000: 00012070 00000000 00000000
-t0			write GRAS_SU_POLY_OFFSET_SCALE (2074)
+			write GRAS_SU_POLY_OFFSET_SCALE (2074)
 				GRAS_SU_POLY_OFFSET_SCALE: 0.000000
 				GRAS_SU_POLY_OFFSET_OFFSET: 0.000000
 				GRAS_SU_POLY_OFFSET_CLAMP: 0.000000
 109ce054:			0000: 00022074 00000000 00000000 00000000
-t0			write GRAS_CL_CLIP_CNTL (2000)
+			write GRAS_CL_CLIP_CNTL (2000)
 				GRAS_CL_CLIP_CNTL: { 0x80000 }
 109ce064:			0000: 00002000 00080000
-t0			write PC_PRIM_VTX_CNTL (21c4)
+			write PC_PRIM_VTX_CNTL (21c4)
 				PC_PRIM_VTX_CNTL: { VAROUT = 0 | PROVOKING_VTX_LAST }
 				PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES }
 109ce06c:			0000: 000121c4 02000000 00000012
-t0			write GRAS_SC_WINDOW_SCISSOR_BR (209c)
+			write GRAS_SC_WINDOW_SCISSOR_BR (209c)
 				GRAS_SC_WINDOW_SCISSOR_BR: { X = 299 | Y = 299 }
 				GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
 109ce078:			0000: 0001209c 012b012b 00000000
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 109ce084:			0000: c0002600 00000000
-t0			write GRAS_CL_VPORT_XOFFSET_0 (2008)
+			write GRAS_CL_VPORT_XOFFSET_0 (2008)
 				GRAS_CL_VPORT_XOFFSET_0: 150.000000
 				GRAS_CL_VPORT_XSCALE_0: 150.000000
 				GRAS_CL_VPORT_YOFFSET_0: 150.000000
@@ -307,78 +307,78 @@ t0			write GRAS_CL_VPORT_XOFFSET_0 (2008)
 				GRAS_CL_VPORT_ZOFFSET_0: 0.000000
 				GRAS_CL_VPORT_ZSCALE_0: 1.000000
 109ce08c:			0000: 00052008 43160000 43160000 43160000 c3160000 00000000 3f800000
-t0			write RB_VPORT_Z_CLAMP[0].MIN (2120)
+			write RB_VPORT_Z_CLAMP[0].MIN (2120)
 				RB_VPORT_Z_CLAMP[0].MIN: 0
 				RB_VPORT_Z_CLAMP[0].MAX: 0xffffff
 109ce0a8:			0000: 00012120 00000000 00ffffff
-t0			write HLSQ_UPDATE_CONTROL (23db)
+			write HLSQ_UPDATE_CONTROL (23db)
 				HLSQ_UPDATE_CONTROL: 0x3
 109ce0b4:			0000: 000023db 00000003
-t0			write HLSQ_CONTROL_0_REG (23c0)
+			write HLSQ_CONTROL_0_REG (23c0)
 				HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | SPSHADERRESTART | CONSTMODE = 1 | SPCONSTFULLUPDATE }
 				HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x }
 				HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x }
 				HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r63.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x }
 				HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 }
 109ce0bc:			0000: 000423c0 28000250 fcfc0100 fff3f3f0 fcfcfcfc 00fcfcfc
-t0			write HLSQ_VS_CONTROL_REG (23c5)
+			write HLSQ_VS_CONTROL_REG (23c5)
 				HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 1 }
 				HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 }
 				HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
 				HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
 				HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
 109ce0d4:			0000: 000423c5 01000042 017e423e 007e4200 007e4200 007e4200
-t0			write SP_SP_CTRL_REG (22c0)
+			write SP_SP_CTRL_REG (22c0)
 				SP_SP_CTRL_REG: { 0x140010 }
 109ce0ec:			0000: 000022c0 00140010
-t0			write SP_INSTR_CACHE_CTRL (22c1)
+			write SP_INSTR_CACHE_CTRL (22c1)
 				SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x7f }
 109ce0f4:			0000: 000022c1 000005ff
-t0			write SP_VS_LENGTH_REG (22e5)
+			write SP_VS_LENGTH_REG (22e5)
 				SP_VS_LENGTH_REG: 1
 109ce0fc:			0000: 000022e5 00000001
-t0			write SP_VS_CTRL_REG0 (22c4)
+			write SP_VS_CTRL_REG0 (22c4)
 				SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE }
 				SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 4 }
 				SP_VS_PARAM_REG: { POSREGID = r0.x | PSIZEREGID = r63.x | TOTALVSOUTVAR = 0 }
 109ce104:			0000: 000222c4 00200400 04000042 0000fc00
-t0			write SP_VS_OBJ_OFFSET_REG (22e0)
+			write SP_VS_OBJ_OFFSET_REG (22e0)
 				SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 }
 				SP_VS_OBJ_START: 0x1073c000
 109ce114:			0000: 000122e0 00000000 1073c000
-t0			write SP_FS_LENGTH_REG (22ef)
+			write SP_FS_LENGTH_REG (22ef)
 				SP_FS_LENGTH_REG: 1
 109ce120:			0000: 000022ef 00000001
-t0			write SP_FS_CTRL_REG0 (22e8)
+			write SP_FS_CTRL_REG0 (22e8)
 				SP_FS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE }
 				SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | 0x80000000 }
 109ce128:			0000: 000122e8 00340400 8000003e
-t0			write SP_FS_OBJ_OFFSET_REG (22ea)
+			write SP_FS_OBJ_OFFSET_REG (22ea)
 				SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
 				SP_FS_OBJ_START: 0x1073b000
 109ce134:			0000: 000122ea 7e420000 1073b000
-t0			write SP_HS_OBJ_OFFSET_REG (230d)
+			write SP_HS_OBJ_OFFSET_REG (230d)
 				SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
 109ce140:			0000: 0000230d 7e420000
-t0			write SP_DS_OBJ_OFFSET_REG (2334)
+			write SP_DS_OBJ_OFFSET_REG (2334)
 				SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
 109ce148:			0000: 00002334 7e420000
-t0			write SP_GS_OBJ_OFFSET_REG (235b)
+			write SP_GS_OBJ_OFFSET_REG (235b)
 				SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
 109ce150:			0000: 0000235b 7e420000
-t0			write GRAS_CNTL (2003)
+			write GRAS_CNTL (2003)
 				GRAS_CNTL: { 0 }
 109ce158:			0000: 00002003 00000000
-t0			write RB_RENDER_CONTROL2 (20a3)
+			write RB_RENDER_CONTROL2 (20a3)
 				RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 }
 109ce160:			0000: 000020a3 00000000
-t0			write RB_FS_OUTPUT_REG (2100)
+			write RB_FS_OUTPUT_REG (2100)
 				RB_FS_OUTPUT_REG: { MRT = 1 }
 109ce168:			0000: 00002100 00000001
-t0			write SP_FS_OUTPUT_REG (22f0)
+			write SP_FS_OUTPUT_REG (22f0)
 				SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r0.x }
 109ce170:			0000: 000022f0 0000fc01
-t0			write SP_FS_MRT[0].REG (22f1)
+			write SP_FS_MRT[0].REG (22f1)
 				SP_FS_MRT[0].REG: { REGID = r0.x | MRTFORMAT = RB4_R8G8B8A8_UNORM }
 				SP_FS_MRT[0x1].REG: { REGID = r0.x | MRTFORMAT = 0 }
 				SP_FS_MRT[0x2].REG: { REGID = r0.x | MRTFORMAT = 0 }
@@ -389,11 +389,11 @@ t0			write SP_FS_MRT[0].REG (22f1)
 				SP_FS_MRT[0x7].REG: { REGID = r0.x | MRTFORMAT = 0 }
 109ce178:			0000: 000722f1 0001a000 00000000 00000000 00000000 00000000 00000000 00000000
 *
-t0			write VPC_ATTR (2140)
+			write VPC_ATTR (2140)
 				VPC_ATTR: { TOTALATTR = 0 | THRDASSIGN = 1 | 0x40000000 }
 				VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 0 | NUMNONPOSVSVAR = 0 }
 109ce19c:			0000: 00012140 40001000 00000000
-t0			write VPC_VARYING_INTERP[0].MODE (2142)
+			write VPC_VARYING_INTERP[0].MODE (2142)
 				VPC_VARYING_INTERP[0].MODE: 0
 				VPC_VARYING_INTERP[0x1].MODE: 0
 				VPC_VARYING_INTERP[0x2].MODE: 0
@@ -404,7 +404,7 @@ t0			write VPC_VARYING_INTERP[0].MODE (2142)
 				VPC_VARYING_INTERP[0x7].MODE: 0
 109ce1a8:			0000: 00072142 00000000 00000000 00000000 00000000 00000000 00000000 00000000
 *
-t0			write VPC_VARYING_PS_REPL[0].MODE (214a)
+			write VPC_VARYING_PS_REPL[0].MODE (214a)
 				VPC_VARYING_PS_REPL[0].MODE: 0
 				VPC_VARYING_PS_REPL[0x1].MODE: 0
 				VPC_VARYING_PS_REPL[0x2].MODE: 0
@@ -415,7 +415,7 @@ t0			write VPC_VARYING_PS_REPL[0].MODE (214a)
 				VPC_VARYING_PS_REPL[0x7].MODE: 0
 109ce1cc:			0000: 0007214a 00000000 00000000 00000000 00000000 00000000 00000000 00000000
 *
-t3			opcode: CP_LOAD_STATE4 (30) (35 dwords)
+			opcode: CP_LOAD_STATE4 (30) (35 dwords)
 				{ DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 1 }
 				{ STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 }
 				:0:0000:0000[03000000x_00000000x] end
@@ -430,7 +430,7 @@ t3			opcode: CP_LOAD_STATE4 (30) (35 dwords)
 				- shaderdb: 0 sstall, 0 (ss), 0 (sy)
 109ce1f0:			0000: c0213000 00600000 00000000 00000000 03000000 00000000 00000000 00000000
 *
-t3			opcode: CP_LOAD_STATE4 (30) (35 dwords)
+			opcode: CP_LOAD_STATE4 (30) (35 dwords)
 				{ DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_SHADER | NUM_UNIT = 1 }
 				{ STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 }
 				:1:0000:0000[20244000x_00000000x] mov.f32f32 r0.x, c0.x
@@ -450,7 +450,7 @@ t3			opcode: CP_LOAD_STATE4 (30) (35 dwords)
 109ce27c:			0000: c0213000 00700000 00000000 00000000 20244000 00000001 20244001 00000002
 109ce29c:			0020: 20244002 00000003 20244003 00000000 03000000 00000000 00000000 00000000
 *
-t3			opcode: CP_LOAD_STATE4 (30) (19 dwords)
+			opcode: CP_LOAD_STATE4 (30) (19 dwords)
 				{ DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_SHADER | NUM_UNIT = 4 }
 				{ STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 }
 109ce314:				0.000000 0.000000 0.000000 0.000000     -nan     -nan 0.000000 0.000000
@@ -460,58 +460,58 @@ t3			opcode: CP_LOAD_STATE4 (30) (19 dwords)
 109ce308:			0000: c0113000 01300000 00000001 00000000 00000000 00000000 00000000 ffffffff
 109ce328:			0020: ffffffff 00000405 00000000 00000000 00000000 02070000 00000000 00000000
 *
-t0			write RB_MRT[0].CONTROL (20a4)
+			write RB_MRT[0].CONTROL (20a4)
 				RB_MRT[0].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0xf }
 109ce354:			0000: 000020a4 0f000c00
-t0			write RB_MRT[0].BLEND_CONTROL (20a8)
+			write RB_MRT[0].BLEND_CONTROL (20a8)
 				RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO }
 109ce35c:			0000: 000020a8 00000000
-t0			write RB_MRT[0x1].CONTROL (20a9)
+			write RB_MRT[0x1].CONTROL (20a9)
 				RB_MRT[0x1].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0 }
 109ce364:			0000: 000020a9 00000c00
-t0			write RB_MRT[0x1].BLEND_CONTROL (20ad)
+			write RB_MRT[0x1].BLEND_CONTROL (20ad)
 				RB_MRT[0x1].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO }
 109ce36c:			0000: 000020ad 00000000
-t0			write RB_MRT[0x2].CONTROL (20ae)
+			write RB_MRT[0x2].CONTROL (20ae)
 				RB_MRT[0x2].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0 }
 109ce374:			0000: 000020ae 00000c00
-t0			write RB_MRT[0x2].BLEND_CONTROL (20b2)
+			write RB_MRT[0x2].BLEND_CONTROL (20b2)
 				RB_MRT[0x2].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO }
 109ce37c:			0000: 000020b2 00000000
-t0			write RB_MRT[0x3].CONTROL (20b3)
+			write RB_MRT[0x3].CONTROL (20b3)
 				RB_MRT[0x3].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0 }
 109ce384:			0000: 000020b3 00000c00
-t0			write RB_MRT[0x3].BLEND_CONTROL (20b7)
+			write RB_MRT[0x3].BLEND_CONTROL (20b7)
 				RB_MRT[0x3].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO }
 109ce38c:			0000: 000020b7 00000000
-t0			write RB_MRT[0x4].CONTROL (20b8)
+			write RB_MRT[0x4].CONTROL (20b8)
 				RB_MRT[0x4].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0 }
 109ce394:			0000: 000020b8 00000c00
-t0			write RB_MRT[0x4].BLEND_CONTROL (20bc)
+			write RB_MRT[0x4].BLEND_CONTROL (20bc)
 				RB_MRT[0x4].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO }
 109ce39c:			0000: 000020bc 00000000
-t0			write RB_MRT[0x5].CONTROL (20bd)
+			write RB_MRT[0x5].CONTROL (20bd)
 				RB_MRT[0x5].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0 }
 109ce3a4:			0000: 000020bd 00000c00
-t0			write RB_MRT[0x5].BLEND_CONTROL (20c1)
+			write RB_MRT[0x5].BLEND_CONTROL (20c1)
 				RB_MRT[0x5].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO }
 109ce3ac:			0000: 000020c1 00000000
-t0			write RB_MRT[0x6].CONTROL (20c2)
+			write RB_MRT[0x6].CONTROL (20c2)
 				RB_MRT[0x6].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0 }
 109ce3b4:			0000: 000020c2 00000c00
-t0			write RB_MRT[0x6].BLEND_CONTROL (20c6)
+			write RB_MRT[0x6].BLEND_CONTROL (20c6)
 				RB_MRT[0x6].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO }
 109ce3bc:			0000: 000020c6 00000000
-t0			write RB_MRT[0x7].CONTROL (20c7)
+			write RB_MRT[0x7].CONTROL (20c7)
 				RB_MRT[0x7].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0 }
 109ce3c4:			0000: 000020c7 00000c00
-t0			write RB_MRT[0x7].BLEND_CONTROL (20cb)
+			write RB_MRT[0x7].BLEND_CONTROL (20cb)
 				RB_MRT[0x7].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO }
 109ce3cc:			0000: 000020cb 00000000
-t0			write RB_FS_OUTPUT (20f9)
+			write RB_FS_OUTPUT (20f9)
 				RB_FS_OUTPUT: { ENABLE_BLEND = 0 | INDEPENDENT_BLEND | SAMPLE_MASK = 0xffff }
 109ce3d4:			0000: 000020f9 ffff0100
-t0			write RB_BLEND_RED (20f0)
+			write RB_BLEND_RED (20f0)
 				RB_BLEND_RED: { UINT = 0 | SINT = 0 | FLOAT = 0.000000 }
 				RB_BLEND_RED_F32: 0.000000
 				RB_BLEND_GREEN: { UINT = 0 | SINT = 0 | FLOAT = 0.000000 }
@@ -522,38 +522,38 @@ t0			write RB_BLEND_RED (20f0)
 				RB_BLEND_ALPHA_F32: 0.000000
 109ce3dc:			0000: 000720f0 00000000 00000000 00000000 00000000 00000000 00000000 00000000
 *
-t0			write VFD_FETCH[0].INSTR_0 (220a)
+			write VFD_FETCH[0].INSTR_0 (220a)
 				VFD_FETCH[0].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 12 }
 				VFD_FETCH[0].INSTR_1: 0x1074a000
 				VFD_FETCH[0].INSTR_2: { SIZE = 0x1000 }
 				VFD_FETCH[0].INSTR_3: { STEPRATE = 1 }
 109ce400:			0000: 0003220a 0000060b 1074a000 00001000 00000001
-t0			write VFD_DECODE[0].INSTR (228a)
+			write VFD_DECODE[0].INSTR (228a)
 				VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID }
 109ce414:			0000: 0000228a 2c0000df
-t0			write VFD_CONTROL_0 (2200)
+			write VFD_CONTROL_0 (2200)
 				VFD_CONTROL_0: { TOTALATTRTOVS = 4 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 1 | STRMFETCHINSTRCNT = 1 | 0xa0000 }
 				VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x }
 				VFD_CONTROL_2: 0
 				VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x }
 				VFD_CONTROL_4: 0
 109ce41c:			0000: 00042200 041a0004 fcfc0081 00000000 0000fc00 00000000
-t0			write UCHE_INVALIDATE0 (0e8a)
+			write UCHE_INVALIDATE0 (0e8a)
 				UCHE_INVALIDATE0: 0
 				UCHE_INVALIDATE1: 0x12
 109ce434:			0000: 00010e8a 00000000 00000012
-t0			write VFD_INDEX_OFFSET (2208)
+			write VFD_INDEX_OFFSET (2208)
 				VFD_INDEX_OFFSET: 0
 				UNKNOWN_2209: 0
 109ce440:			0000: 00012208 00000000 00000000
-t0			write PC_RESTART_INDEX (21c6)
+			write PC_RESTART_INDEX (21c6)
 				PC_RESTART_INDEX: 0xffffffff
 109ce44c:			0000: 000021c6 ffffffff
-t0			write CP_SCRATCH[0x7].REG (057f)
+			write CP_SCRATCH[0x7].REG (057f)
 				CP_SCRATCH[0x7].REG: 0x2
 				:0,1,115,2
 109ce454:			0000: 0000057f 00000002
-t3			opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords)
+			opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords)
 				{ PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS }
 				{ NUM_INSTANCES = 1 }
 				{ NUM_INDICES = 2 }
@@ -787,57 +787,57 @@ t3			opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords)
 !+	007e4200			HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
 !+	00000003			HLSQ_UPDATE_CONTROL: 0x3
 109ce45c:			0000: c0023800 00000888 00000001 00000002
-t0			write CP_SCRATCH[0x7].REG (057f)
+			write CP_SCRATCH[0x7].REG (057f)
 				CP_SCRATCH[0x7].REG: 0x3
 				:0,1,115,3
 109ce46c:			0000: 0000057f 00000003
-t0			write CP_SCRATCH[0x5].REG (057d)
+			write CP_SCRATCH[0x5].REG (057d)
 				CP_SCRATCH[0x5].REG: 0x7
 				:0,7,115,3
 109ce474:			0000: 0000057d 00000007
-t0			write RB_ALPHA_CONTROL (20f8)
+			write RB_ALPHA_CONTROL (20f8)
 				RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_NEVER }
 109ce47c:			0000: 000020f8 00000000
-t0			write RB_STENCIL_CONTROL (2106)
+			write RB_STENCIL_CONTROL (2106)
 				RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP }
 				RB_STENCIL_CONTROL2: { 0 }
 109ce484:			0000: 00012106 00000000 00000000
-t0			write RB_STENCILREFMASK (210b)
+			write RB_STENCILREFMASK (210b)
 				RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
 				RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
 109ce490:			0000: 0001210b 00000000 00000000
-t0			write RB_DEPTH_CONTROL (2101)
+			write RB_DEPTH_CONTROL (2101)
 				RB_DEPTH_CONTROL: { Z_TEST_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_READ_ENABLE }
 109ce49c:			0000: 00002101 80000016
-t0			write GRAS_ALPHA_CONTROL (2073)
+			write GRAS_ALPHA_CONTROL (2073)
 				GRAS_ALPHA_CONTROL: { 0 }
 109ce4a4:			0000: 00002073 00000000
-t0			write GRAS_SU_MODE_CONTROL (2078)
+			write GRAS_SU_MODE_CONTROL (2078)
 				GRAS_SU_MODE_CONTROL: { CULL_BACK | LINEHALFWIDTH = 0.500000 | RENDERING_PASS }
 109ce4ac:			0000: 00002078 00100012
-t0			write GRAS_SU_POINT_MINMAX (2070)
+			write GRAS_SU_POINT_MINMAX (2070)
 				GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 1.000000 }
 				GRAS_SU_POINT_SIZE: 1.000000
 109ce4b4:			0000: 00012070 00100010 00000010
-t0			write GRAS_SU_POLY_OFFSET_SCALE (2074)
+			write GRAS_SU_POLY_OFFSET_SCALE (2074)
 				GRAS_SU_POLY_OFFSET_SCALE: 0.000000
 				GRAS_SU_POLY_OFFSET_OFFSET: 0.000000
 				GRAS_SU_POLY_OFFSET_CLAMP: 0.000000
 109ce4c0:			0000: 00022074 00000000 00000000 00000000
-t0			write GRAS_CL_CLIP_CNTL (2000)
+			write GRAS_CL_CLIP_CNTL (2000)
 				GRAS_CL_CLIP_CNTL: { 0x80000 }
 109ce4d0:			0000: 00002000 00080000
-t0			write PC_PRIM_VTX_CNTL (21c4)
+			write PC_PRIM_VTX_CNTL (21c4)
 				PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST }
 				PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES }
 109ce4d8:			0000: 000121c4 02000001 00000012
-t0			write GRAS_SC_WINDOW_SCISSOR_BR (209c)
+			write GRAS_SC_WINDOW_SCISSOR_BR (209c)
 				GRAS_SC_WINDOW_SCISSOR_BR: { X = 299 | Y = 299 }
 				GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
 109ce4e4:			0000: 0001209c 012b012b 00000000
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 109ce4f0:			0000: c0002600 00000000
-t0			write GRAS_CL_VPORT_XOFFSET_0 (2008)
+			write GRAS_CL_VPORT_XOFFSET_0 (2008)
 				GRAS_CL_VPORT_XOFFSET_0: 150.000000
 				GRAS_CL_VPORT_XSCALE_0: 150.000000
 				GRAS_CL_VPORT_YOFFSET_0: 150.000000
@@ -845,84 +845,84 @@ t0			write GRAS_CL_VPORT_XOFFSET_0 (2008)
 				GRAS_CL_VPORT_ZOFFSET_0: 0.500000
 				GRAS_CL_VPORT_ZSCALE_0: 0.500000
 109ce4f8:			0000: 00052008 43160000 43160000 43160000 c3160000 3f000000 3f000000
-t0			write RB_VPORT_Z_CLAMP[0].MIN (2120)
+			write RB_VPORT_Z_CLAMP[0].MIN (2120)
 				RB_VPORT_Z_CLAMP[0].MIN: 0
 				RB_VPORT_Z_CLAMP[0].MAX: 0xffffff
 109ce514:			0000: 00012120 00000000 00ffffff
-t0			write HLSQ_UPDATE_CONTROL (23db)
+			write HLSQ_UPDATE_CONTROL (23db)
 				HLSQ_UPDATE_CONTROL: 0x3
 109ce520:			0000: 000023db 00000003
-t0			write HLSQ_CONTROL_0_REG (23c0)
+			write HLSQ_CONTROL_0_REG (23c0)
 				HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | SPSHADERRESTART | CONSTMODE = 1 | SPCONSTFULLUPDATE }
 				HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x }
 				HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x }
 				HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r63.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x }
 				HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 }
 109ce528:			0000: 000423c0 28000250 fcfc0100 fff3f3f0 fcfcfcfc 00fcfcfc
-t0			write HLSQ_VS_CONTROL_REG (23c5)
+			write HLSQ_VS_CONTROL_REG (23c5)
 				HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 4 }
 				HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 }
 				HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
 				HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
 				HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
 109ce540:			0000: 000423c5 04000042 017e423e 007e4200 007e4200 007e4200
-t0			write SP_SP_CTRL_REG (22c0)
+			write SP_SP_CTRL_REG (22c0)
 				SP_SP_CTRL_REG: { 0x140010 }
 109ce558:			0000: 000022c0 00140010
-t0			write SP_INSTR_CACHE_CTRL (22c1)
+			write SP_INSTR_CACHE_CTRL (22c1)
 				SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x7f }
 109ce560:			0000: 000022c1 000005ff
-t0			write SP_VS_LENGTH_REG (22e5)
+			write SP_VS_LENGTH_REG (22e5)
 				SP_VS_LENGTH_REG: 4
 109ce568:			0000: 000022e5 00000004
-t0			write SP_VS_CTRL_REG0 (22c4)
+			write SP_VS_CTRL_REG0 (22c4)
 				SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 4 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE }
 				SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 4 }
 				SP_VS_PARAM_REG: { POSREGID = r1.z | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 }
 109ce570:			0000: 000222c4 00201000 04000042 0010fc06
-t0			write SP_VS_OUT[0].REG (22c7)
+			write SP_VS_OUT[0].REG (22c7)
 				SP_VS_OUT[0].REG: { A_REGID = r2.z | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 }
 109ce580:			0000: 000022c7 00001e0a
-t0			write SP_VS_VPC_DST[0].REG (22d8)
+			write SP_VS_VPC_DST[0].REG (22d8)
 				SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 8 | OUTLOC2 = 8 | OUTLOC3 = 8 }
 109ce588:			0000: 000022d8 08080808
-t0			write SP_VS_OBJ_OFFSET_REG (22e0)
+			write SP_VS_OBJ_OFFSET_REG (22e0)
 				SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 }
 				SP_VS_OBJ_START: 0x10cd0000
 109ce590:			0000: 000122e0 00000000 10cd0000
-t0			write SP_FS_LENGTH_REG (22ef)
+			write SP_FS_LENGTH_REG (22ef)
 				SP_FS_LENGTH_REG: 1
 109ce59c:			0000: 000022ef 00000001
-t0			write SP_FS_CTRL_REG0 (22e8)
+			write SP_FS_CTRL_REG0 (22e8)
 				SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE }
 				SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 }
 109ce5a4:			0000: 000122e8 00340402 8010003e
-t0			write SP_FS_OBJ_OFFSET_REG (22ea)
+			write SP_FS_OBJ_OFFSET_REG (22ea)
 				SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
 				SP_FS_OBJ_START: 0x10cd2000
 109ce5b0:			0000: 000122ea 7e420000 10cd2000
-t0			write SP_HS_OBJ_OFFSET_REG (230d)
+			write SP_HS_OBJ_OFFSET_REG (230d)
 				SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
 109ce5bc:			0000: 0000230d 7e420000
-t0			write SP_DS_OBJ_OFFSET_REG (2334)
+			write SP_DS_OBJ_OFFSET_REG (2334)
 				SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
 109ce5c4:			0000: 00002334 7e420000
-t0			write SP_GS_OBJ_OFFSET_REG (235b)
+			write SP_GS_OBJ_OFFSET_REG (235b)
 				SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
 109ce5cc:			0000: 0000235b 7e420000
-t0			write GRAS_CNTL (2003)
+			write GRAS_CNTL (2003)
 				GRAS_CNTL: { 0 }
 109ce5d4:			0000: 00002003 00000000
-t0			write RB_RENDER_CONTROL2 (20a3)
+			write RB_RENDER_CONTROL2 (20a3)
 				RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 }
 109ce5dc:			0000: 000020a3 00000000
-t0			write RB_FS_OUTPUT_REG (2100)
+			write RB_FS_OUTPUT_REG (2100)
 				RB_FS_OUTPUT_REG: { MRT = 1 }
 109ce5e4:			0000: 00002100 00000001
-t0			write SP_FS_OUTPUT_REG (22f0)
+			write SP_FS_OUTPUT_REG (22f0)
 				SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r0.x }
 109ce5ec:			0000: 000022f0 0000fc01
-t0			write SP_FS_MRT[0].REG (22f1)
+			write SP_FS_MRT[0].REG (22f1)
 				SP_FS_MRT[0].REG: { REGID = r0.x | MRTFORMAT = RB4_R8G8B8A8_UNORM }
 				SP_FS_MRT[0x1].REG: { REGID = r0.x | MRTFORMAT = 0 }
 				SP_FS_MRT[0x2].REG: { REGID = r0.x | MRTFORMAT = 0 }
@@ -933,11 +933,11 @@ t0			write SP_FS_MRT[0].REG (22f1)
 				SP_FS_MRT[0x7].REG: { REGID = r0.x | MRTFORMAT = 0 }
 109ce5f4:			0000: 000722f1 0001a000 00000000 00000000 00000000 00000000 00000000 00000000
 *
-t0			write VPC_ATTR (2140)
+			write VPC_ATTR (2140)
 				VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 }
 				VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 }
 109ce618:			0000: 00012140 42001004 00040400
-t0			write VPC_VARYING_INTERP[0].MODE (2142)
+			write VPC_VARYING_INTERP[0].MODE (2142)
 				VPC_VARYING_INTERP[0].MODE: 0x55
 				VPC_VARYING_INTERP[0x1].MODE: 0
 				VPC_VARYING_INTERP[0x2].MODE: 0
@@ -948,7 +948,7 @@ t0			write VPC_VARYING_INTERP[0].MODE (2142)
 				VPC_VARYING_INTERP[0x7].MODE: 0
 109ce624:			0000: 00072142 00000055 00000000 00000000 00000000 00000000 00000000 00000000
 *
-t0			write VPC_VARYING_PS_REPL[0].MODE (214a)
+			write VPC_VARYING_PS_REPL[0].MODE (214a)
 				VPC_VARYING_PS_REPL[0].MODE: 0
 				VPC_VARYING_PS_REPL[0x1].MODE: 0
 				VPC_VARYING_PS_REPL[0x2].MODE: 0
@@ -959,7 +959,7 @@ t0			write VPC_VARYING_PS_REPL[0].MODE (214a)
 				VPC_VARYING_PS_REPL[0x7].MODE: 0
 109ce648:			0000: 0007214a 00000000 00000000 00000000 00000000 00000000 00000000 00000000
 *
-t3			opcode: CP_LOAD_STATE4 (30) (131 dwords)
+			opcode: CP_LOAD_STATE4 (30) (131 dwords)
 				{ DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 4 }
 				{ STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 }
 				:2:0000:0000[40700000x_10000002x] mul.f r0.x, r0.z, c0.x
@@ -1044,7 +1044,7 @@ t3			opcode: CP_LOAD_STATE4 (30) (131 dwords)
 109ce80c:			01a0: 63800001 00021025 63800002 00031026 63800000 00011028 6382040a 00021029
 109ce82c:			01c0: 6382040b 0000102a 6382040c 00000000 03000000 00000000 00000000 00000000
 *
-t3			opcode: CP_LOAD_STATE4 (30) (35 dwords)
+			opcode: CP_LOAD_STATE4 (30) (35 dwords)
 				{ DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_SHADER | NUM_UNIT = 1 }
 				{ STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 }
 				:0:0000:0000[00000000x_00000000x] nop
@@ -1067,7 +1067,7 @@ t3			opcode: CP_LOAD_STATE4 (30) (35 dwords)
 109ce898:			0020: c7c60001 01c00004 c7c60002 01c00006 c7c60003 00002000 473090fc 00000000
 109ce8b8:			0040: 03000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
 *
-t3			opcode: CP_LOAD_STATE4 (30) (51 dwords)
+			opcode: CP_LOAD_STATE4 (30) (51 dwords)
 				{ DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 12 }
 				{ STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 }
 109ce910:				4.330127 0.855050 0.555273 0.469846 0.000000 4.698463 -0.404206 -0.342020
@@ -1089,95 +1089,95 @@ t3			opcode: CP_LOAD_STATE4 (30) (51 dwords)
 109ce984:			0080: 00000000 00000000 00000000 00000000 00000000 00000000 3f800000 3f4ccccd
 109ce9a4:			00a0: 3dcccccd 00000000 3f800000 00000000 00000000 00000000 3f800000 00000000
 109ce9c4:			00c0: 00000000 00000000 3f800000
-t3			opcode: CP_LOAD_STATE4 (30) (7 dwords)
+			opcode: CP_LOAD_STATE4 (30) (7 dwords)
 				{ DST_OFF = 13 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 1 }
 				{ STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 }
 109ce9dc:				0.000000 -28026765312.000000 -28026765312.000000 -28026765312.000000
 109ce9dc:				0000: 00000000 d0d0d0d0 d0d0d0d0 d0d0d0d0
 109ce9d0:			0000: c0053000 0060000d 00000001 00000000 d0d0d0d0 d0d0d0d0 d0d0d0d0
-t0			write RB_MRT[0].CONTROL (20a4)
+			write RB_MRT[0].CONTROL (20a4)
 				RB_MRT[0].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0xf }
 109ce9ec:			0000: 000020a4 0f000c00
-t0			write RB_MRT[0].BLEND_CONTROL (20a8)
+			write RB_MRT[0].BLEND_CONTROL (20a8)
 				RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO }
 109ce9f4:			0000: 000020a8 00000000
-t0			write RB_MRT[0x1].CONTROL (20a9)
+			write RB_MRT[0x1].CONTROL (20a9)
 				RB_MRT[0x1].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0xf }
 109ce9fc:			0000: 000020a9 0f000c00
-t0			write RB_MRT[0x1].BLEND_CONTROL (20ad)
+			write RB_MRT[0x1].BLEND_CONTROL (20ad)
 				RB_MRT[0x1].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO }
 109cea04:			0000: 000020ad 00000000
-t0			write RB_MRT[0x2].CONTROL (20ae)
+			write RB_MRT[0x2].CONTROL (20ae)
 				RB_MRT[0x2].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0xf }
 109cea0c:			0000: 000020ae 0f000c00
-t0			write RB_MRT[0x2].BLEND_CONTROL (20b2)
+			write RB_MRT[0x2].BLEND_CONTROL (20b2)
 				RB_MRT[0x2].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO }
 109cea14:			0000: 000020b2 00000000
-t0			write RB_MRT[0x3].CONTROL (20b3)
+			write RB_MRT[0x3].CONTROL (20b3)
 				RB_MRT[0x3].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0xf }
 109cea1c:			0000: 000020b3 0f000c00
-t0			write RB_MRT[0x3].BLEND_CONTROL (20b7)
+			write RB_MRT[0x3].BLEND_CONTROL (20b7)
 				RB_MRT[0x3].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO }
 109cea24:			0000: 000020b7 00000000
-t0			write RB_MRT[0x4].CONTROL (20b8)
+			write RB_MRT[0x4].CONTROL (20b8)
 				RB_MRT[0x4].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0xf }
 109cea2c:			0000: 000020b8 0f000c00
-t0			write RB_MRT[0x4].BLEND_CONTROL (20bc)
+			write RB_MRT[0x4].BLEND_CONTROL (20bc)
 				RB_MRT[0x4].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO }
 109cea34:			0000: 000020bc 00000000
-t0			write RB_MRT[0x5].CONTROL (20bd)
+			write RB_MRT[0x5].CONTROL (20bd)
 				RB_MRT[0x5].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0xf }
 109cea3c:			0000: 000020bd 0f000c00
-t0			write RB_MRT[0x5].BLEND_CONTROL (20c1)
+			write RB_MRT[0x5].BLEND_CONTROL (20c1)
 				RB_MRT[0x5].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO }
 109cea44:			0000: 000020c1 00000000
-t0			write RB_MRT[0x6].CONTROL (20c2)
+			write RB_MRT[0x6].CONTROL (20c2)
 				RB_MRT[0x6].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0xf }
 109cea4c:			0000: 000020c2 0f000c00
-t0			write RB_MRT[0x6].BLEND_CONTROL (20c6)
+			write RB_MRT[0x6].BLEND_CONTROL (20c6)
 				RB_MRT[0x6].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO }
 109cea54:			0000: 000020c6 00000000
-t0			write RB_MRT[0x7].CONTROL (20c7)
+			write RB_MRT[0x7].CONTROL (20c7)
 				RB_MRT[0x7].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0xf }
 109cea5c:			0000: 000020c7 0f000c00
-t0			write RB_MRT[0x7].BLEND_CONTROL (20cb)
+			write RB_MRT[0x7].BLEND_CONTROL (20cb)
 				RB_MRT[0x7].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO }
 109cea64:			0000: 000020cb 00000000
-t0			write RB_FS_OUTPUT (20f9)
+			write RB_FS_OUTPUT (20f9)
 				RB_FS_OUTPUT: { ENABLE_BLEND = 0 | SAMPLE_MASK = 0xffff }
 109cea6c:			0000: 000020f9 ffff0000
-t0			write VFD_FETCH[0].INSTR_0 (220a)
+			write VFD_FETCH[0].INSTR_0 (220a)
 				VFD_FETCH[0].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 12 }
 				VFD_FETCH[0].INSTR_1: 0x107cb000
 				VFD_FETCH[0].INSTR_2: { SIZE = 0x100000 }
 				VFD_FETCH[0].INSTR_3: { STEPRATE = 1 }
 109cea74:			0000: 0003220a 0000060b 107cb000 00100000 00000001
-t0			write VFD_DECODE[0].INSTR (228a)
+			write VFD_DECODE[0].INSTR (228a)
 				VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_FLOAT | REGID = r0.z | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID }
 109cea88:			0000: 0000228a 2c0020df
-t0			write VFD_CONTROL_0 (2200)
+			write VFD_CONTROL_0 (2200)
 				VFD_CONTROL_0: { TOTALATTRTOVS = 4 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 1 | STRMFETCHINSTRCNT = 1 | 0xa0000 }
 				VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x }
 				VFD_CONTROL_2: 0
 				VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x }
 				VFD_CONTROL_4: 0
 109cea90:			0000: 00042200 041a0004 fcfc0081 00000000 0000fc00 00000000
-t0			write UCHE_INVALIDATE0 (0e8a)
+			write UCHE_INVALIDATE0 (0e8a)
 				UCHE_INVALIDATE0: 0
 				UCHE_INVALIDATE1: 0x12
 109ceaa8:			0000: 00010e8a 00000000 00000012
-t0			write VFD_INDEX_OFFSET (2208)
+			write VFD_INDEX_OFFSET (2208)
 				VFD_INDEX_OFFSET: 0
 				UNKNOWN_2209: 0
 109ceab4:			0000: 00012208 00000000 00000000
-t0			write PC_RESTART_INDEX (21c6)
+			write PC_RESTART_INDEX (21c6)
 				PC_RESTART_INDEX: 0xffffffff
 109ceac0:			0000: 000021c6 ffffffff
-t0			write CP_SCRATCH[0x7].REG (057f)
+			write CP_SCRATCH[0x7].REG (057f)
 				CP_SCRATCH[0x7].REG: 0x8
 				:0,7,115,8
 109ceac8:			0000: 0000057f 00000008
-t3			opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords)
+			opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords)
 				{ PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_16_BIT | PATCH_TYPE = TESS_QUADS }
 				{ NUM_INSTANCES = 1 }
 				{ NUM_INDICES = 240 }
@@ -1307,30 +1307,30 @@ t3			opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords)
  +	007e4200			HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
  +	00000003			HLSQ_UPDATE_CONTROL: 0x3
 109cead0:			0000: c0053800 00000404 00000001 000000f0 00000000 10bd0000 000001e0
-t0			write CP_SCRATCH[0x7].REG (057f)
+			write CP_SCRATCH[0x7].REG (057f)
 				CP_SCRATCH[0x7].REG: 0x9
 				:0,7,115,9
 109ceaec:			0000: 0000057f 00000009
-t0			write CP_SCRATCH[0x5].REG (057d)
+			write CP_SCRATCH[0x5].REG (057d)
 				CP_SCRATCH[0x5].REG: 0xd
 				:0,13,115,9
 109ceaf4:			0000: 0000057d 0000000d
-t0			write PC_PRIM_VTX_CNTL (21c4)
+			write PC_PRIM_VTX_CNTL (21c4)
 				PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST }
 				PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES }
 109ceafc:			0000: 000121c4 02000001 00000012
-t0			write VFD_INDEX_OFFSET (2208)
+			write VFD_INDEX_OFFSET (2208)
 				VFD_INDEX_OFFSET: 0
 				UNKNOWN_2209: 0
 109ceb08:			0000: 00012208 00000000 00000000
-t0			write PC_RESTART_INDEX (21c6)
+			write PC_RESTART_INDEX (21c6)
 				PC_RESTART_INDEX: 0xffffffff
 109ceb14:			0000: 000021c6 ffffffff
-t0			write CP_SCRATCH[0x7].REG (057f)
+			write CP_SCRATCH[0x7].REG (057f)
 				CP_SCRATCH[0x7].REG: 0xe
 				:0,13,115,14
 109ceb1c:			0000: 0000057f 0000000e
-t3			opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords)
+			opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords)
 				{ PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_16_BIT | PATCH_TYPE = TESS_QUADS }
 				{ NUM_INSTANCES = 1 }
 				{ NUM_INDICES = 120 }
@@ -1348,21 +1348,21 @@ t3			opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords)
  +	00000000			VFD_INDEX_OFFSET: 0
  +	00000000			UNKNOWN_2209: 0
 109ceb24:			0000: c0053800 00000404 00000001 00000078 00000000 10bd01e0 000000f0
-t0			write CP_SCRATCH[0x7].REG (057f)
+			write CP_SCRATCH[0x7].REG (057f)
 				CP_SCRATCH[0x7].REG: 0xf
 				:0,13,115,15
 109ceb40:			0000: 0000057f 0000000f
-t0			write CP_SCRATCH[0x5].REG (057d)
+			write CP_SCRATCH[0x5].REG (057d)
 				CP_SCRATCH[0x5].REG: 0x13
 				:0,19,115,15
 109ceb48:			0000: 0000057d 00000013
-t0			write PC_PRIM_VTX_CNTL (21c4)
+			write PC_PRIM_VTX_CNTL (21c4)
 				PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST }
 				PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES }
 109ceb50:			0000: 000121c4 02000001 00000012
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 109ceb5c:			0000: c0002600 00000000
-t3			opcode: CP_LOAD_STATE4 (30) (51 dwords)
+			opcode: CP_LOAD_STATE4 (30) (51 dwords)
 				{ DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 12 }
 				{ STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 }
 109ceb70:				4.330127 0.855050 0.555273 0.469846 0.000000 4.698463 -0.404206 -0.342020
@@ -1384,18 +1384,18 @@ t3			opcode: CP_LOAD_STATE4 (30) (51 dwords)
 109cebe4:			0080: 00000000 00000000 00000000 00000000 00000000 00000000 3f800000 3f4ccccd
 109cec04:			00a0: 3dcccccd 00000000 3f800000 00000000 00000000 00000000 3f800000 00000000
 109cec24:			00c0: 00000000 00000000 3f800000
-t0			write VFD_INDEX_OFFSET (2208)
+			write VFD_INDEX_OFFSET (2208)
 				VFD_INDEX_OFFSET: 0
 				UNKNOWN_2209: 0
 109cec30:			0000: 00012208 00000000 00000000
-t0			write PC_RESTART_INDEX (21c6)
+			write PC_RESTART_INDEX (21c6)
 				PC_RESTART_INDEX: 0xffffffff
 109cec3c:			0000: 000021c6 ffffffff
-t0			write CP_SCRATCH[0x7].REG (057f)
+			write CP_SCRATCH[0x7].REG (057f)
 				CP_SCRATCH[0x7].REG: 0x14
 				:0,19,115,20
 109cec44:			0000: 0000057f 00000014
-t3			opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords)
+			opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords)
 				{ PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_16_BIT | PATCH_TYPE = TESS_QUADS }
 				{ NUM_INSTANCES = 1 }
 				{ NUM_INDICES = 240 }
@@ -1413,30 +1413,30 @@ t3			opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords)
  +	00000000			VFD_INDEX_OFFSET: 0
  +	00000000			UNKNOWN_2209: 0
 109cec4c:			0000: c0053800 00000404 00000001 000000f0 00000000 10bd02d0 000001e0
-t0			write CP_SCRATCH[0x7].REG (057f)
+			write CP_SCRATCH[0x7].REG (057f)
 				CP_SCRATCH[0x7].REG: 0x15
 				:0,19,115,21
 109cec68:			0000: 0000057f 00000015
-t0			write CP_SCRATCH[0x5].REG (057d)
+			write CP_SCRATCH[0x5].REG (057d)
 				CP_SCRATCH[0x5].REG: 0x19
 				:0,25,115,21
 109cec70:			0000: 0000057d 00000019
-t0			write PC_PRIM_VTX_CNTL (21c4)
+			write PC_PRIM_VTX_CNTL (21c4)
 				PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST }
 				PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES }
 109cec78:			0000: 000121c4 02000001 00000012
-t0			write VFD_INDEX_OFFSET (2208)
+			write VFD_INDEX_OFFSET (2208)
 				VFD_INDEX_OFFSET: 0
 				UNKNOWN_2209: 0
 109cec84:			0000: 00012208 00000000 00000000
-t0			write PC_RESTART_INDEX (21c6)
+			write PC_RESTART_INDEX (21c6)
 				PC_RESTART_INDEX: 0xffffffff
 109cec90:			0000: 000021c6 ffffffff
-t0			write CP_SCRATCH[0x7].REG (057f)
+			write CP_SCRATCH[0x7].REG (057f)
 				CP_SCRATCH[0x7].REG: 0x1a
 				:0,25,115,26
 109cec98:			0000: 0000057f 0000001a
-t3			opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords)
+			opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords)
 				{ PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_16_BIT | PATCH_TYPE = TESS_QUADS }
 				{ NUM_INSTANCES = 1 }
 				{ NUM_INDICES = 120 }
@@ -1454,98 +1454,98 @@ t3			opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords)
  +	00000000			VFD_INDEX_OFFSET: 0
  +	00000000			UNKNOWN_2209: 0
 109ceca0:			0000: c0053800 00000404 00000001 00000078 00000000 10bd04b0 000000f0
-t0			write CP_SCRATCH[0x7].REG (057f)
+			write CP_SCRATCH[0x7].REG (057f)
 				CP_SCRATCH[0x7].REG: 0x1b
 				:0,25,115,27
 109cecbc:			0000: 0000057f 0000001b
-t0			write CP_SCRATCH[0x5].REG (057d)
+			write CP_SCRATCH[0x5].REG (057d)
 				CP_SCRATCH[0x5].REG: 0x1f
 				:0,31,115,27
 109cecc4:			0000: 0000057d 0000001f
-t0			write RB_DEPTH_CONTROL (2101)
+			write RB_DEPTH_CONTROL (2101)
 				RB_DEPTH_CONTROL: { Z_TEST_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_READ_ENABLE }
 109ceccc:			0000: 00002101 80000016
-t0			write GRAS_ALPHA_CONTROL (2073)
+			write GRAS_ALPHA_CONTROL (2073)
 				GRAS_ALPHA_CONTROL: { 0 }
 109cecd4:			0000: 00002073 00000000
-t0			write PC_PRIM_VTX_CNTL (21c4)
+			write PC_PRIM_VTX_CNTL (21c4)
 				PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST }
 				PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES }
 109cecdc:			0000: 000121c4 02000001 00000012
-t0			write HLSQ_UPDATE_CONTROL (23db)
+			write HLSQ_UPDATE_CONTROL (23db)
 				HLSQ_UPDATE_CONTROL: 0x3
 109cece8:			0000: 000023db 00000003
-t0			write HLSQ_CONTROL_0_REG (23c0)
+			write HLSQ_CONTROL_0_REG (23c0)
 				HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | SPSHADERRESTART | CONSTMODE = 1 | SPCONSTFULLUPDATE }
 				HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x }
 				HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x }
 				HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r63.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x }
 				HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 }
 109cecf0:			0000: 000423c0 28000250 fcfc0100 fff3f3f0 fcfcfcfc 00fcfcfc
-t0			write HLSQ_VS_CONTROL_REG (23c5)
+			write HLSQ_VS_CONTROL_REG (23c5)
 				HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 4 }
 				HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 }
 				HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
 				HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
 				HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
 109ced08:			0000: 000423c5 04000042 017e423e 007e4200 007e4200 007e4200
-t0			write SP_SP_CTRL_REG (22c0)
+			write SP_SP_CTRL_REG (22c0)
 				SP_SP_CTRL_REG: { 0x140010 }
 109ced20:			0000: 000022c0 00140010
-t0			write SP_INSTR_CACHE_CTRL (22c1)
+			write SP_INSTR_CACHE_CTRL (22c1)
 				SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x7f }
 109ced28:			0000: 000022c1 000005ff
-t0			write SP_VS_LENGTH_REG (22e5)
+			write SP_VS_LENGTH_REG (22e5)
 				SP_VS_LENGTH_REG: 4
 109ced30:			0000: 000022e5 00000004
-t0			write SP_VS_CTRL_REG0 (22c4)
+			write SP_VS_CTRL_REG0 (22c4)
 				SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 5 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE }
 				SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 8 }
 				SP_VS_PARAM_REG: { POSREGID = r2.z | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 }
 109ced38:			0000: 000222c4 00201400 08000042 0010fc0a
-t0			write SP_VS_OUT[0].REG (22c7)
+			write SP_VS_OUT[0].REG (22c7)
 				SP_VS_OUT[0].REG: { A_REGID = r3.z | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 }
 109ced48:			0000: 000022c7 00001e0e
-t0			write SP_VS_VPC_DST[0].REG (22d8)
+			write SP_VS_VPC_DST[0].REG (22d8)
 				SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 8 | OUTLOC2 = 8 | OUTLOC3 = 8 }
 109ced50:			0000: 000022d8 08080808
-t0			write SP_VS_OBJ_OFFSET_REG (22e0)
+			write SP_VS_OBJ_OFFSET_REG (22e0)
 				SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 }
 				SP_VS_OBJ_START: 0x10cd5000
 109ced58:			0000: 000122e0 00000000 10cd5000
-t0			write SP_FS_LENGTH_REG (22ef)
+			write SP_FS_LENGTH_REG (22ef)
 				SP_FS_LENGTH_REG: 1
 109ced64:			0000: 000022ef 00000001
-t0			write SP_FS_CTRL_REG0 (22e8)
+			write SP_FS_CTRL_REG0 (22e8)
 				SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE }
 				SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 }
 109ced6c:			0000: 000122e8 00340402 8010003e
-t0			write SP_FS_OBJ_OFFSET_REG (22ea)
+			write SP_FS_OBJ_OFFSET_REG (22ea)
 				SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
 				SP_FS_OBJ_START: 0x10cd2000
 109ced78:			0000: 000122ea 7e420000 10cd2000
-t0			write SP_HS_OBJ_OFFSET_REG (230d)
+			write SP_HS_OBJ_OFFSET_REG (230d)
 				SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
 109ced84:			0000: 0000230d 7e420000
-t0			write SP_DS_OBJ_OFFSET_REG (2334)
+			write SP_DS_OBJ_OFFSET_REG (2334)
 				SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
 109ced8c:			0000: 00002334 7e420000
-t0			write SP_GS_OBJ_OFFSET_REG (235b)
+			write SP_GS_OBJ_OFFSET_REG (235b)
 				SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
 109ced94:			0000: 0000235b 7e420000
-t0			write GRAS_CNTL (2003)
+			write GRAS_CNTL (2003)
 				GRAS_CNTL: { 0 }
 109ced9c:			0000: 00002003 00000000
-t0			write RB_RENDER_CONTROL2 (20a3)
+			write RB_RENDER_CONTROL2 (20a3)
 				RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 }
 109ceda4:			0000: 000020a3 00000000
-t0			write RB_FS_OUTPUT_REG (2100)
+			write RB_FS_OUTPUT_REG (2100)
 				RB_FS_OUTPUT_REG: { MRT = 1 }
 109cedac:			0000: 00002100 00000001
-t0			write SP_FS_OUTPUT_REG (22f0)
+			write SP_FS_OUTPUT_REG (22f0)
 				SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r0.x }
 109cedb4:			0000: 000022f0 0000fc01
-t0			write SP_FS_MRT[0].REG (22f1)
+			write SP_FS_MRT[0].REG (22f1)
 				SP_FS_MRT[0].REG: { REGID = r0.x | MRTFORMAT = RB4_R8G8B8A8_UNORM }
 				SP_FS_MRT[0x1].REG: { REGID = r0.x | MRTFORMAT = 0 }
 				SP_FS_MRT[0x2].REG: { REGID = r0.x | MRTFORMAT = 0 }
@@ -1556,11 +1556,11 @@ t0			write SP_FS_MRT[0].REG (22f1)
 				SP_FS_MRT[0x7].REG: { REGID = r0.x | MRTFORMAT = 0 }
 109cedbc:			0000: 000722f1 0001a000 00000000 00000000 00000000 00000000 00000000 00000000
 *
-t0			write VPC_ATTR (2140)
+			write VPC_ATTR (2140)
 				VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 }
 				VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 }
 109cede0:			0000: 00012140 42001004 00040400
-t0			write VPC_VARYING_INTERP[0].MODE (2142)
+			write VPC_VARYING_INTERP[0].MODE (2142)
 				VPC_VARYING_INTERP[0].MODE: 0x55
 				VPC_VARYING_INTERP[0x1].MODE: 0
 				VPC_VARYING_INTERP[0x2].MODE: 0
@@ -1571,7 +1571,7 @@ t0			write VPC_VARYING_INTERP[0].MODE (2142)
 				VPC_VARYING_INTERP[0x7].MODE: 0
 109cedec:			0000: 00072142 00000055 00000000 00000000 00000000 00000000 00000000 00000000
 *
-t0			write VPC_VARYING_PS_REPL[0].MODE (214a)
+			write VPC_VARYING_PS_REPL[0].MODE (214a)
 				VPC_VARYING_PS_REPL[0].MODE: 0
 				VPC_VARYING_PS_REPL[0x1].MODE: 0
 				VPC_VARYING_PS_REPL[0x2].MODE: 0
@@ -1582,7 +1582,7 @@ t0			write VPC_VARYING_PS_REPL[0].MODE (214a)
 				VPC_VARYING_PS_REPL[0x7].MODE: 0
 109cee10:			0000: 0007214a 00000000 00000000 00000000 00000000 00000000 00000000 00000000
 *
-t3			opcode: CP_LOAD_STATE4 (30) (131 dwords)
+			opcode: CP_LOAD_STATE4 (30) (131 dwords)
 				{ DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 4 }
 				{ STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 }
 				:2:0000:0000[40700000x_10000002x] mul.f r0.x, r0.z, c0.x
@@ -1661,7 +1661,7 @@ t3			opcode: CP_LOAD_STATE4 (30) (131 dwords)
 109cefb4:			0180: 63800002 00031022 63800000 00011024 6382040e 00021025 6382040f 00001026
 109cefd4:			01a0: 63820410 00000000 03000000 00000000 00000000 00000000 00000000 00000000
 *
-t3			opcode: CP_LOAD_STATE4 (30) (35 dwords)
+			opcode: CP_LOAD_STATE4 (30) (35 dwords)
 				{ DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_SHADER | NUM_UNIT = 1 }
 				{ STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 }
 				:0:0000:0000[00000000x_00000000x] nop
@@ -1684,9 +1684,9 @@ t3			opcode: CP_LOAD_STATE4 (30) (35 dwords)
 109cf060:			0020: c7c60001 01c00004 c7c60002 01c00006 c7c60003 00002000 473090fc 00000000
 109cf080:			0040: 03000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
 *
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 109cf0cc:			0000: c0002600 00000000
-t3			opcode: CP_LOAD_STATE4 (30) (51 dwords)
+			opcode: CP_LOAD_STATE4 (30) (51 dwords)
 				{ DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 12 }
 				{ STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 }
 109cf0e0:				4.330127 0.855050 0.555273 0.469846 0.000000 4.698463 -0.404206 -0.342020
@@ -1708,53 +1708,53 @@ t3			opcode: CP_LOAD_STATE4 (30) (51 dwords)
 109cf154:			0080: 00000000 00000000 3f800000 3f4ccccd 3dcccccd 00000000 3f800000 00000000
 109cf174:			00a0: 00000000 00000000 3f800000 00000000 00000000 00000000 3f800000 02020000
 109cf194:			00c0: 02020202 02020202 00000202
-t3			opcode: CP_LOAD_STATE4 (30) (7 dwords)
+			opcode: CP_LOAD_STATE4 (30) (7 dwords)
 				{ DST_OFF = 13 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 1 }
 				{ STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 }
 109cf1ac:				0.000000 -28026765312.000000 -28026765312.000000 -28026765312.000000
 109cf1ac:				0000: 00000000 d0d0d0d0 d0d0d0d0 d0d0d0d0
 109cf1a0:			0000: c0053000 0060000d 00000001 00000000 d0d0d0d0 d0d0d0d0 d0d0d0d0
-t0			write VFD_FETCH[0].INSTR_0 (220a)
+			write VFD_FETCH[0].INSTR_0 (220a)
 				VFD_FETCH[0].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 24 | SWITCHNEXT }
 				VFD_FETCH[0].INSTR_1: 0x107cb000
 				VFD_FETCH[0].INSTR_2: { SIZE = 0x100000 }
 				VFD_FETCH[0].INSTR_3: { STEPRATE = 1 }
 109cf1bc:			0000: 0003220a 00080c0b 107cb000 00100000 00000001
-t0			write VFD_DECODE[0].INSTR (228a)
+			write VFD_DECODE[0].INSTR (228a)
 				VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_FLOAT | REGID = r0.z | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID | SWITCHNEXT }
 109cf1d0:			0000: 0000228a 6c0020df
-t0			write VFD_FETCH[0x1].INSTR_0 (220e)
+			write VFD_FETCH[0x1].INSTR_0 (220e)
 				VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 24 }
 				VFD_FETCH[0x1].INSTR_1: 0x107cb00c
 				VFD_FETCH[0x1].INSTR_2: { SIZE = 0xffff4 }
 				VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 }
 109cf1d8:			0000: 0003220e 00000c0b 107cb00c 000ffff4 00000001
-t0			write VFD_DECODE[0x1].INSTR (228b)
+			write VFD_DECODE[0x1].INSTR (228b)
 				VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_FLOAT | REGID = r1.z | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID }
 109cf1ec:			0000: 0000228b 2c0060df
-t0			write VFD_CONTROL_0 (2200)
+			write VFD_CONTROL_0 (2200)
 				VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 }
 				VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x }
 				VFD_CONTROL_2: 0
 				VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x }
 				VFD_CONTROL_4: 0
 109cf1f4:			0000: 00042200 082a0008 fcfc0081 00000000 0000fc00 00000000
-t0			write UCHE_INVALIDATE0 (0e8a)
+			write UCHE_INVALIDATE0 (0e8a)
 				UCHE_INVALIDATE0: 0
 				UCHE_INVALIDATE1: 0x12
 109cf20c:			0000: 00010e8a 00000000 00000012
-t0			write VFD_INDEX_OFFSET (2208)
+			write VFD_INDEX_OFFSET (2208)
 				VFD_INDEX_OFFSET: 0
 				UNKNOWN_2209: 0
 109cf218:			0000: 00012208 00000000 00000000
-t0			write PC_RESTART_INDEX (21c6)
+			write PC_RESTART_INDEX (21c6)
 				PC_RESTART_INDEX: 0xffffffff
 109cf224:			0000: 000021c6 ffffffff
-t0			write CP_SCRATCH[0x7].REG (057f)
+			write CP_SCRATCH[0x7].REG (057f)
 				CP_SCRATCH[0x7].REG: 0x20
 				:0,31,115,32
 109cf22c:			0000: 0000057f 00000020
-t3			opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords)
+			opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords)
 				{ PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_16_BIT | PATCH_TYPE = TESS_QUADS }
 				{ NUM_INSTANCES = 1 }
 				{ NUM_INDICES = 480 }
@@ -1850,121 +1850,121 @@ t3			opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords)
  +	007e4200			HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
  +	00000003			HLSQ_UPDATE_CONTROL: 0x3
 109cf234:			0000: c0053800 00000404 00000001 000001e0 00000000 10bd05a0 000003c0
-t0			write CP_SCRATCH[0x7].REG (057f)
+			write CP_SCRATCH[0x7].REG (057f)
 				CP_SCRATCH[0x7].REG: 0x21
 				:0,31,115,33
 109cf250:			0000: 0000057f 00000021
-t0			write CP_SCRATCH[0x5].REG (057d)
+			write CP_SCRATCH[0x5].REG (057d)
 				CP_SCRATCH[0x5].REG: 0x25
 				:0,37,115,33
 109cf258:			0000: 0000057d 00000025
-t0			write RB_DEPTH_CONTROL (2101)
+			write RB_DEPTH_CONTROL (2101)
 				RB_DEPTH_CONTROL: { Z_TEST_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_READ_ENABLE }
 109cf260:			0000: 00002101 80000016
-t0			write GRAS_ALPHA_CONTROL (2073)
+			write GRAS_ALPHA_CONTROL (2073)
 				GRAS_ALPHA_CONTROL: { 0 }
 109cf268:			0000: 00002073 00000000
-t0			write GRAS_SU_MODE_CONTROL (2078)
+			write GRAS_SU_MODE_CONTROL (2078)
 				GRAS_SU_MODE_CONTROL: { CULL_BACK | LINEHALFWIDTH = 0.500000 | RENDERING_PASS }
 109cf270:			0000: 00002078 00100012
-t0			write GRAS_SU_POINT_MINMAX (2070)
+			write GRAS_SU_POINT_MINMAX (2070)
 				GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 1.000000 }
 				GRAS_SU_POINT_SIZE: 1.000000
 109cf278:			0000: 00012070 00100010 00000010
-t0			write GRAS_SU_POLY_OFFSET_SCALE (2074)
+			write GRAS_SU_POLY_OFFSET_SCALE (2074)
 				GRAS_SU_POLY_OFFSET_SCALE: 0.000000
 				GRAS_SU_POLY_OFFSET_OFFSET: 0.000000
 				GRAS_SU_POLY_OFFSET_CLAMP: 0.000000
 109cf284:			0000: 00022074 00000000 00000000 00000000
-t0			write GRAS_CL_CLIP_CNTL (2000)
+			write GRAS_CL_CLIP_CNTL (2000)
 				GRAS_CL_CLIP_CNTL: { 0x80000 }
 109cf294:			0000: 00002000 00080000
-t0			write PC_PRIM_VTX_CNTL (21c4)
+			write PC_PRIM_VTX_CNTL (21c4)
 				PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST }
 				PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES }
 109cf29c:			0000: 000121c4 02000001 00000012
-t0			write GRAS_SC_WINDOW_SCISSOR_BR (209c)
+			write GRAS_SC_WINDOW_SCISSOR_BR (209c)
 				GRAS_SC_WINDOW_SCISSOR_BR: { X = 299 | Y = 299 }
 				GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
 109cf2a8:			0000: 0001209c 012b012b 00000000
-t0			write RB_VPORT_Z_CLAMP[0].MIN (2120)
+			write RB_VPORT_Z_CLAMP[0].MIN (2120)
 				RB_VPORT_Z_CLAMP[0].MIN: 0
 				RB_VPORT_Z_CLAMP[0].MAX: 0xffffff
 109cf2b4:			0000: 00012120 00000000 00ffffff
-t0			write HLSQ_UPDATE_CONTROL (23db)
+			write HLSQ_UPDATE_CONTROL (23db)
 				HLSQ_UPDATE_CONTROL: 0x3
 109cf2c0:			0000: 000023db 00000003
-t0			write HLSQ_CONTROL_0_REG (23c0)
+			write HLSQ_CONTROL_0_REG (23c0)
 				HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | SPSHADERRESTART | CONSTMODE = 1 | SPCONSTFULLUPDATE }
 				HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x }
 				HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x }
 				HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x }
 				HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 }
 109cf2c8:			0000: 000423c0 28000250 fcfc0100 fff3f3f0 fcfcfc00 00fcfcfc
-t0			write HLSQ_VS_CONTROL_REG (23c5)
+			write HLSQ_VS_CONTROL_REG (23c5)
 				HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 4 }
 				HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 }
 				HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
 				HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
 				HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
 109cf2e0:			0000: 000423c5 04000042 017e423e 007e4200 007e4200 007e4200
-t0			write SP_SP_CTRL_REG (22c0)
+			write SP_SP_CTRL_REG (22c0)
 				SP_SP_CTRL_REG: { 0x140010 }
 109cf2f8:			0000: 000022c0 00140010
-t0			write SP_INSTR_CACHE_CTRL (22c1)
+			write SP_INSTR_CACHE_CTRL (22c1)
 				SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x7f }
 109cf300:			0000: 000022c1 000005ff
-t0			write SP_VS_LENGTH_REG (22e5)
+			write SP_VS_LENGTH_REG (22e5)
 				SP_VS_LENGTH_REG: 4
 109cf308:			0000: 000022e5 00000004
-t0			write SP_VS_CTRL_REG0 (22c4)
+			write SP_VS_CTRL_REG0 (22c4)
 				SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 5 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE }
 				SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 8 }
 				SP_VS_PARAM_REG: { POSREGID = r2.z | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 }
 109cf310:			0000: 000222c4 00201400 08000042 0010fc0a
-t0			write SP_VS_OUT[0].REG (22c7)
+			write SP_VS_OUT[0].REG (22c7)
 				SP_VS_OUT[0].REG: { A_REGID = r3.z | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 }
 109cf320:			0000: 000022c7 00001e0e
-t0			write SP_VS_VPC_DST[0].REG (22d8)
+			write SP_VS_VPC_DST[0].REG (22d8)
 				SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 8 | OUTLOC2 = 8 | OUTLOC3 = 8 }
 109cf328:			0000: 000022d8 08080808
-t0			write SP_VS_OBJ_OFFSET_REG (22e0)
+			write SP_VS_OBJ_OFFSET_REG (22e0)
 				SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 }
 				SP_VS_OBJ_START: 0x10cd5000
 109cf330:			0000: 000122e0 00000000 10cd5000
-t0			write SP_FS_LENGTH_REG (22ef)
+			write SP_FS_LENGTH_REG (22ef)
 				SP_FS_LENGTH_REG: 1
 109cf33c:			0000: 000022ef 00000001
-t0			write SP_FS_CTRL_REG0 (22e8)
+			write SP_FS_CTRL_REG0 (22e8)
 				SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 2 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE }
 				SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 }
 109cf344:			0000: 000122e8 00340802 8010003e
-t0			write SP_FS_OBJ_OFFSET_REG (22ea)
+			write SP_FS_OBJ_OFFSET_REG (22ea)
 				SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
 				SP_FS_OBJ_START: 0x108cb000
 109cf350:			0000: 000122ea 7e420000 108cb000
-t0			write SP_HS_OBJ_OFFSET_REG (230d)
+			write SP_HS_OBJ_OFFSET_REG (230d)
 				SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
 109cf35c:			0000: 0000230d 7e420000
-t0			write SP_DS_OBJ_OFFSET_REG (2334)
+			write SP_DS_OBJ_OFFSET_REG (2334)
 				SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
 109cf364:			0000: 00002334 7e420000
-t0			write SP_GS_OBJ_OFFSET_REG (235b)
+			write SP_GS_OBJ_OFFSET_REG (235b)
 				SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
 109cf36c:			0000: 0000235b 7e420000
-t0			write GRAS_CNTL (2003)
+			write GRAS_CNTL (2003)
 				GRAS_CNTL: { IJ_PERSP }
 109cf374:			0000: 00002003 00000001
-t0			write RB_RENDER_CONTROL2 (20a3)
+			write RB_RENDER_CONTROL2 (20a3)
 				RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 | IJ_PERSP_PIXEL }
 109cf37c:			0000: 000020a3 00001000
-t0			write RB_FS_OUTPUT_REG (2100)
+			write RB_FS_OUTPUT_REG (2100)
 				RB_FS_OUTPUT_REG: { MRT = 1 }
 109cf384:			0000: 00002100 00000001
-t0			write SP_FS_OUTPUT_REG (22f0)
+			write SP_FS_OUTPUT_REG (22f0)
 				SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r0.x }
 109cf38c:			0000: 000022f0 0000fc01
-t0			write SP_FS_MRT[0].REG (22f1)
+			write SP_FS_MRT[0].REG (22f1)
 				SP_FS_MRT[0].REG: { REGID = r0.z | MRTFORMAT = RB4_R8G8B8A8_UNORM }
 				SP_FS_MRT[0x1].REG: { REGID = r0.z | MRTFORMAT = 0 }
 				SP_FS_MRT[0x2].REG: { REGID = r0.z | MRTFORMAT = 0 }
@@ -1975,11 +1975,11 @@ t0			write SP_FS_MRT[0].REG (22f1)
 				SP_FS_MRT[0x7].REG: { REGID = r0.z | MRTFORMAT = 0 }
 109cf394:			0000: 000722f1 0001a002 00000002 00000002 00000002 00000002 00000002 00000002
 109cf3b4:			0020: 00000002
-t0			write VPC_ATTR (2140)
+			write VPC_ATTR (2140)
 				VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 }
 				VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 }
 109cf3b8:			0000: 00012140 42001004 00040400
-t0			write VPC_VARYING_INTERP[0].MODE (2142)
+			write VPC_VARYING_INTERP[0].MODE (2142)
 				VPC_VARYING_INTERP[0].MODE: 0
 				VPC_VARYING_INTERP[0x1].MODE: 0
 				VPC_VARYING_INTERP[0x2].MODE: 0
@@ -1990,7 +1990,7 @@ t0			write VPC_VARYING_INTERP[0].MODE (2142)
 				VPC_VARYING_INTERP[0x7].MODE: 0
 109cf3c4:			0000: 00072142 00000000 00000000 00000000 00000000 00000000 00000000 00000000
 *
-t0			write VPC_VARYING_PS_REPL[0].MODE (214a)
+			write VPC_VARYING_PS_REPL[0].MODE (214a)
 				VPC_VARYING_PS_REPL[0].MODE: 0
 				VPC_VARYING_PS_REPL[0x1].MODE: 0
 				VPC_VARYING_PS_REPL[0x2].MODE: 0
@@ -2001,7 +2001,7 @@ t0			write VPC_VARYING_PS_REPL[0].MODE (214a)
 				VPC_VARYING_PS_REPL[0x7].MODE: 0
 109cf3e8:			0000: 0007214a 00000000 00000000 00000000 00000000 00000000 00000000 00000000
 *
-t3			opcode: CP_LOAD_STATE4 (30) (131 dwords)
+			opcode: CP_LOAD_STATE4 (30) (131 dwords)
 				{ DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 4 }
 				{ STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 }
 				:2:0000:0000[40700000x_10000002x] mul.f r0.x, r0.z, c0.x
@@ -2080,7 +2080,7 @@ t3			opcode: CP_LOAD_STATE4 (30) (131 dwords)
 109cf58c:			0180: 63800002 00031022 63800000 00011024 6382040e 00021025 6382040f 00001026
 109cf5ac:			01a0: 63820410 00000000 03000000 00000000 00000000 00000000 00000000 00000000
 *
-t3			opcode: CP_LOAD_STATE4 (30) (35 dwords)
+			opcode: CP_LOAD_STATE4 (30) (35 dwords)
 				{ DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_SHADER | NUM_UNIT = 1 }
 				{ STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 }
 				:2:0000:0000[47300002x_00002000x] bary.f r0.z, 0, r0.x
@@ -2100,9 +2100,9 @@ t3			opcode: CP_LOAD_STATE4 (30) (35 dwords)
 109cf618:			0000: c0213000 00700000 00000000 00002000 47300002 00002001 47300003 00002002
 109cf638:			0020: 47300004 00002003 47308005 00000000 03000000 00000000 00000000 00000000
 *
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 109cf6a4:			0000: c0002600 00000000
-t3			opcode: CP_LOAD_STATE4 (30) (51 dwords)
+			opcode: CP_LOAD_STATE4 (30) (51 dwords)
 				{ DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 12 }
 				{ STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 }
 109cf6b8:				4.330127 0.855050 0.555273 0.469846 0.000000 4.698463 -0.404206 -0.342020
@@ -2124,18 +2124,18 @@ t3			opcode: CP_LOAD_STATE4 (30) (51 dwords)
 109cf72c:			0080: 00000000 00000000 3f800000 3f4ccccd 3dcccccd 00000000 3f800000 00000000
 109cf74c:			00a0: 00000000 00000000 3f800000 00000000 00000000 00000000 3f800000 02020000
 109cf76c:			00c0: 02020202 02020202 00000202
-t0			write VFD_INDEX_OFFSET (2208)
+			write VFD_INDEX_OFFSET (2208)
 				VFD_INDEX_OFFSET: 0
 				UNKNOWN_2209: 0
 109cf778:			0000: 00012208 00000000 00000000
-t0			write PC_RESTART_INDEX (21c6)
+			write PC_RESTART_INDEX (21c6)
 				PC_RESTART_INDEX: 0xffffffff
 109cf784:			0000: 000021c6 ffffffff
-t0			write CP_SCRATCH[0x7].REG (057f)
+			write CP_SCRATCH[0x7].REG (057f)
 				CP_SCRATCH[0x7].REG: 0x26
 				:0,37,115,38
 109cf78c:			0000: 0000057f 00000026
-t3			opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords)
+			opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords)
 				{ PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_16_BIT | PATCH_TYPE = TESS_QUADS }
 				{ NUM_INSTANCES = 1 }
 				{ NUM_INDICES = 120 }
@@ -2225,121 +2225,121 @@ t3			opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords)
  +	007e4200			HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
  +	00000003			HLSQ_UPDATE_CONTROL: 0x3
 109cf794:			0000: c0053800 00000404 00000001 00000078 00000000 10bd0960 000000f0
-t0			write CP_SCRATCH[0x7].REG (057f)
+			write CP_SCRATCH[0x7].REG (057f)
 				CP_SCRATCH[0x7].REG: 0x27
 				:0,37,115,39
 109cf7b0:			0000: 0000057f 00000027
-t0			write CP_SCRATCH[0x5].REG (057d)
+			write CP_SCRATCH[0x5].REG (057d)
 				CP_SCRATCH[0x5].REG: 0x2b
 				:0,43,115,39
 109cf7b8:			0000: 0000057d 0000002b
-t0			write RB_DEPTH_CONTROL (2101)
+			write RB_DEPTH_CONTROL (2101)
 				RB_DEPTH_CONTROL: { Z_TEST_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_READ_ENABLE }
 109cf7c0:			0000: 00002101 80000016
-t0			write GRAS_ALPHA_CONTROL (2073)
+			write GRAS_ALPHA_CONTROL (2073)
 				GRAS_ALPHA_CONTROL: { 0 }
 109cf7c8:			0000: 00002073 00000000
-t0			write GRAS_SU_MODE_CONTROL (2078)
+			write GRAS_SU_MODE_CONTROL (2078)
 				GRAS_SU_MODE_CONTROL: { CULL_BACK | LINEHALFWIDTH = 0.500000 | RENDERING_PASS }
 109cf7d0:			0000: 00002078 00100012
-t0			write GRAS_SU_POINT_MINMAX (2070)
+			write GRAS_SU_POINT_MINMAX (2070)
 				GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 1.000000 }
 				GRAS_SU_POINT_SIZE: 1.000000
 109cf7d8:			0000: 00012070 00100010 00000010
-t0			write GRAS_SU_POLY_OFFSET_SCALE (2074)
+			write GRAS_SU_POLY_OFFSET_SCALE (2074)
 				GRAS_SU_POLY_OFFSET_SCALE: 0.000000
 				GRAS_SU_POLY_OFFSET_OFFSET: 0.000000
 				GRAS_SU_POLY_OFFSET_CLAMP: 0.000000
 109cf7e4:			0000: 00022074 00000000 00000000 00000000
-t0			write GRAS_CL_CLIP_CNTL (2000)
+			write GRAS_CL_CLIP_CNTL (2000)
 				GRAS_CL_CLIP_CNTL: { 0x80000 }
 109cf7f4:			0000: 00002000 00080000
-t0			write PC_PRIM_VTX_CNTL (21c4)
+			write PC_PRIM_VTX_CNTL (21c4)
 				PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST }
 				PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES }
 109cf7fc:			0000: 000121c4 02000001 00000012
-t0			write GRAS_SC_WINDOW_SCISSOR_BR (209c)
+			write GRAS_SC_WINDOW_SCISSOR_BR (209c)
 				GRAS_SC_WINDOW_SCISSOR_BR: { X = 299 | Y = 299 }
 				GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
 109cf808:			0000: 0001209c 012b012b 00000000
-t0			write RB_VPORT_Z_CLAMP[0].MIN (2120)
+			write RB_VPORT_Z_CLAMP[0].MIN (2120)
 				RB_VPORT_Z_CLAMP[0].MIN: 0
 				RB_VPORT_Z_CLAMP[0].MAX: 0xffffff
 109cf814:			0000: 00012120 00000000 00ffffff
-t0			write HLSQ_UPDATE_CONTROL (23db)
+			write HLSQ_UPDATE_CONTROL (23db)
 				HLSQ_UPDATE_CONTROL: 0x3
 109cf820:			0000: 000023db 00000003
-t0			write HLSQ_CONTROL_0_REG (23c0)
+			write HLSQ_CONTROL_0_REG (23c0)
 				HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | SPSHADERRESTART | CONSTMODE = 1 | SPCONSTFULLUPDATE }
 				HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x }
 				HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x }
 				HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r63.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x }
 				HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 }
 109cf828:			0000: 000423c0 28000250 fcfc0100 fff3f3f0 fcfcfcfc 00fcfcfc
-t0			write HLSQ_VS_CONTROL_REG (23c5)
+			write HLSQ_VS_CONTROL_REG (23c5)
 				HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 4 }
 				HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 }
 				HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
 				HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
 				HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
 109cf840:			0000: 000423c5 04000042 017e423e 007e4200 007e4200 007e4200
-t0			write SP_SP_CTRL_REG (22c0)
+			write SP_SP_CTRL_REG (22c0)
 				SP_SP_CTRL_REG: { 0x140010 }
 109cf858:			0000: 000022c0 00140010
-t0			write SP_INSTR_CACHE_CTRL (22c1)
+			write SP_INSTR_CACHE_CTRL (22c1)
 				SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x7f }
 109cf860:			0000: 000022c1 000005ff
-t0			write SP_VS_LENGTH_REG (22e5)
+			write SP_VS_LENGTH_REG (22e5)
 				SP_VS_LENGTH_REG: 4
 109cf868:			0000: 000022e5 00000004
-t0			write SP_VS_CTRL_REG0 (22c4)
+			write SP_VS_CTRL_REG0 (22c4)
 				SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 4 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE }
 				SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 4 }
 				SP_VS_PARAM_REG: { POSREGID = r1.z | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 }
 109cf870:			0000: 000222c4 00201000 04000042 0010fc06
-t0			write SP_VS_OUT[0].REG (22c7)
+			write SP_VS_OUT[0].REG (22c7)
 				SP_VS_OUT[0].REG: { A_REGID = r2.z | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 }
 109cf880:			0000: 000022c7 00001e0a
-t0			write SP_VS_VPC_DST[0].REG (22d8)
+			write SP_VS_VPC_DST[0].REG (22d8)
 				SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 8 | OUTLOC2 = 8 | OUTLOC3 = 8 }
 109cf888:			0000: 000022d8 08080808
-t0			write SP_VS_OBJ_OFFSET_REG (22e0)
+			write SP_VS_OBJ_OFFSET_REG (22e0)
 				SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 }
 				SP_VS_OBJ_START: 0x10cd0000
 109cf890:			0000: 000122e0 00000000 10cd0000
-t0			write SP_FS_LENGTH_REG (22ef)
+			write SP_FS_LENGTH_REG (22ef)
 				SP_FS_LENGTH_REG: 1
 109cf89c:			0000: 000022ef 00000001
-t0			write SP_FS_CTRL_REG0 (22e8)
+			write SP_FS_CTRL_REG0 (22e8)
 				SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE }
 				SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 }
 109cf8a4:			0000: 000122e8 00340402 8010003e
-t0			write SP_FS_OBJ_OFFSET_REG (22ea)
+			write SP_FS_OBJ_OFFSET_REG (22ea)
 				SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
 				SP_FS_OBJ_START: 0x10cd2000
 109cf8b0:			0000: 000122ea 7e420000 10cd2000
-t0			write SP_HS_OBJ_OFFSET_REG (230d)
+			write SP_HS_OBJ_OFFSET_REG (230d)
 				SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
 109cf8bc:			0000: 0000230d 7e420000
-t0			write SP_DS_OBJ_OFFSET_REG (2334)
+			write SP_DS_OBJ_OFFSET_REG (2334)
 				SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
 109cf8c4:			0000: 00002334 7e420000
-t0			write SP_GS_OBJ_OFFSET_REG (235b)
+			write SP_GS_OBJ_OFFSET_REG (235b)
 				SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
 109cf8cc:			0000: 0000235b 7e420000
-t0			write GRAS_CNTL (2003)
+			write GRAS_CNTL (2003)
 				GRAS_CNTL: { 0 }
 109cf8d4:			0000: 00002003 00000000
-t0			write RB_RENDER_CONTROL2 (20a3)
+			write RB_RENDER_CONTROL2 (20a3)
 				RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 }
 109cf8dc:			0000: 000020a3 00000000
-t0			write RB_FS_OUTPUT_REG (2100)
+			write RB_FS_OUTPUT_REG (2100)
 				RB_FS_OUTPUT_REG: { MRT = 1 }
 109cf8e4:			0000: 00002100 00000001
-t0			write SP_FS_OUTPUT_REG (22f0)
+			write SP_FS_OUTPUT_REG (22f0)
 				SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r0.x }
 109cf8ec:			0000: 000022f0 0000fc01
-t0			write SP_FS_MRT[0].REG (22f1)
+			write SP_FS_MRT[0].REG (22f1)
 				SP_FS_MRT[0].REG: { REGID = r0.x | MRTFORMAT = RB4_R8G8B8A8_UNORM }
 				SP_FS_MRT[0x1].REG: { REGID = r0.x | MRTFORMAT = 0 }
 				SP_FS_MRT[0x2].REG: { REGID = r0.x | MRTFORMAT = 0 }
@@ -2350,11 +2350,11 @@ t0			write SP_FS_MRT[0].REG (22f1)
 				SP_FS_MRT[0x7].REG: { REGID = r0.x | MRTFORMAT = 0 }
 109cf8f4:			0000: 000722f1 0001a000 00000000 00000000 00000000 00000000 00000000 00000000
 *
-t0			write VPC_ATTR (2140)
+			write VPC_ATTR (2140)
 				VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 }
 				VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 }
 109cf918:			0000: 00012140 42001004 00040400
-t0			write VPC_VARYING_INTERP[0].MODE (2142)
+			write VPC_VARYING_INTERP[0].MODE (2142)
 				VPC_VARYING_INTERP[0].MODE: 0x55
 				VPC_VARYING_INTERP[0x1].MODE: 0
 				VPC_VARYING_INTERP[0x2].MODE: 0
@@ -2365,7 +2365,7 @@ t0			write VPC_VARYING_INTERP[0].MODE (2142)
 				VPC_VARYING_INTERP[0x7].MODE: 0
 109cf924:			0000: 00072142 00000055 00000000 00000000 00000000 00000000 00000000 00000000
 *
-t0			write VPC_VARYING_PS_REPL[0].MODE (214a)
+			write VPC_VARYING_PS_REPL[0].MODE (214a)
 				VPC_VARYING_PS_REPL[0].MODE: 0
 				VPC_VARYING_PS_REPL[0x1].MODE: 0
 				VPC_VARYING_PS_REPL[0x2].MODE: 0
@@ -2376,7 +2376,7 @@ t0			write VPC_VARYING_PS_REPL[0].MODE (214a)
 				VPC_VARYING_PS_REPL[0x7].MODE: 0
 109cf948:			0000: 0007214a 00000000 00000000 00000000 00000000 00000000 00000000 00000000
 *
-t3			opcode: CP_LOAD_STATE4 (30) (131 dwords)
+			opcode: CP_LOAD_STATE4 (30) (131 dwords)
 				{ DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 4 }
 				{ STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 }
 				:2:0000:0000[40700000x_10000002x] mul.f r0.x, r0.z, c0.x
@@ -2461,7 +2461,7 @@ t3			opcode: CP_LOAD_STATE4 (30) (131 dwords)
 109cfb0c:			01a0: 63800001 00021025 63800002 00031026 63800000 00011028 6382040a 00021029
 109cfb2c:			01c0: 6382040b 0000102a 6382040c 00000000 03000000 00000000 00000000 00000000
 *
-t3			opcode: CP_LOAD_STATE4 (30) (35 dwords)
+			opcode: CP_LOAD_STATE4 (30) (35 dwords)
 				{ DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_SHADER | NUM_UNIT = 1 }
 				{ STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 }
 				:0:0000:0000[00000000x_00000000x] nop
@@ -2484,9 +2484,9 @@ t3			opcode: CP_LOAD_STATE4 (30) (35 dwords)
 109cfb98:			0020: c7c60001 01c00004 c7c60002 01c00006 c7c60003 00002000 473090fc 00000000
 109cfbb8:			0040: 03000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
 *
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 109cfc04:			0000: c0002600 00000000
-t3			opcode: CP_LOAD_STATE4 (30) (51 dwords)
+			opcode: CP_LOAD_STATE4 (30) (51 dwords)
 				{ DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 12 }
 				{ STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 }
 109cfc18:				4.276816 0.109522 0.611668 0.517565 0.677381 4.774377 -0.312365 -0.264309
@@ -2508,44 +2508,44 @@ t3			opcode: CP_LOAD_STATE4 (30) (51 dwords)
 109cfc8c:			0080: 00000000 00000000 00000000 00000000 00000000 00000000 3f800000 00000000
 109cfcac:			00a0: 3f4ccccd 3e4ccccd 3f800000 00000000 00000000 00000000 3f800000 00000000
 109cfccc:			00c0: 00000000 00000000 3f800000
-t3			opcode: CP_LOAD_STATE4 (30) (7 dwords)
+			opcode: CP_LOAD_STATE4 (30) (7 dwords)
 				{ DST_OFF = 13 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 1 }
 				{ STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 }
 109cfce4:				0.000000 -28026765312.000000 -28026765312.000000 -28026765312.000000
 109cfce4:				0000: 00000000 d0d0d0d0 d0d0d0d0 d0d0d0d0
 109cfcd8:			0000: c0053000 0060000d 00000001 00000000 d0d0d0d0 d0d0d0d0 d0d0d0d0
-t0			write VFD_FETCH[0].INSTR_0 (220a)
+			write VFD_FETCH[0].INSTR_0 (220a)
 				VFD_FETCH[0].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 12 }
 				VFD_FETCH[0].INSTR_1: 0x107cb000
 				VFD_FETCH[0].INSTR_2: { SIZE = 0x100000 }
 				VFD_FETCH[0].INSTR_3: { STEPRATE = 1 }
 109cfcf4:			0000: 0003220a 0000060b 107cb000 00100000 00000001
-t0			write VFD_DECODE[0].INSTR (228a)
+			write VFD_DECODE[0].INSTR (228a)
 				VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_FLOAT | REGID = r0.z | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID }
 109cfd08:			0000: 0000228a 2c0020df
-t0			write VFD_CONTROL_0 (2200)
+			write VFD_CONTROL_0 (2200)
 				VFD_CONTROL_0: { TOTALATTRTOVS = 4 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 1 | STRMFETCHINSTRCNT = 1 | 0xa0000 }
 				VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x }
 				VFD_CONTROL_2: 0
 				VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x }
 				VFD_CONTROL_4: 0
 109cfd10:			0000: 00042200 041a0004 fcfc0081 00000000 0000fc00 00000000
-t0			write UCHE_INVALIDATE0 (0e8a)
+			write UCHE_INVALIDATE0 (0e8a)
 				UCHE_INVALIDATE0: 0
 				UCHE_INVALIDATE1: 0x12
 109cfd28:			0000: 00010e8a 00000000 00000012
-t0			write VFD_INDEX_OFFSET (2208)
+			write VFD_INDEX_OFFSET (2208)
 				VFD_INDEX_OFFSET: 0
 				UNKNOWN_2209: 0
 109cfd34:			0000: 00012208 00000000 00000000
-t0			write PC_RESTART_INDEX (21c6)
+			write PC_RESTART_INDEX (21c6)
 				PC_RESTART_INDEX: 0xffffffff
 109cfd40:			0000: 000021c6 ffffffff
-t0			write CP_SCRATCH[0x7].REG (057f)
+			write CP_SCRATCH[0x7].REG (057f)
 				CP_SCRATCH[0x7].REG: 0x2c
 				:0,43,115,44
 109cfd48:			0000: 0000057f 0000002c
-t3			opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords)
+			opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords)
 				{ PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_16_BIT | PATCH_TYPE = TESS_QUADS }
 				{ NUM_INSTANCES = 1 }
 				{ NUM_INDICES = 120 }
@@ -2647,30 +2647,30 @@ t3			opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords)
  +	007e4200			HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
  +	00000003			HLSQ_UPDATE_CONTROL: 0x3
 109cfd50:			0000: c0053800 00000404 00000001 00000078 00000000 10bd0a50 000000f0
-t0			write CP_SCRATCH[0x7].REG (057f)
+			write CP_SCRATCH[0x7].REG (057f)
 				CP_SCRATCH[0x7].REG: 0x2d
 				:0,43,115,45
 109cfd6c:			0000: 0000057f 0000002d
-t0			write CP_SCRATCH[0x5].REG (057d)
+			write CP_SCRATCH[0x5].REG (057d)
 				CP_SCRATCH[0x5].REG: 0x31
 				:0,49,115,45
 109cfd74:			0000: 0000057d 00000031
-t0			write PC_PRIM_VTX_CNTL (21c4)
+			write PC_PRIM_VTX_CNTL (21c4)
 				PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST }
 				PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES }
 109cfd7c:			0000: 000121c4 02000001 00000012
-t0			write VFD_INDEX_OFFSET (2208)
+			write VFD_INDEX_OFFSET (2208)
 				VFD_INDEX_OFFSET: 0
 				UNKNOWN_2209: 0
 109cfd88:			0000: 00012208 00000000 00000000
-t0			write PC_RESTART_INDEX (21c6)
+			write PC_RESTART_INDEX (21c6)
 				PC_RESTART_INDEX: 0xffffffff
 109cfd94:			0000: 000021c6 ffffffff
-t0			write CP_SCRATCH[0x7].REG (057f)
+			write CP_SCRATCH[0x7].REG (057f)
 				CP_SCRATCH[0x7].REG: 0x32
 				:0,49,115,50
 109cfd9c:			0000: 0000057f 00000032
-t3			opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords)
+			opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords)
 				{ PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_16_BIT | PATCH_TYPE = TESS_QUADS }
 				{ NUM_INSTANCES = 1 }
 				{ NUM_INDICES = 60 }
@@ -2688,21 +2688,21 @@ t3			opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords)
  +	00000000			VFD_INDEX_OFFSET: 0
  +	00000000			UNKNOWN_2209: 0
 109cfda4:			0000: c0053800 00000404 00000001 0000003c 00000000 10bd0b40 00000078
-t0			write CP_SCRATCH[0x7].REG (057f)
+			write CP_SCRATCH[0x7].REG (057f)
 				CP_SCRATCH[0x7].REG: 0x33
 				:0,49,115,51
 109cfdc0:			0000: 0000057f 00000033
-t0			write CP_SCRATCH[0x5].REG (057d)
+			write CP_SCRATCH[0x5].REG (057d)
 				CP_SCRATCH[0x5].REG: 0x37
 				:0,55,115,51
 109cfdc8:			0000: 0000057d 00000037
-t0			write PC_PRIM_VTX_CNTL (21c4)
+			write PC_PRIM_VTX_CNTL (21c4)
 				PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST }
 				PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES }
 109cfdd0:			0000: 000121c4 02000001 00000012
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 109cfddc:			0000: c0002600 00000000
-t3			opcode: CP_LOAD_STATE4 (30) (51 dwords)
+			opcode: CP_LOAD_STATE4 (30) (51 dwords)
 				{ DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 12 }
 				{ STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 }
 109cfdf0:				4.276816 0.109522 0.611668 0.517565 0.677381 4.774377 -0.312365 -0.264309
@@ -2724,18 +2724,18 @@ t3			opcode: CP_LOAD_STATE4 (30) (51 dwords)
 109cfe64:			0080: 00000000 00000000 00000000 00000000 00000000 00000000 3f800000 00000000
 109cfe84:			00a0: 3f4ccccd 3e4ccccd 3f800000 00000000 00000000 00000000 3f800000 00000000
 109cfea4:			00c0: 00000000 00000000 3f800000
-t0			write VFD_INDEX_OFFSET (2208)
+			write VFD_INDEX_OFFSET (2208)
 				VFD_INDEX_OFFSET: 0
 				UNKNOWN_2209: 0
 109cfeb0:			0000: 00012208 00000000 00000000
-t0			write PC_RESTART_INDEX (21c6)
+			write PC_RESTART_INDEX (21c6)
 				PC_RESTART_INDEX: 0xffffffff
 109cfebc:			0000: 000021c6 ffffffff
-t0			write CP_SCRATCH[0x7].REG (057f)
+			write CP_SCRATCH[0x7].REG (057f)
 				CP_SCRATCH[0x7].REG: 0x38
 				:0,55,115,56
 109cfec4:			0000: 0000057f 00000038
-t3			opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords)
+			opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords)
 				{ PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_16_BIT | PATCH_TYPE = TESS_QUADS }
 				{ NUM_INSTANCES = 1 }
 				{ NUM_INDICES = 120 }
@@ -2753,30 +2753,30 @@ t3			opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords)
  +	00000000			VFD_INDEX_OFFSET: 0
  +	00000000			UNKNOWN_2209: 0
 109cfecc:			0000: c0053800 00000404 00000001 00000078 00000000 10bd0bb8 000000f0
-t0			write CP_SCRATCH[0x7].REG (057f)
+			write CP_SCRATCH[0x7].REG (057f)
 				CP_SCRATCH[0x7].REG: 0x39
 				:0,55,115,57
 109cfee8:			0000: 0000057f 00000039
-t0			write CP_SCRATCH[0x5].REG (057d)
+			write CP_SCRATCH[0x5].REG (057d)
 				CP_SCRATCH[0x5].REG: 0x3d
 				:0,61,115,57
 109cfef0:			0000: 0000057d 0000003d
-t0			write PC_PRIM_VTX_CNTL (21c4)
+			write PC_PRIM_VTX_CNTL (21c4)
 				PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST }
 				PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES }
 109cfef8:			0000: 000121c4 02000001 00000012
-t0			write VFD_INDEX_OFFSET (2208)
+			write VFD_INDEX_OFFSET (2208)
 				VFD_INDEX_OFFSET: 0
 				UNKNOWN_2209: 0
 109cff04:			0000: 00012208 00000000 00000000
-t0			write PC_RESTART_INDEX (21c6)
+			write PC_RESTART_INDEX (21c6)
 				PC_RESTART_INDEX: 0xffffffff
 109cff10:			0000: 000021c6 ffffffff
-t0			write CP_SCRATCH[0x7].REG (057f)
+			write CP_SCRATCH[0x7].REG (057f)
 				CP_SCRATCH[0x7].REG: 0x3e
 				:0,61,115,62
 109cff18:			0000: 0000057f 0000003e
-t3			opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords)
+			opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords)
 				{ PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_16_BIT | PATCH_TYPE = TESS_QUADS }
 				{ NUM_INSTANCES = 1 }
 				{ NUM_INDICES = 60 }
@@ -2794,98 +2794,98 @@ t3			opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords)
  +	00000000			VFD_INDEX_OFFSET: 0
  +	00000000			UNKNOWN_2209: 0
 109cff20:			0000: c0053800 00000404 00000001 0000003c 00000000 10bd0ca8 00000078
-t0			write CP_SCRATCH[0x7].REG (057f)
+			write CP_SCRATCH[0x7].REG (057f)
 				CP_SCRATCH[0x7].REG: 0x3f
 				:0,61,115,63
 109cff3c:			0000: 0000057f 0000003f
-t0			write CP_SCRATCH[0x5].REG (057d)
+			write CP_SCRATCH[0x5].REG (057d)
 				CP_SCRATCH[0x5].REG: 0x43
 				:0,67,115,63
 109cff44:			0000: 0000057d 00000043
-t0			write RB_DEPTH_CONTROL (2101)
+			write RB_DEPTH_CONTROL (2101)
 				RB_DEPTH_CONTROL: { Z_TEST_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_READ_ENABLE }
 109cff4c:			0000: 00002101 80000016
-t0			write GRAS_ALPHA_CONTROL (2073)
+			write GRAS_ALPHA_CONTROL (2073)
 				GRAS_ALPHA_CONTROL: { 0 }
 109cff54:			0000: 00002073 00000000
-t0			write PC_PRIM_VTX_CNTL (21c4)
+			write PC_PRIM_VTX_CNTL (21c4)
 				PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST }
 				PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES }
 109cff5c:			0000: 000121c4 02000001 00000012
-t0			write HLSQ_UPDATE_CONTROL (23db)
+			write HLSQ_UPDATE_CONTROL (23db)
 				HLSQ_UPDATE_CONTROL: 0x3
 109cff68:			0000: 000023db 00000003
-t0			write HLSQ_CONTROL_0_REG (23c0)
+			write HLSQ_CONTROL_0_REG (23c0)
 				HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | SPSHADERRESTART | CONSTMODE = 1 | SPCONSTFULLUPDATE }
 				HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x }
 				HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x }
 				HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r63.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x }
 				HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 }
 109cff70:			0000: 000423c0 28000250 fcfc0100 fff3f3f0 fcfcfcfc 00fcfcfc
-t0			write HLSQ_VS_CONTROL_REG (23c5)
+			write HLSQ_VS_CONTROL_REG (23c5)
 				HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 4 }
 				HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 }
 				HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
 				HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
 				HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
 109cff88:			0000: 000423c5 04000042 017e423e 007e4200 007e4200 007e4200
-t0			write SP_SP_CTRL_REG (22c0)
+			write SP_SP_CTRL_REG (22c0)
 				SP_SP_CTRL_REG: { 0x140010 }
 109cffa0:			0000: 000022c0 00140010
-t0			write SP_INSTR_CACHE_CTRL (22c1)
+			write SP_INSTR_CACHE_CTRL (22c1)
 				SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x7f }
 109cffa8:			0000: 000022c1 000005ff
-t0			write SP_VS_LENGTH_REG (22e5)
+			write SP_VS_LENGTH_REG (22e5)
 				SP_VS_LENGTH_REG: 4
 109cffb0:			0000: 000022e5 00000004
-t0			write SP_VS_CTRL_REG0 (22c4)
+			write SP_VS_CTRL_REG0 (22c4)
 				SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 5 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE }
 				SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 8 }
 				SP_VS_PARAM_REG: { POSREGID = r2.z | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 }
 109cffb8:			0000: 000222c4 00201400 08000042 0010fc0a
-t0			write SP_VS_OUT[0].REG (22c7)
+			write SP_VS_OUT[0].REG (22c7)
 				SP_VS_OUT[0].REG: { A_REGID = r3.z | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 }
 109cffc8:			0000: 000022c7 00001e0e
-t0			write SP_VS_VPC_DST[0].REG (22d8)
+			write SP_VS_VPC_DST[0].REG (22d8)
 				SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 8 | OUTLOC2 = 8 | OUTLOC3 = 8 }
 109cffd0:			0000: 000022d8 08080808
-t0			write SP_VS_OBJ_OFFSET_REG (22e0)
+			write SP_VS_OBJ_OFFSET_REG (22e0)
 				SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 }
 				SP_VS_OBJ_START: 0x10cd5000
 109cffd8:			0000: 000122e0 00000000 10cd5000
-t0			write SP_FS_LENGTH_REG (22ef)
+			write SP_FS_LENGTH_REG (22ef)
 				SP_FS_LENGTH_REG: 1
 109cffe4:			0000: 000022ef 00000001
-t0			write SP_FS_CTRL_REG0 (22e8)
+			write SP_FS_CTRL_REG0 (22e8)
 				SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE }
 				SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 }
 109cffec:			0000: 000122e8 00340402 8010003e
-t0			write SP_FS_OBJ_OFFSET_REG (22ea)
+			write SP_FS_OBJ_OFFSET_REG (22ea)
 				SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
 				SP_FS_OBJ_START: 0x10cd2000
 109cfff8:			0000: 000122ea 7e420000 10cd2000
-t0			write SP_HS_OBJ_OFFSET_REG (230d)
+			write SP_HS_OBJ_OFFSET_REG (230d)
 				SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
 109d0004:			0000: 0000230d 7e420000
-t0			write SP_DS_OBJ_OFFSET_REG (2334)
+			write SP_DS_OBJ_OFFSET_REG (2334)
 				SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
 109d000c:			0000: 00002334 7e420000
-t0			write SP_GS_OBJ_OFFSET_REG (235b)
+			write SP_GS_OBJ_OFFSET_REG (235b)
 				SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
 109d0014:			0000: 0000235b 7e420000
-t0			write GRAS_CNTL (2003)
+			write GRAS_CNTL (2003)
 				GRAS_CNTL: { 0 }
 109d001c:			0000: 00002003 00000000
-t0			write RB_RENDER_CONTROL2 (20a3)
+			write RB_RENDER_CONTROL2 (20a3)
 				RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 }
 109d0024:			0000: 000020a3 00000000
-t0			write RB_FS_OUTPUT_REG (2100)
+			write RB_FS_OUTPUT_REG (2100)
 				RB_FS_OUTPUT_REG: { MRT = 1 }
 109d002c:			0000: 00002100 00000001
-t0			write SP_FS_OUTPUT_REG (22f0)
+			write SP_FS_OUTPUT_REG (22f0)
 				SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r0.x }
 109d0034:			0000: 000022f0 0000fc01
-t0			write SP_FS_MRT[0].REG (22f1)
+			write SP_FS_MRT[0].REG (22f1)
 				SP_FS_MRT[0].REG: { REGID = r0.x | MRTFORMAT = RB4_R8G8B8A8_UNORM }
 				SP_FS_MRT[0x1].REG: { REGID = r0.x | MRTFORMAT = 0 }
 				SP_FS_MRT[0x2].REG: { REGID = r0.x | MRTFORMAT = 0 }
@@ -2896,11 +2896,11 @@ t0			write SP_FS_MRT[0].REG (22f1)
 				SP_FS_MRT[0x7].REG: { REGID = r0.x | MRTFORMAT = 0 }
 109d003c:			0000: 000722f1 0001a000 00000000 00000000 00000000 00000000 00000000 00000000
 *
-t0			write VPC_ATTR (2140)
+			write VPC_ATTR (2140)
 				VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 }
 				VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 }
 109d0060:			0000: 00012140 42001004 00040400
-t0			write VPC_VARYING_INTERP[0].MODE (2142)
+			write VPC_VARYING_INTERP[0].MODE (2142)
 				VPC_VARYING_INTERP[0].MODE: 0x55
 				VPC_VARYING_INTERP[0x1].MODE: 0
 				VPC_VARYING_INTERP[0x2].MODE: 0
@@ -2911,7 +2911,7 @@ t0			write VPC_VARYING_INTERP[0].MODE (2142)
 				VPC_VARYING_INTERP[0x7].MODE: 0
 109d006c:			0000: 00072142 00000055 00000000 00000000 00000000 00000000 00000000 00000000
 *
-t0			write VPC_VARYING_PS_REPL[0].MODE (214a)
+			write VPC_VARYING_PS_REPL[0].MODE (214a)
 				VPC_VARYING_PS_REPL[0].MODE: 0
 				VPC_VARYING_PS_REPL[0x1].MODE: 0
 				VPC_VARYING_PS_REPL[0x2].MODE: 0
@@ -2922,7 +2922,7 @@ t0			write VPC_VARYING_PS_REPL[0].MODE (214a)
 				VPC_VARYING_PS_REPL[0x7].MODE: 0
 109d0090:			0000: 0007214a 00000000 00000000 00000000 00000000 00000000 00000000 00000000
 *
-t3			opcode: CP_LOAD_STATE4 (30) (131 dwords)
+			opcode: CP_LOAD_STATE4 (30) (131 dwords)
 				{ DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 4 }
 				{ STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 }
 				:2:0000:0000[40700000x_10000002x] mul.f r0.x, r0.z, c0.x
@@ -3001,7 +3001,7 @@ t3			opcode: CP_LOAD_STATE4 (30) (131 dwords)
 109d0234:			0180: 63800002 00031022 63800000 00011024 6382040e 00021025 6382040f 00001026
 109d0254:			01a0: 63820410 00000000 03000000 00000000 00000000 00000000 00000000 00000000
 *
-t3			opcode: CP_LOAD_STATE4 (30) (35 dwords)
+			opcode: CP_LOAD_STATE4 (30) (35 dwords)
 				{ DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_SHADER | NUM_UNIT = 1 }
 				{ STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 }
 				:0:0000:0000[00000000x_00000000x] nop
@@ -3024,9 +3024,9 @@ t3			opcode: CP_LOAD_STATE4 (30) (35 dwords)
 109d02e0:			0020: c7c60001 01c00004 c7c60002 01c00006 c7c60003 00002000 473090fc 00000000
 109d0300:			0040: 03000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
 *
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 109d034c:			0000: c0002600 00000000
-t3			opcode: CP_LOAD_STATE4 (30) (51 dwords)
+			opcode: CP_LOAD_STATE4 (30) (51 dwords)
 				{ DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 12 }
 				{ STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 }
 109d0360:				4.276816 0.109522 0.611668 0.517565 0.677381 4.774377 -0.312365 -0.264309
@@ -3048,53 +3048,53 @@ t3			opcode: CP_LOAD_STATE4 (30) (51 dwords)
 109d03d4:			0080: 00000000 00000000 3f800000 00000000 3f4ccccd 3e4ccccd 3f800000 00000000
 109d03f4:			00a0: 00000000 00000000 3f800000 00000000 00000000 00000000 3f800000 02020000
 109d0414:			00c0: 02020202 02020202 00000202
-t3			opcode: CP_LOAD_STATE4 (30) (7 dwords)
+			opcode: CP_LOAD_STATE4 (30) (7 dwords)
 				{ DST_OFF = 13 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 1 }
 				{ STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 }
 109d042c:				0.000000 -28026765312.000000 -28026765312.000000 -28026765312.000000
 109d042c:				0000: 00000000 d0d0d0d0 d0d0d0d0 d0d0d0d0
 109d0420:			0000: c0053000 0060000d 00000001 00000000 d0d0d0d0 d0d0d0d0 d0d0d0d0
-t0			write VFD_FETCH[0].INSTR_0 (220a)
+			write VFD_FETCH[0].INSTR_0 (220a)
 				VFD_FETCH[0].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 24 | SWITCHNEXT }
 				VFD_FETCH[0].INSTR_1: 0x107cb000
 				VFD_FETCH[0].INSTR_2: { SIZE = 0x100000 }
 				VFD_FETCH[0].INSTR_3: { STEPRATE = 1 }
 109d043c:			0000: 0003220a 00080c0b 107cb000 00100000 00000001
-t0			write VFD_DECODE[0].INSTR (228a)
+			write VFD_DECODE[0].INSTR (228a)
 				VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_FLOAT | REGID = r0.z | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID | SWITCHNEXT }
 109d0450:			0000: 0000228a 6c0020df
-t0			write VFD_FETCH[0x1].INSTR_0 (220e)
+			write VFD_FETCH[0x1].INSTR_0 (220e)
 				VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 24 }
 				VFD_FETCH[0x1].INSTR_1: 0x107cb00c
 				VFD_FETCH[0x1].INSTR_2: { SIZE = 0xffff4 }
 				VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 }
 109d0458:			0000: 0003220e 00000c0b 107cb00c 000ffff4 00000001
-t0			write VFD_DECODE[0x1].INSTR (228b)
+			write VFD_DECODE[0x1].INSTR (228b)
 				VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_FLOAT | REGID = r1.z | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID }
 109d046c:			0000: 0000228b 2c0060df
-t0			write VFD_CONTROL_0 (2200)
+			write VFD_CONTROL_0 (2200)
 				VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 }
 				VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x }
 				VFD_CONTROL_2: 0
 				VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x }
 				VFD_CONTROL_4: 0
 109d0474:			0000: 00042200 082a0008 fcfc0081 00000000 0000fc00 00000000
-t0			write UCHE_INVALIDATE0 (0e8a)
+			write UCHE_INVALIDATE0 (0e8a)
 				UCHE_INVALIDATE0: 0
 				UCHE_INVALIDATE1: 0x12
 109d048c:			0000: 00010e8a 00000000 00000012
-t0			write VFD_INDEX_OFFSET (2208)
+			write VFD_INDEX_OFFSET (2208)
 				VFD_INDEX_OFFSET: 0
 				UNKNOWN_2209: 0
 109d0498:			0000: 00012208 00000000 00000000
-t0			write PC_RESTART_INDEX (21c6)
+			write PC_RESTART_INDEX (21c6)
 				PC_RESTART_INDEX: 0xffffffff
 109d04a4:			0000: 000021c6 ffffffff
-t0			write CP_SCRATCH[0x7].REG (057f)
+			write CP_SCRATCH[0x7].REG (057f)
 				CP_SCRATCH[0x7].REG: 0x44
 				:0,67,115,68
 109d04ac:			0000: 0000057f 00000044
-t3			opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords)
+			opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords)
 				{ PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_16_BIT | PATCH_TYPE = TESS_QUADS }
 				{ NUM_INSTANCES = 1 }
 				{ NUM_INDICES = 240 }
@@ -3190,121 +3190,121 @@ t3			opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords)
  +	007e4200			HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
  +	00000003			HLSQ_UPDATE_CONTROL: 0x3
 109d04b4:			0000: c0053800 00000404 00000001 000000f0 00000000 10bd0d20 000001e0
-t0			write CP_SCRATCH[0x7].REG (057f)
+			write CP_SCRATCH[0x7].REG (057f)
 				CP_SCRATCH[0x7].REG: 0x45
 				:0,67,115,69
 109d04d0:			0000: 0000057f 00000045
-t0			write CP_SCRATCH[0x5].REG (057d)
+			write CP_SCRATCH[0x5].REG (057d)
 				CP_SCRATCH[0x5].REG: 0x49
 				:0,73,115,69
 109d04d8:			0000: 0000057d 00000049
-t0			write RB_DEPTH_CONTROL (2101)
+			write RB_DEPTH_CONTROL (2101)
 				RB_DEPTH_CONTROL: { Z_TEST_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_READ_ENABLE }
 109d04e0:			0000: 00002101 80000016
-t0			write GRAS_ALPHA_CONTROL (2073)
+			write GRAS_ALPHA_CONTROL (2073)
 				GRAS_ALPHA_CONTROL: { 0 }
 109d04e8:			0000: 00002073 00000000
-t0			write GRAS_SU_MODE_CONTROL (2078)
+			write GRAS_SU_MODE_CONTROL (2078)
 				GRAS_SU_MODE_CONTROL: { CULL_BACK | LINEHALFWIDTH = 0.500000 | RENDERING_PASS }
 109d04f0:			0000: 00002078 00100012
-t0			write GRAS_SU_POINT_MINMAX (2070)
+			write GRAS_SU_POINT_MINMAX (2070)
 				GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 1.000000 }
 				GRAS_SU_POINT_SIZE: 1.000000
 109d04f8:			0000: 00012070 00100010 00000010
-t0			write GRAS_SU_POLY_OFFSET_SCALE (2074)
+			write GRAS_SU_POLY_OFFSET_SCALE (2074)
 				GRAS_SU_POLY_OFFSET_SCALE: 0.000000
 				GRAS_SU_POLY_OFFSET_OFFSET: 0.000000
 				GRAS_SU_POLY_OFFSET_CLAMP: 0.000000
 109d0504:			0000: 00022074 00000000 00000000 00000000
-t0			write GRAS_CL_CLIP_CNTL (2000)
+			write GRAS_CL_CLIP_CNTL (2000)
 				GRAS_CL_CLIP_CNTL: { 0x80000 }
 109d0514:			0000: 00002000 00080000
-t0			write PC_PRIM_VTX_CNTL (21c4)
+			write PC_PRIM_VTX_CNTL (21c4)
 				PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST }
 				PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES }
 109d051c:			0000: 000121c4 02000001 00000012
-t0			write GRAS_SC_WINDOW_SCISSOR_BR (209c)
+			write GRAS_SC_WINDOW_SCISSOR_BR (209c)
 				GRAS_SC_WINDOW_SCISSOR_BR: { X = 299 | Y = 299 }
 				GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
 109d0528:			0000: 0001209c 012b012b 00000000
-t0			write RB_VPORT_Z_CLAMP[0].MIN (2120)
+			write RB_VPORT_Z_CLAMP[0].MIN (2120)
 				RB_VPORT_Z_CLAMP[0].MIN: 0
 				RB_VPORT_Z_CLAMP[0].MAX: 0xffffff
 109d0534:			0000: 00012120 00000000 00ffffff
-t0			write HLSQ_UPDATE_CONTROL (23db)
+			write HLSQ_UPDATE_CONTROL (23db)
 				HLSQ_UPDATE_CONTROL: 0x3
 109d0540:			0000: 000023db 00000003
-t0			write HLSQ_CONTROL_0_REG (23c0)
+			write HLSQ_CONTROL_0_REG (23c0)
 				HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | SPSHADERRESTART | CONSTMODE = 1 | SPCONSTFULLUPDATE }
 				HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x }
 				HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x }
 				HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x }
 				HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 }
 109d0548:			0000: 000423c0 28000250 fcfc0100 fff3f3f0 fcfcfc00 00fcfcfc
-t0			write HLSQ_VS_CONTROL_REG (23c5)
+			write HLSQ_VS_CONTROL_REG (23c5)
 				HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 4 }
 				HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 }
 				HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
 				HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
 				HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
 109d0560:			0000: 000423c5 04000042 017e423e 007e4200 007e4200 007e4200
-t0			write SP_SP_CTRL_REG (22c0)
+			write SP_SP_CTRL_REG (22c0)
 				SP_SP_CTRL_REG: { 0x140010 }
 109d0578:			0000: 000022c0 00140010
-t0			write SP_INSTR_CACHE_CTRL (22c1)
+			write SP_INSTR_CACHE_CTRL (22c1)
 				SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x7f }
 109d0580:			0000: 000022c1 000005ff
-t0			write SP_VS_LENGTH_REG (22e5)
+			write SP_VS_LENGTH_REG (22e5)
 				SP_VS_LENGTH_REG: 4
 109d0588:			0000: 000022e5 00000004
-t0			write SP_VS_CTRL_REG0 (22c4)
+			write SP_VS_CTRL_REG0 (22c4)
 				SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 5 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE }
 				SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 8 }
 				SP_VS_PARAM_REG: { POSREGID = r2.z | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 }
 109d0590:			0000: 000222c4 00201400 08000042 0010fc0a
-t0			write SP_VS_OUT[0].REG (22c7)
+			write SP_VS_OUT[0].REG (22c7)
 				SP_VS_OUT[0].REG: { A_REGID = r3.z | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 }
 109d05a0:			0000: 000022c7 00001e0e
-t0			write SP_VS_VPC_DST[0].REG (22d8)
+			write SP_VS_VPC_DST[0].REG (22d8)
 				SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 8 | OUTLOC2 = 8 | OUTLOC3 = 8 }
 109d05a8:			0000: 000022d8 08080808
-t0			write SP_VS_OBJ_OFFSET_REG (22e0)
+			write SP_VS_OBJ_OFFSET_REG (22e0)
 				SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 }
 				SP_VS_OBJ_START: 0x10cd5000
 109d05b0:			0000: 000122e0 00000000 10cd5000
-t0			write SP_FS_LENGTH_REG (22ef)
+			write SP_FS_LENGTH_REG (22ef)
 				SP_FS_LENGTH_REG: 1
 109d05bc:			0000: 000022ef 00000001
-t0			write SP_FS_CTRL_REG0 (22e8)
+			write SP_FS_CTRL_REG0 (22e8)
 				SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 2 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE }
 				SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 }
 109d05c4:			0000: 000122e8 00340802 8010003e
-t0			write SP_FS_OBJ_OFFSET_REG (22ea)
+			write SP_FS_OBJ_OFFSET_REG (22ea)
 				SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
 				SP_FS_OBJ_START: 0x108cb000
 109d05d0:			0000: 000122ea 7e420000 108cb000
-t0			write SP_HS_OBJ_OFFSET_REG (230d)
+			write SP_HS_OBJ_OFFSET_REG (230d)
 				SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
 109d05dc:			0000: 0000230d 7e420000
-t0			write SP_DS_OBJ_OFFSET_REG (2334)
+			write SP_DS_OBJ_OFFSET_REG (2334)
 				SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
 109d05e4:			0000: 00002334 7e420000
-t0			write SP_GS_OBJ_OFFSET_REG (235b)
+			write SP_GS_OBJ_OFFSET_REG (235b)
 				SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
 109d05ec:			0000: 0000235b 7e420000
-t0			write GRAS_CNTL (2003)
+			write GRAS_CNTL (2003)
 				GRAS_CNTL: { IJ_PERSP }
 109d05f4:			0000: 00002003 00000001
-t0			write RB_RENDER_CONTROL2 (20a3)
+			write RB_RENDER_CONTROL2 (20a3)
 				RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 | IJ_PERSP_PIXEL }
 109d05fc:			0000: 000020a3 00001000
-t0			write RB_FS_OUTPUT_REG (2100)
+			write RB_FS_OUTPUT_REG (2100)
 				RB_FS_OUTPUT_REG: { MRT = 1 }
 109d0604:			0000: 00002100 00000001
-t0			write SP_FS_OUTPUT_REG (22f0)
+			write SP_FS_OUTPUT_REG (22f0)
 				SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r0.x }
 109d060c:			0000: 000022f0 0000fc01
-t0			write SP_FS_MRT[0].REG (22f1)
+			write SP_FS_MRT[0].REG (22f1)
 				SP_FS_MRT[0].REG: { REGID = r0.z | MRTFORMAT = RB4_R8G8B8A8_UNORM }
 				SP_FS_MRT[0x1].REG: { REGID = r0.z | MRTFORMAT = 0 }
 				SP_FS_MRT[0x2].REG: { REGID = r0.z | MRTFORMAT = 0 }
@@ -3315,11 +3315,11 @@ t0			write SP_FS_MRT[0].REG (22f1)
 				SP_FS_MRT[0x7].REG: { REGID = r0.z | MRTFORMAT = 0 }
 109d0614:			0000: 000722f1 0001a002 00000002 00000002 00000002 00000002 00000002 00000002
 109d0634:			0020: 00000002
-t0			write VPC_ATTR (2140)
+			write VPC_ATTR (2140)
 				VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 }
 				VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 }
 109d0638:			0000: 00012140 42001004 00040400
-t0			write VPC_VARYING_INTERP[0].MODE (2142)
+			write VPC_VARYING_INTERP[0].MODE (2142)
 				VPC_VARYING_INTERP[0].MODE: 0
 				VPC_VARYING_INTERP[0x1].MODE: 0
 				VPC_VARYING_INTERP[0x2].MODE: 0
@@ -3330,7 +3330,7 @@ t0			write VPC_VARYING_INTERP[0].MODE (2142)
 				VPC_VARYING_INTERP[0x7].MODE: 0
 109d0644:			0000: 00072142 00000000 00000000 00000000 00000000 00000000 00000000 00000000
 *
-t0			write VPC_VARYING_PS_REPL[0].MODE (214a)
+			write VPC_VARYING_PS_REPL[0].MODE (214a)
 				VPC_VARYING_PS_REPL[0].MODE: 0
 				VPC_VARYING_PS_REPL[0x1].MODE: 0
 				VPC_VARYING_PS_REPL[0x2].MODE: 0
@@ -3341,7 +3341,7 @@ t0			write VPC_VARYING_PS_REPL[0].MODE (214a)
 				VPC_VARYING_PS_REPL[0x7].MODE: 0
 109d0668:			0000: 0007214a 00000000 00000000 00000000 00000000 00000000 00000000 00000000
 *
-t3			opcode: CP_LOAD_STATE4 (30) (131 dwords)
+			opcode: CP_LOAD_STATE4 (30) (131 dwords)
 				{ DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 4 }
 				{ STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 }
 				:2:0000:0000[40700000x_10000002x] mul.f r0.x, r0.z, c0.x
@@ -3420,7 +3420,7 @@ t3			opcode: CP_LOAD_STATE4 (30) (131 dwords)
 109d080c:			0180: 63800002 00031022 63800000 00011024 6382040e 00021025 6382040f 00001026
 109d082c:			01a0: 63820410 00000000 03000000 00000000 00000000 00000000 00000000 00000000
 *
-t3			opcode: CP_LOAD_STATE4 (30) (35 dwords)
+			opcode: CP_LOAD_STATE4 (30) (35 dwords)
 				{ DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_SHADER | NUM_UNIT = 1 }
 				{ STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 }
 				:2:0000:0000[47300002x_00002000x] bary.f r0.z, 0, r0.x
@@ -3440,9 +3440,9 @@ t3			opcode: CP_LOAD_STATE4 (30) (35 dwords)
 109d0898:			0000: c0213000 00700000 00000000 00002000 47300002 00002001 47300003 00002002
 109d08b8:			0020: 47300004 00002003 47308005 00000000 03000000 00000000 00000000 00000000
 *
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 109d0924:			0000: c0002600 00000000
-t3			opcode: CP_LOAD_STATE4 (30) (51 dwords)
+			opcode: CP_LOAD_STATE4 (30) (51 dwords)
 				{ DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 12 }
 				{ STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 }
 109d0938:				4.276816 0.109522 0.611668 0.517565 0.677381 4.774377 -0.312365 -0.264309
@@ -3464,18 +3464,18 @@ t3			opcode: CP_LOAD_STATE4 (30) (51 dwords)
 109d09ac:			0080: 00000000 00000000 3f800000 00000000 3f4ccccd 3e4ccccd 3f800000 00000000
 109d09cc:			00a0: 00000000 00000000 3f800000 00000000 00000000 00000000 3f800000 02020000
 109d09ec:			00c0: 02020202 02020202 00000202
-t0			write VFD_INDEX_OFFSET (2208)
+			write VFD_INDEX_OFFSET (2208)
 				VFD_INDEX_OFFSET: 0
 				UNKNOWN_2209: 0
 109d09f8:			0000: 00012208 00000000 00000000
-t0			write PC_RESTART_INDEX (21c6)
+			write PC_RESTART_INDEX (21c6)
 				PC_RESTART_INDEX: 0xffffffff
 109d0a04:			0000: 000021c6 ffffffff
-t0			write CP_SCRATCH[0x7].REG (057f)
+			write CP_SCRATCH[0x7].REG (057f)
 				CP_SCRATCH[0x7].REG: 0x4a
 				:0,73,115,74
 109d0a0c:			0000: 0000057f 0000004a
-t3			opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords)
+			opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords)
 				{ PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_16_BIT | PATCH_TYPE = TESS_QUADS }
 				{ NUM_INSTANCES = 1 }
 				{ NUM_INDICES = 60 }
@@ -3565,121 +3565,121 @@ t3			opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords)
  +	007e4200			HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
  +	00000003			HLSQ_UPDATE_CONTROL: 0x3
 109d0a14:			0000: c0053800 00000404 00000001 0000003c 00000000 10bd0f00 00000078
-t0			write CP_SCRATCH[0x7].REG (057f)
+			write CP_SCRATCH[0x7].REG (057f)
 				CP_SCRATCH[0x7].REG: 0x4b
 				:0,73,115,75
 109d0a30:			0000: 0000057f 0000004b
-t0			write CP_SCRATCH[0x5].REG (057d)
+			write CP_SCRATCH[0x5].REG (057d)
 				CP_SCRATCH[0x5].REG: 0x4f
 				:0,79,115,75
 109d0a38:			0000: 0000057d 0000004f
-t0			write RB_DEPTH_CONTROL (2101)
+			write RB_DEPTH_CONTROL (2101)
 				RB_DEPTH_CONTROL: { Z_TEST_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_READ_ENABLE }
 109d0a40:			0000: 00002101 80000016
-t0			write GRAS_ALPHA_CONTROL (2073)
+			write GRAS_ALPHA_CONTROL (2073)
 				GRAS_ALPHA_CONTROL: { 0 }
 109d0a48:			0000: 00002073 00000000
-t0			write GRAS_SU_MODE_CONTROL (2078)
+			write GRAS_SU_MODE_CONTROL (2078)
 				GRAS_SU_MODE_CONTROL: { CULL_BACK | LINEHALFWIDTH = 0.500000 | RENDERING_PASS }
 109d0a50:			0000: 00002078 00100012
-t0			write GRAS_SU_POINT_MINMAX (2070)
+			write GRAS_SU_POINT_MINMAX (2070)
 				GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 1.000000 }
 				GRAS_SU_POINT_SIZE: 1.000000
 109d0a58:			0000: 00012070 00100010 00000010
-t0			write GRAS_SU_POLY_OFFSET_SCALE (2074)
+			write GRAS_SU_POLY_OFFSET_SCALE (2074)
 				GRAS_SU_POLY_OFFSET_SCALE: 0.000000
 				GRAS_SU_POLY_OFFSET_OFFSET: 0.000000
 				GRAS_SU_POLY_OFFSET_CLAMP: 0.000000
 109d0a64:			0000: 00022074 00000000 00000000 00000000
-t0			write GRAS_CL_CLIP_CNTL (2000)
+			write GRAS_CL_CLIP_CNTL (2000)
 				GRAS_CL_CLIP_CNTL: { 0x80000 }
 109d0a74:			0000: 00002000 00080000
-t0			write PC_PRIM_VTX_CNTL (21c4)
+			write PC_PRIM_VTX_CNTL (21c4)
 				PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST }
 				PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES }
 109d0a7c:			0000: 000121c4 02000001 00000012
-t0			write GRAS_SC_WINDOW_SCISSOR_BR (209c)
+			write GRAS_SC_WINDOW_SCISSOR_BR (209c)
 				GRAS_SC_WINDOW_SCISSOR_BR: { X = 299 | Y = 299 }
 				GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
 109d0a88:			0000: 0001209c 012b012b 00000000
-t0			write RB_VPORT_Z_CLAMP[0].MIN (2120)
+			write RB_VPORT_Z_CLAMP[0].MIN (2120)
 				RB_VPORT_Z_CLAMP[0].MIN: 0
 				RB_VPORT_Z_CLAMP[0].MAX: 0xffffff
 109d0a94:			0000: 00012120 00000000 00ffffff
-t0			write HLSQ_UPDATE_CONTROL (23db)
+			write HLSQ_UPDATE_CONTROL (23db)
 				HLSQ_UPDATE_CONTROL: 0x3
 109d0aa0:			0000: 000023db 00000003
-t0			write HLSQ_CONTROL_0_REG (23c0)
+			write HLSQ_CONTROL_0_REG (23c0)
 				HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | SPSHADERRESTART | CONSTMODE = 1 | SPCONSTFULLUPDATE }
 				HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x }
 				HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x }
 				HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r63.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x }
 				HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 }
 109d0aa8:			0000: 000423c0 28000250 fcfc0100 fff3f3f0 fcfcfcfc 00fcfcfc
-t0			write HLSQ_VS_CONTROL_REG (23c5)
+			write HLSQ_VS_CONTROL_REG (23c5)
 				HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 4 }
 				HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 }
 				HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
 				HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
 				HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
 109d0ac0:			0000: 000423c5 04000042 017e423e 007e4200 007e4200 007e4200
-t0			write SP_SP_CTRL_REG (22c0)
+			write SP_SP_CTRL_REG (22c0)
 				SP_SP_CTRL_REG: { 0x140010 }
 109d0ad8:			0000: 000022c0 00140010
-t0			write SP_INSTR_CACHE_CTRL (22c1)
+			write SP_INSTR_CACHE_CTRL (22c1)
 				SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x7f }
 109d0ae0:			0000: 000022c1 000005ff
-t0			write SP_VS_LENGTH_REG (22e5)
+			write SP_VS_LENGTH_REG (22e5)
 				SP_VS_LENGTH_REG: 4
 109d0ae8:			0000: 000022e5 00000004
-t0			write SP_VS_CTRL_REG0 (22c4)
+			write SP_VS_CTRL_REG0 (22c4)
 				SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 4 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE }
 				SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 4 }
 				SP_VS_PARAM_REG: { POSREGID = r1.z | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 }
 109d0af0:			0000: 000222c4 00201000 04000042 0010fc06
-t0			write SP_VS_OUT[0].REG (22c7)
+			write SP_VS_OUT[0].REG (22c7)
 				SP_VS_OUT[0].REG: { A_REGID = r2.z | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 }
 109d0b00:			0000: 000022c7 00001e0a
-t0			write SP_VS_VPC_DST[0].REG (22d8)
+			write SP_VS_VPC_DST[0].REG (22d8)
 				SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 8 | OUTLOC2 = 8 | OUTLOC3 = 8 }
 109d0b08:			0000: 000022d8 08080808
-t0			write SP_VS_OBJ_OFFSET_REG (22e0)
+			write SP_VS_OBJ_OFFSET_REG (22e0)
 				SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 }
 				SP_VS_OBJ_START: 0x10cd0000
 109d0b10:			0000: 000122e0 00000000 10cd0000
-t0			write SP_FS_LENGTH_REG (22ef)
+			write SP_FS_LENGTH_REG (22ef)
 				SP_FS_LENGTH_REG: 1
 109d0b1c:			0000: 000022ef 00000001
-t0			write SP_FS_CTRL_REG0 (22e8)
+			write SP_FS_CTRL_REG0 (22e8)
 				SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE }
 				SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 }
 109d0b24:			0000: 000122e8 00340402 8010003e
-t0			write SP_FS_OBJ_OFFSET_REG (22ea)
+			write SP_FS_OBJ_OFFSET_REG (22ea)
 				SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
 				SP_FS_OBJ_START: 0x10cd2000
 109d0b30:			0000: 000122ea 7e420000 10cd2000
-t0			write SP_HS_OBJ_OFFSET_REG (230d)
+			write SP_HS_OBJ_OFFSET_REG (230d)
 				SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
 109d0b3c:			0000: 0000230d 7e420000
-t0			write SP_DS_OBJ_OFFSET_REG (2334)
+			write SP_DS_OBJ_OFFSET_REG (2334)
 				SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
 109d0b44:			0000: 00002334 7e420000
-t0			write SP_GS_OBJ_OFFSET_REG (235b)
+			write SP_GS_OBJ_OFFSET_REG (235b)
 				SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
 109d0b4c:			0000: 0000235b 7e420000
-t0			write GRAS_CNTL (2003)
+			write GRAS_CNTL (2003)
 				GRAS_CNTL: { 0 }
 109d0b54:			0000: 00002003 00000000
-t0			write RB_RENDER_CONTROL2 (20a3)
+			write RB_RENDER_CONTROL2 (20a3)
 				RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 }
 109d0b5c:			0000: 000020a3 00000000
-t0			write RB_FS_OUTPUT_REG (2100)
+			write RB_FS_OUTPUT_REG (2100)
 				RB_FS_OUTPUT_REG: { MRT = 1 }
 109d0b64:			0000: 00002100 00000001
-t0			write SP_FS_OUTPUT_REG (22f0)
+			write SP_FS_OUTPUT_REG (22f0)
 				SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r0.x }
 109d0b6c:			0000: 000022f0 0000fc01
-t0			write SP_FS_MRT[0].REG (22f1)
+			write SP_FS_MRT[0].REG (22f1)
 				SP_FS_MRT[0].REG: { REGID = r0.x | MRTFORMAT = RB4_R8G8B8A8_UNORM }
 				SP_FS_MRT[0x1].REG: { REGID = r0.x | MRTFORMAT = 0 }
 				SP_FS_MRT[0x2].REG: { REGID = r0.x | MRTFORMAT = 0 }
@@ -3690,11 +3690,11 @@ t0			write SP_FS_MRT[0].REG (22f1)
 				SP_FS_MRT[0x7].REG: { REGID = r0.x | MRTFORMAT = 0 }
 109d0b74:			0000: 000722f1 0001a000 00000000 00000000 00000000 00000000 00000000 00000000
 *
-t0			write VPC_ATTR (2140)
+			write VPC_ATTR (2140)
 				VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 }
 				VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 }
 109d0b98:			0000: 00012140 42001004 00040400
-t0			write VPC_VARYING_INTERP[0].MODE (2142)
+			write VPC_VARYING_INTERP[0].MODE (2142)
 				VPC_VARYING_INTERP[0].MODE: 0x55
 				VPC_VARYING_INTERP[0x1].MODE: 0
 				VPC_VARYING_INTERP[0x2].MODE: 0
@@ -3705,7 +3705,7 @@ t0			write VPC_VARYING_INTERP[0].MODE (2142)
 				VPC_VARYING_INTERP[0x7].MODE: 0
 109d0ba4:			0000: 00072142 00000055 00000000 00000000 00000000 00000000 00000000 00000000
 *
-t0			write VPC_VARYING_PS_REPL[0].MODE (214a)
+			write VPC_VARYING_PS_REPL[0].MODE (214a)
 				VPC_VARYING_PS_REPL[0].MODE: 0
 				VPC_VARYING_PS_REPL[0x1].MODE: 0
 				VPC_VARYING_PS_REPL[0x2].MODE: 0
@@ -3716,7 +3716,7 @@ t0			write VPC_VARYING_PS_REPL[0].MODE (214a)
 				VPC_VARYING_PS_REPL[0x7].MODE: 0
 109d0bc8:			0000: 0007214a 00000000 00000000 00000000 00000000 00000000 00000000 00000000
 *
-t3			opcode: CP_LOAD_STATE4 (30) (131 dwords)
+			opcode: CP_LOAD_STATE4 (30) (131 dwords)
 				{ DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 4 }
 				{ STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 }
 				:2:0000:0000[40700000x_10000002x] mul.f r0.x, r0.z, c0.x
@@ -3801,7 +3801,7 @@ t3			opcode: CP_LOAD_STATE4 (30) (131 dwords)
 109d0d8c:			01a0: 63800001 00021025 63800002 00031026 63800000 00011028 6382040a 00021029
 109d0dac:			01c0: 6382040b 0000102a 6382040c 00000000 03000000 00000000 00000000 00000000
 *
-t3			opcode: CP_LOAD_STATE4 (30) (35 dwords)
+			opcode: CP_LOAD_STATE4 (30) (35 dwords)
 				{ DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_SHADER | NUM_UNIT = 1 }
 				{ STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 }
 				:0:0000:0000[00000000x_00000000x] nop
@@ -3824,9 +3824,9 @@ t3			opcode: CP_LOAD_STATE4 (30) (35 dwords)
 109d0e18:			0020: c7c60001 01c00004 c7c60002 01c00006 c7c60003 00002000 473090fc 00000000
 109d0e38:			0040: 03000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
 *
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 109d0e84:			0000: c0002600 00000000
-t3			opcode: CP_LOAD_STATE4 (30) (51 dwords)
+			opcode: CP_LOAD_STATE4 (30) (51 dwords)
 				{ DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 12 }
 				{ STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 }
 109d0e98:				3.924428 -1.210718 0.674073 0.570369 1.829991 4.619613 -0.131666 -0.111410
@@ -3848,44 +3848,44 @@ t3			opcode: CP_LOAD_STATE4 (30) (51 dwords)
 109d0f0c:			0080: 00000000 00000000 00000000 00000000 00000000 00000000 3f800000 3e4ccccd
 109d0f2c:			00a0: 3e4ccccd 3f800000 3f800000 00000000 00000000 00000000 3f800000 00000000
 109d0f4c:			00c0: 00000000 00000000 3f800000
-t3			opcode: CP_LOAD_STATE4 (30) (7 dwords)
+			opcode: CP_LOAD_STATE4 (30) (7 dwords)
 				{ DST_OFF = 13 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 1 }
 				{ STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 }
 109d0f64:				0.000000 -28026765312.000000 -28026765312.000000 -28026765312.000000
 109d0f64:				0000: 00000000 d0d0d0d0 d0d0d0d0 d0d0d0d0
 109d0f58:			0000: c0053000 0060000d 00000001 00000000 d0d0d0d0 d0d0d0d0 d0d0d0d0
-t0			write VFD_FETCH[0].INSTR_0 (220a)
+			write VFD_FETCH[0].INSTR_0 (220a)
 				VFD_FETCH[0].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 12 }
 				VFD_FETCH[0].INSTR_1: 0x107cb000
 				VFD_FETCH[0].INSTR_2: { SIZE = 0x100000 }
 				VFD_FETCH[0].INSTR_3: { STEPRATE = 1 }
 109d0f74:			0000: 0003220a 0000060b 107cb000 00100000 00000001
-t0			write VFD_DECODE[0].INSTR (228a)
+			write VFD_DECODE[0].INSTR (228a)
 				VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_FLOAT | REGID = r0.z | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID }
 109d0f88:			0000: 0000228a 2c0020df
-t0			write VFD_CONTROL_0 (2200)
+			write VFD_CONTROL_0 (2200)
 				VFD_CONTROL_0: { TOTALATTRTOVS = 4 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 1 | STRMFETCHINSTRCNT = 1 | 0xa0000 }
 				VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x }
 				VFD_CONTROL_2: 0
 				VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x }
 				VFD_CONTROL_4: 0
 109d0f90:			0000: 00042200 041a0004 fcfc0081 00000000 0000fc00 00000000
-t0			write UCHE_INVALIDATE0 (0e8a)
+			write UCHE_INVALIDATE0 (0e8a)
 				UCHE_INVALIDATE0: 0
 				UCHE_INVALIDATE1: 0x12
 109d0fa8:			0000: 00010e8a 00000000 00000012
-t0			write VFD_INDEX_OFFSET (2208)
+			write VFD_INDEX_OFFSET (2208)
 				VFD_INDEX_OFFSET: 0
 				UNKNOWN_2209: 0
 109d0fb4:			0000: 00012208 00000000 00000000
-t0			write PC_RESTART_INDEX (21c6)
+			write PC_RESTART_INDEX (21c6)
 				PC_RESTART_INDEX: 0xffffffff
 109d0fc0:			0000: 000021c6 ffffffff
-t0			write CP_SCRATCH[0x7].REG (057f)
+			write CP_SCRATCH[0x7].REG (057f)
 				CP_SCRATCH[0x7].REG: 0x50
 				:0,79,115,80
 109d0fc8:			0000: 0000057f 00000050
-t3			opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords)
+			opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords)
 				{ PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_16_BIT | PATCH_TYPE = TESS_QUADS }
 				{ NUM_INSTANCES = 1 }
 				{ NUM_INDICES = 120 }
@@ -3987,30 +3987,30 @@ t3			opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords)
  +	007e4200			HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
  +	00000003			HLSQ_UPDATE_CONTROL: 0x3
 109d0fd0:			0000: c0053800 00000404 00000001 00000078 00000000 10bd0f78 000000f0
-t0			write CP_SCRATCH[0x7].REG (057f)
+			write CP_SCRATCH[0x7].REG (057f)
 				CP_SCRATCH[0x7].REG: 0x51
 				:0,79,115,81
 109d0fec:			0000: 0000057f 00000051
-t0			write CP_SCRATCH[0x5].REG (057d)
+			write CP_SCRATCH[0x5].REG (057d)
 				CP_SCRATCH[0x5].REG: 0x55
 				:0,85,115,81
 109d0ff4:			0000: 0000057d 00000055
-t0			write PC_PRIM_VTX_CNTL (21c4)
+			write PC_PRIM_VTX_CNTL (21c4)
 				PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST }
 				PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES }
 109d0ffc:			0000: 000121c4 02000001 00000012
-t0			write VFD_INDEX_OFFSET (2208)
+			write VFD_INDEX_OFFSET (2208)
 				VFD_INDEX_OFFSET: 0
 				UNKNOWN_2209: 0
 109d1008:			0000: 00012208 00000000 00000000
-t0			write PC_RESTART_INDEX (21c6)
+			write PC_RESTART_INDEX (21c6)
 				PC_RESTART_INDEX: 0xffffffff
 109d1014:			0000: 000021c6 ffffffff
-t0			write CP_SCRATCH[0x7].REG (057f)
+			write CP_SCRATCH[0x7].REG (057f)
 				CP_SCRATCH[0x7].REG: 0x56
 				:0,85,115,86
 109d101c:			0000: 0000057f 00000056
-t3			opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords)
+			opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords)
 				{ PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_16_BIT | PATCH_TYPE = TESS_QUADS }
 				{ NUM_INSTANCES = 1 }
 				{ NUM_INDICES = 60 }
@@ -4028,21 +4028,21 @@ t3			opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords)
  +	00000000			VFD_INDEX_OFFSET: 0
  +	00000000			UNKNOWN_2209: 0
 109d1024:			0000: c0053800 00000404 00000001 0000003c 00000000 10bd1068 00000078
-t0			write CP_SCRATCH[0x7].REG (057f)
+			write CP_SCRATCH[0x7].REG (057f)
 				CP_SCRATCH[0x7].REG: 0x57
 				:0,85,115,87
 109d1040:			0000: 0000057f 00000057
-t0			write CP_SCRATCH[0x5].REG (057d)
+			write CP_SCRATCH[0x5].REG (057d)
 				CP_SCRATCH[0x5].REG: 0x5b
 				:0,91,115,87
 109d1048:			0000: 0000057d 0000005b
-t0			write PC_PRIM_VTX_CNTL (21c4)
+			write PC_PRIM_VTX_CNTL (21c4)
 				PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST }
 				PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES }
 109d1050:			0000: 000121c4 02000001 00000012
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 109d105c:			0000: c0002600 00000000
-t3			opcode: CP_LOAD_STATE4 (30) (51 dwords)
+			opcode: CP_LOAD_STATE4 (30) (51 dwords)
 				{ DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 12 }
 				{ STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 }
 109d1070:				3.924428 -1.210718 0.674073 0.570369 1.829991 4.619613 -0.131666 -0.111410
@@ -4064,18 +4064,18 @@ t3			opcode: CP_LOAD_STATE4 (30) (51 dwords)
 109d10e4:			0080: 00000000 00000000 00000000 00000000 00000000 00000000 3f800000 3e4ccccd
 109d1104:			00a0: 3e4ccccd 3f800000 3f800000 00000000 00000000 00000000 3f800000 00000000
 109d1124:			00c0: 00000000 00000000 3f800000
-t0			write VFD_INDEX_OFFSET (2208)
+			write VFD_INDEX_OFFSET (2208)
 				VFD_INDEX_OFFSET: 0
 				UNKNOWN_2209: 0
 109d1130:			0000: 00012208 00000000 00000000
-t0			write PC_RESTART_INDEX (21c6)
+			write PC_RESTART_INDEX (21c6)
 				PC_RESTART_INDEX: 0xffffffff
 109d113c:			0000: 000021c6 ffffffff
-t0			write CP_SCRATCH[0x7].REG (057f)
+			write CP_SCRATCH[0x7].REG (057f)
 				CP_SCRATCH[0x7].REG: 0x5c
 				:0,91,115,92
 109d1144:			0000: 0000057f 0000005c
-t3			opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords)
+			opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords)
 				{ PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_16_BIT | PATCH_TYPE = TESS_QUADS }
 				{ NUM_INSTANCES = 1 }
 				{ NUM_INDICES = 120 }
@@ -4093,30 +4093,30 @@ t3			opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords)
  +	00000000			VFD_INDEX_OFFSET: 0
  +	00000000			UNKNOWN_2209: 0
 109d114c:			0000: c0053800 00000404 00000001 00000078 00000000 10bd10e0 000000f0
-t0			write CP_SCRATCH[0x7].REG (057f)
+			write CP_SCRATCH[0x7].REG (057f)
 				CP_SCRATCH[0x7].REG: 0x5d
 				:0,91,115,93
 109d1168:			0000: 0000057f 0000005d
-t0			write CP_SCRATCH[0x5].REG (057d)
+			write CP_SCRATCH[0x5].REG (057d)
 				CP_SCRATCH[0x5].REG: 0x61
 				:0,97,115,93
 109d1170:			0000: 0000057d 00000061
-t0			write PC_PRIM_VTX_CNTL (21c4)
+			write PC_PRIM_VTX_CNTL (21c4)
 				PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST }
 				PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES }
 109d1178:			0000: 000121c4 02000001 00000012
-t0			write VFD_INDEX_OFFSET (2208)
+			write VFD_INDEX_OFFSET (2208)
 				VFD_INDEX_OFFSET: 0
 				UNKNOWN_2209: 0
 109d1184:			0000: 00012208 00000000 00000000
-t0			write PC_RESTART_INDEX (21c6)
+			write PC_RESTART_INDEX (21c6)
 				PC_RESTART_INDEX: 0xffffffff
 109d1190:			0000: 000021c6 ffffffff
-t0			write CP_SCRATCH[0x7].REG (057f)
+			write CP_SCRATCH[0x7].REG (057f)
 				CP_SCRATCH[0x7].REG: 0x62
 				:0,97,115,98
 109d1198:			0000: 0000057f 00000062
-t3			opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords)
+			opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords)
 				{ PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_16_BIT | PATCH_TYPE = TESS_QUADS }
 				{ NUM_INSTANCES = 1 }
 				{ NUM_INDICES = 60 }
@@ -4134,98 +4134,98 @@ t3			opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords)
  +	00000000			VFD_INDEX_OFFSET: 0
  +	00000000			UNKNOWN_2209: 0
 109d11a0:			0000: c0053800 00000404 00000001 0000003c 00000000 10bd11d0 00000078
-t0			write CP_SCRATCH[0x7].REG (057f)
+			write CP_SCRATCH[0x7].REG (057f)
 				CP_SCRATCH[0x7].REG: 0x63
 				:0,97,115,99
 109d11bc:			0000: 0000057f 00000063
-t0			write CP_SCRATCH[0x5].REG (057d)
+			write CP_SCRATCH[0x5].REG (057d)
 				CP_SCRATCH[0x5].REG: 0x67
 				:0,103,115,99
 109d11c4:			0000: 0000057d 00000067
-t0			write RB_DEPTH_CONTROL (2101)
+			write RB_DEPTH_CONTROL (2101)
 				RB_DEPTH_CONTROL: { Z_TEST_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_READ_ENABLE }
 109d11cc:			0000: 00002101 80000016
-t0			write GRAS_ALPHA_CONTROL (2073)
+			write GRAS_ALPHA_CONTROL (2073)
 				GRAS_ALPHA_CONTROL: { 0 }
 109d11d4:			0000: 00002073 00000000
-t0			write PC_PRIM_VTX_CNTL (21c4)
+			write PC_PRIM_VTX_CNTL (21c4)
 				PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST }
 				PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES }
 109d11dc:			0000: 000121c4 02000001 00000012
-t0			write HLSQ_UPDATE_CONTROL (23db)
+			write HLSQ_UPDATE_CONTROL (23db)
 				HLSQ_UPDATE_CONTROL: 0x3
 109d11e8:			0000: 000023db 00000003
-t0			write HLSQ_CONTROL_0_REG (23c0)
+			write HLSQ_CONTROL_0_REG (23c0)
 				HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | SPSHADERRESTART | CONSTMODE = 1 | SPCONSTFULLUPDATE }
 				HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x }
 				HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x }
 				HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r63.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x }
 				HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 }
 109d11f0:			0000: 000423c0 28000250 fcfc0100 fff3f3f0 fcfcfcfc 00fcfcfc
-t0			write HLSQ_VS_CONTROL_REG (23c5)
+			write HLSQ_VS_CONTROL_REG (23c5)
 				HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 4 }
 				HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 }
 				HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
 				HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
 				HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
 109d1208:			0000: 000423c5 04000042 017e423e 007e4200 007e4200 007e4200
-t0			write SP_SP_CTRL_REG (22c0)
+			write SP_SP_CTRL_REG (22c0)
 				SP_SP_CTRL_REG: { 0x140010 }
 109d1220:			0000: 000022c0 00140010
-t0			write SP_INSTR_CACHE_CTRL (22c1)
+			write SP_INSTR_CACHE_CTRL (22c1)
 				SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x7f }
 109d1228:			0000: 000022c1 000005ff
-t0			write SP_VS_LENGTH_REG (22e5)
+			write SP_VS_LENGTH_REG (22e5)
 				SP_VS_LENGTH_REG: 4
 109d1230:			0000: 000022e5 00000004
-t0			write SP_VS_CTRL_REG0 (22c4)
+			write SP_VS_CTRL_REG0 (22c4)
 				SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 5 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE }
 				SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 8 }
 				SP_VS_PARAM_REG: { POSREGID = r2.z | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 }
 109d1238:			0000: 000222c4 00201400 08000042 0010fc0a
-t0			write SP_VS_OUT[0].REG (22c7)
+			write SP_VS_OUT[0].REG (22c7)
 				SP_VS_OUT[0].REG: { A_REGID = r3.z | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 }
 109d1248:			0000: 000022c7 00001e0e
-t0			write SP_VS_VPC_DST[0].REG (22d8)
+			write SP_VS_VPC_DST[0].REG (22d8)
 				SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 8 | OUTLOC2 = 8 | OUTLOC3 = 8 }
 109d1250:			0000: 000022d8 08080808
-t0			write SP_VS_OBJ_OFFSET_REG (22e0)
+			write SP_VS_OBJ_OFFSET_REG (22e0)
 				SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 }
 				SP_VS_OBJ_START: 0x10cd5000
 109d1258:			0000: 000122e0 00000000 10cd5000
-t0			write SP_FS_LENGTH_REG (22ef)
+			write SP_FS_LENGTH_REG (22ef)
 				SP_FS_LENGTH_REG: 1
 109d1264:			0000: 000022ef 00000001
-t0			write SP_FS_CTRL_REG0 (22e8)
+			write SP_FS_CTRL_REG0 (22e8)
 				SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE }
 				SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 }
 109d126c:			0000: 000122e8 00340402 8010003e
-t0			write SP_FS_OBJ_OFFSET_REG (22ea)
+			write SP_FS_OBJ_OFFSET_REG (22ea)
 				SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
 				SP_FS_OBJ_START: 0x10cd2000
 109d1278:			0000: 000122ea 7e420000 10cd2000
-t0			write SP_HS_OBJ_OFFSET_REG (230d)
+			write SP_HS_OBJ_OFFSET_REG (230d)
 				SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
 109d1284:			0000: 0000230d 7e420000
-t0			write SP_DS_OBJ_OFFSET_REG (2334)
+			write SP_DS_OBJ_OFFSET_REG (2334)
 				SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
 109d128c:			0000: 00002334 7e420000
-t0			write SP_GS_OBJ_OFFSET_REG (235b)
+			write SP_GS_OBJ_OFFSET_REG (235b)
 				SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
 109d1294:			0000: 0000235b 7e420000
-t0			write GRAS_CNTL (2003)
+			write GRAS_CNTL (2003)
 				GRAS_CNTL: { 0 }
 109d129c:			0000: 00002003 00000000
-t0			write RB_RENDER_CONTROL2 (20a3)
+			write RB_RENDER_CONTROL2 (20a3)
 				RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 }
 109d12a4:			0000: 000020a3 00000000
-t0			write RB_FS_OUTPUT_REG (2100)
+			write RB_FS_OUTPUT_REG (2100)
 				RB_FS_OUTPUT_REG: { MRT = 1 }
 109d12ac:			0000: 00002100 00000001
-t0			write SP_FS_OUTPUT_REG (22f0)
+			write SP_FS_OUTPUT_REG (22f0)
 				SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r0.x }
 109d12b4:			0000: 000022f0 0000fc01
-t0			write SP_FS_MRT[0].REG (22f1)
+			write SP_FS_MRT[0].REG (22f1)
 				SP_FS_MRT[0].REG: { REGID = r0.x | MRTFORMAT = RB4_R8G8B8A8_UNORM }
 				SP_FS_MRT[0x1].REG: { REGID = r0.x | MRTFORMAT = 0 }
 				SP_FS_MRT[0x2].REG: { REGID = r0.x | MRTFORMAT = 0 }
@@ -4236,11 +4236,11 @@ t0			write SP_FS_MRT[0].REG (22f1)
 				SP_FS_MRT[0x7].REG: { REGID = r0.x | MRTFORMAT = 0 }
 109d12bc:			0000: 000722f1 0001a000 00000000 00000000 00000000 00000000 00000000 00000000
 *
-t0			write VPC_ATTR (2140)
+			write VPC_ATTR (2140)
 				VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 }
 				VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 }
 109d12e0:			0000: 00012140 42001004 00040400
-t0			write VPC_VARYING_INTERP[0].MODE (2142)
+			write VPC_VARYING_INTERP[0].MODE (2142)
 				VPC_VARYING_INTERP[0].MODE: 0x55
 				VPC_VARYING_INTERP[0x1].MODE: 0
 				VPC_VARYING_INTERP[0x2].MODE: 0
@@ -4251,7 +4251,7 @@ t0			write VPC_VARYING_INTERP[0].MODE (2142)
 				VPC_VARYING_INTERP[0x7].MODE: 0
 109d12ec:			0000: 00072142 00000055 00000000 00000000 00000000 00000000 00000000 00000000
 *
-t0			write VPC_VARYING_PS_REPL[0].MODE (214a)
+			write VPC_VARYING_PS_REPL[0].MODE (214a)
 				VPC_VARYING_PS_REPL[0].MODE: 0
 				VPC_VARYING_PS_REPL[0x1].MODE: 0
 				VPC_VARYING_PS_REPL[0x2].MODE: 0
@@ -4262,7 +4262,7 @@ t0			write VPC_VARYING_PS_REPL[0].MODE (214a)
 				VPC_VARYING_PS_REPL[0x7].MODE: 0
 109d1310:			0000: 0007214a 00000000 00000000 00000000 00000000 00000000 00000000 00000000
 *
-t3			opcode: CP_LOAD_STATE4 (30) (131 dwords)
+			opcode: CP_LOAD_STATE4 (30) (131 dwords)
 				{ DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 4 }
 				{ STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 }
 				:2:0000:0000[40700000x_10000002x] mul.f r0.x, r0.z, c0.x
@@ -4341,7 +4341,7 @@ t3			opcode: CP_LOAD_STATE4 (30) (131 dwords)
 109d14b4:			0180: 63800002 00031022 63800000 00011024 6382040e 00021025 6382040f 00001026
 109d14d4:			01a0: 63820410 00000000 03000000 00000000 00000000 00000000 00000000 00000000
 *
-t3			opcode: CP_LOAD_STATE4 (30) (35 dwords)
+			opcode: CP_LOAD_STATE4 (30) (35 dwords)
 				{ DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_SHADER | NUM_UNIT = 1 }
 				{ STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 }
 				:0:0000:0000[00000000x_00000000x] nop
@@ -4364,9 +4364,9 @@ t3			opcode: CP_LOAD_STATE4 (30) (35 dwords)
 109d1560:			0020: c7c60001 01c00004 c7c60002 01c00006 c7c60003 00002000 473090fc 00000000
 109d1580:			0040: 03000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
 *
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 109d15cc:			0000: c0002600 00000000
-t3			opcode: CP_LOAD_STATE4 (30) (51 dwords)
+			opcode: CP_LOAD_STATE4 (30) (51 dwords)
 				{ DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 12 }
 				{ STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 }
 109d15e0:				3.924428 -1.210718 0.674073 0.570369 1.829991 4.619613 -0.131666 -0.111410
@@ -4388,53 +4388,53 @@ t3			opcode: CP_LOAD_STATE4 (30) (51 dwords)
 109d1654:			0080: 00000000 00000000 3f800000 3e4ccccd 3e4ccccd 3f800000 3f800000 00000000
 109d1674:			00a0: 00000000 00000000 3f800000 00000000 00000000 00000000 3f800000 02020000
 109d1694:			00c0: 02020202 02020202 00000202
-t3			opcode: CP_LOAD_STATE4 (30) (7 dwords)
+			opcode: CP_LOAD_STATE4 (30) (7 dwords)
 				{ DST_OFF = 13 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 1 }
 				{ STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 }
 109d16ac:				0.000000 -28026765312.000000 -28026765312.000000 -28026765312.000000
 109d16ac:				0000: 00000000 d0d0d0d0 d0d0d0d0 d0d0d0d0
 109d16a0:			0000: c0053000 0060000d 00000001 00000000 d0d0d0d0 d0d0d0d0 d0d0d0d0
-t0			write VFD_FETCH[0].INSTR_0 (220a)
+			write VFD_FETCH[0].INSTR_0 (220a)
 				VFD_FETCH[0].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 24 | SWITCHNEXT }
 				VFD_FETCH[0].INSTR_1: 0x107cb000
 				VFD_FETCH[0].INSTR_2: { SIZE = 0x100000 }
 				VFD_FETCH[0].INSTR_3: { STEPRATE = 1 }
 109d16bc:			0000: 0003220a 00080c0b 107cb000 00100000 00000001
-t0			write VFD_DECODE[0].INSTR (228a)
+			write VFD_DECODE[0].INSTR (228a)
 				VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_FLOAT | REGID = r0.z | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID | SWITCHNEXT }
 109d16d0:			0000: 0000228a 6c0020df
-t0			write VFD_FETCH[0x1].INSTR_0 (220e)
+			write VFD_FETCH[0x1].INSTR_0 (220e)
 				VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 24 }
 				VFD_FETCH[0x1].INSTR_1: 0x107cb00c
 				VFD_FETCH[0x1].INSTR_2: { SIZE = 0xffff4 }
 				VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 }
 109d16d8:			0000: 0003220e 00000c0b 107cb00c 000ffff4 00000001
-t0			write VFD_DECODE[0x1].INSTR (228b)
+			write VFD_DECODE[0x1].INSTR (228b)
 				VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_FLOAT | REGID = r1.z | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID }
 109d16ec:			0000: 0000228b 2c0060df
-t0			write VFD_CONTROL_0 (2200)
+			write VFD_CONTROL_0 (2200)
 				VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 }
 				VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x }
 				VFD_CONTROL_2: 0
 				VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x }
 				VFD_CONTROL_4: 0
 109d16f4:			0000: 00042200 082a0008 fcfc0081 00000000 0000fc00 00000000
-t0			write UCHE_INVALIDATE0 (0e8a)
+			write UCHE_INVALIDATE0 (0e8a)
 				UCHE_INVALIDATE0: 0
 				UCHE_INVALIDATE1: 0x12
 109d170c:			0000: 00010e8a 00000000 00000012
-t0			write VFD_INDEX_OFFSET (2208)
+			write VFD_INDEX_OFFSET (2208)
 				VFD_INDEX_OFFSET: 0
 				UNKNOWN_2209: 0
 109d1718:			0000: 00012208 00000000 00000000
-t0			write PC_RESTART_INDEX (21c6)
+			write PC_RESTART_INDEX (21c6)
 				PC_RESTART_INDEX: 0xffffffff
 109d1724:			0000: 000021c6 ffffffff
-t0			write CP_SCRATCH[0x7].REG (057f)
+			write CP_SCRATCH[0x7].REG (057f)
 				CP_SCRATCH[0x7].REG: 0x68
 				:0,103,115,104
 109d172c:			0000: 0000057f 00000068
-t3			opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords)
+			opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords)
 				{ PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_16_BIT | PATCH_TYPE = TESS_QUADS }
 				{ NUM_INSTANCES = 1 }
 				{ NUM_INDICES = 240 }
@@ -4530,121 +4530,121 @@ t3			opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords)
  +	007e4200			HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
  +	00000003			HLSQ_UPDATE_CONTROL: 0x3
 109d1734:			0000: c0053800 00000404 00000001 000000f0 00000000 10bd1248 000001e0
-t0			write CP_SCRATCH[0x7].REG (057f)
+			write CP_SCRATCH[0x7].REG (057f)
 				CP_SCRATCH[0x7].REG: 0x69
 				:0,103,115,105
 109d1750:			0000: 0000057f 00000069
-t0			write CP_SCRATCH[0x5].REG (057d)
+			write CP_SCRATCH[0x5].REG (057d)
 				CP_SCRATCH[0x5].REG: 0x6d
 				:0,109,115,105
 109d1758:			0000: 0000057d 0000006d
-t0			write RB_DEPTH_CONTROL (2101)
+			write RB_DEPTH_CONTROL (2101)
 				RB_DEPTH_CONTROL: { Z_TEST_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_READ_ENABLE }
 109d1760:			0000: 00002101 80000016
-t0			write GRAS_ALPHA_CONTROL (2073)
+			write GRAS_ALPHA_CONTROL (2073)
 				GRAS_ALPHA_CONTROL: { 0 }
 109d1768:			0000: 00002073 00000000
-t0			write GRAS_SU_MODE_CONTROL (2078)
+			write GRAS_SU_MODE_CONTROL (2078)
 				GRAS_SU_MODE_CONTROL: { CULL_BACK | LINEHALFWIDTH = 0.500000 | RENDERING_PASS }
 109d1770:			0000: 00002078 00100012
-t0			write GRAS_SU_POINT_MINMAX (2070)
+			write GRAS_SU_POINT_MINMAX (2070)
 				GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 1.000000 }
 				GRAS_SU_POINT_SIZE: 1.000000
 109d1778:			0000: 00012070 00100010 00000010
-t0			write GRAS_SU_POLY_OFFSET_SCALE (2074)
+			write GRAS_SU_POLY_OFFSET_SCALE (2074)
 				GRAS_SU_POLY_OFFSET_SCALE: 0.000000
 				GRAS_SU_POLY_OFFSET_OFFSET: 0.000000
 				GRAS_SU_POLY_OFFSET_CLAMP: 0.000000
 109d1784:			0000: 00022074 00000000 00000000 00000000
-t0			write GRAS_CL_CLIP_CNTL (2000)
+			write GRAS_CL_CLIP_CNTL (2000)
 				GRAS_CL_CLIP_CNTL: { 0x80000 }
 109d1794:			0000: 00002000 00080000
-t0			write PC_PRIM_VTX_CNTL (21c4)
+			write PC_PRIM_VTX_CNTL (21c4)
 				PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST }
 				PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES }
 109d179c:			0000: 000121c4 02000001 00000012
-t0			write GRAS_SC_WINDOW_SCISSOR_BR (209c)
+			write GRAS_SC_WINDOW_SCISSOR_BR (209c)
 				GRAS_SC_WINDOW_SCISSOR_BR: { X = 299 | Y = 299 }
 				GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
 109d17a8:			0000: 0001209c 012b012b 00000000
-t0			write RB_VPORT_Z_CLAMP[0].MIN (2120)
+			write RB_VPORT_Z_CLAMP[0].MIN (2120)
 				RB_VPORT_Z_CLAMP[0].MIN: 0
 				RB_VPORT_Z_CLAMP[0].MAX: 0xffffff
 109d17b4:			0000: 00012120 00000000 00ffffff
-t0			write HLSQ_UPDATE_CONTROL (23db)
+			write HLSQ_UPDATE_CONTROL (23db)
 				HLSQ_UPDATE_CONTROL: 0x3
 109d17c0:			0000: 000023db 00000003
-t0			write HLSQ_CONTROL_0_REG (23c0)
+			write HLSQ_CONTROL_0_REG (23c0)
 				HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | SPSHADERRESTART | CONSTMODE = 1 | SPCONSTFULLUPDATE }
 				HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x }
 				HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x }
 				HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x }
 				HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 }
 109d17c8:			0000: 000423c0 28000250 fcfc0100 fff3f3f0 fcfcfc00 00fcfcfc
-t0			write HLSQ_VS_CONTROL_REG (23c5)
+			write HLSQ_VS_CONTROL_REG (23c5)
 				HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 4 }
 				HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 }
 				HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
 				HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
 				HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
 109d17e0:			0000: 000423c5 04000042 017e423e 007e4200 007e4200 007e4200
-t0			write SP_SP_CTRL_REG (22c0)
+			write SP_SP_CTRL_REG (22c0)
 				SP_SP_CTRL_REG: { 0x140010 }
 109d17f8:			0000: 000022c0 00140010
-t0			write SP_INSTR_CACHE_CTRL (22c1)
+			write SP_INSTR_CACHE_CTRL (22c1)
 				SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x7f }
 109d1800:			0000: 000022c1 000005ff
-t0			write SP_VS_LENGTH_REG (22e5)
+			write SP_VS_LENGTH_REG (22e5)
 				SP_VS_LENGTH_REG: 4
 109d1808:			0000: 000022e5 00000004
-t0			write SP_VS_CTRL_REG0 (22c4)
+			write SP_VS_CTRL_REG0 (22c4)
 				SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 5 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE }
 				SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 8 }
 				SP_VS_PARAM_REG: { POSREGID = r2.z | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 }
 109d1810:			0000: 000222c4 00201400 08000042 0010fc0a
-t0			write SP_VS_OUT[0].REG (22c7)
+			write SP_VS_OUT[0].REG (22c7)
 				SP_VS_OUT[0].REG: { A_REGID = r3.z | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 }
 109d1820:			0000: 000022c7 00001e0e
-t0			write SP_VS_VPC_DST[0].REG (22d8)
+			write SP_VS_VPC_DST[0].REG (22d8)
 				SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 8 | OUTLOC2 = 8 | OUTLOC3 = 8 }
 109d1828:			0000: 000022d8 08080808
-t0			write SP_VS_OBJ_OFFSET_REG (22e0)
+			write SP_VS_OBJ_OFFSET_REG (22e0)
 				SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 }
 				SP_VS_OBJ_START: 0x10cd5000
 109d1830:			0000: 000122e0 00000000 10cd5000
-t0			write SP_FS_LENGTH_REG (22ef)
+			write SP_FS_LENGTH_REG (22ef)
 				SP_FS_LENGTH_REG: 1
 109d183c:			0000: 000022ef 00000001
-t0			write SP_FS_CTRL_REG0 (22e8)
+			write SP_FS_CTRL_REG0 (22e8)
 				SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 2 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE }
 				SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 }
 109d1844:			0000: 000122e8 00340802 8010003e
-t0			write SP_FS_OBJ_OFFSET_REG (22ea)
+			write SP_FS_OBJ_OFFSET_REG (22ea)
 				SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
 				SP_FS_OBJ_START: 0x108cb000
 109d1850:			0000: 000122ea 7e420000 108cb000
-t0			write SP_HS_OBJ_OFFSET_REG (230d)
+			write SP_HS_OBJ_OFFSET_REG (230d)
 				SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
 109d185c:			0000: 0000230d 7e420000
-t0			write SP_DS_OBJ_OFFSET_REG (2334)
+			write SP_DS_OBJ_OFFSET_REG (2334)
 				SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
 109d1864:			0000: 00002334 7e420000
-t0			write SP_GS_OBJ_OFFSET_REG (235b)
+			write SP_GS_OBJ_OFFSET_REG (235b)
 				SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
 109d186c:			0000: 0000235b 7e420000
-t0			write GRAS_CNTL (2003)
+			write GRAS_CNTL (2003)
 				GRAS_CNTL: { IJ_PERSP }
 109d1874:			0000: 00002003 00000001
-t0			write RB_RENDER_CONTROL2 (20a3)
+			write RB_RENDER_CONTROL2 (20a3)
 				RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 | IJ_PERSP_PIXEL }
 109d187c:			0000: 000020a3 00001000
-t0			write RB_FS_OUTPUT_REG (2100)
+			write RB_FS_OUTPUT_REG (2100)
 				RB_FS_OUTPUT_REG: { MRT = 1 }
 109d1884:			0000: 00002100 00000001
-t0			write SP_FS_OUTPUT_REG (22f0)
+			write SP_FS_OUTPUT_REG (22f0)
 				SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r0.x }
 109d188c:			0000: 000022f0 0000fc01
-t0			write SP_FS_MRT[0].REG (22f1)
+			write SP_FS_MRT[0].REG (22f1)
 				SP_FS_MRT[0].REG: { REGID = r0.z | MRTFORMAT = RB4_R8G8B8A8_UNORM }
 				SP_FS_MRT[0x1].REG: { REGID = r0.z | MRTFORMAT = 0 }
 				SP_FS_MRT[0x2].REG: { REGID = r0.z | MRTFORMAT = 0 }
@@ -4655,11 +4655,11 @@ t0			write SP_FS_MRT[0].REG (22f1)
 				SP_FS_MRT[0x7].REG: { REGID = r0.z | MRTFORMAT = 0 }
 109d1894:			0000: 000722f1 0001a002 00000002 00000002 00000002 00000002 00000002 00000002
 109d18b4:			0020: 00000002
-t0			write VPC_ATTR (2140)
+			write VPC_ATTR (2140)
 				VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 }
 				VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 }
 109d18b8:			0000: 00012140 42001004 00040400
-t0			write VPC_VARYING_INTERP[0].MODE (2142)
+			write VPC_VARYING_INTERP[0].MODE (2142)
 				VPC_VARYING_INTERP[0].MODE: 0
 				VPC_VARYING_INTERP[0x1].MODE: 0
 				VPC_VARYING_INTERP[0x2].MODE: 0
@@ -4670,7 +4670,7 @@ t0			write VPC_VARYING_INTERP[0].MODE (2142)
 				VPC_VARYING_INTERP[0x7].MODE: 0
 109d18c4:			0000: 00072142 00000000 00000000 00000000 00000000 00000000 00000000 00000000
 *
-t0			write VPC_VARYING_PS_REPL[0].MODE (214a)
+			write VPC_VARYING_PS_REPL[0].MODE (214a)
 				VPC_VARYING_PS_REPL[0].MODE: 0
 				VPC_VARYING_PS_REPL[0x1].MODE: 0
 				VPC_VARYING_PS_REPL[0x2].MODE: 0
@@ -4681,7 +4681,7 @@ t0			write VPC_VARYING_PS_REPL[0].MODE (214a)
 				VPC_VARYING_PS_REPL[0x7].MODE: 0
 109d18e8:			0000: 0007214a 00000000 00000000 00000000 00000000 00000000 00000000 00000000
 *
-t3			opcode: CP_LOAD_STATE4 (30) (131 dwords)
+			opcode: CP_LOAD_STATE4 (30) (131 dwords)
 				{ DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 4 }
 				{ STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 }
 				:2:0000:0000[40700000x_10000002x] mul.f r0.x, r0.z, c0.x
@@ -4760,7 +4760,7 @@ t3			opcode: CP_LOAD_STATE4 (30) (131 dwords)
 109d1a8c:			0180: 63800002 00031022 63800000 00011024 6382040e 00021025 6382040f 00001026
 109d1aac:			01a0: 63820410 00000000 03000000 00000000 00000000 00000000 00000000 00000000
 *
-t3			opcode: CP_LOAD_STATE4 (30) (35 dwords)
+			opcode: CP_LOAD_STATE4 (30) (35 dwords)
 				{ DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_SHADER | NUM_UNIT = 1 }
 				{ STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 }
 				:2:0000:0000[47300002x_00002000x] bary.f r0.z, 0, r0.x
@@ -4780,9 +4780,9 @@ t3			opcode: CP_LOAD_STATE4 (30) (35 dwords)
 109d1b18:			0000: c0213000 00700000 00000000 00002000 47300002 00002001 47300003 00002002
 109d1b38:			0020: 47300004 00002003 47308005 00000000 03000000 00000000 00000000 00000000
 *
-t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 109d1ba4:			0000: c0002600 00000000
-t3			opcode: CP_LOAD_STATE4 (30) (51 dwords)
+			opcode: CP_LOAD_STATE4 (30) (51 dwords)
 				{ DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 12 }
 				{ STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 }
 109d1bb8:				3.924428 -1.210718 0.674073 0.570369 1.829991 4.619613 -0.131666 -0.111410
@@ -4804,18 +4804,18 @@ t3			opcode: CP_LOAD_STATE4 (30) (51 dwords)
 109d1c2c:			0080: 00000000 00000000 3f800000 3e4ccccd 3e4ccccd 3f800000 3f800000 00000000
 109d1c4c:			00a0: 00000000 00000000 3f800000 00000000 00000000 00000000 3f800000 02020000
 109d1c6c:			00c0: 02020202 02020202 00000202
-t0			write VFD_INDEX_OFFSET (2208)
+			write VFD_INDEX_OFFSET (2208)
 				VFD_INDEX_OFFSET: 0
 				UNKNOWN_2209: 0
 109d1c78:			0000: 00012208 00000000 00000000
-t0			write PC_RESTART_INDEX (21c6)
+			write PC_RESTART_INDEX (21c6)
 				PC_RESTART_INDEX: 0xffffffff
 109d1c84:			0000: 000021c6 ffffffff
-t0			write CP_SCRATCH[0x7].REG (057f)
+			write CP_SCRATCH[0x7].REG (057f)
 				CP_SCRATCH[0x7].REG: 0x6e
 				:0,109,115,110
 109d1c8c:			0000: 0000057f 0000006e
-t3			opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords)
+			opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords)
 				{ PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_16_BIT | PATCH_TYPE = TESS_QUADS }
 				{ NUM_INSTANCES = 1 }
 				{ NUM_INDICES = 60 }
@@ -4905,32 +4905,32 @@ t3			opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords)
  +	007e4200			HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
  +	00000003			HLSQ_UPDATE_CONTROL: 0x3
 109d1c94:			0000: c0053800 00000404 00000001 0000003c 00000000 10bd1428 00000078
-t0			write CP_SCRATCH[0x7].REG (057f)
+			write CP_SCRATCH[0x7].REG (057f)
 				CP_SCRATCH[0x7].REG: 0x6f
 				:0,109,115,111
 109d1cb0:			0000: 0000057f 0000006f
 108ce2d0:		0000: c0013f00 109ce000 00000f2e
-t2		nop
-t0		write RB_DEPTH_CONTROL (2101)
+		nop
+		write RB_DEPTH_CONTROL (2101)
 			RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER }
 108ce2e8:		0000: 00002101 00000000
-t0		write RB_STENCIL_CONTROL (2106)
+		write RB_STENCIL_CONTROL (2106)
 			RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP }
 			RB_STENCIL_CONTROL2: { 0 }
 108ce2f0:		0000: 00012106 00000000 00000000
-t0		write RB_STENCILREFMASK (210b)
+		write RB_STENCILREFMASK (210b)
 			RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0xff | 0xff000000 }
 			RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0xff | 0xff000000 }
 108ce2fc:		0000: 0001210b ffff0000 ffff0000
-t0		write GRAS_SU_MODE_CONTROL (2078)
+		write GRAS_SU_MODE_CONTROL (2078)
 			GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 }
 108ce308:		0000: 00002078 00000000
-t3		opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
+		opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
 108ce310:		0000: c0002600 00000000
-t0		write GRAS_CL_CLIP_CNTL (2000)
+		write GRAS_CL_CLIP_CNTL (2000)
 			GRAS_CL_CLIP_CNTL: { 0x80000 }
 108ce318:		0000: 00002000 00080000
-t0		write GRAS_CL_VPORT_XOFFSET_0 (2008)
+		write GRAS_CL_VPORT_XOFFSET_0 (2008)
 			GRAS_CL_VPORT_XOFFSET_0: 150.000000
 			GRAS_CL_VPORT_XSCALE_0: 150.000000
 			GRAS_CL_VPORT_YOFFSET_0: 150.000000
@@ -4938,94 +4938,94 @@ t0		write GRAS_CL_VPORT_XOFFSET_0 (2008)
 			GRAS_CL_VPORT_ZOFFSET_0: 0.000000
 			GRAS_CL_VPORT_ZSCALE_0: 1.000000
 108ce320:		0000: 00052008 43160000 43160000 43160000 c3160000 00000000 3f800000
-t0		write RB_RENDER_CONTROL (20a1)
+		write RB_RENDER_CONTROL (20a1)
 			RB_RENDER_CONTROL: { DISABLE_COLOR_PIPE | 0xa }
 108ce33c:		0000: 000020a1 0000002a
-t0		write GRAS_SC_CONTROL (207b)
+		write GRAS_SC_CONTROL (207b)
 			GRAS_SC_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MSAA_SAMPLES = 0 | MSAA_DISABLE | RASTER_MODE = 0x1 }
 108ce344:		0000: 0000207b 00001808
-t0		write PC_PRIM_VTX_CNTL (21c4)
+		write PC_PRIM_VTX_CNTL (21c4)
 			PC_PRIM_VTX_CNTL: { VAROUT = 0 | PROVOKING_VTX_LAST }
 108ce34c:		0000: 000021c4 02000000
-t0		write GRAS_ALPHA_CONTROL (2073)
+		write GRAS_ALPHA_CONTROL (2073)
 			GRAS_ALPHA_CONTROL: { 0x2 }
 108ce354:		0000: 00002073 00000002
-t0		write GRAS_SC_WINDOW_SCISSOR_BR (209c)
+		write GRAS_SC_WINDOW_SCISSOR_BR (209c)
 			GRAS_SC_WINDOW_SCISSOR_BR: { X = 299 | Y = 299 }
 			GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
 108ce35c:		0000: 0001209c 012b012b 00000000
-t0		write VFD_INDEX_OFFSET (2208)
+		write VFD_INDEX_OFFSET (2208)
 			VFD_INDEX_OFFSET: 0
 			UNKNOWN_2209: 0
 108ce368:		0000: 00012208 00000000 00000000
-t0		write HLSQ_UPDATE_CONTROL (23db)
+		write HLSQ_UPDATE_CONTROL (23db)
 			HLSQ_UPDATE_CONTROL: 0x3
 108ce374:		0000: 000023db 00000003
-t0		write HLSQ_CONTROL_0_REG (23c0)
+		write HLSQ_CONTROL_0_REG (23c0)
 			HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | SPSHADERRESTART | CONSTMODE = 1 | SPCONSTFULLUPDATE }
 			HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x }
 			HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x }
 			HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r63.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x }
 			HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 }
 108ce37c:		0000: 000423c0 28000250 fcfc0100 fff3f3f0 fcfcfcfc 00fcfcfc
-t0		write HLSQ_VS_CONTROL_REG (23c5)
+		write HLSQ_VS_CONTROL_REG (23c5)
 			HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 1 }
 			HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 }
 			HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
 			HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
 			HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
 108ce394:		0000: 000423c5 01000042 017e423e 007e4200 007e4200 007e4200
-t0		write SP_SP_CTRL_REG (22c0)
+		write SP_SP_CTRL_REG (22c0)
 			SP_SP_CTRL_REG: { 0x140010 }
 108ce3ac:		0000: 000022c0 00140010
-t0		write SP_INSTR_CACHE_CTRL (22c1)
+		write SP_INSTR_CACHE_CTRL (22c1)
 			SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x7f }
 108ce3b4:		0000: 000022c1 000005ff
-t0		write SP_VS_LENGTH_REG (22e5)
+		write SP_VS_LENGTH_REG (22e5)
 			SP_VS_LENGTH_REG: 1
 108ce3bc:		0000: 000022e5 00000001
-t0		write SP_VS_CTRL_REG0 (22c4)
+		write SP_VS_CTRL_REG0 (22c4)
 			SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE }
 			SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 4 }
 			SP_VS_PARAM_REG: { POSREGID = r0.x | PSIZEREGID = r63.x | TOTALVSOUTVAR = 0 }
 108ce3c4:		0000: 000222c4 00200400 04000042 0000fc00
-t0		write SP_VS_OBJ_OFFSET_REG (22e0)
+		write SP_VS_OBJ_OFFSET_REG (22e0)
 			SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 }
 			SP_VS_OBJ_START: 0x1073c000
 108ce3d4:		0000: 000122e0 00000000 1073c000
-t0		write SP_FS_LENGTH_REG (22ef)
+		write SP_FS_LENGTH_REG (22ef)
 			SP_FS_LENGTH_REG: 1
 108ce3e0:		0000: 000022ef 00000001
-t0		write SP_FS_CTRL_REG0 (22e8)
+		write SP_FS_CTRL_REG0 (22e8)
 			SP_FS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE }
 			SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | 0x80000000 }
 108ce3e8:		0000: 000122e8 00340400 8000003e
-t0		write SP_FS_OBJ_OFFSET_REG (22ea)
+		write SP_FS_OBJ_OFFSET_REG (22ea)
 			SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
 			SP_FS_OBJ_START: 0x1073b000
 108ce3f4:		0000: 000122ea 7e420000 1073b000
-t0		write SP_HS_OBJ_OFFSET_REG (230d)
+		write SP_HS_OBJ_OFFSET_REG (230d)
 			SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
 108ce400:		0000: 0000230d 7e420000
-t0		write SP_DS_OBJ_OFFSET_REG (2334)
+		write SP_DS_OBJ_OFFSET_REG (2334)
 			SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
 108ce408:		0000: 00002334 7e420000
-t0		write SP_GS_OBJ_OFFSET_REG (235b)
+		write SP_GS_OBJ_OFFSET_REG (235b)
 			SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
 108ce410:		0000: 0000235b 7e420000
-t0		write GRAS_CNTL (2003)
+		write GRAS_CNTL (2003)
 			GRAS_CNTL: { 0 }
 108ce418:		0000: 00002003 00000000
-t0		write RB_RENDER_CONTROL2 (20a3)
+		write RB_RENDER_CONTROL2 (20a3)
 			RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 }
 108ce420:		0000: 000020a3 00000000
-t0		write RB_FS_OUTPUT_REG (2100)
+		write RB_FS_OUTPUT_REG (2100)
 			RB_FS_OUTPUT_REG: { MRT = 0 }
 108ce428:		0000: 00002100 00000000
-t0		write SP_FS_OUTPUT_REG (22f0)
+		write SP_FS_OUTPUT_REG (22f0)
 			SP_FS_OUTPUT_REG: { MRT = 0 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r0.x }
 108ce430:		0000: 000022f0 0000fc00
-t0		write SP_FS_MRT[0].REG (22f1)
+		write SP_FS_MRT[0].REG (22f1)
 			SP_FS_MRT[0].REG: { REGID = r0.x | MRTFORMAT = 0 }
 			SP_FS_MRT[0x1].REG: { REGID = r0.x | MRTFORMAT = 0 }
 			SP_FS_MRT[0x2].REG: { REGID = r0.x | MRTFORMAT = 0 }
@@ -5036,11 +5036,11 @@ t0		write SP_FS_MRT[0].REG (22f1)
 			SP_FS_MRT[0x7].REG: { REGID = r0.x | MRTFORMAT = 0 }
 108ce438:		0000: 000722f1 00000000 00000000 00000000 00000000 00000000 00000000 00000000
 *
-t0		write VPC_ATTR (2140)
+		write VPC_ATTR (2140)
 			VPC_ATTR: { TOTALATTR = 0 | THRDASSIGN = 1 | 0x40000000 }
 			VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 0 | NUMNONPOSVSVAR = 0 }
 108ce45c:		0000: 00012140 40001000 00000000
-t0		write VPC_VARYING_INTERP[0].MODE (2142)
+		write VPC_VARYING_INTERP[0].MODE (2142)
 			VPC_VARYING_INTERP[0].MODE: 0
 			VPC_VARYING_INTERP[0x1].MODE: 0
 			VPC_VARYING_INTERP[0x2].MODE: 0
@@ -5051,7 +5051,7 @@ t0		write VPC_VARYING_INTERP[0].MODE (2142)
 			VPC_VARYING_INTERP[0x7].MODE: 0
 108ce468:		0000: 00072142 00000000 00000000 00000000 00000000 00000000 00000000 00000000
 *
-t0		write VPC_VARYING_PS_REPL[0].MODE (214a)
+		write VPC_VARYING_PS_REPL[0].MODE (214a)
 			VPC_VARYING_PS_REPL[0].MODE: 0
 			VPC_VARYING_PS_REPL[0x1].MODE: 0
 			VPC_VARYING_PS_REPL[0x2].MODE: 0
@@ -5062,7 +5062,7 @@ t0		write VPC_VARYING_PS_REPL[0].MODE (214a)
 			VPC_VARYING_PS_REPL[0x7].MODE: 0
 108ce48c:		0000: 0007214a 00000000 00000000 00000000 00000000 00000000 00000000 00000000
 *
-t3		opcode: CP_LOAD_STATE4 (30) (35 dwords)
+		opcode: CP_LOAD_STATE4 (30) (35 dwords)
 			{ DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 1 }
 			{ STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 }
 			:0:0000:0000[03000000x_00000000x] end
@@ -5077,7 +5077,7 @@ t3		opcode: CP_LOAD_STATE4 (30) (35 dwords)
 			- shaderdb: 0 sstall, 0 (ss), 0 (sy)
 108ce4b0:		0000: c0213000 00600000 00000000 00000000 03000000 00000000 00000000 00000000
 *
-t3		opcode: CP_LOAD_STATE4 (30) (35 dwords)
+		opcode: CP_LOAD_STATE4 (30) (35 dwords)
 			{ DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_SHADER | NUM_UNIT = 1 }
 			{ STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 }
 			:1:0000:0000[20244000x_00000000x] mov.f32f32 r0.x, c0.x
@@ -5097,37 +5097,37 @@ t3		opcode: CP_LOAD_STATE4 (30) (35 dwords)
 108ce53c:		0000: c0213000 00700000 00000000 00000000 20244000 00000001 20244001 00000002
 108ce55c:		0020: 20244002 00000003 20244003 00000000 03000000 00000000 00000000 00000000
 *
-t0		write VFD_FETCH[0].INSTR_0 (220a)
+		write VFD_FETCH[0].INSTR_0 (220a)
 			VFD_FETCH[0].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 12 }
 			VFD_FETCH[0].INSTR_1: 0x1074a000
 			VFD_FETCH[0].INSTR_2: { SIZE = 0x1000 }
 			VFD_FETCH[0].INSTR_3: { STEPRATE = 1 }
 108ce5c8:		0000: 0003220a 0000060b 1074a000 00001000 00000001
-t0		write VFD_DECODE[0].INSTR (228a)
+		write VFD_DECODE[0].INSTR (228a)
 			VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID }
 108ce5dc:		0000: 0000228a 2c0000df
-t0		write VFD_CONTROL_0 (2200)
+		write VFD_CONTROL_0 (2200)
 			VFD_CONTROL_0: { TOTALATTRTOVS = 4 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 1 | STRMFETCHINSTRCNT = 1 | 0xa0000 }
 			VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x }
 			VFD_CONTROL_2: 0
 			VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x }
 			VFD_CONTROL_4: 0
 108ce5e4:		0000: 00042200 041a0004 fcfc0081 00000000 0000fc00 00000000
-t0		write UCHE_INVALIDATE0 (0e8a)
+		write UCHE_INVALIDATE0 (0e8a)
 			UCHE_INVALIDATE0: 0
 			UCHE_INVALIDATE1: 0x12
 108ce5fc:		0000: 00010e8a 00000000 00000012
-t0		write RB_COPY_CONTROL (20fc)
+		write RB_COPY_CONTROL (20fc)
 			RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_ONE | MODE = RB_COPY_RESOLVE | FASTCLEAR = 0 | GMEM_BASE = 0x64000 }
 			RB_COPY_DEST_BASE: { BASE = 0x10edc000 }
 			RB_COPY_DEST_PITCH: { PITCH = 1280 }
 			RB_COPY_DEST_INFO: { FORMAT = RB4_R8G8B8A8_UNORM | SWAP = WZYX | DITHER_MODE = DITHER_DISABLE | COMPONENT_ENABLE = 0xf | ENDIAN = ENDIAN_NONE | TILE = TILE4_LINEAR }
 108ce608:		0000: 000320fc 00064010 10edc000 00000028 0003c068
-t0		write CP_SCRATCH[0x7].REG (057f)
+		write CP_SCRATCH[0x7].REG (057f)
 			CP_SCRATCH[0x7].REG: 0x75
 			:0,109,115,117
 108ce61c:		0000: 0000057f 00000075
-t3		opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords)
+		opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords)
 			{ PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_8_BIT | PATCH_TYPE = TESS_QUADS }
 			{ NUM_INSTANCES = 1 }
 			{ NUM_INDICES = 2 }
@@ -5229,21 +5229,21 @@ t3		opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords)
  +	007e4200		HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
  +	00000003		HLSQ_UPDATE_CONTROL: 0x3
 108ce624:		0000: c0023800 00000088 00000001 00000002
-t0		write CP_SCRATCH[0x7].REG (057f)
+		write CP_SCRATCH[0x7].REG (057f)
 			CP_SCRATCH[0x7].REG: 0x76
 			:0,109,115,118
 108ce634:		0000: 0000057f 00000076
-t0		write RB_COPY_CONTROL (20fc)
+		write RB_COPY_CONTROL (20fc)
 			RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_ONE | MODE = RB_COPY_RESOLVE | FASTCLEAR = 0 | GMEM_BASE = 0 }
 			RB_COPY_DEST_BASE: { BASE = 0x10f3c000 }
 			RB_COPY_DEST_PITCH: { PITCH = 1280 }
 			RB_COPY_DEST_INFO: { FORMAT = RB4_R8G8B8A8_UNORM | SWAP = WXYZ | DITHER_MODE = DITHER_DISABLE | COMPONENT_ENABLE = 0xf | ENDIAN = ENDIAN_NONE | TILE = TILE4_LINEAR }
 108ce63c:		0000: 000320fc 00000010 10f3c000 00000028 0003c168
-t0		write CP_SCRATCH[0x7].REG (057f)
+		write CP_SCRATCH[0x7].REG (057f)
 			CP_SCRATCH[0x7].REG: 0x77
 			:0,109,115,119
 108ce650:		0000: 0000057f 00000077
-t3		opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords)
+		opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords)
 			{ PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_8_BIT | PATCH_TYPE = TESS_QUADS }
 			{ NUM_INSTANCES = 1 }
 			{ NUM_INDICES = 2 }
@@ -5255,11 +5255,11 @@ t3		opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords)
  +	00000028		RB_COPY_DEST_PITCH: { PITCH = 1280 }
 !+	0003c168		RB_COPY_DEST_INFO: { FORMAT = RB4_R8G8B8A8_UNORM | SWAP = WXYZ | DITHER_MODE = DITHER_DISABLE | COMPONENT_ENABLE = 0xf | ENDIAN = ENDIAN_NONE | TILE = TILE4_LINEAR }
 108ce658:		0000: c0023800 00000088 00000001 00000002
-t0		write CP_SCRATCH[0x7].REG (057f)
+		write CP_SCRATCH[0x7].REG (057f)
 			CP_SCRATCH[0x7].REG: 0x78
 			:0,109,115,120
 108ce668:		0000: 0000057f 00000078
-t0		write GRAS_SC_CONTROL (207b)
+		write GRAS_SC_CONTROL (207b)
 			GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = 0 | MSAA_DISABLE | RASTER_MODE = 0 }
 108ce670:		0000: 0000207b 00000800
 ############################################################
diff --git a/src/freedreno/decode/cffdec.c b/src/freedreno/decode/cffdec.c
index 6b5b4eecc53..e15ece788d6 100644
--- a/src/freedreno/decode/cffdec.c
+++ b/src/freedreno/decode/cffdec.c
@@ -2776,7 +2776,6 @@ dump_commands(uint32_t *dwords, uint32_t sizedwords, int level)
       //			goto skip;
 
       if (pkt_is_type0(dwords[0])) {
-         printl(3, "t0");
          count = type0_pkt_size(dwords[0]) + 1;
          val = type0_pkt_offset(dwords[0]);
          assert(val < regcnt());
@@ -2787,7 +2786,6 @@ dump_commands(uint32_t *dwords, uint32_t sizedwords, int level)
             dump_hex(dwords, count, level + 1);
       } else if (pkt_is_type4(dwords[0])) {
          /* basically the same(ish) as type0 prior to a5xx */
-         printl(3, "t4");
          count = type4_pkt_size(dwords[0]) + 1;
          val = type4_pkt_offset(dwords[0]);
          assert(val < regcnt());
@@ -2798,7 +2796,6 @@ dump_commands(uint32_t *dwords, uint32_t sizedwords, int level)
             dump_hex(dwords, count, level + 1);
 #if 0
       } else if (pkt_is_type1(dwords[0])) {
-         printl(3, "t1");
          count = 3;
          val = dwords[0] & 0xfff;
          printl(3, "%swrite %s\n", levels[level+1], regname(val, 1));
@@ -2815,7 +2812,6 @@ dump_commands(uint32_t *dwords, uint32_t sizedwords, int level)
          const struct type3_op *op = get_type3_op(val);
          if (op->options.load_all_groups)
             load_all_groups(level + 1);
-         printl(3, "t3");
          const char *name = pktname(val);
          if (!quiet(2)) {
             printf("\t%sopcode: %s%s%s (%02x) (%d dwords)%s\n", levels[level],
@@ -2833,7 +2829,6 @@ dump_commands(uint32_t *dwords, uint32_t sizedwords, int level)
          const struct type3_op *op = get_type3_op(val);
          if (op->options.load_all_groups)
             load_all_groups(level + 1);
-         printl(3, "t7");
          const char *name = pktname(val);
          if (!quiet(2)) {
             printf("\t%sopcode: %s%s%s (%02x) (%d dwords)\n", levels[level],
@@ -2853,7 +2848,6 @@ dump_commands(uint32_t *dwords, uint32_t sizedwords, int level)
          if (!quiet(2))
             dump_hex(dwords, count, level + 1);
       } else if (pkt_is_type2(dwords[0])) {
-         printl(3, "t2");
          printl(3, "%snop\n", levels[level + 1]);
       } else {
          /* for 5xx+ we can do a passable job of looking for start of next valid