diff --git a/src/amd/vpelib/src/chip/vpe10/inc/vpe10_dpp.h b/src/amd/vpelib/src/chip/vpe10/inc/vpe10_dpp.h index ef9170fc043..aef8a24e8f6 100644 --- a/src/amd/vpelib/src/chip/vpe10/inc/vpe10_dpp.h +++ b/src/amd/vpelib/src/chip/vpe10/inc/vpe10_dpp.h @@ -55,7 +55,7 @@ extern "C" { SRIDFVL(VPCNVC_PRE_CSC_C23_C24, VPCNVC_CFG, id), \ SRIDFVL(VPCNVC_PRE_CSC_C31_C32, VPCNVC_CFG, id), \ SRIDFVL(VPCNVC_PRE_CSC_C33_C34, VPCNVC_CFG, id), \ - SRIDFVL(VPCNVC_COEF_FORMAT, VPCNVC_CFG, id), SRIDFVL(VPCNVC_PRE_DEGAM, VPCNVC_CFG, id), \ + SRIDFVL(VPCNVC_COEF_FORMAT, VPCNVC_CFG, id), \ SRIDFVL(VPCNVC_PRE_REALPHA, VPCNVC_CFG, id), \ SRIDFVL(VPDSCL_COEF_RAM_TAP_SELECT, VPDSCL, id), \ SRIDFVL(VPDSCL_COEF_RAM_TAP_DATA, VPDSCL, id), SRIDFVL(VPDSCL_MODE, VPDSCL, id), \ @@ -130,7 +130,8 @@ extern "C" { SRIDFVL(VPCM_GAMUT_REMAP_CONTROL, VPCM, id), \ SRIDFVL(VPCM_GAMUT_REMAP_C11_C12, VPCM, id), SRIDFVL(VPCM_GAMUT_REMAP_C13_C14, VPCM, id), \ SRIDFVL(VPCM_GAMUT_REMAP_C21_C22, VPCM, id), SRIDFVL(VPCM_GAMUT_REMAP_C23_C24, VPCM, id), \ - SRIDFVL(VPCM_GAMUT_REMAP_C31_C32, VPCM, id), SRIDFVL(VPCM_GAMUT_REMAP_C33_C34, VPCM, id) + SRIDFVL(VPCM_GAMUT_REMAP_C31_C32, VPCM, id), SRIDFVL(VPCM_GAMUT_REMAP_C33_C34, VPCM, id), \ + SRIDFVL(VPCNVC_PRE_DEGAM, VPCNVC_CFG, id), #define DPP_FIELD_LIST_VPE10_COMMON(post_fix) \ SFRB(VPCNVC_SURFACE_PIXEL_FORMAT, VPCNVC_SURFACE_PIXEL_FORMAT, post_fix), \ @@ -175,8 +176,6 @@ extern "C" { SFRB(PRE_CSC_C33, VPCNVC_PRE_CSC_C33_C34, post_fix), \ SFRB(PRE_CSC_C34, VPCNVC_PRE_CSC_C33_C34, post_fix), \ SFRB(PRE_CSC_COEF_FORMAT, VPCNVC_COEF_FORMAT, post_fix), \ - SFRB(PRE_DEGAM_MODE, VPCNVC_PRE_DEGAM, post_fix), \ - SFRB(PRE_DEGAM_SELECT, VPCNVC_PRE_DEGAM, post_fix), \ SFRB(PRE_REALPHA_EN, VPCNVC_PRE_REALPHA, post_fix), \ SFRB(PRE_REALPHA_ABLND_EN, VPCNVC_PRE_REALPHA, post_fix), \ SFRB(SCL_COEF_RAM_TAP_PAIR_IDX, VPDSCL_COEF_RAM_TAP_SELECT, post_fix), \ @@ -424,7 +423,9 @@ extern "C" { SFRB(DISPCLK_R_GATE_DISABLE, VPDPP_CONTROL, post_fix), \ SFRB(DISPCLK_G_GATE_DISABLE, VPDPP_CONTROL, post_fix), \ SFRB(VPDPP_TEST_CLK_SEL, VPDPP_CONTROL, post_fix), \ - SFRB(VPDPP_CLOCK_ENABLE, VPDPP_CONTROL, post_fix) + SFRB(VPDPP_CLOCK_ENABLE, VPDPP_CONTROL, post_fix), \ + SFRB(PRE_DEGAM_MODE, VPCNVC_PRE_DEGAM, post_fix), \ + SFRB(PRE_DEGAM_SELECT, VPCNVC_PRE_DEGAM, post_fix) #define DPP_REG_VARIABLE_LIST_VPE10_COMMON \ @@ -450,7 +451,6 @@ extern "C" { reg_id_val VPCNVC_PRE_CSC_C31_C32; \ reg_id_val VPCNVC_PRE_CSC_C33_C34; \ reg_id_val VPCNVC_COEF_FORMAT; \ - reg_id_val VPCNVC_PRE_DEGAM; \ reg_id_val VPCNVC_PRE_REALPHA; \ reg_id_val VPDSCL_COEF_RAM_TAP_SELECT; \ reg_id_val VPDSCL_COEF_RAM_TAP_DATA; \ @@ -548,9 +548,10 @@ extern "C" { reg_id_val VPCM_GAMUT_REMAP_C21_C22; \ reg_id_val VPCM_GAMUT_REMAP_C23_C24; \ reg_id_val VPCM_GAMUT_REMAP_C31_C32; \ - reg_id_val VPCM_GAMUT_REMAP_C33_C34; + reg_id_val VPCM_GAMUT_REMAP_C33_C34; \ + reg_id_val VPCNVC_PRE_DEGAM; \ -#define DPP_FIELD_VARIABLE_LIST_VPE10(type) \ +#define DPP_FIELD_VARIABLE_LIST_VPE10_COMMON(type) \ type VPCNVC_SURFACE_PIXEL_FORMAT; \ type FORMAT_EXPANSION_MODE; \ type FORMAT_CNV16; \ @@ -597,8 +598,6 @@ extern "C" { type PRE_CSC_C33; \ type PRE_CSC_C34; \ type PRE_CSC_COEF_FORMAT; \ - type PRE_DEGAM_MODE; \ - type PRE_DEGAM_SELECT; \ type PRE_REALPHA_EN; \ type PRE_REALPHA_ABLND_EN; \ type SCL_COEF_RAM_TAP_PAIR_IDX; \ @@ -834,6 +833,11 @@ extern "C" { type VPDPP_CRC_PIX_FORMAT_SEL; \ type VPDPP_CRC_MASK; +#define DPP_FIELD_VARIABLE_LIST_VPE10(type) \ + DPP_FIELD_VARIABLE_LIST_VPE10_COMMON(type) \ + type PRE_DEGAM_MODE; \ + type PRE_DEGAM_SELECT; + #define IDENTITY_RATIO(ratio) (vpe_fixpt_u3d19(ratio) == (1 << 19)) struct vpe10_dpp_registers { diff --git a/src/amd/vpelib/src/chip/vpe10/inc/vpe10_opp.h b/src/amd/vpelib/src/chip/vpe10/inc/vpe10_opp.h index 3873d33cc2a..ba8474c2190 100644 --- a/src/amd/vpelib/src/chip/vpe10/inc/vpe10_opp.h +++ b/src/amd/vpelib/src/chip/vpe10/inc/vpe10_opp.h @@ -81,7 +81,6 @@ extern "C" { SFRB(VPFMT_CLAMP_COLOR_FORMAT, VPFMT_CLAMP_CNTL, post_fix), \ SFRB(VPOPP_PIPE_CLOCK_ON, VPOPP_PIPE_CONTROL, post_fix), \ SFRB(VPOPP_PIPE_DIGITAL_BYPASS_EN, VPOPP_PIPE_CONTROL, post_fix), \ - SFRB(VPOPP_PIPE_ALPHA, VPOPP_PIPE_CONTROL, post_fix), \ SFRB(VPOPP_VPECLK_R_GATE_DIS, VPOPP_TOP_CLK_CONTROL, post_fix), \ SFRB(VPOPP_VPECLK_G_GATE_DIS, VPOPP_TOP_CLK_CONTROL, post_fix) @@ -89,7 +88,8 @@ extern "C" { OPP_FIELD_LIST_VPE10_COMMON(post_fix), \ SFRB(VPOPP_PIPE_CRC_EN, VPOPP_PIPE_CRC_CONTROL, post_fix), \ SFRB(VPOPP_PIPE_CRC_CONT_EN, VPOPP_PIPE_CRC_CONTROL, post_fix), \ - SFRB(VPOPP_PIPE_CRC_PIXEL_SELECT, VPOPP_PIPE_CRC_CONTROL, post_fix) + SFRB(VPOPP_PIPE_CRC_PIXEL_SELECT, VPOPP_PIPE_CRC_CONTROL, post_fix), \ + SFRB(VPOPP_PIPE_ALPHA, VPOPP_PIPE_CONTROL, post_fix) #define OPP_REG_VARIABLE_LIST_VPE10_COMMON \ reg_id_val VPFMT_CLAMP_COMPONENT_R; \ @@ -142,7 +142,6 @@ extern "C" { type VPFMT_CLAMP_COLOR_FORMAT; \ type VPOPP_PIPE_CLOCK_ON; \ type VPOPP_PIPE_DIGITAL_BYPASS_EN; \ - type VPOPP_PIPE_ALPHA; \ type VPOPP_VPECLK_R_GATE_DIS; \ type VPOPP_VPECLK_G_GATE_DIS; @@ -150,7 +149,8 @@ extern "C" { OPP_FIELD_VARIABLE_LIST_VPE10_COMMON(type) \ type VPOPP_PIPE_CRC_EN; \ type VPOPP_PIPE_CRC_CONT_EN; \ - type VPOPP_PIPE_CRC_PIXEL_SELECT; + type VPOPP_PIPE_CRC_PIXEL_SELECT; \ + type VPOPP_PIPE_ALPHA; struct vpe10_opp_registers { OPP_REG_VARIABLE_LIST_VPE10