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ac/gpu_info: add has_unaligned_shader_loads

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Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
This commit is contained in:
Marek Olšák
2018-05-02 19:39:08 -04:00
parent 8b9694da4b
commit 125adc92ad
4 changed files with 8 additions and 5 deletions
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src/amd/common/ac_gpu_info.c
+3
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@@ -328,6 +328,8 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
info->kernel_flushes_tc_l2_after_ib = info->chip_class != VI ||
info->drm_minor >= 2;
info->has_indirect_compute_dispatch = true;
/* SI doesn't support unaligned loads. */
info->has_unaligned_shader_loads = info->chip_class != SI;
info->num_render_backends = amdinfo->rb_pipes;
/* The value returned by the kernel driver was wrong. */
@@ -485,6 +487,7 @@ void ac_print_gpu_info(struct radeon_info *info)
printf(" has_format_bc1_through_bc7 = %u\n", info->has_format_bc1_through_bc7);
printf(" kernel_flushes_tc_l2_after_ib = %u\n", info->kernel_flushes_tc_l2_after_ib);
printf(" has_indirect_compute_dispatch = %u\n", info->has_indirect_compute_dispatch);
printf(" has_unaligned_shader_loads = %u\n", info->has_unaligned_shader_loads);
printf("Shader core info:\n");
printf(" max_shader_clock = %i\n", info->max_shader_clock);
src/amd/common/ac_gpu_info.h
+1
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@@ -106,6 +106,7 @@ struct radeon_info {
bool has_format_bc1_through_bc7;
bool kernel_flushes_tc_l2_after_ib;
bool has_indirect_compute_dispatch;
bool has_unaligned_shader_loads;
/* Shader cores. */
uint32_t r600_max_quad_pipes; /* wave size / 16 */
src/gallium/drivers/radeonsi/si_get.c
+1 -5
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@@ -226,11 +226,7 @@ static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
/* SI doesn't support unaligned loads.
* CIK needs DRM 2.50.0 on radeon. */
return sscreen->info.chip_class == SI ||
(sscreen->info.drm_major == 2 &&
sscreen->info.drm_minor < 50);
return !sscreen->info.has_unaligned_shader_loads;
case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
/* TODO: GFX9 hangs. */
src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
+3
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@@ -544,6 +544,9 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
ws->info.has_indirect_compute_dispatch = ws->info.chip_class == CIK ||
(ws->info.chip_class == SI &&
ws->info.drm_minor >= 45);
/* SI doesn't support unaligned loads. */
ws->info.has_unaligned_shader_loads = ws->info.chip_class == CIK &&
ws->info.drm_minor >= 50;
ws->check_vm = strstr(debug_get_option("R600_DEBUG", ""), "check_vm") != NULL;