From 12530fb8dfcc7eb9f812d67d98d1d19b83e88559 Mon Sep 17 00:00:00 2001 From: Rob Clark Date: Sat, 21 Jun 2025 06:34:16 -0700 Subject: [PATCH] freedreno/registers: Some reg64 conversion Signed-off-by: Rob Clark Part-of: --- src/freedreno/.gitlab-ci/reference/crash.log | 33 +++++++------------ .../.gitlab-ci/reference/crash_prefetch.log | 33 +++++++------------ .../.gitlab-ci/reference/prefetch-test.log | 33 +++++++------------ src/freedreno/registers/adreno/a6xx.xml | 33 +++++++------------ src/freedreno/vulkan/tu_query_pool.cc | 10 +++--- .../drivers/freedreno/a6xx/fd6_query.cc | 4 +-- 6 files changed, 51 insertions(+), 95 deletions(-) diff --git a/src/freedreno/.gitlab-ci/reference/crash.log b/src/freedreno/.gitlab-ci/reference/crash.log index 2df17053fdc..c8c0c576574 100644 --- a/src/freedreno/.gitlab-ci/reference/crash.log +++ b/src/freedreno/.gitlab-ci/reference/crash.log @@ -593,28 +593,17 @@ registers: 00000000 RBBM_PERFCTR_SRAM_INIT_STATUS: 0 00000000 0x511: 00000000 00000000 RBBM_ISDB_CNT: 0 - 80108000 RBBM_PRIMCTR_0_LO: 0x80108000 - 10044400 RBBM_PRIMCTR_0_HI: 0x10044400 - 48004008 RBBM_PRIMCTR_1_LO: 0x48004008 - 00010000 RBBM_PRIMCTR_1_HI: 0x10000 - 04100000 RBBM_PRIMCTR_2_LO: 0x4100000 - 401a3089 RBBM_PRIMCTR_2_HI: 0x401a3089 - 08240112 RBBM_PRIMCTR_3_LO: 0x8240112 - 01000408 RBBM_PRIMCTR_3_HI: 0x1000408 - 00005020 RBBM_PRIMCTR_4_LO: 0x5020 - 00024000 RBBM_PRIMCTR_4_HI: 0x24000 - 10001000 RBBM_PRIMCTR_5_LO: 0x10001000 - 80400000 RBBM_PRIMCTR_5_HI: 0x80400000 - 0006000a RBBM_PRIMCTR_6_LO: 0x6000a - 00040002 RBBM_PRIMCTR_6_HI: 0x40002 - 10008100 RBBM_PRIMCTR_7_LO: 0x10008100 - 24000000 RBBM_PRIMCTR_7_HI: 0x24000000 - 24420000 RBBM_PRIMCTR_8_LO: 0x24420000 - 10800000 RBBM_PRIMCTR_8_HI: 0x10800000 - 21030200 RBBM_PRIMCTR_9_LO: 0x21030200 - 0c000020 RBBM_PRIMCTR_9_HI: 0xc000020 - 80820000 RBBM_PRIMCTR_10_LO: 0x80820000 - 40000800 RBBM_PRIMCTR_10_HI: 0x40000800 + 1004440080108000 RBBM_PRIMCTR_0: 0x1004440080108000 + 1000048004008 RBBM_PRIMCTR_1: 0x1000048004008 + 401a308904100000 RBBM_PRIMCTR_2: 0x401a308904100000 + 100040808240112 RBBM_PRIMCTR_3: 0x100040808240112 + 2400000005020 RBBM_PRIMCTR_4: 0x2400000005020 + 8040000010001000 RBBM_PRIMCTR_5: 0x8040000010001000 + 400020006000a RBBM_PRIMCTR_6: 0x400020006000a + 2400000010008100 RBBM_PRIMCTR_7: 0x2400000010008100 + 1080000024420000 RBBM_PRIMCTR_8: 0x1080000024420000 + c00002021030200 RBBM_PRIMCTR_9: 0xc00002021030200 + 4000080080820000 RBBM_PRIMCTR_10: 0x4000080080820000 1000000001000 CP_RB_BASE: 0x1000000001000 0000020c CP_RB_CNTL: 0x20c 00000000 0x803: 00000000 diff --git a/src/freedreno/.gitlab-ci/reference/crash_prefetch.log b/src/freedreno/.gitlab-ci/reference/crash_prefetch.log index b75b0af4d54..23e971ff6ae 100644 --- a/src/freedreno/.gitlab-ci/reference/crash_prefetch.log +++ b/src/freedreno/.gitlab-ci/reference/crash_prefetch.log @@ -808,28 +808,17 @@ registers: 00000001 RBBM_PERFCTR_SRAM_INIT_STATUS: 0x1 00000000 0x511: 00000000 00000000 RBBM_ISDB_CNT: 0 - 00000000 RBBM_PRIMCTR_0_LO: 0 - 00000000 RBBM_PRIMCTR_0_HI: 0 - 00000000 RBBM_PRIMCTR_1_LO: 0 - 00000000 RBBM_PRIMCTR_1_HI: 0 - 00000000 RBBM_PRIMCTR_2_LO: 0 - 00000000 RBBM_PRIMCTR_2_HI: 0 - 00000000 RBBM_PRIMCTR_3_LO: 0 - 00000000 RBBM_PRIMCTR_3_HI: 0 - 00000000 RBBM_PRIMCTR_4_LO: 0 - 00000000 RBBM_PRIMCTR_4_HI: 0 - 00000000 RBBM_PRIMCTR_5_LO: 0 - 00000000 RBBM_PRIMCTR_5_HI: 0 - 00000000 RBBM_PRIMCTR_6_LO: 0 - 00000000 RBBM_PRIMCTR_6_HI: 0 - 00000000 RBBM_PRIMCTR_7_LO: 0 - 00000000 RBBM_PRIMCTR_7_HI: 0 - 00000000 RBBM_PRIMCTR_8_LO: 0 - 00000000 RBBM_PRIMCTR_8_HI: 0 - 00000000 RBBM_PRIMCTR_9_LO: 0 - 00000000 RBBM_PRIMCTR_9_HI: 0 - 00000000 RBBM_PRIMCTR_10_LO: 0 - 00000000 RBBM_PRIMCTR_10_HI: 0 + 00000000 RBBM_PRIMCTR_0: 0 + 00000000 RBBM_PRIMCTR_1: 0 + 00000000 RBBM_PRIMCTR_2: 0 + 00000000 RBBM_PRIMCTR_3: 0 + 00000000 RBBM_PRIMCTR_4: 0 + 00000000 RBBM_PRIMCTR_5: 0 + 00000000 RBBM_PRIMCTR_6: 0 + 00000000 RBBM_PRIMCTR_7: 0 + 00000000 RBBM_PRIMCTR_8: 0 + 00000000 RBBM_PRIMCTR_9: 0 + 00000000 RBBM_PRIMCTR_10: 0 1000000001000 CP_RB_BASE: 0x1000000001000 0800020c CP_RB_CNTL: 0x800020c 00000000 0x803: 00000000 diff --git a/src/freedreno/.gitlab-ci/reference/prefetch-test.log b/src/freedreno/.gitlab-ci/reference/prefetch-test.log index 2af723e8d5a..62dfff7b1c3 100644 --- a/src/freedreno/.gitlab-ci/reference/prefetch-test.log +++ b/src/freedreno/.gitlab-ci/reference/prefetch-test.log @@ -1387,28 +1387,17 @@ registers: 00000001 RBBM_PERFCTR_SRAM_INIT_STATUS: 0x1 00000000 0x511: 00000000 00000000 RBBM_ISDB_CNT: 0 - 00000000 RBBM_PRIMCTR_0_LO: 0 - 00000000 RBBM_PRIMCTR_0_HI: 0 - 00000000 RBBM_PRIMCTR_1_LO: 0 - 00000000 RBBM_PRIMCTR_1_HI: 0 - 00000000 RBBM_PRIMCTR_2_LO: 0 - 00000000 RBBM_PRIMCTR_2_HI: 0 - 00000000 RBBM_PRIMCTR_3_LO: 0 - 00000000 RBBM_PRIMCTR_3_HI: 0 - 00000000 RBBM_PRIMCTR_4_LO: 0 - 00000000 RBBM_PRIMCTR_4_HI: 0 - 00000000 RBBM_PRIMCTR_5_LO: 0 - 00000000 RBBM_PRIMCTR_5_HI: 0 - 00000000 RBBM_PRIMCTR_6_LO: 0 - 00000000 RBBM_PRIMCTR_6_HI: 0 - 00000000 RBBM_PRIMCTR_7_LO: 0 - 00000000 RBBM_PRIMCTR_7_HI: 0 - 00000000 RBBM_PRIMCTR_8_LO: 0 - 00000000 RBBM_PRIMCTR_8_HI: 0 - 00000000 RBBM_PRIMCTR_9_LO: 0 - 00000000 RBBM_PRIMCTR_9_HI: 0 - 00000000 RBBM_PRIMCTR_10_LO: 0 - 00000000 RBBM_PRIMCTR_10_HI: 0 + 00000000 RBBM_PRIMCTR_0: 0 + 00000000 RBBM_PRIMCTR_1: 0 + 00000000 RBBM_PRIMCTR_2: 0 + 00000000 RBBM_PRIMCTR_3: 0 + 00000000 RBBM_PRIMCTR_4: 0 + 00000000 RBBM_PRIMCTR_5: 0 + 00000000 RBBM_PRIMCTR_6: 0 + 00000000 RBBM_PRIMCTR_7: 0 + 00000000 RBBM_PRIMCTR_8: 0 + 00000000 RBBM_PRIMCTR_9: 0 + 00000000 RBBM_PRIMCTR_10: 0 1000000001000 CP_RB_BASE: 0x1000000001000 0800020c CP_RB_CNTL: 0x800020c 00000000 0x803: 00000000 diff --git a/src/freedreno/registers/adreno/a6xx.xml b/src/freedreno/registers/adreno/a6xx.xml index 68ca40c9bf2..e0e6e07ebfa 100644 --- a/src/freedreno/registers/adreno/a6xx.xml +++ b/src/freedreno/registers/adreno/a6xx.xml @@ -2622,28 +2622,17 @@ to upconvert to 32b float internally? vertices in, number of primnitives assembled etc. --> - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + diff --git a/src/freedreno/vulkan/tu_query_pool.cc b/src/freedreno/vulkan/tu_query_pool.cc index 95b0994cdd1..b7400240964 100644 --- a/src/freedreno/vulkan/tu_query_pool.cc +++ b/src/freedreno/vulkan/tu_query_pool.cc @@ -27,7 +27,7 @@ #define NSEC_PER_SEC 1000000000ull #define WAIT_TIMEOUT 5 -#define STAT_COUNT ((REG_A6XX_RBBM_PRIMCTR_10_LO - REG_A6XX_RBBM_PRIMCTR_0_LO) / 2 + 1) +#define STAT_COUNT ((REG_A6XX_RBBM_PRIMCTR_10 - REG_A6XX_RBBM_PRIMCTR_0) / 2 + 1) struct PACKED query_slot { uint64_t available; @@ -1130,7 +1130,7 @@ emit_begin_stat_query(struct tu_cmd_buffer *cmdbuf, tu_cs_emit_wfi(cs); tu_cs_emit_pkt7(cs, CP_REG_TO_MEM, 3); - tu_cs_emit(cs, CP_REG_TO_MEM_0_REG(REG_A6XX_RBBM_PRIMCTR_0_LO) | + tu_cs_emit(cs, CP_REG_TO_MEM_0_REG(REG_A6XX_RBBM_PRIMCTR_0) | CP_REG_TO_MEM_0_CNT(STAT_COUNT * 2) | CP_REG_TO_MEM_0_64B); tu_cs_emit_qw(cs, begin_iova); @@ -1339,7 +1339,7 @@ emit_begin_prim_generated_query(struct tu_cmd_buffer *cmdbuf, tu_cs_emit_wfi(cs); tu_cs_emit_pkt7(cs, CP_REG_TO_MEM, 3); - tu_cs_emit(cs, CP_REG_TO_MEM_0_REG(REG_A6XX_RBBM_PRIMCTR_7_LO) | + tu_cs_emit(cs, CP_REG_TO_MEM_0_REG(REG_A6XX_RBBM_PRIMCTR_7) | CP_REG_TO_MEM_0_CNT(2) | CP_REG_TO_MEM_0_64B); tu_cs_emit_qw(cs, begin_iova); @@ -1592,7 +1592,7 @@ emit_end_stat_query(struct tu_cmd_buffer *cmdbuf, tu_cs_emit_wfi(cs); tu_cs_emit_pkt7(cs, CP_REG_TO_MEM, 3); - tu_cs_emit(cs, CP_REG_TO_MEM_0_REG(REG_A6XX_RBBM_PRIMCTR_0_LO) | + tu_cs_emit(cs, CP_REG_TO_MEM_0_REG(REG_A6XX_RBBM_PRIMCTR_0) | CP_REG_TO_MEM_0_CNT(STAT_COUNT * 2) | CP_REG_TO_MEM_0_64B); tu_cs_emit_qw(cs, end_iova); @@ -1872,7 +1872,7 @@ emit_end_prim_generated_query(struct tu_cmd_buffer *cmdbuf, tu_cs_emit_wfi(cs); tu_cs_emit_pkt7(cs, CP_REG_TO_MEM, 3); - tu_cs_emit(cs, CP_REG_TO_MEM_0_REG(REG_A6XX_RBBM_PRIMCTR_7_LO) | + tu_cs_emit(cs, CP_REG_TO_MEM_0_REG(REG_A6XX_RBBM_PRIMCTR_7) | CP_REG_TO_MEM_0_CNT(2) | CP_REG_TO_MEM_0_64B); tu_cs_emit_qw(cs, end_iova); diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_query.cc b/src/gallium/drivers/freedreno/a6xx/fd6_query.cc index d015b37f59b..6732be97265 100644 --- a/src/gallium/drivers/freedreno/a6xx/fd6_query.cc +++ b/src/gallium/drivers/freedreno/a6xx/fd6_query.cc @@ -497,7 +497,7 @@ pipeline_stats_resume(struct fd_acc_query *aq, struct fd_batch *batch) struct fd_ringbuffer *ring = batch->draw; enum stats_type type = get_stats_type(aq); unsigned idx = stats_counter_index(aq); - unsigned reg = REG_A6XX_RBBM_PRIMCTR_0_LO + (2 * idx); + unsigned reg = REG_A6XX_RBBM_PRIMCTR_0 + (2 * idx); OUT_WFI5(ring); @@ -522,7 +522,7 @@ pipeline_stats_pause(struct fd_acc_query *aq, struct fd_batch *batch) struct fd_ringbuffer *ring = batch->draw; enum stats_type type = get_stats_type(aq); unsigned idx = stats_counter_index(aq); - unsigned reg = REG_A6XX_RBBM_PRIMCTR_0_LO + (2 * idx); + unsigned reg = REG_A6XX_RBBM_PRIMCTR_0 + (2 * idx); OUT_WFI5(ring);