diff --git a/src/amd/common/nir/ac_nir.c b/src/amd/common/nir/ac_nir.c
index c89513110f1..8e9db9b65e6 100644
--- a/src/amd/common/nir/ac_nir.c
+++ b/src/amd/common/nir/ac_nir.c
@@ -8,6 +8,7 @@
 #include "ac_nir.h"
 #include "ac_nir_helpers.h"
 #include "nir_builder.h"
+#include "nir_intrinsics.h"
 
 /* Set NIR options shared by ACO, LLVM, RADV, and radeonsi. */
 void ac_nir_set_options(struct radeon_info *info, bool use_llvm,
@@ -893,3 +894,16 @@ ac_nir_lower_phis_to_scalar_cb(const nir_instr *instr, const void *_)
 
    return 32 / phi->def.bit_size;
 }
+
+bool
+ac_nir_allow_offset_wrap_cb(nir_intrinsic_instr *instr, const void *data)
+{
+   switch (instr->intrinsic) {
+   case nir_intrinsic_load_shared:
+   case nir_intrinsic_store_shared:
+   case nir_intrinsic_shared_atomic:
+   case nir_intrinsic_shared_atomic_swap:
+      return true;
+   default: return false;
+   }
+}
diff --git a/src/amd/common/nir/ac_nir.h b/src/amd/common/nir/ac_nir.h
index 0ec6a0b467e..f44bfd4c137 100644
--- a/src/amd/common/nir/ac_nir.h
+++ b/src/amd/common/nir/ac_nir.h
@@ -441,6 +441,9 @@ ac_nir_store_may_be_subdword(const nir_intrinsic_instr *instr);
 uint8_t
 ac_nir_lower_phis_to_scalar_cb(const nir_instr *instr, const void *_);
 
+bool
+ac_nir_allow_offset_wrap_cb(nir_intrinsic_instr *instr, const void *data);
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index 52ae64cf6ca..90cf999a80f 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -260,8 +260,9 @@ radv_optimize_nir_algebraic(nir_shader *nir, bool opt_offsets, bool opt_mqsad)
       static const nir_opt_offsets_options offset_options = {
          .uniform_max = 0,
          .buffer_max = ~0,
-         .shared_max = ~0,
-         .shared_atomic_max = ~0,
+         .shared_max = UINT16_MAX,
+         .shared_atomic_max = UINT16_MAX,
+         .allow_offset_wrap_cb = ac_nir_allow_offset_wrap_cb,
       };
       NIR_PASS(_, nir, nir_opt_offsets, &offset_options);
    }