From 1005a2a25f5d964e7945d4a41b4bbe438f43eb6a Mon Sep 17 00:00:00 2001 From: Yogesh mohan marimuthu Date: Tue, 24 Aug 2021 12:53:06 +0530 Subject: [PATCH] radeonsi/gfx11: program inst_pref_size for compute MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit For gfx11, program INST_PREF_SIZE value in SPI registers. v2: move INST_PREF_SIZE reg programming (Marek Olšák) Signed-off-by: Yogesh mohan marimuthu Acked-by: Pierre-Eric Pelloux-Prayer Part-of: --- src/gallium/drivers/radeonsi/si_compute.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_compute.c b/src/gallium/drivers/radeonsi/si_compute.c index d0cf5d9d9a5..93e767d64f2 100644 --- a/src/gallium/drivers/radeonsi/si_compute.c +++ b/src/gallium/drivers/radeonsi/si_compute.c @@ -438,14 +438,16 @@ void si_emit_initial_compute_regs(struct si_context *sctx, struct radeon_cmdbuf } if (sctx->chip_class >= GFX10) { - radeon_set_sh_reg_seq(R_00B890_COMPUTE_USER_ACCUM_0, 5); + radeon_set_sh_reg_seq(R_00B890_COMPUTE_USER_ACCUM_0, 4); radeon_emit(0); /* R_00B890_COMPUTE_USER_ACCUM_0 */ radeon_emit(0); /* R_00B894_COMPUTE_USER_ACCUM_1 */ radeon_emit(0); /* R_00B898_COMPUTE_USER_ACCUM_2 */ radeon_emit(0); /* R_00B89C_COMPUTE_USER_ACCUM_3 */ - radeon_emit(0); /* R_00B8A0_COMPUTE_PGM_RSRC3 */ radeon_set_sh_reg(R_00B9F4_COMPUTE_DISPATCH_TUNNEL, 0); + + if (sctx->chip_class < GFX11) + radeon_set_sh_reg(R_00B8A0_COMPUTE_PGM_RSRC3, 0); } radeon_end(); } @@ -551,6 +553,11 @@ static bool si_switch_compute_shader(struct si_context *sctx, struct si_compute radeon_begin(cs); radeon_set_sh_reg(R_00B830_COMPUTE_PGM_LO, shader_va >> 8); + if (sctx->chip_class >= GFX11) { + radeon_set_sh_reg(R_00B8A0_COMPUTE_PGM_RSRC3, + S_00B8A0_INST_PREF_SIZE(si_calc_inst_pref_size(shader))); + } + if (sctx->chip_class >= GFX11 && shader->scratch_bo) { radeon_set_sh_reg_seq(R_00B840_COMPUTE_DISPATCH_SCRATCH_BASE_LO, 4); radeon_emit(sctx->compute_scratch_buffer->gpu_address >> 8);