diff --git a/src/gallium/winsys/radeon/drm/radeon_surface.c b/src/gallium/winsys/radeon/drm/radeon_surface.c index 1950ff77723..1c235b0423b 100644 --- a/src/gallium/winsys/radeon/drm/radeon_surface.c +++ b/src/gallium/winsys/radeon/drm/radeon_surface.c @@ -287,7 +287,7 @@ static int r6_surface_init_linear(struct radeon_surface_manager *surf_man, /* level0 and first mipmap need to have alignment */ offset = surf->bo_size; if (i == 0) { - offset = ALIGN(offset, surf->bo_alignment); + offset = align64(offset, surf->bo_alignment); } } return 0; @@ -315,7 +315,7 @@ static int r6_surface_init_linear_aligned(struct radeon_surface_manager *surf_ma /* level0 and first mipmap need to have alignment */ offset = surf->bo_size; if (i == 0) { - offset = ALIGN(offset, surf->bo_alignment); + offset = align64(offset, surf->bo_alignment); } } return 0; @@ -348,7 +348,7 @@ static int r6_surface_init_1d(struct radeon_surface_manager *surf_man, /* level0 and first mipmap need to have alignment */ offset = surf->bo_size; if (i == 0) { - offset = ALIGN(offset, surf->bo_alignment); + offset = align64(offset, surf->bo_alignment); } } return 0; @@ -391,7 +391,7 @@ static int r6_surface_init_2d(struct radeon_surface_manager *surf_man, /* level0 and first mipmap need to have alignment */ offset = surf->bo_size; if (i == 0) { - offset = ALIGN(offset, surf->bo_alignment); + offset = align64(offset, surf->bo_alignment); } } return 0; @@ -632,7 +632,7 @@ static int eg_surface_init_1d(struct radeon_surface_manager *surf_man, surf->bo_alignment = MAX2(surf->bo_alignment, alignment); if (offset) { - offset = ALIGN(offset, alignment); + offset = align64(offset, alignment); } } @@ -645,7 +645,7 @@ static int eg_surface_init_1d(struct radeon_surface_manager *surf_man, /* level0 and first mipmap need to have alignment */ offset = surf->bo_size; if (i == 0) { - offset = ALIGN(offset, surf->bo_alignment); + offset = align64(offset, surf->bo_alignment); } } return 0; @@ -685,7 +685,7 @@ static int eg_surface_init_2d(struct radeon_surface_manager *surf_man, surf->bo_alignment = MAX2(surf->bo_alignment, alignment); if (offset) { - offset = ALIGN(offset, alignment); + offset = align64(offset, alignment); } } @@ -699,7 +699,7 @@ static int eg_surface_init_2d(struct radeon_surface_manager *surf_man, /* level0 and first mipmap need to have alignment */ offset = surf->bo_size; if (i == 0) { - offset = ALIGN(offset, surf->bo_alignment); + offset = align64(offset, surf->bo_alignment); } } return 0; @@ -1488,7 +1488,7 @@ static void si_surf_minify(struct radeon_surface *surf, surflevel->offset = offset; surflevel->pitch_bytes = surflevel->nblk_x * bpe * surf->nsamples; - surflevel->slice_size = ALIGN((uint64_t)surflevel->pitch_bytes * surflevel->nblk_y, + surflevel->slice_size = align64((uint64_t)surflevel->pitch_bytes * surflevel->nblk_y, (uint64_t)slice_align); surf->bo_size = offset + surflevel->slice_size * surflevel->nblk_z * surf->array_size; @@ -1566,7 +1566,7 @@ static int si_surface_init_linear_aligned(struct radeon_surface_manager *surf_ma /* level0 and first mipmap need to have alignment */ offset = surf->bo_size; if (i == 0) { - offset = ALIGN(offset, surf->bo_alignment); + offset = align64(offset, surf->bo_alignment); } if (surf->flags & RADEON_SURF_HAS_TILE_MODE_INDEX) { surf->tiling_index[i] = tile_mode; @@ -1598,7 +1598,7 @@ static int si_surface_init_1d(struct radeon_surface_manager *surf_man, surf->bo_alignment = MAX2(surf->bo_alignment, alignment); if (offset) { - offset = ALIGN(offset, alignment); + offset = align64(offset, alignment); } } @@ -1609,7 +1609,7 @@ static int si_surface_init_1d(struct radeon_surface_manager *surf_man, /* level0 and first mipmap need to have alignment */ offset = surf->bo_size; if (i == 0) { - offset = ALIGN(offset, alignment); + offset = align64(offset, alignment); } if (surf->flags & RADEON_SURF_HAS_TILE_MODE_INDEX) { if (surf->level == level) { @@ -1680,7 +1680,7 @@ static int si_surface_init_2d(struct radeon_surface_manager *surf_man, surf->bo_alignment = MAX2(surf->bo_alignment, alignment); if (aligned_offset) { - aligned_offset = ALIGN(aligned_offset, alignment); + aligned_offset = align64(aligned_offset, alignment); } } @@ -1711,7 +1711,7 @@ static int si_surface_init_2d(struct radeon_surface_manager *surf_man, /* level0 and first mipmap need to have alignment */ aligned_offset = offset = surf->bo_size; if (i == 0) { - aligned_offset = ALIGN(aligned_offset, surf->bo_alignment); + aligned_offset = align64(aligned_offset, surf->bo_alignment); } if (surf->flags & RADEON_SURF_HAS_TILE_MODE_INDEX) { if (surf->level == level) { @@ -2283,7 +2283,7 @@ static int cik_surface_init_2d(struct radeon_surface_manager *surf_man, surf->bo_alignment = MAX2(surf->bo_alignment, alignment); if (aligned_offset) { - aligned_offset = ALIGN(aligned_offset, alignment); + aligned_offset = align64(aligned_offset, alignment); } } @@ -2314,7 +2314,7 @@ static int cik_surface_init_2d(struct radeon_surface_manager *surf_man, /* level0 and first mipmap need to have alignment */ aligned_offset = offset = surf->bo_size; if (i == 0) { - aligned_offset = ALIGN(aligned_offset, surf->bo_alignment); + aligned_offset = align64(aligned_offset, surf->bo_alignment); } if (surf->flags & RADEON_SURF_HAS_TILE_MODE_INDEX) { if (surf->level == level) {