From 0fd40af59f46b6b875a165345914e4b8efe3fc5c Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Tue, 31 Aug 2021 09:21:41 +0200 Subject: [PATCH] radv: allow to conditionally read HTILE value when copying VRS rates When a subpass is bound without a VRS attachment, the driver has to create one internally and the copy can be a write only operation. Signed-off-by: Samuel Pitoiset Reviewed-by: Bas Nieuwenhuizen Part-of: --- src/amd/vulkan/radv_meta_copy_vrs_htile.c | 33 ++++++++++++++++------- 1 file changed, 23 insertions(+), 10 deletions(-) diff --git a/src/amd/vulkan/radv_meta_copy_vrs_htile.c b/src/amd/vulkan/radv_meta_copy_vrs_htile.c index adf98c71355..4f5e78be8e1 100644 --- a/src/amd/vulkan/radv_meta_copy_vrs_htile.c +++ b/src/amd/vulkan/radv_meta_copy_vrs_htile.c @@ -63,9 +63,10 @@ build_copy_vrs_htile_shader(struct radv_device *device, struct radeon_surf *surf coord = nir_imul(&b, coord, nir_imm_ivec2(&b, 8, 8)); /* Load constants. */ - nir_ssa_def *constants = nir_load_push_constant(&b, 2, 32, nir_imm_int(&b, 0), .range = 8); + nir_ssa_def *constants = nir_load_push_constant(&b, 3, 32, nir_imm_int(&b, 0), .range = 12); nir_ssa_def *htile_pitch = nir_channel(&b, constants, 0); nir_ssa_def *htile_slice_size = nir_channel(&b, constants, 1); + nir_ssa_def *read_htile_value = nir_channel(&b, constants, 2); /* Get the HTILE addr from coordinates. */ nir_ssa_def *zero = nir_imm_int(&b, 0); @@ -119,17 +120,28 @@ build_copy_vrs_htile_shader(struct radv_device *device, struct radeon_surf *surf /* Load the HTILE buffer descriptor. */ nir_ssa_def *htile_buf = radv_meta_load_descriptor(&b, 0, 1); - /* Load the existing HTILE 32-bit value for this 8x8 pixels area. */ - nir_ssa_def *htile_value = nir_load_ssbo(&b, 1, 32, htile_buf, htile_addr, .align_mul = 4); + /* Load the HTILE value if requested, otherwise use the default value. */ + nir_variable *htile_value = nir_local_variable_create(b.impl, glsl_int_type(), "htile_value"); - /* Clear the 4-bit VRS rates. */ - htile_value = nir_iand(&b, htile_value, nir_imm_int(&b, 0xfffff33f)); + nir_push_if(&b, nir_ieq(&b, read_htile_value, nir_imm_int(&b, 1))); + { + /* Load the existing HTILE 32-bit value for this 8x8 pixels area. */ + nir_ssa_def *input_value = nir_load_ssbo(&b, 1, 32, htile_buf, htile_addr, .align_mul = 4); + + /* Clear the 4-bit VRS rates. */ + nir_store_var(&b, htile_value, nir_iand(&b, input_value, nir_imm_int(&b, 0xfffff33f)), 0x1); + } + nir_push_else(&b, NULL); + { + nir_store_var(&b, htile_value, nir_imm_int(&b, 0xfffff33f), 0x1); + } + nir_pop_if(&b, NULL); /* Set the VRS rates loaded from the image. */ - htile_value = nir_ior(&b, htile_value, vrs_rates); + nir_ssa_def *output_value = nir_ior(&b, nir_load_var(&b, htile_value), vrs_rates); /* Store the updated HTILE 32-bit which contains the VRS rates. */ - nir_store_ssbo(&b, htile_value, htile_buf, htile_addr, .write_mask = 0x1, + nir_store_ssbo(&b, output_value, htile_buf, htile_addr, .write_mask = 0x1, .access = ACCESS_NON_READABLE, .align_mul = 4); return b.shader; @@ -174,7 +186,7 @@ radv_device_init_meta_copy_vrs_htile_state(struct radv_device *device, &(VkPushConstantRange){ VK_SHADER_STAGE_COMPUTE_BIT, 0, - 8, + 12, }, }; @@ -284,12 +296,13 @@ radv_copy_vrs_htile(struct radv_cmd_buffer *cmd_buffer, struct radv_image *vrs_i .offset = 0, .range = htile_size}}}); - const unsigned constants[2] = { + const unsigned constants[3] = { dst_image->planes[0].surface.meta_pitch, dst_image->planes[0].surface.meta_slice_size, + true, }; radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), state->copy_vrs_htile_p_layout, - VK_SHADER_STAGE_COMPUTE_BIT, 0, 8, constants); + VK_SHADER_STAGE_COMPUTE_BIT, 0, 12, constants); uint32_t width = DIV_ROUND_UP(extent->width, 8); uint32_t height = DIV_ROUND_UP(extent->height, 8);