iris: Reduce use of RHWO optimization (Wa_1508744258)

Implement Wa_1508744258:

   Disable RHWO by setting 0x7010[14] by default except during resolve
   pass.

Disable the RCC RHWO optimization at all times except when resolving
single sampled color surfaces. MCS partial resolves are done via
software (i.e., not via a HW bit) and so are not expected to need this
workaround.

Reviewed-by: Mark Janes <markjanes@swizzler.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19360>

src/gallium/drivers/iris/iris_resolve.c

@@ -465,6 +465,18 @@ iris_resolve_color(struct iris_context *ice,
    iris_emit_end_of_pipe_sync(batch, "color resolve: pre-flush",
                               PIPE_CONTROL_RENDER_TARGET_FLUSH);
 
+   /* Wa_1508744258
+    *
+    *    Disable RHWO by setting 0x7010[14] by default except during resolve
+    *    pass.
+    *
+    * We implement global disabling of the RHWO optimization during
+    * iris_init_render_context. We toggle it around the blorp resolve call.
+    */
+   assert(resolve_op == ISL_AUX_OP_FULL_RESOLVE ||
+          resolve_op == ISL_AUX_OP_PARTIAL_RESOLVE);
+   batch->screen->vtbl.disable_rhwo_optimization(batch, false);
+
    iris_batch_sync_region_start(batch);
    struct blorp_batch blorp_batch;
    blorp_batch_init(&ice->blorp, &blorp_batch, batch, 0);
@@ -475,6 +487,9 @@ iris_resolve_color(struct iris_context *ice,
    /* See comment above */
    iris_emit_end_of_pipe_sync(batch, "color resolve: post-flush",
                               PIPE_CONTROL_RENDER_TARGET_FLUSH);
+
+   batch->screen->vtbl.disable_rhwo_optimization(batch, true);
+
    iris_batch_sync_region_end(batch);
 }
 

src/gallium/drivers/iris/iris_screen.h

@@ -140,6 +140,7 @@ struct iris_vtable {
    void (*populate_cs_key)(const struct iris_context *ice,
                            struct iris_cs_prog_key *key);
    void (*lost_genx_state)(struct iris_context *ice, struct iris_batch *batch);
+   void (*disable_rhwo_optimization)(struct iris_batch *batch, bool disable);
 };
 
 struct iris_address {

src/gallium/drivers/iris/iris_state.c

@@ -999,6 +999,18 @@ static void
 init_aux_map_state(struct iris_batch *batch);
 #endif
 
+/* This updates a register. Caller should stall the pipeline as needed. */
+static void
+iris_disable_rhwo_optimization(struct iris_batch *batch, bool disable)
+{
+#if GFX_VERx10 == 120
+   iris_emit_reg(batch, GENX(COMMON_SLICE_CHICKEN1), c1) {
+      c1.RCCRHWOOptimizationDisable = disable;
+      c1.RCCRHWOOptimizationDisableMask = true;
+   };
+#endif
+}
+
 /**
  * Upload initial GPU state for any kind of context.
  *
@@ -1142,6 +1154,22 @@ iris_init_render_context(struct iris_batch *batch)
 #endif
 
 #if GFX_VERx10 == 120
+   /* Wa_1508744258
+    *
+    *    Disable RHWO by setting 0x7010[14] by default except during resolve
+    *    pass.
+    *
+    * We implement global disabling of the optimization here and we toggle it
+    * in iris_resolve_color.
+    *
+    * iris_init_compute_context is unmodified because we don't expect to
+    * access the RCC in the compute context. iris_mcs_partial_resolve is
+    * unmodified because that pass doesn't use a HW bit to perform the
+    * resolve (related HSDs specifically call out the RenderTargetResolveType
+    * field in the 3DSTATE_PS instruction).
+    */
+   iris_disable_rhwo_optimization(batch, true);
+
    /* Wa_1806527549 says to disable the following HiZ optimization when the
     * depth buffer is D16_UNORM. We've found the WA to help with more depth
     * buffer configurations however, so we always disable it just to be safe.
@@ -8531,6 +8559,7 @@ genX(init_screen_state)(struct iris_screen *screen)
    screen->vtbl.populate_fs_key = iris_populate_fs_key;
    screen->vtbl.populate_cs_key = iris_populate_cs_key;
    screen->vtbl.lost_genx_state = iris_lost_genx_state;
+   screen->vtbl.disable_rhwo_optimization = iris_disable_rhwo_optimization;
 }
 
 void

src/intel/genxml/gen12.xml

@@ -6888,7 +6888,9 @@
   </register>
   <register name="COMMON_SLICE_CHICKEN1" length="1" num="0x7010">
     <field name="HIZ Plane Optimization disable bit" start="9" end="9" type="bool" />
+    <field name="RCC RHWO Optimization Disable" start="14" end="14" type="bool" />
     <field name="HIZ Plane Optimization disable bit Mask" start="25" end="25" type="bool" />
+    <field name="RCC RHWO Optimization Disable Mask" start="30" end="30" type="bool" />
   </register>
   <register name="COMMON_SLICE_CHICKEN3" length="1" num="0x7304">
     <field name="PS Thread Panic Dispatch" start="6" end="7" type="uint" />