From 0f2f247f919fe217e2fb1bf09bec6e11e6675c33 Mon Sep 17 00:00:00 2001 From: Rob Clark Date: Mon, 25 Aug 2025 08:03:28 -0700 Subject: [PATCH] freedreno: Name a few events And add them to the gpu_event helper so we don't need to open-code these packets. Signed-off-by: Rob Clark Part-of: --- src/freedreno/common/freedreno_gpu_event.h | 9 +++++++++ src/freedreno/registers/adreno/adreno_pm4.xml | 6 +++--- src/freedreno/tests/reference/fd-clouds.log | 8 ++++---- src/freedreno/vulkan/tu_cmd_buffer.cc | 8 +++----- src/gallium/drivers/freedreno/a5xx/fd5_gmem.c | 4 ++-- src/gallium/drivers/freedreno/a6xx/fd6_emit.cc | 6 ++---- src/gallium/drivers/freedreno/a6xx/fd6_gmem.cc | 6 ++---- 7 files changed, 25 insertions(+), 22 deletions(-) diff --git a/src/freedreno/common/freedreno_gpu_event.h b/src/freedreno/common/freedreno_gpu_event.h index 3ca2a6cebd8..562a7f33d39 100644 --- a/src/freedreno/common/freedreno_gpu_event.h +++ b/src/freedreno/common/freedreno_gpu_event.h @@ -43,6 +43,9 @@ enum fd_gpu_event : uint32_t { FD_CCU_CLEAN_COLOR, FD_LRZ_CLEAR, FD_LRZ_FLUSH, + FD_LRZ_INVALIDATE, + FD_VSC_BINNING_START, + FD_VSC_BINNING_END, FD_BLIT, FD_LABEL, FD_DUMMY_EVENT, @@ -82,6 +85,9 @@ constexpr inline struct fd_gpu_event_info fd_gpu_events[FD_GPU_EVENT_MAX] {PC_CCU_FLUSH_COLOR_TS, true}, /* FD_CCU_CLEAN_COLOR */ {LRZ_CLEAR, false}, /* FD_LRZ_CLEAR */ {LRZ_FLUSH, false}, /* FD_LRZ_FLUSH */ + {LRZ_CACHE_INVALIDATE, false}, /* FD_LRZ_INVALIDATE */ + {VSC_BINNING_START, false}, /* FD_VSC_BINNING_START */ + {VSC_BINNING_END, false}, /* FD_VSC_BINNING_END */ {BLIT, false}, /* FD_BLIT */ {LABEL, false}, /* FD_LABEL */ }; @@ -110,6 +116,9 @@ constexpr inline struct fd_gpu_event_info fd_gpu_events[FD_GPU_EVENT_MAX] {CCU_CLEAN_COLOR, false}, /* FD_CCU_CLEAN_COLOR */ {LRZ_CLEAR, false}, /* FD_LRZ_CLEAR */ {LRZ_FLUSH, false}, /* FD_LRZ_FLUSH */ + {LRZ_CACHE_INVALIDATE, false}, /* FD_LRZ_INVALIDATE */ + {VSC_BINNING_START, false}, /* FD_VSC_BINNING_START */ + {VSC_BINNING_END, false}, /* FD_VSC_BINNING_END */ {BLIT, false}, /* FD_BLIT */ {LABEL, false}, /* FD_LABEL */ {DUMMY_EVENT, false}, /* FD_DUMMY_EVENT */ diff --git a/src/freedreno/registers/adreno/adreno_pm4.xml b/src/freedreno/registers/adreno/adreno_pm4.xml index 22175f13d1b..0e10e1c6d26 100644 --- a/src/freedreno/registers/adreno/adreno_pm4.xml +++ b/src/freedreno/registers/adreno/adreno_pm4.xml @@ -120,12 +120,12 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd"> - + - - + + diff --git a/src/freedreno/tests/reference/fd-clouds.log b/src/freedreno/tests/reference/fd-clouds.log index 86921b000e8..f322e4c8397 100644 --- a/src/freedreno/tests/reference/fd-clouds.log +++ b/src/freedreno/tests/reference/fd-clouds.log @@ -418,8 +418,8 @@ cmdstream[0]: 1023 dwords VFD_POWER_CNTL: 0x1 0000000001d914a0: 0000: 40a0f801 00000001 opcode: CP_EVENT_WRITE (46) (2 dwords) - { EVENT = UNK_2C } - event UNK_2C + { EVENT = VSC_BINNING_START } + event VSC_BINNING_START 0000000001d914a8: 0000: 70460001 0000002c write RB_WINDOW_OFFSET (8890) RB_WINDOW_OFFSET: { X = 0 | Y = 0 } @@ -1139,8 +1139,8 @@ cmdstream[0]: 1023 dwords { [0].ADDR = 0 } 0000000001d914e8: 0000: 70438003 00040000 00000000 00000000 opcode: CP_EVENT_WRITE (46) (2 dwords) - { EVENT = UNK_2D } - event UNK_2D + { EVENT = VSC_BINNING_END } + event VSC_BINNING_END 0000000001d914f8: 0000: 70460001 0000002d opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = CACHE_INVALIDATE } diff --git a/src/freedreno/vulkan/tu_cmd_buffer.cc b/src/freedreno/vulkan/tu_cmd_buffer.cc index b113d19bd6b..7f5c03f7e82 100644 --- a/src/freedreno/vulkan/tu_cmd_buffer.cc +++ b/src/freedreno/vulkan/tu_cmd_buffer.cc @@ -1947,7 +1947,7 @@ tu6_init_hw(struct tu_cmd_buffer *cmd, struct tu_cs *cs) tu_emit_event_write(cmd, cs, FD_CCU_INVALIDATE_COLOR); tu_emit_event_write(cmd, cs, FD_CCU_INVALIDATE_DEPTH); - tu_emit_raw_event_write(cmd, cs, UNK_40, false); + tu_emit_event_write(cmd, cs, FD_LRZ_INVALIDATE); tu_emit_event_write(cmd, cs, FD_CACHE_INVALIDATE); tu_cs_emit_wfi(cs); } @@ -2189,8 +2189,7 @@ tu6_emit_binning_pass(struct tu_cmd_buffer *cmd, struct tu_cs *cs, A6XX_VFD_POWER_CNTL(phys_dev->info->a6xx.magic.PC_POWER_CNTL)); } - tu_cs_emit_pkt7(cs, CP_EVENT_WRITE, 1); - tu_cs_emit(cs, UNK_2C); + tu_emit_event_write(cmd, cs, FD_VSC_BINNING_START); tu_cs_emit_regs(cs, A6XX_RB_WINDOW_OFFSET(.x = 0, .y = 0)); @@ -2219,8 +2218,7 @@ tu6_emit_binning_pass(struct tu_cmd_buffer *cmd, struct tu_cs *cs, tu_cs_emit(cs, CP_SET_DRAW_STATE__1_ADDR_LO(0)); tu_cs_emit(cs, CP_SET_DRAW_STATE__2_ADDR_HI(0)); - tu_cs_emit_pkt7(cs, CP_EVENT_WRITE, 1); - tu_cs_emit(cs, UNK_2D); + tu_emit_event_write(cmd, cs, FD_VSC_BINNING_END); /* This flush is probably required because the VSC, which produces the * visibility stream, is a client of UCHE, whereas the CP needs to read the diff --git a/src/gallium/drivers/freedreno/a5xx/fd5_gmem.c b/src/gallium/drivers/freedreno/a5xx/fd5_gmem.c index 2352f2fab30..d0c8b301fe2 100644 --- a/src/gallium/drivers/freedreno/a5xx/fd5_gmem.c +++ b/src/gallium/drivers/freedreno/a5xx/fd5_gmem.c @@ -350,7 +350,7 @@ emit_binning_pass(struct fd_batch *batch) assert_dt OUT_PKT4(ring, REG_A5XX_VPC_MODE_CNTL, 1); OUT_RING(ring, A5XX_VPC_MODE_CNTL_BINNING_PASS); - fd5_event_write(batch, ring, UNK_2C, false); + fd5_event_write(batch, ring, VSC_BINNING_START, false); OUT_PKT4(ring, REG_A5XX_RB_WINDOW_OFFSET, 1); OUT_RING(ring, A5XX_RB_WINDOW_OFFSET_X(0) | A5XX_RB_WINDOW_OFFSET_Y(0)); @@ -360,7 +360,7 @@ emit_binning_pass(struct fd_batch *batch) assert_dt fd_reset_wfi(batch); - fd5_event_write(batch, ring, UNK_2D, false); + fd5_event_write(batch, ring, VSC_BINNING_END, false); fd5_event_write(batch, ring, CACHE_FLUSH_TS, true); diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_emit.cc b/src/gallium/drivers/freedreno/a6xx/fd6_emit.cc index 642a4690f80..2b5ceae5169 100644 --- a/src/gallium/drivers/freedreno/a6xx/fd6_emit.cc +++ b/src/gallium/drivers/freedreno/a6xx/fd6_emit.cc @@ -1099,11 +1099,9 @@ fd6_emit_restore(fd_cs &cs, struct fd_batch *batch) fd6_event_write(ctx, cs, FD_CCU_INVALIDATE_COLOR); fd6_event_write(ctx, cs, FD_CCU_INVALIDATE_DEPTH); - - fd_pkt7(cs, CP_EVENT_WRITE, 1) - .add(UNK_40); - + fd6_event_write(ctx, cs, FD_LRZ_INVALIDATE); fd6_event_write(ctx, cs, FD_CACHE_INVALIDATE); + fd_pkt7(cs, CP_WAIT_FOR_IDLE, 0); } diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_gmem.cc b/src/gallium/drivers/freedreno/a6xx/fd6_gmem.cc index caf1ec27ff3..73d38dcc361 100644 --- a/src/gallium/drivers/freedreno/a6xx/fd6_gmem.cc +++ b/src/gallium/drivers/freedreno/a6xx/fd6_gmem.cc @@ -969,8 +969,7 @@ emit_binning_pass(fd_cs &cs, struct fd_batch *batch) assert_dt .add(A6XX_VFD_POWER_CNTL(screen->info->a6xx.magic.PC_POWER_CNTL)); } - fd_pkt7(cs, CP_EVENT_WRITE, 1) - .add(UNK_2C); + fd6_event_write(batch->ctx, cs, FD_VSC_BINNING_START); fd_crb(cs, 2) .add(A6XX_RB_WINDOW_OFFSET(.x = 0, .y = 0)) @@ -988,8 +987,7 @@ emit_binning_pass(fd_cs &cs, struct fd_batch *batch) assert_dt .add(CP_SET_DRAW_STATE__0(0, .disable_all_groups = true)) .add(CP_SET_DRAW_STATE__ADDR(0)); - fd_pkt7(cs, CP_EVENT_WRITE, 1) - .add(UNK_2D); + fd6_event_write(batch->ctx, cs, FD_VSC_BINNING_END); /* This flush is probably required because the VSC, which produces the * visibility stream, is a client of UCHE, whereas the CP needs to read