diff --git a/src/gallium/drivers/iris/iris_resolve.c b/src/gallium/drivers/iris/iris_resolve.c
index 35a86a5417c..b768d7e5adc 100644
--- a/src/gallium/drivers/iris/iris_resolve.c
+++ b/src/gallium/drivers/iris/iris_resolve.c
@@ -1046,6 +1046,10 @@ iris_image_view_aux_usage(struct iris_context *ice,
    bool uses_atomic_load_store =
       ice->shaders.uncompiled[info->stage]->uses_atomic_load_store;
 
+   /* Prior to GFX12, render compression is not supported for images. */
+   if (devinfo->ver < 12)
+      return ISL_AUX_USAGE_NONE;
+
    /* On GFX12, compressed surfaces supports non-atomic operations. GFX12HP and
     * further, add support for all the operations.
     */
@@ -1059,10 +1063,13 @@ iris_image_view_aux_usage(struct iris_context *ice,
        !iris_has_invalid_primary(res, level, 1, 0, INTEL_REMAINING_LAYERS))
       return ISL_AUX_USAGE_NONE;
 
+   /* The FCV feature is documented to occur on regular render writes. Images
+    * are written to with the DC data port however.
+    */
    if (res->aux.usage == ISL_AUX_USAGE_FCV_CCS_E)
-      return res->aux.usage;
+      return ISL_AUX_USAGE_CCS_E;
 
-   return ISL_AUX_USAGE_NONE;
+   return res->aux.usage;
 }
 
 bool
diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c
index 0aaff4eac95..fed17a7bef9 100644
--- a/src/gallium/drivers/iris/iris_state.c
+++ b/src/gallium/drivers/iris/iris_state.c
@@ -3071,8 +3071,8 @@ iris_set_shader_images(struct pipe_context *ctx,
          unsigned aux_usages = 1 << ISL_AUX_USAGE_NONE;
 
          /* Gfx12+ supports render compression for images */
-         if (GFX_VER >= 12)
-            aux_usages |= 1 << res->aux.usage;
+         if (GFX_VER >= 12 && isl_aux_usage_has_ccs_e(res->aux.usage))
+            aux_usages |= 1 << ISL_AUX_USAGE_CCS_E;
 
          alloc_surface_states(&iv->surface_state, aux_usages);
          iv->surface_state.bo_address = res->bo->address;