diff --git a/src/gallium/drivers/radeonsi/si_barrier.c b/src/gallium/drivers/radeonsi/si_barrier.c
index bbb4accd82b..86d910d8014 100644
--- a/src/gallium/drivers/radeonsi/si_barrier.c
+++ b/src/gallium/drivers/radeonsi/si_barrier.c
@@ -377,7 +377,7 @@ static void gfx6_emit_barrier(struct si_context *sctx, struct radeon_cmdbuf *cs)
          tc_flags = EVENT_TC_ACTION_ENA | EVENT_TC_MD_ACTION_ENA;
       }
 
-      /* Ideally flush TC together with CB/DB. */
+      /* Ideally flush L2 together with CB/DB. */
       if (flags & SI_CONTEXT_INV_L2) {
          /* Writeback and invalidate everything in L2 & L1. */
          tc_flags = EVENT_TC_ACTION_ENA | EVENT_TC_WB_ACTION_ENA;
@@ -680,7 +680,7 @@ static void si_memory_barrier(struct pipe_context *ctx, unsigned flags)
    }
 
    if (flags & PIPE_BARRIER_INDEX_BUFFER) {
-      /* Indices are read through TC L2 since GFX8.
+      /* Indices are read through L2 since GFX8.
        * L1 isn't used.
        */
       if (sctx->screen->info.gfx_level <= GFX7)
@@ -697,7 +697,7 @@ static void si_memory_barrier(struct pipe_context *ctx, unsigned flags)
          sctx->flags |= SI_CONTEXT_WB_L2;
    }
 
-   /* Indirect buffers use TC L2 on GFX9, but not older hw. */
+   /* Indirect buffers use L2 on GFX9, but not older hw. */
    if (sctx->screen->info.gfx_level <= GFX8 && flags & PIPE_BARRIER_INDIRECT_BUFFER)
       sctx->flags |= SI_CONTEXT_WB_L2;
 
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.cpp b/src/gallium/drivers/radeonsi/si_state_draw.cpp
index 0985c271b93..5ad72fc4892 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.cpp
+++ b/src/gallium/drivers/radeonsi/si_state_draw.cpp
@@ -2120,7 +2120,7 @@ static void si_draw(struct pipe_context *ctx,
          index_offset = 0;
          index_size = 2;
 
-         /* GFX6-7 don't read index buffers through TC L2. */
+         /* GFX6-7 don't read index buffers through L2. */
          sctx->flags |= SI_CONTEXT_WB_L2 | SI_CONTEXT_PFP_SYNC_ME;
          si_mark_atom_dirty(sctx, &sctx->atoms.s.barrier);
          si_resource(indexbuf)->TC_L2_dirty = false;