From 0e8100bf581df25052ee35f4d2d03f3088660307 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Thu, 6 May 2021 20:43:34 -0400 Subject: [PATCH] radeonsi: simplify the NGG culling vertex count heuristic MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This removes another chip-specific switch. It enables a lower threshold on Navi1x, which should be fine. Acked-by: Timur Kristóf Part-of: --- src/gallium/drivers/radeonsi/si_state_shaders.c | 17 +---------------- 1 file changed, 1 insertion(+), 16 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c b/src/gallium/drivers/radeonsi/si_state_shaders.c index 6ce4b2db349..221d28eecf3 100644 --- a/src/gallium/drivers/radeonsi/si_state_shaders.c +++ b/src/gallium/drivers/radeonsi/si_state_shaders.c @@ -2849,22 +2849,7 @@ static void *si_create_shader_selector(struct pipe_context *ctx, sscreen->info.chip_class == GFX10_3 || (sscreen->info.chip_class == GFX10 && sscreen->info.is_pro_graphics)) { - /* Rough estimates. */ - switch (sctx->family) { - case CHIP_NAVI10: - case CHIP_NAVI12: - case CHIP_SIENNA_CICHLID: - sel->ngg_cull_vert_threshold = 511; - break; - case CHIP_NAVI14: - case CHIP_NAVY_FLOUNDER: - case CHIP_DIMGREY_CAVEFISH: - case CHIP_VANGOGH: - sel->ngg_cull_vert_threshold = 255; - break; - default: - assert(!sscreen->use_ngg_culling); - } + sel->ngg_cull_vert_threshold = sscreen->info.num_se >= 3 ? 511 : 255; } } else if (sel->info.stage == MESA_SHADER_TESS_EVAL) { if (sel->rast_prim == PIPE_PRIM_TRIANGLES &&