From 0ce2401144469f966da68db487ef29f818e5a690 Mon Sep 17 00:00:00 2001 From: Bas Nieuwenhuizen Date: Thu, 5 May 2022 01:40:34 +0200 Subject: [PATCH] radv: update the initialization of SGPR0/1 registers for HS and GS on GFX11 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Samuel Pitoiset Reviewed-by: Timur Kristóf Part-of: --- src/amd/vulkan/radv_device.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c index 2a0a2a26e70..8fc6f5b69d6 100644 --- a/src/amd/vulkan/radv_device.c +++ b/src/amd/vulkan/radv_device.c @@ -3930,7 +3930,15 @@ radv_emit_global_shader_pointers(struct radv_queue *queue, struct radeon_cmdbuf radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo); - if (queue->device->physical_device->rad_info.gfx_level >= GFX10) { + if (queue->device->physical_device->rad_info.gfx_level >= GFX11) { + uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0, + R_00B420_SPI_SHADER_PGM_LO_HS, + R_00B220_SPI_SHADER_PGM_LO_GS}; + + for (int i = 0; i < ARRAY_SIZE(regs); ++i) { + radv_emit_shader_pointer(queue->device, cs, regs[i], va, true); + } + } else if (queue->device->physical_device->rad_info.gfx_level >= GFX10) { uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0, R_00B130_SPI_SHADER_USER_DATA_VS_0, R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS, R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};