diff --git a/src/freedreno/ir3/ir3_delay.c b/src/freedreno/ir3/ir3_delay.c
index 71617aee90f..83730b5132e 100644
--- a/src/freedreno/ir3/ir3_delay.c
+++ b/src/freedreno/ir3/ir3_delay.c
@@ -30,19 +30,6 @@
  */
 #define MAX_NOPS 6
 
-/* The soft delay for approximating the cost of (ss). On a6xx, it takes the
- * number of delay slots to get a SFU result back (ie. using nop's instead of
- * (ss) is:
- *
- *     8 - single warp
- *     9 - two warps
- *    10 - four warps
- *
- * and so on. Not quite sure where it tapers out (ie. how many warps share an
- * SFU unit). But 10 seems like a reasonable # to choose:
- */
-#define SOFT_SS_NOPS 10
-
 /*
  * Helpers to figure out the necessary delay slots between instructions.  Used
  * both in scheduling pass(es) and the final pass to insert any required nop's
@@ -76,11 +63,11 @@ ir3_delayslots(struct ir3_instruction *assigner,
    if (writes_addr0(assigner) || writes_addr1(assigner))
       return 6;
 
-   if (soft && is_sfu(assigner))
-      return SOFT_SS_NOPS;
+   if (soft && is_ss_producer(assigner))
+      return soft_ss_delay(assigner);
 
    /* handled via sync flags: */
-   if (is_sfu(assigner) || is_tex(assigner) || is_mem(assigner))
+   if (is_ss_producer(assigner) || is_sy_producer(assigner))
       return 0;
 
    /* As far as we know, shader outputs don't need any delay. */
diff --git a/src/freedreno/ir3/ir3_postsched.c b/src/freedreno/ir3/ir3_postsched.c
index 43a6223ee0a..402262053c9 100644
--- a/src/freedreno/ir3/ir3_postsched.c
+++ b/src/freedreno/ir3/ir3_postsched.c
@@ -140,16 +140,16 @@ schedule(struct ir3_postsched_ctx *ctx, struct ir3_instruction *instr)
    if (is_meta(instr) && (instr->opc != OPC_META_TEX_PREFETCH))
       return;
 
-   if (is_sfu(instr)) {
-      ctx->sfu_delay = 8;
+   if (is_ss_producer(instr)) {
+      ctx->sfu_delay = soft_ss_delay(instr);
    } else if (has_sfu_src(instr)) {
       ctx->sfu_delay = 0;
    } else if (ctx->sfu_delay > 0) {
       ctx->sfu_delay--;
    }
 
-   if (is_tex_or_prefetch(instr)) {
-      ctx->tex_delay = 10;
+   if (is_sy_producer(instr)) {
+      ctx->tex_delay = soft_sy_delay(instr, ctx->block->shader);
    } else if (has_tex_src(instr)) {
       ctx->tex_delay = 0;
    } else if (ctx->tex_delay > 0) {
@@ -261,7 +261,7 @@ choose_instr(struct ir3_postsched_ctx *ctx)
       if (d > 0)
          continue;
 
-      if (!(is_sfu(n->instr) || is_tex(n->instr)))
+      if (!(is_ss_producer(n->instr) || is_sy_producer(n->instr)))
          continue;
 
       if (!chosen || (chosen->max_delay < n->max_delay))
@@ -403,9 +403,9 @@ add_single_reg_dep(struct ir3_postsched_deps_state *state,
       unsigned d_soft = ir3_delayslots(dep->instr, node->instr, src_n, true);
       d = ir3_delayslots_with_repeat(dep->instr, node->instr, dst_n, src_n);
       node->delay = MAX2(node->delay, d_soft);
-      if (is_tex_or_prefetch(dep->instr))
+      if (is_sy_producer(dep->instr))
          node->has_tex_src = true;
-      if (is_sfu(dep->instr))
+      if (is_ss_producer(dep->instr))
          node->has_sfu_src = true;
    }
 
diff --git a/src/freedreno/ir3/ir3_sched.c b/src/freedreno/ir3/ir3_sched.c
index f26de995044..98c9c69c105 100644
--- a/src/freedreno/ir3/ir3_sched.c
+++ b/src/freedreno/ir3/ir3_sched.c
@@ -212,7 +212,7 @@ static bool
 is_outstanding_tex_or_prefetch(struct ir3_instruction *instr,
                                struct ir3_sched_ctx *ctx)
 {
-   if (!is_tex_or_prefetch(instr))
+   if (!is_sy_producer(instr))
       return false;
 
    /* The sched node is only valid within the same block, we cannot
@@ -228,7 +228,7 @@ is_outstanding_tex_or_prefetch(struct ir3_instruction *instr,
 static bool
 is_outstanding_sfu(struct ir3_instruction *instr, struct ir3_sched_ctx *ctx)
 {
-   if (!is_sfu(instr))
+   if (!is_ss_producer(instr))
       return false;
 
    /* The sched node is only valid within the same block, we cannot
@@ -330,8 +330,8 @@ schedule(struct ir3_sched_ctx *ctx, struct ir3_instruction *instr)
 
    unsigned cycles = cycle_count(instr);
 
-   if (is_sfu(instr)) {
-      ctx->sfu_delay = 8;
+   if (is_ss_producer(instr)) {
+      ctx->sfu_delay = soft_ss_delay(instr);
       n->sfu_index = ctx->sfu_index++;
    } else if (!is_meta(instr) &&
               sched_check_src_cond(instr, is_outstanding_sfu, ctx)) {
@@ -341,13 +341,13 @@ schedule(struct ir3_sched_ctx *ctx, struct ir3_instruction *instr)
       ctx->sfu_delay -= MIN2(cycles, ctx->sfu_delay);
    }
 
-   if (is_tex_or_prefetch(instr)) {
+   if (is_sy_producer(instr)) {
       /* NOTE that this isn't an attempt to hide texture fetch latency,
        * but an attempt to hide the cost of switching to another warp.
        * If we can, we'd like to try to schedule another texture fetch
        * before scheduling something that would sync.
        */
-      ctx->tex_delay = 10;
+      ctx->tex_delay = soft_sy_delay(instr, ctx->block->shader);
       assert(ctx->remaining_tex > 0);
       ctx->remaining_tex--;
       n->tex_index = ctx->tex_index++;
@@ -607,10 +607,10 @@ should_defer(struct ir3_sched_ctx *ctx, struct ir3_instruction *instr)
     * and prevents unacceptably large increases in register pressure from too
     * many outstanding texture instructions.
     */
-   if (ctx->tex_index - ctx->first_outstanding_tex_index >= 8 && is_tex(instr))
+   if (ctx->tex_index - ctx->first_outstanding_tex_index >= 8 && is_sy_producer(instr))
       return true;
 
-   if (ctx->sfu_index - ctx->first_outstanding_sfu_index >= 8 && is_sfu(instr))
+   if (ctx->sfu_index - ctx->first_outstanding_sfu_index >= 8 && is_ss_producer(instr))
       return true;
 
    return false;
@@ -1179,7 +1179,7 @@ sched_block(struct ir3_sched_ctx *ctx, struct ir3_block *block)
    foreach_instr_safe (instr, &ctx->unscheduled_list) {
       if (is_kill_or_demote(instr))
          ctx->remaining_kills++;
-      if (is_tex_or_prefetch(instr))
+      if (is_sy_producer(instr))
          ctx->remaining_tex++;
    }