diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index c486617166f..9a0c5ea4ec2 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -231,7 +231,7 @@ radv_use_dcc_for_image(struct radv_device *device, struct radv_image *image,
     * decompressing a lot anyway we might as well not have DCC.
     */
    if ((pCreateInfo->usage & VK_IMAGE_USAGE_STORAGE_BIT) &&
-       (!radv_image_use_dcc_image_stores(device, image) ||
+       (device->physical_device->rad_info.chip_class < GFX10 ||
         radv_formats_is_atomic_allowed(pCreateInfo->pNext, format, pCreateInfo->flags)))
       return false;
 
@@ -281,7 +281,20 @@ radv_use_dcc_for_image(struct radv_device *device, struct radv_image *image,
 bool
 radv_image_use_dcc_image_stores(const struct radv_device *device, const struct radv_image *image)
 {
-   return device->physical_device->rad_info.chip_class >= GFX10;
+   /* DCC image stores is only available for GFX10+. */
+   if (device->physical_device->rad_info.chip_class < GFX10)
+      return false;
+
+   if ((device->physical_device->rad_info.family == CHIP_NAVI12 ||
+        device->physical_device->rad_info.family == CHIP_NAVI14) &&
+       !image->planes[0].surface.u.gfx9.color.dcc.independent_128B_blocks) {
+      /* Do not enable DCC image stores because INDEPENDENT_128B_BLOCKS is required, and 64B is used
+       * for displayable DCC on NAVI12-14.
+       */
+      return false;
+   }
+
+   return true;
 }
 
 /*