diff --git a/src/amd/vulkan/Makefile.sources b/src/amd/vulkan/Makefile.sources index 025dd558f46..126b67b06bf 100644 --- a/src/amd/vulkan/Makefile.sources +++ b/src/amd/vulkan/Makefile.sources @@ -60,6 +60,7 @@ VULKAN_FILES := \ radv_meta_bufimage.c \ radv_meta_clear.c \ radv_meta_copy.c \ + radv_meta_copy_vrs_htile.c \ radv_meta_dcc_retile.c \ radv_meta_decompress.c \ radv_meta_fast_clear.c \ diff --git a/src/amd/vulkan/meson.build b/src/amd/vulkan/meson.build index abe80db75cb..629dd04c431 100644 --- a/src/amd/vulkan/meson.build +++ b/src/amd/vulkan/meson.build @@ -57,6 +57,7 @@ libradv_files = files( 'radv_meta_bufimage.c', 'radv_meta_clear.c', 'radv_meta_copy.c', + 'radv_meta_copy_vrs_htile.c', 'radv_meta_dcc_retile.c', 'radv_meta_decompress.c', 'radv_meta_fast_clear.c', diff --git a/src/amd/vulkan/radv_meta.c b/src/amd/vulkan/radv_meta.c index 28a266f0824..db456e146a7 100644 --- a/src/amd/vulkan/radv_meta.c +++ b/src/amd/vulkan/radv_meta.c @@ -506,6 +506,7 @@ radv_device_finish_meta(struct radv_device *device) radv_device_finish_meta_resolve_fragment_state(device); radv_device_finish_meta_fmask_expand_state(device); radv_device_finish_meta_dcc_retile_state(device); + radv_device_finish_meta_copy_vrs_htile_state(device); radv_store_meta_pipeline(device); radv_pipeline_cache_finish(&device->meta_state.cache); diff --git a/src/amd/vulkan/radv_meta.h b/src/amd/vulkan/radv_meta.h index 0e351702470..c1b34a2b49f 100644 --- a/src/amd/vulkan/radv_meta.h +++ b/src/amd/vulkan/radv_meta.h @@ -127,6 +127,8 @@ void radv_device_finish_meta_fmask_expand_state(struct radv_device *device); void radv_device_finish_meta_dcc_retile_state(struct radv_device *device); +void radv_device_finish_meta_copy_vrs_htile_state(struct radv_device *device); + void radv_meta_save(struct radv_meta_saved_state *saved_state, struct radv_cmd_buffer *cmd_buffer, uint32_t flags); @@ -206,6 +208,8 @@ void radv_decompress_dcc(struct radv_cmd_buffer *cmd_buffer, struct radv_image * void radv_retile_dcc(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image); void radv_expand_fmask_image_inplace(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image, const VkImageSubresourceRange *subresourceRange); +void radv_copy_vrs_htile(struct radv_cmd_buffer *cmd_buffer, struct radv_image *vrs_image, + VkExtent2D *extent, struct radv_image *dst_image); void radv_meta_resolve_compute_image(struct radv_cmd_buffer *cmd_buffer, struct radv_image *src_image, VkFormat src_format, diff --git a/src/amd/vulkan/radv_meta_copy_vrs_htile.c b/src/amd/vulkan/radv_meta_copy_vrs_htile.c new file mode 100644 index 00000000000..d67dece2f2f --- /dev/null +++ b/src/amd/vulkan/radv_meta_copy_vrs_htile.c @@ -0,0 +1,304 @@ +/* + * Copyright © 2021 Valve Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +#define AC_SURFACE_INCLUDE_NIR +#include "ac_surface.h" + +#include "radv_meta.h" +#include "radv_private.h" +#include "vk_format.h" + +void +radv_device_finish_meta_copy_vrs_htile_state(struct radv_device *device) +{ + struct radv_meta_state *state = &device->meta_state; + + radv_DestroyPipeline(radv_device_to_handle(device), state->copy_vrs_htile_pipeline, + &state->alloc); + radv_DestroyPipelineLayout(radv_device_to_handle(device), state->copy_vrs_htile_p_layout, + &state->alloc); + radv_DestroyDescriptorSetLayout(radv_device_to_handle(device), state->copy_vrs_htile_ds_layout, + &state->alloc); +} + +static nir_shader * +build_copy_vrs_htile_shader(struct radv_device *device, struct radeon_surf *surf) +{ + nir_builder b = nir_builder_init_simple_shader(MESA_SHADER_COMPUTE, NULL, "meta_copy_vrs_htile"); + b.shader->info.cs.local_size[0] = 8; + b.shader->info.cs.local_size[1] = 8; + b.shader->info.cs.local_size[2] = 1; + + nir_ssa_def *invoc_id = nir_load_local_invocation_id(&b); + nir_ssa_def *wg_id = nir_load_work_group_id(&b, 32); + nir_ssa_def *block_size = + nir_imm_ivec4(&b, b.shader->info.cs.local_size[0], b.shader->info.cs.local_size[1], + b.shader->info.cs.local_size[2], 0); + + /* Get coordinates. */ + nir_ssa_def *global_id = nir_iadd(&b, nir_imul(&b, wg_id, block_size), invoc_id); + nir_ssa_def *coord = nir_channels(&b, global_id, 0x3); + + /* Multiply the coordinates by the HTILE block size. */ + coord = nir_imul(&b, coord, nir_imm_ivec2(&b, 8, 8)); + + /* Load constants. */ + nir_ssa_def *constants = nir_load_push_constant(&b, 2, 32, nir_imm_int(&b, 0), .range = 8); + nir_ssa_def *htile_pitch = nir_channel(&b, constants, 0); + nir_ssa_def *htile_slice_size = nir_channel(&b, constants, 1); + + /* Get the HTILE addr from coordinates. */ + nir_ssa_def *zero = nir_imm_int(&b, 0); + nir_ssa_def *htile_addr = ac_nir_htile_addr_from_coord( + &b, &device->physical_device->rad_info, &surf->u.gfx9.zs.htile_equation, htile_pitch, + htile_slice_size, nir_channel(&b, coord, 0), nir_channel(&b, coord, 1), zero, zero); + + /* Set up the input VRS image descriptor. */ + const struct glsl_type *vrs_sampler_type = + glsl_sampler_type(GLSL_SAMPLER_DIM_2D, false, false, GLSL_TYPE_FLOAT); + nir_variable *input_vrs_img = + nir_variable_create(b.shader, nir_var_uniform, vrs_sampler_type, "input_vrs_image"); + input_vrs_img->data.descriptor_set = 0; + input_vrs_img->data.binding = 0; + + nir_ssa_def *input_vrs_img_deref = &nir_build_deref_var(&b, input_vrs_img)->dest.ssa; + + /* Load the VRS rates from the 2D image. */ + nir_tex_instr *tex = nir_tex_instr_create(b.shader, 3); + tex->sampler_dim = GLSL_SAMPLER_DIM_2D; + tex->op = nir_texop_txf; + tex->src[0].src_type = nir_tex_src_coord; + tex->src[0].src = nir_src_for_ssa(nir_channels(&b, global_id, 0x3)); + tex->src[1].src_type = nir_tex_src_lod; + tex->src[1].src = nir_src_for_ssa(nir_imm_int(&b, 0)); + tex->src[2].src_type = nir_tex_src_texture_deref; + tex->src[2].src = nir_src_for_ssa(input_vrs_img_deref); + tex->dest_type = nir_type_float32; + tex->is_array = false; + tex->coord_components = 2; + + nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32, "tex"); + nir_builder_instr_insert(&b, &tex->instr); + + /* Extract the X/Y rates and clamp them because the maximum supported VRS rate is 2x2 (1x1 in + * hardware). + * + * VRS rate X = min(value >> 2, 1) + * VRS rate Y = min(value & 3, 1) + */ + nir_ssa_def *x_rate = nir_ushr(&b, &tex->dest.ssa, nir_imm_int(&b, 2)); + x_rate = nir_umin(&b, x_rate, nir_imm_int(&b, 1)); + + nir_ssa_def *y_rate = nir_iand(&b, &tex->dest.ssa, nir_imm_int(&b, 3)); + y_rate = nir_umin(&b, y_rate, nir_imm_int(&b, 1)); + + /* Compute the final VRS rate. */ + nir_ssa_def *vrs_rates = nir_ior(&b, nir_ishl(&b, y_rate, nir_imm_int(&b, 10)), + nir_ishl(&b, x_rate, nir_imm_int(&b, 6))); + + /* Load the HTILE buffer descriptor. */ + nir_ssa_def *htile_buf = radv_meta_load_descriptor(&b, 0, 1); + + /* Load the existing HTILE 32-bit value for this 8x8 pixels area. */ + nir_ssa_def *htile_value = nir_load_ssbo(&b, 1, 32, htile_buf, htile_addr, .align_mul = 4); + + /* Clear the 4-bit VRS rates. */ + htile_value = nir_iand(&b, htile_value, nir_imm_int(&b, 0xfffff33f)); + + /* Set the VRS rates loaded from the image. */ + htile_value = nir_ior(&b, htile_value, vrs_rates); + + /* Store the updated HTILE 32-bit which contains the VRS rates. */ + nir_store_ssbo(&b, htile_value, htile_buf, htile_addr, .write_mask = 0x1, + .access = ACCESS_NON_READABLE, .align_mul = 4); + + return b.shader; +} + +static VkResult +radv_device_init_meta_copy_vrs_htile_state(struct radv_device *device, + struct radeon_surf *surf) +{ + struct radv_meta_state *state = &device->meta_state; + nir_shader *cs = build_copy_vrs_htile_shader(device, surf); + VkResult result; + + VkDescriptorSetLayoutCreateInfo ds_layout_info = { + .sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO, + .flags = VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR, + .bindingCount = 2, + .pBindings = (VkDescriptorSetLayoutBinding[]){ + {.binding = 0, + .descriptorType = VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE, + .descriptorCount = 1, + .stageFlags = VK_SHADER_STAGE_COMPUTE_BIT, + .pImmutableSamplers = NULL}, + {.binding = 1, + .descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_BUFFER, + .descriptorCount = 1, + .stageFlags = VK_SHADER_STAGE_COMPUTE_BIT, + .pImmutableSamplers = NULL}, + }}; + + result = radv_CreateDescriptorSetLayout(radv_device_to_handle(device), &ds_layout_info, + &state->alloc, &state->copy_vrs_htile_ds_layout); + if (result != VK_SUCCESS) + goto fail; + + VkPipelineLayoutCreateInfo p_layout_info = { + .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO, + .setLayoutCount = 1, + .pSetLayouts = &state->copy_vrs_htile_ds_layout, + .pushConstantRangeCount = 1, + .pPushConstantRanges = + &(VkPushConstantRange){ + VK_SHADER_STAGE_COMPUTE_BIT, + 0, + 8, + }, + }; + + result = radv_CreatePipelineLayout(radv_device_to_handle(device), &p_layout_info, &state->alloc, + &state->copy_vrs_htile_p_layout); + if (result != VK_SUCCESS) + goto fail; + + VkPipelineShaderStageCreateInfo shader_stage = { + .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO, + .stage = VK_SHADER_STAGE_COMPUTE_BIT, + .module = vk_shader_module_handle_from_nir(cs), + .pName = "main", + .pSpecializationInfo = NULL, + }; + + VkComputePipelineCreateInfo pipeline_info = { + .sType = VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO, + .stage = shader_stage, + .flags = 0, + .layout = state->copy_vrs_htile_p_layout, + }; + + result = radv_CreateComputePipelines(radv_device_to_handle(device), + radv_pipeline_cache_to_handle(&state->cache), 1, + &pipeline_info, NULL, &state->copy_vrs_htile_pipeline); +fail: + ralloc_free(cs); + return result; +} + +void +radv_copy_vrs_htile(struct radv_cmd_buffer *cmd_buffer, struct radv_image *vrs_image, + VkExtent2D *extent, struct radv_image *dst_image) +{ + struct radv_device *device = cmd_buffer->device; + struct radv_meta_state *state = &device->meta_state; + struct radv_meta_saved_state saved_state; + struct radv_image_view vrs_iview; + + assert(radv_image_has_htile(dst_image)); + + if (!cmd_buffer->device->meta_state.copy_vrs_htile_pipeline) { + VkResult ret = radv_device_init_meta_copy_vrs_htile_state(cmd_buffer->device, + &dst_image->planes[0].surface); + if (ret != VK_SUCCESS) { + cmd_buffer->record_result = ret; + return; + } + } + + cmd_buffer->state.flush_bits |= + radv_src_access_flush(cmd_buffer, VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT, NULL) | + radv_dst_access_flush(cmd_buffer, VK_ACCESS_SHADER_READ_BIT, NULL); + + radv_meta_save( + &saved_state, cmd_buffer, + RADV_META_SAVE_COMPUTE_PIPELINE | RADV_META_SAVE_CONSTANTS | RADV_META_SAVE_DESCRIPTORS); + + radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer), VK_PIPELINE_BIND_POINT_COMPUTE, + state->copy_vrs_htile_pipeline); + + /* HTILE buffer */ + uint64_t htile_offset = dst_image->offset + dst_image->planes[0].surface.meta_offset; + uint64_t htile_size = dst_image->planes[0].surface.meta_slice_size; + struct radv_buffer htile_buffer = {.bo = dst_image->bo, + .offset = htile_offset, + .size = htile_size}; + + radv_image_view_init(&vrs_iview, cmd_buffer->device, + &(VkImageViewCreateInfo){ + .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO, + .image = radv_image_to_handle(vrs_image), + .viewType = VK_IMAGE_VIEW_TYPE_2D, + .format = vrs_image->vk_format, + .subresourceRange = {.aspectMask = VK_IMAGE_ASPECT_COLOR_BIT, + .baseMipLevel = 0, + .levelCount = 1, + .baseArrayLayer = 0, + .layerCount = 1}, + }, + NULL); + + radv_meta_push_descriptor_set( + cmd_buffer, VK_PIPELINE_BIND_POINT_COMPUTE, state->copy_vrs_htile_p_layout, 0, /* set */ + 2, /* descriptorWriteCount */ + (VkWriteDescriptorSet[]){ + {.sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET, + .dstBinding = 0, + .dstArrayElement = 0, + .descriptorCount = 1, + .descriptorType = VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE, + .pImageInfo = + (VkDescriptorImageInfo[]){ + { + .sampler = VK_NULL_HANDLE, + .imageView = radv_image_view_to_handle(&vrs_iview), + .imageLayout = VK_IMAGE_LAYOUT_GENERAL, + }, + }}, + {.sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET, + .dstBinding = 1, + .dstArrayElement = 0, + .descriptorCount = 1, + .descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_BUFFER, + .pBufferInfo = &(VkDescriptorBufferInfo){.buffer = radv_buffer_to_handle(&htile_buffer), + .offset = 0, + .range = htile_size}}}); + + const unsigned constants[2] = { + dst_image->planes[0].surface.meta_pitch, dst_image->planes[0].surface.meta_slice_size, + }; + + radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), state->copy_vrs_htile_p_layout, + VK_SHADER_STAGE_COMPUTE_BIT, 0, 8, constants); + + uint32_t width = DIV_ROUND_UP(extent->width, 8); + uint32_t height = DIV_ROUND_UP(extent->height, 8); + + radv_unaligned_dispatch(cmd_buffer, width, height, 1); + + radv_meta_restore(&saved_state, cmd_buffer); + + cmd_buffer->state.flush_bits |= + RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_INV_VCACHE | + radv_src_access_flush(cmd_buffer, VK_ACCESS_SHADER_WRITE_BIT, NULL); +} diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index 5f176914fc3..06cb896e1d3 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/amd/vulkan/radv_private.h @@ -473,6 +473,11 @@ struct radv_meta_state { VkPipelineLayout clear_htile_mask_p_layout; VkDescriptorSetLayout clear_htile_mask_ds_layout; + /* Copy VRS into HTILE. */ + VkPipeline copy_vrs_htile_pipeline; + VkPipelineLayout copy_vrs_htile_p_layout; + VkDescriptorSetLayout copy_vrs_htile_ds_layout; + struct { VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];