From 0aaea5d038e30deb8205166c6f69a43ffa2e50e2 Mon Sep 17 00:00:00 2001
From: Danylo Piliaiev <dpiliaiev@igalia.com>
Date: Tue, 28 Jan 2025 19:08:05 +0100
Subject: [PATCH] tu: Fix stale A7XX_GRAS_LRZ_CNTL2 in 3d blits or !valid lrz
 case

Fixes GPU faults with
TU_DEBUG_STALE_REGS_RANGE=0x810b,0x810b TU_DEBUG_STALE_REGS_FLAGS=cmdbuf,renderpass

Cc: mesa-stable

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33274>
---
 src/freedreno/vulkan/tu_clear_blit.cc | 1 +
 src/freedreno/vulkan/tu_lrz.cc        | 1 +
 2 files changed, 2 insertions(+)

diff --git a/src/freedreno/vulkan/tu_clear_blit.cc b/src/freedreno/vulkan/tu_clear_blit.cc
index 575135a69cd..4886fd4fa14 100644
--- a/src/freedreno/vulkan/tu_clear_blit.cc
+++ b/src/freedreno/vulkan/tu_clear_blit.cc
@@ -1628,6 +1628,7 @@ r3d_setup(struct tu_cmd_buffer *cmd,
    tu_cs_emit_regs(cs, A6XX_RB_LRZ_CNTL(0));
 
    if (CHIP >= A7XX) {
+      tu_cs_emit_regs(cs, A7XX_GRAS_LRZ_CNTL2(0));
       tu_cs_emit_regs(cs, A7XX_GRAS_LRZ_DEPTH_BUFFER_INFO());
 
       tu_cs_emit_regs(cs, A6XX_RB_FSR_CONFIG());
diff --git a/src/freedreno/vulkan/tu_lrz.cc b/src/freedreno/vulkan/tu_lrz.cc
index f1b0c5d526b..dc7a757db14 100644
--- a/src/freedreno/vulkan/tu_lrz.cc
+++ b/src/freedreno/vulkan/tu_lrz.cc
@@ -310,6 +310,7 @@ tu_lrz_begin_renderpass(struct tu_cmd_buffer *cmd)
    tu_lrz_begin_resumed_renderpass<CHIP>(cmd);
 
    if (!cmd->state.lrz.valid) {
+      tu6_write_lrz_cntl<CHIP>(cmd, &cmd->cs, {});
       tu6_emit_lrz_buffer<CHIP>(&cmd->cs, NULL);
    }
 }