etnaviv: isa: Combine branch and branch_if
As we want to use the new asm as a drop-in replacement we need to combine branch and branch_if back to one bitset. This is caused by the fact that we need to replicate the defines in isa.xml.h. Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27871>
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-11
@@ -730,13 +730,19 @@ SPDX-License-Identifier: MIT
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<pattern low="96" high="98">000</pattern>
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</bitset>
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<bitset name="#instruction-cf-src0-src1" extends="#instruction-cf">
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<bitset name="#instruction-cf-maybe-src0-src1" extends="#instruction-cf">
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<display>
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{INSTR_CF} {:align=18}void, {SRC0}, {SRC1}, {TARGET}
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{INSTR_CF} {:align=18}void, void, void, {TARGET}
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</display>
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<override expr="#instruction-has-src0-src1">
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<display>
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{INSTR_CF} {:align=18}void, {SRC0}, {SRC1}, {TARGET}
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</display>
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</override>
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<!-- SRC0 -->
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<pattern pos="43">1</pattern> <!-- SRC0_USE -->
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<field name="SRC0_USE" pos="43" type="bool"/>
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<field name="SRC0_REG" low="44" high="52" type="uint"/>
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<field name="SRC0" low="54" high="63" type="#instruction-src">
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<param name="SRC0_REG" as="SRC_REG"/>
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@@ -747,7 +753,7 @@ SPDX-License-Identifier: MIT
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<field name="SRC0_RGROUP" low="67" high="69" type="#reg_group"/>
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<!-- SRC1 -->
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<pattern pos="70">1</pattern> <!-- SRC1_USE -->
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<field name="SRC1_USE" pos="70" type="bool"/>
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<field name="SRC1_REG" low="71" high="79" type="uint"/>
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<field name="SRC1" low="81" high="90" type="#instruction-src">
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<param name="SRC1_REG" as="SRC_REG"/>
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@@ -1001,12 +1007,7 @@ SPDX-License-Identifier: MIT
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<pattern pos="80">0</pattern> <!-- OPCODE_BIT6 -->
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</bitset>
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<bitset name="branch" extends="#instruction-cf-no-src">
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<pattern low="0" high="5">010110</pattern> <!-- OPC -->
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<pattern pos="80">0</pattern> <!-- OPCODE_BIT6 -->
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</bitset>
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<bitset name="branch_if" extends="#instruction-cf-src0-src1" displayname="branch">
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<bitset name="branch" extends="#instruction-cf-maybe-src0-src1">
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<pattern low="0" high="5">010110</pattern> <!-- OPC -->
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<pattern pos="80">0</pattern> <!-- OPCODE_BIT6 -->
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</bitset>
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@@ -1059,7 +1060,7 @@ SPDX-License-Identifier: MIT
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<pattern pos="80">0</pattern> <!-- OPCODE_BIT6 -->
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</bitset>
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<bitset name="branch_any" extends="#instruction-cf-src0-src1">
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<bitset name="branch_any" extends="#instruction-cf-maybe-src0-src1">
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<pattern low="0" high="5">100100</pattern> <!-- OPC -->
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<pattern pos="80">0</pattern> <!-- OPCODE_BIT6 -->
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</bitset>
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