diff --git a/src/gallium/drivers/panfrost/pan_assemble.c b/src/gallium/drivers/panfrost/pan_assemble.c
index 494976d04d8..05b96fbd108 100644
--- a/src/gallium/drivers/panfrost/pan_assemble.c
+++ b/src/gallium/drivers/panfrost/pan_assemble.c
@@ -236,14 +236,17 @@ panfrost_shader_compile(struct panfrost_context *ctx,
 
         /* Call out to Midgard compiler given the above NIR */
         panfrost_program program = {0};
-        memcpy(program.rt_formats, state->rt_formats, sizeof(program.rt_formats));
+        struct panfrost_compile_inputs inputs = {
+                .gpu_id = dev->gpu_id,
+                .shaderdb = !!(dev->debug & PAN_DBG_PRECOMPILE),
+        };
 
-        if (dev->quirks & IS_BIFROST) {
-                bifrost_compile_shader_nir(s, &program, dev->gpu_id);
-        } else {
-                midgard_compile_shader_nir(s, &program, false, 0, dev->gpu_id,
-                                dev->debug & PAN_DBG_PRECOMPILE);
-        }
+        memcpy(inputs.rt_formats, state->rt_formats, sizeof(inputs.rt_formats));
+
+        if (dev->quirks & IS_BIFROST)
+                bifrost_compile_shader_nir(s, &program, &inputs);
+        else
+                midgard_compile_shader_nir(s, &program, &inputs);
 
         /* Prepare the compiled binary for upload */
         mali_ptr shader = 0;
diff --git a/src/gallium/drivers/panfrost/pan_blend_shaders.c b/src/gallium/drivers/panfrost/pan_blend_shaders.c
index 74aac4ebb38..8564fa0eaf9 100644
--- a/src/gallium/drivers/panfrost/pan_blend_shaders.c
+++ b/src/gallium/drivers/panfrost/pan_blend_shaders.c
@@ -213,11 +213,16 @@ panfrost_compile_blend_shader(
 
         /* Compile the built shader */
 
-        panfrost_program program = {
-           .rt_formats = {format}
+        panfrost_program program;
+
+        struct panfrost_compile_inputs inputs = {
+                .gpu_id = dev->gpu_id,
+                .is_blend = true,
+                .blend.rt = rt,
+                .rt_formats = {format},
         };
 
-        midgard_compile_shader_nir(shader, &program, true, rt, dev->gpu_id, false);
+        midgard_compile_shader_nir(shader, &program, &inputs);
 
         /* Allow us to patch later */
         res.patch_index = program.blend_patch_offset;
diff --git a/src/panfrost/bifrost/bifrost_compile.c b/src/panfrost/bifrost/bifrost_compile.c
index 6dda8811ab9..203dc566ed2 100644
--- a/src/panfrost/bifrost/bifrost_compile.c
+++ b/src/panfrost/bifrost/bifrost_compile.c
@@ -1321,14 +1321,15 @@ bi_optimize_nir(nir_shader *nir)
 }
 
 void
-bifrost_compile_shader_nir(nir_shader *nir, panfrost_program *program, unsigned product_id)
+bifrost_compile_shader_nir(nir_shader *nir, panfrost_program *program,
+                           const struct panfrost_compile_inputs *inputs)
 {
         bifrost_debug = debug_get_option_bifrost_debug();
 
         bi_context *ctx = rzalloc(NULL, bi_context);
         ctx->nir = nir;
         ctx->stage = nir->info.stage;
-        ctx->quirks = bifrost_get_quirks(product_id);
+        ctx->quirks = bifrost_get_quirks(inputs->gpu_id);
         list_inithead(&ctx->blocks);
 
         /* Lower gl_Position pre-optimisation, but after lowering vars to ssa
diff --git a/src/panfrost/bifrost/bifrost_compile.h b/src/panfrost/bifrost/bifrost_compile.h
index b4182f28860..e93d4713c9e 100644
--- a/src/panfrost/bifrost/bifrost_compile.h
+++ b/src/panfrost/bifrost/bifrost_compile.h
@@ -28,7 +28,8 @@
 #include "util/u_dynarray.h"
 #include "panfrost/util/pan_ir.h"
 
-void bifrost_compile_shader_nir(nir_shader *nir, panfrost_program *program, unsigned product_id);
+void bifrost_compile_shader_nir(nir_shader *nir, panfrost_program *program,
+                                const struct panfrost_compile_inputs *inputs);
 
 static const nir_shader_compiler_options bifrost_nir_options = {
         .lower_scmp = true,
diff --git a/src/panfrost/bifrost/cmdline.c b/src/panfrost/bifrost/cmdline.c
index 3668de5487d..a21f646491f 100644
--- a/src/panfrost/bifrost/cmdline.c
+++ b/src/panfrost/bifrost/cmdline.c
@@ -67,8 +67,11 @@ compile_shader(char **argv, bool vertex_only)
                 NIR_PASS_V(nir[i], gl_nir_lower_buffers, prog);
                 NIR_PASS_V(nir[i], nir_opt_constant_folding);
 
-                unsigned product_id = 0x7212; /* Mali G52 */
-                bifrost_compile_shader_nir(nir[i], &compiled, product_id);
+                struct panfrost_compile_inputs inputs = {
+                        .gpu_id = 0x7212, /* Mali G52 */
+                };
+
+                bifrost_compile_shader_nir(nir[i], &compiled, &inputs);
 
                 if (vertex_only)
                         return compiled;
diff --git a/src/panfrost/lib/pan_blit.c b/src/panfrost/lib/pan_blit.c
index 626e761d75c..4d74dd4345e 100644
--- a/src/panfrost/lib/pan_blit.c
+++ b/src/panfrost/lib/pan_blit.c
@@ -98,7 +98,11 @@ panfrost_build_blit_shader(panfrost_program *program, unsigned gpu_id, gl_frag_r
         else
                 nir_store_var(b, c_out, nir_channel(b, &tex->dest.ssa, 0), 0xFF);
 
-        midgard_compile_shader_nir(shader, program, false, 0, gpu_id, false);
+        struct panfrost_compile_inputs inputs = {
+                .gpu_id = gpu_id,
+        };
+
+        midgard_compile_shader_nir(shader, program, &inputs);
         ralloc_free(shader);
 }
 
diff --git a/src/panfrost/midgard/midgard_compile.c b/src/panfrost/midgard/midgard_compile.c
index c8d8961f405..d2c08471bc4 100644
--- a/src/panfrost/midgard/midgard_compile.c
+++ b/src/panfrost/midgard/midgard_compile.c
@@ -2949,7 +2949,8 @@ mir_add_writeout_loops(compiler_context *ctx)
 }
 
 int
-midgard_compile_shader_nir(nir_shader *nir, panfrost_program *program, bool is_blend, unsigned blend_rt, unsigned gpu_id, bool shaderdb)
+midgard_compile_shader_nir(nir_shader *nir, panfrost_program *program,
+                           const struct panfrost_compile_inputs *inputs)
 {
         struct util_dynarray *compiled = &program->compiled;
 
@@ -2960,11 +2961,11 @@ midgard_compile_shader_nir(nir_shader *nir, panfrost_program *program, bool is_b
 
         ctx->nir = nir;
         ctx->stage = nir->info.stage;
-        ctx->is_blend = is_blend;
-        ctx->blend_rt = MIDGARD_COLOR_RT0 + blend_rt;
+        ctx->is_blend = inputs->is_blend;
+        ctx->blend_rt = MIDGARD_COLOR_RT0 + inputs->blend.rt;
         ctx->blend_input = ~0;
         ctx->blend_src1 = ~0;
-        ctx->quirks = midgard_get_quirks(gpu_id);
+        ctx->quirks = midgard_get_quirks(inputs->gpu_id);
 
         /* Start off with a safe cutoff, allowing usage of all 16 work
          * registers. Later, we'll promote uniform reads to uniform registers
@@ -2994,9 +2995,9 @@ midgard_compile_shader_nir(nir_shader *nir, panfrost_program *program, bool is_b
         NIR_PASS_V(nir, nir_lower_var_copies);
         NIR_PASS_V(nir, nir_lower_vars_to_ssa);
 
-        unsigned pan_quirks = panfrost_get_quirks(gpu_id);
+        unsigned pan_quirks = panfrost_get_quirks(inputs->gpu_id);
         NIR_PASS_V(nir, pan_lower_framebuffer,
-                   program->rt_formats, is_blend, pan_quirks);
+                   inputs->rt_formats, inputs->is_blend, pan_quirks);
 
         NIR_PASS_V(nir, nir_lower_io, nir_var_shader_in | nir_var_shader_out,
                         glsl_type_size, 0);
@@ -3005,7 +3006,7 @@ midgard_compile_shader_nir(nir_shader *nir, panfrost_program *program, bool is_b
 
         /* Optimisation passes */
 
-        optimise_nir(nir, ctx->quirks, is_blend);
+        optimise_nir(nir, ctx->quirks, inputs->is_blend);
 
         NIR_PASS_V(nir, midgard_nir_reorder_writeout);
 
@@ -3029,7 +3030,7 @@ midgard_compile_shader_nir(nir_shader *nir, panfrost_program *program, bool is_b
                 ctx->func = func;
                 ctx->already_emitted = calloc(BITSET_WORDS(func->impl->ssa_alloc), sizeof(BITSET_WORD));
 
-                if (nir->info.outputs_read && !is_blend) {
+                if (nir->info.outputs_read && !inputs->is_blend) {
                         emit_block_init(ctx);
 
                         struct midgard_instruction wait = v_branch(false, false);
@@ -3143,10 +3144,15 @@ midgard_compile_shader_nir(nir_shader *nir, panfrost_program *program, bool is_b
         program->blend_patch_offset = ctx->blend_constant_offset;
         program->tls_size = ctx->tls_size;
 
-        if ((midgard_debug & MIDGARD_DBG_SHADERS) && !nir->info.internal)
-                disassemble_midgard(stdout, program->compiled.data, program->compiled.size, gpu_id, ctx->stage);
+        if ((midgard_debug & MIDGARD_DBG_SHADERS) && !nir->info.internal) {
+                disassemble_midgard(stdout,
+                                    program->compiled.data,
+                                    program->compiled.size,
+                                    inputs->gpu_id, ctx->stage);
+        }
 
-        if ((midgard_debug & MIDGARD_DBG_SHADERDB || shaderdb) && !nir->info.internal) {
+        if ((midgard_debug & MIDGARD_DBG_SHADERDB || inputs->shaderdb) &&
+            !nir->info.internal) {
                 unsigned nr_bundles = 0, nr_ins = 0;
 
                 /* Count instructions and bundles */
diff --git a/src/panfrost/midgard/midgard_compile.h b/src/panfrost/midgard/midgard_compile.h
index ffdfb90598c..93ac3a825db 100644
--- a/src/panfrost/midgard/midgard_compile.h
+++ b/src/panfrost/midgard/midgard_compile.h
@@ -29,7 +29,8 @@
 #include "panfrost/util/pan_ir.h"
 
 int
-midgard_compile_shader_nir(nir_shader *nir, panfrost_program *program, bool is_blend, unsigned blend_rt, unsigned gpu_id, bool shaderdb);
+midgard_compile_shader_nir(nir_shader *nir, panfrost_program *program,
+                           const struct panfrost_compile_inputs *inputs);
 
 /* NIR options are shared between the standalone compiler and the online
  * compiler. Defining it here is the simplest, though maybe not the Right
diff --git a/src/panfrost/util/pan_ir.h b/src/panfrost/util/pan_ir.h
index 80e1a877677..955e94f255c 100644
--- a/src/panfrost/util/pan_ir.h
+++ b/src/panfrost/util/pan_ir.h
@@ -107,10 +107,19 @@ typedef struct {
          * (register spilling), or zero if no spilling is used */
         unsigned tls_size;
 
-        /* IN: Render target formats for output load/store lowering */
-        enum pipe_format rt_formats[8];
 } panfrost_program;
 
+struct panfrost_compile_inputs {
+        unsigned gpu_id;
+        bool is_blend;
+        struct {
+                unsigned rt;
+        } blend;
+        bool shaderdb;
+
+        enum pipe_format rt_formats[8];
+};
+
 typedef struct pan_block {
         /* Link to next block. Must be first for mir_get_block */
         struct list_head link;