diff --git a/src/broadcom/compiler/v3d_compiler.h b/src/broadcom/compiler/v3d_compiler.h
index 9770043298f..a041eeeb31e 100644
--- a/src/broadcom/compiler/v3d_compiler.h
+++ b/src/broadcom/compiler/v3d_compiler.h
@@ -1488,6 +1488,11 @@ VIR_M_ALU1(FTOSNORM16)
 VIR_M_ALU1(VFTOUNORM8)
 VIR_M_ALU1(VFTOSNORM8)
 
+VIR_M_ALU1(FUNPACKUNORMLO)
+VIR_M_ALU1(FUNPACKUNORMHI)
+VIR_M_ALU1(FUNPACKSNORMLO)
+VIR_M_ALU1(FUNPACKSNORMHI)
+
 VIR_M_ALU1(VFTOUNORM10LO)
 VIR_M_ALU1(VFTOUNORM10HI)
 
diff --git a/src/broadcom/qpu/qpu_instr.c b/src/broadcom/qpu/qpu_instr.c
index 0a21a169095..36b0a063404 100644
--- a/src/broadcom/qpu/qpu_instr.c
+++ b/src/broadcom/qpu/qpu_instr.c
@@ -216,6 +216,10 @@ v3d_qpu_mul_op_name(enum v3d_qpu_mul_op op)
                 [V3D_QPU_M_FTOSNORM16] = "ftosnorm16",
                 [V3D_QPU_M_VFTOUNORM8] = "vftounorm8",
                 [V3D_QPU_M_VFTOSNORM8] = "vftosnorm8",
+                [V3D_QPU_M_FUNPACKUNORMLO] = "funpackunormlo",
+                [V3D_QPU_M_FUNPACKUNORMHI] = "funpackunormhi",
+                [V3D_QPU_M_FUNPACKSNORMLO] = "funpacksnormlo",
+                [V3D_QPU_M_FUNPACKSNORMHI] = "funpacksnormhi",
                 [V3D_QPU_M_VFTOUNORM10LO] = "vftounorm10lo",
                 [V3D_QPU_M_VFTOUNORM10HI] = "vftounorm10hi",
         };
@@ -515,6 +519,10 @@ static const uint8_t mul_op_args[] = {
         [V3D_QPU_M_FTOSNORM16] = D | A,
         [V3D_QPU_M_VFTOUNORM8] = D | A,
         [V3D_QPU_M_VFTOSNORM8] = D | A,
+        [V3D_QPU_M_FUNPACKUNORMLO] = D | A,
+        [V3D_QPU_M_FUNPACKUNORMHI] = D | A,
+        [V3D_QPU_M_FUNPACKSNORMLO] = D | A,
+        [V3D_QPU_M_FUNPACKSNORMHI] = D | A,
         [V3D_QPU_M_VFTOUNORM10LO] = D | A,
         [V3D_QPU_M_VFTOUNORM10HI] = D | A,
 };
diff --git a/src/broadcom/qpu/qpu_instr.h b/src/broadcom/qpu/qpu_instr.h
index 9a05fc8b7dc..c7925aa0d2e 100644
--- a/src/broadcom/qpu/qpu_instr.h
+++ b/src/broadcom/qpu/qpu_instr.h
@@ -261,6 +261,10 @@ enum v3d_qpu_mul_op {
         V3D_QPU_M_FTOSNORM16,
         V3D_QPU_M_VFTOUNORM8,
         V3D_QPU_M_VFTOSNORM8,
+        V3D_QPU_M_FUNPACKUNORMLO,
+        V3D_QPU_M_FUNPACKUNORMHI,
+        V3D_QPU_M_FUNPACKSNORMLO,
+        V3D_QPU_M_FUNPACKSNORMHI,
         V3D_QPU_M_VFTOUNORM10LO,
         V3D_QPU_M_VFTOUNORM10HI,
 };
diff --git a/src/broadcom/qpu/qpu_pack.c b/src/broadcom/qpu/qpu_pack.c
index b3c633a03ec..e0a1dbf778b 100644
--- a/src/broadcom/qpu/qpu_pack.c
+++ b/src/broadcom/qpu/qpu_pack.c
@@ -773,6 +773,10 @@ static const struct opcode_desc v3d71_mul_ops[] = {
         { 14, 14, .raddr_mask = OP_MASK(33), V3D_QPU_M_FTOSNORM16, 71 },
         { 14, 14, .raddr_mask = OP_MASK(34), V3D_QPU_M_VFTOUNORM8, 71 },
         { 14, 14, .raddr_mask = OP_MASK(35), V3D_QPU_M_VFTOSNORM8, 71 },
+        { 14, 14, .raddr_mask = OP_MASK(36), V3D_QPU_M_FUNPACKUNORMLO, 71 },
+        { 14, 14, .raddr_mask = OP_MASK(37), V3D_QPU_M_FUNPACKUNORMHI, 71 },
+        { 14, 14, .raddr_mask = OP_MASK(38), V3D_QPU_M_FUNPACKSNORMLO, 71 },
+        { 14, 14, .raddr_mask = OP_MASK(39), V3D_QPU_M_FUNPACKSNORMHI, 71 },
         { 14, 14, .raddr_mask = OP_MASK(48), V3D_QPU_M_VFTOUNORM10LO, 71 },
         { 14, 14, .raddr_mask = OP_MASK(49), V3D_QPU_M_VFTOUNORM10HI, 71 },