From 0a376a672a71df5ef1cf51bf80ea9907e994a5e8 Mon Sep 17 00:00:00 2001 From: Kenneth Graunke Date: Mon, 4 Nov 2024 17:31:21 -0800 Subject: [PATCH] brw: Fix emit_a64_oword_block_header UNIFORM -> VGRF copies This was triggering an assertion in the fs_builder::MOV helper that the destination stride can't be 0 when dispatch_width > 1. What we want to do is copy the single 64-bit channel of data from the UNIFORM file to a VGRF. We can use a SIMD1 builder for that. Reviewed-by: Lionel Landwerlin Part-of: --- src/intel/compiler/brw_lower_logical_sends.cpp | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/src/intel/compiler/brw_lower_logical_sends.cpp b/src/intel/compiler/brw_lower_logical_sends.cpp index 39384d3d95d..33aff4e7fd8 100644 --- a/src/intel/compiler/brw_lower_logical_sends.cpp +++ b/src/intel/compiler/brw_lower_logical_sends.cpp @@ -1589,9 +1589,13 @@ emit_a64_oword_block_header(const fs_builder &bld, const brw_reg &addr) brw_reg expanded_addr = addr; if (addr.file == UNIFORM) { /* We can't do stride 1 with the UNIFORM file, it requires stride 0 */ - expanded_addr = ubld.vgrf(BRW_TYPE_UQ); - expanded_addr.stride = 0; - ubld.MOV(expanded_addr, retype(addr, BRW_TYPE_UQ)); + fs_builder ubld1 = ubld.group(1, 0); + + brw_reg tmp = ubld1.vgrf(BRW_TYPE_UQ); + ubld1.UNDEF(tmp); + + expanded_addr = component(tmp, 0); + ubld1.MOV(expanded_addr, retype(addr, BRW_TYPE_UQ)); } brw_reg header = ubld.vgrf(BRW_TYPE_UD);